1 /* 2 * ARM virtual CPU header 3 * 4 * Copyright (c) 2003 Fabrice Bellard 5 * 6 * This library is free software; you can redistribute it and/or 7 * modify it under the terms of the GNU Lesser General Public 8 * License as published by the Free Software Foundation; either 9 * version 2 of the License, or (at your option) any later version. 10 * 11 * This library is distributed in the hope that it will be useful, 12 * but WITHOUT ANY WARRANTY; without even the implied warranty of 13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU 14 * Lesser General Public License for more details. 15 * 16 * You should have received a copy of the GNU Lesser General Public 17 * License along with this library; if not, see <http://www.gnu.org/licenses/>. 18 */ 19 20 #ifndef ARM_CPU_H 21 #define ARM_CPU_H 22 23 #include "kvm-consts.h" 24 #include "hw/registerfields.h" 25 26 #if defined(TARGET_AARCH64) 27 /* AArch64 definitions */ 28 # define TARGET_LONG_BITS 64 29 #else 30 # define TARGET_LONG_BITS 32 31 #endif 32 33 /* ARM processors have a weak memory model */ 34 #define TCG_GUEST_DEFAULT_MO (0) 35 36 #define CPUArchState struct CPUARMState 37 38 #include "qemu-common.h" 39 #include "cpu-qom.h" 40 #include "exec/cpu-defs.h" 41 42 #define EXCP_UDEF 1 /* undefined instruction */ 43 #define EXCP_SWI 2 /* software interrupt */ 44 #define EXCP_PREFETCH_ABORT 3 45 #define EXCP_DATA_ABORT 4 46 #define EXCP_IRQ 5 47 #define EXCP_FIQ 6 48 #define EXCP_BKPT 7 49 #define EXCP_EXCEPTION_EXIT 8 /* Return from v7M exception. */ 50 #define EXCP_KERNEL_TRAP 9 /* Jumped to kernel code page. */ 51 #define EXCP_HVC 11 /* HyperVisor Call */ 52 #define EXCP_HYP_TRAP 12 53 #define EXCP_SMC 13 /* Secure Monitor Call */ 54 #define EXCP_VIRQ 14 55 #define EXCP_VFIQ 15 56 #define EXCP_SEMIHOST 16 /* semihosting call */ 57 #define EXCP_NOCP 17 /* v7M NOCP UsageFault */ 58 #define EXCP_INVSTATE 18 /* v7M INVSTATE UsageFault */ 59 #define EXCP_STKOF 19 /* v8M STKOF UsageFault */ 60 /* NB: add new EXCP_ defines to the array in arm_log_exception() too */ 61 62 #define ARMV7M_EXCP_RESET 1 63 #define ARMV7M_EXCP_NMI 2 64 #define ARMV7M_EXCP_HARD 3 65 #define ARMV7M_EXCP_MEM 4 66 #define ARMV7M_EXCP_BUS 5 67 #define ARMV7M_EXCP_USAGE 6 68 #define ARMV7M_EXCP_SECURE 7 69 #define ARMV7M_EXCP_SVC 11 70 #define ARMV7M_EXCP_DEBUG 12 71 #define ARMV7M_EXCP_PENDSV 14 72 #define ARMV7M_EXCP_SYSTICK 15 73 74 /* For M profile, some registers are banked secure vs non-secure; 75 * these are represented as a 2-element array where the first element 76 * is the non-secure copy and the second is the secure copy. 77 * When the CPU does not have implement the security extension then 78 * only the first element is used. 79 * This means that the copy for the current security state can be 80 * accessed via env->registerfield[env->v7m.secure] (whether the security 81 * extension is implemented or not). 82 */ 83 enum { 84 M_REG_NS = 0, 85 M_REG_S = 1, 86 M_REG_NUM_BANKS = 2, 87 }; 88 89 /* ARM-specific interrupt pending bits. */ 90 #define CPU_INTERRUPT_FIQ CPU_INTERRUPT_TGT_EXT_1 91 #define CPU_INTERRUPT_VIRQ CPU_INTERRUPT_TGT_EXT_2 92 #define CPU_INTERRUPT_VFIQ CPU_INTERRUPT_TGT_EXT_3 93 94 /* The usual mapping for an AArch64 system register to its AArch32 95 * counterpart is for the 32 bit world to have access to the lower 96 * half only (with writes leaving the upper half untouched). It's 97 * therefore useful to be able to pass TCG the offset of the least 98 * significant half of a uint64_t struct member. 99 */ 100 #ifdef HOST_WORDS_BIGENDIAN 101 #define offsetoflow32(S, M) (offsetof(S, M) + sizeof(uint32_t)) 102 #define offsetofhigh32(S, M) offsetof(S, M) 103 #else 104 #define offsetoflow32(S, M) offsetof(S, M) 105 #define offsetofhigh32(S, M) (offsetof(S, M) + sizeof(uint32_t)) 106 #endif 107 108 /* Meanings of the ARMCPU object's four inbound GPIO lines */ 109 #define ARM_CPU_IRQ 0 110 #define ARM_CPU_FIQ 1 111 #define ARM_CPU_VIRQ 2 112 #define ARM_CPU_VFIQ 3 113 114 #define NB_MMU_MODES 8 115 /* ARM-specific extra insn start words: 116 * 1: Conditional execution bits 117 * 2: Partial exception syndrome for data aborts 118 */ 119 #define TARGET_INSN_START_EXTRA_WORDS 2 120 121 /* The 2nd extra word holding syndrome info for data aborts does not use 122 * the upper 6 bits nor the lower 14 bits. We mask and shift it down to 123 * help the sleb128 encoder do a better job. 124 * When restoring the CPU state, we shift it back up. 125 */ 126 #define ARM_INSN_START_WORD2_MASK ((1 << 26) - 1) 127 #define ARM_INSN_START_WORD2_SHIFT 14 128 129 /* We currently assume float and double are IEEE single and double 130 precision respectively. 131 Doing runtime conversions is tricky because VFP registers may contain 132 integer values (eg. as the result of a FTOSI instruction). 133 s<2n> maps to the least significant half of d<n> 134 s<2n+1> maps to the most significant half of d<n> 135 */ 136 137 /** 138 * DynamicGDBXMLInfo: 139 * @desc: Contains the XML descriptions. 140 * @num_cpregs: Number of the Coprocessor registers seen by GDB. 141 * @cpregs_keys: Array that contains the corresponding Key of 142 * a given cpreg with the same order of the cpreg in the XML description. 143 */ 144 typedef struct DynamicGDBXMLInfo { 145 char *desc; 146 int num_cpregs; 147 uint32_t *cpregs_keys; 148 } DynamicGDBXMLInfo; 149 150 /* CPU state for each instance of a generic timer (in cp15 c14) */ 151 typedef struct ARMGenericTimer { 152 uint64_t cval; /* Timer CompareValue register */ 153 uint64_t ctl; /* Timer Control register */ 154 } ARMGenericTimer; 155 156 #define GTIMER_PHYS 0 157 #define GTIMER_VIRT 1 158 #define GTIMER_HYP 2 159 #define GTIMER_SEC 3 160 #define NUM_GTIMERS 4 161 162 typedef struct { 163 uint64_t raw_tcr; 164 uint32_t mask; 165 uint32_t base_mask; 166 } TCR; 167 168 /* Define a maximum sized vector register. 169 * For 32-bit, this is a 128-bit NEON/AdvSIMD register. 170 * For 64-bit, this is a 2048-bit SVE register. 171 * 172 * Note that the mapping between S, D, and Q views of the register bank 173 * differs between AArch64 and AArch32. 174 * In AArch32: 175 * Qn = regs[n].d[1]:regs[n].d[0] 176 * Dn = regs[n / 2].d[n & 1] 177 * Sn = regs[n / 4].d[n % 4 / 2], 178 * bits 31..0 for even n, and bits 63..32 for odd n 179 * (and regs[16] to regs[31] are inaccessible) 180 * In AArch64: 181 * Zn = regs[n].d[*] 182 * Qn = regs[n].d[1]:regs[n].d[0] 183 * Dn = regs[n].d[0] 184 * Sn = regs[n].d[0] bits 31..0 185 * Hn = regs[n].d[0] bits 15..0 186 * 187 * This corresponds to the architecturally defined mapping between 188 * the two execution states, and means we do not need to explicitly 189 * map these registers when changing states. 190 * 191 * Align the data for use with TCG host vector operations. 192 */ 193 194 #ifdef TARGET_AARCH64 195 # define ARM_MAX_VQ 16 196 #else 197 # define ARM_MAX_VQ 1 198 #endif 199 200 typedef struct ARMVectorReg { 201 uint64_t d[2 * ARM_MAX_VQ] QEMU_ALIGNED(16); 202 } ARMVectorReg; 203 204 #ifdef TARGET_AARCH64 205 /* In AArch32 mode, predicate registers do not exist at all. */ 206 typedef struct ARMPredicateReg { 207 uint64_t p[2 * ARM_MAX_VQ / 8] QEMU_ALIGNED(16); 208 } ARMPredicateReg; 209 210 /* In AArch32 mode, PAC keys do not exist at all. */ 211 typedef struct ARMPACKey { 212 uint64_t lo, hi; 213 } ARMPACKey; 214 #endif 215 216 217 typedef struct CPUARMState { 218 /* Regs for current mode. */ 219 uint32_t regs[16]; 220 221 /* 32/64 switch only happens when taking and returning from 222 * exceptions so the overlap semantics are taken care of then 223 * instead of having a complicated union. 224 */ 225 /* Regs for A64 mode. */ 226 uint64_t xregs[32]; 227 uint64_t pc; 228 /* PSTATE isn't an architectural register for ARMv8. However, it is 229 * convenient for us to assemble the underlying state into a 32 bit format 230 * identical to the architectural format used for the SPSR. (This is also 231 * what the Linux kernel's 'pstate' field in signal handlers and KVM's 232 * 'pstate' register are.) Of the PSTATE bits: 233 * NZCV are kept in the split out env->CF/VF/NF/ZF, (which have the same 234 * semantics as for AArch32, as described in the comments on each field) 235 * nRW (also known as M[4]) is kept, inverted, in env->aarch64 236 * DAIF (exception masks) are kept in env->daif 237 * BTYPE is kept in env->btype 238 * all other bits are stored in their correct places in env->pstate 239 */ 240 uint32_t pstate; 241 uint32_t aarch64; /* 1 if CPU is in aarch64 state; inverse of PSTATE.nRW */ 242 243 /* Frequently accessed CPSR bits are stored separately for efficiency. 244 This contains all the other bits. Use cpsr_{read,write} to access 245 the whole CPSR. */ 246 uint32_t uncached_cpsr; 247 uint32_t spsr; 248 249 /* Banked registers. */ 250 uint64_t banked_spsr[8]; 251 uint32_t banked_r13[8]; 252 uint32_t banked_r14[8]; 253 254 /* These hold r8-r12. */ 255 uint32_t usr_regs[5]; 256 uint32_t fiq_regs[5]; 257 258 /* cpsr flag cache for faster execution */ 259 uint32_t CF; /* 0 or 1 */ 260 uint32_t VF; /* V is the bit 31. All other bits are undefined */ 261 uint32_t NF; /* N is bit 31. All other bits are undefined. */ 262 uint32_t ZF; /* Z set if zero. */ 263 uint32_t QF; /* 0 or 1 */ 264 uint32_t GE; /* cpsr[19:16] */ 265 uint32_t thumb; /* cpsr[5]. 0 = arm mode, 1 = thumb mode. */ 266 uint32_t condexec_bits; /* IT bits. cpsr[15:10,26:25]. */ 267 uint32_t btype; /* BTI branch type. spsr[11:10]. */ 268 uint64_t daif; /* exception masks, in the bits they are in PSTATE */ 269 270 uint64_t elr_el[4]; /* AArch64 exception link regs */ 271 uint64_t sp_el[4]; /* AArch64 banked stack pointers */ 272 273 /* System control coprocessor (cp15) */ 274 struct { 275 uint32_t c0_cpuid; 276 union { /* Cache size selection */ 277 struct { 278 uint64_t _unused_csselr0; 279 uint64_t csselr_ns; 280 uint64_t _unused_csselr1; 281 uint64_t csselr_s; 282 }; 283 uint64_t csselr_el[4]; 284 }; 285 union { /* System control register. */ 286 struct { 287 uint64_t _unused_sctlr; 288 uint64_t sctlr_ns; 289 uint64_t hsctlr; 290 uint64_t sctlr_s; 291 }; 292 uint64_t sctlr_el[4]; 293 }; 294 uint64_t cpacr_el1; /* Architectural feature access control register */ 295 uint64_t cptr_el[4]; /* ARMv8 feature trap registers */ 296 uint32_t c1_xscaleauxcr; /* XScale auxiliary control register. */ 297 uint64_t sder; /* Secure debug enable register. */ 298 uint32_t nsacr; /* Non-secure access control register. */ 299 union { /* MMU translation table base 0. */ 300 struct { 301 uint64_t _unused_ttbr0_0; 302 uint64_t ttbr0_ns; 303 uint64_t _unused_ttbr0_1; 304 uint64_t ttbr0_s; 305 }; 306 uint64_t ttbr0_el[4]; 307 }; 308 union { /* MMU translation table base 1. */ 309 struct { 310 uint64_t _unused_ttbr1_0; 311 uint64_t ttbr1_ns; 312 uint64_t _unused_ttbr1_1; 313 uint64_t ttbr1_s; 314 }; 315 uint64_t ttbr1_el[4]; 316 }; 317 uint64_t vttbr_el2; /* Virtualization Translation Table Base. */ 318 /* MMU translation table base control. */ 319 TCR tcr_el[4]; 320 TCR vtcr_el2; /* Virtualization Translation Control. */ 321 uint32_t c2_data; /* MPU data cacheable bits. */ 322 uint32_t c2_insn; /* MPU instruction cacheable bits. */ 323 union { /* MMU domain access control register 324 * MPU write buffer control. 325 */ 326 struct { 327 uint64_t dacr_ns; 328 uint64_t dacr_s; 329 }; 330 struct { 331 uint64_t dacr32_el2; 332 }; 333 }; 334 uint32_t pmsav5_data_ap; /* PMSAv5 MPU data access permissions */ 335 uint32_t pmsav5_insn_ap; /* PMSAv5 MPU insn access permissions */ 336 uint64_t hcr_el2; /* Hypervisor configuration register */ 337 uint64_t scr_el3; /* Secure configuration register. */ 338 union { /* Fault status registers. */ 339 struct { 340 uint64_t ifsr_ns; 341 uint64_t ifsr_s; 342 }; 343 struct { 344 uint64_t ifsr32_el2; 345 }; 346 }; 347 union { 348 struct { 349 uint64_t _unused_dfsr; 350 uint64_t dfsr_ns; 351 uint64_t hsr; 352 uint64_t dfsr_s; 353 }; 354 uint64_t esr_el[4]; 355 }; 356 uint32_t c6_region[8]; /* MPU base/size registers. */ 357 union { /* Fault address registers. */ 358 struct { 359 uint64_t _unused_far0; 360 #ifdef HOST_WORDS_BIGENDIAN 361 uint32_t ifar_ns; 362 uint32_t dfar_ns; 363 uint32_t ifar_s; 364 uint32_t dfar_s; 365 #else 366 uint32_t dfar_ns; 367 uint32_t ifar_ns; 368 uint32_t dfar_s; 369 uint32_t ifar_s; 370 #endif 371 uint64_t _unused_far3; 372 }; 373 uint64_t far_el[4]; 374 }; 375 uint64_t hpfar_el2; 376 uint64_t hstr_el2; 377 union { /* Translation result. */ 378 struct { 379 uint64_t _unused_par_0; 380 uint64_t par_ns; 381 uint64_t _unused_par_1; 382 uint64_t par_s; 383 }; 384 uint64_t par_el[4]; 385 }; 386 387 uint32_t c9_insn; /* Cache lockdown registers. */ 388 uint32_t c9_data; 389 uint64_t c9_pmcr; /* performance monitor control register */ 390 uint64_t c9_pmcnten; /* perf monitor counter enables */ 391 uint64_t c9_pmovsr; /* perf monitor overflow status */ 392 uint64_t c9_pmuserenr; /* perf monitor user enable */ 393 uint64_t c9_pmselr; /* perf monitor counter selection register */ 394 uint64_t c9_pminten; /* perf monitor interrupt enables */ 395 union { /* Memory attribute redirection */ 396 struct { 397 #ifdef HOST_WORDS_BIGENDIAN 398 uint64_t _unused_mair_0; 399 uint32_t mair1_ns; 400 uint32_t mair0_ns; 401 uint64_t _unused_mair_1; 402 uint32_t mair1_s; 403 uint32_t mair0_s; 404 #else 405 uint64_t _unused_mair_0; 406 uint32_t mair0_ns; 407 uint32_t mair1_ns; 408 uint64_t _unused_mair_1; 409 uint32_t mair0_s; 410 uint32_t mair1_s; 411 #endif 412 }; 413 uint64_t mair_el[4]; 414 }; 415 union { /* vector base address register */ 416 struct { 417 uint64_t _unused_vbar; 418 uint64_t vbar_ns; 419 uint64_t hvbar; 420 uint64_t vbar_s; 421 }; 422 uint64_t vbar_el[4]; 423 }; 424 uint32_t mvbar; /* (monitor) vector base address register */ 425 struct { /* FCSE PID. */ 426 uint32_t fcseidr_ns; 427 uint32_t fcseidr_s; 428 }; 429 union { /* Context ID. */ 430 struct { 431 uint64_t _unused_contextidr_0; 432 uint64_t contextidr_ns; 433 uint64_t _unused_contextidr_1; 434 uint64_t contextidr_s; 435 }; 436 uint64_t contextidr_el[4]; 437 }; 438 union { /* User RW Thread register. */ 439 struct { 440 uint64_t tpidrurw_ns; 441 uint64_t tpidrprw_ns; 442 uint64_t htpidr; 443 uint64_t _tpidr_el3; 444 }; 445 uint64_t tpidr_el[4]; 446 }; 447 /* The secure banks of these registers don't map anywhere */ 448 uint64_t tpidrurw_s; 449 uint64_t tpidrprw_s; 450 uint64_t tpidruro_s; 451 452 union { /* User RO Thread register. */ 453 uint64_t tpidruro_ns; 454 uint64_t tpidrro_el[1]; 455 }; 456 uint64_t c14_cntfrq; /* Counter Frequency register */ 457 uint64_t c14_cntkctl; /* Timer Control register */ 458 uint32_t cnthctl_el2; /* Counter/Timer Hyp Control register */ 459 uint64_t cntvoff_el2; /* Counter Virtual Offset register */ 460 ARMGenericTimer c14_timer[NUM_GTIMERS]; 461 uint32_t c15_cpar; /* XScale Coprocessor Access Register */ 462 uint32_t c15_ticonfig; /* TI925T configuration byte. */ 463 uint32_t c15_i_max; /* Maximum D-cache dirty line index. */ 464 uint32_t c15_i_min; /* Minimum D-cache dirty line index. */ 465 uint32_t c15_threadid; /* TI debugger thread-ID. */ 466 uint32_t c15_config_base_address; /* SCU base address. */ 467 uint32_t c15_diagnostic; /* diagnostic register */ 468 uint32_t c15_power_diagnostic; 469 uint32_t c15_power_control; /* power control */ 470 uint64_t dbgbvr[16]; /* breakpoint value registers */ 471 uint64_t dbgbcr[16]; /* breakpoint control registers */ 472 uint64_t dbgwvr[16]; /* watchpoint value registers */ 473 uint64_t dbgwcr[16]; /* watchpoint control registers */ 474 uint64_t mdscr_el1; 475 uint64_t oslsr_el1; /* OS Lock Status */ 476 uint64_t mdcr_el2; 477 uint64_t mdcr_el3; 478 /* Stores the architectural value of the counter *the last time it was 479 * updated* by pmccntr_op_start. Accesses should always be surrounded 480 * by pmccntr_op_start/pmccntr_op_finish to guarantee the latest 481 * architecturally-correct value is being read/set. 482 */ 483 uint64_t c15_ccnt; 484 /* Stores the delta between the architectural value and the underlying 485 * cycle count during normal operation. It is used to update c15_ccnt 486 * to be the correct architectural value before accesses. During 487 * accesses, c15_ccnt_delta contains the underlying count being used 488 * for the access, after which it reverts to the delta value in 489 * pmccntr_op_finish. 490 */ 491 uint64_t c15_ccnt_delta; 492 uint64_t c14_pmevcntr[31]; 493 uint64_t c14_pmevcntr_delta[31]; 494 uint64_t c14_pmevtyper[31]; 495 uint64_t pmccfiltr_el0; /* Performance Monitor Filter Register */ 496 uint64_t vpidr_el2; /* Virtualization Processor ID Register */ 497 uint64_t vmpidr_el2; /* Virtualization Multiprocessor ID Register */ 498 } cp15; 499 500 struct { 501 /* M profile has up to 4 stack pointers: 502 * a Main Stack Pointer and a Process Stack Pointer for each 503 * of the Secure and Non-Secure states. (If the CPU doesn't support 504 * the security extension then it has only two SPs.) 505 * In QEMU we always store the currently active SP in regs[13], 506 * and the non-active SP for the current security state in 507 * v7m.other_sp. The stack pointers for the inactive security state 508 * are stored in other_ss_msp and other_ss_psp. 509 * switch_v7m_security_state() is responsible for rearranging them 510 * when we change security state. 511 */ 512 uint32_t other_sp; 513 uint32_t other_ss_msp; 514 uint32_t other_ss_psp; 515 uint32_t vecbase[M_REG_NUM_BANKS]; 516 uint32_t basepri[M_REG_NUM_BANKS]; 517 uint32_t control[M_REG_NUM_BANKS]; 518 uint32_t ccr[M_REG_NUM_BANKS]; /* Configuration and Control */ 519 uint32_t cfsr[M_REG_NUM_BANKS]; /* Configurable Fault Status */ 520 uint32_t hfsr; /* HardFault Status */ 521 uint32_t dfsr; /* Debug Fault Status Register */ 522 uint32_t sfsr; /* Secure Fault Status Register */ 523 uint32_t mmfar[M_REG_NUM_BANKS]; /* MemManage Fault Address */ 524 uint32_t bfar; /* BusFault Address */ 525 uint32_t sfar; /* Secure Fault Address Register */ 526 unsigned mpu_ctrl[M_REG_NUM_BANKS]; /* MPU_CTRL */ 527 int exception; 528 uint32_t primask[M_REG_NUM_BANKS]; 529 uint32_t faultmask[M_REG_NUM_BANKS]; 530 uint32_t aircr; /* only holds r/w state if security extn implemented */ 531 uint32_t secure; /* Is CPU in Secure state? (not guest visible) */ 532 uint32_t csselr[M_REG_NUM_BANKS]; 533 uint32_t scr[M_REG_NUM_BANKS]; 534 uint32_t msplim[M_REG_NUM_BANKS]; 535 uint32_t psplim[M_REG_NUM_BANKS]; 536 } v7m; 537 538 /* Information associated with an exception about to be taken: 539 * code which raises an exception must set cs->exception_index and 540 * the relevant parts of this structure; the cpu_do_interrupt function 541 * will then set the guest-visible registers as part of the exception 542 * entry process. 543 */ 544 struct { 545 uint32_t syndrome; /* AArch64 format syndrome register */ 546 uint32_t fsr; /* AArch32 format fault status register info */ 547 uint64_t vaddress; /* virtual addr associated with exception, if any */ 548 uint32_t target_el; /* EL the exception should be targeted for */ 549 /* If we implement EL2 we will also need to store information 550 * about the intermediate physical address for stage 2 faults. 551 */ 552 } exception; 553 554 /* Information associated with an SError */ 555 struct { 556 uint8_t pending; 557 uint8_t has_esr; 558 uint64_t esr; 559 } serror; 560 561 /* State of our input IRQ/FIQ/VIRQ/VFIQ lines */ 562 uint32_t irq_line_state; 563 564 /* Thumb-2 EE state. */ 565 uint32_t teecr; 566 uint32_t teehbr; 567 568 /* VFP coprocessor state. */ 569 struct { 570 ARMVectorReg zregs[32]; 571 572 #ifdef TARGET_AARCH64 573 /* Store FFR as pregs[16] to make it easier to treat as any other. */ 574 #define FFR_PRED_NUM 16 575 ARMPredicateReg pregs[17]; 576 /* Scratch space for aa64 sve predicate temporary. */ 577 ARMPredicateReg preg_tmp; 578 #endif 579 580 /* We store these fpcsr fields separately for convenience. */ 581 uint32_t qc[4] QEMU_ALIGNED(16); 582 int vec_len; 583 int vec_stride; 584 585 uint32_t xregs[16]; 586 587 /* Scratch space for aa32 neon expansion. */ 588 uint32_t scratch[8]; 589 590 /* There are a number of distinct float control structures: 591 * 592 * fp_status: is the "normal" fp status. 593 * fp_status_fp16: used for half-precision calculations 594 * standard_fp_status : the ARM "Standard FPSCR Value" 595 * 596 * Half-precision operations are governed by a separate 597 * flush-to-zero control bit in FPSCR:FZ16. We pass a separate 598 * status structure to control this. 599 * 600 * The "Standard FPSCR", ie default-NaN, flush-to-zero, 601 * round-to-nearest and is used by any operations (generally 602 * Neon) which the architecture defines as controlled by the 603 * standard FPSCR value rather than the FPSCR. 604 * 605 * To avoid having to transfer exception bits around, we simply 606 * say that the FPSCR cumulative exception flags are the logical 607 * OR of the flags in the three fp statuses. This relies on the 608 * only thing which needs to read the exception flags being 609 * an explicit FPSCR read. 610 */ 611 float_status fp_status; 612 float_status fp_status_f16; 613 float_status standard_fp_status; 614 615 /* ZCR_EL[1-3] */ 616 uint64_t zcr_el[4]; 617 } vfp; 618 uint64_t exclusive_addr; 619 uint64_t exclusive_val; 620 uint64_t exclusive_high; 621 622 /* iwMMXt coprocessor state. */ 623 struct { 624 uint64_t regs[16]; 625 uint64_t val; 626 627 uint32_t cregs[16]; 628 } iwmmxt; 629 630 #ifdef TARGET_AARCH64 631 ARMPACKey apia_key; 632 ARMPACKey apib_key; 633 ARMPACKey apda_key; 634 ARMPACKey apdb_key; 635 ARMPACKey apga_key; 636 #endif 637 638 #if defined(CONFIG_USER_ONLY) 639 /* For usermode syscall translation. */ 640 int eabi; 641 #endif 642 643 struct CPUBreakpoint *cpu_breakpoint[16]; 644 struct CPUWatchpoint *cpu_watchpoint[16]; 645 646 /* Fields up to this point are cleared by a CPU reset */ 647 struct {} end_reset_fields; 648 649 CPU_COMMON 650 651 /* Fields after CPU_COMMON are preserved across CPU reset. */ 652 653 /* Internal CPU feature flags. */ 654 uint64_t features; 655 656 /* PMSAv7 MPU */ 657 struct { 658 uint32_t *drbar; 659 uint32_t *drsr; 660 uint32_t *dracr; 661 uint32_t rnr[M_REG_NUM_BANKS]; 662 } pmsav7; 663 664 /* PMSAv8 MPU */ 665 struct { 666 /* The PMSAv8 implementation also shares some PMSAv7 config 667 * and state: 668 * pmsav7.rnr (region number register) 669 * pmsav7_dregion (number of configured regions) 670 */ 671 uint32_t *rbar[M_REG_NUM_BANKS]; 672 uint32_t *rlar[M_REG_NUM_BANKS]; 673 uint32_t mair0[M_REG_NUM_BANKS]; 674 uint32_t mair1[M_REG_NUM_BANKS]; 675 } pmsav8; 676 677 /* v8M SAU */ 678 struct { 679 uint32_t *rbar; 680 uint32_t *rlar; 681 uint32_t rnr; 682 uint32_t ctrl; 683 } sau; 684 685 void *nvic; 686 const struct arm_boot_info *boot_info; 687 /* Store GICv3CPUState to access from this struct */ 688 void *gicv3state; 689 } CPUARMState; 690 691 /** 692 * ARMELChangeHookFn: 693 * type of a function which can be registered via arm_register_el_change_hook() 694 * to get callbacks when the CPU changes its exception level or mode. 695 */ 696 typedef void ARMELChangeHookFn(ARMCPU *cpu, void *opaque); 697 typedef struct ARMELChangeHook ARMELChangeHook; 698 struct ARMELChangeHook { 699 ARMELChangeHookFn *hook; 700 void *opaque; 701 QLIST_ENTRY(ARMELChangeHook) node; 702 }; 703 704 /* These values map onto the return values for 705 * QEMU_PSCI_0_2_FN_AFFINITY_INFO */ 706 typedef enum ARMPSCIState { 707 PSCI_ON = 0, 708 PSCI_OFF = 1, 709 PSCI_ON_PENDING = 2 710 } ARMPSCIState; 711 712 typedef struct ARMISARegisters ARMISARegisters; 713 714 /** 715 * ARMCPU: 716 * @env: #CPUARMState 717 * 718 * An ARM CPU core. 719 */ 720 struct ARMCPU { 721 /*< private >*/ 722 CPUState parent_obj; 723 /*< public >*/ 724 725 CPUARMState env; 726 727 /* Coprocessor information */ 728 GHashTable *cp_regs; 729 /* For marshalling (mostly coprocessor) register state between the 730 * kernel and QEMU (for KVM) and between two QEMUs (for migration), 731 * we use these arrays. 732 */ 733 /* List of register indexes managed via these arrays; (full KVM style 734 * 64 bit indexes, not CPRegInfo 32 bit indexes) 735 */ 736 uint64_t *cpreg_indexes; 737 /* Values of the registers (cpreg_indexes[i]'s value is cpreg_values[i]) */ 738 uint64_t *cpreg_values; 739 /* Length of the indexes, values, reset_values arrays */ 740 int32_t cpreg_array_len; 741 /* These are used only for migration: incoming data arrives in 742 * these fields and is sanity checked in post_load before copying 743 * to the working data structures above. 744 */ 745 uint64_t *cpreg_vmstate_indexes; 746 uint64_t *cpreg_vmstate_values; 747 int32_t cpreg_vmstate_array_len; 748 749 DynamicGDBXMLInfo dyn_xml; 750 751 /* Timers used by the generic (architected) timer */ 752 QEMUTimer *gt_timer[NUM_GTIMERS]; 753 /* 754 * Timer used by the PMU. Its state is restored after migration by 755 * pmu_op_finish() - it does not need other handling during migration 756 */ 757 QEMUTimer *pmu_timer; 758 /* GPIO outputs for generic timer */ 759 qemu_irq gt_timer_outputs[NUM_GTIMERS]; 760 /* GPIO output for GICv3 maintenance interrupt signal */ 761 qemu_irq gicv3_maintenance_interrupt; 762 /* GPIO output for the PMU interrupt */ 763 qemu_irq pmu_interrupt; 764 765 /* MemoryRegion to use for secure physical accesses */ 766 MemoryRegion *secure_memory; 767 768 /* For v8M, pointer to the IDAU interface provided by board/SoC */ 769 Object *idau; 770 771 /* 'compatible' string for this CPU for Linux device trees */ 772 const char *dtb_compatible; 773 774 /* PSCI version for this CPU 775 * Bits[31:16] = Major Version 776 * Bits[15:0] = Minor Version 777 */ 778 uint32_t psci_version; 779 780 /* Should CPU start in PSCI powered-off state? */ 781 bool start_powered_off; 782 783 /* Current power state, access guarded by BQL */ 784 ARMPSCIState power_state; 785 786 /* CPU has virtualization extension */ 787 bool has_el2; 788 /* CPU has security extension */ 789 bool has_el3; 790 /* CPU has PMU (Performance Monitor Unit) */ 791 bool has_pmu; 792 793 /* CPU has memory protection unit */ 794 bool has_mpu; 795 /* PMSAv7 MPU number of supported regions */ 796 uint32_t pmsav7_dregion; 797 /* v8M SAU number of supported regions */ 798 uint32_t sau_sregion; 799 800 /* PSCI conduit used to invoke PSCI methods 801 * 0 - disabled, 1 - smc, 2 - hvc 802 */ 803 uint32_t psci_conduit; 804 805 /* For v8M, initial value of the Secure VTOR */ 806 uint32_t init_svtor; 807 808 /* [QEMU_]KVM_ARM_TARGET_* constant for this CPU, or 809 * QEMU_KVM_ARM_TARGET_NONE if the kernel doesn't support this CPU type. 810 */ 811 uint32_t kvm_target; 812 813 /* KVM init features for this CPU */ 814 uint32_t kvm_init_features[7]; 815 816 /* Uniprocessor system with MP extensions */ 817 bool mp_is_up; 818 819 /* True if we tried kvm_arm_host_cpu_features() during CPU instance_init 820 * and the probe failed (so we need to report the error in realize) 821 */ 822 bool host_cpu_probe_failed; 823 824 /* Specify the number of cores in this CPU cluster. Used for the L2CTLR 825 * register. 826 */ 827 int32_t core_count; 828 829 /* The instance init functions for implementation-specific subclasses 830 * set these fields to specify the implementation-dependent values of 831 * various constant registers and reset values of non-constant 832 * registers. 833 * Some of these might become QOM properties eventually. 834 * Field names match the official register names as defined in the 835 * ARMv7AR ARM Architecture Reference Manual. A reset_ prefix 836 * is used for reset values of non-constant registers; no reset_ 837 * prefix means a constant register. 838 * Some of these registers are split out into a substructure that 839 * is shared with the translators to control the ISA. 840 */ 841 struct ARMISARegisters { 842 uint32_t id_isar0; 843 uint32_t id_isar1; 844 uint32_t id_isar2; 845 uint32_t id_isar3; 846 uint32_t id_isar4; 847 uint32_t id_isar5; 848 uint32_t id_isar6; 849 uint32_t mvfr0; 850 uint32_t mvfr1; 851 uint32_t mvfr2; 852 uint64_t id_aa64isar0; 853 uint64_t id_aa64isar1; 854 uint64_t id_aa64pfr0; 855 uint64_t id_aa64pfr1; 856 uint64_t id_aa64mmfr0; 857 uint64_t id_aa64mmfr1; 858 } isar; 859 uint32_t midr; 860 uint32_t revidr; 861 uint32_t reset_fpsid; 862 uint32_t ctr; 863 uint32_t reset_sctlr; 864 uint32_t id_pfr0; 865 uint32_t id_pfr1; 866 uint32_t id_dfr0; 867 uint64_t pmceid0; 868 uint64_t pmceid1; 869 uint32_t id_afr0; 870 uint32_t id_mmfr0; 871 uint32_t id_mmfr1; 872 uint32_t id_mmfr2; 873 uint32_t id_mmfr3; 874 uint32_t id_mmfr4; 875 uint64_t id_aa64dfr0; 876 uint64_t id_aa64dfr1; 877 uint64_t id_aa64afr0; 878 uint64_t id_aa64afr1; 879 uint32_t dbgdidr; 880 uint32_t clidr; 881 uint64_t mp_affinity; /* MP ID without feature bits */ 882 /* The elements of this array are the CCSIDR values for each cache, 883 * in the order L1DCache, L1ICache, L2DCache, L2ICache, etc. 884 */ 885 uint32_t ccsidr[16]; 886 uint64_t reset_cbar; 887 uint32_t reset_auxcr; 888 bool reset_hivecs; 889 /* DCZ blocksize, in log_2(words), ie low 4 bits of DCZID_EL0 */ 890 uint32_t dcz_blocksize; 891 uint64_t rvbar; 892 893 /* Configurable aspects of GIC cpu interface (which is part of the CPU) */ 894 int gic_num_lrs; /* number of list registers */ 895 int gic_vpribits; /* number of virtual priority bits */ 896 int gic_vprebits; /* number of virtual preemption bits */ 897 898 /* Whether the cfgend input is high (i.e. this CPU should reset into 899 * big-endian mode). This setting isn't used directly: instead it modifies 900 * the reset_sctlr value to have SCTLR_B or SCTLR_EE set, depending on the 901 * architecture version. 902 */ 903 bool cfgend; 904 905 QLIST_HEAD(, ARMELChangeHook) pre_el_change_hooks; 906 QLIST_HEAD(, ARMELChangeHook) el_change_hooks; 907 908 int32_t node_id; /* NUMA node this CPU belongs to */ 909 910 /* Used to synchronize KVM and QEMU in-kernel device levels */ 911 uint8_t device_irq_level; 912 913 /* Used to set the maximum vector length the cpu will support. */ 914 uint32_t sve_max_vq; 915 }; 916 917 static inline ARMCPU *arm_env_get_cpu(CPUARMState *env) 918 { 919 return container_of(env, ARMCPU, env); 920 } 921 922 void arm_cpu_post_init(Object *obj); 923 924 uint64_t arm_cpu_mp_affinity(int idx, uint8_t clustersz); 925 926 #define ENV_GET_CPU(e) CPU(arm_env_get_cpu(e)) 927 928 #define ENV_OFFSET offsetof(ARMCPU, env) 929 930 #ifndef CONFIG_USER_ONLY 931 extern const struct VMStateDescription vmstate_arm_cpu; 932 #endif 933 934 void arm_cpu_do_interrupt(CPUState *cpu); 935 void arm_v7m_cpu_do_interrupt(CPUState *cpu); 936 bool arm_cpu_exec_interrupt(CPUState *cpu, int int_req); 937 938 void arm_cpu_dump_state(CPUState *cs, FILE *f, fprintf_function cpu_fprintf, 939 int flags); 940 941 hwaddr arm_cpu_get_phys_page_attrs_debug(CPUState *cpu, vaddr addr, 942 MemTxAttrs *attrs); 943 944 int arm_cpu_gdb_read_register(CPUState *cpu, uint8_t *buf, int reg); 945 int arm_cpu_gdb_write_register(CPUState *cpu, uint8_t *buf, int reg); 946 947 /* Dynamically generates for gdb stub an XML description of the sysregs from 948 * the cp_regs hashtable. Returns the registered sysregs number. 949 */ 950 int arm_gen_dynamic_xml(CPUState *cpu); 951 952 /* Returns the dynamically generated XML for the gdb stub. 953 * Returns a pointer to the XML contents for the specified XML file or NULL 954 * if the XML name doesn't match the predefined one. 955 */ 956 const char *arm_gdb_get_dynamic_xml(CPUState *cpu, const char *xmlname); 957 958 int arm_cpu_write_elf64_note(WriteCoreDumpFunction f, CPUState *cs, 959 int cpuid, void *opaque); 960 int arm_cpu_write_elf32_note(WriteCoreDumpFunction f, CPUState *cs, 961 int cpuid, void *opaque); 962 963 #ifdef TARGET_AARCH64 964 int aarch64_cpu_gdb_read_register(CPUState *cpu, uint8_t *buf, int reg); 965 int aarch64_cpu_gdb_write_register(CPUState *cpu, uint8_t *buf, int reg); 966 void aarch64_sve_narrow_vq(CPUARMState *env, unsigned vq); 967 void aarch64_sve_change_el(CPUARMState *env, int old_el, 968 int new_el, bool el0_a64); 969 #else 970 static inline void aarch64_sve_narrow_vq(CPUARMState *env, unsigned vq) { } 971 static inline void aarch64_sve_change_el(CPUARMState *env, int o, 972 int n, bool a) 973 { } 974 #endif 975 976 target_ulong do_arm_semihosting(CPUARMState *env); 977 void aarch64_sync_32_to_64(CPUARMState *env); 978 void aarch64_sync_64_to_32(CPUARMState *env); 979 980 int fp_exception_el(CPUARMState *env, int cur_el); 981 int sve_exception_el(CPUARMState *env, int cur_el); 982 uint32_t sve_zcr_len_for_el(CPUARMState *env, int el); 983 984 static inline bool is_a64(CPUARMState *env) 985 { 986 return env->aarch64; 987 } 988 989 /* you can call this signal handler from your SIGBUS and SIGSEGV 990 signal handlers to inform the virtual CPU of exceptions. non zero 991 is returned if the signal was handled by the virtual CPU. */ 992 int cpu_arm_signal_handler(int host_signum, void *pinfo, 993 void *puc); 994 995 /** 996 * pmccntr_op_start/finish 997 * @env: CPUARMState 998 * 999 * Convert the counter in the PMCCNTR between its delta form (the typical mode 1000 * when it's enabled) and the guest-visible value. These two calls must always 1001 * surround any action which might affect the counter. 1002 */ 1003 void pmccntr_op_start(CPUARMState *env); 1004 void pmccntr_op_finish(CPUARMState *env); 1005 1006 /** 1007 * pmu_op_start/finish 1008 * @env: CPUARMState 1009 * 1010 * Convert all PMU counters between their delta form (the typical mode when 1011 * they are enabled) and the guest-visible values. These two calls must 1012 * surround any action which might affect the counters. 1013 */ 1014 void pmu_op_start(CPUARMState *env); 1015 void pmu_op_finish(CPUARMState *env); 1016 1017 /* 1018 * Called when a PMU counter is due to overflow 1019 */ 1020 void arm_pmu_timer_cb(void *opaque); 1021 1022 /** 1023 * Functions to register as EL change hooks for PMU mode filtering 1024 */ 1025 void pmu_pre_el_change(ARMCPU *cpu, void *ignored); 1026 void pmu_post_el_change(ARMCPU *cpu, void *ignored); 1027 1028 /* 1029 * pmu_init 1030 * @cpu: ARMCPU 1031 * 1032 * Initialize the CPU's PMCEID[01]_EL0 registers and associated internal state 1033 * for the current configuration 1034 */ 1035 void pmu_init(ARMCPU *cpu); 1036 1037 /* SCTLR bit meanings. Several bits have been reused in newer 1038 * versions of the architecture; in that case we define constants 1039 * for both old and new bit meanings. Code which tests against those 1040 * bits should probably check or otherwise arrange that the CPU 1041 * is the architectural version it expects. 1042 */ 1043 #define SCTLR_M (1U << 0) 1044 #define SCTLR_A (1U << 1) 1045 #define SCTLR_C (1U << 2) 1046 #define SCTLR_W (1U << 3) /* up to v6; RAO in v7 */ 1047 #define SCTLR_nTLSMD_32 (1U << 3) /* v8.2-LSMAOC, AArch32 only */ 1048 #define SCTLR_SA (1U << 3) /* AArch64 only */ 1049 #define SCTLR_P (1U << 4) /* up to v5; RAO in v6 and v7 */ 1050 #define SCTLR_LSMAOE_32 (1U << 4) /* v8.2-LSMAOC, AArch32 only */ 1051 #define SCTLR_SA0 (1U << 4) /* v8 onward, AArch64 only */ 1052 #define SCTLR_D (1U << 5) /* up to v5; RAO in v6 */ 1053 #define SCTLR_CP15BEN (1U << 5) /* v7 onward */ 1054 #define SCTLR_L (1U << 6) /* up to v5; RAO in v6 and v7; RAZ in v8 */ 1055 #define SCTLR_nAA (1U << 6) /* when v8.4-LSE is implemented */ 1056 #define SCTLR_B (1U << 7) /* up to v6; RAZ in v7 */ 1057 #define SCTLR_ITD (1U << 7) /* v8 onward */ 1058 #define SCTLR_S (1U << 8) /* up to v6; RAZ in v7 */ 1059 #define SCTLR_SED (1U << 8) /* v8 onward */ 1060 #define SCTLR_R (1U << 9) /* up to v6; RAZ in v7 */ 1061 #define SCTLR_UMA (1U << 9) /* v8 onward, AArch64 only */ 1062 #define SCTLR_F (1U << 10) /* up to v6 */ 1063 #define SCTLR_SW (1U << 10) /* v7, RES0 in v8 */ 1064 #define SCTLR_Z (1U << 11) /* in v7, RES1 in v8 */ 1065 #define SCTLR_EOS (1U << 11) /* v8.5-ExS */ 1066 #define SCTLR_I (1U << 12) 1067 #define SCTLR_V (1U << 13) /* AArch32 only */ 1068 #define SCTLR_EnDB (1U << 13) /* v8.3, AArch64 only */ 1069 #define SCTLR_RR (1U << 14) /* up to v7 */ 1070 #define SCTLR_DZE (1U << 14) /* v8 onward, AArch64 only */ 1071 #define SCTLR_L4 (1U << 15) /* up to v6; RAZ in v7 */ 1072 #define SCTLR_UCT (1U << 15) /* v8 onward, AArch64 only */ 1073 #define SCTLR_DT (1U << 16) /* up to ??, RAO in v6 and v7 */ 1074 #define SCTLR_nTWI (1U << 16) /* v8 onward */ 1075 #define SCTLR_HA (1U << 17) /* up to v7, RES0 in v8 */ 1076 #define SCTLR_BR (1U << 17) /* PMSA only */ 1077 #define SCTLR_IT (1U << 18) /* up to ??, RAO in v6 and v7 */ 1078 #define SCTLR_nTWE (1U << 18) /* v8 onward */ 1079 #define SCTLR_WXN (1U << 19) 1080 #define SCTLR_ST (1U << 20) /* up to ??, RAZ in v6 */ 1081 #define SCTLR_UWXN (1U << 20) /* v7 onward, AArch32 only */ 1082 #define SCTLR_FI (1U << 21) /* up to v7, v8 RES0 */ 1083 #define SCTLR_IESB (1U << 21) /* v8.2-IESB, AArch64 only */ 1084 #define SCTLR_U (1U << 22) /* up to v6, RAO in v7 */ 1085 #define SCTLR_EIS (1U << 22) /* v8.5-ExS */ 1086 #define SCTLR_XP (1U << 23) /* up to v6; v7 onward RAO */ 1087 #define SCTLR_SPAN (1U << 23) /* v8.1-PAN */ 1088 #define SCTLR_VE (1U << 24) /* up to v7 */ 1089 #define SCTLR_E0E (1U << 24) /* v8 onward, AArch64 only */ 1090 #define SCTLR_EE (1U << 25) 1091 #define SCTLR_L2 (1U << 26) /* up to v6, RAZ in v7 */ 1092 #define SCTLR_UCI (1U << 26) /* v8 onward, AArch64 only */ 1093 #define SCTLR_NMFI (1U << 27) /* up to v7, RAZ in v7VE and v8 */ 1094 #define SCTLR_EnDA (1U << 27) /* v8.3, AArch64 only */ 1095 #define SCTLR_TRE (1U << 28) /* AArch32 only */ 1096 #define SCTLR_nTLSMD_64 (1U << 28) /* v8.2-LSMAOC, AArch64 only */ 1097 #define SCTLR_AFE (1U << 29) /* AArch32 only */ 1098 #define SCTLR_LSMAOE_64 (1U << 29) /* v8.2-LSMAOC, AArch64 only */ 1099 #define SCTLR_TE (1U << 30) /* AArch32 only */ 1100 #define SCTLR_EnIB (1U << 30) /* v8.3, AArch64 only */ 1101 #define SCTLR_EnIA (1U << 31) /* v8.3, AArch64 only */ 1102 #define SCTLR_BT0 (1ULL << 35) /* v8.5-BTI */ 1103 #define SCTLR_BT1 (1ULL << 36) /* v8.5-BTI */ 1104 #define SCTLR_ITFSB (1ULL << 37) /* v8.5-MemTag */ 1105 #define SCTLR_TCF0 (3ULL << 38) /* v8.5-MemTag */ 1106 #define SCTLR_TCF (3ULL << 40) /* v8.5-MemTag */ 1107 #define SCTLR_ATA0 (1ULL << 42) /* v8.5-MemTag */ 1108 #define SCTLR_ATA (1ULL << 43) /* v8.5-MemTag */ 1109 #define SCTLR_DSSBS (1ULL << 44) /* v8.5 */ 1110 1111 #define CPTR_TCPAC (1U << 31) 1112 #define CPTR_TTA (1U << 20) 1113 #define CPTR_TFP (1U << 10) 1114 #define CPTR_TZ (1U << 8) /* CPTR_EL2 */ 1115 #define CPTR_EZ (1U << 8) /* CPTR_EL3 */ 1116 1117 #define MDCR_EPMAD (1U << 21) 1118 #define MDCR_EDAD (1U << 20) 1119 #define MDCR_SPME (1U << 17) /* MDCR_EL3 */ 1120 #define MDCR_HPMD (1U << 17) /* MDCR_EL2 */ 1121 #define MDCR_SDD (1U << 16) 1122 #define MDCR_SPD (3U << 14) 1123 #define MDCR_TDRA (1U << 11) 1124 #define MDCR_TDOSA (1U << 10) 1125 #define MDCR_TDA (1U << 9) 1126 #define MDCR_TDE (1U << 8) 1127 #define MDCR_HPME (1U << 7) 1128 #define MDCR_TPM (1U << 6) 1129 #define MDCR_TPMCR (1U << 5) 1130 #define MDCR_HPMN (0x1fU) 1131 1132 /* Not all of the MDCR_EL3 bits are present in the 32-bit SDCR */ 1133 #define SDCR_VALID_MASK (MDCR_EPMAD | MDCR_EDAD | MDCR_SPME | MDCR_SPD) 1134 1135 #define CPSR_M (0x1fU) 1136 #define CPSR_T (1U << 5) 1137 #define CPSR_F (1U << 6) 1138 #define CPSR_I (1U << 7) 1139 #define CPSR_A (1U << 8) 1140 #define CPSR_E (1U << 9) 1141 #define CPSR_IT_2_7 (0xfc00U) 1142 #define CPSR_GE (0xfU << 16) 1143 #define CPSR_IL (1U << 20) 1144 /* Note that the RESERVED bits include bit 21, which is PSTATE_SS in 1145 * an AArch64 SPSR but RES0 in AArch32 SPSR and CPSR. In QEMU we use 1146 * env->uncached_cpsr bit 21 to store PSTATE.SS when executing in AArch32, 1147 * where it is live state but not accessible to the AArch32 code. 1148 */ 1149 #define CPSR_RESERVED (0x7U << 21) 1150 #define CPSR_J (1U << 24) 1151 #define CPSR_IT_0_1 (3U << 25) 1152 #define CPSR_Q (1U << 27) 1153 #define CPSR_V (1U << 28) 1154 #define CPSR_C (1U << 29) 1155 #define CPSR_Z (1U << 30) 1156 #define CPSR_N (1U << 31) 1157 #define CPSR_NZCV (CPSR_N | CPSR_Z | CPSR_C | CPSR_V) 1158 #define CPSR_AIF (CPSR_A | CPSR_I | CPSR_F) 1159 1160 #define CPSR_IT (CPSR_IT_0_1 | CPSR_IT_2_7) 1161 #define CACHED_CPSR_BITS (CPSR_T | CPSR_AIF | CPSR_GE | CPSR_IT | CPSR_Q \ 1162 | CPSR_NZCV) 1163 /* Bits writable in user mode. */ 1164 #define CPSR_USER (CPSR_NZCV | CPSR_Q | CPSR_GE) 1165 /* Execution state bits. MRS read as zero, MSR writes ignored. */ 1166 #define CPSR_EXEC (CPSR_T | CPSR_IT | CPSR_J | CPSR_IL) 1167 /* Mask of bits which may be set by exception return copying them from SPSR */ 1168 #define CPSR_ERET_MASK (~CPSR_RESERVED) 1169 1170 /* Bit definitions for M profile XPSR. Most are the same as CPSR. */ 1171 #define XPSR_EXCP 0x1ffU 1172 #define XPSR_SPREALIGN (1U << 9) /* Only set in exception stack frames */ 1173 #define XPSR_IT_2_7 CPSR_IT_2_7 1174 #define XPSR_GE CPSR_GE 1175 #define XPSR_SFPA (1U << 20) /* Only set in exception stack frames */ 1176 #define XPSR_T (1U << 24) /* Not the same as CPSR_T ! */ 1177 #define XPSR_IT_0_1 CPSR_IT_0_1 1178 #define XPSR_Q CPSR_Q 1179 #define XPSR_V CPSR_V 1180 #define XPSR_C CPSR_C 1181 #define XPSR_Z CPSR_Z 1182 #define XPSR_N CPSR_N 1183 #define XPSR_NZCV CPSR_NZCV 1184 #define XPSR_IT CPSR_IT 1185 1186 #define TTBCR_N (7U << 0) /* TTBCR.EAE==0 */ 1187 #define TTBCR_T0SZ (7U << 0) /* TTBCR.EAE==1 */ 1188 #define TTBCR_PD0 (1U << 4) 1189 #define TTBCR_PD1 (1U << 5) 1190 #define TTBCR_EPD0 (1U << 7) 1191 #define TTBCR_IRGN0 (3U << 8) 1192 #define TTBCR_ORGN0 (3U << 10) 1193 #define TTBCR_SH0 (3U << 12) 1194 #define TTBCR_T1SZ (3U << 16) 1195 #define TTBCR_A1 (1U << 22) 1196 #define TTBCR_EPD1 (1U << 23) 1197 #define TTBCR_IRGN1 (3U << 24) 1198 #define TTBCR_ORGN1 (3U << 26) 1199 #define TTBCR_SH1 (1U << 28) 1200 #define TTBCR_EAE (1U << 31) 1201 1202 /* Bit definitions for ARMv8 SPSR (PSTATE) format. 1203 * Only these are valid when in AArch64 mode; in 1204 * AArch32 mode SPSRs are basically CPSR-format. 1205 */ 1206 #define PSTATE_SP (1U) 1207 #define PSTATE_M (0xFU) 1208 #define PSTATE_nRW (1U << 4) 1209 #define PSTATE_F (1U << 6) 1210 #define PSTATE_I (1U << 7) 1211 #define PSTATE_A (1U << 8) 1212 #define PSTATE_D (1U << 9) 1213 #define PSTATE_BTYPE (3U << 10) 1214 #define PSTATE_IL (1U << 20) 1215 #define PSTATE_SS (1U << 21) 1216 #define PSTATE_V (1U << 28) 1217 #define PSTATE_C (1U << 29) 1218 #define PSTATE_Z (1U << 30) 1219 #define PSTATE_N (1U << 31) 1220 #define PSTATE_NZCV (PSTATE_N | PSTATE_Z | PSTATE_C | PSTATE_V) 1221 #define PSTATE_DAIF (PSTATE_D | PSTATE_A | PSTATE_I | PSTATE_F) 1222 #define CACHED_PSTATE_BITS (PSTATE_NZCV | PSTATE_DAIF | PSTATE_BTYPE) 1223 /* Mode values for AArch64 */ 1224 #define PSTATE_MODE_EL3h 13 1225 #define PSTATE_MODE_EL3t 12 1226 #define PSTATE_MODE_EL2h 9 1227 #define PSTATE_MODE_EL2t 8 1228 #define PSTATE_MODE_EL1h 5 1229 #define PSTATE_MODE_EL1t 4 1230 #define PSTATE_MODE_EL0t 0 1231 1232 /* Write a new value to v7m.exception, thus transitioning into or out 1233 * of Handler mode; this may result in a change of active stack pointer. 1234 */ 1235 void write_v7m_exception(CPUARMState *env, uint32_t new_exc); 1236 1237 /* Map EL and handler into a PSTATE_MODE. */ 1238 static inline unsigned int aarch64_pstate_mode(unsigned int el, bool handler) 1239 { 1240 return (el << 2) | handler; 1241 } 1242 1243 /* Return the current PSTATE value. For the moment we don't support 32<->64 bit 1244 * interprocessing, so we don't attempt to sync with the cpsr state used by 1245 * the 32 bit decoder. 1246 */ 1247 static inline uint32_t pstate_read(CPUARMState *env) 1248 { 1249 int ZF; 1250 1251 ZF = (env->ZF == 0); 1252 return (env->NF & 0x80000000) | (ZF << 30) 1253 | (env->CF << 29) | ((env->VF & 0x80000000) >> 3) 1254 | env->pstate | env->daif | (env->btype << 10); 1255 } 1256 1257 static inline void pstate_write(CPUARMState *env, uint32_t val) 1258 { 1259 env->ZF = (~val) & PSTATE_Z; 1260 env->NF = val; 1261 env->CF = (val >> 29) & 1; 1262 env->VF = (val << 3) & 0x80000000; 1263 env->daif = val & PSTATE_DAIF; 1264 env->btype = (val >> 10) & 3; 1265 env->pstate = val & ~CACHED_PSTATE_BITS; 1266 } 1267 1268 /* Return the current CPSR value. */ 1269 uint32_t cpsr_read(CPUARMState *env); 1270 1271 typedef enum CPSRWriteType { 1272 CPSRWriteByInstr = 0, /* from guest MSR or CPS */ 1273 CPSRWriteExceptionReturn = 1, /* from guest exception return insn */ 1274 CPSRWriteRaw = 2, /* trust values, do not switch reg banks */ 1275 CPSRWriteByGDBStub = 3, /* from the GDB stub */ 1276 } CPSRWriteType; 1277 1278 /* Set the CPSR. Note that some bits of mask must be all-set or all-clear.*/ 1279 void cpsr_write(CPUARMState *env, uint32_t val, uint32_t mask, 1280 CPSRWriteType write_type); 1281 1282 /* Return the current xPSR value. */ 1283 static inline uint32_t xpsr_read(CPUARMState *env) 1284 { 1285 int ZF; 1286 ZF = (env->ZF == 0); 1287 return (env->NF & 0x80000000) | (ZF << 30) 1288 | (env->CF << 29) | ((env->VF & 0x80000000) >> 3) | (env->QF << 27) 1289 | (env->thumb << 24) | ((env->condexec_bits & 3) << 25) 1290 | ((env->condexec_bits & 0xfc) << 8) 1291 | env->v7m.exception; 1292 } 1293 1294 /* Set the xPSR. Note that some bits of mask must be all-set or all-clear. */ 1295 static inline void xpsr_write(CPUARMState *env, uint32_t val, uint32_t mask) 1296 { 1297 if (mask & XPSR_NZCV) { 1298 env->ZF = (~val) & XPSR_Z; 1299 env->NF = val; 1300 env->CF = (val >> 29) & 1; 1301 env->VF = (val << 3) & 0x80000000; 1302 } 1303 if (mask & XPSR_Q) { 1304 env->QF = ((val & XPSR_Q) != 0); 1305 } 1306 if (mask & XPSR_T) { 1307 env->thumb = ((val & XPSR_T) != 0); 1308 } 1309 if (mask & XPSR_IT_0_1) { 1310 env->condexec_bits &= ~3; 1311 env->condexec_bits |= (val >> 25) & 3; 1312 } 1313 if (mask & XPSR_IT_2_7) { 1314 env->condexec_bits &= 3; 1315 env->condexec_bits |= (val >> 8) & 0xfc; 1316 } 1317 if (mask & XPSR_EXCP) { 1318 /* Note that this only happens on exception exit */ 1319 write_v7m_exception(env, val & XPSR_EXCP); 1320 } 1321 } 1322 1323 #define HCR_VM (1ULL << 0) 1324 #define HCR_SWIO (1ULL << 1) 1325 #define HCR_PTW (1ULL << 2) 1326 #define HCR_FMO (1ULL << 3) 1327 #define HCR_IMO (1ULL << 4) 1328 #define HCR_AMO (1ULL << 5) 1329 #define HCR_VF (1ULL << 6) 1330 #define HCR_VI (1ULL << 7) 1331 #define HCR_VSE (1ULL << 8) 1332 #define HCR_FB (1ULL << 9) 1333 #define HCR_BSU_MASK (3ULL << 10) 1334 #define HCR_DC (1ULL << 12) 1335 #define HCR_TWI (1ULL << 13) 1336 #define HCR_TWE (1ULL << 14) 1337 #define HCR_TID0 (1ULL << 15) 1338 #define HCR_TID1 (1ULL << 16) 1339 #define HCR_TID2 (1ULL << 17) 1340 #define HCR_TID3 (1ULL << 18) 1341 #define HCR_TSC (1ULL << 19) 1342 #define HCR_TIDCP (1ULL << 20) 1343 #define HCR_TACR (1ULL << 21) 1344 #define HCR_TSW (1ULL << 22) 1345 #define HCR_TPCP (1ULL << 23) 1346 #define HCR_TPU (1ULL << 24) 1347 #define HCR_TTLB (1ULL << 25) 1348 #define HCR_TVM (1ULL << 26) 1349 #define HCR_TGE (1ULL << 27) 1350 #define HCR_TDZ (1ULL << 28) 1351 #define HCR_HCD (1ULL << 29) 1352 #define HCR_TRVM (1ULL << 30) 1353 #define HCR_RW (1ULL << 31) 1354 #define HCR_CD (1ULL << 32) 1355 #define HCR_ID (1ULL << 33) 1356 #define HCR_E2H (1ULL << 34) 1357 #define HCR_TLOR (1ULL << 35) 1358 #define HCR_TERR (1ULL << 36) 1359 #define HCR_TEA (1ULL << 37) 1360 #define HCR_MIOCNCE (1ULL << 38) 1361 #define HCR_APK (1ULL << 40) 1362 #define HCR_API (1ULL << 41) 1363 #define HCR_NV (1ULL << 42) 1364 #define HCR_NV1 (1ULL << 43) 1365 #define HCR_AT (1ULL << 44) 1366 #define HCR_NV2 (1ULL << 45) 1367 #define HCR_FWB (1ULL << 46) 1368 #define HCR_FIEN (1ULL << 47) 1369 #define HCR_TID4 (1ULL << 49) 1370 #define HCR_TICAB (1ULL << 50) 1371 #define HCR_TOCU (1ULL << 52) 1372 #define HCR_TTLBIS (1ULL << 54) 1373 #define HCR_TTLBOS (1ULL << 55) 1374 #define HCR_ATA (1ULL << 56) 1375 #define HCR_DCT (1ULL << 57) 1376 1377 /* 1378 * When we actually implement ARMv8.1-VHE we should add HCR_E2H to 1379 * HCR_MASK and then clear it again if the feature bit is not set in 1380 * hcr_write(). 1381 */ 1382 #define HCR_MASK ((1ULL << 34) - 1) 1383 1384 #define SCR_NS (1U << 0) 1385 #define SCR_IRQ (1U << 1) 1386 #define SCR_FIQ (1U << 2) 1387 #define SCR_EA (1U << 3) 1388 #define SCR_FW (1U << 4) 1389 #define SCR_AW (1U << 5) 1390 #define SCR_NET (1U << 6) 1391 #define SCR_SMD (1U << 7) 1392 #define SCR_HCE (1U << 8) 1393 #define SCR_SIF (1U << 9) 1394 #define SCR_RW (1U << 10) 1395 #define SCR_ST (1U << 11) 1396 #define SCR_TWI (1U << 12) 1397 #define SCR_TWE (1U << 13) 1398 #define SCR_TLOR (1U << 14) 1399 #define SCR_TERR (1U << 15) 1400 #define SCR_APK (1U << 16) 1401 #define SCR_API (1U << 17) 1402 #define SCR_EEL2 (1U << 18) 1403 #define SCR_EASE (1U << 19) 1404 #define SCR_NMEA (1U << 20) 1405 #define SCR_FIEN (1U << 21) 1406 #define SCR_ENSCXT (1U << 25) 1407 #define SCR_ATA (1U << 26) 1408 1409 /* Return the current FPSCR value. */ 1410 uint32_t vfp_get_fpscr(CPUARMState *env); 1411 void vfp_set_fpscr(CPUARMState *env, uint32_t val); 1412 1413 /* FPCR, Floating Point Control Register 1414 * FPSR, Floating Poiht Status Register 1415 * 1416 * For A64 the FPSCR is split into two logically distinct registers, 1417 * FPCR and FPSR. However since they still use non-overlapping bits 1418 * we store the underlying state in fpscr and just mask on read/write. 1419 */ 1420 #define FPSR_MASK 0xf800009f 1421 #define FPCR_MASK 0x07ff9f00 1422 1423 #define FPCR_IOE (1 << 8) /* Invalid Operation exception trap enable */ 1424 #define FPCR_DZE (1 << 9) /* Divide by Zero exception trap enable */ 1425 #define FPCR_OFE (1 << 10) /* Overflow exception trap enable */ 1426 #define FPCR_UFE (1 << 11) /* Underflow exception trap enable */ 1427 #define FPCR_IXE (1 << 12) /* Inexact exception trap enable */ 1428 #define FPCR_IDE (1 << 15) /* Input Denormal exception trap enable */ 1429 #define FPCR_FZ16 (1 << 19) /* ARMv8.2+, FP16 flush-to-zero */ 1430 #define FPCR_FZ (1 << 24) /* Flush-to-zero enable bit */ 1431 #define FPCR_DN (1 << 25) /* Default NaN enable bit */ 1432 #define FPCR_QC (1 << 27) /* Cumulative saturation bit */ 1433 1434 static inline uint32_t vfp_get_fpsr(CPUARMState *env) 1435 { 1436 return vfp_get_fpscr(env) & FPSR_MASK; 1437 } 1438 1439 static inline void vfp_set_fpsr(CPUARMState *env, uint32_t val) 1440 { 1441 uint32_t new_fpscr = (vfp_get_fpscr(env) & ~FPSR_MASK) | (val & FPSR_MASK); 1442 vfp_set_fpscr(env, new_fpscr); 1443 } 1444 1445 static inline uint32_t vfp_get_fpcr(CPUARMState *env) 1446 { 1447 return vfp_get_fpscr(env) & FPCR_MASK; 1448 } 1449 1450 static inline void vfp_set_fpcr(CPUARMState *env, uint32_t val) 1451 { 1452 uint32_t new_fpscr = (vfp_get_fpscr(env) & ~FPCR_MASK) | (val & FPCR_MASK); 1453 vfp_set_fpscr(env, new_fpscr); 1454 } 1455 1456 enum arm_cpu_mode { 1457 ARM_CPU_MODE_USR = 0x10, 1458 ARM_CPU_MODE_FIQ = 0x11, 1459 ARM_CPU_MODE_IRQ = 0x12, 1460 ARM_CPU_MODE_SVC = 0x13, 1461 ARM_CPU_MODE_MON = 0x16, 1462 ARM_CPU_MODE_ABT = 0x17, 1463 ARM_CPU_MODE_HYP = 0x1a, 1464 ARM_CPU_MODE_UND = 0x1b, 1465 ARM_CPU_MODE_SYS = 0x1f 1466 }; 1467 1468 /* VFP system registers. */ 1469 #define ARM_VFP_FPSID 0 1470 #define ARM_VFP_FPSCR 1 1471 #define ARM_VFP_MVFR2 5 1472 #define ARM_VFP_MVFR1 6 1473 #define ARM_VFP_MVFR0 7 1474 #define ARM_VFP_FPEXC 8 1475 #define ARM_VFP_FPINST 9 1476 #define ARM_VFP_FPINST2 10 1477 1478 /* iwMMXt coprocessor control registers. */ 1479 #define ARM_IWMMXT_wCID 0 1480 #define ARM_IWMMXT_wCon 1 1481 #define ARM_IWMMXT_wCSSF 2 1482 #define ARM_IWMMXT_wCASF 3 1483 #define ARM_IWMMXT_wCGR0 8 1484 #define ARM_IWMMXT_wCGR1 9 1485 #define ARM_IWMMXT_wCGR2 10 1486 #define ARM_IWMMXT_wCGR3 11 1487 1488 /* V7M CCR bits */ 1489 FIELD(V7M_CCR, NONBASETHRDENA, 0, 1) 1490 FIELD(V7M_CCR, USERSETMPEND, 1, 1) 1491 FIELD(V7M_CCR, UNALIGN_TRP, 3, 1) 1492 FIELD(V7M_CCR, DIV_0_TRP, 4, 1) 1493 FIELD(V7M_CCR, BFHFNMIGN, 8, 1) 1494 FIELD(V7M_CCR, STKALIGN, 9, 1) 1495 FIELD(V7M_CCR, STKOFHFNMIGN, 10, 1) 1496 FIELD(V7M_CCR, DC, 16, 1) 1497 FIELD(V7M_CCR, IC, 17, 1) 1498 FIELD(V7M_CCR, BP, 18, 1) 1499 1500 /* V7M SCR bits */ 1501 FIELD(V7M_SCR, SLEEPONEXIT, 1, 1) 1502 FIELD(V7M_SCR, SLEEPDEEP, 2, 1) 1503 FIELD(V7M_SCR, SLEEPDEEPS, 3, 1) 1504 FIELD(V7M_SCR, SEVONPEND, 4, 1) 1505 1506 /* V7M AIRCR bits */ 1507 FIELD(V7M_AIRCR, VECTRESET, 0, 1) 1508 FIELD(V7M_AIRCR, VECTCLRACTIVE, 1, 1) 1509 FIELD(V7M_AIRCR, SYSRESETREQ, 2, 1) 1510 FIELD(V7M_AIRCR, SYSRESETREQS, 3, 1) 1511 FIELD(V7M_AIRCR, PRIGROUP, 8, 3) 1512 FIELD(V7M_AIRCR, BFHFNMINS, 13, 1) 1513 FIELD(V7M_AIRCR, PRIS, 14, 1) 1514 FIELD(V7M_AIRCR, ENDIANNESS, 15, 1) 1515 FIELD(V7M_AIRCR, VECTKEY, 16, 16) 1516 1517 /* V7M CFSR bits for MMFSR */ 1518 FIELD(V7M_CFSR, IACCVIOL, 0, 1) 1519 FIELD(V7M_CFSR, DACCVIOL, 1, 1) 1520 FIELD(V7M_CFSR, MUNSTKERR, 3, 1) 1521 FIELD(V7M_CFSR, MSTKERR, 4, 1) 1522 FIELD(V7M_CFSR, MLSPERR, 5, 1) 1523 FIELD(V7M_CFSR, MMARVALID, 7, 1) 1524 1525 /* V7M CFSR bits for BFSR */ 1526 FIELD(V7M_CFSR, IBUSERR, 8 + 0, 1) 1527 FIELD(V7M_CFSR, PRECISERR, 8 + 1, 1) 1528 FIELD(V7M_CFSR, IMPRECISERR, 8 + 2, 1) 1529 FIELD(V7M_CFSR, UNSTKERR, 8 + 3, 1) 1530 FIELD(V7M_CFSR, STKERR, 8 + 4, 1) 1531 FIELD(V7M_CFSR, LSPERR, 8 + 5, 1) 1532 FIELD(V7M_CFSR, BFARVALID, 8 + 7, 1) 1533 1534 /* V7M CFSR bits for UFSR */ 1535 FIELD(V7M_CFSR, UNDEFINSTR, 16 + 0, 1) 1536 FIELD(V7M_CFSR, INVSTATE, 16 + 1, 1) 1537 FIELD(V7M_CFSR, INVPC, 16 + 2, 1) 1538 FIELD(V7M_CFSR, NOCP, 16 + 3, 1) 1539 FIELD(V7M_CFSR, STKOF, 16 + 4, 1) 1540 FIELD(V7M_CFSR, UNALIGNED, 16 + 8, 1) 1541 FIELD(V7M_CFSR, DIVBYZERO, 16 + 9, 1) 1542 1543 /* V7M CFSR bit masks covering all of the subregister bits */ 1544 FIELD(V7M_CFSR, MMFSR, 0, 8) 1545 FIELD(V7M_CFSR, BFSR, 8, 8) 1546 FIELD(V7M_CFSR, UFSR, 16, 16) 1547 1548 /* V7M HFSR bits */ 1549 FIELD(V7M_HFSR, VECTTBL, 1, 1) 1550 FIELD(V7M_HFSR, FORCED, 30, 1) 1551 FIELD(V7M_HFSR, DEBUGEVT, 31, 1) 1552 1553 /* V7M DFSR bits */ 1554 FIELD(V7M_DFSR, HALTED, 0, 1) 1555 FIELD(V7M_DFSR, BKPT, 1, 1) 1556 FIELD(V7M_DFSR, DWTTRAP, 2, 1) 1557 FIELD(V7M_DFSR, VCATCH, 3, 1) 1558 FIELD(V7M_DFSR, EXTERNAL, 4, 1) 1559 1560 /* V7M SFSR bits */ 1561 FIELD(V7M_SFSR, INVEP, 0, 1) 1562 FIELD(V7M_SFSR, INVIS, 1, 1) 1563 FIELD(V7M_SFSR, INVER, 2, 1) 1564 FIELD(V7M_SFSR, AUVIOL, 3, 1) 1565 FIELD(V7M_SFSR, INVTRAN, 4, 1) 1566 FIELD(V7M_SFSR, LSPERR, 5, 1) 1567 FIELD(V7M_SFSR, SFARVALID, 6, 1) 1568 FIELD(V7M_SFSR, LSERR, 7, 1) 1569 1570 /* v7M MPU_CTRL bits */ 1571 FIELD(V7M_MPU_CTRL, ENABLE, 0, 1) 1572 FIELD(V7M_MPU_CTRL, HFNMIENA, 1, 1) 1573 FIELD(V7M_MPU_CTRL, PRIVDEFENA, 2, 1) 1574 1575 /* v7M CLIDR bits */ 1576 FIELD(V7M_CLIDR, CTYPE_ALL, 0, 21) 1577 FIELD(V7M_CLIDR, LOUIS, 21, 3) 1578 FIELD(V7M_CLIDR, LOC, 24, 3) 1579 FIELD(V7M_CLIDR, LOUU, 27, 3) 1580 FIELD(V7M_CLIDR, ICB, 30, 2) 1581 1582 FIELD(V7M_CSSELR, IND, 0, 1) 1583 FIELD(V7M_CSSELR, LEVEL, 1, 3) 1584 /* We use the combination of InD and Level to index into cpu->ccsidr[]; 1585 * define a mask for this and check that it doesn't permit running off 1586 * the end of the array. 1587 */ 1588 FIELD(V7M_CSSELR, INDEX, 0, 4) 1589 1590 /* 1591 * System register ID fields. 1592 */ 1593 FIELD(ID_ISAR0, SWAP, 0, 4) 1594 FIELD(ID_ISAR0, BITCOUNT, 4, 4) 1595 FIELD(ID_ISAR0, BITFIELD, 8, 4) 1596 FIELD(ID_ISAR0, CMPBRANCH, 12, 4) 1597 FIELD(ID_ISAR0, COPROC, 16, 4) 1598 FIELD(ID_ISAR0, DEBUG, 20, 4) 1599 FIELD(ID_ISAR0, DIVIDE, 24, 4) 1600 1601 FIELD(ID_ISAR1, ENDIAN, 0, 4) 1602 FIELD(ID_ISAR1, EXCEPT, 4, 4) 1603 FIELD(ID_ISAR1, EXCEPT_AR, 8, 4) 1604 FIELD(ID_ISAR1, EXTEND, 12, 4) 1605 FIELD(ID_ISAR1, IFTHEN, 16, 4) 1606 FIELD(ID_ISAR1, IMMEDIATE, 20, 4) 1607 FIELD(ID_ISAR1, INTERWORK, 24, 4) 1608 FIELD(ID_ISAR1, JAZELLE, 28, 4) 1609 1610 FIELD(ID_ISAR2, LOADSTORE, 0, 4) 1611 FIELD(ID_ISAR2, MEMHINT, 4, 4) 1612 FIELD(ID_ISAR2, MULTIACCESSINT, 8, 4) 1613 FIELD(ID_ISAR2, MULT, 12, 4) 1614 FIELD(ID_ISAR2, MULTS, 16, 4) 1615 FIELD(ID_ISAR2, MULTU, 20, 4) 1616 FIELD(ID_ISAR2, PSR_AR, 24, 4) 1617 FIELD(ID_ISAR2, REVERSAL, 28, 4) 1618 1619 FIELD(ID_ISAR3, SATURATE, 0, 4) 1620 FIELD(ID_ISAR3, SIMD, 4, 4) 1621 FIELD(ID_ISAR3, SVC, 8, 4) 1622 FIELD(ID_ISAR3, SYNCHPRIM, 12, 4) 1623 FIELD(ID_ISAR3, TABBRANCH, 16, 4) 1624 FIELD(ID_ISAR3, T32COPY, 20, 4) 1625 FIELD(ID_ISAR3, TRUENOP, 24, 4) 1626 FIELD(ID_ISAR3, T32EE, 28, 4) 1627 1628 FIELD(ID_ISAR4, UNPRIV, 0, 4) 1629 FIELD(ID_ISAR4, WITHSHIFTS, 4, 4) 1630 FIELD(ID_ISAR4, WRITEBACK, 8, 4) 1631 FIELD(ID_ISAR4, SMC, 12, 4) 1632 FIELD(ID_ISAR4, BARRIER, 16, 4) 1633 FIELD(ID_ISAR4, SYNCHPRIM_FRAC, 20, 4) 1634 FIELD(ID_ISAR4, PSR_M, 24, 4) 1635 FIELD(ID_ISAR4, SWP_FRAC, 28, 4) 1636 1637 FIELD(ID_ISAR5, SEVL, 0, 4) 1638 FIELD(ID_ISAR5, AES, 4, 4) 1639 FIELD(ID_ISAR5, SHA1, 8, 4) 1640 FIELD(ID_ISAR5, SHA2, 12, 4) 1641 FIELD(ID_ISAR5, CRC32, 16, 4) 1642 FIELD(ID_ISAR5, RDM, 24, 4) 1643 FIELD(ID_ISAR5, VCMA, 28, 4) 1644 1645 FIELD(ID_ISAR6, JSCVT, 0, 4) 1646 FIELD(ID_ISAR6, DP, 4, 4) 1647 FIELD(ID_ISAR6, FHM, 8, 4) 1648 FIELD(ID_ISAR6, SB, 12, 4) 1649 FIELD(ID_ISAR6, SPECRES, 16, 4) 1650 1651 FIELD(ID_MMFR4, SPECSEI, 0, 4) 1652 FIELD(ID_MMFR4, AC2, 4, 4) 1653 FIELD(ID_MMFR4, XNX, 8, 4) 1654 FIELD(ID_MMFR4, CNP, 12, 4) 1655 FIELD(ID_MMFR4, HPDS, 16, 4) 1656 FIELD(ID_MMFR4, LSM, 20, 4) 1657 FIELD(ID_MMFR4, CCIDX, 24, 4) 1658 FIELD(ID_MMFR4, EVT, 28, 4) 1659 1660 FIELD(ID_AA64ISAR0, AES, 4, 4) 1661 FIELD(ID_AA64ISAR0, SHA1, 8, 4) 1662 FIELD(ID_AA64ISAR0, SHA2, 12, 4) 1663 FIELD(ID_AA64ISAR0, CRC32, 16, 4) 1664 FIELD(ID_AA64ISAR0, ATOMIC, 20, 4) 1665 FIELD(ID_AA64ISAR0, RDM, 28, 4) 1666 FIELD(ID_AA64ISAR0, SHA3, 32, 4) 1667 FIELD(ID_AA64ISAR0, SM3, 36, 4) 1668 FIELD(ID_AA64ISAR0, SM4, 40, 4) 1669 FIELD(ID_AA64ISAR0, DP, 44, 4) 1670 FIELD(ID_AA64ISAR0, FHM, 48, 4) 1671 FIELD(ID_AA64ISAR0, TS, 52, 4) 1672 FIELD(ID_AA64ISAR0, TLB, 56, 4) 1673 FIELD(ID_AA64ISAR0, RNDR, 60, 4) 1674 1675 FIELD(ID_AA64ISAR1, DPB, 0, 4) 1676 FIELD(ID_AA64ISAR1, APA, 4, 4) 1677 FIELD(ID_AA64ISAR1, API, 8, 4) 1678 FIELD(ID_AA64ISAR1, JSCVT, 12, 4) 1679 FIELD(ID_AA64ISAR1, FCMA, 16, 4) 1680 FIELD(ID_AA64ISAR1, LRCPC, 20, 4) 1681 FIELD(ID_AA64ISAR1, GPA, 24, 4) 1682 FIELD(ID_AA64ISAR1, GPI, 28, 4) 1683 FIELD(ID_AA64ISAR1, FRINTTS, 32, 4) 1684 FIELD(ID_AA64ISAR1, SB, 36, 4) 1685 FIELD(ID_AA64ISAR1, SPECRES, 40, 4) 1686 1687 FIELD(ID_AA64PFR0, EL0, 0, 4) 1688 FIELD(ID_AA64PFR0, EL1, 4, 4) 1689 FIELD(ID_AA64PFR0, EL2, 8, 4) 1690 FIELD(ID_AA64PFR0, EL3, 12, 4) 1691 FIELD(ID_AA64PFR0, FP, 16, 4) 1692 FIELD(ID_AA64PFR0, ADVSIMD, 20, 4) 1693 FIELD(ID_AA64PFR0, GIC, 24, 4) 1694 FIELD(ID_AA64PFR0, RAS, 28, 4) 1695 FIELD(ID_AA64PFR0, SVE, 32, 4) 1696 1697 FIELD(ID_AA64PFR1, BT, 0, 4) 1698 FIELD(ID_AA64PFR1, SBSS, 4, 4) 1699 FIELD(ID_AA64PFR1, MTE, 8, 4) 1700 FIELD(ID_AA64PFR1, RAS_FRAC, 12, 4) 1701 1702 FIELD(ID_AA64MMFR0, PARANGE, 0, 4) 1703 FIELD(ID_AA64MMFR0, ASIDBITS, 4, 4) 1704 FIELD(ID_AA64MMFR0, BIGEND, 8, 4) 1705 FIELD(ID_AA64MMFR0, SNSMEM, 12, 4) 1706 FIELD(ID_AA64MMFR0, BIGENDEL0, 16, 4) 1707 FIELD(ID_AA64MMFR0, TGRAN16, 20, 4) 1708 FIELD(ID_AA64MMFR0, TGRAN64, 24, 4) 1709 FIELD(ID_AA64MMFR0, TGRAN4, 28, 4) 1710 FIELD(ID_AA64MMFR0, TGRAN16_2, 32, 4) 1711 FIELD(ID_AA64MMFR0, TGRAN64_2, 36, 4) 1712 FIELD(ID_AA64MMFR0, TGRAN4_2, 40, 4) 1713 FIELD(ID_AA64MMFR0, EXS, 44, 4) 1714 1715 FIELD(ID_AA64MMFR1, HAFDBS, 0, 4) 1716 FIELD(ID_AA64MMFR1, VMIDBITS, 4, 4) 1717 FIELD(ID_AA64MMFR1, VH, 8, 4) 1718 FIELD(ID_AA64MMFR1, HPDS, 12, 4) 1719 FIELD(ID_AA64MMFR1, LO, 16, 4) 1720 FIELD(ID_AA64MMFR1, PAN, 20, 4) 1721 FIELD(ID_AA64MMFR1, SPECSEI, 24, 4) 1722 FIELD(ID_AA64MMFR1, XNX, 28, 4) 1723 1724 FIELD(ID_DFR0, COPDBG, 0, 4) 1725 FIELD(ID_DFR0, COPSDBG, 4, 4) 1726 FIELD(ID_DFR0, MMAPDBG, 8, 4) 1727 FIELD(ID_DFR0, COPTRC, 12, 4) 1728 FIELD(ID_DFR0, MMAPTRC, 16, 4) 1729 FIELD(ID_DFR0, MPROFDBG, 20, 4) 1730 FIELD(ID_DFR0, PERFMON, 24, 4) 1731 FIELD(ID_DFR0, TRACEFILT, 28, 4) 1732 1733 QEMU_BUILD_BUG_ON(ARRAY_SIZE(((ARMCPU *)0)->ccsidr) <= R_V7M_CSSELR_INDEX_MASK); 1734 1735 /* If adding a feature bit which corresponds to a Linux ELF 1736 * HWCAP bit, remember to update the feature-bit-to-hwcap 1737 * mapping in linux-user/elfload.c:get_elf_hwcap(). 1738 */ 1739 enum arm_features { 1740 ARM_FEATURE_VFP, 1741 ARM_FEATURE_AUXCR, /* ARM1026 Auxiliary control register. */ 1742 ARM_FEATURE_XSCALE, /* Intel XScale extensions. */ 1743 ARM_FEATURE_IWMMXT, /* Intel iwMMXt extension. */ 1744 ARM_FEATURE_V6, 1745 ARM_FEATURE_V6K, 1746 ARM_FEATURE_V7, 1747 ARM_FEATURE_THUMB2, 1748 ARM_FEATURE_PMSA, /* no MMU; may have Memory Protection Unit */ 1749 ARM_FEATURE_VFP3, 1750 ARM_FEATURE_VFP_FP16, 1751 ARM_FEATURE_NEON, 1752 ARM_FEATURE_M, /* Microcontroller profile. */ 1753 ARM_FEATURE_OMAPCP, /* OMAP specific CP15 ops handling. */ 1754 ARM_FEATURE_THUMB2EE, 1755 ARM_FEATURE_V7MP, /* v7 Multiprocessing Extensions */ 1756 ARM_FEATURE_V7VE, /* v7 Virtualization Extensions (non-EL2 parts) */ 1757 ARM_FEATURE_V4T, 1758 ARM_FEATURE_V5, 1759 ARM_FEATURE_STRONGARM, 1760 ARM_FEATURE_VAPA, /* cp15 VA to PA lookups */ 1761 ARM_FEATURE_VFP4, /* VFPv4 (implies that NEON is v2) */ 1762 ARM_FEATURE_GENERIC_TIMER, 1763 ARM_FEATURE_MVFR, /* Media and VFP Feature Registers 0 and 1 */ 1764 ARM_FEATURE_DUMMY_C15_REGS, /* RAZ/WI all of cp15 crn=15 */ 1765 ARM_FEATURE_CACHE_TEST_CLEAN, /* 926/1026 style test-and-clean ops */ 1766 ARM_FEATURE_CACHE_DIRTY_REG, /* 1136/1176 cache dirty status register */ 1767 ARM_FEATURE_CACHE_BLOCK_OPS, /* v6 optional cache block operations */ 1768 ARM_FEATURE_MPIDR, /* has cp15 MPIDR */ 1769 ARM_FEATURE_PXN, /* has Privileged Execute Never bit */ 1770 ARM_FEATURE_LPAE, /* has Large Physical Address Extension */ 1771 ARM_FEATURE_V8, 1772 ARM_FEATURE_AARCH64, /* supports 64 bit mode */ 1773 ARM_FEATURE_CBAR, /* has cp15 CBAR */ 1774 ARM_FEATURE_CRC, /* ARMv8 CRC instructions */ 1775 ARM_FEATURE_CBAR_RO, /* has cp15 CBAR and it is read-only */ 1776 ARM_FEATURE_EL2, /* has EL2 Virtualization support */ 1777 ARM_FEATURE_EL3, /* has EL3 Secure monitor support */ 1778 ARM_FEATURE_THUMB_DSP, /* DSP insns supported in the Thumb encodings */ 1779 ARM_FEATURE_PMU, /* has PMU support */ 1780 ARM_FEATURE_VBAR, /* has cp15 VBAR */ 1781 ARM_FEATURE_M_SECURITY, /* M profile Security Extension */ 1782 ARM_FEATURE_M_MAIN, /* M profile Main Extension */ 1783 }; 1784 1785 static inline int arm_feature(CPUARMState *env, int feature) 1786 { 1787 return (env->features & (1ULL << feature)) != 0; 1788 } 1789 1790 #if !defined(CONFIG_USER_ONLY) 1791 /* Return true if exception levels below EL3 are in secure state, 1792 * or would be following an exception return to that level. 1793 * Unlike arm_is_secure() (which is always a question about the 1794 * _current_ state of the CPU) this doesn't care about the current 1795 * EL or mode. 1796 */ 1797 static inline bool arm_is_secure_below_el3(CPUARMState *env) 1798 { 1799 if (arm_feature(env, ARM_FEATURE_EL3)) { 1800 return !(env->cp15.scr_el3 & SCR_NS); 1801 } else { 1802 /* If EL3 is not supported then the secure state is implementation 1803 * defined, in which case QEMU defaults to non-secure. 1804 */ 1805 return false; 1806 } 1807 } 1808 1809 /* Return true if the CPU is AArch64 EL3 or AArch32 Mon */ 1810 static inline bool arm_is_el3_or_mon(CPUARMState *env) 1811 { 1812 if (arm_feature(env, ARM_FEATURE_EL3)) { 1813 if (is_a64(env) && extract32(env->pstate, 2, 2) == 3) { 1814 /* CPU currently in AArch64 state and EL3 */ 1815 return true; 1816 } else if (!is_a64(env) && 1817 (env->uncached_cpsr & CPSR_M) == ARM_CPU_MODE_MON) { 1818 /* CPU currently in AArch32 state and monitor mode */ 1819 return true; 1820 } 1821 } 1822 return false; 1823 } 1824 1825 /* Return true if the processor is in secure state */ 1826 static inline bool arm_is_secure(CPUARMState *env) 1827 { 1828 if (arm_is_el3_or_mon(env)) { 1829 return true; 1830 } 1831 return arm_is_secure_below_el3(env); 1832 } 1833 1834 #else 1835 static inline bool arm_is_secure_below_el3(CPUARMState *env) 1836 { 1837 return false; 1838 } 1839 1840 static inline bool arm_is_secure(CPUARMState *env) 1841 { 1842 return false; 1843 } 1844 #endif 1845 1846 /** 1847 * arm_hcr_el2_eff(): Return the effective value of HCR_EL2. 1848 * E.g. when in secure state, fields in HCR_EL2 are suppressed, 1849 * "for all purposes other than a direct read or write access of HCR_EL2." 1850 * Not included here is HCR_RW. 1851 */ 1852 uint64_t arm_hcr_el2_eff(CPUARMState *env); 1853 1854 /* Return true if the specified exception level is running in AArch64 state. */ 1855 static inline bool arm_el_is_aa64(CPUARMState *env, int el) 1856 { 1857 /* This isn't valid for EL0 (if we're in EL0, is_a64() is what you want, 1858 * and if we're not in EL0 then the state of EL0 isn't well defined.) 1859 */ 1860 assert(el >= 1 && el <= 3); 1861 bool aa64 = arm_feature(env, ARM_FEATURE_AARCH64); 1862 1863 /* The highest exception level is always at the maximum supported 1864 * register width, and then lower levels have a register width controlled 1865 * by bits in the SCR or HCR registers. 1866 */ 1867 if (el == 3) { 1868 return aa64; 1869 } 1870 1871 if (arm_feature(env, ARM_FEATURE_EL3)) { 1872 aa64 = aa64 && (env->cp15.scr_el3 & SCR_RW); 1873 } 1874 1875 if (el == 2) { 1876 return aa64; 1877 } 1878 1879 if (arm_feature(env, ARM_FEATURE_EL2) && !arm_is_secure_below_el3(env)) { 1880 aa64 = aa64 && (env->cp15.hcr_el2 & HCR_RW); 1881 } 1882 1883 return aa64; 1884 } 1885 1886 /* Function for determing whether guest cp register reads and writes should 1887 * access the secure or non-secure bank of a cp register. When EL3 is 1888 * operating in AArch32 state, the NS-bit determines whether the secure 1889 * instance of a cp register should be used. When EL3 is AArch64 (or if 1890 * it doesn't exist at all) then there is no register banking, and all 1891 * accesses are to the non-secure version. 1892 */ 1893 static inline bool access_secure_reg(CPUARMState *env) 1894 { 1895 bool ret = (arm_feature(env, ARM_FEATURE_EL3) && 1896 !arm_el_is_aa64(env, 3) && 1897 !(env->cp15.scr_el3 & SCR_NS)); 1898 1899 return ret; 1900 } 1901 1902 /* Macros for accessing a specified CP register bank */ 1903 #define A32_BANKED_REG_GET(_env, _regname, _secure) \ 1904 ((_secure) ? (_env)->cp15._regname##_s : (_env)->cp15._regname##_ns) 1905 1906 #define A32_BANKED_REG_SET(_env, _regname, _secure, _val) \ 1907 do { \ 1908 if (_secure) { \ 1909 (_env)->cp15._regname##_s = (_val); \ 1910 } else { \ 1911 (_env)->cp15._regname##_ns = (_val); \ 1912 } \ 1913 } while (0) 1914 1915 /* Macros for automatically accessing a specific CP register bank depending on 1916 * the current secure state of the system. These macros are not intended for 1917 * supporting instruction translation reads/writes as these are dependent 1918 * solely on the SCR.NS bit and not the mode. 1919 */ 1920 #define A32_BANKED_CURRENT_REG_GET(_env, _regname) \ 1921 A32_BANKED_REG_GET((_env), _regname, \ 1922 (arm_is_secure(_env) && !arm_el_is_aa64((_env), 3))) 1923 1924 #define A32_BANKED_CURRENT_REG_SET(_env, _regname, _val) \ 1925 A32_BANKED_REG_SET((_env), _regname, \ 1926 (arm_is_secure(_env) && !arm_el_is_aa64((_env), 3)), \ 1927 (_val)) 1928 1929 void arm_cpu_list(FILE *f, fprintf_function cpu_fprintf); 1930 uint32_t arm_phys_excp_target_el(CPUState *cs, uint32_t excp_idx, 1931 uint32_t cur_el, bool secure); 1932 1933 /* Interface between CPU and Interrupt controller. */ 1934 #ifndef CONFIG_USER_ONLY 1935 bool armv7m_nvic_can_take_pending_exception(void *opaque); 1936 #else 1937 static inline bool armv7m_nvic_can_take_pending_exception(void *opaque) 1938 { 1939 return true; 1940 } 1941 #endif 1942 /** 1943 * armv7m_nvic_set_pending: mark the specified exception as pending 1944 * @opaque: the NVIC 1945 * @irq: the exception number to mark pending 1946 * @secure: false for non-banked exceptions or for the nonsecure 1947 * version of a banked exception, true for the secure version of a banked 1948 * exception. 1949 * 1950 * Marks the specified exception as pending. Note that we will assert() 1951 * if @secure is true and @irq does not specify one of the fixed set 1952 * of architecturally banked exceptions. 1953 */ 1954 void armv7m_nvic_set_pending(void *opaque, int irq, bool secure); 1955 /** 1956 * armv7m_nvic_set_pending_derived: mark this derived exception as pending 1957 * @opaque: the NVIC 1958 * @irq: the exception number to mark pending 1959 * @secure: false for non-banked exceptions or for the nonsecure 1960 * version of a banked exception, true for the secure version of a banked 1961 * exception. 1962 * 1963 * Similar to armv7m_nvic_set_pending(), but specifically for derived 1964 * exceptions (exceptions generated in the course of trying to take 1965 * a different exception). 1966 */ 1967 void armv7m_nvic_set_pending_derived(void *opaque, int irq, bool secure); 1968 /** 1969 * armv7m_nvic_get_pending_irq_info: return highest priority pending 1970 * exception, and whether it targets Secure state 1971 * @opaque: the NVIC 1972 * @pirq: set to pending exception number 1973 * @ptargets_secure: set to whether pending exception targets Secure 1974 * 1975 * This function writes the number of the highest priority pending 1976 * exception (the one which would be made active by 1977 * armv7m_nvic_acknowledge_irq()) to @pirq, and sets @ptargets_secure 1978 * to true if the current highest priority pending exception should 1979 * be taken to Secure state, false for NS. 1980 */ 1981 void armv7m_nvic_get_pending_irq_info(void *opaque, int *pirq, 1982 bool *ptargets_secure); 1983 /** 1984 * armv7m_nvic_acknowledge_irq: make highest priority pending exception active 1985 * @opaque: the NVIC 1986 * 1987 * Move the current highest priority pending exception from the pending 1988 * state to the active state, and update v7m.exception to indicate that 1989 * it is the exception currently being handled. 1990 */ 1991 void armv7m_nvic_acknowledge_irq(void *opaque); 1992 /** 1993 * armv7m_nvic_complete_irq: complete specified interrupt or exception 1994 * @opaque: the NVIC 1995 * @irq: the exception number to complete 1996 * @secure: true if this exception was secure 1997 * 1998 * Returns: -1 if the irq was not active 1999 * 1 if completing this irq brought us back to base (no active irqs) 2000 * 0 if there is still an irq active after this one was completed 2001 * (Ignoring -1, this is the same as the RETTOBASE value before completion.) 2002 */ 2003 int armv7m_nvic_complete_irq(void *opaque, int irq, bool secure); 2004 /** 2005 * armv7m_nvic_raw_execution_priority: return the raw execution priority 2006 * @opaque: the NVIC 2007 * 2008 * Returns: the raw execution priority as defined by the v8M architecture. 2009 * This is the execution priority minus the effects of AIRCR.PRIS, 2010 * and minus any PRIMASK/FAULTMASK/BASEPRI priority boosting. 2011 * (v8M ARM ARM I_PKLD.) 2012 */ 2013 int armv7m_nvic_raw_execution_priority(void *opaque); 2014 /** 2015 * armv7m_nvic_neg_prio_requested: return true if the requested execution 2016 * priority is negative for the specified security state. 2017 * @opaque: the NVIC 2018 * @secure: the security state to test 2019 * This corresponds to the pseudocode IsReqExecPriNeg(). 2020 */ 2021 #ifndef CONFIG_USER_ONLY 2022 bool armv7m_nvic_neg_prio_requested(void *opaque, bool secure); 2023 #else 2024 static inline bool armv7m_nvic_neg_prio_requested(void *opaque, bool secure) 2025 { 2026 return false; 2027 } 2028 #endif 2029 2030 /* Interface for defining coprocessor registers. 2031 * Registers are defined in tables of arm_cp_reginfo structs 2032 * which are passed to define_arm_cp_regs(). 2033 */ 2034 2035 /* When looking up a coprocessor register we look for it 2036 * via an integer which encodes all of: 2037 * coprocessor number 2038 * Crn, Crm, opc1, opc2 fields 2039 * 32 or 64 bit register (ie is it accessed via MRC/MCR 2040 * or via MRRC/MCRR?) 2041 * non-secure/secure bank (AArch32 only) 2042 * We allow 4 bits for opc1 because MRRC/MCRR have a 4 bit field. 2043 * (In this case crn and opc2 should be zero.) 2044 * For AArch64, there is no 32/64 bit size distinction; 2045 * instead all registers have a 2 bit op0, 3 bit op1 and op2, 2046 * and 4 bit CRn and CRm. The encoding patterns are chosen 2047 * to be easy to convert to and from the KVM encodings, and also 2048 * so that the hashtable can contain both AArch32 and AArch64 2049 * registers (to allow for interprocessing where we might run 2050 * 32 bit code on a 64 bit core). 2051 */ 2052 /* This bit is private to our hashtable cpreg; in KVM register 2053 * IDs the AArch64/32 distinction is the KVM_REG_ARM/ARM64 2054 * in the upper bits of the 64 bit ID. 2055 */ 2056 #define CP_REG_AA64_SHIFT 28 2057 #define CP_REG_AA64_MASK (1 << CP_REG_AA64_SHIFT) 2058 2059 /* To enable banking of coprocessor registers depending on ns-bit we 2060 * add a bit to distinguish between secure and non-secure cpregs in the 2061 * hashtable. 2062 */ 2063 #define CP_REG_NS_SHIFT 29 2064 #define CP_REG_NS_MASK (1 << CP_REG_NS_SHIFT) 2065 2066 #define ENCODE_CP_REG(cp, is64, ns, crn, crm, opc1, opc2) \ 2067 ((ns) << CP_REG_NS_SHIFT | ((cp) << 16) | ((is64) << 15) | \ 2068 ((crn) << 11) | ((crm) << 7) | ((opc1) << 3) | (opc2)) 2069 2070 #define ENCODE_AA64_CP_REG(cp, crn, crm, op0, op1, op2) \ 2071 (CP_REG_AA64_MASK | \ 2072 ((cp) << CP_REG_ARM_COPROC_SHIFT) | \ 2073 ((op0) << CP_REG_ARM64_SYSREG_OP0_SHIFT) | \ 2074 ((op1) << CP_REG_ARM64_SYSREG_OP1_SHIFT) | \ 2075 ((crn) << CP_REG_ARM64_SYSREG_CRN_SHIFT) | \ 2076 ((crm) << CP_REG_ARM64_SYSREG_CRM_SHIFT) | \ 2077 ((op2) << CP_REG_ARM64_SYSREG_OP2_SHIFT)) 2078 2079 /* Convert a full 64 bit KVM register ID to the truncated 32 bit 2080 * version used as a key for the coprocessor register hashtable 2081 */ 2082 static inline uint32_t kvm_to_cpreg_id(uint64_t kvmid) 2083 { 2084 uint32_t cpregid = kvmid; 2085 if ((kvmid & CP_REG_ARCH_MASK) == CP_REG_ARM64) { 2086 cpregid |= CP_REG_AA64_MASK; 2087 } else { 2088 if ((kvmid & CP_REG_SIZE_MASK) == CP_REG_SIZE_U64) { 2089 cpregid |= (1 << 15); 2090 } 2091 2092 /* KVM is always non-secure so add the NS flag on AArch32 register 2093 * entries. 2094 */ 2095 cpregid |= 1 << CP_REG_NS_SHIFT; 2096 } 2097 return cpregid; 2098 } 2099 2100 /* Convert a truncated 32 bit hashtable key into the full 2101 * 64 bit KVM register ID. 2102 */ 2103 static inline uint64_t cpreg_to_kvm_id(uint32_t cpregid) 2104 { 2105 uint64_t kvmid; 2106 2107 if (cpregid & CP_REG_AA64_MASK) { 2108 kvmid = cpregid & ~CP_REG_AA64_MASK; 2109 kvmid |= CP_REG_SIZE_U64 | CP_REG_ARM64; 2110 } else { 2111 kvmid = cpregid & ~(1 << 15); 2112 if (cpregid & (1 << 15)) { 2113 kvmid |= CP_REG_SIZE_U64 | CP_REG_ARM; 2114 } else { 2115 kvmid |= CP_REG_SIZE_U32 | CP_REG_ARM; 2116 } 2117 } 2118 return kvmid; 2119 } 2120 2121 /* ARMCPRegInfo type field bits. If the SPECIAL bit is set this is a 2122 * special-behaviour cp reg and bits [11..8] indicate what behaviour 2123 * it has. Otherwise it is a simple cp reg, where CONST indicates that 2124 * TCG can assume the value to be constant (ie load at translate time) 2125 * and 64BIT indicates a 64 bit wide coprocessor register. SUPPRESS_TB_END 2126 * indicates that the TB should not be ended after a write to this register 2127 * (the default is that the TB ends after cp writes). OVERRIDE permits 2128 * a register definition to override a previous definition for the 2129 * same (cp, is64, crn, crm, opc1, opc2) tuple: either the new or the 2130 * old must have the OVERRIDE bit set. 2131 * ALIAS indicates that this register is an alias view of some underlying 2132 * state which is also visible via another register, and that the other 2133 * register is handling migration and reset; registers marked ALIAS will not be 2134 * migrated but may have their state set by syncing of register state from KVM. 2135 * NO_RAW indicates that this register has no underlying state and does not 2136 * support raw access for state saving/loading; it will not be used for either 2137 * migration or KVM state synchronization. (Typically this is for "registers" 2138 * which are actually used as instructions for cache maintenance and so on.) 2139 * IO indicates that this register does I/O and therefore its accesses 2140 * need to be surrounded by gen_io_start()/gen_io_end(). In particular, 2141 * registers which implement clocks or timers require this. 2142 */ 2143 #define ARM_CP_SPECIAL 0x0001 2144 #define ARM_CP_CONST 0x0002 2145 #define ARM_CP_64BIT 0x0004 2146 #define ARM_CP_SUPPRESS_TB_END 0x0008 2147 #define ARM_CP_OVERRIDE 0x0010 2148 #define ARM_CP_ALIAS 0x0020 2149 #define ARM_CP_IO 0x0040 2150 #define ARM_CP_NO_RAW 0x0080 2151 #define ARM_CP_NOP (ARM_CP_SPECIAL | 0x0100) 2152 #define ARM_CP_WFI (ARM_CP_SPECIAL | 0x0200) 2153 #define ARM_CP_NZCV (ARM_CP_SPECIAL | 0x0300) 2154 #define ARM_CP_CURRENTEL (ARM_CP_SPECIAL | 0x0400) 2155 #define ARM_CP_DC_ZVA (ARM_CP_SPECIAL | 0x0500) 2156 #define ARM_LAST_SPECIAL ARM_CP_DC_ZVA 2157 #define ARM_CP_FPU 0x1000 2158 #define ARM_CP_SVE 0x2000 2159 #define ARM_CP_NO_GDB 0x4000 2160 /* Used only as a terminator for ARMCPRegInfo lists */ 2161 #define ARM_CP_SENTINEL 0xffff 2162 /* Mask of only the flag bits in a type field */ 2163 #define ARM_CP_FLAG_MASK 0x70ff 2164 2165 /* Valid values for ARMCPRegInfo state field, indicating which of 2166 * the AArch32 and AArch64 execution states this register is visible in. 2167 * If the reginfo doesn't explicitly specify then it is AArch32 only. 2168 * If the reginfo is declared to be visible in both states then a second 2169 * reginfo is synthesised for the AArch32 view of the AArch64 register, 2170 * such that the AArch32 view is the lower 32 bits of the AArch64 one. 2171 * Note that we rely on the values of these enums as we iterate through 2172 * the various states in some places. 2173 */ 2174 enum { 2175 ARM_CP_STATE_AA32 = 0, 2176 ARM_CP_STATE_AA64 = 1, 2177 ARM_CP_STATE_BOTH = 2, 2178 }; 2179 2180 /* ARM CP register secure state flags. These flags identify security state 2181 * attributes for a given CP register entry. 2182 * The existence of both or neither secure and non-secure flags indicates that 2183 * the register has both a secure and non-secure hash entry. A single one of 2184 * these flags causes the register to only be hashed for the specified 2185 * security state. 2186 * Although definitions may have any combination of the S/NS bits, each 2187 * registered entry will only have one to identify whether the entry is secure 2188 * or non-secure. 2189 */ 2190 enum { 2191 ARM_CP_SECSTATE_S = (1 << 0), /* bit[0]: Secure state register */ 2192 ARM_CP_SECSTATE_NS = (1 << 1), /* bit[1]: Non-secure state register */ 2193 }; 2194 2195 /* Return true if cptype is a valid type field. This is used to try to 2196 * catch errors where the sentinel has been accidentally left off the end 2197 * of a list of registers. 2198 */ 2199 static inline bool cptype_valid(int cptype) 2200 { 2201 return ((cptype & ~ARM_CP_FLAG_MASK) == 0) 2202 || ((cptype & ARM_CP_SPECIAL) && 2203 ((cptype & ~ARM_CP_FLAG_MASK) <= ARM_LAST_SPECIAL)); 2204 } 2205 2206 /* Access rights: 2207 * We define bits for Read and Write access for what rev C of the v7-AR ARM ARM 2208 * defines as PL0 (user), PL1 (fiq/irq/svc/abt/und/sys, ie privileged), and 2209 * PL2 (hyp). The other level which has Read and Write bits is Secure PL1 2210 * (ie any of the privileged modes in Secure state, or Monitor mode). 2211 * If a register is accessible in one privilege level it's always accessible 2212 * in higher privilege levels too. Since "Secure PL1" also follows this rule 2213 * (ie anything visible in PL2 is visible in S-PL1, some things are only 2214 * visible in S-PL1) but "Secure PL1" is a bit of a mouthful, we bend the 2215 * terminology a little and call this PL3. 2216 * In AArch64 things are somewhat simpler as the PLx bits line up exactly 2217 * with the ELx exception levels. 2218 * 2219 * If access permissions for a register are more complex than can be 2220 * described with these bits, then use a laxer set of restrictions, and 2221 * do the more restrictive/complex check inside a helper function. 2222 */ 2223 #define PL3_R 0x80 2224 #define PL3_W 0x40 2225 #define PL2_R (0x20 | PL3_R) 2226 #define PL2_W (0x10 | PL3_W) 2227 #define PL1_R (0x08 | PL2_R) 2228 #define PL1_W (0x04 | PL2_W) 2229 #define PL0_R (0x02 | PL1_R) 2230 #define PL0_W (0x01 | PL1_W) 2231 2232 /* 2233 * For user-mode some registers are accessible to EL0 via a kernel 2234 * trap-and-emulate ABI. In this case we define the read permissions 2235 * as actually being PL0_R. However some bits of any given register 2236 * may still be masked. 2237 */ 2238 #ifdef CONFIG_USER_ONLY 2239 #define PL0U_R PL0_R 2240 #else 2241 #define PL0U_R PL1_R 2242 #endif 2243 2244 #define PL3_RW (PL3_R | PL3_W) 2245 #define PL2_RW (PL2_R | PL2_W) 2246 #define PL1_RW (PL1_R | PL1_W) 2247 #define PL0_RW (PL0_R | PL0_W) 2248 2249 /* Return the highest implemented Exception Level */ 2250 static inline int arm_highest_el(CPUARMState *env) 2251 { 2252 if (arm_feature(env, ARM_FEATURE_EL3)) { 2253 return 3; 2254 } 2255 if (arm_feature(env, ARM_FEATURE_EL2)) { 2256 return 2; 2257 } 2258 return 1; 2259 } 2260 2261 /* Return true if a v7M CPU is in Handler mode */ 2262 static inline bool arm_v7m_is_handler_mode(CPUARMState *env) 2263 { 2264 return env->v7m.exception != 0; 2265 } 2266 2267 /* Return the current Exception Level (as per ARMv8; note that this differs 2268 * from the ARMv7 Privilege Level). 2269 */ 2270 static inline int arm_current_el(CPUARMState *env) 2271 { 2272 if (arm_feature(env, ARM_FEATURE_M)) { 2273 return arm_v7m_is_handler_mode(env) || 2274 !(env->v7m.control[env->v7m.secure] & 1); 2275 } 2276 2277 if (is_a64(env)) { 2278 return extract32(env->pstate, 2, 2); 2279 } 2280 2281 switch (env->uncached_cpsr & 0x1f) { 2282 case ARM_CPU_MODE_USR: 2283 return 0; 2284 case ARM_CPU_MODE_HYP: 2285 return 2; 2286 case ARM_CPU_MODE_MON: 2287 return 3; 2288 default: 2289 if (arm_is_secure(env) && !arm_el_is_aa64(env, 3)) { 2290 /* If EL3 is 32-bit then all secure privileged modes run in 2291 * EL3 2292 */ 2293 return 3; 2294 } 2295 2296 return 1; 2297 } 2298 } 2299 2300 typedef struct ARMCPRegInfo ARMCPRegInfo; 2301 2302 typedef enum CPAccessResult { 2303 /* Access is permitted */ 2304 CP_ACCESS_OK = 0, 2305 /* Access fails due to a configurable trap or enable which would 2306 * result in a categorized exception syndrome giving information about 2307 * the failing instruction (ie syndrome category 0x3, 0x4, 0x5, 0x6, 2308 * 0xc or 0x18). The exception is taken to the usual target EL (EL1 or 2309 * PL1 if in EL0, otherwise to the current EL). 2310 */ 2311 CP_ACCESS_TRAP = 1, 2312 /* Access fails and results in an exception syndrome 0x0 ("uncategorized"). 2313 * Note that this is not a catch-all case -- the set of cases which may 2314 * result in this failure is specifically defined by the architecture. 2315 */ 2316 CP_ACCESS_TRAP_UNCATEGORIZED = 2, 2317 /* As CP_ACCESS_TRAP, but for traps directly to EL2 or EL3 */ 2318 CP_ACCESS_TRAP_EL2 = 3, 2319 CP_ACCESS_TRAP_EL3 = 4, 2320 /* As CP_ACCESS_UNCATEGORIZED, but for traps directly to EL2 or EL3 */ 2321 CP_ACCESS_TRAP_UNCATEGORIZED_EL2 = 5, 2322 CP_ACCESS_TRAP_UNCATEGORIZED_EL3 = 6, 2323 /* Access fails and results in an exception syndrome for an FP access, 2324 * trapped directly to EL2 or EL3 2325 */ 2326 CP_ACCESS_TRAP_FP_EL2 = 7, 2327 CP_ACCESS_TRAP_FP_EL3 = 8, 2328 } CPAccessResult; 2329 2330 /* Access functions for coprocessor registers. These cannot fail and 2331 * may not raise exceptions. 2332 */ 2333 typedef uint64_t CPReadFn(CPUARMState *env, const ARMCPRegInfo *opaque); 2334 typedef void CPWriteFn(CPUARMState *env, const ARMCPRegInfo *opaque, 2335 uint64_t value); 2336 /* Access permission check functions for coprocessor registers. */ 2337 typedef CPAccessResult CPAccessFn(CPUARMState *env, 2338 const ARMCPRegInfo *opaque, 2339 bool isread); 2340 /* Hook function for register reset */ 2341 typedef void CPResetFn(CPUARMState *env, const ARMCPRegInfo *opaque); 2342 2343 #define CP_ANY 0xff 2344 2345 /* Definition of an ARM coprocessor register */ 2346 struct ARMCPRegInfo { 2347 /* Name of register (useful mainly for debugging, need not be unique) */ 2348 const char *name; 2349 /* Location of register: coprocessor number and (crn,crm,opc1,opc2) 2350 * tuple. Any of crm, opc1 and opc2 may be CP_ANY to indicate a 2351 * 'wildcard' field -- any value of that field in the MRC/MCR insn 2352 * will be decoded to this register. The register read and write 2353 * callbacks will be passed an ARMCPRegInfo with the crn/crm/opc1/opc2 2354 * used by the program, so it is possible to register a wildcard and 2355 * then behave differently on read/write if necessary. 2356 * For 64 bit registers, only crm and opc1 are relevant; crn and opc2 2357 * must both be zero. 2358 * For AArch64-visible registers, opc0 is also used. 2359 * Since there are no "coprocessors" in AArch64, cp is purely used as a 2360 * way to distinguish (for KVM's benefit) guest-visible system registers 2361 * from demuxed ones provided to preserve the "no side effects on 2362 * KVM register read/write from QEMU" semantics. cp==0x13 is guest 2363 * visible (to match KVM's encoding); cp==0 will be converted to 2364 * cp==0x13 when the ARMCPRegInfo is registered, for convenience. 2365 */ 2366 uint8_t cp; 2367 uint8_t crn; 2368 uint8_t crm; 2369 uint8_t opc0; 2370 uint8_t opc1; 2371 uint8_t opc2; 2372 /* Execution state in which this register is visible: ARM_CP_STATE_* */ 2373 int state; 2374 /* Register type: ARM_CP_* bits/values */ 2375 int type; 2376 /* Access rights: PL*_[RW] */ 2377 int access; 2378 /* Security state: ARM_CP_SECSTATE_* bits/values */ 2379 int secure; 2380 /* The opaque pointer passed to define_arm_cp_regs_with_opaque() when 2381 * this register was defined: can be used to hand data through to the 2382 * register read/write functions, since they are passed the ARMCPRegInfo*. 2383 */ 2384 void *opaque; 2385 /* Value of this register, if it is ARM_CP_CONST. Otherwise, if 2386 * fieldoffset is non-zero, the reset value of the register. 2387 */ 2388 uint64_t resetvalue; 2389 /* Offset of the field in CPUARMState for this register. 2390 * 2391 * This is not needed if either: 2392 * 1. type is ARM_CP_CONST or one of the ARM_CP_SPECIALs 2393 * 2. both readfn and writefn are specified 2394 */ 2395 ptrdiff_t fieldoffset; /* offsetof(CPUARMState, field) */ 2396 2397 /* Offsets of the secure and non-secure fields in CPUARMState for the 2398 * register if it is banked. These fields are only used during the static 2399 * registration of a register. During hashing the bank associated 2400 * with a given security state is copied to fieldoffset which is used from 2401 * there on out. 2402 * 2403 * It is expected that register definitions use either fieldoffset or 2404 * bank_fieldoffsets in the definition but not both. It is also expected 2405 * that both bank offsets are set when defining a banked register. This 2406 * use indicates that a register is banked. 2407 */ 2408 ptrdiff_t bank_fieldoffsets[2]; 2409 2410 /* Function for making any access checks for this register in addition to 2411 * those specified by the 'access' permissions bits. If NULL, no extra 2412 * checks required. The access check is performed at runtime, not at 2413 * translate time. 2414 */ 2415 CPAccessFn *accessfn; 2416 /* Function for handling reads of this register. If NULL, then reads 2417 * will be done by loading from the offset into CPUARMState specified 2418 * by fieldoffset. 2419 */ 2420 CPReadFn *readfn; 2421 /* Function for handling writes of this register. If NULL, then writes 2422 * will be done by writing to the offset into CPUARMState specified 2423 * by fieldoffset. 2424 */ 2425 CPWriteFn *writefn; 2426 /* Function for doing a "raw" read; used when we need to copy 2427 * coprocessor state to the kernel for KVM or out for 2428 * migration. This only needs to be provided if there is also a 2429 * readfn and it has side effects (for instance clear-on-read bits). 2430 */ 2431 CPReadFn *raw_readfn; 2432 /* Function for doing a "raw" write; used when we need to copy KVM 2433 * kernel coprocessor state into userspace, or for inbound 2434 * migration. This only needs to be provided if there is also a 2435 * writefn and it masks out "unwritable" bits or has write-one-to-clear 2436 * or similar behaviour. 2437 */ 2438 CPWriteFn *raw_writefn; 2439 /* Function for resetting the register. If NULL, then reset will be done 2440 * by writing resetvalue to the field specified in fieldoffset. If 2441 * fieldoffset is 0 then no reset will be done. 2442 */ 2443 CPResetFn *resetfn; 2444 }; 2445 2446 /* Macros which are lvalues for the field in CPUARMState for the 2447 * ARMCPRegInfo *ri. 2448 */ 2449 #define CPREG_FIELD32(env, ri) \ 2450 (*(uint32_t *)((char *)(env) + (ri)->fieldoffset)) 2451 #define CPREG_FIELD64(env, ri) \ 2452 (*(uint64_t *)((char *)(env) + (ri)->fieldoffset)) 2453 2454 #define REGINFO_SENTINEL { .type = ARM_CP_SENTINEL } 2455 2456 void define_arm_cp_regs_with_opaque(ARMCPU *cpu, 2457 const ARMCPRegInfo *regs, void *opaque); 2458 void define_one_arm_cp_reg_with_opaque(ARMCPU *cpu, 2459 const ARMCPRegInfo *regs, void *opaque); 2460 static inline void define_arm_cp_regs(ARMCPU *cpu, const ARMCPRegInfo *regs) 2461 { 2462 define_arm_cp_regs_with_opaque(cpu, regs, 0); 2463 } 2464 static inline void define_one_arm_cp_reg(ARMCPU *cpu, const ARMCPRegInfo *regs) 2465 { 2466 define_one_arm_cp_reg_with_opaque(cpu, regs, 0); 2467 } 2468 const ARMCPRegInfo *get_arm_cp_reginfo(GHashTable *cpregs, uint32_t encoded_cp); 2469 2470 /* 2471 * Definition of an ARM co-processor register as viewed from 2472 * userspace. This is used for presenting sanitised versions of 2473 * registers to userspace when emulating the Linux AArch64 CPU 2474 * ID/feature ABI (advertised as HWCAP_CPUID). 2475 */ 2476 typedef struct ARMCPRegUserSpaceInfo { 2477 /* Name of register */ 2478 const char *name; 2479 2480 /* Is the name actually a glob pattern */ 2481 bool is_glob; 2482 2483 /* Only some bits are exported to user space */ 2484 uint64_t exported_bits; 2485 2486 /* Fixed bits are applied after the mask */ 2487 uint64_t fixed_bits; 2488 } ARMCPRegUserSpaceInfo; 2489 2490 #define REGUSERINFO_SENTINEL { .name = NULL } 2491 2492 void modify_arm_cp_regs(ARMCPRegInfo *regs, const ARMCPRegUserSpaceInfo *mods); 2493 2494 /* CPWriteFn that can be used to implement writes-ignored behaviour */ 2495 void arm_cp_write_ignore(CPUARMState *env, const ARMCPRegInfo *ri, 2496 uint64_t value); 2497 /* CPReadFn that can be used for read-as-zero behaviour */ 2498 uint64_t arm_cp_read_zero(CPUARMState *env, const ARMCPRegInfo *ri); 2499 2500 /* CPResetFn that does nothing, for use if no reset is required even 2501 * if fieldoffset is non zero. 2502 */ 2503 void arm_cp_reset_ignore(CPUARMState *env, const ARMCPRegInfo *opaque); 2504 2505 /* Return true if this reginfo struct's field in the cpu state struct 2506 * is 64 bits wide. 2507 */ 2508 static inline bool cpreg_field_is_64bit(const ARMCPRegInfo *ri) 2509 { 2510 return (ri->state == ARM_CP_STATE_AA64) || (ri->type & ARM_CP_64BIT); 2511 } 2512 2513 static inline bool cp_access_ok(int current_el, 2514 const ARMCPRegInfo *ri, int isread) 2515 { 2516 return (ri->access >> ((current_el * 2) + isread)) & 1; 2517 } 2518 2519 /* Raw read of a coprocessor register (as needed for migration, etc) */ 2520 uint64_t read_raw_cp_reg(CPUARMState *env, const ARMCPRegInfo *ri); 2521 2522 /** 2523 * write_list_to_cpustate 2524 * @cpu: ARMCPU 2525 * 2526 * For each register listed in the ARMCPU cpreg_indexes list, write 2527 * its value from the cpreg_values list into the ARMCPUState structure. 2528 * This updates TCG's working data structures from KVM data or 2529 * from incoming migration state. 2530 * 2531 * Returns: true if all register values were updated correctly, 2532 * false if some register was unknown or could not be written. 2533 * Note that we do not stop early on failure -- we will attempt 2534 * writing all registers in the list. 2535 */ 2536 bool write_list_to_cpustate(ARMCPU *cpu); 2537 2538 /** 2539 * write_cpustate_to_list: 2540 * @cpu: ARMCPU 2541 * @kvm_sync: true if this is for syncing back to KVM 2542 * 2543 * For each register listed in the ARMCPU cpreg_indexes list, write 2544 * its value from the ARMCPUState structure into the cpreg_values list. 2545 * This is used to copy info from TCG's working data structures into 2546 * KVM or for outbound migration. 2547 * 2548 * @kvm_sync is true if we are doing this in order to sync the 2549 * register state back to KVM. In this case we will only update 2550 * values in the list if the previous list->cpustate sync actually 2551 * successfully wrote the CPU state. Otherwise we will keep the value 2552 * that is in the list. 2553 * 2554 * Returns: true if all register values were read correctly, 2555 * false if some register was unknown or could not be read. 2556 * Note that we do not stop early on failure -- we will attempt 2557 * reading all registers in the list. 2558 */ 2559 bool write_cpustate_to_list(ARMCPU *cpu, bool kvm_sync); 2560 2561 #define ARM_CPUID_TI915T 0x54029152 2562 #define ARM_CPUID_TI925T 0x54029252 2563 2564 #if defined(CONFIG_USER_ONLY) 2565 #define TARGET_PAGE_BITS 12 2566 #else 2567 /* ARMv7 and later CPUs have 4K pages minimum, but ARMv5 and v6 2568 * have to support 1K tiny pages. 2569 */ 2570 #define TARGET_PAGE_BITS_VARY 2571 #define TARGET_PAGE_BITS_MIN 10 2572 #endif 2573 2574 #if defined(TARGET_AARCH64) 2575 # define TARGET_PHYS_ADDR_SPACE_BITS 48 2576 # define TARGET_VIRT_ADDR_SPACE_BITS 48 2577 #else 2578 # define TARGET_PHYS_ADDR_SPACE_BITS 40 2579 # define TARGET_VIRT_ADDR_SPACE_BITS 32 2580 #endif 2581 2582 static inline bool arm_excp_unmasked(CPUState *cs, unsigned int excp_idx, 2583 unsigned int target_el) 2584 { 2585 CPUARMState *env = cs->env_ptr; 2586 unsigned int cur_el = arm_current_el(env); 2587 bool secure = arm_is_secure(env); 2588 bool pstate_unmasked; 2589 int8_t unmasked = 0; 2590 uint64_t hcr_el2; 2591 2592 /* Don't take exceptions if they target a lower EL. 2593 * This check should catch any exceptions that would not be taken but left 2594 * pending. 2595 */ 2596 if (cur_el > target_el) { 2597 return false; 2598 } 2599 2600 hcr_el2 = arm_hcr_el2_eff(env); 2601 2602 switch (excp_idx) { 2603 case EXCP_FIQ: 2604 pstate_unmasked = !(env->daif & PSTATE_F); 2605 break; 2606 2607 case EXCP_IRQ: 2608 pstate_unmasked = !(env->daif & PSTATE_I); 2609 break; 2610 2611 case EXCP_VFIQ: 2612 if (secure || !(hcr_el2 & HCR_FMO) || (hcr_el2 & HCR_TGE)) { 2613 /* VFIQs are only taken when hypervized and non-secure. */ 2614 return false; 2615 } 2616 return !(env->daif & PSTATE_F); 2617 case EXCP_VIRQ: 2618 if (secure || !(hcr_el2 & HCR_IMO) || (hcr_el2 & HCR_TGE)) { 2619 /* VIRQs are only taken when hypervized and non-secure. */ 2620 return false; 2621 } 2622 return !(env->daif & PSTATE_I); 2623 default: 2624 g_assert_not_reached(); 2625 } 2626 2627 /* Use the target EL, current execution state and SCR/HCR settings to 2628 * determine whether the corresponding CPSR bit is used to mask the 2629 * interrupt. 2630 */ 2631 if ((target_el > cur_el) && (target_el != 1)) { 2632 /* Exceptions targeting a higher EL may not be maskable */ 2633 if (arm_feature(env, ARM_FEATURE_AARCH64)) { 2634 /* 64-bit masking rules are simple: exceptions to EL3 2635 * can't be masked, and exceptions to EL2 can only be 2636 * masked from Secure state. The HCR and SCR settings 2637 * don't affect the masking logic, only the interrupt routing. 2638 */ 2639 if (target_el == 3 || !secure) { 2640 unmasked = 1; 2641 } 2642 } else { 2643 /* The old 32-bit-only environment has a more complicated 2644 * masking setup. HCR and SCR bits not only affect interrupt 2645 * routing but also change the behaviour of masking. 2646 */ 2647 bool hcr, scr; 2648 2649 switch (excp_idx) { 2650 case EXCP_FIQ: 2651 /* If FIQs are routed to EL3 or EL2 then there are cases where 2652 * we override the CPSR.F in determining if the exception is 2653 * masked or not. If neither of these are set then we fall back 2654 * to the CPSR.F setting otherwise we further assess the state 2655 * below. 2656 */ 2657 hcr = hcr_el2 & HCR_FMO; 2658 scr = (env->cp15.scr_el3 & SCR_FIQ); 2659 2660 /* When EL3 is 32-bit, the SCR.FW bit controls whether the 2661 * CPSR.F bit masks FIQ interrupts when taken in non-secure 2662 * state. If SCR.FW is set then FIQs can be masked by CPSR.F 2663 * when non-secure but only when FIQs are only routed to EL3. 2664 */ 2665 scr = scr && !((env->cp15.scr_el3 & SCR_FW) && !hcr); 2666 break; 2667 case EXCP_IRQ: 2668 /* When EL3 execution state is 32-bit, if HCR.IMO is set then 2669 * we may override the CPSR.I masking when in non-secure state. 2670 * The SCR.IRQ setting has already been taken into consideration 2671 * when setting the target EL, so it does not have a further 2672 * affect here. 2673 */ 2674 hcr = hcr_el2 & HCR_IMO; 2675 scr = false; 2676 break; 2677 default: 2678 g_assert_not_reached(); 2679 } 2680 2681 if ((scr || hcr) && !secure) { 2682 unmasked = 1; 2683 } 2684 } 2685 } 2686 2687 /* The PSTATE bits only mask the interrupt if we have not overriden the 2688 * ability above. 2689 */ 2690 return unmasked || pstate_unmasked; 2691 } 2692 2693 #define ARM_CPU_TYPE_SUFFIX "-" TYPE_ARM_CPU 2694 #define ARM_CPU_TYPE_NAME(name) (name ARM_CPU_TYPE_SUFFIX) 2695 #define CPU_RESOLVING_TYPE TYPE_ARM_CPU 2696 2697 #define cpu_signal_handler cpu_arm_signal_handler 2698 #define cpu_list arm_cpu_list 2699 2700 /* ARM has the following "translation regimes" (as the ARM ARM calls them): 2701 * 2702 * If EL3 is 64-bit: 2703 * + NonSecure EL1 & 0 stage 1 2704 * + NonSecure EL1 & 0 stage 2 2705 * + NonSecure EL2 2706 * + Secure EL1 & EL0 2707 * + Secure EL3 2708 * If EL3 is 32-bit: 2709 * + NonSecure PL1 & 0 stage 1 2710 * + NonSecure PL1 & 0 stage 2 2711 * + NonSecure PL2 2712 * + Secure PL0 & PL1 2713 * (reminder: for 32 bit EL3, Secure PL1 is *EL3*, not EL1.) 2714 * 2715 * For QEMU, an mmu_idx is not quite the same as a translation regime because: 2716 * 1. we need to split the "EL1 & 0" regimes into two mmu_idxes, because they 2717 * may differ in access permissions even if the VA->PA map is the same 2718 * 2. we want to cache in our TLB the full VA->IPA->PA lookup for a stage 1+2 2719 * translation, which means that we have one mmu_idx that deals with two 2720 * concatenated translation regimes [this sort of combined s1+2 TLB is 2721 * architecturally permitted] 2722 * 3. we don't need to allocate an mmu_idx to translations that we won't be 2723 * handling via the TLB. The only way to do a stage 1 translation without 2724 * the immediate stage 2 translation is via the ATS or AT system insns, 2725 * which can be slow-pathed and always do a page table walk. 2726 * 4. we can also safely fold together the "32 bit EL3" and "64 bit EL3" 2727 * translation regimes, because they map reasonably well to each other 2728 * and they can't both be active at the same time. 2729 * This gives us the following list of mmu_idx values: 2730 * 2731 * NS EL0 (aka NS PL0) stage 1+2 2732 * NS EL1 (aka NS PL1) stage 1+2 2733 * NS EL2 (aka NS PL2) 2734 * S EL3 (aka S PL1) 2735 * S EL0 (aka S PL0) 2736 * S EL1 (not used if EL3 is 32 bit) 2737 * NS EL0+1 stage 2 2738 * 2739 * (The last of these is an mmu_idx because we want to be able to use the TLB 2740 * for the accesses done as part of a stage 1 page table walk, rather than 2741 * having to walk the stage 2 page table over and over.) 2742 * 2743 * R profile CPUs have an MPU, but can use the same set of MMU indexes 2744 * as A profile. They only need to distinguish NS EL0 and NS EL1 (and 2745 * NS EL2 if we ever model a Cortex-R52). 2746 * 2747 * M profile CPUs are rather different as they do not have a true MMU. 2748 * They have the following different MMU indexes: 2749 * User 2750 * Privileged 2751 * User, execution priority negative (ie the MPU HFNMIENA bit may apply) 2752 * Privileged, execution priority negative (ditto) 2753 * If the CPU supports the v8M Security Extension then there are also: 2754 * Secure User 2755 * Secure Privileged 2756 * Secure User, execution priority negative 2757 * Secure Privileged, execution priority negative 2758 * 2759 * The ARMMMUIdx and the mmu index value used by the core QEMU TLB code 2760 * are not quite the same -- different CPU types (most notably M profile 2761 * vs A/R profile) would like to use MMU indexes with different semantics, 2762 * but since we don't ever need to use all of those in a single CPU we 2763 * can avoid setting NB_MMU_MODES to more than 8. The lower bits of 2764 * ARMMMUIdx are the core TLB mmu index, and the higher bits are always 2765 * the same for any particular CPU. 2766 * Variables of type ARMMUIdx are always full values, and the core 2767 * index values are in variables of type 'int'. 2768 * 2769 * Our enumeration includes at the end some entries which are not "true" 2770 * mmu_idx values in that they don't have corresponding TLBs and are only 2771 * valid for doing slow path page table walks. 2772 * 2773 * The constant names here are patterned after the general style of the names 2774 * of the AT/ATS operations. 2775 * The values used are carefully arranged to make mmu_idx => EL lookup easy. 2776 * For M profile we arrange them to have a bit for priv, a bit for negpri 2777 * and a bit for secure. 2778 */ 2779 #define ARM_MMU_IDX_A 0x10 /* A profile */ 2780 #define ARM_MMU_IDX_NOTLB 0x20 /* does not have a TLB */ 2781 #define ARM_MMU_IDX_M 0x40 /* M profile */ 2782 2783 /* meanings of the bits for M profile mmu idx values */ 2784 #define ARM_MMU_IDX_M_PRIV 0x1 2785 #define ARM_MMU_IDX_M_NEGPRI 0x2 2786 #define ARM_MMU_IDX_M_S 0x4 2787 2788 #define ARM_MMU_IDX_TYPE_MASK (~0x7) 2789 #define ARM_MMU_IDX_COREIDX_MASK 0x7 2790 2791 typedef enum ARMMMUIdx { 2792 ARMMMUIdx_S12NSE0 = 0 | ARM_MMU_IDX_A, 2793 ARMMMUIdx_S12NSE1 = 1 | ARM_MMU_IDX_A, 2794 ARMMMUIdx_S1E2 = 2 | ARM_MMU_IDX_A, 2795 ARMMMUIdx_S1E3 = 3 | ARM_MMU_IDX_A, 2796 ARMMMUIdx_S1SE0 = 4 | ARM_MMU_IDX_A, 2797 ARMMMUIdx_S1SE1 = 5 | ARM_MMU_IDX_A, 2798 ARMMMUIdx_S2NS = 6 | ARM_MMU_IDX_A, 2799 ARMMMUIdx_MUser = 0 | ARM_MMU_IDX_M, 2800 ARMMMUIdx_MPriv = 1 | ARM_MMU_IDX_M, 2801 ARMMMUIdx_MUserNegPri = 2 | ARM_MMU_IDX_M, 2802 ARMMMUIdx_MPrivNegPri = 3 | ARM_MMU_IDX_M, 2803 ARMMMUIdx_MSUser = 4 | ARM_MMU_IDX_M, 2804 ARMMMUIdx_MSPriv = 5 | ARM_MMU_IDX_M, 2805 ARMMMUIdx_MSUserNegPri = 6 | ARM_MMU_IDX_M, 2806 ARMMMUIdx_MSPrivNegPri = 7 | ARM_MMU_IDX_M, 2807 /* Indexes below here don't have TLBs and are used only for AT system 2808 * instructions or for the first stage of an S12 page table walk. 2809 */ 2810 ARMMMUIdx_S1NSE0 = 0 | ARM_MMU_IDX_NOTLB, 2811 ARMMMUIdx_S1NSE1 = 1 | ARM_MMU_IDX_NOTLB, 2812 } ARMMMUIdx; 2813 2814 /* Bit macros for the core-mmu-index values for each index, 2815 * for use when calling tlb_flush_by_mmuidx() and friends. 2816 */ 2817 typedef enum ARMMMUIdxBit { 2818 ARMMMUIdxBit_S12NSE0 = 1 << 0, 2819 ARMMMUIdxBit_S12NSE1 = 1 << 1, 2820 ARMMMUIdxBit_S1E2 = 1 << 2, 2821 ARMMMUIdxBit_S1E3 = 1 << 3, 2822 ARMMMUIdxBit_S1SE0 = 1 << 4, 2823 ARMMMUIdxBit_S1SE1 = 1 << 5, 2824 ARMMMUIdxBit_S2NS = 1 << 6, 2825 ARMMMUIdxBit_MUser = 1 << 0, 2826 ARMMMUIdxBit_MPriv = 1 << 1, 2827 ARMMMUIdxBit_MUserNegPri = 1 << 2, 2828 ARMMMUIdxBit_MPrivNegPri = 1 << 3, 2829 ARMMMUIdxBit_MSUser = 1 << 4, 2830 ARMMMUIdxBit_MSPriv = 1 << 5, 2831 ARMMMUIdxBit_MSUserNegPri = 1 << 6, 2832 ARMMMUIdxBit_MSPrivNegPri = 1 << 7, 2833 } ARMMMUIdxBit; 2834 2835 #define MMU_USER_IDX 0 2836 2837 static inline int arm_to_core_mmu_idx(ARMMMUIdx mmu_idx) 2838 { 2839 return mmu_idx & ARM_MMU_IDX_COREIDX_MASK; 2840 } 2841 2842 static inline ARMMMUIdx core_to_arm_mmu_idx(CPUARMState *env, int mmu_idx) 2843 { 2844 if (arm_feature(env, ARM_FEATURE_M)) { 2845 return mmu_idx | ARM_MMU_IDX_M; 2846 } else { 2847 return mmu_idx | ARM_MMU_IDX_A; 2848 } 2849 } 2850 2851 /* Return the exception level we're running at if this is our mmu_idx */ 2852 static inline int arm_mmu_idx_to_el(ARMMMUIdx mmu_idx) 2853 { 2854 switch (mmu_idx & ARM_MMU_IDX_TYPE_MASK) { 2855 case ARM_MMU_IDX_A: 2856 return mmu_idx & 3; 2857 case ARM_MMU_IDX_M: 2858 return mmu_idx & ARM_MMU_IDX_M_PRIV; 2859 default: 2860 g_assert_not_reached(); 2861 } 2862 } 2863 2864 /* Return the MMU index for a v7M CPU in the specified security and 2865 * privilege state. 2866 */ 2867 ARMMMUIdx arm_v7m_mmu_idx_for_secstate_and_priv(CPUARMState *env, 2868 bool secstate, bool priv); 2869 2870 /* Return the MMU index for a v7M CPU in the specified security state */ 2871 ARMMMUIdx arm_v7m_mmu_idx_for_secstate(CPUARMState *env, bool secstate); 2872 2873 /** 2874 * cpu_mmu_index: 2875 * @env: The cpu environment 2876 * @ifetch: True for code access, false for data access. 2877 * 2878 * Return the core mmu index for the current translation regime. 2879 * This function is used by generic TCG code paths. 2880 */ 2881 int cpu_mmu_index(CPUARMState *env, bool ifetch); 2882 2883 /* Indexes used when registering address spaces with cpu_address_space_init */ 2884 typedef enum ARMASIdx { 2885 ARMASIdx_NS = 0, 2886 ARMASIdx_S = 1, 2887 } ARMASIdx; 2888 2889 /* Return the Exception Level targeted by debug exceptions. */ 2890 static inline int arm_debug_target_el(CPUARMState *env) 2891 { 2892 bool secure = arm_is_secure(env); 2893 bool route_to_el2 = false; 2894 2895 if (arm_feature(env, ARM_FEATURE_EL2) && !secure) { 2896 route_to_el2 = env->cp15.hcr_el2 & HCR_TGE || 2897 env->cp15.mdcr_el2 & MDCR_TDE; 2898 } 2899 2900 if (route_to_el2) { 2901 return 2; 2902 } else if (arm_feature(env, ARM_FEATURE_EL3) && 2903 !arm_el_is_aa64(env, 3) && secure) { 2904 return 3; 2905 } else { 2906 return 1; 2907 } 2908 } 2909 2910 static inline bool arm_v7m_csselr_razwi(ARMCPU *cpu) 2911 { 2912 /* If all the CLIDR.Ctypem bits are 0 there are no caches, and 2913 * CSSELR is RAZ/WI. 2914 */ 2915 return (cpu->clidr & R_V7M_CLIDR_CTYPE_ALL_MASK) != 0; 2916 } 2917 2918 /* See AArch64.GenerateDebugExceptionsFrom() in ARM ARM pseudocode */ 2919 static inline bool aa64_generate_debug_exceptions(CPUARMState *env) 2920 { 2921 int cur_el = arm_current_el(env); 2922 int debug_el; 2923 2924 if (cur_el == 3) { 2925 return false; 2926 } 2927 2928 /* MDCR_EL3.SDD disables debug events from Secure state */ 2929 if (arm_is_secure_below_el3(env) 2930 && extract32(env->cp15.mdcr_el3, 16, 1)) { 2931 return false; 2932 } 2933 2934 /* 2935 * Same EL to same EL debug exceptions need MDSCR_KDE enabled 2936 * while not masking the (D)ebug bit in DAIF. 2937 */ 2938 debug_el = arm_debug_target_el(env); 2939 2940 if (cur_el == debug_el) { 2941 return extract32(env->cp15.mdscr_el1, 13, 1) 2942 && !(env->daif & PSTATE_D); 2943 } 2944 2945 /* Otherwise the debug target needs to be a higher EL */ 2946 return debug_el > cur_el; 2947 } 2948 2949 static inline bool aa32_generate_debug_exceptions(CPUARMState *env) 2950 { 2951 int el = arm_current_el(env); 2952 2953 if (el == 0 && arm_el_is_aa64(env, 1)) { 2954 return aa64_generate_debug_exceptions(env); 2955 } 2956 2957 if (arm_is_secure(env)) { 2958 int spd; 2959 2960 if (el == 0 && (env->cp15.sder & 1)) { 2961 /* SDER.SUIDEN means debug exceptions from Secure EL0 2962 * are always enabled. Otherwise they are controlled by 2963 * SDCR.SPD like those from other Secure ELs. 2964 */ 2965 return true; 2966 } 2967 2968 spd = extract32(env->cp15.mdcr_el3, 14, 2); 2969 switch (spd) { 2970 case 1: 2971 /* SPD == 0b01 is reserved, but behaves as 0b00. */ 2972 case 0: 2973 /* For 0b00 we return true if external secure invasive debug 2974 * is enabled. On real hardware this is controlled by external 2975 * signals to the core. QEMU always permits debug, and behaves 2976 * as if DBGEN, SPIDEN, NIDEN and SPNIDEN are all tied high. 2977 */ 2978 return true; 2979 case 2: 2980 return false; 2981 case 3: 2982 return true; 2983 } 2984 } 2985 2986 return el != 2; 2987 } 2988 2989 /* Return true if debugging exceptions are currently enabled. 2990 * This corresponds to what in ARM ARM pseudocode would be 2991 * if UsingAArch32() then 2992 * return AArch32.GenerateDebugExceptions() 2993 * else 2994 * return AArch64.GenerateDebugExceptions() 2995 * We choose to push the if() down into this function for clarity, 2996 * since the pseudocode has it at all callsites except for the one in 2997 * CheckSoftwareStep(), where it is elided because both branches would 2998 * always return the same value. 2999 */ 3000 static inline bool arm_generate_debug_exceptions(CPUARMState *env) 3001 { 3002 if (env->aarch64) { 3003 return aa64_generate_debug_exceptions(env); 3004 } else { 3005 return aa32_generate_debug_exceptions(env); 3006 } 3007 } 3008 3009 /* Is single-stepping active? (Note that the "is EL_D AArch64?" check 3010 * implicitly means this always returns false in pre-v8 CPUs.) 3011 */ 3012 static inline bool arm_singlestep_active(CPUARMState *env) 3013 { 3014 return extract32(env->cp15.mdscr_el1, 0, 1) 3015 && arm_el_is_aa64(env, arm_debug_target_el(env)) 3016 && arm_generate_debug_exceptions(env); 3017 } 3018 3019 static inline bool arm_sctlr_b(CPUARMState *env) 3020 { 3021 return 3022 /* We need not implement SCTLR.ITD in user-mode emulation, so 3023 * let linux-user ignore the fact that it conflicts with SCTLR_B. 3024 * This lets people run BE32 binaries with "-cpu any". 3025 */ 3026 #ifndef CONFIG_USER_ONLY 3027 !arm_feature(env, ARM_FEATURE_V7) && 3028 #endif 3029 (env->cp15.sctlr_el[1] & SCTLR_B) != 0; 3030 } 3031 3032 /* Return true if the processor is in big-endian mode. */ 3033 static inline bool arm_cpu_data_is_big_endian(CPUARMState *env) 3034 { 3035 int cur_el; 3036 3037 /* In 32bit endianness is determined by looking at CPSR's E bit */ 3038 if (!is_a64(env)) { 3039 return 3040 #ifdef CONFIG_USER_ONLY 3041 /* In system mode, BE32 is modelled in line with the 3042 * architecture (as word-invariant big-endianness), where loads 3043 * and stores are done little endian but from addresses which 3044 * are adjusted by XORing with the appropriate constant. So the 3045 * endianness to use for the raw data access is not affected by 3046 * SCTLR.B. 3047 * In user mode, however, we model BE32 as byte-invariant 3048 * big-endianness (because user-only code cannot tell the 3049 * difference), and so we need to use a data access endianness 3050 * that depends on SCTLR.B. 3051 */ 3052 arm_sctlr_b(env) || 3053 #endif 3054 ((env->uncached_cpsr & CPSR_E) ? 1 : 0); 3055 } 3056 3057 cur_el = arm_current_el(env); 3058 3059 if (cur_el == 0) { 3060 return (env->cp15.sctlr_el[1] & SCTLR_E0E) != 0; 3061 } 3062 3063 return (env->cp15.sctlr_el[cur_el] & SCTLR_EE) != 0; 3064 } 3065 3066 #include "exec/cpu-all.h" 3067 3068 /* Bit usage in the TB flags field: bit 31 indicates whether we are 3069 * in 32 or 64 bit mode. The meaning of the other bits depends on that. 3070 * We put flags which are shared between 32 and 64 bit mode at the top 3071 * of the word, and flags which apply to only one mode at the bottom. 3072 */ 3073 FIELD(TBFLAG_ANY, AARCH64_STATE, 31, 1) 3074 FIELD(TBFLAG_ANY, MMUIDX, 28, 3) 3075 FIELD(TBFLAG_ANY, SS_ACTIVE, 27, 1) 3076 FIELD(TBFLAG_ANY, PSTATE_SS, 26, 1) 3077 /* Target EL if we take a floating-point-disabled exception */ 3078 FIELD(TBFLAG_ANY, FPEXC_EL, 24, 2) 3079 FIELD(TBFLAG_ANY, BE_DATA, 23, 1) 3080 3081 /* Bit usage when in AArch32 state: */ 3082 FIELD(TBFLAG_A32, THUMB, 0, 1) 3083 FIELD(TBFLAG_A32, VECLEN, 1, 3) 3084 FIELD(TBFLAG_A32, VECSTRIDE, 4, 2) 3085 FIELD(TBFLAG_A32, VFPEN, 7, 1) 3086 FIELD(TBFLAG_A32, CONDEXEC, 8, 8) 3087 FIELD(TBFLAG_A32, SCTLR_B, 16, 1) 3088 /* We store the bottom two bits of the CPAR as TB flags and handle 3089 * checks on the other bits at runtime 3090 */ 3091 FIELD(TBFLAG_A32, XSCALE_CPAR, 17, 2) 3092 /* Indicates whether cp register reads and writes by guest code should access 3093 * the secure or nonsecure bank of banked registers; note that this is not 3094 * the same thing as the current security state of the processor! 3095 */ 3096 FIELD(TBFLAG_A32, NS, 19, 1) 3097 /* For M profile only, Handler (ie not Thread) mode */ 3098 FIELD(TBFLAG_A32, HANDLER, 21, 1) 3099 /* For M profile only, whether we should generate stack-limit checks */ 3100 FIELD(TBFLAG_A32, STACKCHECK, 22, 1) 3101 3102 /* Bit usage when in AArch64 state */ 3103 FIELD(TBFLAG_A64, TBII, 0, 2) 3104 FIELD(TBFLAG_A64, SVEEXC_EL, 2, 2) 3105 FIELD(TBFLAG_A64, ZCR_LEN, 4, 4) 3106 FIELD(TBFLAG_A64, PAUTH_ACTIVE, 8, 1) 3107 FIELD(TBFLAG_A64, BT, 9, 1) 3108 FIELD(TBFLAG_A64, BTYPE, 10, 2) 3109 FIELD(TBFLAG_A64, TBID, 12, 2) 3110 3111 static inline bool bswap_code(bool sctlr_b) 3112 { 3113 #ifdef CONFIG_USER_ONLY 3114 /* BE8 (SCTLR.B = 0, TARGET_WORDS_BIGENDIAN = 1) is mixed endian. 3115 * The invalid combination SCTLR.B=1/CPSR.E=1/TARGET_WORDS_BIGENDIAN=0 3116 * would also end up as a mixed-endian mode with BE code, LE data. 3117 */ 3118 return 3119 #ifdef TARGET_WORDS_BIGENDIAN 3120 1 ^ 3121 #endif 3122 sctlr_b; 3123 #else 3124 /* All code access in ARM is little endian, and there are no loaders 3125 * doing swaps that need to be reversed 3126 */ 3127 return 0; 3128 #endif 3129 } 3130 3131 #ifdef CONFIG_USER_ONLY 3132 static inline bool arm_cpu_bswap_data(CPUARMState *env) 3133 { 3134 return 3135 #ifdef TARGET_WORDS_BIGENDIAN 3136 1 ^ 3137 #endif 3138 arm_cpu_data_is_big_endian(env); 3139 } 3140 #endif 3141 3142 void cpu_get_tb_cpu_state(CPUARMState *env, target_ulong *pc, 3143 target_ulong *cs_base, uint32_t *flags); 3144 3145 enum { 3146 QEMU_PSCI_CONDUIT_DISABLED = 0, 3147 QEMU_PSCI_CONDUIT_SMC = 1, 3148 QEMU_PSCI_CONDUIT_HVC = 2, 3149 }; 3150 3151 #ifndef CONFIG_USER_ONLY 3152 /* Return the address space index to use for a memory access */ 3153 static inline int arm_asidx_from_attrs(CPUState *cs, MemTxAttrs attrs) 3154 { 3155 return attrs.secure ? ARMASIdx_S : ARMASIdx_NS; 3156 } 3157 3158 /* Return the AddressSpace to use for a memory access 3159 * (which depends on whether the access is S or NS, and whether 3160 * the board gave us a separate AddressSpace for S accesses). 3161 */ 3162 static inline AddressSpace *arm_addressspace(CPUState *cs, MemTxAttrs attrs) 3163 { 3164 return cpu_get_address_space(cs, arm_asidx_from_attrs(cs, attrs)); 3165 } 3166 #endif 3167 3168 /** 3169 * arm_register_pre_el_change_hook: 3170 * Register a hook function which will be called immediately before this 3171 * CPU changes exception level or mode. The hook function will be 3172 * passed a pointer to the ARMCPU and the opaque data pointer passed 3173 * to this function when the hook was registered. 3174 * 3175 * Note that if a pre-change hook is called, any registered post-change hooks 3176 * are guaranteed to subsequently be called. 3177 */ 3178 void arm_register_pre_el_change_hook(ARMCPU *cpu, ARMELChangeHookFn *hook, 3179 void *opaque); 3180 /** 3181 * arm_register_el_change_hook: 3182 * Register a hook function which will be called immediately after this 3183 * CPU changes exception level or mode. The hook function will be 3184 * passed a pointer to the ARMCPU and the opaque data pointer passed 3185 * to this function when the hook was registered. 3186 * 3187 * Note that any registered hooks registered here are guaranteed to be called 3188 * if pre-change hooks have been. 3189 */ 3190 void arm_register_el_change_hook(ARMCPU *cpu, ARMELChangeHookFn *hook, void 3191 *opaque); 3192 3193 /** 3194 * aa32_vfp_dreg: 3195 * Return a pointer to the Dn register within env in 32-bit mode. 3196 */ 3197 static inline uint64_t *aa32_vfp_dreg(CPUARMState *env, unsigned regno) 3198 { 3199 return &env->vfp.zregs[regno >> 1].d[regno & 1]; 3200 } 3201 3202 /** 3203 * aa32_vfp_qreg: 3204 * Return a pointer to the Qn register within env in 32-bit mode. 3205 */ 3206 static inline uint64_t *aa32_vfp_qreg(CPUARMState *env, unsigned regno) 3207 { 3208 return &env->vfp.zregs[regno].d[0]; 3209 } 3210 3211 /** 3212 * aa64_vfp_qreg: 3213 * Return a pointer to the Qn register within env in 64-bit mode. 3214 */ 3215 static inline uint64_t *aa64_vfp_qreg(CPUARMState *env, unsigned regno) 3216 { 3217 return &env->vfp.zregs[regno].d[0]; 3218 } 3219 3220 /* Shared between translate-sve.c and sve_helper.c. */ 3221 extern const uint64_t pred_esz_masks[4]; 3222 3223 /* 3224 * 32-bit feature tests via id registers. 3225 */ 3226 static inline bool isar_feature_thumb_div(const ARMISARegisters *id) 3227 { 3228 return FIELD_EX32(id->id_isar0, ID_ISAR0, DIVIDE) != 0; 3229 } 3230 3231 static inline bool isar_feature_arm_div(const ARMISARegisters *id) 3232 { 3233 return FIELD_EX32(id->id_isar0, ID_ISAR0, DIVIDE) > 1; 3234 } 3235 3236 static inline bool isar_feature_jazelle(const ARMISARegisters *id) 3237 { 3238 return FIELD_EX32(id->id_isar1, ID_ISAR1, JAZELLE) != 0; 3239 } 3240 3241 static inline bool isar_feature_aa32_aes(const ARMISARegisters *id) 3242 { 3243 return FIELD_EX32(id->id_isar5, ID_ISAR5, AES) != 0; 3244 } 3245 3246 static inline bool isar_feature_aa32_pmull(const ARMISARegisters *id) 3247 { 3248 return FIELD_EX32(id->id_isar5, ID_ISAR5, AES) > 1; 3249 } 3250 3251 static inline bool isar_feature_aa32_sha1(const ARMISARegisters *id) 3252 { 3253 return FIELD_EX32(id->id_isar5, ID_ISAR5, SHA1) != 0; 3254 } 3255 3256 static inline bool isar_feature_aa32_sha2(const ARMISARegisters *id) 3257 { 3258 return FIELD_EX32(id->id_isar5, ID_ISAR5, SHA2) != 0; 3259 } 3260 3261 static inline bool isar_feature_aa32_crc32(const ARMISARegisters *id) 3262 { 3263 return FIELD_EX32(id->id_isar5, ID_ISAR5, CRC32) != 0; 3264 } 3265 3266 static inline bool isar_feature_aa32_rdm(const ARMISARegisters *id) 3267 { 3268 return FIELD_EX32(id->id_isar5, ID_ISAR5, RDM) != 0; 3269 } 3270 3271 static inline bool isar_feature_aa32_vcma(const ARMISARegisters *id) 3272 { 3273 return FIELD_EX32(id->id_isar5, ID_ISAR5, VCMA) != 0; 3274 } 3275 3276 static inline bool isar_feature_aa32_jscvt(const ARMISARegisters *id) 3277 { 3278 return FIELD_EX32(id->id_isar6, ID_ISAR6, JSCVT) != 0; 3279 } 3280 3281 static inline bool isar_feature_aa32_dp(const ARMISARegisters *id) 3282 { 3283 return FIELD_EX32(id->id_isar6, ID_ISAR6, DP) != 0; 3284 } 3285 3286 static inline bool isar_feature_aa32_fp16_arith(const ARMISARegisters *id) 3287 { 3288 /* 3289 * This is a placeholder for use by VCMA until the rest of 3290 * the ARMv8.2-FP16 extension is implemented for aa32 mode. 3291 * At which point we can properly set and check MVFR1.FPHP. 3292 */ 3293 return FIELD_EX64(id->id_aa64pfr0, ID_AA64PFR0, FP) == 1; 3294 } 3295 3296 /* 3297 * 64-bit feature tests via id registers. 3298 */ 3299 static inline bool isar_feature_aa64_aes(const ARMISARegisters *id) 3300 { 3301 return FIELD_EX64(id->id_aa64isar0, ID_AA64ISAR0, AES) != 0; 3302 } 3303 3304 static inline bool isar_feature_aa64_pmull(const ARMISARegisters *id) 3305 { 3306 return FIELD_EX64(id->id_aa64isar0, ID_AA64ISAR0, AES) > 1; 3307 } 3308 3309 static inline bool isar_feature_aa64_sha1(const ARMISARegisters *id) 3310 { 3311 return FIELD_EX64(id->id_aa64isar0, ID_AA64ISAR0, SHA1) != 0; 3312 } 3313 3314 static inline bool isar_feature_aa64_sha256(const ARMISARegisters *id) 3315 { 3316 return FIELD_EX64(id->id_aa64isar0, ID_AA64ISAR0, SHA2) != 0; 3317 } 3318 3319 static inline bool isar_feature_aa64_sha512(const ARMISARegisters *id) 3320 { 3321 return FIELD_EX64(id->id_aa64isar0, ID_AA64ISAR0, SHA2) > 1; 3322 } 3323 3324 static inline bool isar_feature_aa64_crc32(const ARMISARegisters *id) 3325 { 3326 return FIELD_EX64(id->id_aa64isar0, ID_AA64ISAR0, CRC32) != 0; 3327 } 3328 3329 static inline bool isar_feature_aa64_atomics(const ARMISARegisters *id) 3330 { 3331 return FIELD_EX64(id->id_aa64isar0, ID_AA64ISAR0, ATOMIC) != 0; 3332 } 3333 3334 static inline bool isar_feature_aa64_rdm(const ARMISARegisters *id) 3335 { 3336 return FIELD_EX64(id->id_aa64isar0, ID_AA64ISAR0, RDM) != 0; 3337 } 3338 3339 static inline bool isar_feature_aa64_sha3(const ARMISARegisters *id) 3340 { 3341 return FIELD_EX64(id->id_aa64isar0, ID_AA64ISAR0, SHA3) != 0; 3342 } 3343 3344 static inline bool isar_feature_aa64_sm3(const ARMISARegisters *id) 3345 { 3346 return FIELD_EX64(id->id_aa64isar0, ID_AA64ISAR0, SM3) != 0; 3347 } 3348 3349 static inline bool isar_feature_aa64_sm4(const ARMISARegisters *id) 3350 { 3351 return FIELD_EX64(id->id_aa64isar0, ID_AA64ISAR0, SM4) != 0; 3352 } 3353 3354 static inline bool isar_feature_aa64_dp(const ARMISARegisters *id) 3355 { 3356 return FIELD_EX64(id->id_aa64isar0, ID_AA64ISAR0, DP) != 0; 3357 } 3358 3359 static inline bool isar_feature_aa64_jscvt(const ARMISARegisters *id) 3360 { 3361 return FIELD_EX64(id->id_aa64isar1, ID_AA64ISAR1, JSCVT) != 0; 3362 } 3363 3364 static inline bool isar_feature_aa64_fcma(const ARMISARegisters *id) 3365 { 3366 return FIELD_EX64(id->id_aa64isar1, ID_AA64ISAR1, FCMA) != 0; 3367 } 3368 3369 static inline bool isar_feature_aa64_pauth(const ARMISARegisters *id) 3370 { 3371 /* 3372 * Note that while QEMU will only implement the architected algorithm 3373 * QARMA, and thus APA+GPA, the host cpu for kvm may use implementation 3374 * defined algorithms, and thus API+GPI, and this predicate controls 3375 * migration of the 128-bit keys. 3376 */ 3377 return (id->id_aa64isar1 & 3378 (FIELD_DP64(0, ID_AA64ISAR1, APA, 0xf) | 3379 FIELD_DP64(0, ID_AA64ISAR1, API, 0xf) | 3380 FIELD_DP64(0, ID_AA64ISAR1, GPA, 0xf) | 3381 FIELD_DP64(0, ID_AA64ISAR1, GPI, 0xf))) != 0; 3382 } 3383 3384 static inline bool isar_feature_aa64_fp16(const ARMISARegisters *id) 3385 { 3386 /* We always set the AdvSIMD and FP fields identically wrt FP16. */ 3387 return FIELD_EX64(id->id_aa64pfr0, ID_AA64PFR0, FP) == 1; 3388 } 3389 3390 static inline bool isar_feature_aa64_aa32(const ARMISARegisters *id) 3391 { 3392 return FIELD_EX64(id->id_aa64pfr0, ID_AA64PFR0, EL0) >= 2; 3393 } 3394 3395 static inline bool isar_feature_aa64_sve(const ARMISARegisters *id) 3396 { 3397 return FIELD_EX64(id->id_aa64pfr0, ID_AA64PFR0, SVE) != 0; 3398 } 3399 3400 static inline bool isar_feature_aa64_lor(const ARMISARegisters *id) 3401 { 3402 return FIELD_EX64(id->id_aa64mmfr1, ID_AA64MMFR1, LO) != 0; 3403 } 3404 3405 static inline bool isar_feature_aa64_bti(const ARMISARegisters *id) 3406 { 3407 return FIELD_EX64(id->id_aa64pfr1, ID_AA64PFR1, BT) != 0; 3408 } 3409 3410 /* 3411 * Forward to the above feature tests given an ARMCPU pointer. 3412 */ 3413 #define cpu_isar_feature(name, cpu) \ 3414 ({ ARMCPU *cpu_ = (cpu); isar_feature_##name(&cpu_->isar); }) 3415 3416 #endif 3417