1 /* 2 * ARM virtual CPU header 3 * 4 * Copyright (c) 2003 Fabrice Bellard 5 * 6 * This library is free software; you can redistribute it and/or 7 * modify it under the terms of the GNU Lesser General Public 8 * License as published by the Free Software Foundation; either 9 * version 2 of the License, or (at your option) any later version. 10 * 11 * This library is distributed in the hope that it will be useful, 12 * but WITHOUT ANY WARRANTY; without even the implied warranty of 13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU 14 * Lesser General Public License for more details. 15 * 16 * You should have received a copy of the GNU Lesser General Public 17 * License along with this library; if not, see <http://www.gnu.org/licenses/>. 18 */ 19 20 #ifndef ARM_CPU_H 21 #define ARM_CPU_H 22 23 #include "kvm-consts.h" 24 #include "hw/registerfields.h" 25 26 #if defined(TARGET_AARCH64) 27 /* AArch64 definitions */ 28 # define TARGET_LONG_BITS 64 29 #else 30 # define TARGET_LONG_BITS 32 31 #endif 32 33 #define CPUArchState struct CPUARMState 34 35 #include "qemu-common.h" 36 #include "cpu-qom.h" 37 #include "exec/cpu-defs.h" 38 39 #include "fpu/softfloat.h" 40 41 #define EXCP_UDEF 1 /* undefined instruction */ 42 #define EXCP_SWI 2 /* software interrupt */ 43 #define EXCP_PREFETCH_ABORT 3 44 #define EXCP_DATA_ABORT 4 45 #define EXCP_IRQ 5 46 #define EXCP_FIQ 6 47 #define EXCP_BKPT 7 48 #define EXCP_EXCEPTION_EXIT 8 /* Return from v7M exception. */ 49 #define EXCP_KERNEL_TRAP 9 /* Jumped to kernel code page. */ 50 #define EXCP_HVC 11 /* HyperVisor Call */ 51 #define EXCP_HYP_TRAP 12 52 #define EXCP_SMC 13 /* Secure Monitor Call */ 53 #define EXCP_VIRQ 14 54 #define EXCP_VFIQ 15 55 #define EXCP_SEMIHOST 16 /* semihosting call */ 56 #define EXCP_NOCP 17 /* v7M NOCP UsageFault */ 57 58 #define ARMV7M_EXCP_RESET 1 59 #define ARMV7M_EXCP_NMI 2 60 #define ARMV7M_EXCP_HARD 3 61 #define ARMV7M_EXCP_MEM 4 62 #define ARMV7M_EXCP_BUS 5 63 #define ARMV7M_EXCP_USAGE 6 64 #define ARMV7M_EXCP_SVC 11 65 #define ARMV7M_EXCP_DEBUG 12 66 #define ARMV7M_EXCP_PENDSV 14 67 #define ARMV7M_EXCP_SYSTICK 15 68 69 /* ARM-specific interrupt pending bits. */ 70 #define CPU_INTERRUPT_FIQ CPU_INTERRUPT_TGT_EXT_1 71 #define CPU_INTERRUPT_VIRQ CPU_INTERRUPT_TGT_EXT_2 72 #define CPU_INTERRUPT_VFIQ CPU_INTERRUPT_TGT_EXT_3 73 74 /* The usual mapping for an AArch64 system register to its AArch32 75 * counterpart is for the 32 bit world to have access to the lower 76 * half only (with writes leaving the upper half untouched). It's 77 * therefore useful to be able to pass TCG the offset of the least 78 * significant half of a uint64_t struct member. 79 */ 80 #ifdef HOST_WORDS_BIGENDIAN 81 #define offsetoflow32(S, M) (offsetof(S, M) + sizeof(uint32_t)) 82 #define offsetofhigh32(S, M) offsetof(S, M) 83 #else 84 #define offsetoflow32(S, M) offsetof(S, M) 85 #define offsetofhigh32(S, M) (offsetof(S, M) + sizeof(uint32_t)) 86 #endif 87 88 /* Meanings of the ARMCPU object's four inbound GPIO lines */ 89 #define ARM_CPU_IRQ 0 90 #define ARM_CPU_FIQ 1 91 #define ARM_CPU_VIRQ 2 92 #define ARM_CPU_VFIQ 3 93 94 #define NB_MMU_MODES 7 95 /* ARM-specific extra insn start words: 96 * 1: Conditional execution bits 97 * 2: Partial exception syndrome for data aborts 98 */ 99 #define TARGET_INSN_START_EXTRA_WORDS 2 100 101 /* The 2nd extra word holding syndrome info for data aborts does not use 102 * the upper 6 bits nor the lower 14 bits. We mask and shift it down to 103 * help the sleb128 encoder do a better job. 104 * When restoring the CPU state, we shift it back up. 105 */ 106 #define ARM_INSN_START_WORD2_MASK ((1 << 26) - 1) 107 #define ARM_INSN_START_WORD2_SHIFT 14 108 109 /* We currently assume float and double are IEEE single and double 110 precision respectively. 111 Doing runtime conversions is tricky because VFP registers may contain 112 integer values (eg. as the result of a FTOSI instruction). 113 s<2n> maps to the least significant half of d<n> 114 s<2n+1> maps to the most significant half of d<n> 115 */ 116 117 /* CPU state for each instance of a generic timer (in cp15 c14) */ 118 typedef struct ARMGenericTimer { 119 uint64_t cval; /* Timer CompareValue register */ 120 uint64_t ctl; /* Timer Control register */ 121 } ARMGenericTimer; 122 123 #define GTIMER_PHYS 0 124 #define GTIMER_VIRT 1 125 #define GTIMER_HYP 2 126 #define GTIMER_SEC 3 127 #define NUM_GTIMERS 4 128 129 typedef struct { 130 uint64_t raw_tcr; 131 uint32_t mask; 132 uint32_t base_mask; 133 } TCR; 134 135 typedef struct CPUARMState { 136 /* Regs for current mode. */ 137 uint32_t regs[16]; 138 139 /* 32/64 switch only happens when taking and returning from 140 * exceptions so the overlap semantics are taken care of then 141 * instead of having a complicated union. 142 */ 143 /* Regs for A64 mode. */ 144 uint64_t xregs[32]; 145 uint64_t pc; 146 /* PSTATE isn't an architectural register for ARMv8. However, it is 147 * convenient for us to assemble the underlying state into a 32 bit format 148 * identical to the architectural format used for the SPSR. (This is also 149 * what the Linux kernel's 'pstate' field in signal handlers and KVM's 150 * 'pstate' register are.) Of the PSTATE bits: 151 * NZCV are kept in the split out env->CF/VF/NF/ZF, (which have the same 152 * semantics as for AArch32, as described in the comments on each field) 153 * nRW (also known as M[4]) is kept, inverted, in env->aarch64 154 * DAIF (exception masks) are kept in env->daif 155 * all other bits are stored in their correct places in env->pstate 156 */ 157 uint32_t pstate; 158 uint32_t aarch64; /* 1 if CPU is in aarch64 state; inverse of PSTATE.nRW */ 159 160 /* Frequently accessed CPSR bits are stored separately for efficiency. 161 This contains all the other bits. Use cpsr_{read,write} to access 162 the whole CPSR. */ 163 uint32_t uncached_cpsr; 164 uint32_t spsr; 165 166 /* Banked registers. */ 167 uint64_t banked_spsr[8]; 168 uint32_t banked_r13[8]; 169 uint32_t banked_r14[8]; 170 171 /* These hold r8-r12. */ 172 uint32_t usr_regs[5]; 173 uint32_t fiq_regs[5]; 174 175 /* cpsr flag cache for faster execution */ 176 uint32_t CF; /* 0 or 1 */ 177 uint32_t VF; /* V is the bit 31. All other bits are undefined */ 178 uint32_t NF; /* N is bit 31. All other bits are undefined. */ 179 uint32_t ZF; /* Z set if zero. */ 180 uint32_t QF; /* 0 or 1 */ 181 uint32_t GE; /* cpsr[19:16] */ 182 uint32_t thumb; /* cpsr[5]. 0 = arm mode, 1 = thumb mode. */ 183 uint32_t condexec_bits; /* IT bits. cpsr[15:10,26:25]. */ 184 uint64_t daif; /* exception masks, in the bits they are in PSTATE */ 185 186 uint64_t elr_el[4]; /* AArch64 exception link regs */ 187 uint64_t sp_el[4]; /* AArch64 banked stack pointers */ 188 189 /* System control coprocessor (cp15) */ 190 struct { 191 uint32_t c0_cpuid; 192 union { /* Cache size selection */ 193 struct { 194 uint64_t _unused_csselr0; 195 uint64_t csselr_ns; 196 uint64_t _unused_csselr1; 197 uint64_t csselr_s; 198 }; 199 uint64_t csselr_el[4]; 200 }; 201 union { /* System control register. */ 202 struct { 203 uint64_t _unused_sctlr; 204 uint64_t sctlr_ns; 205 uint64_t hsctlr; 206 uint64_t sctlr_s; 207 }; 208 uint64_t sctlr_el[4]; 209 }; 210 uint64_t cpacr_el1; /* Architectural feature access control register */ 211 uint64_t cptr_el[4]; /* ARMv8 feature trap registers */ 212 uint32_t c1_xscaleauxcr; /* XScale auxiliary control register. */ 213 uint64_t sder; /* Secure debug enable register. */ 214 uint32_t nsacr; /* Non-secure access control register. */ 215 union { /* MMU translation table base 0. */ 216 struct { 217 uint64_t _unused_ttbr0_0; 218 uint64_t ttbr0_ns; 219 uint64_t _unused_ttbr0_1; 220 uint64_t ttbr0_s; 221 }; 222 uint64_t ttbr0_el[4]; 223 }; 224 union { /* MMU translation table base 1. */ 225 struct { 226 uint64_t _unused_ttbr1_0; 227 uint64_t ttbr1_ns; 228 uint64_t _unused_ttbr1_1; 229 uint64_t ttbr1_s; 230 }; 231 uint64_t ttbr1_el[4]; 232 }; 233 uint64_t vttbr_el2; /* Virtualization Translation Table Base. */ 234 /* MMU translation table base control. */ 235 TCR tcr_el[4]; 236 TCR vtcr_el2; /* Virtualization Translation Control. */ 237 uint32_t c2_data; /* MPU data cacheable bits. */ 238 uint32_t c2_insn; /* MPU instruction cacheable bits. */ 239 union { /* MMU domain access control register 240 * MPU write buffer control. 241 */ 242 struct { 243 uint64_t dacr_ns; 244 uint64_t dacr_s; 245 }; 246 struct { 247 uint64_t dacr32_el2; 248 }; 249 }; 250 uint32_t pmsav5_data_ap; /* PMSAv5 MPU data access permissions */ 251 uint32_t pmsav5_insn_ap; /* PMSAv5 MPU insn access permissions */ 252 uint64_t hcr_el2; /* Hypervisor configuration register */ 253 uint64_t scr_el3; /* Secure configuration register. */ 254 union { /* Fault status registers. */ 255 struct { 256 uint64_t ifsr_ns; 257 uint64_t ifsr_s; 258 }; 259 struct { 260 uint64_t ifsr32_el2; 261 }; 262 }; 263 union { 264 struct { 265 uint64_t _unused_dfsr; 266 uint64_t dfsr_ns; 267 uint64_t hsr; 268 uint64_t dfsr_s; 269 }; 270 uint64_t esr_el[4]; 271 }; 272 uint32_t c6_region[8]; /* MPU base/size registers. */ 273 union { /* Fault address registers. */ 274 struct { 275 uint64_t _unused_far0; 276 #ifdef HOST_WORDS_BIGENDIAN 277 uint32_t ifar_ns; 278 uint32_t dfar_ns; 279 uint32_t ifar_s; 280 uint32_t dfar_s; 281 #else 282 uint32_t dfar_ns; 283 uint32_t ifar_ns; 284 uint32_t dfar_s; 285 uint32_t ifar_s; 286 #endif 287 uint64_t _unused_far3; 288 }; 289 uint64_t far_el[4]; 290 }; 291 uint64_t hpfar_el2; 292 uint64_t hstr_el2; 293 union { /* Translation result. */ 294 struct { 295 uint64_t _unused_par_0; 296 uint64_t par_ns; 297 uint64_t _unused_par_1; 298 uint64_t par_s; 299 }; 300 uint64_t par_el[4]; 301 }; 302 303 uint32_t c6_rgnr; 304 305 uint32_t c9_insn; /* Cache lockdown registers. */ 306 uint32_t c9_data; 307 uint64_t c9_pmcr; /* performance monitor control register */ 308 uint64_t c9_pmcnten; /* perf monitor counter enables */ 309 uint32_t c9_pmovsr; /* perf monitor overflow status */ 310 uint32_t c9_pmuserenr; /* perf monitor user enable */ 311 uint64_t c9_pmselr; /* perf monitor counter selection register */ 312 uint64_t c9_pminten; /* perf monitor interrupt enables */ 313 union { /* Memory attribute redirection */ 314 struct { 315 #ifdef HOST_WORDS_BIGENDIAN 316 uint64_t _unused_mair_0; 317 uint32_t mair1_ns; 318 uint32_t mair0_ns; 319 uint64_t _unused_mair_1; 320 uint32_t mair1_s; 321 uint32_t mair0_s; 322 #else 323 uint64_t _unused_mair_0; 324 uint32_t mair0_ns; 325 uint32_t mair1_ns; 326 uint64_t _unused_mair_1; 327 uint32_t mair0_s; 328 uint32_t mair1_s; 329 #endif 330 }; 331 uint64_t mair_el[4]; 332 }; 333 union { /* vector base address register */ 334 struct { 335 uint64_t _unused_vbar; 336 uint64_t vbar_ns; 337 uint64_t hvbar; 338 uint64_t vbar_s; 339 }; 340 uint64_t vbar_el[4]; 341 }; 342 uint32_t mvbar; /* (monitor) vector base address register */ 343 struct { /* FCSE PID. */ 344 uint32_t fcseidr_ns; 345 uint32_t fcseidr_s; 346 }; 347 union { /* Context ID. */ 348 struct { 349 uint64_t _unused_contextidr_0; 350 uint64_t contextidr_ns; 351 uint64_t _unused_contextidr_1; 352 uint64_t contextidr_s; 353 }; 354 uint64_t contextidr_el[4]; 355 }; 356 union { /* User RW Thread register. */ 357 struct { 358 uint64_t tpidrurw_ns; 359 uint64_t tpidrprw_ns; 360 uint64_t htpidr; 361 uint64_t _tpidr_el3; 362 }; 363 uint64_t tpidr_el[4]; 364 }; 365 /* The secure banks of these registers don't map anywhere */ 366 uint64_t tpidrurw_s; 367 uint64_t tpidrprw_s; 368 uint64_t tpidruro_s; 369 370 union { /* User RO Thread register. */ 371 uint64_t tpidruro_ns; 372 uint64_t tpidrro_el[1]; 373 }; 374 uint64_t c14_cntfrq; /* Counter Frequency register */ 375 uint64_t c14_cntkctl; /* Timer Control register */ 376 uint32_t cnthctl_el2; /* Counter/Timer Hyp Control register */ 377 uint64_t cntvoff_el2; /* Counter Virtual Offset register */ 378 ARMGenericTimer c14_timer[NUM_GTIMERS]; 379 uint32_t c15_cpar; /* XScale Coprocessor Access Register */ 380 uint32_t c15_ticonfig; /* TI925T configuration byte. */ 381 uint32_t c15_i_max; /* Maximum D-cache dirty line index. */ 382 uint32_t c15_i_min; /* Minimum D-cache dirty line index. */ 383 uint32_t c15_threadid; /* TI debugger thread-ID. */ 384 uint32_t c15_config_base_address; /* SCU base address. */ 385 uint32_t c15_diagnostic; /* diagnostic register */ 386 uint32_t c15_power_diagnostic; 387 uint32_t c15_power_control; /* power control */ 388 uint64_t dbgbvr[16]; /* breakpoint value registers */ 389 uint64_t dbgbcr[16]; /* breakpoint control registers */ 390 uint64_t dbgwvr[16]; /* watchpoint value registers */ 391 uint64_t dbgwcr[16]; /* watchpoint control registers */ 392 uint64_t mdscr_el1; 393 uint64_t oslsr_el1; /* OS Lock Status */ 394 uint64_t mdcr_el2; 395 uint64_t mdcr_el3; 396 /* If the counter is enabled, this stores the last time the counter 397 * was reset. Otherwise it stores the counter value 398 */ 399 uint64_t c15_ccnt; 400 uint64_t pmccfiltr_el0; /* Performance Monitor Filter Register */ 401 uint64_t vpidr_el2; /* Virtualization Processor ID Register */ 402 uint64_t vmpidr_el2; /* Virtualization Multiprocessor ID Register */ 403 } cp15; 404 405 struct { 406 uint32_t other_sp; 407 uint32_t vecbase; 408 uint32_t basepri; 409 uint32_t control; 410 uint32_t ccr; /* Configuration and Control */ 411 uint32_t cfsr; /* Configurable Fault Status */ 412 uint32_t hfsr; /* HardFault Status */ 413 uint32_t dfsr; /* Debug Fault Status Register */ 414 uint32_t mmfar; /* MemManage Fault Address */ 415 uint32_t bfar; /* BusFault Address */ 416 int exception; 417 } v7m; 418 419 /* Information associated with an exception about to be taken: 420 * code which raises an exception must set cs->exception_index and 421 * the relevant parts of this structure; the cpu_do_interrupt function 422 * will then set the guest-visible registers as part of the exception 423 * entry process. 424 */ 425 struct { 426 uint32_t syndrome; /* AArch64 format syndrome register */ 427 uint32_t fsr; /* AArch32 format fault status register info */ 428 uint64_t vaddress; /* virtual addr associated with exception, if any */ 429 uint32_t target_el; /* EL the exception should be targeted for */ 430 /* If we implement EL2 we will also need to store information 431 * about the intermediate physical address for stage 2 faults. 432 */ 433 } exception; 434 435 /* Thumb-2 EE state. */ 436 uint32_t teecr; 437 uint32_t teehbr; 438 439 /* VFP coprocessor state. */ 440 struct { 441 /* VFP/Neon register state. Note that the mapping between S, D and Q 442 * views of the register bank differs between AArch64 and AArch32: 443 * In AArch32: 444 * Qn = regs[2n+1]:regs[2n] 445 * Dn = regs[n] 446 * Sn = regs[n/2] bits 31..0 for even n, and bits 63..32 for odd n 447 * (and regs[32] to regs[63] are inaccessible) 448 * In AArch64: 449 * Qn = regs[2n+1]:regs[2n] 450 * Dn = regs[2n] 451 * Sn = regs[2n] bits 31..0 452 * This corresponds to the architecturally defined mapping between 453 * the two execution states, and means we do not need to explicitly 454 * map these registers when changing states. 455 */ 456 float64 regs[64]; 457 458 uint32_t xregs[16]; 459 /* We store these fpcsr fields separately for convenience. */ 460 int vec_len; 461 int vec_stride; 462 463 /* scratch space when Tn are not sufficient. */ 464 uint32_t scratch[8]; 465 466 /* fp_status is the "normal" fp status. standard_fp_status retains 467 * values corresponding to the ARM "Standard FPSCR Value", ie 468 * default-NaN, flush-to-zero, round-to-nearest and is used by 469 * any operations (generally Neon) which the architecture defines 470 * as controlled by the standard FPSCR value rather than the FPSCR. 471 * 472 * To avoid having to transfer exception bits around, we simply 473 * say that the FPSCR cumulative exception flags are the logical 474 * OR of the flags in the two fp statuses. This relies on the 475 * only thing which needs to read the exception flags being 476 * an explicit FPSCR read. 477 */ 478 float_status fp_status; 479 float_status standard_fp_status; 480 } vfp; 481 uint64_t exclusive_addr; 482 uint64_t exclusive_val; 483 uint64_t exclusive_high; 484 485 /* iwMMXt coprocessor state. */ 486 struct { 487 uint64_t regs[16]; 488 uint64_t val; 489 490 uint32_t cregs[16]; 491 } iwmmxt; 492 493 #if defined(CONFIG_USER_ONLY) 494 /* For usermode syscall translation. */ 495 int eabi; 496 #endif 497 498 struct CPUBreakpoint *cpu_breakpoint[16]; 499 struct CPUWatchpoint *cpu_watchpoint[16]; 500 501 /* Fields up to this point are cleared by a CPU reset */ 502 struct {} end_reset_fields; 503 504 CPU_COMMON 505 506 /* Fields after CPU_COMMON are preserved across CPU reset. */ 507 508 /* Internal CPU feature flags. */ 509 uint64_t features; 510 511 /* PMSAv7 MPU */ 512 struct { 513 uint32_t *drbar; 514 uint32_t *drsr; 515 uint32_t *dracr; 516 } pmsav7; 517 518 void *nvic; 519 const struct arm_boot_info *boot_info; 520 } CPUARMState; 521 522 /** 523 * ARMELChangeHook: 524 * type of a function which can be registered via arm_register_el_change_hook() 525 * to get callbacks when the CPU changes its exception level or mode. 526 */ 527 typedef void ARMELChangeHook(ARMCPU *cpu, void *opaque); 528 529 /** 530 * ARMCPU: 531 * @env: #CPUARMState 532 * 533 * An ARM CPU core. 534 */ 535 struct ARMCPU { 536 /*< private >*/ 537 CPUState parent_obj; 538 /*< public >*/ 539 540 CPUARMState env; 541 542 /* Coprocessor information */ 543 GHashTable *cp_regs; 544 /* For marshalling (mostly coprocessor) register state between the 545 * kernel and QEMU (for KVM) and between two QEMUs (for migration), 546 * we use these arrays. 547 */ 548 /* List of register indexes managed via these arrays; (full KVM style 549 * 64 bit indexes, not CPRegInfo 32 bit indexes) 550 */ 551 uint64_t *cpreg_indexes; 552 /* Values of the registers (cpreg_indexes[i]'s value is cpreg_values[i]) */ 553 uint64_t *cpreg_values; 554 /* Length of the indexes, values, reset_values arrays */ 555 int32_t cpreg_array_len; 556 /* These are used only for migration: incoming data arrives in 557 * these fields and is sanity checked in post_load before copying 558 * to the working data structures above. 559 */ 560 uint64_t *cpreg_vmstate_indexes; 561 uint64_t *cpreg_vmstate_values; 562 int32_t cpreg_vmstate_array_len; 563 564 /* Timers used by the generic (architected) timer */ 565 QEMUTimer *gt_timer[NUM_GTIMERS]; 566 /* GPIO outputs for generic timer */ 567 qemu_irq gt_timer_outputs[NUM_GTIMERS]; 568 /* GPIO output for GICv3 maintenance interrupt signal */ 569 qemu_irq gicv3_maintenance_interrupt; 570 571 /* MemoryRegion to use for secure physical accesses */ 572 MemoryRegion *secure_memory; 573 574 /* 'compatible' string for this CPU for Linux device trees */ 575 const char *dtb_compatible; 576 577 /* PSCI version for this CPU 578 * Bits[31:16] = Major Version 579 * Bits[15:0] = Minor Version 580 */ 581 uint32_t psci_version; 582 583 /* Should CPU start in PSCI powered-off state? */ 584 bool start_powered_off; 585 /* CPU currently in PSCI powered-off state */ 586 bool powered_off; 587 /* CPU has virtualization extension */ 588 bool has_el2; 589 /* CPU has security extension */ 590 bool has_el3; 591 /* CPU has PMU (Performance Monitor Unit) */ 592 bool has_pmu; 593 594 /* CPU has memory protection unit */ 595 bool has_mpu; 596 /* PMSAv7 MPU number of supported regions */ 597 uint32_t pmsav7_dregion; 598 599 /* PSCI conduit used to invoke PSCI methods 600 * 0 - disabled, 1 - smc, 2 - hvc 601 */ 602 uint32_t psci_conduit; 603 604 /* [QEMU_]KVM_ARM_TARGET_* constant for this CPU, or 605 * QEMU_KVM_ARM_TARGET_NONE if the kernel doesn't support this CPU type. 606 */ 607 uint32_t kvm_target; 608 609 /* KVM init features for this CPU */ 610 uint32_t kvm_init_features[7]; 611 612 /* Uniprocessor system with MP extensions */ 613 bool mp_is_up; 614 615 /* The instance init functions for implementation-specific subclasses 616 * set these fields to specify the implementation-dependent values of 617 * various constant registers and reset values of non-constant 618 * registers. 619 * Some of these might become QOM properties eventually. 620 * Field names match the official register names as defined in the 621 * ARMv7AR ARM Architecture Reference Manual. A reset_ prefix 622 * is used for reset values of non-constant registers; no reset_ 623 * prefix means a constant register. 624 */ 625 uint32_t midr; 626 uint32_t revidr; 627 uint32_t reset_fpsid; 628 uint32_t mvfr0; 629 uint32_t mvfr1; 630 uint32_t mvfr2; 631 uint32_t ctr; 632 uint32_t reset_sctlr; 633 uint32_t id_pfr0; 634 uint32_t id_pfr1; 635 uint32_t id_dfr0; 636 uint32_t pmceid0; 637 uint32_t pmceid1; 638 uint32_t id_afr0; 639 uint32_t id_mmfr0; 640 uint32_t id_mmfr1; 641 uint32_t id_mmfr2; 642 uint32_t id_mmfr3; 643 uint32_t id_mmfr4; 644 uint32_t id_isar0; 645 uint32_t id_isar1; 646 uint32_t id_isar2; 647 uint32_t id_isar3; 648 uint32_t id_isar4; 649 uint32_t id_isar5; 650 uint64_t id_aa64pfr0; 651 uint64_t id_aa64pfr1; 652 uint64_t id_aa64dfr0; 653 uint64_t id_aa64dfr1; 654 uint64_t id_aa64afr0; 655 uint64_t id_aa64afr1; 656 uint64_t id_aa64isar0; 657 uint64_t id_aa64isar1; 658 uint64_t id_aa64mmfr0; 659 uint64_t id_aa64mmfr1; 660 uint32_t dbgdidr; 661 uint32_t clidr; 662 uint64_t mp_affinity; /* MP ID without feature bits */ 663 /* The elements of this array are the CCSIDR values for each cache, 664 * in the order L1DCache, L1ICache, L2DCache, L2ICache, etc. 665 */ 666 uint32_t ccsidr[16]; 667 uint64_t reset_cbar; 668 uint32_t reset_auxcr; 669 bool reset_hivecs; 670 /* DCZ blocksize, in log_2(words), ie low 4 bits of DCZID_EL0 */ 671 uint32_t dcz_blocksize; 672 uint64_t rvbar; 673 674 /* Configurable aspects of GIC cpu interface (which is part of the CPU) */ 675 int gic_num_lrs; /* number of list registers */ 676 int gic_vpribits; /* number of virtual priority bits */ 677 int gic_vprebits; /* number of virtual preemption bits */ 678 679 /* Whether the cfgend input is high (i.e. this CPU should reset into 680 * big-endian mode). This setting isn't used directly: instead it modifies 681 * the reset_sctlr value to have SCTLR_B or SCTLR_EE set, depending on the 682 * architecture version. 683 */ 684 bool cfgend; 685 686 ARMELChangeHook *el_change_hook; 687 void *el_change_hook_opaque; 688 }; 689 690 static inline ARMCPU *arm_env_get_cpu(CPUARMState *env) 691 { 692 return container_of(env, ARMCPU, env); 693 } 694 695 #define ENV_GET_CPU(e) CPU(arm_env_get_cpu(e)) 696 697 #define ENV_OFFSET offsetof(ARMCPU, env) 698 699 #ifndef CONFIG_USER_ONLY 700 extern const struct VMStateDescription vmstate_arm_cpu; 701 #endif 702 703 void arm_cpu_do_interrupt(CPUState *cpu); 704 void arm_v7m_cpu_do_interrupt(CPUState *cpu); 705 bool arm_cpu_exec_interrupt(CPUState *cpu, int int_req); 706 707 void arm_cpu_dump_state(CPUState *cs, FILE *f, fprintf_function cpu_fprintf, 708 int flags); 709 710 hwaddr arm_cpu_get_phys_page_attrs_debug(CPUState *cpu, vaddr addr, 711 MemTxAttrs *attrs); 712 713 int arm_cpu_gdb_read_register(CPUState *cpu, uint8_t *buf, int reg); 714 int arm_cpu_gdb_write_register(CPUState *cpu, uint8_t *buf, int reg); 715 716 int arm_cpu_write_elf64_note(WriteCoreDumpFunction f, CPUState *cs, 717 int cpuid, void *opaque); 718 int arm_cpu_write_elf32_note(WriteCoreDumpFunction f, CPUState *cs, 719 int cpuid, void *opaque); 720 721 #ifdef TARGET_AARCH64 722 int aarch64_cpu_gdb_read_register(CPUState *cpu, uint8_t *buf, int reg); 723 int aarch64_cpu_gdb_write_register(CPUState *cpu, uint8_t *buf, int reg); 724 #endif 725 726 ARMCPU *cpu_arm_init(const char *cpu_model); 727 target_ulong do_arm_semihosting(CPUARMState *env); 728 void aarch64_sync_32_to_64(CPUARMState *env); 729 void aarch64_sync_64_to_32(CPUARMState *env); 730 731 static inline bool is_a64(CPUARMState *env) 732 { 733 return env->aarch64; 734 } 735 736 /* you can call this signal handler from your SIGBUS and SIGSEGV 737 signal handlers to inform the virtual CPU of exceptions. non zero 738 is returned if the signal was handled by the virtual CPU. */ 739 int cpu_arm_signal_handler(int host_signum, void *pinfo, 740 void *puc); 741 742 /** 743 * pmccntr_sync 744 * @env: CPUARMState 745 * 746 * Synchronises the counter in the PMCCNTR. This must always be called twice, 747 * once before any action that might affect the timer and again afterwards. 748 * The function is used to swap the state of the register if required. 749 * This only happens when not in user mode (!CONFIG_USER_ONLY) 750 */ 751 void pmccntr_sync(CPUARMState *env); 752 753 /* SCTLR bit meanings. Several bits have been reused in newer 754 * versions of the architecture; in that case we define constants 755 * for both old and new bit meanings. Code which tests against those 756 * bits should probably check or otherwise arrange that the CPU 757 * is the architectural version it expects. 758 */ 759 #define SCTLR_M (1U << 0) 760 #define SCTLR_A (1U << 1) 761 #define SCTLR_C (1U << 2) 762 #define SCTLR_W (1U << 3) /* up to v6; RAO in v7 */ 763 #define SCTLR_SA (1U << 3) 764 #define SCTLR_P (1U << 4) /* up to v5; RAO in v6 and v7 */ 765 #define SCTLR_SA0 (1U << 4) /* v8 onward, AArch64 only */ 766 #define SCTLR_D (1U << 5) /* up to v5; RAO in v6 */ 767 #define SCTLR_CP15BEN (1U << 5) /* v7 onward */ 768 #define SCTLR_L (1U << 6) /* up to v5; RAO in v6 and v7; RAZ in v8 */ 769 #define SCTLR_B (1U << 7) /* up to v6; RAZ in v7 */ 770 #define SCTLR_ITD (1U << 7) /* v8 onward */ 771 #define SCTLR_S (1U << 8) /* up to v6; RAZ in v7 */ 772 #define SCTLR_SED (1U << 8) /* v8 onward */ 773 #define SCTLR_R (1U << 9) /* up to v6; RAZ in v7 */ 774 #define SCTLR_UMA (1U << 9) /* v8 onward, AArch64 only */ 775 #define SCTLR_F (1U << 10) /* up to v6 */ 776 #define SCTLR_SW (1U << 10) /* v7 onward */ 777 #define SCTLR_Z (1U << 11) 778 #define SCTLR_I (1U << 12) 779 #define SCTLR_V (1U << 13) 780 #define SCTLR_RR (1U << 14) /* up to v7 */ 781 #define SCTLR_DZE (1U << 14) /* v8 onward, AArch64 only */ 782 #define SCTLR_L4 (1U << 15) /* up to v6; RAZ in v7 */ 783 #define SCTLR_UCT (1U << 15) /* v8 onward, AArch64 only */ 784 #define SCTLR_DT (1U << 16) /* up to ??, RAO in v6 and v7 */ 785 #define SCTLR_nTWI (1U << 16) /* v8 onward */ 786 #define SCTLR_HA (1U << 17) 787 #define SCTLR_BR (1U << 17) /* PMSA only */ 788 #define SCTLR_IT (1U << 18) /* up to ??, RAO in v6 and v7 */ 789 #define SCTLR_nTWE (1U << 18) /* v8 onward */ 790 #define SCTLR_WXN (1U << 19) 791 #define SCTLR_ST (1U << 20) /* up to ??, RAZ in v6 */ 792 #define SCTLR_UWXN (1U << 20) /* v7 onward */ 793 #define SCTLR_FI (1U << 21) 794 #define SCTLR_U (1U << 22) 795 #define SCTLR_XP (1U << 23) /* up to v6; v7 onward RAO */ 796 #define SCTLR_VE (1U << 24) /* up to v7 */ 797 #define SCTLR_E0E (1U << 24) /* v8 onward, AArch64 only */ 798 #define SCTLR_EE (1U << 25) 799 #define SCTLR_L2 (1U << 26) /* up to v6, RAZ in v7 */ 800 #define SCTLR_UCI (1U << 26) /* v8 onward, AArch64 only */ 801 #define SCTLR_NMFI (1U << 27) 802 #define SCTLR_TRE (1U << 28) 803 #define SCTLR_AFE (1U << 29) 804 #define SCTLR_TE (1U << 30) 805 806 #define CPTR_TCPAC (1U << 31) 807 #define CPTR_TTA (1U << 20) 808 #define CPTR_TFP (1U << 10) 809 810 #define MDCR_EPMAD (1U << 21) 811 #define MDCR_EDAD (1U << 20) 812 #define MDCR_SPME (1U << 17) 813 #define MDCR_SDD (1U << 16) 814 #define MDCR_SPD (3U << 14) 815 #define MDCR_TDRA (1U << 11) 816 #define MDCR_TDOSA (1U << 10) 817 #define MDCR_TDA (1U << 9) 818 #define MDCR_TDE (1U << 8) 819 #define MDCR_HPME (1U << 7) 820 #define MDCR_TPM (1U << 6) 821 #define MDCR_TPMCR (1U << 5) 822 823 /* Not all of the MDCR_EL3 bits are present in the 32-bit SDCR */ 824 #define SDCR_VALID_MASK (MDCR_EPMAD | MDCR_EDAD | MDCR_SPME | MDCR_SPD) 825 826 #define CPSR_M (0x1fU) 827 #define CPSR_T (1U << 5) 828 #define CPSR_F (1U << 6) 829 #define CPSR_I (1U << 7) 830 #define CPSR_A (1U << 8) 831 #define CPSR_E (1U << 9) 832 #define CPSR_IT_2_7 (0xfc00U) 833 #define CPSR_GE (0xfU << 16) 834 #define CPSR_IL (1U << 20) 835 /* Note that the RESERVED bits include bit 21, which is PSTATE_SS in 836 * an AArch64 SPSR but RES0 in AArch32 SPSR and CPSR. In QEMU we use 837 * env->uncached_cpsr bit 21 to store PSTATE.SS when executing in AArch32, 838 * where it is live state but not accessible to the AArch32 code. 839 */ 840 #define CPSR_RESERVED (0x7U << 21) 841 #define CPSR_J (1U << 24) 842 #define CPSR_IT_0_1 (3U << 25) 843 #define CPSR_Q (1U << 27) 844 #define CPSR_V (1U << 28) 845 #define CPSR_C (1U << 29) 846 #define CPSR_Z (1U << 30) 847 #define CPSR_N (1U << 31) 848 #define CPSR_NZCV (CPSR_N | CPSR_Z | CPSR_C | CPSR_V) 849 #define CPSR_AIF (CPSR_A | CPSR_I | CPSR_F) 850 851 #define CPSR_IT (CPSR_IT_0_1 | CPSR_IT_2_7) 852 #define CACHED_CPSR_BITS (CPSR_T | CPSR_AIF | CPSR_GE | CPSR_IT | CPSR_Q \ 853 | CPSR_NZCV) 854 /* Bits writable in user mode. */ 855 #define CPSR_USER (CPSR_NZCV | CPSR_Q | CPSR_GE) 856 /* Execution state bits. MRS read as zero, MSR writes ignored. */ 857 #define CPSR_EXEC (CPSR_T | CPSR_IT | CPSR_J | CPSR_IL) 858 /* Mask of bits which may be set by exception return copying them from SPSR */ 859 #define CPSR_ERET_MASK (~CPSR_RESERVED) 860 861 #define TTBCR_N (7U << 0) /* TTBCR.EAE==0 */ 862 #define TTBCR_T0SZ (7U << 0) /* TTBCR.EAE==1 */ 863 #define TTBCR_PD0 (1U << 4) 864 #define TTBCR_PD1 (1U << 5) 865 #define TTBCR_EPD0 (1U << 7) 866 #define TTBCR_IRGN0 (3U << 8) 867 #define TTBCR_ORGN0 (3U << 10) 868 #define TTBCR_SH0 (3U << 12) 869 #define TTBCR_T1SZ (3U << 16) 870 #define TTBCR_A1 (1U << 22) 871 #define TTBCR_EPD1 (1U << 23) 872 #define TTBCR_IRGN1 (3U << 24) 873 #define TTBCR_ORGN1 (3U << 26) 874 #define TTBCR_SH1 (1U << 28) 875 #define TTBCR_EAE (1U << 31) 876 877 /* Bit definitions for ARMv8 SPSR (PSTATE) format. 878 * Only these are valid when in AArch64 mode; in 879 * AArch32 mode SPSRs are basically CPSR-format. 880 */ 881 #define PSTATE_SP (1U) 882 #define PSTATE_M (0xFU) 883 #define PSTATE_nRW (1U << 4) 884 #define PSTATE_F (1U << 6) 885 #define PSTATE_I (1U << 7) 886 #define PSTATE_A (1U << 8) 887 #define PSTATE_D (1U << 9) 888 #define PSTATE_IL (1U << 20) 889 #define PSTATE_SS (1U << 21) 890 #define PSTATE_V (1U << 28) 891 #define PSTATE_C (1U << 29) 892 #define PSTATE_Z (1U << 30) 893 #define PSTATE_N (1U << 31) 894 #define PSTATE_NZCV (PSTATE_N | PSTATE_Z | PSTATE_C | PSTATE_V) 895 #define PSTATE_DAIF (PSTATE_D | PSTATE_A | PSTATE_I | PSTATE_F) 896 #define CACHED_PSTATE_BITS (PSTATE_NZCV | PSTATE_DAIF) 897 /* Mode values for AArch64 */ 898 #define PSTATE_MODE_EL3h 13 899 #define PSTATE_MODE_EL3t 12 900 #define PSTATE_MODE_EL2h 9 901 #define PSTATE_MODE_EL2t 8 902 #define PSTATE_MODE_EL1h 5 903 #define PSTATE_MODE_EL1t 4 904 #define PSTATE_MODE_EL0t 0 905 906 /* Map EL and handler into a PSTATE_MODE. */ 907 static inline unsigned int aarch64_pstate_mode(unsigned int el, bool handler) 908 { 909 return (el << 2) | handler; 910 } 911 912 /* Return the current PSTATE value. For the moment we don't support 32<->64 bit 913 * interprocessing, so we don't attempt to sync with the cpsr state used by 914 * the 32 bit decoder. 915 */ 916 static inline uint32_t pstate_read(CPUARMState *env) 917 { 918 int ZF; 919 920 ZF = (env->ZF == 0); 921 return (env->NF & 0x80000000) | (ZF << 30) 922 | (env->CF << 29) | ((env->VF & 0x80000000) >> 3) 923 | env->pstate | env->daif; 924 } 925 926 static inline void pstate_write(CPUARMState *env, uint32_t val) 927 { 928 env->ZF = (~val) & PSTATE_Z; 929 env->NF = val; 930 env->CF = (val >> 29) & 1; 931 env->VF = (val << 3) & 0x80000000; 932 env->daif = val & PSTATE_DAIF; 933 env->pstate = val & ~CACHED_PSTATE_BITS; 934 } 935 936 /* Return the current CPSR value. */ 937 uint32_t cpsr_read(CPUARMState *env); 938 939 typedef enum CPSRWriteType { 940 CPSRWriteByInstr = 0, /* from guest MSR or CPS */ 941 CPSRWriteExceptionReturn = 1, /* from guest exception return insn */ 942 CPSRWriteRaw = 2, /* trust values, do not switch reg banks */ 943 CPSRWriteByGDBStub = 3, /* from the GDB stub */ 944 } CPSRWriteType; 945 946 /* Set the CPSR. Note that some bits of mask must be all-set or all-clear.*/ 947 void cpsr_write(CPUARMState *env, uint32_t val, uint32_t mask, 948 CPSRWriteType write_type); 949 950 /* Return the current xPSR value. */ 951 static inline uint32_t xpsr_read(CPUARMState *env) 952 { 953 int ZF; 954 ZF = (env->ZF == 0); 955 return (env->NF & 0x80000000) | (ZF << 30) 956 | (env->CF << 29) | ((env->VF & 0x80000000) >> 3) | (env->QF << 27) 957 | (env->thumb << 24) | ((env->condexec_bits & 3) << 25) 958 | ((env->condexec_bits & 0xfc) << 8) 959 | env->v7m.exception; 960 } 961 962 /* Set the xPSR. Note that some bits of mask must be all-set or all-clear. */ 963 static inline void xpsr_write(CPUARMState *env, uint32_t val, uint32_t mask) 964 { 965 if (mask & CPSR_NZCV) { 966 env->ZF = (~val) & CPSR_Z; 967 env->NF = val; 968 env->CF = (val >> 29) & 1; 969 env->VF = (val << 3) & 0x80000000; 970 } 971 if (mask & CPSR_Q) 972 env->QF = ((val & CPSR_Q) != 0); 973 if (mask & (1 << 24)) 974 env->thumb = ((val & (1 << 24)) != 0); 975 if (mask & CPSR_IT_0_1) { 976 env->condexec_bits &= ~3; 977 env->condexec_bits |= (val >> 25) & 3; 978 } 979 if (mask & CPSR_IT_2_7) { 980 env->condexec_bits &= 3; 981 env->condexec_bits |= (val >> 8) & 0xfc; 982 } 983 if (mask & 0x1ff) { 984 env->v7m.exception = val & 0x1ff; 985 } 986 } 987 988 #define HCR_VM (1ULL << 0) 989 #define HCR_SWIO (1ULL << 1) 990 #define HCR_PTW (1ULL << 2) 991 #define HCR_FMO (1ULL << 3) 992 #define HCR_IMO (1ULL << 4) 993 #define HCR_AMO (1ULL << 5) 994 #define HCR_VF (1ULL << 6) 995 #define HCR_VI (1ULL << 7) 996 #define HCR_VSE (1ULL << 8) 997 #define HCR_FB (1ULL << 9) 998 #define HCR_BSU_MASK (3ULL << 10) 999 #define HCR_DC (1ULL << 12) 1000 #define HCR_TWI (1ULL << 13) 1001 #define HCR_TWE (1ULL << 14) 1002 #define HCR_TID0 (1ULL << 15) 1003 #define HCR_TID1 (1ULL << 16) 1004 #define HCR_TID2 (1ULL << 17) 1005 #define HCR_TID3 (1ULL << 18) 1006 #define HCR_TSC (1ULL << 19) 1007 #define HCR_TIDCP (1ULL << 20) 1008 #define HCR_TACR (1ULL << 21) 1009 #define HCR_TSW (1ULL << 22) 1010 #define HCR_TPC (1ULL << 23) 1011 #define HCR_TPU (1ULL << 24) 1012 #define HCR_TTLB (1ULL << 25) 1013 #define HCR_TVM (1ULL << 26) 1014 #define HCR_TGE (1ULL << 27) 1015 #define HCR_TDZ (1ULL << 28) 1016 #define HCR_HCD (1ULL << 29) 1017 #define HCR_TRVM (1ULL << 30) 1018 #define HCR_RW (1ULL << 31) 1019 #define HCR_CD (1ULL << 32) 1020 #define HCR_ID (1ULL << 33) 1021 #define HCR_MASK ((1ULL << 34) - 1) 1022 1023 #define SCR_NS (1U << 0) 1024 #define SCR_IRQ (1U << 1) 1025 #define SCR_FIQ (1U << 2) 1026 #define SCR_EA (1U << 3) 1027 #define SCR_FW (1U << 4) 1028 #define SCR_AW (1U << 5) 1029 #define SCR_NET (1U << 6) 1030 #define SCR_SMD (1U << 7) 1031 #define SCR_HCE (1U << 8) 1032 #define SCR_SIF (1U << 9) 1033 #define SCR_RW (1U << 10) 1034 #define SCR_ST (1U << 11) 1035 #define SCR_TWI (1U << 12) 1036 #define SCR_TWE (1U << 13) 1037 #define SCR_AARCH32_MASK (0x3fff & ~(SCR_RW | SCR_ST)) 1038 #define SCR_AARCH64_MASK (0x3fff & ~SCR_NET) 1039 1040 /* Return the current FPSCR value. */ 1041 uint32_t vfp_get_fpscr(CPUARMState *env); 1042 void vfp_set_fpscr(CPUARMState *env, uint32_t val); 1043 1044 /* For A64 the FPSCR is split into two logically distinct registers, 1045 * FPCR and FPSR. However since they still use non-overlapping bits 1046 * we store the underlying state in fpscr and just mask on read/write. 1047 */ 1048 #define FPSR_MASK 0xf800009f 1049 #define FPCR_MASK 0x07f79f00 1050 static inline uint32_t vfp_get_fpsr(CPUARMState *env) 1051 { 1052 return vfp_get_fpscr(env) & FPSR_MASK; 1053 } 1054 1055 static inline void vfp_set_fpsr(CPUARMState *env, uint32_t val) 1056 { 1057 uint32_t new_fpscr = (vfp_get_fpscr(env) & ~FPSR_MASK) | (val & FPSR_MASK); 1058 vfp_set_fpscr(env, new_fpscr); 1059 } 1060 1061 static inline uint32_t vfp_get_fpcr(CPUARMState *env) 1062 { 1063 return vfp_get_fpscr(env) & FPCR_MASK; 1064 } 1065 1066 static inline void vfp_set_fpcr(CPUARMState *env, uint32_t val) 1067 { 1068 uint32_t new_fpscr = (vfp_get_fpscr(env) & ~FPCR_MASK) | (val & FPCR_MASK); 1069 vfp_set_fpscr(env, new_fpscr); 1070 } 1071 1072 enum arm_cpu_mode { 1073 ARM_CPU_MODE_USR = 0x10, 1074 ARM_CPU_MODE_FIQ = 0x11, 1075 ARM_CPU_MODE_IRQ = 0x12, 1076 ARM_CPU_MODE_SVC = 0x13, 1077 ARM_CPU_MODE_MON = 0x16, 1078 ARM_CPU_MODE_ABT = 0x17, 1079 ARM_CPU_MODE_HYP = 0x1a, 1080 ARM_CPU_MODE_UND = 0x1b, 1081 ARM_CPU_MODE_SYS = 0x1f 1082 }; 1083 1084 /* VFP system registers. */ 1085 #define ARM_VFP_FPSID 0 1086 #define ARM_VFP_FPSCR 1 1087 #define ARM_VFP_MVFR2 5 1088 #define ARM_VFP_MVFR1 6 1089 #define ARM_VFP_MVFR0 7 1090 #define ARM_VFP_FPEXC 8 1091 #define ARM_VFP_FPINST 9 1092 #define ARM_VFP_FPINST2 10 1093 1094 /* iwMMXt coprocessor control registers. */ 1095 #define ARM_IWMMXT_wCID 0 1096 #define ARM_IWMMXT_wCon 1 1097 #define ARM_IWMMXT_wCSSF 2 1098 #define ARM_IWMMXT_wCASF 3 1099 #define ARM_IWMMXT_wCGR0 8 1100 #define ARM_IWMMXT_wCGR1 9 1101 #define ARM_IWMMXT_wCGR2 10 1102 #define ARM_IWMMXT_wCGR3 11 1103 1104 /* V7M CCR bits */ 1105 FIELD(V7M_CCR, NONBASETHRDENA, 0, 1) 1106 FIELD(V7M_CCR, USERSETMPEND, 1, 1) 1107 FIELD(V7M_CCR, UNALIGN_TRP, 3, 1) 1108 FIELD(V7M_CCR, DIV_0_TRP, 4, 1) 1109 FIELD(V7M_CCR, BFHFNMIGN, 8, 1) 1110 FIELD(V7M_CCR, STKALIGN, 9, 1) 1111 FIELD(V7M_CCR, DC, 16, 1) 1112 FIELD(V7M_CCR, IC, 17, 1) 1113 1114 /* V7M CFSR bits for MMFSR */ 1115 FIELD(V7M_CFSR, IACCVIOL, 0, 1) 1116 FIELD(V7M_CFSR, DACCVIOL, 1, 1) 1117 FIELD(V7M_CFSR, MUNSTKERR, 3, 1) 1118 FIELD(V7M_CFSR, MSTKERR, 4, 1) 1119 FIELD(V7M_CFSR, MLSPERR, 5, 1) 1120 FIELD(V7M_CFSR, MMARVALID, 7, 1) 1121 1122 /* V7M CFSR bits for BFSR */ 1123 FIELD(V7M_CFSR, IBUSERR, 8 + 0, 1) 1124 FIELD(V7M_CFSR, PRECISERR, 8 + 1, 1) 1125 FIELD(V7M_CFSR, IMPRECISERR, 8 + 2, 1) 1126 FIELD(V7M_CFSR, UNSTKERR, 8 + 3, 1) 1127 FIELD(V7M_CFSR, STKERR, 8 + 4, 1) 1128 FIELD(V7M_CFSR, LSPERR, 8 + 5, 1) 1129 FIELD(V7M_CFSR, BFARVALID, 8 + 7, 1) 1130 1131 /* V7M CFSR bits for UFSR */ 1132 FIELD(V7M_CFSR, UNDEFINSTR, 16 + 0, 1) 1133 FIELD(V7M_CFSR, INVSTATE, 16 + 1, 1) 1134 FIELD(V7M_CFSR, INVPC, 16 + 2, 1) 1135 FIELD(V7M_CFSR, NOCP, 16 + 3, 1) 1136 FIELD(V7M_CFSR, UNALIGNED, 16 + 8, 1) 1137 FIELD(V7M_CFSR, DIVBYZERO, 16 + 9, 1) 1138 1139 /* V7M HFSR bits */ 1140 FIELD(V7M_HFSR, VECTTBL, 1, 1) 1141 FIELD(V7M_HFSR, FORCED, 30, 1) 1142 FIELD(V7M_HFSR, DEBUGEVT, 31, 1) 1143 1144 /* V7M DFSR bits */ 1145 FIELD(V7M_DFSR, HALTED, 0, 1) 1146 FIELD(V7M_DFSR, BKPT, 1, 1) 1147 FIELD(V7M_DFSR, DWTTRAP, 2, 1) 1148 FIELD(V7M_DFSR, VCATCH, 3, 1) 1149 FIELD(V7M_DFSR, EXTERNAL, 4, 1) 1150 1151 /* If adding a feature bit which corresponds to a Linux ELF 1152 * HWCAP bit, remember to update the feature-bit-to-hwcap 1153 * mapping in linux-user/elfload.c:get_elf_hwcap(). 1154 */ 1155 enum arm_features { 1156 ARM_FEATURE_VFP, 1157 ARM_FEATURE_AUXCR, /* ARM1026 Auxiliary control register. */ 1158 ARM_FEATURE_XSCALE, /* Intel XScale extensions. */ 1159 ARM_FEATURE_IWMMXT, /* Intel iwMMXt extension. */ 1160 ARM_FEATURE_V6, 1161 ARM_FEATURE_V6K, 1162 ARM_FEATURE_V7, 1163 ARM_FEATURE_THUMB2, 1164 ARM_FEATURE_MPU, /* Only has Memory Protection Unit, not full MMU. */ 1165 ARM_FEATURE_VFP3, 1166 ARM_FEATURE_VFP_FP16, 1167 ARM_FEATURE_NEON, 1168 ARM_FEATURE_THUMB_DIV, /* divide supported in Thumb encoding */ 1169 ARM_FEATURE_M, /* Microcontroller profile. */ 1170 ARM_FEATURE_OMAPCP, /* OMAP specific CP15 ops handling. */ 1171 ARM_FEATURE_THUMB2EE, 1172 ARM_FEATURE_V7MP, /* v7 Multiprocessing Extensions */ 1173 ARM_FEATURE_V4T, 1174 ARM_FEATURE_V5, 1175 ARM_FEATURE_STRONGARM, 1176 ARM_FEATURE_VAPA, /* cp15 VA to PA lookups */ 1177 ARM_FEATURE_ARM_DIV, /* divide supported in ARM encoding */ 1178 ARM_FEATURE_VFP4, /* VFPv4 (implies that NEON is v2) */ 1179 ARM_FEATURE_GENERIC_TIMER, 1180 ARM_FEATURE_MVFR, /* Media and VFP Feature Registers 0 and 1 */ 1181 ARM_FEATURE_DUMMY_C15_REGS, /* RAZ/WI all of cp15 crn=15 */ 1182 ARM_FEATURE_CACHE_TEST_CLEAN, /* 926/1026 style test-and-clean ops */ 1183 ARM_FEATURE_CACHE_DIRTY_REG, /* 1136/1176 cache dirty status register */ 1184 ARM_FEATURE_CACHE_BLOCK_OPS, /* v6 optional cache block operations */ 1185 ARM_FEATURE_MPIDR, /* has cp15 MPIDR */ 1186 ARM_FEATURE_PXN, /* has Privileged Execute Never bit */ 1187 ARM_FEATURE_LPAE, /* has Large Physical Address Extension */ 1188 ARM_FEATURE_V8, 1189 ARM_FEATURE_AARCH64, /* supports 64 bit mode */ 1190 ARM_FEATURE_V8_AES, /* implements AES part of v8 Crypto Extensions */ 1191 ARM_FEATURE_CBAR, /* has cp15 CBAR */ 1192 ARM_FEATURE_CRC, /* ARMv8 CRC instructions */ 1193 ARM_FEATURE_CBAR_RO, /* has cp15 CBAR and it is read-only */ 1194 ARM_FEATURE_EL2, /* has EL2 Virtualization support */ 1195 ARM_FEATURE_EL3, /* has EL3 Secure monitor support */ 1196 ARM_FEATURE_V8_SHA1, /* implements SHA1 part of v8 Crypto Extensions */ 1197 ARM_FEATURE_V8_SHA256, /* implements SHA256 part of v8 Crypto Extensions */ 1198 ARM_FEATURE_V8_PMULL, /* implements PMULL part of v8 Crypto Extensions */ 1199 ARM_FEATURE_THUMB_DSP, /* DSP insns supported in the Thumb encodings */ 1200 ARM_FEATURE_PMU, /* has PMU support */ 1201 ARM_FEATURE_VBAR, /* has cp15 VBAR */ 1202 }; 1203 1204 static inline int arm_feature(CPUARMState *env, int feature) 1205 { 1206 return (env->features & (1ULL << feature)) != 0; 1207 } 1208 1209 #if !defined(CONFIG_USER_ONLY) 1210 /* Return true if exception levels below EL3 are in secure state, 1211 * or would be following an exception return to that level. 1212 * Unlike arm_is_secure() (which is always a question about the 1213 * _current_ state of the CPU) this doesn't care about the current 1214 * EL or mode. 1215 */ 1216 static inline bool arm_is_secure_below_el3(CPUARMState *env) 1217 { 1218 if (arm_feature(env, ARM_FEATURE_EL3)) { 1219 return !(env->cp15.scr_el3 & SCR_NS); 1220 } else { 1221 /* If EL3 is not supported then the secure state is implementation 1222 * defined, in which case QEMU defaults to non-secure. 1223 */ 1224 return false; 1225 } 1226 } 1227 1228 /* Return true if the CPU is AArch64 EL3 or AArch32 Mon */ 1229 static inline bool arm_is_el3_or_mon(CPUARMState *env) 1230 { 1231 if (arm_feature(env, ARM_FEATURE_EL3)) { 1232 if (is_a64(env) && extract32(env->pstate, 2, 2) == 3) { 1233 /* CPU currently in AArch64 state and EL3 */ 1234 return true; 1235 } else if (!is_a64(env) && 1236 (env->uncached_cpsr & CPSR_M) == ARM_CPU_MODE_MON) { 1237 /* CPU currently in AArch32 state and monitor mode */ 1238 return true; 1239 } 1240 } 1241 return false; 1242 } 1243 1244 /* Return true if the processor is in secure state */ 1245 static inline bool arm_is_secure(CPUARMState *env) 1246 { 1247 if (arm_is_el3_or_mon(env)) { 1248 return true; 1249 } 1250 return arm_is_secure_below_el3(env); 1251 } 1252 1253 #else 1254 static inline bool arm_is_secure_below_el3(CPUARMState *env) 1255 { 1256 return false; 1257 } 1258 1259 static inline bool arm_is_secure(CPUARMState *env) 1260 { 1261 return false; 1262 } 1263 #endif 1264 1265 /* Return true if the specified exception level is running in AArch64 state. */ 1266 static inline bool arm_el_is_aa64(CPUARMState *env, int el) 1267 { 1268 /* This isn't valid for EL0 (if we're in EL0, is_a64() is what you want, 1269 * and if we're not in EL0 then the state of EL0 isn't well defined.) 1270 */ 1271 assert(el >= 1 && el <= 3); 1272 bool aa64 = arm_feature(env, ARM_FEATURE_AARCH64); 1273 1274 /* The highest exception level is always at the maximum supported 1275 * register width, and then lower levels have a register width controlled 1276 * by bits in the SCR or HCR registers. 1277 */ 1278 if (el == 3) { 1279 return aa64; 1280 } 1281 1282 if (arm_feature(env, ARM_FEATURE_EL3)) { 1283 aa64 = aa64 && (env->cp15.scr_el3 & SCR_RW); 1284 } 1285 1286 if (el == 2) { 1287 return aa64; 1288 } 1289 1290 if (arm_feature(env, ARM_FEATURE_EL2) && !arm_is_secure_below_el3(env)) { 1291 aa64 = aa64 && (env->cp15.hcr_el2 & HCR_RW); 1292 } 1293 1294 return aa64; 1295 } 1296 1297 /* Function for determing whether guest cp register reads and writes should 1298 * access the secure or non-secure bank of a cp register. When EL3 is 1299 * operating in AArch32 state, the NS-bit determines whether the secure 1300 * instance of a cp register should be used. When EL3 is AArch64 (or if 1301 * it doesn't exist at all) then there is no register banking, and all 1302 * accesses are to the non-secure version. 1303 */ 1304 static inline bool access_secure_reg(CPUARMState *env) 1305 { 1306 bool ret = (arm_feature(env, ARM_FEATURE_EL3) && 1307 !arm_el_is_aa64(env, 3) && 1308 !(env->cp15.scr_el3 & SCR_NS)); 1309 1310 return ret; 1311 } 1312 1313 /* Macros for accessing a specified CP register bank */ 1314 #define A32_BANKED_REG_GET(_env, _regname, _secure) \ 1315 ((_secure) ? (_env)->cp15._regname##_s : (_env)->cp15._regname##_ns) 1316 1317 #define A32_BANKED_REG_SET(_env, _regname, _secure, _val) \ 1318 do { \ 1319 if (_secure) { \ 1320 (_env)->cp15._regname##_s = (_val); \ 1321 } else { \ 1322 (_env)->cp15._regname##_ns = (_val); \ 1323 } \ 1324 } while (0) 1325 1326 /* Macros for automatically accessing a specific CP register bank depending on 1327 * the current secure state of the system. These macros are not intended for 1328 * supporting instruction translation reads/writes as these are dependent 1329 * solely on the SCR.NS bit and not the mode. 1330 */ 1331 #define A32_BANKED_CURRENT_REG_GET(_env, _regname) \ 1332 A32_BANKED_REG_GET((_env), _regname, \ 1333 (arm_is_secure(_env) && !arm_el_is_aa64((_env), 3))) 1334 1335 #define A32_BANKED_CURRENT_REG_SET(_env, _regname, _val) \ 1336 A32_BANKED_REG_SET((_env), _regname, \ 1337 (arm_is_secure(_env) && !arm_el_is_aa64((_env), 3)), \ 1338 (_val)) 1339 1340 void arm_cpu_list(FILE *f, fprintf_function cpu_fprintf); 1341 uint32_t arm_phys_excp_target_el(CPUState *cs, uint32_t excp_idx, 1342 uint32_t cur_el, bool secure); 1343 1344 /* Interface between CPU and Interrupt controller. */ 1345 void armv7m_nvic_set_pending(void *opaque, int irq); 1346 int armv7m_nvic_acknowledge_irq(void *opaque); 1347 void armv7m_nvic_complete_irq(void *opaque, int irq); 1348 1349 /* Interface for defining coprocessor registers. 1350 * Registers are defined in tables of arm_cp_reginfo structs 1351 * which are passed to define_arm_cp_regs(). 1352 */ 1353 1354 /* When looking up a coprocessor register we look for it 1355 * via an integer which encodes all of: 1356 * coprocessor number 1357 * Crn, Crm, opc1, opc2 fields 1358 * 32 or 64 bit register (ie is it accessed via MRC/MCR 1359 * or via MRRC/MCRR?) 1360 * non-secure/secure bank (AArch32 only) 1361 * We allow 4 bits for opc1 because MRRC/MCRR have a 4 bit field. 1362 * (In this case crn and opc2 should be zero.) 1363 * For AArch64, there is no 32/64 bit size distinction; 1364 * instead all registers have a 2 bit op0, 3 bit op1 and op2, 1365 * and 4 bit CRn and CRm. The encoding patterns are chosen 1366 * to be easy to convert to and from the KVM encodings, and also 1367 * so that the hashtable can contain both AArch32 and AArch64 1368 * registers (to allow for interprocessing where we might run 1369 * 32 bit code on a 64 bit core). 1370 */ 1371 /* This bit is private to our hashtable cpreg; in KVM register 1372 * IDs the AArch64/32 distinction is the KVM_REG_ARM/ARM64 1373 * in the upper bits of the 64 bit ID. 1374 */ 1375 #define CP_REG_AA64_SHIFT 28 1376 #define CP_REG_AA64_MASK (1 << CP_REG_AA64_SHIFT) 1377 1378 /* To enable banking of coprocessor registers depending on ns-bit we 1379 * add a bit to distinguish between secure and non-secure cpregs in the 1380 * hashtable. 1381 */ 1382 #define CP_REG_NS_SHIFT 29 1383 #define CP_REG_NS_MASK (1 << CP_REG_NS_SHIFT) 1384 1385 #define ENCODE_CP_REG(cp, is64, ns, crn, crm, opc1, opc2) \ 1386 ((ns) << CP_REG_NS_SHIFT | ((cp) << 16) | ((is64) << 15) | \ 1387 ((crn) << 11) | ((crm) << 7) | ((opc1) << 3) | (opc2)) 1388 1389 #define ENCODE_AA64_CP_REG(cp, crn, crm, op0, op1, op2) \ 1390 (CP_REG_AA64_MASK | \ 1391 ((cp) << CP_REG_ARM_COPROC_SHIFT) | \ 1392 ((op0) << CP_REG_ARM64_SYSREG_OP0_SHIFT) | \ 1393 ((op1) << CP_REG_ARM64_SYSREG_OP1_SHIFT) | \ 1394 ((crn) << CP_REG_ARM64_SYSREG_CRN_SHIFT) | \ 1395 ((crm) << CP_REG_ARM64_SYSREG_CRM_SHIFT) | \ 1396 ((op2) << CP_REG_ARM64_SYSREG_OP2_SHIFT)) 1397 1398 /* Convert a full 64 bit KVM register ID to the truncated 32 bit 1399 * version used as a key for the coprocessor register hashtable 1400 */ 1401 static inline uint32_t kvm_to_cpreg_id(uint64_t kvmid) 1402 { 1403 uint32_t cpregid = kvmid; 1404 if ((kvmid & CP_REG_ARCH_MASK) == CP_REG_ARM64) { 1405 cpregid |= CP_REG_AA64_MASK; 1406 } else { 1407 if ((kvmid & CP_REG_SIZE_MASK) == CP_REG_SIZE_U64) { 1408 cpregid |= (1 << 15); 1409 } 1410 1411 /* KVM is always non-secure so add the NS flag on AArch32 register 1412 * entries. 1413 */ 1414 cpregid |= 1 << CP_REG_NS_SHIFT; 1415 } 1416 return cpregid; 1417 } 1418 1419 /* Convert a truncated 32 bit hashtable key into the full 1420 * 64 bit KVM register ID. 1421 */ 1422 static inline uint64_t cpreg_to_kvm_id(uint32_t cpregid) 1423 { 1424 uint64_t kvmid; 1425 1426 if (cpregid & CP_REG_AA64_MASK) { 1427 kvmid = cpregid & ~CP_REG_AA64_MASK; 1428 kvmid |= CP_REG_SIZE_U64 | CP_REG_ARM64; 1429 } else { 1430 kvmid = cpregid & ~(1 << 15); 1431 if (cpregid & (1 << 15)) { 1432 kvmid |= CP_REG_SIZE_U64 | CP_REG_ARM; 1433 } else { 1434 kvmid |= CP_REG_SIZE_U32 | CP_REG_ARM; 1435 } 1436 } 1437 return kvmid; 1438 } 1439 1440 /* ARMCPRegInfo type field bits. If the SPECIAL bit is set this is a 1441 * special-behaviour cp reg and bits [15..8] indicate what behaviour 1442 * it has. Otherwise it is a simple cp reg, where CONST indicates that 1443 * TCG can assume the value to be constant (ie load at translate time) 1444 * and 64BIT indicates a 64 bit wide coprocessor register. SUPPRESS_TB_END 1445 * indicates that the TB should not be ended after a write to this register 1446 * (the default is that the TB ends after cp writes). OVERRIDE permits 1447 * a register definition to override a previous definition for the 1448 * same (cp, is64, crn, crm, opc1, opc2) tuple: either the new or the 1449 * old must have the OVERRIDE bit set. 1450 * ALIAS indicates that this register is an alias view of some underlying 1451 * state which is also visible via another register, and that the other 1452 * register is handling migration and reset; registers marked ALIAS will not be 1453 * migrated but may have their state set by syncing of register state from KVM. 1454 * NO_RAW indicates that this register has no underlying state and does not 1455 * support raw access for state saving/loading; it will not be used for either 1456 * migration or KVM state synchronization. (Typically this is for "registers" 1457 * which are actually used as instructions for cache maintenance and so on.) 1458 * IO indicates that this register does I/O and therefore its accesses 1459 * need to be surrounded by gen_io_start()/gen_io_end(). In particular, 1460 * registers which implement clocks or timers require this. 1461 */ 1462 #define ARM_CP_SPECIAL 1 1463 #define ARM_CP_CONST 2 1464 #define ARM_CP_64BIT 4 1465 #define ARM_CP_SUPPRESS_TB_END 8 1466 #define ARM_CP_OVERRIDE 16 1467 #define ARM_CP_ALIAS 32 1468 #define ARM_CP_IO 64 1469 #define ARM_CP_NO_RAW 128 1470 #define ARM_CP_NOP (ARM_CP_SPECIAL | (1 << 8)) 1471 #define ARM_CP_WFI (ARM_CP_SPECIAL | (2 << 8)) 1472 #define ARM_CP_NZCV (ARM_CP_SPECIAL | (3 << 8)) 1473 #define ARM_CP_CURRENTEL (ARM_CP_SPECIAL | (4 << 8)) 1474 #define ARM_CP_DC_ZVA (ARM_CP_SPECIAL | (5 << 8)) 1475 #define ARM_LAST_SPECIAL ARM_CP_DC_ZVA 1476 /* Used only as a terminator for ARMCPRegInfo lists */ 1477 #define ARM_CP_SENTINEL 0xffff 1478 /* Mask of only the flag bits in a type field */ 1479 #define ARM_CP_FLAG_MASK 0xff 1480 1481 /* Valid values for ARMCPRegInfo state field, indicating which of 1482 * the AArch32 and AArch64 execution states this register is visible in. 1483 * If the reginfo doesn't explicitly specify then it is AArch32 only. 1484 * If the reginfo is declared to be visible in both states then a second 1485 * reginfo is synthesised for the AArch32 view of the AArch64 register, 1486 * such that the AArch32 view is the lower 32 bits of the AArch64 one. 1487 * Note that we rely on the values of these enums as we iterate through 1488 * the various states in some places. 1489 */ 1490 enum { 1491 ARM_CP_STATE_AA32 = 0, 1492 ARM_CP_STATE_AA64 = 1, 1493 ARM_CP_STATE_BOTH = 2, 1494 }; 1495 1496 /* ARM CP register secure state flags. These flags identify security state 1497 * attributes for a given CP register entry. 1498 * The existence of both or neither secure and non-secure flags indicates that 1499 * the register has both a secure and non-secure hash entry. A single one of 1500 * these flags causes the register to only be hashed for the specified 1501 * security state. 1502 * Although definitions may have any combination of the S/NS bits, each 1503 * registered entry will only have one to identify whether the entry is secure 1504 * or non-secure. 1505 */ 1506 enum { 1507 ARM_CP_SECSTATE_S = (1 << 0), /* bit[0]: Secure state register */ 1508 ARM_CP_SECSTATE_NS = (1 << 1), /* bit[1]: Non-secure state register */ 1509 }; 1510 1511 /* Return true if cptype is a valid type field. This is used to try to 1512 * catch errors where the sentinel has been accidentally left off the end 1513 * of a list of registers. 1514 */ 1515 static inline bool cptype_valid(int cptype) 1516 { 1517 return ((cptype & ~ARM_CP_FLAG_MASK) == 0) 1518 || ((cptype & ARM_CP_SPECIAL) && 1519 ((cptype & ~ARM_CP_FLAG_MASK) <= ARM_LAST_SPECIAL)); 1520 } 1521 1522 /* Access rights: 1523 * We define bits for Read and Write access for what rev C of the v7-AR ARM ARM 1524 * defines as PL0 (user), PL1 (fiq/irq/svc/abt/und/sys, ie privileged), and 1525 * PL2 (hyp). The other level which has Read and Write bits is Secure PL1 1526 * (ie any of the privileged modes in Secure state, or Monitor mode). 1527 * If a register is accessible in one privilege level it's always accessible 1528 * in higher privilege levels too. Since "Secure PL1" also follows this rule 1529 * (ie anything visible in PL2 is visible in S-PL1, some things are only 1530 * visible in S-PL1) but "Secure PL1" is a bit of a mouthful, we bend the 1531 * terminology a little and call this PL3. 1532 * In AArch64 things are somewhat simpler as the PLx bits line up exactly 1533 * with the ELx exception levels. 1534 * 1535 * If access permissions for a register are more complex than can be 1536 * described with these bits, then use a laxer set of restrictions, and 1537 * do the more restrictive/complex check inside a helper function. 1538 */ 1539 #define PL3_R 0x80 1540 #define PL3_W 0x40 1541 #define PL2_R (0x20 | PL3_R) 1542 #define PL2_W (0x10 | PL3_W) 1543 #define PL1_R (0x08 | PL2_R) 1544 #define PL1_W (0x04 | PL2_W) 1545 #define PL0_R (0x02 | PL1_R) 1546 #define PL0_W (0x01 | PL1_W) 1547 1548 #define PL3_RW (PL3_R | PL3_W) 1549 #define PL2_RW (PL2_R | PL2_W) 1550 #define PL1_RW (PL1_R | PL1_W) 1551 #define PL0_RW (PL0_R | PL0_W) 1552 1553 /* Return the highest implemented Exception Level */ 1554 static inline int arm_highest_el(CPUARMState *env) 1555 { 1556 if (arm_feature(env, ARM_FEATURE_EL3)) { 1557 return 3; 1558 } 1559 if (arm_feature(env, ARM_FEATURE_EL2)) { 1560 return 2; 1561 } 1562 return 1; 1563 } 1564 1565 /* Return the current Exception Level (as per ARMv8; note that this differs 1566 * from the ARMv7 Privilege Level). 1567 */ 1568 static inline int arm_current_el(CPUARMState *env) 1569 { 1570 if (arm_feature(env, ARM_FEATURE_M)) { 1571 return !((env->v7m.exception == 0) && (env->v7m.control & 1)); 1572 } 1573 1574 if (is_a64(env)) { 1575 return extract32(env->pstate, 2, 2); 1576 } 1577 1578 switch (env->uncached_cpsr & 0x1f) { 1579 case ARM_CPU_MODE_USR: 1580 return 0; 1581 case ARM_CPU_MODE_HYP: 1582 return 2; 1583 case ARM_CPU_MODE_MON: 1584 return 3; 1585 default: 1586 if (arm_is_secure(env) && !arm_el_is_aa64(env, 3)) { 1587 /* If EL3 is 32-bit then all secure privileged modes run in 1588 * EL3 1589 */ 1590 return 3; 1591 } 1592 1593 return 1; 1594 } 1595 } 1596 1597 typedef struct ARMCPRegInfo ARMCPRegInfo; 1598 1599 typedef enum CPAccessResult { 1600 /* Access is permitted */ 1601 CP_ACCESS_OK = 0, 1602 /* Access fails due to a configurable trap or enable which would 1603 * result in a categorized exception syndrome giving information about 1604 * the failing instruction (ie syndrome category 0x3, 0x4, 0x5, 0x6, 1605 * 0xc or 0x18). The exception is taken to the usual target EL (EL1 or 1606 * PL1 if in EL0, otherwise to the current EL). 1607 */ 1608 CP_ACCESS_TRAP = 1, 1609 /* Access fails and results in an exception syndrome 0x0 ("uncategorized"). 1610 * Note that this is not a catch-all case -- the set of cases which may 1611 * result in this failure is specifically defined by the architecture. 1612 */ 1613 CP_ACCESS_TRAP_UNCATEGORIZED = 2, 1614 /* As CP_ACCESS_TRAP, but for traps directly to EL2 or EL3 */ 1615 CP_ACCESS_TRAP_EL2 = 3, 1616 CP_ACCESS_TRAP_EL3 = 4, 1617 /* As CP_ACCESS_UNCATEGORIZED, but for traps directly to EL2 or EL3 */ 1618 CP_ACCESS_TRAP_UNCATEGORIZED_EL2 = 5, 1619 CP_ACCESS_TRAP_UNCATEGORIZED_EL3 = 6, 1620 /* Access fails and results in an exception syndrome for an FP access, 1621 * trapped directly to EL2 or EL3 1622 */ 1623 CP_ACCESS_TRAP_FP_EL2 = 7, 1624 CP_ACCESS_TRAP_FP_EL3 = 8, 1625 } CPAccessResult; 1626 1627 /* Access functions for coprocessor registers. These cannot fail and 1628 * may not raise exceptions. 1629 */ 1630 typedef uint64_t CPReadFn(CPUARMState *env, const ARMCPRegInfo *opaque); 1631 typedef void CPWriteFn(CPUARMState *env, const ARMCPRegInfo *opaque, 1632 uint64_t value); 1633 /* Access permission check functions for coprocessor registers. */ 1634 typedef CPAccessResult CPAccessFn(CPUARMState *env, 1635 const ARMCPRegInfo *opaque, 1636 bool isread); 1637 /* Hook function for register reset */ 1638 typedef void CPResetFn(CPUARMState *env, const ARMCPRegInfo *opaque); 1639 1640 #define CP_ANY 0xff 1641 1642 /* Definition of an ARM coprocessor register */ 1643 struct ARMCPRegInfo { 1644 /* Name of register (useful mainly for debugging, need not be unique) */ 1645 const char *name; 1646 /* Location of register: coprocessor number and (crn,crm,opc1,opc2) 1647 * tuple. Any of crm, opc1 and opc2 may be CP_ANY to indicate a 1648 * 'wildcard' field -- any value of that field in the MRC/MCR insn 1649 * will be decoded to this register. The register read and write 1650 * callbacks will be passed an ARMCPRegInfo with the crn/crm/opc1/opc2 1651 * used by the program, so it is possible to register a wildcard and 1652 * then behave differently on read/write if necessary. 1653 * For 64 bit registers, only crm and opc1 are relevant; crn and opc2 1654 * must both be zero. 1655 * For AArch64-visible registers, opc0 is also used. 1656 * Since there are no "coprocessors" in AArch64, cp is purely used as a 1657 * way to distinguish (for KVM's benefit) guest-visible system registers 1658 * from demuxed ones provided to preserve the "no side effects on 1659 * KVM register read/write from QEMU" semantics. cp==0x13 is guest 1660 * visible (to match KVM's encoding); cp==0 will be converted to 1661 * cp==0x13 when the ARMCPRegInfo is registered, for convenience. 1662 */ 1663 uint8_t cp; 1664 uint8_t crn; 1665 uint8_t crm; 1666 uint8_t opc0; 1667 uint8_t opc1; 1668 uint8_t opc2; 1669 /* Execution state in which this register is visible: ARM_CP_STATE_* */ 1670 int state; 1671 /* Register type: ARM_CP_* bits/values */ 1672 int type; 1673 /* Access rights: PL*_[RW] */ 1674 int access; 1675 /* Security state: ARM_CP_SECSTATE_* bits/values */ 1676 int secure; 1677 /* The opaque pointer passed to define_arm_cp_regs_with_opaque() when 1678 * this register was defined: can be used to hand data through to the 1679 * register read/write functions, since they are passed the ARMCPRegInfo*. 1680 */ 1681 void *opaque; 1682 /* Value of this register, if it is ARM_CP_CONST. Otherwise, if 1683 * fieldoffset is non-zero, the reset value of the register. 1684 */ 1685 uint64_t resetvalue; 1686 /* Offset of the field in CPUARMState for this register. 1687 * 1688 * This is not needed if either: 1689 * 1. type is ARM_CP_CONST or one of the ARM_CP_SPECIALs 1690 * 2. both readfn and writefn are specified 1691 */ 1692 ptrdiff_t fieldoffset; /* offsetof(CPUARMState, field) */ 1693 1694 /* Offsets of the secure and non-secure fields in CPUARMState for the 1695 * register if it is banked. These fields are only used during the static 1696 * registration of a register. During hashing the bank associated 1697 * with a given security state is copied to fieldoffset which is used from 1698 * there on out. 1699 * 1700 * It is expected that register definitions use either fieldoffset or 1701 * bank_fieldoffsets in the definition but not both. It is also expected 1702 * that both bank offsets are set when defining a banked register. This 1703 * use indicates that a register is banked. 1704 */ 1705 ptrdiff_t bank_fieldoffsets[2]; 1706 1707 /* Function for making any access checks for this register in addition to 1708 * those specified by the 'access' permissions bits. If NULL, no extra 1709 * checks required. The access check is performed at runtime, not at 1710 * translate time. 1711 */ 1712 CPAccessFn *accessfn; 1713 /* Function for handling reads of this register. If NULL, then reads 1714 * will be done by loading from the offset into CPUARMState specified 1715 * by fieldoffset. 1716 */ 1717 CPReadFn *readfn; 1718 /* Function for handling writes of this register. If NULL, then writes 1719 * will be done by writing to the offset into CPUARMState specified 1720 * by fieldoffset. 1721 */ 1722 CPWriteFn *writefn; 1723 /* Function for doing a "raw" read; used when we need to copy 1724 * coprocessor state to the kernel for KVM or out for 1725 * migration. This only needs to be provided if there is also a 1726 * readfn and it has side effects (for instance clear-on-read bits). 1727 */ 1728 CPReadFn *raw_readfn; 1729 /* Function for doing a "raw" write; used when we need to copy KVM 1730 * kernel coprocessor state into userspace, or for inbound 1731 * migration. This only needs to be provided if there is also a 1732 * writefn and it masks out "unwritable" bits or has write-one-to-clear 1733 * or similar behaviour. 1734 */ 1735 CPWriteFn *raw_writefn; 1736 /* Function for resetting the register. If NULL, then reset will be done 1737 * by writing resetvalue to the field specified in fieldoffset. If 1738 * fieldoffset is 0 then no reset will be done. 1739 */ 1740 CPResetFn *resetfn; 1741 }; 1742 1743 /* Macros which are lvalues for the field in CPUARMState for the 1744 * ARMCPRegInfo *ri. 1745 */ 1746 #define CPREG_FIELD32(env, ri) \ 1747 (*(uint32_t *)((char *)(env) + (ri)->fieldoffset)) 1748 #define CPREG_FIELD64(env, ri) \ 1749 (*(uint64_t *)((char *)(env) + (ri)->fieldoffset)) 1750 1751 #define REGINFO_SENTINEL { .type = ARM_CP_SENTINEL } 1752 1753 void define_arm_cp_regs_with_opaque(ARMCPU *cpu, 1754 const ARMCPRegInfo *regs, void *opaque); 1755 void define_one_arm_cp_reg_with_opaque(ARMCPU *cpu, 1756 const ARMCPRegInfo *regs, void *opaque); 1757 static inline void define_arm_cp_regs(ARMCPU *cpu, const ARMCPRegInfo *regs) 1758 { 1759 define_arm_cp_regs_with_opaque(cpu, regs, 0); 1760 } 1761 static inline void define_one_arm_cp_reg(ARMCPU *cpu, const ARMCPRegInfo *regs) 1762 { 1763 define_one_arm_cp_reg_with_opaque(cpu, regs, 0); 1764 } 1765 const ARMCPRegInfo *get_arm_cp_reginfo(GHashTable *cpregs, uint32_t encoded_cp); 1766 1767 /* CPWriteFn that can be used to implement writes-ignored behaviour */ 1768 void arm_cp_write_ignore(CPUARMState *env, const ARMCPRegInfo *ri, 1769 uint64_t value); 1770 /* CPReadFn that can be used for read-as-zero behaviour */ 1771 uint64_t arm_cp_read_zero(CPUARMState *env, const ARMCPRegInfo *ri); 1772 1773 /* CPResetFn that does nothing, for use if no reset is required even 1774 * if fieldoffset is non zero. 1775 */ 1776 void arm_cp_reset_ignore(CPUARMState *env, const ARMCPRegInfo *opaque); 1777 1778 /* Return true if this reginfo struct's field in the cpu state struct 1779 * is 64 bits wide. 1780 */ 1781 static inline bool cpreg_field_is_64bit(const ARMCPRegInfo *ri) 1782 { 1783 return (ri->state == ARM_CP_STATE_AA64) || (ri->type & ARM_CP_64BIT); 1784 } 1785 1786 static inline bool cp_access_ok(int current_el, 1787 const ARMCPRegInfo *ri, int isread) 1788 { 1789 return (ri->access >> ((current_el * 2) + isread)) & 1; 1790 } 1791 1792 /* Raw read of a coprocessor register (as needed for migration, etc) */ 1793 uint64_t read_raw_cp_reg(CPUARMState *env, const ARMCPRegInfo *ri); 1794 1795 /** 1796 * write_list_to_cpustate 1797 * @cpu: ARMCPU 1798 * 1799 * For each register listed in the ARMCPU cpreg_indexes list, write 1800 * its value from the cpreg_values list into the ARMCPUState structure. 1801 * This updates TCG's working data structures from KVM data or 1802 * from incoming migration state. 1803 * 1804 * Returns: true if all register values were updated correctly, 1805 * false if some register was unknown or could not be written. 1806 * Note that we do not stop early on failure -- we will attempt 1807 * writing all registers in the list. 1808 */ 1809 bool write_list_to_cpustate(ARMCPU *cpu); 1810 1811 /** 1812 * write_cpustate_to_list: 1813 * @cpu: ARMCPU 1814 * 1815 * For each register listed in the ARMCPU cpreg_indexes list, write 1816 * its value from the ARMCPUState structure into the cpreg_values list. 1817 * This is used to copy info from TCG's working data structures into 1818 * KVM or for outbound migration. 1819 * 1820 * Returns: true if all register values were read correctly, 1821 * false if some register was unknown or could not be read. 1822 * Note that we do not stop early on failure -- we will attempt 1823 * reading all registers in the list. 1824 */ 1825 bool write_cpustate_to_list(ARMCPU *cpu); 1826 1827 #define ARM_CPUID_TI915T 0x54029152 1828 #define ARM_CPUID_TI925T 0x54029252 1829 1830 #if defined(CONFIG_USER_ONLY) 1831 #define TARGET_PAGE_BITS 12 1832 #else 1833 /* ARMv7 and later CPUs have 4K pages minimum, but ARMv5 and v6 1834 * have to support 1K tiny pages. 1835 */ 1836 #define TARGET_PAGE_BITS_VARY 1837 #define TARGET_PAGE_BITS_MIN 10 1838 #endif 1839 1840 #if defined(TARGET_AARCH64) 1841 # define TARGET_PHYS_ADDR_SPACE_BITS 48 1842 # define TARGET_VIRT_ADDR_SPACE_BITS 64 1843 #else 1844 # define TARGET_PHYS_ADDR_SPACE_BITS 40 1845 # define TARGET_VIRT_ADDR_SPACE_BITS 32 1846 #endif 1847 1848 static inline bool arm_excp_unmasked(CPUState *cs, unsigned int excp_idx, 1849 unsigned int target_el) 1850 { 1851 CPUARMState *env = cs->env_ptr; 1852 unsigned int cur_el = arm_current_el(env); 1853 bool secure = arm_is_secure(env); 1854 bool pstate_unmasked; 1855 int8_t unmasked = 0; 1856 1857 /* Don't take exceptions if they target a lower EL. 1858 * This check should catch any exceptions that would not be taken but left 1859 * pending. 1860 */ 1861 if (cur_el > target_el) { 1862 return false; 1863 } 1864 1865 switch (excp_idx) { 1866 case EXCP_FIQ: 1867 pstate_unmasked = !(env->daif & PSTATE_F); 1868 break; 1869 1870 case EXCP_IRQ: 1871 pstate_unmasked = !(env->daif & PSTATE_I); 1872 break; 1873 1874 case EXCP_VFIQ: 1875 if (secure || !(env->cp15.hcr_el2 & HCR_FMO)) { 1876 /* VFIQs are only taken when hypervized and non-secure. */ 1877 return false; 1878 } 1879 return !(env->daif & PSTATE_F); 1880 case EXCP_VIRQ: 1881 if (secure || !(env->cp15.hcr_el2 & HCR_IMO)) { 1882 /* VIRQs are only taken when hypervized and non-secure. */ 1883 return false; 1884 } 1885 return !(env->daif & PSTATE_I); 1886 default: 1887 g_assert_not_reached(); 1888 } 1889 1890 /* Use the target EL, current execution state and SCR/HCR settings to 1891 * determine whether the corresponding CPSR bit is used to mask the 1892 * interrupt. 1893 */ 1894 if ((target_el > cur_el) && (target_el != 1)) { 1895 /* Exceptions targeting a higher EL may not be maskable */ 1896 if (arm_feature(env, ARM_FEATURE_AARCH64)) { 1897 /* 64-bit masking rules are simple: exceptions to EL3 1898 * can't be masked, and exceptions to EL2 can only be 1899 * masked from Secure state. The HCR and SCR settings 1900 * don't affect the masking logic, only the interrupt routing. 1901 */ 1902 if (target_el == 3 || !secure) { 1903 unmasked = 1; 1904 } 1905 } else { 1906 /* The old 32-bit-only environment has a more complicated 1907 * masking setup. HCR and SCR bits not only affect interrupt 1908 * routing but also change the behaviour of masking. 1909 */ 1910 bool hcr, scr; 1911 1912 switch (excp_idx) { 1913 case EXCP_FIQ: 1914 /* If FIQs are routed to EL3 or EL2 then there are cases where 1915 * we override the CPSR.F in determining if the exception is 1916 * masked or not. If neither of these are set then we fall back 1917 * to the CPSR.F setting otherwise we further assess the state 1918 * below. 1919 */ 1920 hcr = (env->cp15.hcr_el2 & HCR_FMO); 1921 scr = (env->cp15.scr_el3 & SCR_FIQ); 1922 1923 /* When EL3 is 32-bit, the SCR.FW bit controls whether the 1924 * CPSR.F bit masks FIQ interrupts when taken in non-secure 1925 * state. If SCR.FW is set then FIQs can be masked by CPSR.F 1926 * when non-secure but only when FIQs are only routed to EL3. 1927 */ 1928 scr = scr && !((env->cp15.scr_el3 & SCR_FW) && !hcr); 1929 break; 1930 case EXCP_IRQ: 1931 /* When EL3 execution state is 32-bit, if HCR.IMO is set then 1932 * we may override the CPSR.I masking when in non-secure state. 1933 * The SCR.IRQ setting has already been taken into consideration 1934 * when setting the target EL, so it does not have a further 1935 * affect here. 1936 */ 1937 hcr = (env->cp15.hcr_el2 & HCR_IMO); 1938 scr = false; 1939 break; 1940 default: 1941 g_assert_not_reached(); 1942 } 1943 1944 if ((scr || hcr) && !secure) { 1945 unmasked = 1; 1946 } 1947 } 1948 } 1949 1950 /* The PSTATE bits only mask the interrupt if we have not overriden the 1951 * ability above. 1952 */ 1953 return unmasked || pstate_unmasked; 1954 } 1955 1956 #define cpu_init(cpu_model) CPU(cpu_arm_init(cpu_model)) 1957 1958 #define cpu_signal_handler cpu_arm_signal_handler 1959 #define cpu_list arm_cpu_list 1960 1961 /* ARM has the following "translation regimes" (as the ARM ARM calls them): 1962 * 1963 * If EL3 is 64-bit: 1964 * + NonSecure EL1 & 0 stage 1 1965 * + NonSecure EL1 & 0 stage 2 1966 * + NonSecure EL2 1967 * + Secure EL1 & EL0 1968 * + Secure EL3 1969 * If EL3 is 32-bit: 1970 * + NonSecure PL1 & 0 stage 1 1971 * + NonSecure PL1 & 0 stage 2 1972 * + NonSecure PL2 1973 * + Secure PL0 & PL1 1974 * (reminder: for 32 bit EL3, Secure PL1 is *EL3*, not EL1.) 1975 * 1976 * For QEMU, an mmu_idx is not quite the same as a translation regime because: 1977 * 1. we need to split the "EL1 & 0" regimes into two mmu_idxes, because they 1978 * may differ in access permissions even if the VA->PA map is the same 1979 * 2. we want to cache in our TLB the full VA->IPA->PA lookup for a stage 1+2 1980 * translation, which means that we have one mmu_idx that deals with two 1981 * concatenated translation regimes [this sort of combined s1+2 TLB is 1982 * architecturally permitted] 1983 * 3. we don't need to allocate an mmu_idx to translations that we won't be 1984 * handling via the TLB. The only way to do a stage 1 translation without 1985 * the immediate stage 2 translation is via the ATS or AT system insns, 1986 * which can be slow-pathed and always do a page table walk. 1987 * 4. we can also safely fold together the "32 bit EL3" and "64 bit EL3" 1988 * translation regimes, because they map reasonably well to each other 1989 * and they can't both be active at the same time. 1990 * This gives us the following list of mmu_idx values: 1991 * 1992 * NS EL0 (aka NS PL0) stage 1+2 1993 * NS EL1 (aka NS PL1) stage 1+2 1994 * NS EL2 (aka NS PL2) 1995 * S EL3 (aka S PL1) 1996 * S EL0 (aka S PL0) 1997 * S EL1 (not used if EL3 is 32 bit) 1998 * NS EL0+1 stage 2 1999 * 2000 * (The last of these is an mmu_idx because we want to be able to use the TLB 2001 * for the accesses done as part of a stage 1 page table walk, rather than 2002 * having to walk the stage 2 page table over and over.) 2003 * 2004 * Our enumeration includes at the end some entries which are not "true" 2005 * mmu_idx values in that they don't have corresponding TLBs and are only 2006 * valid for doing slow path page table walks. 2007 * 2008 * The constant names here are patterned after the general style of the names 2009 * of the AT/ATS operations. 2010 * The values used are carefully arranged to make mmu_idx => EL lookup easy. 2011 */ 2012 typedef enum ARMMMUIdx { 2013 ARMMMUIdx_S12NSE0 = 0, 2014 ARMMMUIdx_S12NSE1 = 1, 2015 ARMMMUIdx_S1E2 = 2, 2016 ARMMMUIdx_S1E3 = 3, 2017 ARMMMUIdx_S1SE0 = 4, 2018 ARMMMUIdx_S1SE1 = 5, 2019 ARMMMUIdx_S2NS = 6, 2020 /* Indexes below here don't have TLBs and are used only for AT system 2021 * instructions or for the first stage of an S12 page table walk. 2022 */ 2023 ARMMMUIdx_S1NSE0 = 7, 2024 ARMMMUIdx_S1NSE1 = 8, 2025 } ARMMMUIdx; 2026 2027 #define MMU_USER_IDX 0 2028 2029 /* Return the exception level we're running at if this is our mmu_idx */ 2030 static inline int arm_mmu_idx_to_el(ARMMMUIdx mmu_idx) 2031 { 2032 assert(mmu_idx < ARMMMUIdx_S2NS); 2033 return mmu_idx & 3; 2034 } 2035 2036 /* Determine the current mmu_idx to use for normal loads/stores */ 2037 static inline int cpu_mmu_index(CPUARMState *env, bool ifetch) 2038 { 2039 int el = arm_current_el(env); 2040 2041 if (el < 2 && arm_is_secure_below_el3(env)) { 2042 return ARMMMUIdx_S1SE0 + el; 2043 } 2044 return el; 2045 } 2046 2047 /* Indexes used when registering address spaces with cpu_address_space_init */ 2048 typedef enum ARMASIdx { 2049 ARMASIdx_NS = 0, 2050 ARMASIdx_S = 1, 2051 } ARMASIdx; 2052 2053 /* Return the Exception Level targeted by debug exceptions. */ 2054 static inline int arm_debug_target_el(CPUARMState *env) 2055 { 2056 bool secure = arm_is_secure(env); 2057 bool route_to_el2 = false; 2058 2059 if (arm_feature(env, ARM_FEATURE_EL2) && !secure) { 2060 route_to_el2 = env->cp15.hcr_el2 & HCR_TGE || 2061 env->cp15.mdcr_el2 & (1 << 8); 2062 } 2063 2064 if (route_to_el2) { 2065 return 2; 2066 } else if (arm_feature(env, ARM_FEATURE_EL3) && 2067 !arm_el_is_aa64(env, 3) && secure) { 2068 return 3; 2069 } else { 2070 return 1; 2071 } 2072 } 2073 2074 static inline bool aa64_generate_debug_exceptions(CPUARMState *env) 2075 { 2076 if (arm_is_secure(env)) { 2077 /* MDCR_EL3.SDD disables debug events from Secure state */ 2078 if (extract32(env->cp15.mdcr_el3, 16, 1) != 0 2079 || arm_current_el(env) == 3) { 2080 return false; 2081 } 2082 } 2083 2084 if (arm_current_el(env) == arm_debug_target_el(env)) { 2085 if ((extract32(env->cp15.mdscr_el1, 13, 1) == 0) 2086 || (env->daif & PSTATE_D)) { 2087 return false; 2088 } 2089 } 2090 return true; 2091 } 2092 2093 static inline bool aa32_generate_debug_exceptions(CPUARMState *env) 2094 { 2095 int el = arm_current_el(env); 2096 2097 if (el == 0 && arm_el_is_aa64(env, 1)) { 2098 return aa64_generate_debug_exceptions(env); 2099 } 2100 2101 if (arm_is_secure(env)) { 2102 int spd; 2103 2104 if (el == 0 && (env->cp15.sder & 1)) { 2105 /* SDER.SUIDEN means debug exceptions from Secure EL0 2106 * are always enabled. Otherwise they are controlled by 2107 * SDCR.SPD like those from other Secure ELs. 2108 */ 2109 return true; 2110 } 2111 2112 spd = extract32(env->cp15.mdcr_el3, 14, 2); 2113 switch (spd) { 2114 case 1: 2115 /* SPD == 0b01 is reserved, but behaves as 0b00. */ 2116 case 0: 2117 /* For 0b00 we return true if external secure invasive debug 2118 * is enabled. On real hardware this is controlled by external 2119 * signals to the core. QEMU always permits debug, and behaves 2120 * as if DBGEN, SPIDEN, NIDEN and SPNIDEN are all tied high. 2121 */ 2122 return true; 2123 case 2: 2124 return false; 2125 case 3: 2126 return true; 2127 } 2128 } 2129 2130 return el != 2; 2131 } 2132 2133 /* Return true if debugging exceptions are currently enabled. 2134 * This corresponds to what in ARM ARM pseudocode would be 2135 * if UsingAArch32() then 2136 * return AArch32.GenerateDebugExceptions() 2137 * else 2138 * return AArch64.GenerateDebugExceptions() 2139 * We choose to push the if() down into this function for clarity, 2140 * since the pseudocode has it at all callsites except for the one in 2141 * CheckSoftwareStep(), where it is elided because both branches would 2142 * always return the same value. 2143 * 2144 * Parts of the pseudocode relating to EL2 and EL3 are omitted because we 2145 * don't yet implement those exception levels or their associated trap bits. 2146 */ 2147 static inline bool arm_generate_debug_exceptions(CPUARMState *env) 2148 { 2149 if (env->aarch64) { 2150 return aa64_generate_debug_exceptions(env); 2151 } else { 2152 return aa32_generate_debug_exceptions(env); 2153 } 2154 } 2155 2156 /* Is single-stepping active? (Note that the "is EL_D AArch64?" check 2157 * implicitly means this always returns false in pre-v8 CPUs.) 2158 */ 2159 static inline bool arm_singlestep_active(CPUARMState *env) 2160 { 2161 return extract32(env->cp15.mdscr_el1, 0, 1) 2162 && arm_el_is_aa64(env, arm_debug_target_el(env)) 2163 && arm_generate_debug_exceptions(env); 2164 } 2165 2166 static inline bool arm_sctlr_b(CPUARMState *env) 2167 { 2168 return 2169 /* We need not implement SCTLR.ITD in user-mode emulation, so 2170 * let linux-user ignore the fact that it conflicts with SCTLR_B. 2171 * This lets people run BE32 binaries with "-cpu any". 2172 */ 2173 #ifndef CONFIG_USER_ONLY 2174 !arm_feature(env, ARM_FEATURE_V7) && 2175 #endif 2176 (env->cp15.sctlr_el[1] & SCTLR_B) != 0; 2177 } 2178 2179 /* Return true if the processor is in big-endian mode. */ 2180 static inline bool arm_cpu_data_is_big_endian(CPUARMState *env) 2181 { 2182 int cur_el; 2183 2184 /* In 32bit endianness is determined by looking at CPSR's E bit */ 2185 if (!is_a64(env)) { 2186 return 2187 #ifdef CONFIG_USER_ONLY 2188 /* In system mode, BE32 is modelled in line with the 2189 * architecture (as word-invariant big-endianness), where loads 2190 * and stores are done little endian but from addresses which 2191 * are adjusted by XORing with the appropriate constant. So the 2192 * endianness to use for the raw data access is not affected by 2193 * SCTLR.B. 2194 * In user mode, however, we model BE32 as byte-invariant 2195 * big-endianness (because user-only code cannot tell the 2196 * difference), and so we need to use a data access endianness 2197 * that depends on SCTLR.B. 2198 */ 2199 arm_sctlr_b(env) || 2200 #endif 2201 ((env->uncached_cpsr & CPSR_E) ? 1 : 0); 2202 } 2203 2204 cur_el = arm_current_el(env); 2205 2206 if (cur_el == 0) { 2207 return (env->cp15.sctlr_el[1] & SCTLR_E0E) != 0; 2208 } 2209 2210 return (env->cp15.sctlr_el[cur_el] & SCTLR_EE) != 0; 2211 } 2212 2213 #include "exec/cpu-all.h" 2214 2215 /* Bit usage in the TB flags field: bit 31 indicates whether we are 2216 * in 32 or 64 bit mode. The meaning of the other bits depends on that. 2217 * We put flags which are shared between 32 and 64 bit mode at the top 2218 * of the word, and flags which apply to only one mode at the bottom. 2219 */ 2220 #define ARM_TBFLAG_AARCH64_STATE_SHIFT 31 2221 #define ARM_TBFLAG_AARCH64_STATE_MASK (1U << ARM_TBFLAG_AARCH64_STATE_SHIFT) 2222 #define ARM_TBFLAG_MMUIDX_SHIFT 28 2223 #define ARM_TBFLAG_MMUIDX_MASK (0x7 << ARM_TBFLAG_MMUIDX_SHIFT) 2224 #define ARM_TBFLAG_SS_ACTIVE_SHIFT 27 2225 #define ARM_TBFLAG_SS_ACTIVE_MASK (1 << ARM_TBFLAG_SS_ACTIVE_SHIFT) 2226 #define ARM_TBFLAG_PSTATE_SS_SHIFT 26 2227 #define ARM_TBFLAG_PSTATE_SS_MASK (1 << ARM_TBFLAG_PSTATE_SS_SHIFT) 2228 /* Target EL if we take a floating-point-disabled exception */ 2229 #define ARM_TBFLAG_FPEXC_EL_SHIFT 24 2230 #define ARM_TBFLAG_FPEXC_EL_MASK (0x3 << ARM_TBFLAG_FPEXC_EL_SHIFT) 2231 2232 /* Bit usage when in AArch32 state: */ 2233 #define ARM_TBFLAG_THUMB_SHIFT 0 2234 #define ARM_TBFLAG_THUMB_MASK (1 << ARM_TBFLAG_THUMB_SHIFT) 2235 #define ARM_TBFLAG_VECLEN_SHIFT 1 2236 #define ARM_TBFLAG_VECLEN_MASK (0x7 << ARM_TBFLAG_VECLEN_SHIFT) 2237 #define ARM_TBFLAG_VECSTRIDE_SHIFT 4 2238 #define ARM_TBFLAG_VECSTRIDE_MASK (0x3 << ARM_TBFLAG_VECSTRIDE_SHIFT) 2239 #define ARM_TBFLAG_VFPEN_SHIFT 7 2240 #define ARM_TBFLAG_VFPEN_MASK (1 << ARM_TBFLAG_VFPEN_SHIFT) 2241 #define ARM_TBFLAG_CONDEXEC_SHIFT 8 2242 #define ARM_TBFLAG_CONDEXEC_MASK (0xff << ARM_TBFLAG_CONDEXEC_SHIFT) 2243 #define ARM_TBFLAG_SCTLR_B_SHIFT 16 2244 #define ARM_TBFLAG_SCTLR_B_MASK (1 << ARM_TBFLAG_SCTLR_B_SHIFT) 2245 /* We store the bottom two bits of the CPAR as TB flags and handle 2246 * checks on the other bits at runtime 2247 */ 2248 #define ARM_TBFLAG_XSCALE_CPAR_SHIFT 17 2249 #define ARM_TBFLAG_XSCALE_CPAR_MASK (3 << ARM_TBFLAG_XSCALE_CPAR_SHIFT) 2250 /* Indicates whether cp register reads and writes by guest code should access 2251 * the secure or nonsecure bank of banked registers; note that this is not 2252 * the same thing as the current security state of the processor! 2253 */ 2254 #define ARM_TBFLAG_NS_SHIFT 19 2255 #define ARM_TBFLAG_NS_MASK (1 << ARM_TBFLAG_NS_SHIFT) 2256 #define ARM_TBFLAG_BE_DATA_SHIFT 20 2257 #define ARM_TBFLAG_BE_DATA_MASK (1 << ARM_TBFLAG_BE_DATA_SHIFT) 2258 2259 /* Bit usage when in AArch64 state */ 2260 #define ARM_TBFLAG_TBI0_SHIFT 0 /* TBI0 for EL0/1 or TBI for EL2/3 */ 2261 #define ARM_TBFLAG_TBI0_MASK (0x1ull << ARM_TBFLAG_TBI0_SHIFT) 2262 #define ARM_TBFLAG_TBI1_SHIFT 1 /* TBI1 for EL0/1 */ 2263 #define ARM_TBFLAG_TBI1_MASK (0x1ull << ARM_TBFLAG_TBI1_SHIFT) 2264 2265 /* some convenience accessor macros */ 2266 #define ARM_TBFLAG_AARCH64_STATE(F) \ 2267 (((F) & ARM_TBFLAG_AARCH64_STATE_MASK) >> ARM_TBFLAG_AARCH64_STATE_SHIFT) 2268 #define ARM_TBFLAG_MMUIDX(F) \ 2269 (((F) & ARM_TBFLAG_MMUIDX_MASK) >> ARM_TBFLAG_MMUIDX_SHIFT) 2270 #define ARM_TBFLAG_SS_ACTIVE(F) \ 2271 (((F) & ARM_TBFLAG_SS_ACTIVE_MASK) >> ARM_TBFLAG_SS_ACTIVE_SHIFT) 2272 #define ARM_TBFLAG_PSTATE_SS(F) \ 2273 (((F) & ARM_TBFLAG_PSTATE_SS_MASK) >> ARM_TBFLAG_PSTATE_SS_SHIFT) 2274 #define ARM_TBFLAG_FPEXC_EL(F) \ 2275 (((F) & ARM_TBFLAG_FPEXC_EL_MASK) >> ARM_TBFLAG_FPEXC_EL_SHIFT) 2276 #define ARM_TBFLAG_THUMB(F) \ 2277 (((F) & ARM_TBFLAG_THUMB_MASK) >> ARM_TBFLAG_THUMB_SHIFT) 2278 #define ARM_TBFLAG_VECLEN(F) \ 2279 (((F) & ARM_TBFLAG_VECLEN_MASK) >> ARM_TBFLAG_VECLEN_SHIFT) 2280 #define ARM_TBFLAG_VECSTRIDE(F) \ 2281 (((F) & ARM_TBFLAG_VECSTRIDE_MASK) >> ARM_TBFLAG_VECSTRIDE_SHIFT) 2282 #define ARM_TBFLAG_VFPEN(F) \ 2283 (((F) & ARM_TBFLAG_VFPEN_MASK) >> ARM_TBFLAG_VFPEN_SHIFT) 2284 #define ARM_TBFLAG_CONDEXEC(F) \ 2285 (((F) & ARM_TBFLAG_CONDEXEC_MASK) >> ARM_TBFLAG_CONDEXEC_SHIFT) 2286 #define ARM_TBFLAG_SCTLR_B(F) \ 2287 (((F) & ARM_TBFLAG_SCTLR_B_MASK) >> ARM_TBFLAG_SCTLR_B_SHIFT) 2288 #define ARM_TBFLAG_XSCALE_CPAR(F) \ 2289 (((F) & ARM_TBFLAG_XSCALE_CPAR_MASK) >> ARM_TBFLAG_XSCALE_CPAR_SHIFT) 2290 #define ARM_TBFLAG_NS(F) \ 2291 (((F) & ARM_TBFLAG_NS_MASK) >> ARM_TBFLAG_NS_SHIFT) 2292 #define ARM_TBFLAG_BE_DATA(F) \ 2293 (((F) & ARM_TBFLAG_BE_DATA_MASK) >> ARM_TBFLAG_BE_DATA_SHIFT) 2294 #define ARM_TBFLAG_TBI0(F) \ 2295 (((F) & ARM_TBFLAG_TBI0_MASK) >> ARM_TBFLAG_TBI0_SHIFT) 2296 #define ARM_TBFLAG_TBI1(F) \ 2297 (((F) & ARM_TBFLAG_TBI1_MASK) >> ARM_TBFLAG_TBI1_SHIFT) 2298 2299 static inline bool bswap_code(bool sctlr_b) 2300 { 2301 #ifdef CONFIG_USER_ONLY 2302 /* BE8 (SCTLR.B = 0, TARGET_WORDS_BIGENDIAN = 1) is mixed endian. 2303 * The invalid combination SCTLR.B=1/CPSR.E=1/TARGET_WORDS_BIGENDIAN=0 2304 * would also end up as a mixed-endian mode with BE code, LE data. 2305 */ 2306 return 2307 #ifdef TARGET_WORDS_BIGENDIAN 2308 1 ^ 2309 #endif 2310 sctlr_b; 2311 #else 2312 /* All code access in ARM is little endian, and there are no loaders 2313 * doing swaps that need to be reversed 2314 */ 2315 return 0; 2316 #endif 2317 } 2318 2319 /* Return the exception level to which FP-disabled exceptions should 2320 * be taken, or 0 if FP is enabled. 2321 */ 2322 static inline int fp_exception_el(CPUARMState *env) 2323 { 2324 int fpen; 2325 int cur_el = arm_current_el(env); 2326 2327 /* CPACR and the CPTR registers don't exist before v6, so FP is 2328 * always accessible 2329 */ 2330 if (!arm_feature(env, ARM_FEATURE_V6)) { 2331 return 0; 2332 } 2333 2334 /* The CPACR controls traps to EL1, or PL1 if we're 32 bit: 2335 * 0, 2 : trap EL0 and EL1/PL1 accesses 2336 * 1 : trap only EL0 accesses 2337 * 3 : trap no accesses 2338 */ 2339 fpen = extract32(env->cp15.cpacr_el1, 20, 2); 2340 switch (fpen) { 2341 case 0: 2342 case 2: 2343 if (cur_el == 0 || cur_el == 1) { 2344 /* Trap to PL1, which might be EL1 or EL3 */ 2345 if (arm_is_secure(env) && !arm_el_is_aa64(env, 3)) { 2346 return 3; 2347 } 2348 return 1; 2349 } 2350 if (cur_el == 3 && !is_a64(env)) { 2351 /* Secure PL1 running at EL3 */ 2352 return 3; 2353 } 2354 break; 2355 case 1: 2356 if (cur_el == 0) { 2357 return 1; 2358 } 2359 break; 2360 case 3: 2361 break; 2362 } 2363 2364 /* For the CPTR registers we don't need to guard with an ARM_FEATURE 2365 * check because zero bits in the registers mean "don't trap". 2366 */ 2367 2368 /* CPTR_EL2 : present in v7VE or v8 */ 2369 if (cur_el <= 2 && extract32(env->cp15.cptr_el[2], 10, 1) 2370 && !arm_is_secure_below_el3(env)) { 2371 /* Trap FP ops at EL2, NS-EL1 or NS-EL0 to EL2 */ 2372 return 2; 2373 } 2374 2375 /* CPTR_EL3 : present in v8 */ 2376 if (extract32(env->cp15.cptr_el[3], 10, 1)) { 2377 /* Trap all FP ops to EL3 */ 2378 return 3; 2379 } 2380 2381 return 0; 2382 } 2383 2384 #ifdef CONFIG_USER_ONLY 2385 static inline bool arm_cpu_bswap_data(CPUARMState *env) 2386 { 2387 return 2388 #ifdef TARGET_WORDS_BIGENDIAN 2389 1 ^ 2390 #endif 2391 arm_cpu_data_is_big_endian(env); 2392 } 2393 #endif 2394 2395 #ifndef CONFIG_USER_ONLY 2396 /** 2397 * arm_regime_tbi0: 2398 * @env: CPUARMState 2399 * @mmu_idx: MMU index indicating required translation regime 2400 * 2401 * Extracts the TBI0 value from the appropriate TCR for the current EL 2402 * 2403 * Returns: the TBI0 value. 2404 */ 2405 uint32_t arm_regime_tbi0(CPUARMState *env, ARMMMUIdx mmu_idx); 2406 2407 /** 2408 * arm_regime_tbi1: 2409 * @env: CPUARMState 2410 * @mmu_idx: MMU index indicating required translation regime 2411 * 2412 * Extracts the TBI1 value from the appropriate TCR for the current EL 2413 * 2414 * Returns: the TBI1 value. 2415 */ 2416 uint32_t arm_regime_tbi1(CPUARMState *env, ARMMMUIdx mmu_idx); 2417 #else 2418 /* We can't handle tagged addresses properly in user-only mode */ 2419 static inline uint32_t arm_regime_tbi0(CPUARMState *env, ARMMMUIdx mmu_idx) 2420 { 2421 return 0; 2422 } 2423 2424 static inline uint32_t arm_regime_tbi1(CPUARMState *env, ARMMMUIdx mmu_idx) 2425 { 2426 return 0; 2427 } 2428 #endif 2429 2430 static inline void cpu_get_tb_cpu_state(CPUARMState *env, target_ulong *pc, 2431 target_ulong *cs_base, uint32_t *flags) 2432 { 2433 ARMMMUIdx mmu_idx = cpu_mmu_index(env, false); 2434 if (is_a64(env)) { 2435 *pc = env->pc; 2436 *flags = ARM_TBFLAG_AARCH64_STATE_MASK; 2437 /* Get control bits for tagged addresses */ 2438 *flags |= (arm_regime_tbi0(env, mmu_idx) << ARM_TBFLAG_TBI0_SHIFT); 2439 *flags |= (arm_regime_tbi1(env, mmu_idx) << ARM_TBFLAG_TBI1_SHIFT); 2440 } else { 2441 *pc = env->regs[15]; 2442 *flags = (env->thumb << ARM_TBFLAG_THUMB_SHIFT) 2443 | (env->vfp.vec_len << ARM_TBFLAG_VECLEN_SHIFT) 2444 | (env->vfp.vec_stride << ARM_TBFLAG_VECSTRIDE_SHIFT) 2445 | (env->condexec_bits << ARM_TBFLAG_CONDEXEC_SHIFT) 2446 | (arm_sctlr_b(env) << ARM_TBFLAG_SCTLR_B_SHIFT); 2447 if (!(access_secure_reg(env))) { 2448 *flags |= ARM_TBFLAG_NS_MASK; 2449 } 2450 if (env->vfp.xregs[ARM_VFP_FPEXC] & (1 << 30) 2451 || arm_el_is_aa64(env, 1)) { 2452 *flags |= ARM_TBFLAG_VFPEN_MASK; 2453 } 2454 *flags |= (extract32(env->cp15.c15_cpar, 0, 2) 2455 << ARM_TBFLAG_XSCALE_CPAR_SHIFT); 2456 } 2457 2458 *flags |= (mmu_idx << ARM_TBFLAG_MMUIDX_SHIFT); 2459 2460 /* The SS_ACTIVE and PSTATE_SS bits correspond to the state machine 2461 * states defined in the ARM ARM for software singlestep: 2462 * SS_ACTIVE PSTATE.SS State 2463 * 0 x Inactive (the TB flag for SS is always 0) 2464 * 1 0 Active-pending 2465 * 1 1 Active-not-pending 2466 */ 2467 if (arm_singlestep_active(env)) { 2468 *flags |= ARM_TBFLAG_SS_ACTIVE_MASK; 2469 if (is_a64(env)) { 2470 if (env->pstate & PSTATE_SS) { 2471 *flags |= ARM_TBFLAG_PSTATE_SS_MASK; 2472 } 2473 } else { 2474 if (env->uncached_cpsr & PSTATE_SS) { 2475 *flags |= ARM_TBFLAG_PSTATE_SS_MASK; 2476 } 2477 } 2478 } 2479 if (arm_cpu_data_is_big_endian(env)) { 2480 *flags |= ARM_TBFLAG_BE_DATA_MASK; 2481 } 2482 *flags |= fp_exception_el(env) << ARM_TBFLAG_FPEXC_EL_SHIFT; 2483 2484 *cs_base = 0; 2485 } 2486 2487 enum { 2488 QEMU_PSCI_CONDUIT_DISABLED = 0, 2489 QEMU_PSCI_CONDUIT_SMC = 1, 2490 QEMU_PSCI_CONDUIT_HVC = 2, 2491 }; 2492 2493 #ifndef CONFIG_USER_ONLY 2494 /* Return the address space index to use for a memory access */ 2495 static inline int arm_asidx_from_attrs(CPUState *cs, MemTxAttrs attrs) 2496 { 2497 return attrs.secure ? ARMASIdx_S : ARMASIdx_NS; 2498 } 2499 2500 /* Return the AddressSpace to use for a memory access 2501 * (which depends on whether the access is S or NS, and whether 2502 * the board gave us a separate AddressSpace for S accesses). 2503 */ 2504 static inline AddressSpace *arm_addressspace(CPUState *cs, MemTxAttrs attrs) 2505 { 2506 return cpu_get_address_space(cs, arm_asidx_from_attrs(cs, attrs)); 2507 } 2508 #endif 2509 2510 /** 2511 * arm_register_el_change_hook: 2512 * Register a hook function which will be called back whenever this 2513 * CPU changes exception level or mode. The hook function will be 2514 * passed a pointer to the ARMCPU and the opaque data pointer passed 2515 * to this function when the hook was registered. 2516 * 2517 * Note that we currently only support registering a single hook function, 2518 * and will assert if this function is called twice. 2519 * This facility is intended for the use of the GICv3 emulation. 2520 */ 2521 void arm_register_el_change_hook(ARMCPU *cpu, ARMELChangeHook *hook, 2522 void *opaque); 2523 2524 /** 2525 * arm_get_el_change_hook_opaque: 2526 * Return the opaque data that will be used by the el_change_hook 2527 * for this CPU. 2528 */ 2529 static inline void *arm_get_el_change_hook_opaque(ARMCPU *cpu) 2530 { 2531 return cpu->el_change_hook_opaque; 2532 } 2533 2534 #endif 2535