1 /* 2 * ARM virtual CPU header 3 * 4 * Copyright (c) 2003 Fabrice Bellard 5 * 6 * This library is free software; you can redistribute it and/or 7 * modify it under the terms of the GNU Lesser General Public 8 * License as published by the Free Software Foundation; either 9 * version 2.1 of the License, or (at your option) any later version. 10 * 11 * This library is distributed in the hope that it will be useful, 12 * but WITHOUT ANY WARRANTY; without even the implied warranty of 13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU 14 * Lesser General Public License for more details. 15 * 16 * You should have received a copy of the GNU Lesser General Public 17 * License along with this library; if not, see <http://www.gnu.org/licenses/>. 18 */ 19 20 #ifndef ARM_CPU_H 21 #define ARM_CPU_H 22 23 #include "kvm-consts.h" 24 #include "qemu/cpu-float.h" 25 #include "hw/registerfields.h" 26 #include "cpu-qom.h" 27 #include "exec/cpu-defs.h" 28 #include "qapi/qapi-types-common.h" 29 30 /* ARM processors have a weak memory model */ 31 #define TCG_GUEST_DEFAULT_MO (0) 32 33 #ifdef TARGET_AARCH64 34 #define KVM_HAVE_MCE_INJECTION 1 35 #endif 36 37 #define EXCP_UDEF 1 /* undefined instruction */ 38 #define EXCP_SWI 2 /* software interrupt */ 39 #define EXCP_PREFETCH_ABORT 3 40 #define EXCP_DATA_ABORT 4 41 #define EXCP_IRQ 5 42 #define EXCP_FIQ 6 43 #define EXCP_BKPT 7 44 #define EXCP_EXCEPTION_EXIT 8 /* Return from v7M exception. */ 45 #define EXCP_KERNEL_TRAP 9 /* Jumped to kernel code page. */ 46 #define EXCP_HVC 11 /* HyperVisor Call */ 47 #define EXCP_HYP_TRAP 12 48 #define EXCP_SMC 13 /* Secure Monitor Call */ 49 #define EXCP_VIRQ 14 50 #define EXCP_VFIQ 15 51 #define EXCP_SEMIHOST 16 /* semihosting call */ 52 #define EXCP_NOCP 17 /* v7M NOCP UsageFault */ 53 #define EXCP_INVSTATE 18 /* v7M INVSTATE UsageFault */ 54 #define EXCP_STKOF 19 /* v8M STKOF UsageFault */ 55 #define EXCP_LAZYFP 20 /* v7M fault during lazy FP stacking */ 56 #define EXCP_LSERR 21 /* v8M LSERR SecureFault */ 57 #define EXCP_UNALIGNED 22 /* v7M UNALIGNED UsageFault */ 58 #define EXCP_DIVBYZERO 23 /* v7M DIVBYZERO UsageFault */ 59 #define EXCP_VSERR 24 60 /* NB: add new EXCP_ defines to the array in arm_log_exception() too */ 61 62 #define ARMV7M_EXCP_RESET 1 63 #define ARMV7M_EXCP_NMI 2 64 #define ARMV7M_EXCP_HARD 3 65 #define ARMV7M_EXCP_MEM 4 66 #define ARMV7M_EXCP_BUS 5 67 #define ARMV7M_EXCP_USAGE 6 68 #define ARMV7M_EXCP_SECURE 7 69 #define ARMV7M_EXCP_SVC 11 70 #define ARMV7M_EXCP_DEBUG 12 71 #define ARMV7M_EXCP_PENDSV 14 72 #define ARMV7M_EXCP_SYSTICK 15 73 74 /* For M profile, some registers are banked secure vs non-secure; 75 * these are represented as a 2-element array where the first element 76 * is the non-secure copy and the second is the secure copy. 77 * When the CPU does not have implement the security extension then 78 * only the first element is used. 79 * This means that the copy for the current security state can be 80 * accessed via env->registerfield[env->v7m.secure] (whether the security 81 * extension is implemented or not). 82 */ 83 enum { 84 M_REG_NS = 0, 85 M_REG_S = 1, 86 M_REG_NUM_BANKS = 2, 87 }; 88 89 /* ARM-specific interrupt pending bits. */ 90 #define CPU_INTERRUPT_FIQ CPU_INTERRUPT_TGT_EXT_1 91 #define CPU_INTERRUPT_VIRQ CPU_INTERRUPT_TGT_EXT_2 92 #define CPU_INTERRUPT_VFIQ CPU_INTERRUPT_TGT_EXT_3 93 #define CPU_INTERRUPT_VSERR CPU_INTERRUPT_TGT_INT_0 94 95 /* The usual mapping for an AArch64 system register to its AArch32 96 * counterpart is for the 32 bit world to have access to the lower 97 * half only (with writes leaving the upper half untouched). It's 98 * therefore useful to be able to pass TCG the offset of the least 99 * significant half of a uint64_t struct member. 100 */ 101 #if HOST_BIG_ENDIAN 102 #define offsetoflow32(S, M) (offsetof(S, M) + sizeof(uint32_t)) 103 #define offsetofhigh32(S, M) offsetof(S, M) 104 #else 105 #define offsetoflow32(S, M) offsetof(S, M) 106 #define offsetofhigh32(S, M) (offsetof(S, M) + sizeof(uint32_t)) 107 #endif 108 109 /* Meanings of the ARMCPU object's four inbound GPIO lines */ 110 #define ARM_CPU_IRQ 0 111 #define ARM_CPU_FIQ 1 112 #define ARM_CPU_VIRQ 2 113 #define ARM_CPU_VFIQ 3 114 115 /* ARM-specific extra insn start words: 116 * 1: Conditional execution bits 117 * 2: Partial exception syndrome for data aborts 118 */ 119 #define TARGET_INSN_START_EXTRA_WORDS 2 120 121 /* The 2nd extra word holding syndrome info for data aborts does not use 122 * the upper 6 bits nor the lower 14 bits. We mask and shift it down to 123 * help the sleb128 encoder do a better job. 124 * When restoring the CPU state, we shift it back up. 125 */ 126 #define ARM_INSN_START_WORD2_MASK ((1 << 26) - 1) 127 #define ARM_INSN_START_WORD2_SHIFT 14 128 129 /* We currently assume float and double are IEEE single and double 130 precision respectively. 131 Doing runtime conversions is tricky because VFP registers may contain 132 integer values (eg. as the result of a FTOSI instruction). 133 s<2n> maps to the least significant half of d<n> 134 s<2n+1> maps to the most significant half of d<n> 135 */ 136 137 /** 138 * DynamicGDBXMLInfo: 139 * @desc: Contains the XML descriptions. 140 * @num: Number of the registers in this XML seen by GDB. 141 * @data: A union with data specific to the set of registers 142 * @cpregs_keys: Array that contains the corresponding Key of 143 * a given cpreg with the same order of the cpreg 144 * in the XML description. 145 */ 146 typedef struct DynamicGDBXMLInfo { 147 char *desc; 148 int num; 149 union { 150 struct { 151 uint32_t *keys; 152 } cpregs; 153 } data; 154 } DynamicGDBXMLInfo; 155 156 /* CPU state for each instance of a generic timer (in cp15 c14) */ 157 typedef struct ARMGenericTimer { 158 uint64_t cval; /* Timer CompareValue register */ 159 uint64_t ctl; /* Timer Control register */ 160 } ARMGenericTimer; 161 162 #define GTIMER_PHYS 0 163 #define GTIMER_VIRT 1 164 #define GTIMER_HYP 2 165 #define GTIMER_SEC 3 166 #define GTIMER_HYPVIRT 4 167 #define NUM_GTIMERS 5 168 169 #define VTCR_NSW (1u << 29) 170 #define VTCR_NSA (1u << 30) 171 #define VSTCR_SW VTCR_NSW 172 #define VSTCR_SA VTCR_NSA 173 174 /* Define a maximum sized vector register. 175 * For 32-bit, this is a 128-bit NEON/AdvSIMD register. 176 * For 64-bit, this is a 2048-bit SVE register. 177 * 178 * Note that the mapping between S, D, and Q views of the register bank 179 * differs between AArch64 and AArch32. 180 * In AArch32: 181 * Qn = regs[n].d[1]:regs[n].d[0] 182 * Dn = regs[n / 2].d[n & 1] 183 * Sn = regs[n / 4].d[n % 4 / 2], 184 * bits 31..0 for even n, and bits 63..32 for odd n 185 * (and regs[16] to regs[31] are inaccessible) 186 * In AArch64: 187 * Zn = regs[n].d[*] 188 * Qn = regs[n].d[1]:regs[n].d[0] 189 * Dn = regs[n].d[0] 190 * Sn = regs[n].d[0] bits 31..0 191 * Hn = regs[n].d[0] bits 15..0 192 * 193 * This corresponds to the architecturally defined mapping between 194 * the two execution states, and means we do not need to explicitly 195 * map these registers when changing states. 196 * 197 * Align the data for use with TCG host vector operations. 198 */ 199 200 #ifdef TARGET_AARCH64 201 # define ARM_MAX_VQ 16 202 #else 203 # define ARM_MAX_VQ 1 204 #endif 205 206 typedef struct ARMVectorReg { 207 uint64_t d[2 * ARM_MAX_VQ] QEMU_ALIGNED(16); 208 } ARMVectorReg; 209 210 #ifdef TARGET_AARCH64 211 /* In AArch32 mode, predicate registers do not exist at all. */ 212 typedef struct ARMPredicateReg { 213 uint64_t p[DIV_ROUND_UP(2 * ARM_MAX_VQ, 8)] QEMU_ALIGNED(16); 214 } ARMPredicateReg; 215 216 /* In AArch32 mode, PAC keys do not exist at all. */ 217 typedef struct ARMPACKey { 218 uint64_t lo, hi; 219 } ARMPACKey; 220 #endif 221 222 /* See the commentary above the TBFLAG field definitions. */ 223 typedef struct CPUARMTBFlags { 224 uint32_t flags; 225 target_ulong flags2; 226 } CPUARMTBFlags; 227 228 typedef struct CPUArchState { 229 /* Regs for current mode. */ 230 uint32_t regs[16]; 231 232 /* 32/64 switch only happens when taking and returning from 233 * exceptions so the overlap semantics are taken care of then 234 * instead of having a complicated union. 235 */ 236 /* Regs for A64 mode. */ 237 uint64_t xregs[32]; 238 uint64_t pc; 239 /* PSTATE isn't an architectural register for ARMv8. However, it is 240 * convenient for us to assemble the underlying state into a 32 bit format 241 * identical to the architectural format used for the SPSR. (This is also 242 * what the Linux kernel's 'pstate' field in signal handlers and KVM's 243 * 'pstate' register are.) Of the PSTATE bits: 244 * NZCV are kept in the split out env->CF/VF/NF/ZF, (which have the same 245 * semantics as for AArch32, as described in the comments on each field) 246 * nRW (also known as M[4]) is kept, inverted, in env->aarch64 247 * DAIF (exception masks) are kept in env->daif 248 * BTYPE is kept in env->btype 249 * SM and ZA are kept in env->svcr 250 * all other bits are stored in their correct places in env->pstate 251 */ 252 uint32_t pstate; 253 bool aarch64; /* True if CPU is in aarch64 state; inverse of PSTATE.nRW */ 254 bool thumb; /* True if CPU is in thumb mode; cpsr[5] */ 255 256 /* Cached TBFLAGS state. See below for which bits are included. */ 257 CPUARMTBFlags hflags; 258 259 /* Frequently accessed CPSR bits are stored separately for efficiency. 260 This contains all the other bits. Use cpsr_{read,write} to access 261 the whole CPSR. */ 262 uint32_t uncached_cpsr; 263 uint32_t spsr; 264 265 /* Banked registers. */ 266 uint64_t banked_spsr[8]; 267 uint32_t banked_r13[8]; 268 uint32_t banked_r14[8]; 269 270 /* These hold r8-r12. */ 271 uint32_t usr_regs[5]; 272 uint32_t fiq_regs[5]; 273 274 /* cpsr flag cache for faster execution */ 275 uint32_t CF; /* 0 or 1 */ 276 uint32_t VF; /* V is the bit 31. All other bits are undefined */ 277 uint32_t NF; /* N is bit 31. All other bits are undefined. */ 278 uint32_t ZF; /* Z set if zero. */ 279 uint32_t QF; /* 0 or 1 */ 280 uint32_t GE; /* cpsr[19:16] */ 281 uint32_t condexec_bits; /* IT bits. cpsr[15:10,26:25]. */ 282 uint32_t btype; /* BTI branch type. spsr[11:10]. */ 283 uint64_t daif; /* exception masks, in the bits they are in PSTATE */ 284 uint64_t svcr; /* PSTATE.{SM,ZA} in the bits they are in SVCR */ 285 286 uint64_t elr_el[4]; /* AArch64 exception link regs */ 287 uint64_t sp_el[4]; /* AArch64 banked stack pointers */ 288 289 /* System control coprocessor (cp15) */ 290 struct { 291 uint32_t c0_cpuid; 292 union { /* Cache size selection */ 293 struct { 294 uint64_t _unused_csselr0; 295 uint64_t csselr_ns; 296 uint64_t _unused_csselr1; 297 uint64_t csselr_s; 298 }; 299 uint64_t csselr_el[4]; 300 }; 301 union { /* System control register. */ 302 struct { 303 uint64_t _unused_sctlr; 304 uint64_t sctlr_ns; 305 uint64_t hsctlr; 306 uint64_t sctlr_s; 307 }; 308 uint64_t sctlr_el[4]; 309 }; 310 uint64_t cpacr_el1; /* Architectural feature access control register */ 311 uint64_t cptr_el[4]; /* ARMv8 feature trap registers */ 312 uint32_t c1_xscaleauxcr; /* XScale auxiliary control register. */ 313 uint64_t sder; /* Secure debug enable register. */ 314 uint32_t nsacr; /* Non-secure access control register. */ 315 union { /* MMU translation table base 0. */ 316 struct { 317 uint64_t _unused_ttbr0_0; 318 uint64_t ttbr0_ns; 319 uint64_t _unused_ttbr0_1; 320 uint64_t ttbr0_s; 321 }; 322 uint64_t ttbr0_el[4]; 323 }; 324 union { /* MMU translation table base 1. */ 325 struct { 326 uint64_t _unused_ttbr1_0; 327 uint64_t ttbr1_ns; 328 uint64_t _unused_ttbr1_1; 329 uint64_t ttbr1_s; 330 }; 331 uint64_t ttbr1_el[4]; 332 }; 333 uint64_t vttbr_el2; /* Virtualization Translation Table Base. */ 334 uint64_t vsttbr_el2; /* Secure Virtualization Translation Table. */ 335 /* MMU translation table base control. */ 336 uint64_t tcr_el[4]; 337 uint64_t vtcr_el2; /* Virtualization Translation Control. */ 338 uint64_t vstcr_el2; /* Secure Virtualization Translation Control. */ 339 uint32_t c2_data; /* MPU data cacheable bits. */ 340 uint32_t c2_insn; /* MPU instruction cacheable bits. */ 341 union { /* MMU domain access control register 342 * MPU write buffer control. 343 */ 344 struct { 345 uint64_t dacr_ns; 346 uint64_t dacr_s; 347 }; 348 struct { 349 uint64_t dacr32_el2; 350 }; 351 }; 352 uint32_t pmsav5_data_ap; /* PMSAv5 MPU data access permissions */ 353 uint32_t pmsav5_insn_ap; /* PMSAv5 MPU insn access permissions */ 354 uint64_t hcr_el2; /* Hypervisor configuration register */ 355 uint64_t hcrx_el2; /* Extended Hypervisor configuration register */ 356 uint64_t scr_el3; /* Secure configuration register. */ 357 union { /* Fault status registers. */ 358 struct { 359 uint64_t ifsr_ns; 360 uint64_t ifsr_s; 361 }; 362 struct { 363 uint64_t ifsr32_el2; 364 }; 365 }; 366 union { 367 struct { 368 uint64_t _unused_dfsr; 369 uint64_t dfsr_ns; 370 uint64_t hsr; 371 uint64_t dfsr_s; 372 }; 373 uint64_t esr_el[4]; 374 }; 375 uint32_t c6_region[8]; /* MPU base/size registers. */ 376 union { /* Fault address registers. */ 377 struct { 378 uint64_t _unused_far0; 379 #if HOST_BIG_ENDIAN 380 uint32_t ifar_ns; 381 uint32_t dfar_ns; 382 uint32_t ifar_s; 383 uint32_t dfar_s; 384 #else 385 uint32_t dfar_ns; 386 uint32_t ifar_ns; 387 uint32_t dfar_s; 388 uint32_t ifar_s; 389 #endif 390 uint64_t _unused_far3; 391 }; 392 uint64_t far_el[4]; 393 }; 394 uint64_t hpfar_el2; 395 uint64_t hstr_el2; 396 union { /* Translation result. */ 397 struct { 398 uint64_t _unused_par_0; 399 uint64_t par_ns; 400 uint64_t _unused_par_1; 401 uint64_t par_s; 402 }; 403 uint64_t par_el[4]; 404 }; 405 406 uint32_t c9_insn; /* Cache lockdown registers. */ 407 uint32_t c9_data; 408 uint64_t c9_pmcr; /* performance monitor control register */ 409 uint64_t c9_pmcnten; /* perf monitor counter enables */ 410 uint64_t c9_pmovsr; /* perf monitor overflow status */ 411 uint64_t c9_pmuserenr; /* perf monitor user enable */ 412 uint64_t c9_pmselr; /* perf monitor counter selection register */ 413 uint64_t c9_pminten; /* perf monitor interrupt enables */ 414 union { /* Memory attribute redirection */ 415 struct { 416 #if HOST_BIG_ENDIAN 417 uint64_t _unused_mair_0; 418 uint32_t mair1_ns; 419 uint32_t mair0_ns; 420 uint64_t _unused_mair_1; 421 uint32_t mair1_s; 422 uint32_t mair0_s; 423 #else 424 uint64_t _unused_mair_0; 425 uint32_t mair0_ns; 426 uint32_t mair1_ns; 427 uint64_t _unused_mair_1; 428 uint32_t mair0_s; 429 uint32_t mair1_s; 430 #endif 431 }; 432 uint64_t mair_el[4]; 433 }; 434 union { /* vector base address register */ 435 struct { 436 uint64_t _unused_vbar; 437 uint64_t vbar_ns; 438 uint64_t hvbar; 439 uint64_t vbar_s; 440 }; 441 uint64_t vbar_el[4]; 442 }; 443 uint32_t mvbar; /* (monitor) vector base address register */ 444 uint64_t rvbar; /* rvbar sampled from rvbar property at reset */ 445 struct { /* FCSE PID. */ 446 uint32_t fcseidr_ns; 447 uint32_t fcseidr_s; 448 }; 449 union { /* Context ID. */ 450 struct { 451 uint64_t _unused_contextidr_0; 452 uint64_t contextidr_ns; 453 uint64_t _unused_contextidr_1; 454 uint64_t contextidr_s; 455 }; 456 uint64_t contextidr_el[4]; 457 }; 458 union { /* User RW Thread register. */ 459 struct { 460 uint64_t tpidrurw_ns; 461 uint64_t tpidrprw_ns; 462 uint64_t htpidr; 463 uint64_t _tpidr_el3; 464 }; 465 uint64_t tpidr_el[4]; 466 }; 467 uint64_t tpidr2_el0; 468 /* The secure banks of these registers don't map anywhere */ 469 uint64_t tpidrurw_s; 470 uint64_t tpidrprw_s; 471 uint64_t tpidruro_s; 472 473 union { /* User RO Thread register. */ 474 uint64_t tpidruro_ns; 475 uint64_t tpidrro_el[1]; 476 }; 477 uint64_t c14_cntfrq; /* Counter Frequency register */ 478 uint64_t c14_cntkctl; /* Timer Control register */ 479 uint32_t cnthctl_el2; /* Counter/Timer Hyp Control register */ 480 uint64_t cntvoff_el2; /* Counter Virtual Offset register */ 481 ARMGenericTimer c14_timer[NUM_GTIMERS]; 482 uint32_t c15_cpar; /* XScale Coprocessor Access Register */ 483 uint32_t c15_ticonfig; /* TI925T configuration byte. */ 484 uint32_t c15_i_max; /* Maximum D-cache dirty line index. */ 485 uint32_t c15_i_min; /* Minimum D-cache dirty line index. */ 486 uint32_t c15_threadid; /* TI debugger thread-ID. */ 487 uint32_t c15_config_base_address; /* SCU base address. */ 488 uint32_t c15_diagnostic; /* diagnostic register */ 489 uint32_t c15_power_diagnostic; 490 uint32_t c15_power_control; /* power control */ 491 uint64_t dbgbvr[16]; /* breakpoint value registers */ 492 uint64_t dbgbcr[16]; /* breakpoint control registers */ 493 uint64_t dbgwvr[16]; /* watchpoint value registers */ 494 uint64_t dbgwcr[16]; /* watchpoint control registers */ 495 uint64_t mdscr_el1; 496 uint64_t oslsr_el1; /* OS Lock Status */ 497 uint64_t osdlr_el1; /* OS DoubleLock status */ 498 uint64_t mdcr_el2; 499 uint64_t mdcr_el3; 500 /* Stores the architectural value of the counter *the last time it was 501 * updated* by pmccntr_op_start. Accesses should always be surrounded 502 * by pmccntr_op_start/pmccntr_op_finish to guarantee the latest 503 * architecturally-correct value is being read/set. 504 */ 505 uint64_t c15_ccnt; 506 /* Stores the delta between the architectural value and the underlying 507 * cycle count during normal operation. It is used to update c15_ccnt 508 * to be the correct architectural value before accesses. During 509 * accesses, c15_ccnt_delta contains the underlying count being used 510 * for the access, after which it reverts to the delta value in 511 * pmccntr_op_finish. 512 */ 513 uint64_t c15_ccnt_delta; 514 uint64_t c14_pmevcntr[31]; 515 uint64_t c14_pmevcntr_delta[31]; 516 uint64_t c14_pmevtyper[31]; 517 uint64_t pmccfiltr_el0; /* Performance Monitor Filter Register */ 518 uint64_t vpidr_el2; /* Virtualization Processor ID Register */ 519 uint64_t vmpidr_el2; /* Virtualization Multiprocessor ID Register */ 520 uint64_t tfsr_el[4]; /* tfsre0_el1 is index 0. */ 521 uint64_t gcr_el1; 522 uint64_t rgsr_el1; 523 524 /* Minimal RAS registers */ 525 uint64_t disr_el1; 526 uint64_t vdisr_el2; 527 uint64_t vsesr_el2; 528 } cp15; 529 530 struct { 531 /* M profile has up to 4 stack pointers: 532 * a Main Stack Pointer and a Process Stack Pointer for each 533 * of the Secure and Non-Secure states. (If the CPU doesn't support 534 * the security extension then it has only two SPs.) 535 * In QEMU we always store the currently active SP in regs[13], 536 * and the non-active SP for the current security state in 537 * v7m.other_sp. The stack pointers for the inactive security state 538 * are stored in other_ss_msp and other_ss_psp. 539 * switch_v7m_security_state() is responsible for rearranging them 540 * when we change security state. 541 */ 542 uint32_t other_sp; 543 uint32_t other_ss_msp; 544 uint32_t other_ss_psp; 545 uint32_t vecbase[M_REG_NUM_BANKS]; 546 uint32_t basepri[M_REG_NUM_BANKS]; 547 uint32_t control[M_REG_NUM_BANKS]; 548 uint32_t ccr[M_REG_NUM_BANKS]; /* Configuration and Control */ 549 uint32_t cfsr[M_REG_NUM_BANKS]; /* Configurable Fault Status */ 550 uint32_t hfsr; /* HardFault Status */ 551 uint32_t dfsr; /* Debug Fault Status Register */ 552 uint32_t sfsr; /* Secure Fault Status Register */ 553 uint32_t mmfar[M_REG_NUM_BANKS]; /* MemManage Fault Address */ 554 uint32_t bfar; /* BusFault Address */ 555 uint32_t sfar; /* Secure Fault Address Register */ 556 unsigned mpu_ctrl[M_REG_NUM_BANKS]; /* MPU_CTRL */ 557 int exception; 558 uint32_t primask[M_REG_NUM_BANKS]; 559 uint32_t faultmask[M_REG_NUM_BANKS]; 560 uint32_t aircr; /* only holds r/w state if security extn implemented */ 561 uint32_t secure; /* Is CPU in Secure state? (not guest visible) */ 562 uint32_t csselr[M_REG_NUM_BANKS]; 563 uint32_t scr[M_REG_NUM_BANKS]; 564 uint32_t msplim[M_REG_NUM_BANKS]; 565 uint32_t psplim[M_REG_NUM_BANKS]; 566 uint32_t fpcar[M_REG_NUM_BANKS]; 567 uint32_t fpccr[M_REG_NUM_BANKS]; 568 uint32_t fpdscr[M_REG_NUM_BANKS]; 569 uint32_t cpacr[M_REG_NUM_BANKS]; 570 uint32_t nsacr; 571 uint32_t ltpsize; 572 uint32_t vpr; 573 } v7m; 574 575 /* Information associated with an exception about to be taken: 576 * code which raises an exception must set cs->exception_index and 577 * the relevant parts of this structure; the cpu_do_interrupt function 578 * will then set the guest-visible registers as part of the exception 579 * entry process. 580 */ 581 struct { 582 uint32_t syndrome; /* AArch64 format syndrome register */ 583 uint32_t fsr; /* AArch32 format fault status register info */ 584 uint64_t vaddress; /* virtual addr associated with exception, if any */ 585 uint32_t target_el; /* EL the exception should be targeted for */ 586 /* If we implement EL2 we will also need to store information 587 * about the intermediate physical address for stage 2 faults. 588 */ 589 } exception; 590 591 /* Information associated with an SError */ 592 struct { 593 uint8_t pending; 594 uint8_t has_esr; 595 uint64_t esr; 596 } serror; 597 598 uint8_t ext_dabt_raised; /* Tracking/verifying injection of ext DABT */ 599 600 /* State of our input IRQ/FIQ/VIRQ/VFIQ lines */ 601 uint32_t irq_line_state; 602 603 /* Thumb-2 EE state. */ 604 uint32_t teecr; 605 uint32_t teehbr; 606 607 /* VFP coprocessor state. */ 608 struct { 609 ARMVectorReg zregs[32]; 610 611 #ifdef TARGET_AARCH64 612 /* Store FFR as pregs[16] to make it easier to treat as any other. */ 613 #define FFR_PRED_NUM 16 614 ARMPredicateReg pregs[17]; 615 /* Scratch space for aa64 sve predicate temporary. */ 616 ARMPredicateReg preg_tmp; 617 #endif 618 619 /* We store these fpcsr fields separately for convenience. */ 620 uint32_t qc[4] QEMU_ALIGNED(16); 621 int vec_len; 622 int vec_stride; 623 624 uint32_t xregs[16]; 625 626 /* Scratch space for aa32 neon expansion. */ 627 uint32_t scratch[8]; 628 629 /* There are a number of distinct float control structures: 630 * 631 * fp_status: is the "normal" fp status. 632 * fp_status_fp16: used for half-precision calculations 633 * standard_fp_status : the ARM "Standard FPSCR Value" 634 * standard_fp_status_fp16 : used for half-precision 635 * calculations with the ARM "Standard FPSCR Value" 636 * 637 * Half-precision operations are governed by a separate 638 * flush-to-zero control bit in FPSCR:FZ16. We pass a separate 639 * status structure to control this. 640 * 641 * The "Standard FPSCR", ie default-NaN, flush-to-zero, 642 * round-to-nearest and is used by any operations (generally 643 * Neon) which the architecture defines as controlled by the 644 * standard FPSCR value rather than the FPSCR. 645 * 646 * The "standard FPSCR but for fp16 ops" is needed because 647 * the "standard FPSCR" tracks the FPSCR.FZ16 bit rather than 648 * using a fixed value for it. 649 * 650 * To avoid having to transfer exception bits around, we simply 651 * say that the FPSCR cumulative exception flags are the logical 652 * OR of the flags in the four fp statuses. This relies on the 653 * only thing which needs to read the exception flags being 654 * an explicit FPSCR read. 655 */ 656 float_status fp_status; 657 float_status fp_status_f16; 658 float_status standard_fp_status; 659 float_status standard_fp_status_f16; 660 661 uint64_t zcr_el[4]; /* ZCR_EL[1-3] */ 662 uint64_t smcr_el[4]; /* SMCR_EL[1-3] */ 663 } vfp; 664 uint64_t exclusive_addr; 665 uint64_t exclusive_val; 666 uint64_t exclusive_high; 667 668 /* iwMMXt coprocessor state. */ 669 struct { 670 uint64_t regs[16]; 671 uint64_t val; 672 673 uint32_t cregs[16]; 674 } iwmmxt; 675 676 #ifdef TARGET_AARCH64 677 struct { 678 ARMPACKey apia; 679 ARMPACKey apib; 680 ARMPACKey apda; 681 ARMPACKey apdb; 682 ARMPACKey apga; 683 } keys; 684 685 uint64_t scxtnum_el[4]; 686 687 /* 688 * SME ZA storage -- 256 x 256 byte array, with bytes in host word order, 689 * as we do with vfp.zregs[]. This corresponds to the architectural ZA 690 * array, where ZA[N] is in the least-significant bytes of env->zarray[N]. 691 * When SVL is less than the architectural maximum, the accessible 692 * storage is restricted, such that if the SVL is X bytes the guest can 693 * see only the bottom X elements of zarray[], and only the least 694 * significant X bytes of each element of the array. (In other words, 695 * the observable part is always square.) 696 * 697 * The ZA storage can also be considered as a set of square tiles of 698 * elements of different sizes. The mapping from tiles to the ZA array 699 * is architecturally defined, such that for tiles of elements of esz 700 * bytes, the Nth row (or "horizontal slice") of tile T is in 701 * ZA[T + N * esz]. Note that this means that each tile is not contiguous 702 * in the ZA storage, because its rows are striped through the ZA array. 703 * 704 * Because this is so large, keep this toward the end of the reset area, 705 * to keep the offsets into the rest of the structure smaller. 706 */ 707 ARMVectorReg zarray[ARM_MAX_VQ * 16]; 708 #endif 709 710 #if defined(CONFIG_USER_ONLY) 711 /* For usermode syscall translation. */ 712 int eabi; 713 #endif 714 715 struct CPUBreakpoint *cpu_breakpoint[16]; 716 struct CPUWatchpoint *cpu_watchpoint[16]; 717 718 /* Fields up to this point are cleared by a CPU reset */ 719 struct {} end_reset_fields; 720 721 /* Fields after this point are preserved across CPU reset. */ 722 723 /* Internal CPU feature flags. */ 724 uint64_t features; 725 726 /* PMSAv7 MPU */ 727 struct { 728 uint32_t *drbar; 729 uint32_t *drsr; 730 uint32_t *dracr; 731 uint32_t rnr[M_REG_NUM_BANKS]; 732 } pmsav7; 733 734 /* PMSAv8 MPU */ 735 struct { 736 /* The PMSAv8 implementation also shares some PMSAv7 config 737 * and state: 738 * pmsav7.rnr (region number register) 739 * pmsav7_dregion (number of configured regions) 740 */ 741 uint32_t *rbar[M_REG_NUM_BANKS]; 742 uint32_t *rlar[M_REG_NUM_BANKS]; 743 uint32_t mair0[M_REG_NUM_BANKS]; 744 uint32_t mair1[M_REG_NUM_BANKS]; 745 } pmsav8; 746 747 /* v8M SAU */ 748 struct { 749 uint32_t *rbar; 750 uint32_t *rlar; 751 uint32_t rnr; 752 uint32_t ctrl; 753 } sau; 754 755 void *nvic; 756 const struct arm_boot_info *boot_info; 757 /* Store GICv3CPUState to access from this struct */ 758 void *gicv3state; 759 760 #ifdef TARGET_TAGGED_ADDRESSES 761 /* Linux syscall tagged address support */ 762 bool tagged_addr_enable; 763 #endif 764 } CPUARMState; 765 766 static inline void set_feature(CPUARMState *env, int feature) 767 { 768 env->features |= 1ULL << feature; 769 } 770 771 static inline void unset_feature(CPUARMState *env, int feature) 772 { 773 env->features &= ~(1ULL << feature); 774 } 775 776 /** 777 * ARMELChangeHookFn: 778 * type of a function which can be registered via arm_register_el_change_hook() 779 * to get callbacks when the CPU changes its exception level or mode. 780 */ 781 typedef void ARMELChangeHookFn(ARMCPU *cpu, void *opaque); 782 typedef struct ARMELChangeHook ARMELChangeHook; 783 struct ARMELChangeHook { 784 ARMELChangeHookFn *hook; 785 void *opaque; 786 QLIST_ENTRY(ARMELChangeHook) node; 787 }; 788 789 /* These values map onto the return values for 790 * QEMU_PSCI_0_2_FN_AFFINITY_INFO */ 791 typedef enum ARMPSCIState { 792 PSCI_ON = 0, 793 PSCI_OFF = 1, 794 PSCI_ON_PENDING = 2 795 } ARMPSCIState; 796 797 typedef struct ARMISARegisters ARMISARegisters; 798 799 /* 800 * In map, each set bit is a supported vector length of (bit-number + 1) * 16 801 * bytes, i.e. each bit number + 1 is the vector length in quadwords. 802 * 803 * While processing properties during initialization, corresponding init bits 804 * are set for bits in sve_vq_map that have been set by properties. 805 * 806 * Bits set in supported represent valid vector lengths for the CPU type. 807 */ 808 typedef struct { 809 uint32_t map, init, supported; 810 } ARMVQMap; 811 812 /** 813 * ARMCPU: 814 * @env: #CPUARMState 815 * 816 * An ARM CPU core. 817 */ 818 struct ArchCPU { 819 /*< private >*/ 820 CPUState parent_obj; 821 /*< public >*/ 822 823 CPUNegativeOffsetState neg; 824 CPUARMState env; 825 826 /* Coprocessor information */ 827 GHashTable *cp_regs; 828 /* For marshalling (mostly coprocessor) register state between the 829 * kernel and QEMU (for KVM) and between two QEMUs (for migration), 830 * we use these arrays. 831 */ 832 /* List of register indexes managed via these arrays; (full KVM style 833 * 64 bit indexes, not CPRegInfo 32 bit indexes) 834 */ 835 uint64_t *cpreg_indexes; 836 /* Values of the registers (cpreg_indexes[i]'s value is cpreg_values[i]) */ 837 uint64_t *cpreg_values; 838 /* Length of the indexes, values, reset_values arrays */ 839 int32_t cpreg_array_len; 840 /* These are used only for migration: incoming data arrives in 841 * these fields and is sanity checked in post_load before copying 842 * to the working data structures above. 843 */ 844 uint64_t *cpreg_vmstate_indexes; 845 uint64_t *cpreg_vmstate_values; 846 int32_t cpreg_vmstate_array_len; 847 848 DynamicGDBXMLInfo dyn_sysreg_xml; 849 DynamicGDBXMLInfo dyn_svereg_xml; 850 851 /* Timers used by the generic (architected) timer */ 852 QEMUTimer *gt_timer[NUM_GTIMERS]; 853 /* 854 * Timer used by the PMU. Its state is restored after migration by 855 * pmu_op_finish() - it does not need other handling during migration 856 */ 857 QEMUTimer *pmu_timer; 858 /* GPIO outputs for generic timer */ 859 qemu_irq gt_timer_outputs[NUM_GTIMERS]; 860 /* GPIO output for GICv3 maintenance interrupt signal */ 861 qemu_irq gicv3_maintenance_interrupt; 862 /* GPIO output for the PMU interrupt */ 863 qemu_irq pmu_interrupt; 864 865 /* MemoryRegion to use for secure physical accesses */ 866 MemoryRegion *secure_memory; 867 868 /* MemoryRegion to use for allocation tag accesses */ 869 MemoryRegion *tag_memory; 870 MemoryRegion *secure_tag_memory; 871 872 /* For v8M, pointer to the IDAU interface provided by board/SoC */ 873 Object *idau; 874 875 /* 'compatible' string for this CPU for Linux device trees */ 876 const char *dtb_compatible; 877 878 /* PSCI version for this CPU 879 * Bits[31:16] = Major Version 880 * Bits[15:0] = Minor Version 881 */ 882 uint32_t psci_version; 883 884 /* Current power state, access guarded by BQL */ 885 ARMPSCIState power_state; 886 887 /* CPU has virtualization extension */ 888 bool has_el2; 889 /* CPU has security extension */ 890 bool has_el3; 891 /* CPU has PMU (Performance Monitor Unit) */ 892 bool has_pmu; 893 /* CPU has VFP */ 894 bool has_vfp; 895 /* CPU has Neon */ 896 bool has_neon; 897 /* CPU has M-profile DSP extension */ 898 bool has_dsp; 899 900 /* CPU has memory protection unit */ 901 bool has_mpu; 902 /* PMSAv7 MPU number of supported regions */ 903 uint32_t pmsav7_dregion; 904 /* v8M SAU number of supported regions */ 905 uint32_t sau_sregion; 906 907 /* PSCI conduit used to invoke PSCI methods 908 * 0 - disabled, 1 - smc, 2 - hvc 909 */ 910 uint32_t psci_conduit; 911 912 /* For v8M, initial value of the Secure VTOR */ 913 uint32_t init_svtor; 914 /* For v8M, initial value of the Non-secure VTOR */ 915 uint32_t init_nsvtor; 916 917 /* [QEMU_]KVM_ARM_TARGET_* constant for this CPU, or 918 * QEMU_KVM_ARM_TARGET_NONE if the kernel doesn't support this CPU type. 919 */ 920 uint32_t kvm_target; 921 922 /* KVM init features for this CPU */ 923 uint32_t kvm_init_features[7]; 924 925 /* KVM CPU state */ 926 927 /* KVM virtual time adjustment */ 928 bool kvm_adjvtime; 929 bool kvm_vtime_dirty; 930 uint64_t kvm_vtime; 931 932 /* KVM steal time */ 933 OnOffAuto kvm_steal_time; 934 935 /* Uniprocessor system with MP extensions */ 936 bool mp_is_up; 937 938 /* True if we tried kvm_arm_host_cpu_features() during CPU instance_init 939 * and the probe failed (so we need to report the error in realize) 940 */ 941 bool host_cpu_probe_failed; 942 943 /* Specify the number of cores in this CPU cluster. Used for the L2CTLR 944 * register. 945 */ 946 int32_t core_count; 947 948 /* The instance init functions for implementation-specific subclasses 949 * set these fields to specify the implementation-dependent values of 950 * various constant registers and reset values of non-constant 951 * registers. 952 * Some of these might become QOM properties eventually. 953 * Field names match the official register names as defined in the 954 * ARMv7AR ARM Architecture Reference Manual. A reset_ prefix 955 * is used for reset values of non-constant registers; no reset_ 956 * prefix means a constant register. 957 * Some of these registers are split out into a substructure that 958 * is shared with the translators to control the ISA. 959 * 960 * Note that if you add an ID register to the ARMISARegisters struct 961 * you need to also update the 32-bit and 64-bit versions of the 962 * kvm_arm_get_host_cpu_features() function to correctly populate the 963 * field by reading the value from the KVM vCPU. 964 */ 965 struct ARMISARegisters { 966 uint32_t id_isar0; 967 uint32_t id_isar1; 968 uint32_t id_isar2; 969 uint32_t id_isar3; 970 uint32_t id_isar4; 971 uint32_t id_isar5; 972 uint32_t id_isar6; 973 uint32_t id_mmfr0; 974 uint32_t id_mmfr1; 975 uint32_t id_mmfr2; 976 uint32_t id_mmfr3; 977 uint32_t id_mmfr4; 978 uint32_t id_mmfr5; 979 uint32_t id_pfr0; 980 uint32_t id_pfr1; 981 uint32_t id_pfr2; 982 uint32_t mvfr0; 983 uint32_t mvfr1; 984 uint32_t mvfr2; 985 uint32_t id_dfr0; 986 uint32_t id_dfr1; 987 uint32_t dbgdidr; 988 uint32_t dbgdevid; 989 uint32_t dbgdevid1; 990 uint64_t id_aa64isar0; 991 uint64_t id_aa64isar1; 992 uint64_t id_aa64pfr0; 993 uint64_t id_aa64pfr1; 994 uint64_t id_aa64mmfr0; 995 uint64_t id_aa64mmfr1; 996 uint64_t id_aa64mmfr2; 997 uint64_t id_aa64dfr0; 998 uint64_t id_aa64dfr1; 999 uint64_t id_aa64zfr0; 1000 uint64_t id_aa64smfr0; 1001 uint64_t reset_pmcr_el0; 1002 } isar; 1003 uint64_t midr; 1004 uint32_t revidr; 1005 uint32_t reset_fpsid; 1006 uint64_t ctr; 1007 uint32_t reset_sctlr; 1008 uint64_t pmceid0; 1009 uint64_t pmceid1; 1010 uint32_t id_afr0; 1011 uint64_t id_aa64afr0; 1012 uint64_t id_aa64afr1; 1013 uint64_t clidr; 1014 uint64_t mp_affinity; /* MP ID without feature bits */ 1015 /* The elements of this array are the CCSIDR values for each cache, 1016 * in the order L1DCache, L1ICache, L2DCache, L2ICache, etc. 1017 */ 1018 uint64_t ccsidr[16]; 1019 uint64_t reset_cbar; 1020 uint32_t reset_auxcr; 1021 bool reset_hivecs; 1022 1023 /* 1024 * Intermediate values used during property parsing. 1025 * Once finalized, the values should be read from ID_AA64*. 1026 */ 1027 bool prop_pauth; 1028 bool prop_pauth_impdef; 1029 bool prop_lpa2; 1030 1031 /* DCZ blocksize, in log_2(words), ie low 4 bits of DCZID_EL0 */ 1032 uint32_t dcz_blocksize; 1033 uint64_t rvbar_prop; /* Property/input signals. */ 1034 1035 /* Configurable aspects of GIC cpu interface (which is part of the CPU) */ 1036 int gic_num_lrs; /* number of list registers */ 1037 int gic_vpribits; /* number of virtual priority bits */ 1038 int gic_vprebits; /* number of virtual preemption bits */ 1039 int gic_pribits; /* number of physical priority bits */ 1040 1041 /* Whether the cfgend input is high (i.e. this CPU should reset into 1042 * big-endian mode). This setting isn't used directly: instead it modifies 1043 * the reset_sctlr value to have SCTLR_B or SCTLR_EE set, depending on the 1044 * architecture version. 1045 */ 1046 bool cfgend; 1047 1048 QLIST_HEAD(, ARMELChangeHook) pre_el_change_hooks; 1049 QLIST_HEAD(, ARMELChangeHook) el_change_hooks; 1050 1051 int32_t node_id; /* NUMA node this CPU belongs to */ 1052 1053 /* Used to synchronize KVM and QEMU in-kernel device levels */ 1054 uint8_t device_irq_level; 1055 1056 /* Used to set the maximum vector length the cpu will support. */ 1057 uint32_t sve_max_vq; 1058 1059 #ifdef CONFIG_USER_ONLY 1060 /* Used to set the default vector length at process start. */ 1061 uint32_t sve_default_vq; 1062 uint32_t sme_default_vq; 1063 #endif 1064 1065 ARMVQMap sve_vq; 1066 ARMVQMap sme_vq; 1067 1068 /* Generic timer counter frequency, in Hz */ 1069 uint64_t gt_cntfrq_hz; 1070 }; 1071 1072 unsigned int gt_cntfrq_period_ns(ARMCPU *cpu); 1073 1074 void arm_cpu_post_init(Object *obj); 1075 1076 uint64_t arm_cpu_mp_affinity(int idx, uint8_t clustersz); 1077 1078 #ifndef CONFIG_USER_ONLY 1079 extern const VMStateDescription vmstate_arm_cpu; 1080 1081 void arm_cpu_do_interrupt(CPUState *cpu); 1082 void arm_v7m_cpu_do_interrupt(CPUState *cpu); 1083 #endif /* !CONFIG_USER_ONLY */ 1084 1085 hwaddr arm_cpu_get_phys_page_attrs_debug(CPUState *cpu, vaddr addr, 1086 MemTxAttrs *attrs); 1087 1088 int arm_cpu_gdb_read_register(CPUState *cpu, GByteArray *buf, int reg); 1089 int arm_cpu_gdb_write_register(CPUState *cpu, uint8_t *buf, int reg); 1090 1091 /* 1092 * Helpers to dynamically generates XML descriptions of the sysregs 1093 * and SVE registers. Returns the number of registers in each set. 1094 */ 1095 int arm_gen_dynamic_sysreg_xml(CPUState *cpu, int base_reg); 1096 int arm_gen_dynamic_svereg_xml(CPUState *cpu, int base_reg); 1097 1098 /* Returns the dynamically generated XML for the gdb stub. 1099 * Returns a pointer to the XML contents for the specified XML file or NULL 1100 * if the XML name doesn't match the predefined one. 1101 */ 1102 const char *arm_gdb_get_dynamic_xml(CPUState *cpu, const char *xmlname); 1103 1104 int arm_cpu_write_elf64_note(WriteCoreDumpFunction f, CPUState *cs, 1105 int cpuid, DumpState *s); 1106 int arm_cpu_write_elf32_note(WriteCoreDumpFunction f, CPUState *cs, 1107 int cpuid, DumpState *s); 1108 1109 #ifdef TARGET_AARCH64 1110 int aarch64_cpu_gdb_read_register(CPUState *cpu, GByteArray *buf, int reg); 1111 int aarch64_cpu_gdb_write_register(CPUState *cpu, uint8_t *buf, int reg); 1112 void aarch64_sve_narrow_vq(CPUARMState *env, unsigned vq); 1113 void aarch64_sve_change_el(CPUARMState *env, int old_el, 1114 int new_el, bool el0_a64); 1115 void arm_reset_sve_state(CPUARMState *env); 1116 1117 /* 1118 * SVE registers are encoded in KVM's memory in an endianness-invariant format. 1119 * The byte at offset i from the start of the in-memory representation contains 1120 * the bits [(7 + 8 * i) : (8 * i)] of the register value. As this means the 1121 * lowest offsets are stored in the lowest memory addresses, then that nearly 1122 * matches QEMU's representation, which is to use an array of host-endian 1123 * uint64_t's, where the lower offsets are at the lower indices. To complete 1124 * the translation we just need to byte swap the uint64_t's on big-endian hosts. 1125 */ 1126 static inline uint64_t *sve_bswap64(uint64_t *dst, uint64_t *src, int nr) 1127 { 1128 #if HOST_BIG_ENDIAN 1129 int i; 1130 1131 for (i = 0; i < nr; ++i) { 1132 dst[i] = bswap64(src[i]); 1133 } 1134 1135 return dst; 1136 #else 1137 return src; 1138 #endif 1139 } 1140 1141 #else 1142 static inline void aarch64_sve_narrow_vq(CPUARMState *env, unsigned vq) { } 1143 static inline void aarch64_sve_change_el(CPUARMState *env, int o, 1144 int n, bool a) 1145 { } 1146 #endif 1147 1148 void aarch64_sync_32_to_64(CPUARMState *env); 1149 void aarch64_sync_64_to_32(CPUARMState *env); 1150 1151 int fp_exception_el(CPUARMState *env, int cur_el); 1152 int sve_exception_el(CPUARMState *env, int cur_el); 1153 int sme_exception_el(CPUARMState *env, int cur_el); 1154 1155 /** 1156 * sve_vqm1_for_el_sm: 1157 * @env: CPUARMState 1158 * @el: exception level 1159 * @sm: streaming mode 1160 * 1161 * Compute the current vector length for @el & @sm, in units of 1162 * Quadwords Minus 1 -- the same scale used for ZCR_ELx.LEN. 1163 * If @sm, compute for SVL, otherwise NVL. 1164 */ 1165 uint32_t sve_vqm1_for_el_sm(CPUARMState *env, int el, bool sm); 1166 1167 /* Likewise, but using @sm = PSTATE.SM. */ 1168 uint32_t sve_vqm1_for_el(CPUARMState *env, int el); 1169 1170 static inline bool is_a64(CPUARMState *env) 1171 { 1172 return env->aarch64; 1173 } 1174 1175 /** 1176 * pmu_op_start/finish 1177 * @env: CPUARMState 1178 * 1179 * Convert all PMU counters between their delta form (the typical mode when 1180 * they are enabled) and the guest-visible values. These two calls must 1181 * surround any action which might affect the counters. 1182 */ 1183 void pmu_op_start(CPUARMState *env); 1184 void pmu_op_finish(CPUARMState *env); 1185 1186 /* 1187 * Called when a PMU counter is due to overflow 1188 */ 1189 void arm_pmu_timer_cb(void *opaque); 1190 1191 /** 1192 * Functions to register as EL change hooks for PMU mode filtering 1193 */ 1194 void pmu_pre_el_change(ARMCPU *cpu, void *ignored); 1195 void pmu_post_el_change(ARMCPU *cpu, void *ignored); 1196 1197 /* 1198 * pmu_init 1199 * @cpu: ARMCPU 1200 * 1201 * Initialize the CPU's PMCEID[01]_EL0 registers and associated internal state 1202 * for the current configuration 1203 */ 1204 void pmu_init(ARMCPU *cpu); 1205 1206 /* SCTLR bit meanings. Several bits have been reused in newer 1207 * versions of the architecture; in that case we define constants 1208 * for both old and new bit meanings. Code which tests against those 1209 * bits should probably check or otherwise arrange that the CPU 1210 * is the architectural version it expects. 1211 */ 1212 #define SCTLR_M (1U << 0) 1213 #define SCTLR_A (1U << 1) 1214 #define SCTLR_C (1U << 2) 1215 #define SCTLR_W (1U << 3) /* up to v6; RAO in v7 */ 1216 #define SCTLR_nTLSMD_32 (1U << 3) /* v8.2-LSMAOC, AArch32 only */ 1217 #define SCTLR_SA (1U << 3) /* AArch64 only */ 1218 #define SCTLR_P (1U << 4) /* up to v5; RAO in v6 and v7 */ 1219 #define SCTLR_LSMAOE_32 (1U << 4) /* v8.2-LSMAOC, AArch32 only */ 1220 #define SCTLR_SA0 (1U << 4) /* v8 onward, AArch64 only */ 1221 #define SCTLR_D (1U << 5) /* up to v5; RAO in v6 */ 1222 #define SCTLR_CP15BEN (1U << 5) /* v7 onward */ 1223 #define SCTLR_L (1U << 6) /* up to v5; RAO in v6 and v7; RAZ in v8 */ 1224 #define SCTLR_nAA (1U << 6) /* when v8.4-LSE is implemented */ 1225 #define SCTLR_B (1U << 7) /* up to v6; RAZ in v7 */ 1226 #define SCTLR_ITD (1U << 7) /* v8 onward */ 1227 #define SCTLR_S (1U << 8) /* up to v6; RAZ in v7 */ 1228 #define SCTLR_SED (1U << 8) /* v8 onward */ 1229 #define SCTLR_R (1U << 9) /* up to v6; RAZ in v7 */ 1230 #define SCTLR_UMA (1U << 9) /* v8 onward, AArch64 only */ 1231 #define SCTLR_F (1U << 10) /* up to v6 */ 1232 #define SCTLR_SW (1U << 10) /* v7 */ 1233 #define SCTLR_EnRCTX (1U << 10) /* in v8.0-PredInv */ 1234 #define SCTLR_Z (1U << 11) /* in v7, RES1 in v8 */ 1235 #define SCTLR_EOS (1U << 11) /* v8.5-ExS */ 1236 #define SCTLR_I (1U << 12) 1237 #define SCTLR_V (1U << 13) /* AArch32 only */ 1238 #define SCTLR_EnDB (1U << 13) /* v8.3, AArch64 only */ 1239 #define SCTLR_RR (1U << 14) /* up to v7 */ 1240 #define SCTLR_DZE (1U << 14) /* v8 onward, AArch64 only */ 1241 #define SCTLR_L4 (1U << 15) /* up to v6; RAZ in v7 */ 1242 #define SCTLR_UCT (1U << 15) /* v8 onward, AArch64 only */ 1243 #define SCTLR_DT (1U << 16) /* up to ??, RAO in v6 and v7 */ 1244 #define SCTLR_nTWI (1U << 16) /* v8 onward */ 1245 #define SCTLR_HA (1U << 17) /* up to v7, RES0 in v8 */ 1246 #define SCTLR_BR (1U << 17) /* PMSA only */ 1247 #define SCTLR_IT (1U << 18) /* up to ??, RAO in v6 and v7 */ 1248 #define SCTLR_nTWE (1U << 18) /* v8 onward */ 1249 #define SCTLR_WXN (1U << 19) 1250 #define SCTLR_ST (1U << 20) /* up to ??, RAZ in v6 */ 1251 #define SCTLR_UWXN (1U << 20) /* v7 onward, AArch32 only */ 1252 #define SCTLR_TSCXT (1U << 20) /* FEAT_CSV2_1p2, AArch64 only */ 1253 #define SCTLR_FI (1U << 21) /* up to v7, v8 RES0 */ 1254 #define SCTLR_IESB (1U << 21) /* v8.2-IESB, AArch64 only */ 1255 #define SCTLR_U (1U << 22) /* up to v6, RAO in v7 */ 1256 #define SCTLR_EIS (1U << 22) /* v8.5-ExS */ 1257 #define SCTLR_XP (1U << 23) /* up to v6; v7 onward RAO */ 1258 #define SCTLR_SPAN (1U << 23) /* v8.1-PAN */ 1259 #define SCTLR_VE (1U << 24) /* up to v7 */ 1260 #define SCTLR_E0E (1U << 24) /* v8 onward, AArch64 only */ 1261 #define SCTLR_EE (1U << 25) 1262 #define SCTLR_L2 (1U << 26) /* up to v6, RAZ in v7 */ 1263 #define SCTLR_UCI (1U << 26) /* v8 onward, AArch64 only */ 1264 #define SCTLR_NMFI (1U << 27) /* up to v7, RAZ in v7VE and v8 */ 1265 #define SCTLR_EnDA (1U << 27) /* v8.3, AArch64 only */ 1266 #define SCTLR_TRE (1U << 28) /* AArch32 only */ 1267 #define SCTLR_nTLSMD_64 (1U << 28) /* v8.2-LSMAOC, AArch64 only */ 1268 #define SCTLR_AFE (1U << 29) /* AArch32 only */ 1269 #define SCTLR_LSMAOE_64 (1U << 29) /* v8.2-LSMAOC, AArch64 only */ 1270 #define SCTLR_TE (1U << 30) /* AArch32 only */ 1271 #define SCTLR_EnIB (1U << 30) /* v8.3, AArch64 only */ 1272 #define SCTLR_EnIA (1U << 31) /* v8.3, AArch64 only */ 1273 #define SCTLR_DSSBS_32 (1U << 31) /* v8.5, AArch32 only */ 1274 #define SCTLR_BT0 (1ULL << 35) /* v8.5-BTI */ 1275 #define SCTLR_BT1 (1ULL << 36) /* v8.5-BTI */ 1276 #define SCTLR_ITFSB (1ULL << 37) /* v8.5-MemTag */ 1277 #define SCTLR_TCF0 (3ULL << 38) /* v8.5-MemTag */ 1278 #define SCTLR_TCF (3ULL << 40) /* v8.5-MemTag */ 1279 #define SCTLR_ATA0 (1ULL << 42) /* v8.5-MemTag */ 1280 #define SCTLR_ATA (1ULL << 43) /* v8.5-MemTag */ 1281 #define SCTLR_DSSBS_64 (1ULL << 44) /* v8.5, AArch64 only */ 1282 #define SCTLR_TWEDEn (1ULL << 45) /* FEAT_TWED */ 1283 #define SCTLR_TWEDEL MAKE_64_MASK(46, 4) /* FEAT_TWED */ 1284 #define SCTLR_TMT0 (1ULL << 50) /* FEAT_TME */ 1285 #define SCTLR_TMT (1ULL << 51) /* FEAT_TME */ 1286 #define SCTLR_TME0 (1ULL << 52) /* FEAT_TME */ 1287 #define SCTLR_TME (1ULL << 53) /* FEAT_TME */ 1288 #define SCTLR_EnASR (1ULL << 54) /* FEAT_LS64_V */ 1289 #define SCTLR_EnAS0 (1ULL << 55) /* FEAT_LS64_ACCDATA */ 1290 #define SCTLR_EnALS (1ULL << 56) /* FEAT_LS64 */ 1291 #define SCTLR_EPAN (1ULL << 57) /* FEAT_PAN3 */ 1292 #define SCTLR_EnTP2 (1ULL << 60) /* FEAT_SME */ 1293 #define SCTLR_NMI (1ULL << 61) /* FEAT_NMI */ 1294 #define SCTLR_SPINTMASK (1ULL << 62) /* FEAT_NMI */ 1295 #define SCTLR_TIDCP (1ULL << 63) /* FEAT_TIDCP1 */ 1296 1297 /* Bit definitions for CPACR (AArch32 only) */ 1298 FIELD(CPACR, CP10, 20, 2) 1299 FIELD(CPACR, CP11, 22, 2) 1300 FIELD(CPACR, TRCDIS, 28, 1) /* matches CPACR_EL1.TTA */ 1301 FIELD(CPACR, D32DIS, 30, 1) /* up to v7; RAZ in v8 */ 1302 FIELD(CPACR, ASEDIS, 31, 1) 1303 1304 /* Bit definitions for CPACR_EL1 (AArch64 only) */ 1305 FIELD(CPACR_EL1, ZEN, 16, 2) 1306 FIELD(CPACR_EL1, FPEN, 20, 2) 1307 FIELD(CPACR_EL1, SMEN, 24, 2) 1308 FIELD(CPACR_EL1, TTA, 28, 1) /* matches CPACR.TRCDIS */ 1309 1310 /* Bit definitions for HCPTR (AArch32 only) */ 1311 FIELD(HCPTR, TCP10, 10, 1) 1312 FIELD(HCPTR, TCP11, 11, 1) 1313 FIELD(HCPTR, TASE, 15, 1) 1314 FIELD(HCPTR, TTA, 20, 1) 1315 FIELD(HCPTR, TAM, 30, 1) /* matches CPTR_EL2.TAM */ 1316 FIELD(HCPTR, TCPAC, 31, 1) /* matches CPTR_EL2.TCPAC */ 1317 1318 /* Bit definitions for CPTR_EL2 (AArch64 only) */ 1319 FIELD(CPTR_EL2, TZ, 8, 1) /* !E2H */ 1320 FIELD(CPTR_EL2, TFP, 10, 1) /* !E2H, matches HCPTR.TCP10 */ 1321 FIELD(CPTR_EL2, TSM, 12, 1) /* !E2H */ 1322 FIELD(CPTR_EL2, ZEN, 16, 2) /* E2H */ 1323 FIELD(CPTR_EL2, FPEN, 20, 2) /* E2H */ 1324 FIELD(CPTR_EL2, SMEN, 24, 2) /* E2H */ 1325 FIELD(CPTR_EL2, TTA, 28, 1) 1326 FIELD(CPTR_EL2, TAM, 30, 1) /* matches HCPTR.TAM */ 1327 FIELD(CPTR_EL2, TCPAC, 31, 1) /* matches HCPTR.TCPAC */ 1328 1329 /* Bit definitions for CPTR_EL3 (AArch64 only) */ 1330 FIELD(CPTR_EL3, EZ, 8, 1) 1331 FIELD(CPTR_EL3, TFP, 10, 1) 1332 FIELD(CPTR_EL3, ESM, 12, 1) 1333 FIELD(CPTR_EL3, TTA, 20, 1) 1334 FIELD(CPTR_EL3, TAM, 30, 1) 1335 FIELD(CPTR_EL3, TCPAC, 31, 1) 1336 1337 #define MDCR_MTPME (1U << 28) 1338 #define MDCR_TDCC (1U << 27) 1339 #define MDCR_HLP (1U << 26) /* MDCR_EL2 */ 1340 #define MDCR_SCCD (1U << 23) /* MDCR_EL3 */ 1341 #define MDCR_HCCD (1U << 23) /* MDCR_EL2 */ 1342 #define MDCR_EPMAD (1U << 21) 1343 #define MDCR_EDAD (1U << 20) 1344 #define MDCR_TTRF (1U << 19) 1345 #define MDCR_STE (1U << 18) /* MDCR_EL3 */ 1346 #define MDCR_SPME (1U << 17) /* MDCR_EL3 */ 1347 #define MDCR_HPMD (1U << 17) /* MDCR_EL2 */ 1348 #define MDCR_SDD (1U << 16) 1349 #define MDCR_SPD (3U << 14) 1350 #define MDCR_TDRA (1U << 11) 1351 #define MDCR_TDOSA (1U << 10) 1352 #define MDCR_TDA (1U << 9) 1353 #define MDCR_TDE (1U << 8) 1354 #define MDCR_HPME (1U << 7) 1355 #define MDCR_TPM (1U << 6) 1356 #define MDCR_TPMCR (1U << 5) 1357 #define MDCR_HPMN (0x1fU) 1358 1359 /* Not all of the MDCR_EL3 bits are present in the 32-bit SDCR */ 1360 #define SDCR_VALID_MASK (MDCR_MTPME | MDCR_TDCC | MDCR_SCCD | \ 1361 MDCR_EPMAD | MDCR_EDAD | MDCR_TTRF | \ 1362 MDCR_STE | MDCR_SPME | MDCR_SPD) 1363 1364 #define CPSR_M (0x1fU) 1365 #define CPSR_T (1U << 5) 1366 #define CPSR_F (1U << 6) 1367 #define CPSR_I (1U << 7) 1368 #define CPSR_A (1U << 8) 1369 #define CPSR_E (1U << 9) 1370 #define CPSR_IT_2_7 (0xfc00U) 1371 #define CPSR_GE (0xfU << 16) 1372 #define CPSR_IL (1U << 20) 1373 #define CPSR_DIT (1U << 21) 1374 #define CPSR_PAN (1U << 22) 1375 #define CPSR_SSBS (1U << 23) 1376 #define CPSR_J (1U << 24) 1377 #define CPSR_IT_0_1 (3U << 25) 1378 #define CPSR_Q (1U << 27) 1379 #define CPSR_V (1U << 28) 1380 #define CPSR_C (1U << 29) 1381 #define CPSR_Z (1U << 30) 1382 #define CPSR_N (1U << 31) 1383 #define CPSR_NZCV (CPSR_N | CPSR_Z | CPSR_C | CPSR_V) 1384 #define CPSR_AIF (CPSR_A | CPSR_I | CPSR_F) 1385 1386 #define CPSR_IT (CPSR_IT_0_1 | CPSR_IT_2_7) 1387 #define CACHED_CPSR_BITS (CPSR_T | CPSR_AIF | CPSR_GE | CPSR_IT | CPSR_Q \ 1388 | CPSR_NZCV) 1389 /* Bits writable in user mode. */ 1390 #define CPSR_USER (CPSR_NZCV | CPSR_Q | CPSR_GE | CPSR_E) 1391 /* Execution state bits. MRS read as zero, MSR writes ignored. */ 1392 #define CPSR_EXEC (CPSR_T | CPSR_IT | CPSR_J | CPSR_IL) 1393 1394 /* Bit definitions for M profile XPSR. Most are the same as CPSR. */ 1395 #define XPSR_EXCP 0x1ffU 1396 #define XPSR_SPREALIGN (1U << 9) /* Only set in exception stack frames */ 1397 #define XPSR_IT_2_7 CPSR_IT_2_7 1398 #define XPSR_GE CPSR_GE 1399 #define XPSR_SFPA (1U << 20) /* Only set in exception stack frames */ 1400 #define XPSR_T (1U << 24) /* Not the same as CPSR_T ! */ 1401 #define XPSR_IT_0_1 CPSR_IT_0_1 1402 #define XPSR_Q CPSR_Q 1403 #define XPSR_V CPSR_V 1404 #define XPSR_C CPSR_C 1405 #define XPSR_Z CPSR_Z 1406 #define XPSR_N CPSR_N 1407 #define XPSR_NZCV CPSR_NZCV 1408 #define XPSR_IT CPSR_IT 1409 1410 #define TTBCR_N (7U << 0) /* TTBCR.EAE==0 */ 1411 #define TTBCR_T0SZ (7U << 0) /* TTBCR.EAE==1 */ 1412 #define TTBCR_PD0 (1U << 4) 1413 #define TTBCR_PD1 (1U << 5) 1414 #define TTBCR_EPD0 (1U << 7) 1415 #define TTBCR_IRGN0 (3U << 8) 1416 #define TTBCR_ORGN0 (3U << 10) 1417 #define TTBCR_SH0 (3U << 12) 1418 #define TTBCR_T1SZ (3U << 16) 1419 #define TTBCR_A1 (1U << 22) 1420 #define TTBCR_EPD1 (1U << 23) 1421 #define TTBCR_IRGN1 (3U << 24) 1422 #define TTBCR_ORGN1 (3U << 26) 1423 #define TTBCR_SH1 (1U << 28) 1424 #define TTBCR_EAE (1U << 31) 1425 1426 FIELD(VTCR, T0SZ, 0, 6) 1427 FIELD(VTCR, SL0, 6, 2) 1428 FIELD(VTCR, IRGN0, 8, 2) 1429 FIELD(VTCR, ORGN0, 10, 2) 1430 FIELD(VTCR, SH0, 12, 2) 1431 FIELD(VTCR, TG0, 14, 2) 1432 FIELD(VTCR, PS, 16, 3) 1433 FIELD(VTCR, VS, 19, 1) 1434 FIELD(VTCR, HA, 21, 1) 1435 FIELD(VTCR, HD, 22, 1) 1436 FIELD(VTCR, HWU59, 25, 1) 1437 FIELD(VTCR, HWU60, 26, 1) 1438 FIELD(VTCR, HWU61, 27, 1) 1439 FIELD(VTCR, HWU62, 28, 1) 1440 FIELD(VTCR, NSW, 29, 1) 1441 FIELD(VTCR, NSA, 30, 1) 1442 FIELD(VTCR, DS, 32, 1) 1443 FIELD(VTCR, SL2, 33, 1) 1444 1445 /* Bit definitions for ARMv8 SPSR (PSTATE) format. 1446 * Only these are valid when in AArch64 mode; in 1447 * AArch32 mode SPSRs are basically CPSR-format. 1448 */ 1449 #define PSTATE_SP (1U) 1450 #define PSTATE_M (0xFU) 1451 #define PSTATE_nRW (1U << 4) 1452 #define PSTATE_F (1U << 6) 1453 #define PSTATE_I (1U << 7) 1454 #define PSTATE_A (1U << 8) 1455 #define PSTATE_D (1U << 9) 1456 #define PSTATE_BTYPE (3U << 10) 1457 #define PSTATE_SSBS (1U << 12) 1458 #define PSTATE_IL (1U << 20) 1459 #define PSTATE_SS (1U << 21) 1460 #define PSTATE_PAN (1U << 22) 1461 #define PSTATE_UAO (1U << 23) 1462 #define PSTATE_DIT (1U << 24) 1463 #define PSTATE_TCO (1U << 25) 1464 #define PSTATE_V (1U << 28) 1465 #define PSTATE_C (1U << 29) 1466 #define PSTATE_Z (1U << 30) 1467 #define PSTATE_N (1U << 31) 1468 #define PSTATE_NZCV (PSTATE_N | PSTATE_Z | PSTATE_C | PSTATE_V) 1469 #define PSTATE_DAIF (PSTATE_D | PSTATE_A | PSTATE_I | PSTATE_F) 1470 #define CACHED_PSTATE_BITS (PSTATE_NZCV | PSTATE_DAIF | PSTATE_BTYPE) 1471 /* Mode values for AArch64 */ 1472 #define PSTATE_MODE_EL3h 13 1473 #define PSTATE_MODE_EL3t 12 1474 #define PSTATE_MODE_EL2h 9 1475 #define PSTATE_MODE_EL2t 8 1476 #define PSTATE_MODE_EL1h 5 1477 #define PSTATE_MODE_EL1t 4 1478 #define PSTATE_MODE_EL0t 0 1479 1480 /* PSTATE bits that are accessed via SVCR and not stored in SPSR_ELx. */ 1481 FIELD(SVCR, SM, 0, 1) 1482 FIELD(SVCR, ZA, 1, 1) 1483 1484 /* Fields for SMCR_ELx. */ 1485 FIELD(SMCR, LEN, 0, 4) 1486 FIELD(SMCR, FA64, 31, 1) 1487 1488 /* Write a new value to v7m.exception, thus transitioning into or out 1489 * of Handler mode; this may result in a change of active stack pointer. 1490 */ 1491 void write_v7m_exception(CPUARMState *env, uint32_t new_exc); 1492 1493 /* Map EL and handler into a PSTATE_MODE. */ 1494 static inline unsigned int aarch64_pstate_mode(unsigned int el, bool handler) 1495 { 1496 return (el << 2) | handler; 1497 } 1498 1499 /* Return the current PSTATE value. For the moment we don't support 32<->64 bit 1500 * interprocessing, so we don't attempt to sync with the cpsr state used by 1501 * the 32 bit decoder. 1502 */ 1503 static inline uint32_t pstate_read(CPUARMState *env) 1504 { 1505 int ZF; 1506 1507 ZF = (env->ZF == 0); 1508 return (env->NF & 0x80000000) | (ZF << 30) 1509 | (env->CF << 29) | ((env->VF & 0x80000000) >> 3) 1510 | env->pstate | env->daif | (env->btype << 10); 1511 } 1512 1513 static inline void pstate_write(CPUARMState *env, uint32_t val) 1514 { 1515 env->ZF = (~val) & PSTATE_Z; 1516 env->NF = val; 1517 env->CF = (val >> 29) & 1; 1518 env->VF = (val << 3) & 0x80000000; 1519 env->daif = val & PSTATE_DAIF; 1520 env->btype = (val >> 10) & 3; 1521 env->pstate = val & ~CACHED_PSTATE_BITS; 1522 } 1523 1524 /* Return the current CPSR value. */ 1525 uint32_t cpsr_read(CPUARMState *env); 1526 1527 typedef enum CPSRWriteType { 1528 CPSRWriteByInstr = 0, /* from guest MSR or CPS */ 1529 CPSRWriteExceptionReturn = 1, /* from guest exception return insn */ 1530 CPSRWriteRaw = 2, 1531 /* trust values, no reg bank switch, no hflags rebuild */ 1532 CPSRWriteByGDBStub = 3, /* from the GDB stub */ 1533 } CPSRWriteType; 1534 1535 /* 1536 * Set the CPSR. Note that some bits of mask must be all-set or all-clear. 1537 * This will do an arm_rebuild_hflags() if any of the bits in @mask 1538 * correspond to TB flags bits cached in the hflags, unless @write_type 1539 * is CPSRWriteRaw. 1540 */ 1541 void cpsr_write(CPUARMState *env, uint32_t val, uint32_t mask, 1542 CPSRWriteType write_type); 1543 1544 /* Return the current xPSR value. */ 1545 static inline uint32_t xpsr_read(CPUARMState *env) 1546 { 1547 int ZF; 1548 ZF = (env->ZF == 0); 1549 return (env->NF & 0x80000000) | (ZF << 30) 1550 | (env->CF << 29) | ((env->VF & 0x80000000) >> 3) | (env->QF << 27) 1551 | (env->thumb << 24) | ((env->condexec_bits & 3) << 25) 1552 | ((env->condexec_bits & 0xfc) << 8) 1553 | (env->GE << 16) 1554 | env->v7m.exception; 1555 } 1556 1557 /* Set the xPSR. Note that some bits of mask must be all-set or all-clear. */ 1558 static inline void xpsr_write(CPUARMState *env, uint32_t val, uint32_t mask) 1559 { 1560 if (mask & XPSR_NZCV) { 1561 env->ZF = (~val) & XPSR_Z; 1562 env->NF = val; 1563 env->CF = (val >> 29) & 1; 1564 env->VF = (val << 3) & 0x80000000; 1565 } 1566 if (mask & XPSR_Q) { 1567 env->QF = ((val & XPSR_Q) != 0); 1568 } 1569 if (mask & XPSR_GE) { 1570 env->GE = (val & XPSR_GE) >> 16; 1571 } 1572 #ifndef CONFIG_USER_ONLY 1573 if (mask & XPSR_T) { 1574 env->thumb = ((val & XPSR_T) != 0); 1575 } 1576 if (mask & XPSR_IT_0_1) { 1577 env->condexec_bits &= ~3; 1578 env->condexec_bits |= (val >> 25) & 3; 1579 } 1580 if (mask & XPSR_IT_2_7) { 1581 env->condexec_bits &= 3; 1582 env->condexec_bits |= (val >> 8) & 0xfc; 1583 } 1584 if (mask & XPSR_EXCP) { 1585 /* Note that this only happens on exception exit */ 1586 write_v7m_exception(env, val & XPSR_EXCP); 1587 } 1588 #endif 1589 } 1590 1591 #define HCR_VM (1ULL << 0) 1592 #define HCR_SWIO (1ULL << 1) 1593 #define HCR_PTW (1ULL << 2) 1594 #define HCR_FMO (1ULL << 3) 1595 #define HCR_IMO (1ULL << 4) 1596 #define HCR_AMO (1ULL << 5) 1597 #define HCR_VF (1ULL << 6) 1598 #define HCR_VI (1ULL << 7) 1599 #define HCR_VSE (1ULL << 8) 1600 #define HCR_FB (1ULL << 9) 1601 #define HCR_BSU_MASK (3ULL << 10) 1602 #define HCR_DC (1ULL << 12) 1603 #define HCR_TWI (1ULL << 13) 1604 #define HCR_TWE (1ULL << 14) 1605 #define HCR_TID0 (1ULL << 15) 1606 #define HCR_TID1 (1ULL << 16) 1607 #define HCR_TID2 (1ULL << 17) 1608 #define HCR_TID3 (1ULL << 18) 1609 #define HCR_TSC (1ULL << 19) 1610 #define HCR_TIDCP (1ULL << 20) 1611 #define HCR_TACR (1ULL << 21) 1612 #define HCR_TSW (1ULL << 22) 1613 #define HCR_TPCP (1ULL << 23) 1614 #define HCR_TPU (1ULL << 24) 1615 #define HCR_TTLB (1ULL << 25) 1616 #define HCR_TVM (1ULL << 26) 1617 #define HCR_TGE (1ULL << 27) 1618 #define HCR_TDZ (1ULL << 28) 1619 #define HCR_HCD (1ULL << 29) 1620 #define HCR_TRVM (1ULL << 30) 1621 #define HCR_RW (1ULL << 31) 1622 #define HCR_CD (1ULL << 32) 1623 #define HCR_ID (1ULL << 33) 1624 #define HCR_E2H (1ULL << 34) 1625 #define HCR_TLOR (1ULL << 35) 1626 #define HCR_TERR (1ULL << 36) 1627 #define HCR_TEA (1ULL << 37) 1628 #define HCR_MIOCNCE (1ULL << 38) 1629 /* RES0 bit 39 */ 1630 #define HCR_APK (1ULL << 40) 1631 #define HCR_API (1ULL << 41) 1632 #define HCR_NV (1ULL << 42) 1633 #define HCR_NV1 (1ULL << 43) 1634 #define HCR_AT (1ULL << 44) 1635 #define HCR_NV2 (1ULL << 45) 1636 #define HCR_FWB (1ULL << 46) 1637 #define HCR_FIEN (1ULL << 47) 1638 /* RES0 bit 48 */ 1639 #define HCR_TID4 (1ULL << 49) 1640 #define HCR_TICAB (1ULL << 50) 1641 #define HCR_AMVOFFEN (1ULL << 51) 1642 #define HCR_TOCU (1ULL << 52) 1643 #define HCR_ENSCXT (1ULL << 53) 1644 #define HCR_TTLBIS (1ULL << 54) 1645 #define HCR_TTLBOS (1ULL << 55) 1646 #define HCR_ATA (1ULL << 56) 1647 #define HCR_DCT (1ULL << 57) 1648 #define HCR_TID5 (1ULL << 58) 1649 #define HCR_TWEDEN (1ULL << 59) 1650 #define HCR_TWEDEL MAKE_64BIT_MASK(60, 4) 1651 1652 #define HCRX_ENAS0 (1ULL << 0) 1653 #define HCRX_ENALS (1ULL << 1) 1654 #define HCRX_ENASR (1ULL << 2) 1655 #define HCRX_FNXS (1ULL << 3) 1656 #define HCRX_FGTNXS (1ULL << 4) 1657 #define HCRX_SMPME (1ULL << 5) 1658 #define HCRX_TALLINT (1ULL << 6) 1659 #define HCRX_VINMI (1ULL << 7) 1660 #define HCRX_VFNMI (1ULL << 8) 1661 #define HCRX_CMOW (1ULL << 9) 1662 #define HCRX_MCE2 (1ULL << 10) 1663 #define HCRX_MSCEN (1ULL << 11) 1664 1665 #define HPFAR_NS (1ULL << 63) 1666 1667 #define SCR_NS (1ULL << 0) 1668 #define SCR_IRQ (1ULL << 1) 1669 #define SCR_FIQ (1ULL << 2) 1670 #define SCR_EA (1ULL << 3) 1671 #define SCR_FW (1ULL << 4) 1672 #define SCR_AW (1ULL << 5) 1673 #define SCR_NET (1ULL << 6) 1674 #define SCR_SMD (1ULL << 7) 1675 #define SCR_HCE (1ULL << 8) 1676 #define SCR_SIF (1ULL << 9) 1677 #define SCR_RW (1ULL << 10) 1678 #define SCR_ST (1ULL << 11) 1679 #define SCR_TWI (1ULL << 12) 1680 #define SCR_TWE (1ULL << 13) 1681 #define SCR_TLOR (1ULL << 14) 1682 #define SCR_TERR (1ULL << 15) 1683 #define SCR_APK (1ULL << 16) 1684 #define SCR_API (1ULL << 17) 1685 #define SCR_EEL2 (1ULL << 18) 1686 #define SCR_EASE (1ULL << 19) 1687 #define SCR_NMEA (1ULL << 20) 1688 #define SCR_FIEN (1ULL << 21) 1689 #define SCR_ENSCXT (1ULL << 25) 1690 #define SCR_ATA (1ULL << 26) 1691 #define SCR_FGTEN (1ULL << 27) 1692 #define SCR_ECVEN (1ULL << 28) 1693 #define SCR_TWEDEN (1ULL << 29) 1694 #define SCR_TWEDEL MAKE_64BIT_MASK(30, 4) 1695 #define SCR_TME (1ULL << 34) 1696 #define SCR_AMVOFFEN (1ULL << 35) 1697 #define SCR_ENAS0 (1ULL << 36) 1698 #define SCR_ADEN (1ULL << 37) 1699 #define SCR_HXEN (1ULL << 38) 1700 #define SCR_TRNDR (1ULL << 40) 1701 #define SCR_ENTP2 (1ULL << 41) 1702 #define SCR_GPF (1ULL << 48) 1703 1704 #define HSTR_TTEE (1 << 16) 1705 #define HSTR_TJDBX (1 << 17) 1706 1707 /* Return the current FPSCR value. */ 1708 uint32_t vfp_get_fpscr(CPUARMState *env); 1709 void vfp_set_fpscr(CPUARMState *env, uint32_t val); 1710 1711 /* FPCR, Floating Point Control Register 1712 * FPSR, Floating Poiht Status Register 1713 * 1714 * For A64 the FPSCR is split into two logically distinct registers, 1715 * FPCR and FPSR. However since they still use non-overlapping bits 1716 * we store the underlying state in fpscr and just mask on read/write. 1717 */ 1718 #define FPSR_MASK 0xf800009f 1719 #define FPCR_MASK 0x07ff9f00 1720 1721 #define FPCR_IOE (1 << 8) /* Invalid Operation exception trap enable */ 1722 #define FPCR_DZE (1 << 9) /* Divide by Zero exception trap enable */ 1723 #define FPCR_OFE (1 << 10) /* Overflow exception trap enable */ 1724 #define FPCR_UFE (1 << 11) /* Underflow exception trap enable */ 1725 #define FPCR_IXE (1 << 12) /* Inexact exception trap enable */ 1726 #define FPCR_IDE (1 << 15) /* Input Denormal exception trap enable */ 1727 #define FPCR_FZ16 (1 << 19) /* ARMv8.2+, FP16 flush-to-zero */ 1728 #define FPCR_RMODE_MASK (3 << 22) /* Rounding mode */ 1729 #define FPCR_FZ (1 << 24) /* Flush-to-zero enable bit */ 1730 #define FPCR_DN (1 << 25) /* Default NaN enable bit */ 1731 #define FPCR_AHP (1 << 26) /* Alternative half-precision */ 1732 #define FPCR_QC (1 << 27) /* Cumulative saturation bit */ 1733 #define FPCR_V (1 << 28) /* FP overflow flag */ 1734 #define FPCR_C (1 << 29) /* FP carry flag */ 1735 #define FPCR_Z (1 << 30) /* FP zero flag */ 1736 #define FPCR_N (1 << 31) /* FP negative flag */ 1737 1738 #define FPCR_LTPSIZE_SHIFT 16 /* LTPSIZE, M-profile only */ 1739 #define FPCR_LTPSIZE_MASK (7 << FPCR_LTPSIZE_SHIFT) 1740 #define FPCR_LTPSIZE_LENGTH 3 1741 1742 #define FPCR_NZCV_MASK (FPCR_N | FPCR_Z | FPCR_C | FPCR_V) 1743 #define FPCR_NZCVQC_MASK (FPCR_NZCV_MASK | FPCR_QC) 1744 1745 static inline uint32_t vfp_get_fpsr(CPUARMState *env) 1746 { 1747 return vfp_get_fpscr(env) & FPSR_MASK; 1748 } 1749 1750 static inline void vfp_set_fpsr(CPUARMState *env, uint32_t val) 1751 { 1752 uint32_t new_fpscr = (vfp_get_fpscr(env) & ~FPSR_MASK) | (val & FPSR_MASK); 1753 vfp_set_fpscr(env, new_fpscr); 1754 } 1755 1756 static inline uint32_t vfp_get_fpcr(CPUARMState *env) 1757 { 1758 return vfp_get_fpscr(env) & FPCR_MASK; 1759 } 1760 1761 static inline void vfp_set_fpcr(CPUARMState *env, uint32_t val) 1762 { 1763 uint32_t new_fpscr = (vfp_get_fpscr(env) & ~FPCR_MASK) | (val & FPCR_MASK); 1764 vfp_set_fpscr(env, new_fpscr); 1765 } 1766 1767 enum arm_cpu_mode { 1768 ARM_CPU_MODE_USR = 0x10, 1769 ARM_CPU_MODE_FIQ = 0x11, 1770 ARM_CPU_MODE_IRQ = 0x12, 1771 ARM_CPU_MODE_SVC = 0x13, 1772 ARM_CPU_MODE_MON = 0x16, 1773 ARM_CPU_MODE_ABT = 0x17, 1774 ARM_CPU_MODE_HYP = 0x1a, 1775 ARM_CPU_MODE_UND = 0x1b, 1776 ARM_CPU_MODE_SYS = 0x1f 1777 }; 1778 1779 /* VFP system registers. */ 1780 #define ARM_VFP_FPSID 0 1781 #define ARM_VFP_FPSCR 1 1782 #define ARM_VFP_MVFR2 5 1783 #define ARM_VFP_MVFR1 6 1784 #define ARM_VFP_MVFR0 7 1785 #define ARM_VFP_FPEXC 8 1786 #define ARM_VFP_FPINST 9 1787 #define ARM_VFP_FPINST2 10 1788 /* These ones are M-profile only */ 1789 #define ARM_VFP_FPSCR_NZCVQC 2 1790 #define ARM_VFP_VPR 12 1791 #define ARM_VFP_P0 13 1792 #define ARM_VFP_FPCXT_NS 14 1793 #define ARM_VFP_FPCXT_S 15 1794 1795 /* QEMU-internal value meaning "FPSCR, but we care only about NZCV" */ 1796 #define QEMU_VFP_FPSCR_NZCV 0xffff 1797 1798 /* iwMMXt coprocessor control registers. */ 1799 #define ARM_IWMMXT_wCID 0 1800 #define ARM_IWMMXT_wCon 1 1801 #define ARM_IWMMXT_wCSSF 2 1802 #define ARM_IWMMXT_wCASF 3 1803 #define ARM_IWMMXT_wCGR0 8 1804 #define ARM_IWMMXT_wCGR1 9 1805 #define ARM_IWMMXT_wCGR2 10 1806 #define ARM_IWMMXT_wCGR3 11 1807 1808 /* V7M CCR bits */ 1809 FIELD(V7M_CCR, NONBASETHRDENA, 0, 1) 1810 FIELD(V7M_CCR, USERSETMPEND, 1, 1) 1811 FIELD(V7M_CCR, UNALIGN_TRP, 3, 1) 1812 FIELD(V7M_CCR, DIV_0_TRP, 4, 1) 1813 FIELD(V7M_CCR, BFHFNMIGN, 8, 1) 1814 FIELD(V7M_CCR, STKALIGN, 9, 1) 1815 FIELD(V7M_CCR, STKOFHFNMIGN, 10, 1) 1816 FIELD(V7M_CCR, DC, 16, 1) 1817 FIELD(V7M_CCR, IC, 17, 1) 1818 FIELD(V7M_CCR, BP, 18, 1) 1819 FIELD(V7M_CCR, LOB, 19, 1) 1820 FIELD(V7M_CCR, TRD, 20, 1) 1821 1822 /* V7M SCR bits */ 1823 FIELD(V7M_SCR, SLEEPONEXIT, 1, 1) 1824 FIELD(V7M_SCR, SLEEPDEEP, 2, 1) 1825 FIELD(V7M_SCR, SLEEPDEEPS, 3, 1) 1826 FIELD(V7M_SCR, SEVONPEND, 4, 1) 1827 1828 /* V7M AIRCR bits */ 1829 FIELD(V7M_AIRCR, VECTRESET, 0, 1) 1830 FIELD(V7M_AIRCR, VECTCLRACTIVE, 1, 1) 1831 FIELD(V7M_AIRCR, SYSRESETREQ, 2, 1) 1832 FIELD(V7M_AIRCR, SYSRESETREQS, 3, 1) 1833 FIELD(V7M_AIRCR, PRIGROUP, 8, 3) 1834 FIELD(V7M_AIRCR, BFHFNMINS, 13, 1) 1835 FIELD(V7M_AIRCR, PRIS, 14, 1) 1836 FIELD(V7M_AIRCR, ENDIANNESS, 15, 1) 1837 FIELD(V7M_AIRCR, VECTKEY, 16, 16) 1838 1839 /* V7M CFSR bits for MMFSR */ 1840 FIELD(V7M_CFSR, IACCVIOL, 0, 1) 1841 FIELD(V7M_CFSR, DACCVIOL, 1, 1) 1842 FIELD(V7M_CFSR, MUNSTKERR, 3, 1) 1843 FIELD(V7M_CFSR, MSTKERR, 4, 1) 1844 FIELD(V7M_CFSR, MLSPERR, 5, 1) 1845 FIELD(V7M_CFSR, MMARVALID, 7, 1) 1846 1847 /* V7M CFSR bits for BFSR */ 1848 FIELD(V7M_CFSR, IBUSERR, 8 + 0, 1) 1849 FIELD(V7M_CFSR, PRECISERR, 8 + 1, 1) 1850 FIELD(V7M_CFSR, IMPRECISERR, 8 + 2, 1) 1851 FIELD(V7M_CFSR, UNSTKERR, 8 + 3, 1) 1852 FIELD(V7M_CFSR, STKERR, 8 + 4, 1) 1853 FIELD(V7M_CFSR, LSPERR, 8 + 5, 1) 1854 FIELD(V7M_CFSR, BFARVALID, 8 + 7, 1) 1855 1856 /* V7M CFSR bits for UFSR */ 1857 FIELD(V7M_CFSR, UNDEFINSTR, 16 + 0, 1) 1858 FIELD(V7M_CFSR, INVSTATE, 16 + 1, 1) 1859 FIELD(V7M_CFSR, INVPC, 16 + 2, 1) 1860 FIELD(V7M_CFSR, NOCP, 16 + 3, 1) 1861 FIELD(V7M_CFSR, STKOF, 16 + 4, 1) 1862 FIELD(V7M_CFSR, UNALIGNED, 16 + 8, 1) 1863 FIELD(V7M_CFSR, DIVBYZERO, 16 + 9, 1) 1864 1865 /* V7M CFSR bit masks covering all of the subregister bits */ 1866 FIELD(V7M_CFSR, MMFSR, 0, 8) 1867 FIELD(V7M_CFSR, BFSR, 8, 8) 1868 FIELD(V7M_CFSR, UFSR, 16, 16) 1869 1870 /* V7M HFSR bits */ 1871 FIELD(V7M_HFSR, VECTTBL, 1, 1) 1872 FIELD(V7M_HFSR, FORCED, 30, 1) 1873 FIELD(V7M_HFSR, DEBUGEVT, 31, 1) 1874 1875 /* V7M DFSR bits */ 1876 FIELD(V7M_DFSR, HALTED, 0, 1) 1877 FIELD(V7M_DFSR, BKPT, 1, 1) 1878 FIELD(V7M_DFSR, DWTTRAP, 2, 1) 1879 FIELD(V7M_DFSR, VCATCH, 3, 1) 1880 FIELD(V7M_DFSR, EXTERNAL, 4, 1) 1881 1882 /* V7M SFSR bits */ 1883 FIELD(V7M_SFSR, INVEP, 0, 1) 1884 FIELD(V7M_SFSR, INVIS, 1, 1) 1885 FIELD(V7M_SFSR, INVER, 2, 1) 1886 FIELD(V7M_SFSR, AUVIOL, 3, 1) 1887 FIELD(V7M_SFSR, INVTRAN, 4, 1) 1888 FIELD(V7M_SFSR, LSPERR, 5, 1) 1889 FIELD(V7M_SFSR, SFARVALID, 6, 1) 1890 FIELD(V7M_SFSR, LSERR, 7, 1) 1891 1892 /* v7M MPU_CTRL bits */ 1893 FIELD(V7M_MPU_CTRL, ENABLE, 0, 1) 1894 FIELD(V7M_MPU_CTRL, HFNMIENA, 1, 1) 1895 FIELD(V7M_MPU_CTRL, PRIVDEFENA, 2, 1) 1896 1897 /* v7M CLIDR bits */ 1898 FIELD(V7M_CLIDR, CTYPE_ALL, 0, 21) 1899 FIELD(V7M_CLIDR, LOUIS, 21, 3) 1900 FIELD(V7M_CLIDR, LOC, 24, 3) 1901 FIELD(V7M_CLIDR, LOUU, 27, 3) 1902 FIELD(V7M_CLIDR, ICB, 30, 2) 1903 1904 FIELD(V7M_CSSELR, IND, 0, 1) 1905 FIELD(V7M_CSSELR, LEVEL, 1, 3) 1906 /* We use the combination of InD and Level to index into cpu->ccsidr[]; 1907 * define a mask for this and check that it doesn't permit running off 1908 * the end of the array. 1909 */ 1910 FIELD(V7M_CSSELR, INDEX, 0, 4) 1911 1912 /* v7M FPCCR bits */ 1913 FIELD(V7M_FPCCR, LSPACT, 0, 1) 1914 FIELD(V7M_FPCCR, USER, 1, 1) 1915 FIELD(V7M_FPCCR, S, 2, 1) 1916 FIELD(V7M_FPCCR, THREAD, 3, 1) 1917 FIELD(V7M_FPCCR, HFRDY, 4, 1) 1918 FIELD(V7M_FPCCR, MMRDY, 5, 1) 1919 FIELD(V7M_FPCCR, BFRDY, 6, 1) 1920 FIELD(V7M_FPCCR, SFRDY, 7, 1) 1921 FIELD(V7M_FPCCR, MONRDY, 8, 1) 1922 FIELD(V7M_FPCCR, SPLIMVIOL, 9, 1) 1923 FIELD(V7M_FPCCR, UFRDY, 10, 1) 1924 FIELD(V7M_FPCCR, RES0, 11, 15) 1925 FIELD(V7M_FPCCR, TS, 26, 1) 1926 FIELD(V7M_FPCCR, CLRONRETS, 27, 1) 1927 FIELD(V7M_FPCCR, CLRONRET, 28, 1) 1928 FIELD(V7M_FPCCR, LSPENS, 29, 1) 1929 FIELD(V7M_FPCCR, LSPEN, 30, 1) 1930 FIELD(V7M_FPCCR, ASPEN, 31, 1) 1931 /* These bits are banked. Others are non-banked and live in the M_REG_S bank */ 1932 #define R_V7M_FPCCR_BANKED_MASK \ 1933 (R_V7M_FPCCR_LSPACT_MASK | \ 1934 R_V7M_FPCCR_USER_MASK | \ 1935 R_V7M_FPCCR_THREAD_MASK | \ 1936 R_V7M_FPCCR_MMRDY_MASK | \ 1937 R_V7M_FPCCR_SPLIMVIOL_MASK | \ 1938 R_V7M_FPCCR_UFRDY_MASK | \ 1939 R_V7M_FPCCR_ASPEN_MASK) 1940 1941 /* v7M VPR bits */ 1942 FIELD(V7M_VPR, P0, 0, 16) 1943 FIELD(V7M_VPR, MASK01, 16, 4) 1944 FIELD(V7M_VPR, MASK23, 20, 4) 1945 1946 /* 1947 * System register ID fields. 1948 */ 1949 FIELD(CLIDR_EL1, CTYPE1, 0, 3) 1950 FIELD(CLIDR_EL1, CTYPE2, 3, 3) 1951 FIELD(CLIDR_EL1, CTYPE3, 6, 3) 1952 FIELD(CLIDR_EL1, CTYPE4, 9, 3) 1953 FIELD(CLIDR_EL1, CTYPE5, 12, 3) 1954 FIELD(CLIDR_EL1, CTYPE6, 15, 3) 1955 FIELD(CLIDR_EL1, CTYPE7, 18, 3) 1956 FIELD(CLIDR_EL1, LOUIS, 21, 3) 1957 FIELD(CLIDR_EL1, LOC, 24, 3) 1958 FIELD(CLIDR_EL1, LOUU, 27, 3) 1959 FIELD(CLIDR_EL1, ICB, 30, 3) 1960 1961 /* When FEAT_CCIDX is implemented */ 1962 FIELD(CCSIDR_EL1, CCIDX_LINESIZE, 0, 3) 1963 FIELD(CCSIDR_EL1, CCIDX_ASSOCIATIVITY, 3, 21) 1964 FIELD(CCSIDR_EL1, CCIDX_NUMSETS, 32, 24) 1965 1966 /* When FEAT_CCIDX is not implemented */ 1967 FIELD(CCSIDR_EL1, LINESIZE, 0, 3) 1968 FIELD(CCSIDR_EL1, ASSOCIATIVITY, 3, 10) 1969 FIELD(CCSIDR_EL1, NUMSETS, 13, 15) 1970 1971 FIELD(CTR_EL0, IMINLINE, 0, 4) 1972 FIELD(CTR_EL0, L1IP, 14, 2) 1973 FIELD(CTR_EL0, DMINLINE, 16, 4) 1974 FIELD(CTR_EL0, ERG, 20, 4) 1975 FIELD(CTR_EL0, CWG, 24, 4) 1976 FIELD(CTR_EL0, IDC, 28, 1) 1977 FIELD(CTR_EL0, DIC, 29, 1) 1978 FIELD(CTR_EL0, TMINLINE, 32, 6) 1979 1980 FIELD(MIDR_EL1, REVISION, 0, 4) 1981 FIELD(MIDR_EL1, PARTNUM, 4, 12) 1982 FIELD(MIDR_EL1, ARCHITECTURE, 16, 4) 1983 FIELD(MIDR_EL1, VARIANT, 20, 4) 1984 FIELD(MIDR_EL1, IMPLEMENTER, 24, 8) 1985 1986 FIELD(ID_ISAR0, SWAP, 0, 4) 1987 FIELD(ID_ISAR0, BITCOUNT, 4, 4) 1988 FIELD(ID_ISAR0, BITFIELD, 8, 4) 1989 FIELD(ID_ISAR0, CMPBRANCH, 12, 4) 1990 FIELD(ID_ISAR0, COPROC, 16, 4) 1991 FIELD(ID_ISAR0, DEBUG, 20, 4) 1992 FIELD(ID_ISAR0, DIVIDE, 24, 4) 1993 1994 FIELD(ID_ISAR1, ENDIAN, 0, 4) 1995 FIELD(ID_ISAR1, EXCEPT, 4, 4) 1996 FIELD(ID_ISAR1, EXCEPT_AR, 8, 4) 1997 FIELD(ID_ISAR1, EXTEND, 12, 4) 1998 FIELD(ID_ISAR1, IFTHEN, 16, 4) 1999 FIELD(ID_ISAR1, IMMEDIATE, 20, 4) 2000 FIELD(ID_ISAR1, INTERWORK, 24, 4) 2001 FIELD(ID_ISAR1, JAZELLE, 28, 4) 2002 2003 FIELD(ID_ISAR2, LOADSTORE, 0, 4) 2004 FIELD(ID_ISAR2, MEMHINT, 4, 4) 2005 FIELD(ID_ISAR2, MULTIACCESSINT, 8, 4) 2006 FIELD(ID_ISAR2, MULT, 12, 4) 2007 FIELD(ID_ISAR2, MULTS, 16, 4) 2008 FIELD(ID_ISAR2, MULTU, 20, 4) 2009 FIELD(ID_ISAR2, PSR_AR, 24, 4) 2010 FIELD(ID_ISAR2, REVERSAL, 28, 4) 2011 2012 FIELD(ID_ISAR3, SATURATE, 0, 4) 2013 FIELD(ID_ISAR3, SIMD, 4, 4) 2014 FIELD(ID_ISAR3, SVC, 8, 4) 2015 FIELD(ID_ISAR3, SYNCHPRIM, 12, 4) 2016 FIELD(ID_ISAR3, TABBRANCH, 16, 4) 2017 FIELD(ID_ISAR3, T32COPY, 20, 4) 2018 FIELD(ID_ISAR3, TRUENOP, 24, 4) 2019 FIELD(ID_ISAR3, T32EE, 28, 4) 2020 2021 FIELD(ID_ISAR4, UNPRIV, 0, 4) 2022 FIELD(ID_ISAR4, WITHSHIFTS, 4, 4) 2023 FIELD(ID_ISAR4, WRITEBACK, 8, 4) 2024 FIELD(ID_ISAR4, SMC, 12, 4) 2025 FIELD(ID_ISAR4, BARRIER, 16, 4) 2026 FIELD(ID_ISAR4, SYNCHPRIM_FRAC, 20, 4) 2027 FIELD(ID_ISAR4, PSR_M, 24, 4) 2028 FIELD(ID_ISAR4, SWP_FRAC, 28, 4) 2029 2030 FIELD(ID_ISAR5, SEVL, 0, 4) 2031 FIELD(ID_ISAR5, AES, 4, 4) 2032 FIELD(ID_ISAR5, SHA1, 8, 4) 2033 FIELD(ID_ISAR5, SHA2, 12, 4) 2034 FIELD(ID_ISAR5, CRC32, 16, 4) 2035 FIELD(ID_ISAR5, RDM, 24, 4) 2036 FIELD(ID_ISAR5, VCMA, 28, 4) 2037 2038 FIELD(ID_ISAR6, JSCVT, 0, 4) 2039 FIELD(ID_ISAR6, DP, 4, 4) 2040 FIELD(ID_ISAR6, FHM, 8, 4) 2041 FIELD(ID_ISAR6, SB, 12, 4) 2042 FIELD(ID_ISAR6, SPECRES, 16, 4) 2043 FIELD(ID_ISAR6, BF16, 20, 4) 2044 FIELD(ID_ISAR6, I8MM, 24, 4) 2045 2046 FIELD(ID_MMFR0, VMSA, 0, 4) 2047 FIELD(ID_MMFR0, PMSA, 4, 4) 2048 FIELD(ID_MMFR0, OUTERSHR, 8, 4) 2049 FIELD(ID_MMFR0, SHARELVL, 12, 4) 2050 FIELD(ID_MMFR0, TCM, 16, 4) 2051 FIELD(ID_MMFR0, AUXREG, 20, 4) 2052 FIELD(ID_MMFR0, FCSE, 24, 4) 2053 FIELD(ID_MMFR0, INNERSHR, 28, 4) 2054 2055 FIELD(ID_MMFR1, L1HVDVA, 0, 4) 2056 FIELD(ID_MMFR1, L1UNIVA, 4, 4) 2057 FIELD(ID_MMFR1, L1HVDSW, 8, 4) 2058 FIELD(ID_MMFR1, L1UNISW, 12, 4) 2059 FIELD(ID_MMFR1, L1HVD, 16, 4) 2060 FIELD(ID_MMFR1, L1UNI, 20, 4) 2061 FIELD(ID_MMFR1, L1TSTCLN, 24, 4) 2062 FIELD(ID_MMFR1, BPRED, 28, 4) 2063 2064 FIELD(ID_MMFR2, L1HVDFG, 0, 4) 2065 FIELD(ID_MMFR2, L1HVDBG, 4, 4) 2066 FIELD(ID_MMFR2, L1HVDRNG, 8, 4) 2067 FIELD(ID_MMFR2, HVDTLB, 12, 4) 2068 FIELD(ID_MMFR2, UNITLB, 16, 4) 2069 FIELD(ID_MMFR2, MEMBARR, 20, 4) 2070 FIELD(ID_MMFR2, WFISTALL, 24, 4) 2071 FIELD(ID_MMFR2, HWACCFLG, 28, 4) 2072 2073 FIELD(ID_MMFR3, CMAINTVA, 0, 4) 2074 FIELD(ID_MMFR3, CMAINTSW, 4, 4) 2075 FIELD(ID_MMFR3, BPMAINT, 8, 4) 2076 FIELD(ID_MMFR3, MAINTBCST, 12, 4) 2077 FIELD(ID_MMFR3, PAN, 16, 4) 2078 FIELD(ID_MMFR3, COHWALK, 20, 4) 2079 FIELD(ID_MMFR3, CMEMSZ, 24, 4) 2080 FIELD(ID_MMFR3, SUPERSEC, 28, 4) 2081 2082 FIELD(ID_MMFR4, SPECSEI, 0, 4) 2083 FIELD(ID_MMFR4, AC2, 4, 4) 2084 FIELD(ID_MMFR4, XNX, 8, 4) 2085 FIELD(ID_MMFR4, CNP, 12, 4) 2086 FIELD(ID_MMFR4, HPDS, 16, 4) 2087 FIELD(ID_MMFR4, LSM, 20, 4) 2088 FIELD(ID_MMFR4, CCIDX, 24, 4) 2089 FIELD(ID_MMFR4, EVT, 28, 4) 2090 2091 FIELD(ID_MMFR5, ETS, 0, 4) 2092 FIELD(ID_MMFR5, NTLBPA, 4, 4) 2093 2094 FIELD(ID_PFR0, STATE0, 0, 4) 2095 FIELD(ID_PFR0, STATE1, 4, 4) 2096 FIELD(ID_PFR0, STATE2, 8, 4) 2097 FIELD(ID_PFR0, STATE3, 12, 4) 2098 FIELD(ID_PFR0, CSV2, 16, 4) 2099 FIELD(ID_PFR0, AMU, 20, 4) 2100 FIELD(ID_PFR0, DIT, 24, 4) 2101 FIELD(ID_PFR0, RAS, 28, 4) 2102 2103 FIELD(ID_PFR1, PROGMOD, 0, 4) 2104 FIELD(ID_PFR1, SECURITY, 4, 4) 2105 FIELD(ID_PFR1, MPROGMOD, 8, 4) 2106 FIELD(ID_PFR1, VIRTUALIZATION, 12, 4) 2107 FIELD(ID_PFR1, GENTIMER, 16, 4) 2108 FIELD(ID_PFR1, SEC_FRAC, 20, 4) 2109 FIELD(ID_PFR1, VIRT_FRAC, 24, 4) 2110 FIELD(ID_PFR1, GIC, 28, 4) 2111 2112 FIELD(ID_PFR2, CSV3, 0, 4) 2113 FIELD(ID_PFR2, SSBS, 4, 4) 2114 FIELD(ID_PFR2, RAS_FRAC, 8, 4) 2115 2116 FIELD(ID_AA64ISAR0, AES, 4, 4) 2117 FIELD(ID_AA64ISAR0, SHA1, 8, 4) 2118 FIELD(ID_AA64ISAR0, SHA2, 12, 4) 2119 FIELD(ID_AA64ISAR0, CRC32, 16, 4) 2120 FIELD(ID_AA64ISAR0, ATOMIC, 20, 4) 2121 FIELD(ID_AA64ISAR0, RDM, 28, 4) 2122 FIELD(ID_AA64ISAR0, SHA3, 32, 4) 2123 FIELD(ID_AA64ISAR0, SM3, 36, 4) 2124 FIELD(ID_AA64ISAR0, SM4, 40, 4) 2125 FIELD(ID_AA64ISAR0, DP, 44, 4) 2126 FIELD(ID_AA64ISAR0, FHM, 48, 4) 2127 FIELD(ID_AA64ISAR0, TS, 52, 4) 2128 FIELD(ID_AA64ISAR0, TLB, 56, 4) 2129 FIELD(ID_AA64ISAR0, RNDR, 60, 4) 2130 2131 FIELD(ID_AA64ISAR1, DPB, 0, 4) 2132 FIELD(ID_AA64ISAR1, APA, 4, 4) 2133 FIELD(ID_AA64ISAR1, API, 8, 4) 2134 FIELD(ID_AA64ISAR1, JSCVT, 12, 4) 2135 FIELD(ID_AA64ISAR1, FCMA, 16, 4) 2136 FIELD(ID_AA64ISAR1, LRCPC, 20, 4) 2137 FIELD(ID_AA64ISAR1, GPA, 24, 4) 2138 FIELD(ID_AA64ISAR1, GPI, 28, 4) 2139 FIELD(ID_AA64ISAR1, FRINTTS, 32, 4) 2140 FIELD(ID_AA64ISAR1, SB, 36, 4) 2141 FIELD(ID_AA64ISAR1, SPECRES, 40, 4) 2142 FIELD(ID_AA64ISAR1, BF16, 44, 4) 2143 FIELD(ID_AA64ISAR1, DGH, 48, 4) 2144 FIELD(ID_AA64ISAR1, I8MM, 52, 4) 2145 FIELD(ID_AA64ISAR1, XS, 56, 4) 2146 FIELD(ID_AA64ISAR1, LS64, 60, 4) 2147 2148 FIELD(ID_AA64ISAR2, WFXT, 0, 4) 2149 FIELD(ID_AA64ISAR2, RPRES, 4, 4) 2150 FIELD(ID_AA64ISAR2, GPA3, 8, 4) 2151 FIELD(ID_AA64ISAR2, APA3, 12, 4) 2152 FIELD(ID_AA64ISAR2, MOPS, 16, 4) 2153 FIELD(ID_AA64ISAR2, BC, 20, 4) 2154 FIELD(ID_AA64ISAR2, PAC_FRAC, 24, 4) 2155 2156 FIELD(ID_AA64PFR0, EL0, 0, 4) 2157 FIELD(ID_AA64PFR0, EL1, 4, 4) 2158 FIELD(ID_AA64PFR0, EL2, 8, 4) 2159 FIELD(ID_AA64PFR0, EL3, 12, 4) 2160 FIELD(ID_AA64PFR0, FP, 16, 4) 2161 FIELD(ID_AA64PFR0, ADVSIMD, 20, 4) 2162 FIELD(ID_AA64PFR0, GIC, 24, 4) 2163 FIELD(ID_AA64PFR0, RAS, 28, 4) 2164 FIELD(ID_AA64PFR0, SVE, 32, 4) 2165 FIELD(ID_AA64PFR0, SEL2, 36, 4) 2166 FIELD(ID_AA64PFR0, MPAM, 40, 4) 2167 FIELD(ID_AA64PFR0, AMU, 44, 4) 2168 FIELD(ID_AA64PFR0, DIT, 48, 4) 2169 FIELD(ID_AA64PFR0, CSV2, 56, 4) 2170 FIELD(ID_AA64PFR0, CSV3, 60, 4) 2171 2172 FIELD(ID_AA64PFR1, BT, 0, 4) 2173 FIELD(ID_AA64PFR1, SSBS, 4, 4) 2174 FIELD(ID_AA64PFR1, MTE, 8, 4) 2175 FIELD(ID_AA64PFR1, RAS_FRAC, 12, 4) 2176 FIELD(ID_AA64PFR1, MPAM_FRAC, 16, 4) 2177 FIELD(ID_AA64PFR1, SME, 24, 4) 2178 FIELD(ID_AA64PFR1, RNDR_TRAP, 28, 4) 2179 FIELD(ID_AA64PFR1, CSV2_FRAC, 32, 4) 2180 FIELD(ID_AA64PFR1, NMI, 36, 4) 2181 2182 FIELD(ID_AA64MMFR0, PARANGE, 0, 4) 2183 FIELD(ID_AA64MMFR0, ASIDBITS, 4, 4) 2184 FIELD(ID_AA64MMFR0, BIGEND, 8, 4) 2185 FIELD(ID_AA64MMFR0, SNSMEM, 12, 4) 2186 FIELD(ID_AA64MMFR0, BIGENDEL0, 16, 4) 2187 FIELD(ID_AA64MMFR0, TGRAN16, 20, 4) 2188 FIELD(ID_AA64MMFR0, TGRAN64, 24, 4) 2189 FIELD(ID_AA64MMFR0, TGRAN4, 28, 4) 2190 FIELD(ID_AA64MMFR0, TGRAN16_2, 32, 4) 2191 FIELD(ID_AA64MMFR0, TGRAN64_2, 36, 4) 2192 FIELD(ID_AA64MMFR0, TGRAN4_2, 40, 4) 2193 FIELD(ID_AA64MMFR0, EXS, 44, 4) 2194 FIELD(ID_AA64MMFR0, FGT, 56, 4) 2195 FIELD(ID_AA64MMFR0, ECV, 60, 4) 2196 2197 FIELD(ID_AA64MMFR1, HAFDBS, 0, 4) 2198 FIELD(ID_AA64MMFR1, VMIDBITS, 4, 4) 2199 FIELD(ID_AA64MMFR1, VH, 8, 4) 2200 FIELD(ID_AA64MMFR1, HPDS, 12, 4) 2201 FIELD(ID_AA64MMFR1, LO, 16, 4) 2202 FIELD(ID_AA64MMFR1, PAN, 20, 4) 2203 FIELD(ID_AA64MMFR1, SPECSEI, 24, 4) 2204 FIELD(ID_AA64MMFR1, XNX, 28, 4) 2205 FIELD(ID_AA64MMFR1, TWED, 32, 4) 2206 FIELD(ID_AA64MMFR1, ETS, 36, 4) 2207 FIELD(ID_AA64MMFR1, HCX, 40, 4) 2208 FIELD(ID_AA64MMFR1, AFP, 44, 4) 2209 FIELD(ID_AA64MMFR1, NTLBPA, 48, 4) 2210 FIELD(ID_AA64MMFR1, TIDCP1, 52, 4) 2211 FIELD(ID_AA64MMFR1, CMOW, 56, 4) 2212 2213 FIELD(ID_AA64MMFR2, CNP, 0, 4) 2214 FIELD(ID_AA64MMFR2, UAO, 4, 4) 2215 FIELD(ID_AA64MMFR2, LSM, 8, 4) 2216 FIELD(ID_AA64MMFR2, IESB, 12, 4) 2217 FIELD(ID_AA64MMFR2, VARANGE, 16, 4) 2218 FIELD(ID_AA64MMFR2, CCIDX, 20, 4) 2219 FIELD(ID_AA64MMFR2, NV, 24, 4) 2220 FIELD(ID_AA64MMFR2, ST, 28, 4) 2221 FIELD(ID_AA64MMFR2, AT, 32, 4) 2222 FIELD(ID_AA64MMFR2, IDS, 36, 4) 2223 FIELD(ID_AA64MMFR2, FWB, 40, 4) 2224 FIELD(ID_AA64MMFR2, TTL, 48, 4) 2225 FIELD(ID_AA64MMFR2, BBM, 52, 4) 2226 FIELD(ID_AA64MMFR2, EVT, 56, 4) 2227 FIELD(ID_AA64MMFR2, E0PD, 60, 4) 2228 2229 FIELD(ID_AA64DFR0, DEBUGVER, 0, 4) 2230 FIELD(ID_AA64DFR0, TRACEVER, 4, 4) 2231 FIELD(ID_AA64DFR0, PMUVER, 8, 4) 2232 FIELD(ID_AA64DFR0, BRPS, 12, 4) 2233 FIELD(ID_AA64DFR0, WRPS, 20, 4) 2234 FIELD(ID_AA64DFR0, CTX_CMPS, 28, 4) 2235 FIELD(ID_AA64DFR0, PMSVER, 32, 4) 2236 FIELD(ID_AA64DFR0, DOUBLELOCK, 36, 4) 2237 FIELD(ID_AA64DFR0, TRACEFILT, 40, 4) 2238 FIELD(ID_AA64DFR0, TRACEBUFFER, 44, 4) 2239 FIELD(ID_AA64DFR0, MTPMU, 48, 4) 2240 FIELD(ID_AA64DFR0, BRBE, 52, 4) 2241 FIELD(ID_AA64DFR0, HPMN0, 60, 4) 2242 2243 FIELD(ID_AA64ZFR0, SVEVER, 0, 4) 2244 FIELD(ID_AA64ZFR0, AES, 4, 4) 2245 FIELD(ID_AA64ZFR0, BITPERM, 16, 4) 2246 FIELD(ID_AA64ZFR0, BFLOAT16, 20, 4) 2247 FIELD(ID_AA64ZFR0, SHA3, 32, 4) 2248 FIELD(ID_AA64ZFR0, SM4, 40, 4) 2249 FIELD(ID_AA64ZFR0, I8MM, 44, 4) 2250 FIELD(ID_AA64ZFR0, F32MM, 52, 4) 2251 FIELD(ID_AA64ZFR0, F64MM, 56, 4) 2252 2253 FIELD(ID_AA64SMFR0, F32F32, 32, 1) 2254 FIELD(ID_AA64SMFR0, B16F32, 34, 1) 2255 FIELD(ID_AA64SMFR0, F16F32, 35, 1) 2256 FIELD(ID_AA64SMFR0, I8I32, 36, 4) 2257 FIELD(ID_AA64SMFR0, F64F64, 48, 1) 2258 FIELD(ID_AA64SMFR0, I16I64, 52, 4) 2259 FIELD(ID_AA64SMFR0, SMEVER, 56, 4) 2260 FIELD(ID_AA64SMFR0, FA64, 63, 1) 2261 2262 FIELD(ID_DFR0, COPDBG, 0, 4) 2263 FIELD(ID_DFR0, COPSDBG, 4, 4) 2264 FIELD(ID_DFR0, MMAPDBG, 8, 4) 2265 FIELD(ID_DFR0, COPTRC, 12, 4) 2266 FIELD(ID_DFR0, MMAPTRC, 16, 4) 2267 FIELD(ID_DFR0, MPROFDBG, 20, 4) 2268 FIELD(ID_DFR0, PERFMON, 24, 4) 2269 FIELD(ID_DFR0, TRACEFILT, 28, 4) 2270 2271 FIELD(ID_DFR1, MTPMU, 0, 4) 2272 FIELD(ID_DFR1, HPMN0, 4, 4) 2273 2274 FIELD(DBGDIDR, SE_IMP, 12, 1) 2275 FIELD(DBGDIDR, NSUHD_IMP, 14, 1) 2276 FIELD(DBGDIDR, VERSION, 16, 4) 2277 FIELD(DBGDIDR, CTX_CMPS, 20, 4) 2278 FIELD(DBGDIDR, BRPS, 24, 4) 2279 FIELD(DBGDIDR, WRPS, 28, 4) 2280 2281 FIELD(DBGDEVID, PCSAMPLE, 0, 4) 2282 FIELD(DBGDEVID, WPADDRMASK, 4, 4) 2283 FIELD(DBGDEVID, BPADDRMASK, 8, 4) 2284 FIELD(DBGDEVID, VECTORCATCH, 12, 4) 2285 FIELD(DBGDEVID, VIRTEXTNS, 16, 4) 2286 FIELD(DBGDEVID, DOUBLELOCK, 20, 4) 2287 FIELD(DBGDEVID, AUXREGS, 24, 4) 2288 FIELD(DBGDEVID, CIDMASK, 28, 4) 2289 2290 FIELD(MVFR0, SIMDREG, 0, 4) 2291 FIELD(MVFR0, FPSP, 4, 4) 2292 FIELD(MVFR0, FPDP, 8, 4) 2293 FIELD(MVFR0, FPTRAP, 12, 4) 2294 FIELD(MVFR0, FPDIVIDE, 16, 4) 2295 FIELD(MVFR0, FPSQRT, 20, 4) 2296 FIELD(MVFR0, FPSHVEC, 24, 4) 2297 FIELD(MVFR0, FPROUND, 28, 4) 2298 2299 FIELD(MVFR1, FPFTZ, 0, 4) 2300 FIELD(MVFR1, FPDNAN, 4, 4) 2301 FIELD(MVFR1, SIMDLS, 8, 4) /* A-profile only */ 2302 FIELD(MVFR1, SIMDINT, 12, 4) /* A-profile only */ 2303 FIELD(MVFR1, SIMDSP, 16, 4) /* A-profile only */ 2304 FIELD(MVFR1, SIMDHP, 20, 4) /* A-profile only */ 2305 FIELD(MVFR1, MVE, 8, 4) /* M-profile only */ 2306 FIELD(MVFR1, FP16, 20, 4) /* M-profile only */ 2307 FIELD(MVFR1, FPHP, 24, 4) 2308 FIELD(MVFR1, SIMDFMAC, 28, 4) 2309 2310 FIELD(MVFR2, SIMDMISC, 0, 4) 2311 FIELD(MVFR2, FPMISC, 4, 4) 2312 2313 QEMU_BUILD_BUG_ON(ARRAY_SIZE(((ARMCPU *)0)->ccsidr) <= R_V7M_CSSELR_INDEX_MASK); 2314 2315 /* If adding a feature bit which corresponds to a Linux ELF 2316 * HWCAP bit, remember to update the feature-bit-to-hwcap 2317 * mapping in linux-user/elfload.c:get_elf_hwcap(). 2318 */ 2319 enum arm_features { 2320 ARM_FEATURE_AUXCR, /* ARM1026 Auxiliary control register. */ 2321 ARM_FEATURE_XSCALE, /* Intel XScale extensions. */ 2322 ARM_FEATURE_IWMMXT, /* Intel iwMMXt extension. */ 2323 ARM_FEATURE_V6, 2324 ARM_FEATURE_V6K, 2325 ARM_FEATURE_V7, 2326 ARM_FEATURE_THUMB2, 2327 ARM_FEATURE_PMSA, /* no MMU; may have Memory Protection Unit */ 2328 ARM_FEATURE_NEON, 2329 ARM_FEATURE_M, /* Microcontroller profile. */ 2330 ARM_FEATURE_OMAPCP, /* OMAP specific CP15 ops handling. */ 2331 ARM_FEATURE_THUMB2EE, 2332 ARM_FEATURE_V7MP, /* v7 Multiprocessing Extensions */ 2333 ARM_FEATURE_V7VE, /* v7 Virtualization Extensions (non-EL2 parts) */ 2334 ARM_FEATURE_V4T, 2335 ARM_FEATURE_V5, 2336 ARM_FEATURE_STRONGARM, 2337 ARM_FEATURE_VAPA, /* cp15 VA to PA lookups */ 2338 ARM_FEATURE_GENERIC_TIMER, 2339 ARM_FEATURE_MVFR, /* Media and VFP Feature Registers 0 and 1 */ 2340 ARM_FEATURE_DUMMY_C15_REGS, /* RAZ/WI all of cp15 crn=15 */ 2341 ARM_FEATURE_CACHE_TEST_CLEAN, /* 926/1026 style test-and-clean ops */ 2342 ARM_FEATURE_CACHE_DIRTY_REG, /* 1136/1176 cache dirty status register */ 2343 ARM_FEATURE_CACHE_BLOCK_OPS, /* v6 optional cache block operations */ 2344 ARM_FEATURE_MPIDR, /* has cp15 MPIDR */ 2345 ARM_FEATURE_LPAE, /* has Large Physical Address Extension */ 2346 ARM_FEATURE_V8, 2347 ARM_FEATURE_AARCH64, /* supports 64 bit mode */ 2348 ARM_FEATURE_CBAR, /* has cp15 CBAR */ 2349 ARM_FEATURE_CBAR_RO, /* has cp15 CBAR and it is read-only */ 2350 ARM_FEATURE_EL2, /* has EL2 Virtualization support */ 2351 ARM_FEATURE_EL3, /* has EL3 Secure monitor support */ 2352 ARM_FEATURE_THUMB_DSP, /* DSP insns supported in the Thumb encodings */ 2353 ARM_FEATURE_PMU, /* has PMU support */ 2354 ARM_FEATURE_VBAR, /* has cp15 VBAR */ 2355 ARM_FEATURE_M_SECURITY, /* M profile Security Extension */ 2356 ARM_FEATURE_M_MAIN, /* M profile Main Extension */ 2357 ARM_FEATURE_V8_1M, /* M profile extras only in v8.1M and later */ 2358 }; 2359 2360 static inline int arm_feature(CPUARMState *env, int feature) 2361 { 2362 return (env->features & (1ULL << feature)) != 0; 2363 } 2364 2365 void arm_cpu_finalize_features(ARMCPU *cpu, Error **errp); 2366 2367 #if !defined(CONFIG_USER_ONLY) 2368 /* Return true if exception levels below EL3 are in secure state, 2369 * or would be following an exception return to that level. 2370 * Unlike arm_is_secure() (which is always a question about the 2371 * _current_ state of the CPU) this doesn't care about the current 2372 * EL or mode. 2373 */ 2374 static inline bool arm_is_secure_below_el3(CPUARMState *env) 2375 { 2376 if (arm_feature(env, ARM_FEATURE_EL3)) { 2377 return !(env->cp15.scr_el3 & SCR_NS); 2378 } else { 2379 /* If EL3 is not supported then the secure state is implementation 2380 * defined, in which case QEMU defaults to non-secure. 2381 */ 2382 return false; 2383 } 2384 } 2385 2386 /* Return true if the CPU is AArch64 EL3 or AArch32 Mon */ 2387 static inline bool arm_is_el3_or_mon(CPUARMState *env) 2388 { 2389 if (arm_feature(env, ARM_FEATURE_EL3)) { 2390 if (is_a64(env) && extract32(env->pstate, 2, 2) == 3) { 2391 /* CPU currently in AArch64 state and EL3 */ 2392 return true; 2393 } else if (!is_a64(env) && 2394 (env->uncached_cpsr & CPSR_M) == ARM_CPU_MODE_MON) { 2395 /* CPU currently in AArch32 state and monitor mode */ 2396 return true; 2397 } 2398 } 2399 return false; 2400 } 2401 2402 /* Return true if the processor is in secure state */ 2403 static inline bool arm_is_secure(CPUARMState *env) 2404 { 2405 if (arm_is_el3_or_mon(env)) { 2406 return true; 2407 } 2408 return arm_is_secure_below_el3(env); 2409 } 2410 2411 /* 2412 * Return true if the current security state has AArch64 EL2 or AArch32 Hyp. 2413 * This corresponds to the pseudocode EL2Enabled() 2414 */ 2415 static inline bool arm_is_el2_enabled_secstate(CPUARMState *env, bool secure) 2416 { 2417 return arm_feature(env, ARM_FEATURE_EL2) 2418 && (!secure || (env->cp15.scr_el3 & SCR_EEL2)); 2419 } 2420 2421 static inline bool arm_is_el2_enabled(CPUARMState *env) 2422 { 2423 return arm_is_el2_enabled_secstate(env, arm_is_secure_below_el3(env)); 2424 } 2425 2426 #else 2427 static inline bool arm_is_secure_below_el3(CPUARMState *env) 2428 { 2429 return false; 2430 } 2431 2432 static inline bool arm_is_secure(CPUARMState *env) 2433 { 2434 return false; 2435 } 2436 2437 static inline bool arm_is_el2_enabled_secstate(CPUARMState *env, bool secure) 2438 { 2439 return false; 2440 } 2441 2442 static inline bool arm_is_el2_enabled(CPUARMState *env) 2443 { 2444 return false; 2445 } 2446 #endif 2447 2448 /** 2449 * arm_hcr_el2_eff(): Return the effective value of HCR_EL2. 2450 * E.g. when in secure state, fields in HCR_EL2 are suppressed, 2451 * "for all purposes other than a direct read or write access of HCR_EL2." 2452 * Not included here is HCR_RW. 2453 */ 2454 uint64_t arm_hcr_el2_eff_secstate(CPUARMState *env, bool secure); 2455 uint64_t arm_hcr_el2_eff(CPUARMState *env); 2456 uint64_t arm_hcrx_el2_eff(CPUARMState *env); 2457 2458 /* Return true if the specified exception level is running in AArch64 state. */ 2459 static inline bool arm_el_is_aa64(CPUARMState *env, int el) 2460 { 2461 /* This isn't valid for EL0 (if we're in EL0, is_a64() is what you want, 2462 * and if we're not in EL0 then the state of EL0 isn't well defined.) 2463 */ 2464 assert(el >= 1 && el <= 3); 2465 bool aa64 = arm_feature(env, ARM_FEATURE_AARCH64); 2466 2467 /* The highest exception level is always at the maximum supported 2468 * register width, and then lower levels have a register width controlled 2469 * by bits in the SCR or HCR registers. 2470 */ 2471 if (el == 3) { 2472 return aa64; 2473 } 2474 2475 if (arm_feature(env, ARM_FEATURE_EL3) && 2476 ((env->cp15.scr_el3 & SCR_NS) || !(env->cp15.scr_el3 & SCR_EEL2))) { 2477 aa64 = aa64 && (env->cp15.scr_el3 & SCR_RW); 2478 } 2479 2480 if (el == 2) { 2481 return aa64; 2482 } 2483 2484 if (arm_is_el2_enabled(env)) { 2485 aa64 = aa64 && (env->cp15.hcr_el2 & HCR_RW); 2486 } 2487 2488 return aa64; 2489 } 2490 2491 /* Function for determing whether guest cp register reads and writes should 2492 * access the secure or non-secure bank of a cp register. When EL3 is 2493 * operating in AArch32 state, the NS-bit determines whether the secure 2494 * instance of a cp register should be used. When EL3 is AArch64 (or if 2495 * it doesn't exist at all) then there is no register banking, and all 2496 * accesses are to the non-secure version. 2497 */ 2498 static inline bool access_secure_reg(CPUARMState *env) 2499 { 2500 bool ret = (arm_feature(env, ARM_FEATURE_EL3) && 2501 !arm_el_is_aa64(env, 3) && 2502 !(env->cp15.scr_el3 & SCR_NS)); 2503 2504 return ret; 2505 } 2506 2507 /* Macros for accessing a specified CP register bank */ 2508 #define A32_BANKED_REG_GET(_env, _regname, _secure) \ 2509 ((_secure) ? (_env)->cp15._regname##_s : (_env)->cp15._regname##_ns) 2510 2511 #define A32_BANKED_REG_SET(_env, _regname, _secure, _val) \ 2512 do { \ 2513 if (_secure) { \ 2514 (_env)->cp15._regname##_s = (_val); \ 2515 } else { \ 2516 (_env)->cp15._regname##_ns = (_val); \ 2517 } \ 2518 } while (0) 2519 2520 /* Macros for automatically accessing a specific CP register bank depending on 2521 * the current secure state of the system. These macros are not intended for 2522 * supporting instruction translation reads/writes as these are dependent 2523 * solely on the SCR.NS bit and not the mode. 2524 */ 2525 #define A32_BANKED_CURRENT_REG_GET(_env, _regname) \ 2526 A32_BANKED_REG_GET((_env), _regname, \ 2527 (arm_is_secure(_env) && !arm_el_is_aa64((_env), 3))) 2528 2529 #define A32_BANKED_CURRENT_REG_SET(_env, _regname, _val) \ 2530 A32_BANKED_REG_SET((_env), _regname, \ 2531 (arm_is_secure(_env) && !arm_el_is_aa64((_env), 3)), \ 2532 (_val)) 2533 2534 void arm_cpu_list(void); 2535 uint32_t arm_phys_excp_target_el(CPUState *cs, uint32_t excp_idx, 2536 uint32_t cur_el, bool secure); 2537 2538 /* Interface between CPU and Interrupt controller. */ 2539 #ifndef CONFIG_USER_ONLY 2540 bool armv7m_nvic_can_take_pending_exception(void *opaque); 2541 #else 2542 static inline bool armv7m_nvic_can_take_pending_exception(void *opaque) 2543 { 2544 return true; 2545 } 2546 #endif 2547 /** 2548 * armv7m_nvic_set_pending: mark the specified exception as pending 2549 * @opaque: the NVIC 2550 * @irq: the exception number to mark pending 2551 * @secure: false for non-banked exceptions or for the nonsecure 2552 * version of a banked exception, true for the secure version of a banked 2553 * exception. 2554 * 2555 * Marks the specified exception as pending. Note that we will assert() 2556 * if @secure is true and @irq does not specify one of the fixed set 2557 * of architecturally banked exceptions. 2558 */ 2559 void armv7m_nvic_set_pending(void *opaque, int irq, bool secure); 2560 /** 2561 * armv7m_nvic_set_pending_derived: mark this derived exception as pending 2562 * @opaque: the NVIC 2563 * @irq: the exception number to mark pending 2564 * @secure: false for non-banked exceptions or for the nonsecure 2565 * version of a banked exception, true for the secure version of a banked 2566 * exception. 2567 * 2568 * Similar to armv7m_nvic_set_pending(), but specifically for derived 2569 * exceptions (exceptions generated in the course of trying to take 2570 * a different exception). 2571 */ 2572 void armv7m_nvic_set_pending_derived(void *opaque, int irq, bool secure); 2573 /** 2574 * armv7m_nvic_set_pending_lazyfp: mark this lazy FP exception as pending 2575 * @opaque: the NVIC 2576 * @irq: the exception number to mark pending 2577 * @secure: false for non-banked exceptions or for the nonsecure 2578 * version of a banked exception, true for the secure version of a banked 2579 * exception. 2580 * 2581 * Similar to armv7m_nvic_set_pending(), but specifically for exceptions 2582 * generated in the course of lazy stacking of FP registers. 2583 */ 2584 void armv7m_nvic_set_pending_lazyfp(void *opaque, int irq, bool secure); 2585 /** 2586 * armv7m_nvic_get_pending_irq_info: return highest priority pending 2587 * exception, and whether it targets Secure state 2588 * @opaque: the NVIC 2589 * @pirq: set to pending exception number 2590 * @ptargets_secure: set to whether pending exception targets Secure 2591 * 2592 * This function writes the number of the highest priority pending 2593 * exception (the one which would be made active by 2594 * armv7m_nvic_acknowledge_irq()) to @pirq, and sets @ptargets_secure 2595 * to true if the current highest priority pending exception should 2596 * be taken to Secure state, false for NS. 2597 */ 2598 void armv7m_nvic_get_pending_irq_info(void *opaque, int *pirq, 2599 bool *ptargets_secure); 2600 /** 2601 * armv7m_nvic_acknowledge_irq: make highest priority pending exception active 2602 * @opaque: the NVIC 2603 * 2604 * Move the current highest priority pending exception from the pending 2605 * state to the active state, and update v7m.exception to indicate that 2606 * it is the exception currently being handled. 2607 */ 2608 void armv7m_nvic_acknowledge_irq(void *opaque); 2609 /** 2610 * armv7m_nvic_complete_irq: complete specified interrupt or exception 2611 * @opaque: the NVIC 2612 * @irq: the exception number to complete 2613 * @secure: true if this exception was secure 2614 * 2615 * Returns: -1 if the irq was not active 2616 * 1 if completing this irq brought us back to base (no active irqs) 2617 * 0 if there is still an irq active after this one was completed 2618 * (Ignoring -1, this is the same as the RETTOBASE value before completion.) 2619 */ 2620 int armv7m_nvic_complete_irq(void *opaque, int irq, bool secure); 2621 /** 2622 * armv7m_nvic_get_ready_status(void *opaque, int irq, bool secure) 2623 * @opaque: the NVIC 2624 * @irq: the exception number to mark pending 2625 * @secure: false for non-banked exceptions or for the nonsecure 2626 * version of a banked exception, true for the secure version of a banked 2627 * exception. 2628 * 2629 * Return whether an exception is "ready", i.e. whether the exception is 2630 * enabled and is configured at a priority which would allow it to 2631 * interrupt the current execution priority. This controls whether the 2632 * RDY bit for it in the FPCCR is set. 2633 */ 2634 bool armv7m_nvic_get_ready_status(void *opaque, int irq, bool secure); 2635 /** 2636 * armv7m_nvic_raw_execution_priority: return the raw execution priority 2637 * @opaque: the NVIC 2638 * 2639 * Returns: the raw execution priority as defined by the v8M architecture. 2640 * This is the execution priority minus the effects of AIRCR.PRIS, 2641 * and minus any PRIMASK/FAULTMASK/BASEPRI priority boosting. 2642 * (v8M ARM ARM I_PKLD.) 2643 */ 2644 int armv7m_nvic_raw_execution_priority(void *opaque); 2645 /** 2646 * armv7m_nvic_neg_prio_requested: return true if the requested execution 2647 * priority is negative for the specified security state. 2648 * @opaque: the NVIC 2649 * @secure: the security state to test 2650 * This corresponds to the pseudocode IsReqExecPriNeg(). 2651 */ 2652 #ifndef CONFIG_USER_ONLY 2653 bool armv7m_nvic_neg_prio_requested(void *opaque, bool secure); 2654 #else 2655 static inline bool armv7m_nvic_neg_prio_requested(void *opaque, bool secure) 2656 { 2657 return false; 2658 } 2659 #endif 2660 2661 /* Interface for defining coprocessor registers. 2662 * Registers are defined in tables of arm_cp_reginfo structs 2663 * which are passed to define_arm_cp_regs(). 2664 */ 2665 2666 /* When looking up a coprocessor register we look for it 2667 * via an integer which encodes all of: 2668 * coprocessor number 2669 * Crn, Crm, opc1, opc2 fields 2670 * 32 or 64 bit register (ie is it accessed via MRC/MCR 2671 * or via MRRC/MCRR?) 2672 * non-secure/secure bank (AArch32 only) 2673 * We allow 4 bits for opc1 because MRRC/MCRR have a 4 bit field. 2674 * (In this case crn and opc2 should be zero.) 2675 * For AArch64, there is no 32/64 bit size distinction; 2676 * instead all registers have a 2 bit op0, 3 bit op1 and op2, 2677 * and 4 bit CRn and CRm. The encoding patterns are chosen 2678 * to be easy to convert to and from the KVM encodings, and also 2679 * so that the hashtable can contain both AArch32 and AArch64 2680 * registers (to allow for interprocessing where we might run 2681 * 32 bit code on a 64 bit core). 2682 */ 2683 /* This bit is private to our hashtable cpreg; in KVM register 2684 * IDs the AArch64/32 distinction is the KVM_REG_ARM/ARM64 2685 * in the upper bits of the 64 bit ID. 2686 */ 2687 #define CP_REG_AA64_SHIFT 28 2688 #define CP_REG_AA64_MASK (1 << CP_REG_AA64_SHIFT) 2689 2690 /* To enable banking of coprocessor registers depending on ns-bit we 2691 * add a bit to distinguish between secure and non-secure cpregs in the 2692 * hashtable. 2693 */ 2694 #define CP_REG_NS_SHIFT 29 2695 #define CP_REG_NS_MASK (1 << CP_REG_NS_SHIFT) 2696 2697 #define ENCODE_CP_REG(cp, is64, ns, crn, crm, opc1, opc2) \ 2698 ((ns) << CP_REG_NS_SHIFT | ((cp) << 16) | ((is64) << 15) | \ 2699 ((crn) << 11) | ((crm) << 7) | ((opc1) << 3) | (opc2)) 2700 2701 #define ENCODE_AA64_CP_REG(cp, crn, crm, op0, op1, op2) \ 2702 (CP_REG_AA64_MASK | \ 2703 ((cp) << CP_REG_ARM_COPROC_SHIFT) | \ 2704 ((op0) << CP_REG_ARM64_SYSREG_OP0_SHIFT) | \ 2705 ((op1) << CP_REG_ARM64_SYSREG_OP1_SHIFT) | \ 2706 ((crn) << CP_REG_ARM64_SYSREG_CRN_SHIFT) | \ 2707 ((crm) << CP_REG_ARM64_SYSREG_CRM_SHIFT) | \ 2708 ((op2) << CP_REG_ARM64_SYSREG_OP2_SHIFT)) 2709 2710 /* Convert a full 64 bit KVM register ID to the truncated 32 bit 2711 * version used as a key for the coprocessor register hashtable 2712 */ 2713 static inline uint32_t kvm_to_cpreg_id(uint64_t kvmid) 2714 { 2715 uint32_t cpregid = kvmid; 2716 if ((kvmid & CP_REG_ARCH_MASK) == CP_REG_ARM64) { 2717 cpregid |= CP_REG_AA64_MASK; 2718 } else { 2719 if ((kvmid & CP_REG_SIZE_MASK) == CP_REG_SIZE_U64) { 2720 cpregid |= (1 << 15); 2721 } 2722 2723 /* KVM is always non-secure so add the NS flag on AArch32 register 2724 * entries. 2725 */ 2726 cpregid |= 1 << CP_REG_NS_SHIFT; 2727 } 2728 return cpregid; 2729 } 2730 2731 /* Convert a truncated 32 bit hashtable key into the full 2732 * 64 bit KVM register ID. 2733 */ 2734 static inline uint64_t cpreg_to_kvm_id(uint32_t cpregid) 2735 { 2736 uint64_t kvmid; 2737 2738 if (cpregid & CP_REG_AA64_MASK) { 2739 kvmid = cpregid & ~CP_REG_AA64_MASK; 2740 kvmid |= CP_REG_SIZE_U64 | CP_REG_ARM64; 2741 } else { 2742 kvmid = cpregid & ~(1 << 15); 2743 if (cpregid & (1 << 15)) { 2744 kvmid |= CP_REG_SIZE_U64 | CP_REG_ARM; 2745 } else { 2746 kvmid |= CP_REG_SIZE_U32 | CP_REG_ARM; 2747 } 2748 } 2749 return kvmid; 2750 } 2751 2752 /* Return the highest implemented Exception Level */ 2753 static inline int arm_highest_el(CPUARMState *env) 2754 { 2755 if (arm_feature(env, ARM_FEATURE_EL3)) { 2756 return 3; 2757 } 2758 if (arm_feature(env, ARM_FEATURE_EL2)) { 2759 return 2; 2760 } 2761 return 1; 2762 } 2763 2764 /* Return true if a v7M CPU is in Handler mode */ 2765 static inline bool arm_v7m_is_handler_mode(CPUARMState *env) 2766 { 2767 return env->v7m.exception != 0; 2768 } 2769 2770 /* Return the current Exception Level (as per ARMv8; note that this differs 2771 * from the ARMv7 Privilege Level). 2772 */ 2773 static inline int arm_current_el(CPUARMState *env) 2774 { 2775 if (arm_feature(env, ARM_FEATURE_M)) { 2776 return arm_v7m_is_handler_mode(env) || 2777 !(env->v7m.control[env->v7m.secure] & 1); 2778 } 2779 2780 if (is_a64(env)) { 2781 return extract32(env->pstate, 2, 2); 2782 } 2783 2784 switch (env->uncached_cpsr & 0x1f) { 2785 case ARM_CPU_MODE_USR: 2786 return 0; 2787 case ARM_CPU_MODE_HYP: 2788 return 2; 2789 case ARM_CPU_MODE_MON: 2790 return 3; 2791 default: 2792 if (arm_is_secure(env) && !arm_el_is_aa64(env, 3)) { 2793 /* If EL3 is 32-bit then all secure privileged modes run in 2794 * EL3 2795 */ 2796 return 3; 2797 } 2798 2799 return 1; 2800 } 2801 } 2802 2803 /** 2804 * write_list_to_cpustate 2805 * @cpu: ARMCPU 2806 * 2807 * For each register listed in the ARMCPU cpreg_indexes list, write 2808 * its value from the cpreg_values list into the ARMCPUState structure. 2809 * This updates TCG's working data structures from KVM data or 2810 * from incoming migration state. 2811 * 2812 * Returns: true if all register values were updated correctly, 2813 * false if some register was unknown or could not be written. 2814 * Note that we do not stop early on failure -- we will attempt 2815 * writing all registers in the list. 2816 */ 2817 bool write_list_to_cpustate(ARMCPU *cpu); 2818 2819 /** 2820 * write_cpustate_to_list: 2821 * @cpu: ARMCPU 2822 * @kvm_sync: true if this is for syncing back to KVM 2823 * 2824 * For each register listed in the ARMCPU cpreg_indexes list, write 2825 * its value from the ARMCPUState structure into the cpreg_values list. 2826 * This is used to copy info from TCG's working data structures into 2827 * KVM or for outbound migration. 2828 * 2829 * @kvm_sync is true if we are doing this in order to sync the 2830 * register state back to KVM. In this case we will only update 2831 * values in the list if the previous list->cpustate sync actually 2832 * successfully wrote the CPU state. Otherwise we will keep the value 2833 * that is in the list. 2834 * 2835 * Returns: true if all register values were read correctly, 2836 * false if some register was unknown or could not be read. 2837 * Note that we do not stop early on failure -- we will attempt 2838 * reading all registers in the list. 2839 */ 2840 bool write_cpustate_to_list(ARMCPU *cpu, bool kvm_sync); 2841 2842 #define ARM_CPUID_TI915T 0x54029152 2843 #define ARM_CPUID_TI925T 0x54029252 2844 2845 #define ARM_CPU_TYPE_SUFFIX "-" TYPE_ARM_CPU 2846 #define ARM_CPU_TYPE_NAME(name) (name ARM_CPU_TYPE_SUFFIX) 2847 #define CPU_RESOLVING_TYPE TYPE_ARM_CPU 2848 2849 #define TYPE_ARM_HOST_CPU "host-" TYPE_ARM_CPU 2850 2851 #define cpu_list arm_cpu_list 2852 2853 /* ARM has the following "translation regimes" (as the ARM ARM calls them): 2854 * 2855 * If EL3 is 64-bit: 2856 * + NonSecure EL1 & 0 stage 1 2857 * + NonSecure EL1 & 0 stage 2 2858 * + NonSecure EL2 2859 * + NonSecure EL2 & 0 (ARMv8.1-VHE) 2860 * + Secure EL1 & 0 2861 * + Secure EL3 2862 * If EL3 is 32-bit: 2863 * + NonSecure PL1 & 0 stage 1 2864 * + NonSecure PL1 & 0 stage 2 2865 * + NonSecure PL2 2866 * + Secure PL0 2867 * + Secure PL1 2868 * (reminder: for 32 bit EL3, Secure PL1 is *EL3*, not EL1.) 2869 * 2870 * For QEMU, an mmu_idx is not quite the same as a translation regime because: 2871 * 1. we need to split the "EL1 & 0" and "EL2 & 0" regimes into two mmu_idxes, 2872 * because they may differ in access permissions even if the VA->PA map is 2873 * the same 2874 * 2. we want to cache in our TLB the full VA->IPA->PA lookup for a stage 1+2 2875 * translation, which means that we have one mmu_idx that deals with two 2876 * concatenated translation regimes [this sort of combined s1+2 TLB is 2877 * architecturally permitted] 2878 * 3. we don't need to allocate an mmu_idx to translations that we won't be 2879 * handling via the TLB. The only way to do a stage 1 translation without 2880 * the immediate stage 2 translation is via the ATS or AT system insns, 2881 * which can be slow-pathed and always do a page table walk. 2882 * The only use of stage 2 translations is either as part of an s1+2 2883 * lookup or when loading the descriptors during a stage 1 page table walk, 2884 * and in both those cases we don't use the TLB. 2885 * 4. we can also safely fold together the "32 bit EL3" and "64 bit EL3" 2886 * translation regimes, because they map reasonably well to each other 2887 * and they can't both be active at the same time. 2888 * 5. we want to be able to use the TLB for accesses done as part of a 2889 * stage1 page table walk, rather than having to walk the stage2 page 2890 * table over and over. 2891 * 6. we need separate EL1/EL2 mmu_idx for handling the Privileged Access 2892 * Never (PAN) bit within PSTATE. 2893 * 7. we fold together the secure and non-secure regimes for A-profile, 2894 * because there are no banked system registers for aarch64, so the 2895 * process of switching between secure and non-secure is 2896 * already heavyweight. 2897 * 2898 * This gives us the following list of cases: 2899 * 2900 * EL0 EL1&0 stage 1+2 (aka NS PL0) 2901 * EL1 EL1&0 stage 1+2 (aka NS PL1) 2902 * EL1 EL1&0 stage 1+2 +PAN 2903 * EL0 EL2&0 2904 * EL2 EL2&0 2905 * EL2 EL2&0 +PAN 2906 * EL2 (aka NS PL2) 2907 * EL3 (aka S PL1) 2908 * 2909 * for a total of 8 different mmu_idx. 2910 * 2911 * R profile CPUs have an MPU, but can use the same set of MMU indexes 2912 * as A profile. They only need to distinguish EL0 and EL1 (and 2913 * EL2 if we ever model a Cortex-R52). 2914 * 2915 * M profile CPUs are rather different as they do not have a true MMU. 2916 * They have the following different MMU indexes: 2917 * User 2918 * Privileged 2919 * User, execution priority negative (ie the MPU HFNMIENA bit may apply) 2920 * Privileged, execution priority negative (ditto) 2921 * If the CPU supports the v8M Security Extension then there are also: 2922 * Secure User 2923 * Secure Privileged 2924 * Secure User, execution priority negative 2925 * Secure Privileged, execution priority negative 2926 * 2927 * The ARMMMUIdx and the mmu index value used by the core QEMU TLB code 2928 * are not quite the same -- different CPU types (most notably M profile 2929 * vs A/R profile) would like to use MMU indexes with different semantics, 2930 * but since we don't ever need to use all of those in a single CPU we 2931 * can avoid having to set NB_MMU_MODES to "total number of A profile MMU 2932 * modes + total number of M profile MMU modes". The lower bits of 2933 * ARMMMUIdx are the core TLB mmu index, and the higher bits are always 2934 * the same for any particular CPU. 2935 * Variables of type ARMMUIdx are always full values, and the core 2936 * index values are in variables of type 'int'. 2937 * 2938 * Our enumeration includes at the end some entries which are not "true" 2939 * mmu_idx values in that they don't have corresponding TLBs and are only 2940 * valid for doing slow path page table walks. 2941 * 2942 * The constant names here are patterned after the general style of the names 2943 * of the AT/ATS operations. 2944 * The values used are carefully arranged to make mmu_idx => EL lookup easy. 2945 * For M profile we arrange them to have a bit for priv, a bit for negpri 2946 * and a bit for secure. 2947 */ 2948 #define ARM_MMU_IDX_A 0x10 /* A profile */ 2949 #define ARM_MMU_IDX_NOTLB 0x20 /* does not have a TLB */ 2950 #define ARM_MMU_IDX_M 0x40 /* M profile */ 2951 2952 /* Meanings of the bits for M profile mmu idx values */ 2953 #define ARM_MMU_IDX_M_PRIV 0x1 2954 #define ARM_MMU_IDX_M_NEGPRI 0x2 2955 #define ARM_MMU_IDX_M_S 0x4 /* Secure */ 2956 2957 #define ARM_MMU_IDX_TYPE_MASK \ 2958 (ARM_MMU_IDX_A | ARM_MMU_IDX_M | ARM_MMU_IDX_NOTLB) 2959 #define ARM_MMU_IDX_COREIDX_MASK 0xf 2960 2961 typedef enum ARMMMUIdx { 2962 /* 2963 * A-profile. 2964 */ 2965 ARMMMUIdx_E10_0 = 0 | ARM_MMU_IDX_A, 2966 ARMMMUIdx_E20_0 = 1 | ARM_MMU_IDX_A, 2967 ARMMMUIdx_E10_1 = 2 | ARM_MMU_IDX_A, 2968 ARMMMUIdx_E20_2 = 3 | ARM_MMU_IDX_A, 2969 ARMMMUIdx_E10_1_PAN = 4 | ARM_MMU_IDX_A, 2970 ARMMMUIdx_E20_2_PAN = 5 | ARM_MMU_IDX_A, 2971 ARMMMUIdx_E2 = 6 | ARM_MMU_IDX_A, 2972 ARMMMUIdx_E3 = 7 | ARM_MMU_IDX_A, 2973 2974 /* 2975 * These are not allocated TLBs and are used only for AT system 2976 * instructions or for the first stage of an S12 page table walk. 2977 */ 2978 ARMMMUIdx_Stage1_E0 = 0 | ARM_MMU_IDX_NOTLB, 2979 ARMMMUIdx_Stage1_E1 = 1 | ARM_MMU_IDX_NOTLB, 2980 ARMMMUIdx_Stage1_E1_PAN = 2 | ARM_MMU_IDX_NOTLB, 2981 /* 2982 * Not allocated a TLB: used only for second stage of an S12 page 2983 * table walk, or for descriptor loads during first stage of an S1 2984 * page table walk. Note that if we ever want to have a TLB for this 2985 * then various TLB flush insns which currently are no-ops or flush 2986 * only stage 1 MMU indexes will need to change to flush stage 2. 2987 */ 2988 ARMMMUIdx_Stage2 = 3 | ARM_MMU_IDX_NOTLB, 2989 ARMMMUIdx_Stage2_S = 4 | ARM_MMU_IDX_NOTLB, 2990 2991 /* 2992 * M-profile. 2993 */ 2994 ARMMMUIdx_MUser = ARM_MMU_IDX_M, 2995 ARMMMUIdx_MPriv = ARM_MMU_IDX_M | ARM_MMU_IDX_M_PRIV, 2996 ARMMMUIdx_MUserNegPri = ARMMMUIdx_MUser | ARM_MMU_IDX_M_NEGPRI, 2997 ARMMMUIdx_MPrivNegPri = ARMMMUIdx_MPriv | ARM_MMU_IDX_M_NEGPRI, 2998 ARMMMUIdx_MSUser = ARMMMUIdx_MUser | ARM_MMU_IDX_M_S, 2999 ARMMMUIdx_MSPriv = ARMMMUIdx_MPriv | ARM_MMU_IDX_M_S, 3000 ARMMMUIdx_MSUserNegPri = ARMMMUIdx_MUserNegPri | ARM_MMU_IDX_M_S, 3001 ARMMMUIdx_MSPrivNegPri = ARMMMUIdx_MPrivNegPri | ARM_MMU_IDX_M_S, 3002 } ARMMMUIdx; 3003 3004 /* 3005 * Bit macros for the core-mmu-index values for each index, 3006 * for use when calling tlb_flush_by_mmuidx() and friends. 3007 */ 3008 #define TO_CORE_BIT(NAME) \ 3009 ARMMMUIdxBit_##NAME = 1 << (ARMMMUIdx_##NAME & ARM_MMU_IDX_COREIDX_MASK) 3010 3011 typedef enum ARMMMUIdxBit { 3012 TO_CORE_BIT(E10_0), 3013 TO_CORE_BIT(E20_0), 3014 TO_CORE_BIT(E10_1), 3015 TO_CORE_BIT(E10_1_PAN), 3016 TO_CORE_BIT(E2), 3017 TO_CORE_BIT(E20_2), 3018 TO_CORE_BIT(E20_2_PAN), 3019 TO_CORE_BIT(E3), 3020 3021 TO_CORE_BIT(MUser), 3022 TO_CORE_BIT(MPriv), 3023 TO_CORE_BIT(MUserNegPri), 3024 TO_CORE_BIT(MPrivNegPri), 3025 TO_CORE_BIT(MSUser), 3026 TO_CORE_BIT(MSPriv), 3027 TO_CORE_BIT(MSUserNegPri), 3028 TO_CORE_BIT(MSPrivNegPri), 3029 } ARMMMUIdxBit; 3030 3031 #undef TO_CORE_BIT 3032 3033 #define MMU_USER_IDX 0 3034 3035 /* Indexes used when registering address spaces with cpu_address_space_init */ 3036 typedef enum ARMASIdx { 3037 ARMASIdx_NS = 0, 3038 ARMASIdx_S = 1, 3039 ARMASIdx_TagNS = 2, 3040 ARMASIdx_TagS = 3, 3041 } ARMASIdx; 3042 3043 static inline bool arm_v7m_csselr_razwi(ARMCPU *cpu) 3044 { 3045 /* If all the CLIDR.Ctypem bits are 0 there are no caches, and 3046 * CSSELR is RAZ/WI. 3047 */ 3048 return (cpu->clidr & R_V7M_CLIDR_CTYPE_ALL_MASK) != 0; 3049 } 3050 3051 static inline bool arm_sctlr_b(CPUARMState *env) 3052 { 3053 return 3054 /* We need not implement SCTLR.ITD in user-mode emulation, so 3055 * let linux-user ignore the fact that it conflicts with SCTLR_B. 3056 * This lets people run BE32 binaries with "-cpu any". 3057 */ 3058 #ifndef CONFIG_USER_ONLY 3059 !arm_feature(env, ARM_FEATURE_V7) && 3060 #endif 3061 (env->cp15.sctlr_el[1] & SCTLR_B) != 0; 3062 } 3063 3064 uint64_t arm_sctlr(CPUARMState *env, int el); 3065 3066 static inline bool arm_cpu_data_is_big_endian_a32(CPUARMState *env, 3067 bool sctlr_b) 3068 { 3069 #ifdef CONFIG_USER_ONLY 3070 /* 3071 * In system mode, BE32 is modelled in line with the 3072 * architecture (as word-invariant big-endianness), where loads 3073 * and stores are done little endian but from addresses which 3074 * are adjusted by XORing with the appropriate constant. So the 3075 * endianness to use for the raw data access is not affected by 3076 * SCTLR.B. 3077 * In user mode, however, we model BE32 as byte-invariant 3078 * big-endianness (because user-only code cannot tell the 3079 * difference), and so we need to use a data access endianness 3080 * that depends on SCTLR.B. 3081 */ 3082 if (sctlr_b) { 3083 return true; 3084 } 3085 #endif 3086 /* In 32bit endianness is determined by looking at CPSR's E bit */ 3087 return env->uncached_cpsr & CPSR_E; 3088 } 3089 3090 static inline bool arm_cpu_data_is_big_endian_a64(int el, uint64_t sctlr) 3091 { 3092 return sctlr & (el ? SCTLR_EE : SCTLR_E0E); 3093 } 3094 3095 /* Return true if the processor is in big-endian mode. */ 3096 static inline bool arm_cpu_data_is_big_endian(CPUARMState *env) 3097 { 3098 if (!is_a64(env)) { 3099 return arm_cpu_data_is_big_endian_a32(env, arm_sctlr_b(env)); 3100 } else { 3101 int cur_el = arm_current_el(env); 3102 uint64_t sctlr = arm_sctlr(env, cur_el); 3103 return arm_cpu_data_is_big_endian_a64(cur_el, sctlr); 3104 } 3105 } 3106 3107 #include "exec/cpu-all.h" 3108 3109 /* 3110 * We have more than 32-bits worth of state per TB, so we split the data 3111 * between tb->flags and tb->cs_base, which is otherwise unused for ARM. 3112 * We collect these two parts in CPUARMTBFlags where they are named 3113 * flags and flags2 respectively. 3114 * 3115 * The flags that are shared between all execution modes, TBFLAG_ANY, 3116 * are stored in flags. The flags that are specific to a given mode 3117 * are stores in flags2. Since cs_base is sized on the configured 3118 * address size, flags2 always has 64-bits for A64, and a minimum of 3119 * 32-bits for A32 and M32. 3120 * 3121 * The bits for 32-bit A-profile and M-profile partially overlap: 3122 * 3123 * 31 23 11 10 0 3124 * +-------------+----------+----------------+ 3125 * | | | TBFLAG_A32 | 3126 * | TBFLAG_AM32 | +-----+----------+ 3127 * | | |TBFLAG_M32| 3128 * +-------------+----------------+----------+ 3129 * 31 23 6 5 0 3130 * 3131 * Unless otherwise noted, these bits are cached in env->hflags. 3132 */ 3133 FIELD(TBFLAG_ANY, AARCH64_STATE, 0, 1) 3134 FIELD(TBFLAG_ANY, SS_ACTIVE, 1, 1) 3135 FIELD(TBFLAG_ANY, PSTATE__SS, 2, 1) /* Not cached. */ 3136 FIELD(TBFLAG_ANY, BE_DATA, 3, 1) 3137 FIELD(TBFLAG_ANY, MMUIDX, 4, 4) 3138 /* Target EL if we take a floating-point-disabled exception */ 3139 FIELD(TBFLAG_ANY, FPEXC_EL, 8, 2) 3140 /* Memory operations require alignment: SCTLR_ELx.A or CCR.UNALIGN_TRP */ 3141 FIELD(TBFLAG_ANY, ALIGN_MEM, 10, 1) 3142 FIELD(TBFLAG_ANY, PSTATE__IL, 11, 1) 3143 3144 /* 3145 * Bit usage when in AArch32 state, both A- and M-profile. 3146 */ 3147 FIELD(TBFLAG_AM32, CONDEXEC, 24, 8) /* Not cached. */ 3148 FIELD(TBFLAG_AM32, THUMB, 23, 1) /* Not cached. */ 3149 3150 /* 3151 * Bit usage when in AArch32 state, for A-profile only. 3152 */ 3153 FIELD(TBFLAG_A32, VECLEN, 0, 3) /* Not cached. */ 3154 FIELD(TBFLAG_A32, VECSTRIDE, 3, 2) /* Not cached. */ 3155 /* 3156 * We store the bottom two bits of the CPAR as TB flags and handle 3157 * checks on the other bits at runtime. This shares the same bits as 3158 * VECSTRIDE, which is OK as no XScale CPU has VFP. 3159 * Not cached, because VECLEN+VECSTRIDE are not cached. 3160 */ 3161 FIELD(TBFLAG_A32, XSCALE_CPAR, 5, 2) 3162 FIELD(TBFLAG_A32, VFPEN, 7, 1) /* Partially cached, minus FPEXC. */ 3163 FIELD(TBFLAG_A32, SCTLR__B, 8, 1) /* Cannot overlap with SCTLR_B */ 3164 FIELD(TBFLAG_A32, HSTR_ACTIVE, 9, 1) 3165 /* 3166 * Indicates whether cp register reads and writes by guest code should access 3167 * the secure or nonsecure bank of banked registers; note that this is not 3168 * the same thing as the current security state of the processor! 3169 */ 3170 FIELD(TBFLAG_A32, NS, 10, 1) 3171 /* 3172 * Indicates that SME Streaming mode is active, and SMCR_ELx.FA64 is not. 3173 * This requires an SME trap from AArch32 mode when using NEON. 3174 */ 3175 FIELD(TBFLAG_A32, SME_TRAP_NONSTREAMING, 11, 1) 3176 3177 /* 3178 * Bit usage when in AArch32 state, for M-profile only. 3179 */ 3180 /* Handler (ie not Thread) mode */ 3181 FIELD(TBFLAG_M32, HANDLER, 0, 1) 3182 /* Whether we should generate stack-limit checks */ 3183 FIELD(TBFLAG_M32, STACKCHECK, 1, 1) 3184 /* Set if FPCCR.LSPACT is set */ 3185 FIELD(TBFLAG_M32, LSPACT, 2, 1) /* Not cached. */ 3186 /* Set if we must create a new FP context */ 3187 FIELD(TBFLAG_M32, NEW_FP_CTXT_NEEDED, 3, 1) /* Not cached. */ 3188 /* Set if FPCCR.S does not match current security state */ 3189 FIELD(TBFLAG_M32, FPCCR_S_WRONG, 4, 1) /* Not cached. */ 3190 /* Set if MVE insns are definitely not predicated by VPR or LTPSIZE */ 3191 FIELD(TBFLAG_M32, MVE_NO_PRED, 5, 1) /* Not cached. */ 3192 /* Set if in secure mode */ 3193 FIELD(TBFLAG_M32, SECURE, 6, 1) 3194 3195 /* 3196 * Bit usage when in AArch64 state 3197 */ 3198 FIELD(TBFLAG_A64, TBII, 0, 2) 3199 FIELD(TBFLAG_A64, SVEEXC_EL, 2, 2) 3200 /* The current vector length, either NVL or SVL. */ 3201 FIELD(TBFLAG_A64, VL, 4, 4) 3202 FIELD(TBFLAG_A64, PAUTH_ACTIVE, 8, 1) 3203 FIELD(TBFLAG_A64, BT, 9, 1) 3204 FIELD(TBFLAG_A64, BTYPE, 10, 2) /* Not cached. */ 3205 FIELD(TBFLAG_A64, TBID, 12, 2) 3206 FIELD(TBFLAG_A64, UNPRIV, 14, 1) 3207 FIELD(TBFLAG_A64, ATA, 15, 1) 3208 FIELD(TBFLAG_A64, TCMA, 16, 2) 3209 FIELD(TBFLAG_A64, MTE_ACTIVE, 18, 1) 3210 FIELD(TBFLAG_A64, MTE0_ACTIVE, 19, 1) 3211 FIELD(TBFLAG_A64, SMEEXC_EL, 20, 2) 3212 FIELD(TBFLAG_A64, PSTATE_SM, 22, 1) 3213 FIELD(TBFLAG_A64, PSTATE_ZA, 23, 1) 3214 FIELD(TBFLAG_A64, SVL, 24, 4) 3215 /* Indicates that SME Streaming mode is active, and SMCR_ELx.FA64 is not. */ 3216 FIELD(TBFLAG_A64, SME_TRAP_NONSTREAMING, 28, 1) 3217 3218 /* 3219 * Helpers for using the above. 3220 */ 3221 #define DP_TBFLAG_ANY(DST, WHICH, VAL) \ 3222 (DST.flags = FIELD_DP32(DST.flags, TBFLAG_ANY, WHICH, VAL)) 3223 #define DP_TBFLAG_A64(DST, WHICH, VAL) \ 3224 (DST.flags2 = FIELD_DP32(DST.flags2, TBFLAG_A64, WHICH, VAL)) 3225 #define DP_TBFLAG_A32(DST, WHICH, VAL) \ 3226 (DST.flags2 = FIELD_DP32(DST.flags2, TBFLAG_A32, WHICH, VAL)) 3227 #define DP_TBFLAG_M32(DST, WHICH, VAL) \ 3228 (DST.flags2 = FIELD_DP32(DST.flags2, TBFLAG_M32, WHICH, VAL)) 3229 #define DP_TBFLAG_AM32(DST, WHICH, VAL) \ 3230 (DST.flags2 = FIELD_DP32(DST.flags2, TBFLAG_AM32, WHICH, VAL)) 3231 3232 #define EX_TBFLAG_ANY(IN, WHICH) FIELD_EX32(IN.flags, TBFLAG_ANY, WHICH) 3233 #define EX_TBFLAG_A64(IN, WHICH) FIELD_EX32(IN.flags2, TBFLAG_A64, WHICH) 3234 #define EX_TBFLAG_A32(IN, WHICH) FIELD_EX32(IN.flags2, TBFLAG_A32, WHICH) 3235 #define EX_TBFLAG_M32(IN, WHICH) FIELD_EX32(IN.flags2, TBFLAG_M32, WHICH) 3236 #define EX_TBFLAG_AM32(IN, WHICH) FIELD_EX32(IN.flags2, TBFLAG_AM32, WHICH) 3237 3238 /** 3239 * cpu_mmu_index: 3240 * @env: The cpu environment 3241 * @ifetch: True for code access, false for data access. 3242 * 3243 * Return the core mmu index for the current translation regime. 3244 * This function is used by generic TCG code paths. 3245 */ 3246 static inline int cpu_mmu_index(CPUARMState *env, bool ifetch) 3247 { 3248 return EX_TBFLAG_ANY(env->hflags, MMUIDX); 3249 } 3250 3251 /** 3252 * sve_vq 3253 * @env: the cpu context 3254 * 3255 * Return the VL cached within env->hflags, in units of quadwords. 3256 */ 3257 static inline int sve_vq(CPUARMState *env) 3258 { 3259 return EX_TBFLAG_A64(env->hflags, VL) + 1; 3260 } 3261 3262 /** 3263 * sme_vq 3264 * @env: the cpu context 3265 * 3266 * Return the SVL cached within env->hflags, in units of quadwords. 3267 */ 3268 static inline int sme_vq(CPUARMState *env) 3269 { 3270 return EX_TBFLAG_A64(env->hflags, SVL) + 1; 3271 } 3272 3273 static inline bool bswap_code(bool sctlr_b) 3274 { 3275 #ifdef CONFIG_USER_ONLY 3276 /* BE8 (SCTLR.B = 0, TARGET_BIG_ENDIAN = 1) is mixed endian. 3277 * The invalid combination SCTLR.B=1/CPSR.E=1/TARGET_BIG_ENDIAN=0 3278 * would also end up as a mixed-endian mode with BE code, LE data. 3279 */ 3280 return 3281 #if TARGET_BIG_ENDIAN 3282 1 ^ 3283 #endif 3284 sctlr_b; 3285 #else 3286 /* All code access in ARM is little endian, and there are no loaders 3287 * doing swaps that need to be reversed 3288 */ 3289 return 0; 3290 #endif 3291 } 3292 3293 #ifdef CONFIG_USER_ONLY 3294 static inline bool arm_cpu_bswap_data(CPUARMState *env) 3295 { 3296 return 3297 #if TARGET_BIG_ENDIAN 3298 1 ^ 3299 #endif 3300 arm_cpu_data_is_big_endian(env); 3301 } 3302 #endif 3303 3304 void cpu_get_tb_cpu_state(CPUARMState *env, target_ulong *pc, 3305 target_ulong *cs_base, uint32_t *flags); 3306 3307 enum { 3308 QEMU_PSCI_CONDUIT_DISABLED = 0, 3309 QEMU_PSCI_CONDUIT_SMC = 1, 3310 QEMU_PSCI_CONDUIT_HVC = 2, 3311 }; 3312 3313 #ifndef CONFIG_USER_ONLY 3314 /* Return the address space index to use for a memory access */ 3315 static inline int arm_asidx_from_attrs(CPUState *cs, MemTxAttrs attrs) 3316 { 3317 return attrs.secure ? ARMASIdx_S : ARMASIdx_NS; 3318 } 3319 3320 /* Return the AddressSpace to use for a memory access 3321 * (which depends on whether the access is S or NS, and whether 3322 * the board gave us a separate AddressSpace for S accesses). 3323 */ 3324 static inline AddressSpace *arm_addressspace(CPUState *cs, MemTxAttrs attrs) 3325 { 3326 return cpu_get_address_space(cs, arm_asidx_from_attrs(cs, attrs)); 3327 } 3328 #endif 3329 3330 /** 3331 * arm_register_pre_el_change_hook: 3332 * Register a hook function which will be called immediately before this 3333 * CPU changes exception level or mode. The hook function will be 3334 * passed a pointer to the ARMCPU and the opaque data pointer passed 3335 * to this function when the hook was registered. 3336 * 3337 * Note that if a pre-change hook is called, any registered post-change hooks 3338 * are guaranteed to subsequently be called. 3339 */ 3340 void arm_register_pre_el_change_hook(ARMCPU *cpu, ARMELChangeHookFn *hook, 3341 void *opaque); 3342 /** 3343 * arm_register_el_change_hook: 3344 * Register a hook function which will be called immediately after this 3345 * CPU changes exception level or mode. The hook function will be 3346 * passed a pointer to the ARMCPU and the opaque data pointer passed 3347 * to this function when the hook was registered. 3348 * 3349 * Note that any registered hooks registered here are guaranteed to be called 3350 * if pre-change hooks have been. 3351 */ 3352 void arm_register_el_change_hook(ARMCPU *cpu, ARMELChangeHookFn *hook, void 3353 *opaque); 3354 3355 /** 3356 * arm_rebuild_hflags: 3357 * Rebuild the cached TBFLAGS for arbitrary changed processor state. 3358 */ 3359 void arm_rebuild_hflags(CPUARMState *env); 3360 3361 /** 3362 * aa32_vfp_dreg: 3363 * Return a pointer to the Dn register within env in 32-bit mode. 3364 */ 3365 static inline uint64_t *aa32_vfp_dreg(CPUARMState *env, unsigned regno) 3366 { 3367 return &env->vfp.zregs[regno >> 1].d[regno & 1]; 3368 } 3369 3370 /** 3371 * aa32_vfp_qreg: 3372 * Return a pointer to the Qn register within env in 32-bit mode. 3373 */ 3374 static inline uint64_t *aa32_vfp_qreg(CPUARMState *env, unsigned regno) 3375 { 3376 return &env->vfp.zregs[regno].d[0]; 3377 } 3378 3379 /** 3380 * aa64_vfp_qreg: 3381 * Return a pointer to the Qn register within env in 64-bit mode. 3382 */ 3383 static inline uint64_t *aa64_vfp_qreg(CPUARMState *env, unsigned regno) 3384 { 3385 return &env->vfp.zregs[regno].d[0]; 3386 } 3387 3388 /* Shared between translate-sve.c and sve_helper.c. */ 3389 extern const uint64_t pred_esz_masks[5]; 3390 3391 /* Helper for the macros below, validating the argument type. */ 3392 static inline MemTxAttrs *typecheck_memtxattrs(MemTxAttrs *x) 3393 { 3394 return x; 3395 } 3396 3397 /* 3398 * Lvalue macros for ARM TLB bits that we must cache in the TCG TLB. 3399 * Using these should be a bit more self-documenting than using the 3400 * generic target bits directly. 3401 */ 3402 #define arm_tlb_bti_gp(x) (typecheck_memtxattrs(x)->target_tlb_bit0) 3403 #define arm_tlb_mte_tagged(x) (typecheck_memtxattrs(x)->target_tlb_bit1) 3404 3405 /* 3406 * AArch64 usage of the PAGE_TARGET_* bits for linux-user. 3407 * Note that with the Linux kernel, PROT_MTE may not be cleared by mprotect 3408 * mprotect but PROT_BTI may be cleared. C.f. the kernel's VM_ARCH_CLEAR. 3409 */ 3410 #define PAGE_BTI PAGE_TARGET_1 3411 #define PAGE_MTE PAGE_TARGET_2 3412 #define PAGE_TARGET_STICKY PAGE_MTE 3413 3414 #ifdef TARGET_TAGGED_ADDRESSES 3415 /** 3416 * cpu_untagged_addr: 3417 * @cs: CPU context 3418 * @x: tagged address 3419 * 3420 * Remove any address tag from @x. This is explicitly related to the 3421 * linux syscall TIF_TAGGED_ADDR setting, not TBI in general. 3422 * 3423 * There should be a better place to put this, but we need this in 3424 * include/exec/cpu_ldst.h, and not some place linux-user specific. 3425 */ 3426 static inline target_ulong cpu_untagged_addr(CPUState *cs, target_ulong x) 3427 { 3428 ARMCPU *cpu = ARM_CPU(cs); 3429 if (cpu->env.tagged_addr_enable) { 3430 /* 3431 * TBI is enabled for userspace but not kernelspace addresses. 3432 * Only clear the tag if bit 55 is clear. 3433 */ 3434 x &= sextract64(x, 0, 56); 3435 } 3436 return x; 3437 } 3438 #endif 3439 3440 /* 3441 * Naming convention for isar_feature functions: 3442 * Functions which test 32-bit ID registers should have _aa32_ in 3443 * their name. Functions which test 64-bit ID registers should have 3444 * _aa64_ in their name. These must only be used in code where we 3445 * know for certain that the CPU has AArch32 or AArch64 respectively 3446 * or where the correct answer for a CPU which doesn't implement that 3447 * CPU state is "false" (eg when generating A32 or A64 code, if adding 3448 * system registers that are specific to that CPU state, for "should 3449 * we let this system register bit be set" tests where the 32-bit 3450 * flavour of the register doesn't have the bit, and so on). 3451 * Functions which simply ask "does this feature exist at all" have 3452 * _any_ in their name, and always return the logical OR of the _aa64_ 3453 * and the _aa32_ function. 3454 */ 3455 3456 /* 3457 * 32-bit feature tests via id registers. 3458 */ 3459 static inline bool isar_feature_aa32_thumb_div(const ARMISARegisters *id) 3460 { 3461 return FIELD_EX32(id->id_isar0, ID_ISAR0, DIVIDE) != 0; 3462 } 3463 3464 static inline bool isar_feature_aa32_arm_div(const ARMISARegisters *id) 3465 { 3466 return FIELD_EX32(id->id_isar0, ID_ISAR0, DIVIDE) > 1; 3467 } 3468 3469 static inline bool isar_feature_aa32_lob(const ARMISARegisters *id) 3470 { 3471 /* (M-profile) low-overhead loops and branch future */ 3472 return FIELD_EX32(id->id_isar0, ID_ISAR0, CMPBRANCH) >= 3; 3473 } 3474 3475 static inline bool isar_feature_aa32_jazelle(const ARMISARegisters *id) 3476 { 3477 return FIELD_EX32(id->id_isar1, ID_ISAR1, JAZELLE) != 0; 3478 } 3479 3480 static inline bool isar_feature_aa32_aes(const ARMISARegisters *id) 3481 { 3482 return FIELD_EX32(id->id_isar5, ID_ISAR5, AES) != 0; 3483 } 3484 3485 static inline bool isar_feature_aa32_pmull(const ARMISARegisters *id) 3486 { 3487 return FIELD_EX32(id->id_isar5, ID_ISAR5, AES) > 1; 3488 } 3489 3490 static inline bool isar_feature_aa32_sha1(const ARMISARegisters *id) 3491 { 3492 return FIELD_EX32(id->id_isar5, ID_ISAR5, SHA1) != 0; 3493 } 3494 3495 static inline bool isar_feature_aa32_sha2(const ARMISARegisters *id) 3496 { 3497 return FIELD_EX32(id->id_isar5, ID_ISAR5, SHA2) != 0; 3498 } 3499 3500 static inline bool isar_feature_aa32_crc32(const ARMISARegisters *id) 3501 { 3502 return FIELD_EX32(id->id_isar5, ID_ISAR5, CRC32) != 0; 3503 } 3504 3505 static inline bool isar_feature_aa32_rdm(const ARMISARegisters *id) 3506 { 3507 return FIELD_EX32(id->id_isar5, ID_ISAR5, RDM) != 0; 3508 } 3509 3510 static inline bool isar_feature_aa32_vcma(const ARMISARegisters *id) 3511 { 3512 return FIELD_EX32(id->id_isar5, ID_ISAR5, VCMA) != 0; 3513 } 3514 3515 static inline bool isar_feature_aa32_jscvt(const ARMISARegisters *id) 3516 { 3517 return FIELD_EX32(id->id_isar6, ID_ISAR6, JSCVT) != 0; 3518 } 3519 3520 static inline bool isar_feature_aa32_dp(const ARMISARegisters *id) 3521 { 3522 return FIELD_EX32(id->id_isar6, ID_ISAR6, DP) != 0; 3523 } 3524 3525 static inline bool isar_feature_aa32_fhm(const ARMISARegisters *id) 3526 { 3527 return FIELD_EX32(id->id_isar6, ID_ISAR6, FHM) != 0; 3528 } 3529 3530 static inline bool isar_feature_aa32_sb(const ARMISARegisters *id) 3531 { 3532 return FIELD_EX32(id->id_isar6, ID_ISAR6, SB) != 0; 3533 } 3534 3535 static inline bool isar_feature_aa32_predinv(const ARMISARegisters *id) 3536 { 3537 return FIELD_EX32(id->id_isar6, ID_ISAR6, SPECRES) != 0; 3538 } 3539 3540 static inline bool isar_feature_aa32_bf16(const ARMISARegisters *id) 3541 { 3542 return FIELD_EX32(id->id_isar6, ID_ISAR6, BF16) != 0; 3543 } 3544 3545 static inline bool isar_feature_aa32_i8mm(const ARMISARegisters *id) 3546 { 3547 return FIELD_EX32(id->id_isar6, ID_ISAR6, I8MM) != 0; 3548 } 3549 3550 static inline bool isar_feature_aa32_ras(const ARMISARegisters *id) 3551 { 3552 return FIELD_EX32(id->id_pfr0, ID_PFR0, RAS) != 0; 3553 } 3554 3555 static inline bool isar_feature_aa32_mprofile(const ARMISARegisters *id) 3556 { 3557 return FIELD_EX32(id->id_pfr1, ID_PFR1, MPROGMOD) != 0; 3558 } 3559 3560 static inline bool isar_feature_aa32_m_sec_state(const ARMISARegisters *id) 3561 { 3562 /* 3563 * Return true if M-profile state handling insns 3564 * (VSCCLRM, CLRM, FPCTX access insns) are implemented 3565 */ 3566 return FIELD_EX32(id->id_pfr1, ID_PFR1, SECURITY) >= 3; 3567 } 3568 3569 static inline bool isar_feature_aa32_fp16_arith(const ARMISARegisters *id) 3570 { 3571 /* Sadly this is encoded differently for A-profile and M-profile */ 3572 if (isar_feature_aa32_mprofile(id)) { 3573 return FIELD_EX32(id->mvfr1, MVFR1, FP16) > 0; 3574 } else { 3575 return FIELD_EX32(id->mvfr1, MVFR1, FPHP) >= 3; 3576 } 3577 } 3578 3579 static inline bool isar_feature_aa32_mve(const ARMISARegisters *id) 3580 { 3581 /* 3582 * Return true if MVE is supported (either integer or floating point). 3583 * We must check for M-profile as the MVFR1 field means something 3584 * else for A-profile. 3585 */ 3586 return isar_feature_aa32_mprofile(id) && 3587 FIELD_EX32(id->mvfr1, MVFR1, MVE) > 0; 3588 } 3589 3590 static inline bool isar_feature_aa32_mve_fp(const ARMISARegisters *id) 3591 { 3592 /* 3593 * Return true if MVE is supported (either integer or floating point). 3594 * We must check for M-profile as the MVFR1 field means something 3595 * else for A-profile. 3596 */ 3597 return isar_feature_aa32_mprofile(id) && 3598 FIELD_EX32(id->mvfr1, MVFR1, MVE) >= 2; 3599 } 3600 3601 static inline bool isar_feature_aa32_vfp_simd(const ARMISARegisters *id) 3602 { 3603 /* 3604 * Return true if either VFP or SIMD is implemented. 3605 * In this case, a minimum of VFP w/ D0-D15. 3606 */ 3607 return FIELD_EX32(id->mvfr0, MVFR0, SIMDREG) > 0; 3608 } 3609 3610 static inline bool isar_feature_aa32_simd_r32(const ARMISARegisters *id) 3611 { 3612 /* Return true if D16-D31 are implemented */ 3613 return FIELD_EX32(id->mvfr0, MVFR0, SIMDREG) >= 2; 3614 } 3615 3616 static inline bool isar_feature_aa32_fpshvec(const ARMISARegisters *id) 3617 { 3618 return FIELD_EX32(id->mvfr0, MVFR0, FPSHVEC) > 0; 3619 } 3620 3621 static inline bool isar_feature_aa32_fpsp_v2(const ARMISARegisters *id) 3622 { 3623 /* Return true if CPU supports single precision floating point, VFPv2 */ 3624 return FIELD_EX32(id->mvfr0, MVFR0, FPSP) > 0; 3625 } 3626 3627 static inline bool isar_feature_aa32_fpsp_v3(const ARMISARegisters *id) 3628 { 3629 /* Return true if CPU supports single precision floating point, VFPv3 */ 3630 return FIELD_EX32(id->mvfr0, MVFR0, FPSP) >= 2; 3631 } 3632 3633 static inline bool isar_feature_aa32_fpdp_v2(const ARMISARegisters *id) 3634 { 3635 /* Return true if CPU supports double precision floating point, VFPv2 */ 3636 return FIELD_EX32(id->mvfr0, MVFR0, FPDP) > 0; 3637 } 3638 3639 static inline bool isar_feature_aa32_fpdp_v3(const ARMISARegisters *id) 3640 { 3641 /* Return true if CPU supports double precision floating point, VFPv3 */ 3642 return FIELD_EX32(id->mvfr0, MVFR0, FPDP) >= 2; 3643 } 3644 3645 static inline bool isar_feature_aa32_vfp(const ARMISARegisters *id) 3646 { 3647 return isar_feature_aa32_fpsp_v2(id) || isar_feature_aa32_fpdp_v2(id); 3648 } 3649 3650 /* 3651 * We always set the FP and SIMD FP16 fields to indicate identical 3652 * levels of support (assuming SIMD is implemented at all), so 3653 * we only need one set of accessors. 3654 */ 3655 static inline bool isar_feature_aa32_fp16_spconv(const ARMISARegisters *id) 3656 { 3657 return FIELD_EX32(id->mvfr1, MVFR1, FPHP) > 0; 3658 } 3659 3660 static inline bool isar_feature_aa32_fp16_dpconv(const ARMISARegisters *id) 3661 { 3662 return FIELD_EX32(id->mvfr1, MVFR1, FPHP) > 1; 3663 } 3664 3665 /* 3666 * Note that this ID register field covers both VFP and Neon FMAC, 3667 * so should usually be tested in combination with some other 3668 * check that confirms the presence of whichever of VFP or Neon is 3669 * relevant, to avoid accidentally enabling a Neon feature on 3670 * a VFP-no-Neon core or vice-versa. 3671 */ 3672 static inline bool isar_feature_aa32_simdfmac(const ARMISARegisters *id) 3673 { 3674 return FIELD_EX32(id->mvfr1, MVFR1, SIMDFMAC) != 0; 3675 } 3676 3677 static inline bool isar_feature_aa32_vsel(const ARMISARegisters *id) 3678 { 3679 return FIELD_EX32(id->mvfr2, MVFR2, FPMISC) >= 1; 3680 } 3681 3682 static inline bool isar_feature_aa32_vcvt_dr(const ARMISARegisters *id) 3683 { 3684 return FIELD_EX32(id->mvfr2, MVFR2, FPMISC) >= 2; 3685 } 3686 3687 static inline bool isar_feature_aa32_vrint(const ARMISARegisters *id) 3688 { 3689 return FIELD_EX32(id->mvfr2, MVFR2, FPMISC) >= 3; 3690 } 3691 3692 static inline bool isar_feature_aa32_vminmaxnm(const ARMISARegisters *id) 3693 { 3694 return FIELD_EX32(id->mvfr2, MVFR2, FPMISC) >= 4; 3695 } 3696 3697 static inline bool isar_feature_aa32_pxn(const ARMISARegisters *id) 3698 { 3699 return FIELD_EX32(id->id_mmfr0, ID_MMFR0, VMSA) >= 4; 3700 } 3701 3702 static inline bool isar_feature_aa32_pan(const ARMISARegisters *id) 3703 { 3704 return FIELD_EX32(id->id_mmfr3, ID_MMFR3, PAN) != 0; 3705 } 3706 3707 static inline bool isar_feature_aa32_ats1e1(const ARMISARegisters *id) 3708 { 3709 return FIELD_EX32(id->id_mmfr3, ID_MMFR3, PAN) >= 2; 3710 } 3711 3712 static inline bool isar_feature_aa32_pmuv3p1(const ARMISARegisters *id) 3713 { 3714 /* 0xf means "non-standard IMPDEF PMU" */ 3715 return FIELD_EX32(id->id_dfr0, ID_DFR0, PERFMON) >= 4 && 3716 FIELD_EX32(id->id_dfr0, ID_DFR0, PERFMON) != 0xf; 3717 } 3718 3719 static inline bool isar_feature_aa32_pmuv3p4(const ARMISARegisters *id) 3720 { 3721 /* 0xf means "non-standard IMPDEF PMU" */ 3722 return FIELD_EX32(id->id_dfr0, ID_DFR0, PERFMON) >= 5 && 3723 FIELD_EX32(id->id_dfr0, ID_DFR0, PERFMON) != 0xf; 3724 } 3725 3726 static inline bool isar_feature_aa32_pmuv3p5(const ARMISARegisters *id) 3727 { 3728 /* 0xf means "non-standard IMPDEF PMU" */ 3729 return FIELD_EX32(id->id_dfr0, ID_DFR0, PERFMON) >= 6 && 3730 FIELD_EX32(id->id_dfr0, ID_DFR0, PERFMON) != 0xf; 3731 } 3732 3733 static inline bool isar_feature_aa32_hpd(const ARMISARegisters *id) 3734 { 3735 return FIELD_EX32(id->id_mmfr4, ID_MMFR4, HPDS) != 0; 3736 } 3737 3738 static inline bool isar_feature_aa32_ac2(const ARMISARegisters *id) 3739 { 3740 return FIELD_EX32(id->id_mmfr4, ID_MMFR4, AC2) != 0; 3741 } 3742 3743 static inline bool isar_feature_aa32_ccidx(const ARMISARegisters *id) 3744 { 3745 return FIELD_EX32(id->id_mmfr4, ID_MMFR4, CCIDX) != 0; 3746 } 3747 3748 static inline bool isar_feature_aa32_tts2uxn(const ARMISARegisters *id) 3749 { 3750 return FIELD_EX32(id->id_mmfr4, ID_MMFR4, XNX) != 0; 3751 } 3752 3753 static inline bool isar_feature_aa32_dit(const ARMISARegisters *id) 3754 { 3755 return FIELD_EX32(id->id_pfr0, ID_PFR0, DIT) != 0; 3756 } 3757 3758 static inline bool isar_feature_aa32_ssbs(const ARMISARegisters *id) 3759 { 3760 return FIELD_EX32(id->id_pfr2, ID_PFR2, SSBS) != 0; 3761 } 3762 3763 static inline bool isar_feature_aa32_debugv7p1(const ARMISARegisters *id) 3764 { 3765 return FIELD_EX32(id->id_dfr0, ID_DFR0, COPDBG) >= 5; 3766 } 3767 3768 static inline bool isar_feature_aa32_debugv8p2(const ARMISARegisters *id) 3769 { 3770 return FIELD_EX32(id->id_dfr0, ID_DFR0, COPDBG) >= 8; 3771 } 3772 3773 static inline bool isar_feature_aa32_doublelock(const ARMISARegisters *id) 3774 { 3775 return FIELD_EX32(id->dbgdevid, DBGDEVID, DOUBLELOCK) > 0; 3776 } 3777 3778 /* 3779 * 64-bit feature tests via id registers. 3780 */ 3781 static inline bool isar_feature_aa64_aes(const ARMISARegisters *id) 3782 { 3783 return FIELD_EX64(id->id_aa64isar0, ID_AA64ISAR0, AES) != 0; 3784 } 3785 3786 static inline bool isar_feature_aa64_pmull(const ARMISARegisters *id) 3787 { 3788 return FIELD_EX64(id->id_aa64isar0, ID_AA64ISAR0, AES) > 1; 3789 } 3790 3791 static inline bool isar_feature_aa64_sha1(const ARMISARegisters *id) 3792 { 3793 return FIELD_EX64(id->id_aa64isar0, ID_AA64ISAR0, SHA1) != 0; 3794 } 3795 3796 static inline bool isar_feature_aa64_sha256(const ARMISARegisters *id) 3797 { 3798 return FIELD_EX64(id->id_aa64isar0, ID_AA64ISAR0, SHA2) != 0; 3799 } 3800 3801 static inline bool isar_feature_aa64_sha512(const ARMISARegisters *id) 3802 { 3803 return FIELD_EX64(id->id_aa64isar0, ID_AA64ISAR0, SHA2) > 1; 3804 } 3805 3806 static inline bool isar_feature_aa64_crc32(const ARMISARegisters *id) 3807 { 3808 return FIELD_EX64(id->id_aa64isar0, ID_AA64ISAR0, CRC32) != 0; 3809 } 3810 3811 static inline bool isar_feature_aa64_atomics(const ARMISARegisters *id) 3812 { 3813 return FIELD_EX64(id->id_aa64isar0, ID_AA64ISAR0, ATOMIC) != 0; 3814 } 3815 3816 static inline bool isar_feature_aa64_rdm(const ARMISARegisters *id) 3817 { 3818 return FIELD_EX64(id->id_aa64isar0, ID_AA64ISAR0, RDM) != 0; 3819 } 3820 3821 static inline bool isar_feature_aa64_sha3(const ARMISARegisters *id) 3822 { 3823 return FIELD_EX64(id->id_aa64isar0, ID_AA64ISAR0, SHA3) != 0; 3824 } 3825 3826 static inline bool isar_feature_aa64_sm3(const ARMISARegisters *id) 3827 { 3828 return FIELD_EX64(id->id_aa64isar0, ID_AA64ISAR0, SM3) != 0; 3829 } 3830 3831 static inline bool isar_feature_aa64_sm4(const ARMISARegisters *id) 3832 { 3833 return FIELD_EX64(id->id_aa64isar0, ID_AA64ISAR0, SM4) != 0; 3834 } 3835 3836 static inline bool isar_feature_aa64_dp(const ARMISARegisters *id) 3837 { 3838 return FIELD_EX64(id->id_aa64isar0, ID_AA64ISAR0, DP) != 0; 3839 } 3840 3841 static inline bool isar_feature_aa64_fhm(const ARMISARegisters *id) 3842 { 3843 return FIELD_EX64(id->id_aa64isar0, ID_AA64ISAR0, FHM) != 0; 3844 } 3845 3846 static inline bool isar_feature_aa64_condm_4(const ARMISARegisters *id) 3847 { 3848 return FIELD_EX64(id->id_aa64isar0, ID_AA64ISAR0, TS) != 0; 3849 } 3850 3851 static inline bool isar_feature_aa64_condm_5(const ARMISARegisters *id) 3852 { 3853 return FIELD_EX64(id->id_aa64isar0, ID_AA64ISAR0, TS) >= 2; 3854 } 3855 3856 static inline bool isar_feature_aa64_rndr(const ARMISARegisters *id) 3857 { 3858 return FIELD_EX64(id->id_aa64isar0, ID_AA64ISAR0, RNDR) != 0; 3859 } 3860 3861 static inline bool isar_feature_aa64_jscvt(const ARMISARegisters *id) 3862 { 3863 return FIELD_EX64(id->id_aa64isar1, ID_AA64ISAR1, JSCVT) != 0; 3864 } 3865 3866 static inline bool isar_feature_aa64_fcma(const ARMISARegisters *id) 3867 { 3868 return FIELD_EX64(id->id_aa64isar1, ID_AA64ISAR1, FCMA) != 0; 3869 } 3870 3871 static inline bool isar_feature_aa64_pauth(const ARMISARegisters *id) 3872 { 3873 /* 3874 * Return true if any form of pauth is enabled, as this 3875 * predicate controls migration of the 128-bit keys. 3876 */ 3877 return (id->id_aa64isar1 & 3878 (FIELD_DP64(0, ID_AA64ISAR1, APA, 0xf) | 3879 FIELD_DP64(0, ID_AA64ISAR1, API, 0xf) | 3880 FIELD_DP64(0, ID_AA64ISAR1, GPA, 0xf) | 3881 FIELD_DP64(0, ID_AA64ISAR1, GPI, 0xf))) != 0; 3882 } 3883 3884 static inline bool isar_feature_aa64_pauth_arch(const ARMISARegisters *id) 3885 { 3886 /* 3887 * Return true if pauth is enabled with the architected QARMA algorithm. 3888 * QEMU will always set APA+GPA to the same value. 3889 */ 3890 return FIELD_EX64(id->id_aa64isar1, ID_AA64ISAR1, APA) != 0; 3891 } 3892 3893 static inline bool isar_feature_aa64_tlbirange(const ARMISARegisters *id) 3894 { 3895 return FIELD_EX64(id->id_aa64isar0, ID_AA64ISAR0, TLB) == 2; 3896 } 3897 3898 static inline bool isar_feature_aa64_tlbios(const ARMISARegisters *id) 3899 { 3900 return FIELD_EX64(id->id_aa64isar0, ID_AA64ISAR0, TLB) != 0; 3901 } 3902 3903 static inline bool isar_feature_aa64_sb(const ARMISARegisters *id) 3904 { 3905 return FIELD_EX64(id->id_aa64isar1, ID_AA64ISAR1, SB) != 0; 3906 } 3907 3908 static inline bool isar_feature_aa64_predinv(const ARMISARegisters *id) 3909 { 3910 return FIELD_EX64(id->id_aa64isar1, ID_AA64ISAR1, SPECRES) != 0; 3911 } 3912 3913 static inline bool isar_feature_aa64_frint(const ARMISARegisters *id) 3914 { 3915 return FIELD_EX64(id->id_aa64isar1, ID_AA64ISAR1, FRINTTS) != 0; 3916 } 3917 3918 static inline bool isar_feature_aa64_dcpop(const ARMISARegisters *id) 3919 { 3920 return FIELD_EX64(id->id_aa64isar1, ID_AA64ISAR1, DPB) != 0; 3921 } 3922 3923 static inline bool isar_feature_aa64_dcpodp(const ARMISARegisters *id) 3924 { 3925 return FIELD_EX64(id->id_aa64isar1, ID_AA64ISAR1, DPB) >= 2; 3926 } 3927 3928 static inline bool isar_feature_aa64_bf16(const ARMISARegisters *id) 3929 { 3930 return FIELD_EX64(id->id_aa64isar1, ID_AA64ISAR1, BF16) != 0; 3931 } 3932 3933 static inline bool isar_feature_aa64_fp_simd(const ARMISARegisters *id) 3934 { 3935 /* We always set the AdvSIMD and FP fields identically. */ 3936 return FIELD_EX64(id->id_aa64pfr0, ID_AA64PFR0, FP) != 0xf; 3937 } 3938 3939 static inline bool isar_feature_aa64_fp16(const ARMISARegisters *id) 3940 { 3941 /* We always set the AdvSIMD and FP fields identically wrt FP16. */ 3942 return FIELD_EX64(id->id_aa64pfr0, ID_AA64PFR0, FP) == 1; 3943 } 3944 3945 static inline bool isar_feature_aa64_aa32(const ARMISARegisters *id) 3946 { 3947 return FIELD_EX64(id->id_aa64pfr0, ID_AA64PFR0, EL0) >= 2; 3948 } 3949 3950 static inline bool isar_feature_aa64_aa32_el1(const ARMISARegisters *id) 3951 { 3952 return FIELD_EX64(id->id_aa64pfr0, ID_AA64PFR0, EL1) >= 2; 3953 } 3954 3955 static inline bool isar_feature_aa64_aa32_el2(const ARMISARegisters *id) 3956 { 3957 return FIELD_EX64(id->id_aa64pfr0, ID_AA64PFR0, EL2) >= 2; 3958 } 3959 3960 static inline bool isar_feature_aa64_ras(const ARMISARegisters *id) 3961 { 3962 return FIELD_EX64(id->id_aa64pfr0, ID_AA64PFR0, RAS) != 0; 3963 } 3964 3965 static inline bool isar_feature_aa64_doublefault(const ARMISARegisters *id) 3966 { 3967 return FIELD_EX64(id->id_aa64pfr0, ID_AA64PFR0, RAS) >= 2; 3968 } 3969 3970 static inline bool isar_feature_aa64_sve(const ARMISARegisters *id) 3971 { 3972 return FIELD_EX64(id->id_aa64pfr0, ID_AA64PFR0, SVE) != 0; 3973 } 3974 3975 static inline bool isar_feature_aa64_sel2(const ARMISARegisters *id) 3976 { 3977 return FIELD_EX64(id->id_aa64pfr0, ID_AA64PFR0, SEL2) != 0; 3978 } 3979 3980 static inline bool isar_feature_aa64_vh(const ARMISARegisters *id) 3981 { 3982 return FIELD_EX64(id->id_aa64mmfr1, ID_AA64MMFR1, VH) != 0; 3983 } 3984 3985 static inline bool isar_feature_aa64_lor(const ARMISARegisters *id) 3986 { 3987 return FIELD_EX64(id->id_aa64mmfr1, ID_AA64MMFR1, LO) != 0; 3988 } 3989 3990 static inline bool isar_feature_aa64_pan(const ARMISARegisters *id) 3991 { 3992 return FIELD_EX64(id->id_aa64mmfr1, ID_AA64MMFR1, PAN) != 0; 3993 } 3994 3995 static inline bool isar_feature_aa64_ats1e1(const ARMISARegisters *id) 3996 { 3997 return FIELD_EX64(id->id_aa64mmfr1, ID_AA64MMFR1, PAN) >= 2; 3998 } 3999 4000 static inline bool isar_feature_aa64_hcx(const ARMISARegisters *id) 4001 { 4002 return FIELD_EX64(id->id_aa64mmfr1, ID_AA64MMFR1, HCX) != 0; 4003 } 4004 4005 static inline bool isar_feature_aa64_uao(const ARMISARegisters *id) 4006 { 4007 return FIELD_EX64(id->id_aa64mmfr2, ID_AA64MMFR2, UAO) != 0; 4008 } 4009 4010 static inline bool isar_feature_aa64_st(const ARMISARegisters *id) 4011 { 4012 return FIELD_EX64(id->id_aa64mmfr2, ID_AA64MMFR2, ST) != 0; 4013 } 4014 4015 static inline bool isar_feature_aa64_fwb(const ARMISARegisters *id) 4016 { 4017 return FIELD_EX64(id->id_aa64mmfr2, ID_AA64MMFR2, FWB) != 0; 4018 } 4019 4020 static inline bool isar_feature_aa64_ids(const ARMISARegisters *id) 4021 { 4022 return FIELD_EX64(id->id_aa64mmfr2, ID_AA64MMFR2, IDS) != 0; 4023 } 4024 4025 static inline bool isar_feature_aa64_bti(const ARMISARegisters *id) 4026 { 4027 return FIELD_EX64(id->id_aa64pfr1, ID_AA64PFR1, BT) != 0; 4028 } 4029 4030 static inline bool isar_feature_aa64_mte_insn_reg(const ARMISARegisters *id) 4031 { 4032 return FIELD_EX64(id->id_aa64pfr1, ID_AA64PFR1, MTE) != 0; 4033 } 4034 4035 static inline bool isar_feature_aa64_mte(const ARMISARegisters *id) 4036 { 4037 return FIELD_EX64(id->id_aa64pfr1, ID_AA64PFR1, MTE) >= 2; 4038 } 4039 4040 static inline bool isar_feature_aa64_sme(const ARMISARegisters *id) 4041 { 4042 return FIELD_EX64(id->id_aa64pfr1, ID_AA64PFR1, SME) != 0; 4043 } 4044 4045 static inline bool isar_feature_aa64_pmuv3p1(const ARMISARegisters *id) 4046 { 4047 return FIELD_EX64(id->id_aa64dfr0, ID_AA64DFR0, PMUVER) >= 4 && 4048 FIELD_EX64(id->id_aa64dfr0, ID_AA64DFR0, PMUVER) != 0xf; 4049 } 4050 4051 static inline bool isar_feature_aa64_pmuv3p4(const ARMISARegisters *id) 4052 { 4053 return FIELD_EX64(id->id_aa64dfr0, ID_AA64DFR0, PMUVER) >= 5 && 4054 FIELD_EX64(id->id_aa64dfr0, ID_AA64DFR0, PMUVER) != 0xf; 4055 } 4056 4057 static inline bool isar_feature_aa64_pmuv3p5(const ARMISARegisters *id) 4058 { 4059 return FIELD_EX64(id->id_aa64dfr0, ID_AA64DFR0, PMUVER) >= 6 && 4060 FIELD_EX64(id->id_aa64dfr0, ID_AA64DFR0, PMUVER) != 0xf; 4061 } 4062 4063 static inline bool isar_feature_aa64_rcpc_8_3(const ARMISARegisters *id) 4064 { 4065 return FIELD_EX64(id->id_aa64isar1, ID_AA64ISAR1, LRCPC) != 0; 4066 } 4067 4068 static inline bool isar_feature_aa64_rcpc_8_4(const ARMISARegisters *id) 4069 { 4070 return FIELD_EX64(id->id_aa64isar1, ID_AA64ISAR1, LRCPC) >= 2; 4071 } 4072 4073 static inline bool isar_feature_aa64_i8mm(const ARMISARegisters *id) 4074 { 4075 return FIELD_EX64(id->id_aa64isar1, ID_AA64ISAR1, I8MM) != 0; 4076 } 4077 4078 static inline bool isar_feature_aa64_tgran4_lpa2(const ARMISARegisters *id) 4079 { 4080 return FIELD_SEX64(id->id_aa64mmfr0, ID_AA64MMFR0, TGRAN4) >= 1; 4081 } 4082 4083 static inline bool isar_feature_aa64_tgran4_2_lpa2(const ARMISARegisters *id) 4084 { 4085 unsigned t = FIELD_EX64(id->id_aa64mmfr0, ID_AA64MMFR0, TGRAN4_2); 4086 return t >= 3 || (t == 0 && isar_feature_aa64_tgran4_lpa2(id)); 4087 } 4088 4089 static inline bool isar_feature_aa64_tgran16_lpa2(const ARMISARegisters *id) 4090 { 4091 return FIELD_EX64(id->id_aa64mmfr0, ID_AA64MMFR0, TGRAN16) >= 2; 4092 } 4093 4094 static inline bool isar_feature_aa64_tgran16_2_lpa2(const ARMISARegisters *id) 4095 { 4096 unsigned t = FIELD_EX64(id->id_aa64mmfr0, ID_AA64MMFR0, TGRAN16_2); 4097 return t >= 3 || (t == 0 && isar_feature_aa64_tgran16_lpa2(id)); 4098 } 4099 4100 static inline bool isar_feature_aa64_tgran4(const ARMISARegisters *id) 4101 { 4102 return FIELD_SEX64(id->id_aa64mmfr0, ID_AA64MMFR0, TGRAN4) >= 0; 4103 } 4104 4105 static inline bool isar_feature_aa64_tgran16(const ARMISARegisters *id) 4106 { 4107 return FIELD_EX64(id->id_aa64mmfr0, ID_AA64MMFR0, TGRAN16) >= 1; 4108 } 4109 4110 static inline bool isar_feature_aa64_tgran64(const ARMISARegisters *id) 4111 { 4112 return FIELD_SEX64(id->id_aa64mmfr0, ID_AA64MMFR0, TGRAN64) >= 0; 4113 } 4114 4115 static inline bool isar_feature_aa64_tgran4_2(const ARMISARegisters *id) 4116 { 4117 unsigned t = FIELD_EX64(id->id_aa64mmfr0, ID_AA64MMFR0, TGRAN4_2); 4118 return t >= 2 || (t == 0 && isar_feature_aa64_tgran4(id)); 4119 } 4120 4121 static inline bool isar_feature_aa64_tgran16_2(const ARMISARegisters *id) 4122 { 4123 unsigned t = FIELD_EX64(id->id_aa64mmfr0, ID_AA64MMFR0, TGRAN16_2); 4124 return t >= 2 || (t == 0 && isar_feature_aa64_tgran16(id)); 4125 } 4126 4127 static inline bool isar_feature_aa64_tgran64_2(const ARMISARegisters *id) 4128 { 4129 unsigned t = FIELD_EX64(id->id_aa64mmfr0, ID_AA64MMFR0, TGRAN64_2); 4130 return t >= 2 || (t == 0 && isar_feature_aa64_tgran64(id)); 4131 } 4132 4133 static inline bool isar_feature_aa64_ccidx(const ARMISARegisters *id) 4134 { 4135 return FIELD_EX64(id->id_aa64mmfr2, ID_AA64MMFR2, CCIDX) != 0; 4136 } 4137 4138 static inline bool isar_feature_aa64_lva(const ARMISARegisters *id) 4139 { 4140 return FIELD_EX64(id->id_aa64mmfr2, ID_AA64MMFR2, VARANGE) != 0; 4141 } 4142 4143 static inline bool isar_feature_aa64_tts2uxn(const ARMISARegisters *id) 4144 { 4145 return FIELD_EX64(id->id_aa64mmfr1, ID_AA64MMFR1, XNX) != 0; 4146 } 4147 4148 static inline bool isar_feature_aa64_dit(const ARMISARegisters *id) 4149 { 4150 return FIELD_EX64(id->id_aa64pfr0, ID_AA64PFR0, DIT) != 0; 4151 } 4152 4153 static inline bool isar_feature_aa64_scxtnum(const ARMISARegisters *id) 4154 { 4155 int key = FIELD_EX64(id->id_aa64pfr0, ID_AA64PFR0, CSV2); 4156 if (key >= 2) { 4157 return true; /* FEAT_CSV2_2 */ 4158 } 4159 if (key == 1) { 4160 key = FIELD_EX64(id->id_aa64pfr1, ID_AA64PFR1, CSV2_FRAC); 4161 return key >= 2; /* FEAT_CSV2_1p2 */ 4162 } 4163 return false; 4164 } 4165 4166 static inline bool isar_feature_aa64_ssbs(const ARMISARegisters *id) 4167 { 4168 return FIELD_EX64(id->id_aa64pfr1, ID_AA64PFR1, SSBS) != 0; 4169 } 4170 4171 static inline bool isar_feature_aa64_debugv8p2(const ARMISARegisters *id) 4172 { 4173 return FIELD_EX64(id->id_aa64dfr0, ID_AA64DFR0, DEBUGVER) >= 8; 4174 } 4175 4176 static inline bool isar_feature_aa64_sve2(const ARMISARegisters *id) 4177 { 4178 return FIELD_EX64(id->id_aa64zfr0, ID_AA64ZFR0, SVEVER) != 0; 4179 } 4180 4181 static inline bool isar_feature_aa64_sve2_aes(const ARMISARegisters *id) 4182 { 4183 return FIELD_EX64(id->id_aa64zfr0, ID_AA64ZFR0, AES) != 0; 4184 } 4185 4186 static inline bool isar_feature_aa64_sve2_pmull128(const ARMISARegisters *id) 4187 { 4188 return FIELD_EX64(id->id_aa64zfr0, ID_AA64ZFR0, AES) >= 2; 4189 } 4190 4191 static inline bool isar_feature_aa64_sve2_bitperm(const ARMISARegisters *id) 4192 { 4193 return FIELD_EX64(id->id_aa64zfr0, ID_AA64ZFR0, BITPERM) != 0; 4194 } 4195 4196 static inline bool isar_feature_aa64_sve_bf16(const ARMISARegisters *id) 4197 { 4198 return FIELD_EX64(id->id_aa64zfr0, ID_AA64ZFR0, BFLOAT16) != 0; 4199 } 4200 4201 static inline bool isar_feature_aa64_sve2_sha3(const ARMISARegisters *id) 4202 { 4203 return FIELD_EX64(id->id_aa64zfr0, ID_AA64ZFR0, SHA3) != 0; 4204 } 4205 4206 static inline bool isar_feature_aa64_sve2_sm4(const ARMISARegisters *id) 4207 { 4208 return FIELD_EX64(id->id_aa64zfr0, ID_AA64ZFR0, SM4) != 0; 4209 } 4210 4211 static inline bool isar_feature_aa64_sve_i8mm(const ARMISARegisters *id) 4212 { 4213 return FIELD_EX64(id->id_aa64zfr0, ID_AA64ZFR0, I8MM) != 0; 4214 } 4215 4216 static inline bool isar_feature_aa64_sve_f32mm(const ARMISARegisters *id) 4217 { 4218 return FIELD_EX64(id->id_aa64zfr0, ID_AA64ZFR0, F32MM) != 0; 4219 } 4220 4221 static inline bool isar_feature_aa64_sve_f64mm(const ARMISARegisters *id) 4222 { 4223 return FIELD_EX64(id->id_aa64zfr0, ID_AA64ZFR0, F64MM) != 0; 4224 } 4225 4226 static inline bool isar_feature_aa64_sme_f64f64(const ARMISARegisters *id) 4227 { 4228 return FIELD_EX64(id->id_aa64smfr0, ID_AA64SMFR0, F64F64); 4229 } 4230 4231 static inline bool isar_feature_aa64_sme_i16i64(const ARMISARegisters *id) 4232 { 4233 return FIELD_EX64(id->id_aa64smfr0, ID_AA64SMFR0, I16I64) == 0xf; 4234 } 4235 4236 static inline bool isar_feature_aa64_sme_fa64(const ARMISARegisters *id) 4237 { 4238 return FIELD_EX64(id->id_aa64smfr0, ID_AA64SMFR0, FA64); 4239 } 4240 4241 static inline bool isar_feature_aa64_doublelock(const ARMISARegisters *id) 4242 { 4243 return FIELD_SEX64(id->id_aa64dfr0, ID_AA64DFR0, DOUBLELOCK) >= 0; 4244 } 4245 4246 /* 4247 * Feature tests for "does this exist in either 32-bit or 64-bit?" 4248 */ 4249 static inline bool isar_feature_any_fp16(const ARMISARegisters *id) 4250 { 4251 return isar_feature_aa64_fp16(id) || isar_feature_aa32_fp16_arith(id); 4252 } 4253 4254 static inline bool isar_feature_any_predinv(const ARMISARegisters *id) 4255 { 4256 return isar_feature_aa64_predinv(id) || isar_feature_aa32_predinv(id); 4257 } 4258 4259 static inline bool isar_feature_any_pmuv3p1(const ARMISARegisters *id) 4260 { 4261 return isar_feature_aa64_pmuv3p1(id) || isar_feature_aa32_pmuv3p1(id); 4262 } 4263 4264 static inline bool isar_feature_any_pmuv3p4(const ARMISARegisters *id) 4265 { 4266 return isar_feature_aa64_pmuv3p4(id) || isar_feature_aa32_pmuv3p4(id); 4267 } 4268 4269 static inline bool isar_feature_any_pmuv3p5(const ARMISARegisters *id) 4270 { 4271 return isar_feature_aa64_pmuv3p5(id) || isar_feature_aa32_pmuv3p5(id); 4272 } 4273 4274 static inline bool isar_feature_any_ccidx(const ARMISARegisters *id) 4275 { 4276 return isar_feature_aa64_ccidx(id) || isar_feature_aa32_ccidx(id); 4277 } 4278 4279 static inline bool isar_feature_any_tts2uxn(const ARMISARegisters *id) 4280 { 4281 return isar_feature_aa64_tts2uxn(id) || isar_feature_aa32_tts2uxn(id); 4282 } 4283 4284 static inline bool isar_feature_any_debugv8p2(const ARMISARegisters *id) 4285 { 4286 return isar_feature_aa64_debugv8p2(id) || isar_feature_aa32_debugv8p2(id); 4287 } 4288 4289 static inline bool isar_feature_any_ras(const ARMISARegisters *id) 4290 { 4291 return isar_feature_aa64_ras(id) || isar_feature_aa32_ras(id); 4292 } 4293 4294 /* 4295 * Forward to the above feature tests given an ARMCPU pointer. 4296 */ 4297 #define cpu_isar_feature(name, cpu) \ 4298 ({ ARMCPU *cpu_ = (cpu); isar_feature_##name(&cpu_->isar); }) 4299 4300 #endif 4301