1 /* 2 * ARM virtual CPU header 3 * 4 * Copyright (c) 2003 Fabrice Bellard 5 * 6 * This library is free software; you can redistribute it and/or 7 * modify it under the terms of the GNU Lesser General Public 8 * License as published by the Free Software Foundation; either 9 * version 2 of the License, or (at your option) any later version. 10 * 11 * This library is distributed in the hope that it will be useful, 12 * but WITHOUT ANY WARRANTY; without even the implied warranty of 13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU 14 * Lesser General Public License for more details. 15 * 16 * You should have received a copy of the GNU Lesser General Public 17 * License along with this library; if not, see <http://www.gnu.org/licenses/>. 18 */ 19 20 #ifndef ARM_CPU_H 21 #define ARM_CPU_H 22 23 #include "kvm-consts.h" 24 #include "hw/registerfields.h" 25 26 #if defined(TARGET_AARCH64) 27 /* AArch64 definitions */ 28 # define TARGET_LONG_BITS 64 29 #else 30 # define TARGET_LONG_BITS 32 31 #endif 32 33 /* ARM processors have a weak memory model */ 34 #define TCG_GUEST_DEFAULT_MO (0) 35 36 #define CPUArchState struct CPUARMState 37 38 #include "qemu-common.h" 39 #include "cpu-qom.h" 40 #include "exec/cpu-defs.h" 41 42 #include "fpu/softfloat.h" 43 44 #define EXCP_UDEF 1 /* undefined instruction */ 45 #define EXCP_SWI 2 /* software interrupt */ 46 #define EXCP_PREFETCH_ABORT 3 47 #define EXCP_DATA_ABORT 4 48 #define EXCP_IRQ 5 49 #define EXCP_FIQ 6 50 #define EXCP_BKPT 7 51 #define EXCP_EXCEPTION_EXIT 8 /* Return from v7M exception. */ 52 #define EXCP_KERNEL_TRAP 9 /* Jumped to kernel code page. */ 53 #define EXCP_HVC 11 /* HyperVisor Call */ 54 #define EXCP_HYP_TRAP 12 55 #define EXCP_SMC 13 /* Secure Monitor Call */ 56 #define EXCP_VIRQ 14 57 #define EXCP_VFIQ 15 58 #define EXCP_SEMIHOST 16 /* semihosting call */ 59 #define EXCP_NOCP 17 /* v7M NOCP UsageFault */ 60 #define EXCP_INVSTATE 18 /* v7M INVSTATE UsageFault */ 61 /* NB: add new EXCP_ defines to the array in arm_log_exception() too */ 62 63 #define ARMV7M_EXCP_RESET 1 64 #define ARMV7M_EXCP_NMI 2 65 #define ARMV7M_EXCP_HARD 3 66 #define ARMV7M_EXCP_MEM 4 67 #define ARMV7M_EXCP_BUS 5 68 #define ARMV7M_EXCP_USAGE 6 69 #define ARMV7M_EXCP_SECURE 7 70 #define ARMV7M_EXCP_SVC 11 71 #define ARMV7M_EXCP_DEBUG 12 72 #define ARMV7M_EXCP_PENDSV 14 73 #define ARMV7M_EXCP_SYSTICK 15 74 75 /* For M profile, some registers are banked secure vs non-secure; 76 * these are represented as a 2-element array where the first element 77 * is the non-secure copy and the second is the secure copy. 78 * When the CPU does not have implement the security extension then 79 * only the first element is used. 80 * This means that the copy for the current security state can be 81 * accessed via env->registerfield[env->v7m.secure] (whether the security 82 * extension is implemented or not). 83 */ 84 #define M_REG_NS 0 85 #define M_REG_S 1 86 87 /* ARM-specific interrupt pending bits. */ 88 #define CPU_INTERRUPT_FIQ CPU_INTERRUPT_TGT_EXT_1 89 #define CPU_INTERRUPT_VIRQ CPU_INTERRUPT_TGT_EXT_2 90 #define CPU_INTERRUPT_VFIQ CPU_INTERRUPT_TGT_EXT_3 91 92 /* The usual mapping for an AArch64 system register to its AArch32 93 * counterpart is for the 32 bit world to have access to the lower 94 * half only (with writes leaving the upper half untouched). It's 95 * therefore useful to be able to pass TCG the offset of the least 96 * significant half of a uint64_t struct member. 97 */ 98 #ifdef HOST_WORDS_BIGENDIAN 99 #define offsetoflow32(S, M) (offsetof(S, M) + sizeof(uint32_t)) 100 #define offsetofhigh32(S, M) offsetof(S, M) 101 #else 102 #define offsetoflow32(S, M) offsetof(S, M) 103 #define offsetofhigh32(S, M) (offsetof(S, M) + sizeof(uint32_t)) 104 #endif 105 106 /* Meanings of the ARMCPU object's four inbound GPIO lines */ 107 #define ARM_CPU_IRQ 0 108 #define ARM_CPU_FIQ 1 109 #define ARM_CPU_VIRQ 2 110 #define ARM_CPU_VFIQ 3 111 112 #define NB_MMU_MODES 7 113 /* ARM-specific extra insn start words: 114 * 1: Conditional execution bits 115 * 2: Partial exception syndrome for data aborts 116 */ 117 #define TARGET_INSN_START_EXTRA_WORDS 2 118 119 /* The 2nd extra word holding syndrome info for data aborts does not use 120 * the upper 6 bits nor the lower 14 bits. We mask and shift it down to 121 * help the sleb128 encoder do a better job. 122 * When restoring the CPU state, we shift it back up. 123 */ 124 #define ARM_INSN_START_WORD2_MASK ((1 << 26) - 1) 125 #define ARM_INSN_START_WORD2_SHIFT 14 126 127 /* We currently assume float and double are IEEE single and double 128 precision respectively. 129 Doing runtime conversions is tricky because VFP registers may contain 130 integer values (eg. as the result of a FTOSI instruction). 131 s<2n> maps to the least significant half of d<n> 132 s<2n+1> maps to the most significant half of d<n> 133 */ 134 135 /* CPU state for each instance of a generic timer (in cp15 c14) */ 136 typedef struct ARMGenericTimer { 137 uint64_t cval; /* Timer CompareValue register */ 138 uint64_t ctl; /* Timer Control register */ 139 } ARMGenericTimer; 140 141 #define GTIMER_PHYS 0 142 #define GTIMER_VIRT 1 143 #define GTIMER_HYP 2 144 #define GTIMER_SEC 3 145 #define NUM_GTIMERS 4 146 147 typedef struct { 148 uint64_t raw_tcr; 149 uint32_t mask; 150 uint32_t base_mask; 151 } TCR; 152 153 typedef struct CPUARMState { 154 /* Regs for current mode. */ 155 uint32_t regs[16]; 156 157 /* 32/64 switch only happens when taking and returning from 158 * exceptions so the overlap semantics are taken care of then 159 * instead of having a complicated union. 160 */ 161 /* Regs for A64 mode. */ 162 uint64_t xregs[32]; 163 uint64_t pc; 164 /* PSTATE isn't an architectural register for ARMv8. However, it is 165 * convenient for us to assemble the underlying state into a 32 bit format 166 * identical to the architectural format used for the SPSR. (This is also 167 * what the Linux kernel's 'pstate' field in signal handlers and KVM's 168 * 'pstate' register are.) Of the PSTATE bits: 169 * NZCV are kept in the split out env->CF/VF/NF/ZF, (which have the same 170 * semantics as for AArch32, as described in the comments on each field) 171 * nRW (also known as M[4]) is kept, inverted, in env->aarch64 172 * DAIF (exception masks) are kept in env->daif 173 * all other bits are stored in their correct places in env->pstate 174 */ 175 uint32_t pstate; 176 uint32_t aarch64; /* 1 if CPU is in aarch64 state; inverse of PSTATE.nRW */ 177 178 /* Frequently accessed CPSR bits are stored separately for efficiency. 179 This contains all the other bits. Use cpsr_{read,write} to access 180 the whole CPSR. */ 181 uint32_t uncached_cpsr; 182 uint32_t spsr; 183 184 /* Banked registers. */ 185 uint64_t banked_spsr[8]; 186 uint32_t banked_r13[8]; 187 uint32_t banked_r14[8]; 188 189 /* These hold r8-r12. */ 190 uint32_t usr_regs[5]; 191 uint32_t fiq_regs[5]; 192 193 /* cpsr flag cache for faster execution */ 194 uint32_t CF; /* 0 or 1 */ 195 uint32_t VF; /* V is the bit 31. All other bits are undefined */ 196 uint32_t NF; /* N is bit 31. All other bits are undefined. */ 197 uint32_t ZF; /* Z set if zero. */ 198 uint32_t QF; /* 0 or 1 */ 199 uint32_t GE; /* cpsr[19:16] */ 200 uint32_t thumb; /* cpsr[5]. 0 = arm mode, 1 = thumb mode. */ 201 uint32_t condexec_bits; /* IT bits. cpsr[15:10,26:25]. */ 202 uint64_t daif; /* exception masks, in the bits they are in PSTATE */ 203 204 uint64_t elr_el[4]; /* AArch64 exception link regs */ 205 uint64_t sp_el[4]; /* AArch64 banked stack pointers */ 206 207 /* System control coprocessor (cp15) */ 208 struct { 209 uint32_t c0_cpuid; 210 union { /* Cache size selection */ 211 struct { 212 uint64_t _unused_csselr0; 213 uint64_t csselr_ns; 214 uint64_t _unused_csselr1; 215 uint64_t csselr_s; 216 }; 217 uint64_t csselr_el[4]; 218 }; 219 union { /* System control register. */ 220 struct { 221 uint64_t _unused_sctlr; 222 uint64_t sctlr_ns; 223 uint64_t hsctlr; 224 uint64_t sctlr_s; 225 }; 226 uint64_t sctlr_el[4]; 227 }; 228 uint64_t cpacr_el1; /* Architectural feature access control register */ 229 uint64_t cptr_el[4]; /* ARMv8 feature trap registers */ 230 uint32_t c1_xscaleauxcr; /* XScale auxiliary control register. */ 231 uint64_t sder; /* Secure debug enable register. */ 232 uint32_t nsacr; /* Non-secure access control register. */ 233 union { /* MMU translation table base 0. */ 234 struct { 235 uint64_t _unused_ttbr0_0; 236 uint64_t ttbr0_ns; 237 uint64_t _unused_ttbr0_1; 238 uint64_t ttbr0_s; 239 }; 240 uint64_t ttbr0_el[4]; 241 }; 242 union { /* MMU translation table base 1. */ 243 struct { 244 uint64_t _unused_ttbr1_0; 245 uint64_t ttbr1_ns; 246 uint64_t _unused_ttbr1_1; 247 uint64_t ttbr1_s; 248 }; 249 uint64_t ttbr1_el[4]; 250 }; 251 uint64_t vttbr_el2; /* Virtualization Translation Table Base. */ 252 /* MMU translation table base control. */ 253 TCR tcr_el[4]; 254 TCR vtcr_el2; /* Virtualization Translation Control. */ 255 uint32_t c2_data; /* MPU data cacheable bits. */ 256 uint32_t c2_insn; /* MPU instruction cacheable bits. */ 257 union { /* MMU domain access control register 258 * MPU write buffer control. 259 */ 260 struct { 261 uint64_t dacr_ns; 262 uint64_t dacr_s; 263 }; 264 struct { 265 uint64_t dacr32_el2; 266 }; 267 }; 268 uint32_t pmsav5_data_ap; /* PMSAv5 MPU data access permissions */ 269 uint32_t pmsav5_insn_ap; /* PMSAv5 MPU insn access permissions */ 270 uint64_t hcr_el2; /* Hypervisor configuration register */ 271 uint64_t scr_el3; /* Secure configuration register. */ 272 union { /* Fault status registers. */ 273 struct { 274 uint64_t ifsr_ns; 275 uint64_t ifsr_s; 276 }; 277 struct { 278 uint64_t ifsr32_el2; 279 }; 280 }; 281 union { 282 struct { 283 uint64_t _unused_dfsr; 284 uint64_t dfsr_ns; 285 uint64_t hsr; 286 uint64_t dfsr_s; 287 }; 288 uint64_t esr_el[4]; 289 }; 290 uint32_t c6_region[8]; /* MPU base/size registers. */ 291 union { /* Fault address registers. */ 292 struct { 293 uint64_t _unused_far0; 294 #ifdef HOST_WORDS_BIGENDIAN 295 uint32_t ifar_ns; 296 uint32_t dfar_ns; 297 uint32_t ifar_s; 298 uint32_t dfar_s; 299 #else 300 uint32_t dfar_ns; 301 uint32_t ifar_ns; 302 uint32_t dfar_s; 303 uint32_t ifar_s; 304 #endif 305 uint64_t _unused_far3; 306 }; 307 uint64_t far_el[4]; 308 }; 309 uint64_t hpfar_el2; 310 uint64_t hstr_el2; 311 union { /* Translation result. */ 312 struct { 313 uint64_t _unused_par_0; 314 uint64_t par_ns; 315 uint64_t _unused_par_1; 316 uint64_t par_s; 317 }; 318 uint64_t par_el[4]; 319 }; 320 321 uint32_t c9_insn; /* Cache lockdown registers. */ 322 uint32_t c9_data; 323 uint64_t c9_pmcr; /* performance monitor control register */ 324 uint64_t c9_pmcnten; /* perf monitor counter enables */ 325 uint32_t c9_pmovsr; /* perf monitor overflow status */ 326 uint32_t c9_pmuserenr; /* perf monitor user enable */ 327 uint64_t c9_pmselr; /* perf monitor counter selection register */ 328 uint64_t c9_pminten; /* perf monitor interrupt enables */ 329 union { /* Memory attribute redirection */ 330 struct { 331 #ifdef HOST_WORDS_BIGENDIAN 332 uint64_t _unused_mair_0; 333 uint32_t mair1_ns; 334 uint32_t mair0_ns; 335 uint64_t _unused_mair_1; 336 uint32_t mair1_s; 337 uint32_t mair0_s; 338 #else 339 uint64_t _unused_mair_0; 340 uint32_t mair0_ns; 341 uint32_t mair1_ns; 342 uint64_t _unused_mair_1; 343 uint32_t mair0_s; 344 uint32_t mair1_s; 345 #endif 346 }; 347 uint64_t mair_el[4]; 348 }; 349 union { /* vector base address register */ 350 struct { 351 uint64_t _unused_vbar; 352 uint64_t vbar_ns; 353 uint64_t hvbar; 354 uint64_t vbar_s; 355 }; 356 uint64_t vbar_el[4]; 357 }; 358 uint32_t mvbar; /* (monitor) vector base address register */ 359 struct { /* FCSE PID. */ 360 uint32_t fcseidr_ns; 361 uint32_t fcseidr_s; 362 }; 363 union { /* Context ID. */ 364 struct { 365 uint64_t _unused_contextidr_0; 366 uint64_t contextidr_ns; 367 uint64_t _unused_contextidr_1; 368 uint64_t contextidr_s; 369 }; 370 uint64_t contextidr_el[4]; 371 }; 372 union { /* User RW Thread register. */ 373 struct { 374 uint64_t tpidrurw_ns; 375 uint64_t tpidrprw_ns; 376 uint64_t htpidr; 377 uint64_t _tpidr_el3; 378 }; 379 uint64_t tpidr_el[4]; 380 }; 381 /* The secure banks of these registers don't map anywhere */ 382 uint64_t tpidrurw_s; 383 uint64_t tpidrprw_s; 384 uint64_t tpidruro_s; 385 386 union { /* User RO Thread register. */ 387 uint64_t tpidruro_ns; 388 uint64_t tpidrro_el[1]; 389 }; 390 uint64_t c14_cntfrq; /* Counter Frequency register */ 391 uint64_t c14_cntkctl; /* Timer Control register */ 392 uint32_t cnthctl_el2; /* Counter/Timer Hyp Control register */ 393 uint64_t cntvoff_el2; /* Counter Virtual Offset register */ 394 ARMGenericTimer c14_timer[NUM_GTIMERS]; 395 uint32_t c15_cpar; /* XScale Coprocessor Access Register */ 396 uint32_t c15_ticonfig; /* TI925T configuration byte. */ 397 uint32_t c15_i_max; /* Maximum D-cache dirty line index. */ 398 uint32_t c15_i_min; /* Minimum D-cache dirty line index. */ 399 uint32_t c15_threadid; /* TI debugger thread-ID. */ 400 uint32_t c15_config_base_address; /* SCU base address. */ 401 uint32_t c15_diagnostic; /* diagnostic register */ 402 uint32_t c15_power_diagnostic; 403 uint32_t c15_power_control; /* power control */ 404 uint64_t dbgbvr[16]; /* breakpoint value registers */ 405 uint64_t dbgbcr[16]; /* breakpoint control registers */ 406 uint64_t dbgwvr[16]; /* watchpoint value registers */ 407 uint64_t dbgwcr[16]; /* watchpoint control registers */ 408 uint64_t mdscr_el1; 409 uint64_t oslsr_el1; /* OS Lock Status */ 410 uint64_t mdcr_el2; 411 uint64_t mdcr_el3; 412 /* If the counter is enabled, this stores the last time the counter 413 * was reset. Otherwise it stores the counter value 414 */ 415 uint64_t c15_ccnt; 416 uint64_t pmccfiltr_el0; /* Performance Monitor Filter Register */ 417 uint64_t vpidr_el2; /* Virtualization Processor ID Register */ 418 uint64_t vmpidr_el2; /* Virtualization Multiprocessor ID Register */ 419 } cp15; 420 421 struct { 422 uint32_t other_sp; 423 uint32_t vecbase[2]; 424 uint32_t basepri[2]; 425 uint32_t control[2]; 426 uint32_t ccr[2]; /* Configuration and Control */ 427 uint32_t cfsr[2]; /* Configurable Fault Status */ 428 uint32_t hfsr; /* HardFault Status */ 429 uint32_t dfsr; /* Debug Fault Status Register */ 430 uint32_t mmfar[2]; /* MemManage Fault Address */ 431 uint32_t bfar; /* BusFault Address */ 432 unsigned mpu_ctrl[2]; /* MPU_CTRL */ 433 int exception; 434 uint32_t primask[2]; 435 uint32_t faultmask[2]; 436 uint32_t secure; /* Is CPU in Secure state? (not guest visible) */ 437 } v7m; 438 439 /* Information associated with an exception about to be taken: 440 * code which raises an exception must set cs->exception_index and 441 * the relevant parts of this structure; the cpu_do_interrupt function 442 * will then set the guest-visible registers as part of the exception 443 * entry process. 444 */ 445 struct { 446 uint32_t syndrome; /* AArch64 format syndrome register */ 447 uint32_t fsr; /* AArch32 format fault status register info */ 448 uint64_t vaddress; /* virtual addr associated with exception, if any */ 449 uint32_t target_el; /* EL the exception should be targeted for */ 450 /* If we implement EL2 we will also need to store information 451 * about the intermediate physical address for stage 2 faults. 452 */ 453 } exception; 454 455 /* Thumb-2 EE state. */ 456 uint32_t teecr; 457 uint32_t teehbr; 458 459 /* VFP coprocessor state. */ 460 struct { 461 /* VFP/Neon register state. Note that the mapping between S, D and Q 462 * views of the register bank differs between AArch64 and AArch32: 463 * In AArch32: 464 * Qn = regs[2n+1]:regs[2n] 465 * Dn = regs[n] 466 * Sn = regs[n/2] bits 31..0 for even n, and bits 63..32 for odd n 467 * (and regs[32] to regs[63] are inaccessible) 468 * In AArch64: 469 * Qn = regs[2n+1]:regs[2n] 470 * Dn = regs[2n] 471 * Sn = regs[2n] bits 31..0 472 * This corresponds to the architecturally defined mapping between 473 * the two execution states, and means we do not need to explicitly 474 * map these registers when changing states. 475 */ 476 float64 regs[64]; 477 478 uint32_t xregs[16]; 479 /* We store these fpcsr fields separately for convenience. */ 480 int vec_len; 481 int vec_stride; 482 483 /* scratch space when Tn are not sufficient. */ 484 uint32_t scratch[8]; 485 486 /* fp_status is the "normal" fp status. standard_fp_status retains 487 * values corresponding to the ARM "Standard FPSCR Value", ie 488 * default-NaN, flush-to-zero, round-to-nearest and is used by 489 * any operations (generally Neon) which the architecture defines 490 * as controlled by the standard FPSCR value rather than the FPSCR. 491 * 492 * To avoid having to transfer exception bits around, we simply 493 * say that the FPSCR cumulative exception flags are the logical 494 * OR of the flags in the two fp statuses. This relies on the 495 * only thing which needs to read the exception flags being 496 * an explicit FPSCR read. 497 */ 498 float_status fp_status; 499 float_status standard_fp_status; 500 } vfp; 501 uint64_t exclusive_addr; 502 uint64_t exclusive_val; 503 uint64_t exclusive_high; 504 505 /* iwMMXt coprocessor state. */ 506 struct { 507 uint64_t regs[16]; 508 uint64_t val; 509 510 uint32_t cregs[16]; 511 } iwmmxt; 512 513 #if defined(CONFIG_USER_ONLY) 514 /* For usermode syscall translation. */ 515 int eabi; 516 #endif 517 518 struct CPUBreakpoint *cpu_breakpoint[16]; 519 struct CPUWatchpoint *cpu_watchpoint[16]; 520 521 /* Fields up to this point are cleared by a CPU reset */ 522 struct {} end_reset_fields; 523 524 CPU_COMMON 525 526 /* Fields after CPU_COMMON are preserved across CPU reset. */ 527 528 /* Internal CPU feature flags. */ 529 uint64_t features; 530 531 /* PMSAv7 MPU */ 532 struct { 533 uint32_t *drbar; 534 uint32_t *drsr; 535 uint32_t *dracr; 536 uint32_t rnr[2]; 537 } pmsav7; 538 539 /* PMSAv8 MPU */ 540 struct { 541 /* The PMSAv8 implementation also shares some PMSAv7 config 542 * and state: 543 * pmsav7.rnr (region number register) 544 * pmsav7_dregion (number of configured regions) 545 */ 546 uint32_t *rbar[2]; 547 uint32_t *rlar[2]; 548 uint32_t mair0[2]; 549 uint32_t mair1[2]; 550 } pmsav8; 551 552 void *nvic; 553 const struct arm_boot_info *boot_info; 554 /* Store GICv3CPUState to access from this struct */ 555 void *gicv3state; 556 } CPUARMState; 557 558 /** 559 * ARMELChangeHook: 560 * type of a function which can be registered via arm_register_el_change_hook() 561 * to get callbacks when the CPU changes its exception level or mode. 562 */ 563 typedef void ARMELChangeHook(ARMCPU *cpu, void *opaque); 564 565 566 /* These values map onto the return values for 567 * QEMU_PSCI_0_2_FN_AFFINITY_INFO */ 568 typedef enum ARMPSCIState { 569 PSCI_ON = 0, 570 PSCI_OFF = 1, 571 PSCI_ON_PENDING = 2 572 } ARMPSCIState; 573 574 /** 575 * ARMCPU: 576 * @env: #CPUARMState 577 * 578 * An ARM CPU core. 579 */ 580 struct ARMCPU { 581 /*< private >*/ 582 CPUState parent_obj; 583 /*< public >*/ 584 585 CPUARMState env; 586 587 /* Coprocessor information */ 588 GHashTable *cp_regs; 589 /* For marshalling (mostly coprocessor) register state between the 590 * kernel and QEMU (for KVM) and between two QEMUs (for migration), 591 * we use these arrays. 592 */ 593 /* List of register indexes managed via these arrays; (full KVM style 594 * 64 bit indexes, not CPRegInfo 32 bit indexes) 595 */ 596 uint64_t *cpreg_indexes; 597 /* Values of the registers (cpreg_indexes[i]'s value is cpreg_values[i]) */ 598 uint64_t *cpreg_values; 599 /* Length of the indexes, values, reset_values arrays */ 600 int32_t cpreg_array_len; 601 /* These are used only for migration: incoming data arrives in 602 * these fields and is sanity checked in post_load before copying 603 * to the working data structures above. 604 */ 605 uint64_t *cpreg_vmstate_indexes; 606 uint64_t *cpreg_vmstate_values; 607 int32_t cpreg_vmstate_array_len; 608 609 /* Timers used by the generic (architected) timer */ 610 QEMUTimer *gt_timer[NUM_GTIMERS]; 611 /* GPIO outputs for generic timer */ 612 qemu_irq gt_timer_outputs[NUM_GTIMERS]; 613 /* GPIO output for GICv3 maintenance interrupt signal */ 614 qemu_irq gicv3_maintenance_interrupt; 615 /* GPIO output for the PMU interrupt */ 616 qemu_irq pmu_interrupt; 617 618 /* MemoryRegion to use for secure physical accesses */ 619 MemoryRegion *secure_memory; 620 621 /* 'compatible' string for this CPU for Linux device trees */ 622 const char *dtb_compatible; 623 624 /* PSCI version for this CPU 625 * Bits[31:16] = Major Version 626 * Bits[15:0] = Minor Version 627 */ 628 uint32_t psci_version; 629 630 /* Should CPU start in PSCI powered-off state? */ 631 bool start_powered_off; 632 633 /* Current power state, access guarded by BQL */ 634 ARMPSCIState power_state; 635 636 /* CPU has virtualization extension */ 637 bool has_el2; 638 /* CPU has security extension */ 639 bool has_el3; 640 /* CPU has PMU (Performance Monitor Unit) */ 641 bool has_pmu; 642 643 /* CPU has memory protection unit */ 644 bool has_mpu; 645 /* PMSAv7 MPU number of supported regions */ 646 uint32_t pmsav7_dregion; 647 648 /* PSCI conduit used to invoke PSCI methods 649 * 0 - disabled, 1 - smc, 2 - hvc 650 */ 651 uint32_t psci_conduit; 652 653 /* [QEMU_]KVM_ARM_TARGET_* constant for this CPU, or 654 * QEMU_KVM_ARM_TARGET_NONE if the kernel doesn't support this CPU type. 655 */ 656 uint32_t kvm_target; 657 658 /* KVM init features for this CPU */ 659 uint32_t kvm_init_features[7]; 660 661 /* Uniprocessor system with MP extensions */ 662 bool mp_is_up; 663 664 /* The instance init functions for implementation-specific subclasses 665 * set these fields to specify the implementation-dependent values of 666 * various constant registers and reset values of non-constant 667 * registers. 668 * Some of these might become QOM properties eventually. 669 * Field names match the official register names as defined in the 670 * ARMv7AR ARM Architecture Reference Manual. A reset_ prefix 671 * is used for reset values of non-constant registers; no reset_ 672 * prefix means a constant register. 673 */ 674 uint32_t midr; 675 uint32_t revidr; 676 uint32_t reset_fpsid; 677 uint32_t mvfr0; 678 uint32_t mvfr1; 679 uint32_t mvfr2; 680 uint32_t ctr; 681 uint32_t reset_sctlr; 682 uint32_t id_pfr0; 683 uint32_t id_pfr1; 684 uint32_t id_dfr0; 685 uint32_t pmceid0; 686 uint32_t pmceid1; 687 uint32_t id_afr0; 688 uint32_t id_mmfr0; 689 uint32_t id_mmfr1; 690 uint32_t id_mmfr2; 691 uint32_t id_mmfr3; 692 uint32_t id_mmfr4; 693 uint32_t id_isar0; 694 uint32_t id_isar1; 695 uint32_t id_isar2; 696 uint32_t id_isar3; 697 uint32_t id_isar4; 698 uint32_t id_isar5; 699 uint64_t id_aa64pfr0; 700 uint64_t id_aa64pfr1; 701 uint64_t id_aa64dfr0; 702 uint64_t id_aa64dfr1; 703 uint64_t id_aa64afr0; 704 uint64_t id_aa64afr1; 705 uint64_t id_aa64isar0; 706 uint64_t id_aa64isar1; 707 uint64_t id_aa64mmfr0; 708 uint64_t id_aa64mmfr1; 709 uint32_t dbgdidr; 710 uint32_t clidr; 711 uint64_t mp_affinity; /* MP ID without feature bits */ 712 /* The elements of this array are the CCSIDR values for each cache, 713 * in the order L1DCache, L1ICache, L2DCache, L2ICache, etc. 714 */ 715 uint32_t ccsidr[16]; 716 uint64_t reset_cbar; 717 uint32_t reset_auxcr; 718 bool reset_hivecs; 719 /* DCZ blocksize, in log_2(words), ie low 4 bits of DCZID_EL0 */ 720 uint32_t dcz_blocksize; 721 uint64_t rvbar; 722 723 /* Configurable aspects of GIC cpu interface (which is part of the CPU) */ 724 int gic_num_lrs; /* number of list registers */ 725 int gic_vpribits; /* number of virtual priority bits */ 726 int gic_vprebits; /* number of virtual preemption bits */ 727 728 /* Whether the cfgend input is high (i.e. this CPU should reset into 729 * big-endian mode). This setting isn't used directly: instead it modifies 730 * the reset_sctlr value to have SCTLR_B or SCTLR_EE set, depending on the 731 * architecture version. 732 */ 733 bool cfgend; 734 735 ARMELChangeHook *el_change_hook; 736 void *el_change_hook_opaque; 737 738 int32_t node_id; /* NUMA node this CPU belongs to */ 739 740 /* Used to synchronize KVM and QEMU in-kernel device levels */ 741 uint8_t device_irq_level; 742 }; 743 744 static inline ARMCPU *arm_env_get_cpu(CPUARMState *env) 745 { 746 return container_of(env, ARMCPU, env); 747 } 748 749 uint64_t arm_cpu_mp_affinity(int idx, uint8_t clustersz); 750 751 #define ENV_GET_CPU(e) CPU(arm_env_get_cpu(e)) 752 753 #define ENV_OFFSET offsetof(ARMCPU, env) 754 755 #ifndef CONFIG_USER_ONLY 756 extern const struct VMStateDescription vmstate_arm_cpu; 757 #endif 758 759 void arm_cpu_do_interrupt(CPUState *cpu); 760 void arm_v7m_cpu_do_interrupt(CPUState *cpu); 761 bool arm_cpu_exec_interrupt(CPUState *cpu, int int_req); 762 763 void arm_cpu_dump_state(CPUState *cs, FILE *f, fprintf_function cpu_fprintf, 764 int flags); 765 766 hwaddr arm_cpu_get_phys_page_attrs_debug(CPUState *cpu, vaddr addr, 767 MemTxAttrs *attrs); 768 769 int arm_cpu_gdb_read_register(CPUState *cpu, uint8_t *buf, int reg); 770 int arm_cpu_gdb_write_register(CPUState *cpu, uint8_t *buf, int reg); 771 772 int arm_cpu_write_elf64_note(WriteCoreDumpFunction f, CPUState *cs, 773 int cpuid, void *opaque); 774 int arm_cpu_write_elf32_note(WriteCoreDumpFunction f, CPUState *cs, 775 int cpuid, void *opaque); 776 777 #ifdef TARGET_AARCH64 778 int aarch64_cpu_gdb_read_register(CPUState *cpu, uint8_t *buf, int reg); 779 int aarch64_cpu_gdb_write_register(CPUState *cpu, uint8_t *buf, int reg); 780 #endif 781 782 target_ulong do_arm_semihosting(CPUARMState *env); 783 void aarch64_sync_32_to_64(CPUARMState *env); 784 void aarch64_sync_64_to_32(CPUARMState *env); 785 786 static inline bool is_a64(CPUARMState *env) 787 { 788 return env->aarch64; 789 } 790 791 /* you can call this signal handler from your SIGBUS and SIGSEGV 792 signal handlers to inform the virtual CPU of exceptions. non zero 793 is returned if the signal was handled by the virtual CPU. */ 794 int cpu_arm_signal_handler(int host_signum, void *pinfo, 795 void *puc); 796 797 /** 798 * pmccntr_sync 799 * @env: CPUARMState 800 * 801 * Synchronises the counter in the PMCCNTR. This must always be called twice, 802 * once before any action that might affect the timer and again afterwards. 803 * The function is used to swap the state of the register if required. 804 * This only happens when not in user mode (!CONFIG_USER_ONLY) 805 */ 806 void pmccntr_sync(CPUARMState *env); 807 808 /* SCTLR bit meanings. Several bits have been reused in newer 809 * versions of the architecture; in that case we define constants 810 * for both old and new bit meanings. Code which tests against those 811 * bits should probably check or otherwise arrange that the CPU 812 * is the architectural version it expects. 813 */ 814 #define SCTLR_M (1U << 0) 815 #define SCTLR_A (1U << 1) 816 #define SCTLR_C (1U << 2) 817 #define SCTLR_W (1U << 3) /* up to v6; RAO in v7 */ 818 #define SCTLR_SA (1U << 3) 819 #define SCTLR_P (1U << 4) /* up to v5; RAO in v6 and v7 */ 820 #define SCTLR_SA0 (1U << 4) /* v8 onward, AArch64 only */ 821 #define SCTLR_D (1U << 5) /* up to v5; RAO in v6 */ 822 #define SCTLR_CP15BEN (1U << 5) /* v7 onward */ 823 #define SCTLR_L (1U << 6) /* up to v5; RAO in v6 and v7; RAZ in v8 */ 824 #define SCTLR_B (1U << 7) /* up to v6; RAZ in v7 */ 825 #define SCTLR_ITD (1U << 7) /* v8 onward */ 826 #define SCTLR_S (1U << 8) /* up to v6; RAZ in v7 */ 827 #define SCTLR_SED (1U << 8) /* v8 onward */ 828 #define SCTLR_R (1U << 9) /* up to v6; RAZ in v7 */ 829 #define SCTLR_UMA (1U << 9) /* v8 onward, AArch64 only */ 830 #define SCTLR_F (1U << 10) /* up to v6 */ 831 #define SCTLR_SW (1U << 10) /* v7 onward */ 832 #define SCTLR_Z (1U << 11) 833 #define SCTLR_I (1U << 12) 834 #define SCTLR_V (1U << 13) 835 #define SCTLR_RR (1U << 14) /* up to v7 */ 836 #define SCTLR_DZE (1U << 14) /* v8 onward, AArch64 only */ 837 #define SCTLR_L4 (1U << 15) /* up to v6; RAZ in v7 */ 838 #define SCTLR_UCT (1U << 15) /* v8 onward, AArch64 only */ 839 #define SCTLR_DT (1U << 16) /* up to ??, RAO in v6 and v7 */ 840 #define SCTLR_nTWI (1U << 16) /* v8 onward */ 841 #define SCTLR_HA (1U << 17) 842 #define SCTLR_BR (1U << 17) /* PMSA only */ 843 #define SCTLR_IT (1U << 18) /* up to ??, RAO in v6 and v7 */ 844 #define SCTLR_nTWE (1U << 18) /* v8 onward */ 845 #define SCTLR_WXN (1U << 19) 846 #define SCTLR_ST (1U << 20) /* up to ??, RAZ in v6 */ 847 #define SCTLR_UWXN (1U << 20) /* v7 onward */ 848 #define SCTLR_FI (1U << 21) 849 #define SCTLR_U (1U << 22) 850 #define SCTLR_XP (1U << 23) /* up to v6; v7 onward RAO */ 851 #define SCTLR_VE (1U << 24) /* up to v7 */ 852 #define SCTLR_E0E (1U << 24) /* v8 onward, AArch64 only */ 853 #define SCTLR_EE (1U << 25) 854 #define SCTLR_L2 (1U << 26) /* up to v6, RAZ in v7 */ 855 #define SCTLR_UCI (1U << 26) /* v8 onward, AArch64 only */ 856 #define SCTLR_NMFI (1U << 27) 857 #define SCTLR_TRE (1U << 28) 858 #define SCTLR_AFE (1U << 29) 859 #define SCTLR_TE (1U << 30) 860 861 #define CPTR_TCPAC (1U << 31) 862 #define CPTR_TTA (1U << 20) 863 #define CPTR_TFP (1U << 10) 864 865 #define MDCR_EPMAD (1U << 21) 866 #define MDCR_EDAD (1U << 20) 867 #define MDCR_SPME (1U << 17) 868 #define MDCR_SDD (1U << 16) 869 #define MDCR_SPD (3U << 14) 870 #define MDCR_TDRA (1U << 11) 871 #define MDCR_TDOSA (1U << 10) 872 #define MDCR_TDA (1U << 9) 873 #define MDCR_TDE (1U << 8) 874 #define MDCR_HPME (1U << 7) 875 #define MDCR_TPM (1U << 6) 876 #define MDCR_TPMCR (1U << 5) 877 878 /* Not all of the MDCR_EL3 bits are present in the 32-bit SDCR */ 879 #define SDCR_VALID_MASK (MDCR_EPMAD | MDCR_EDAD | MDCR_SPME | MDCR_SPD) 880 881 #define CPSR_M (0x1fU) 882 #define CPSR_T (1U << 5) 883 #define CPSR_F (1U << 6) 884 #define CPSR_I (1U << 7) 885 #define CPSR_A (1U << 8) 886 #define CPSR_E (1U << 9) 887 #define CPSR_IT_2_7 (0xfc00U) 888 #define CPSR_GE (0xfU << 16) 889 #define CPSR_IL (1U << 20) 890 /* Note that the RESERVED bits include bit 21, which is PSTATE_SS in 891 * an AArch64 SPSR but RES0 in AArch32 SPSR and CPSR. In QEMU we use 892 * env->uncached_cpsr bit 21 to store PSTATE.SS when executing in AArch32, 893 * where it is live state but not accessible to the AArch32 code. 894 */ 895 #define CPSR_RESERVED (0x7U << 21) 896 #define CPSR_J (1U << 24) 897 #define CPSR_IT_0_1 (3U << 25) 898 #define CPSR_Q (1U << 27) 899 #define CPSR_V (1U << 28) 900 #define CPSR_C (1U << 29) 901 #define CPSR_Z (1U << 30) 902 #define CPSR_N (1U << 31) 903 #define CPSR_NZCV (CPSR_N | CPSR_Z | CPSR_C | CPSR_V) 904 #define CPSR_AIF (CPSR_A | CPSR_I | CPSR_F) 905 906 #define CPSR_IT (CPSR_IT_0_1 | CPSR_IT_2_7) 907 #define CACHED_CPSR_BITS (CPSR_T | CPSR_AIF | CPSR_GE | CPSR_IT | CPSR_Q \ 908 | CPSR_NZCV) 909 /* Bits writable in user mode. */ 910 #define CPSR_USER (CPSR_NZCV | CPSR_Q | CPSR_GE) 911 /* Execution state bits. MRS read as zero, MSR writes ignored. */ 912 #define CPSR_EXEC (CPSR_T | CPSR_IT | CPSR_J | CPSR_IL) 913 /* Mask of bits which may be set by exception return copying them from SPSR */ 914 #define CPSR_ERET_MASK (~CPSR_RESERVED) 915 916 /* Bit definitions for M profile XPSR. Most are the same as CPSR. */ 917 #define XPSR_EXCP 0x1ffU 918 #define XPSR_SPREALIGN (1U << 9) /* Only set in exception stack frames */ 919 #define XPSR_IT_2_7 CPSR_IT_2_7 920 #define XPSR_GE CPSR_GE 921 #define XPSR_SFPA (1U << 20) /* Only set in exception stack frames */ 922 #define XPSR_T (1U << 24) /* Not the same as CPSR_T ! */ 923 #define XPSR_IT_0_1 CPSR_IT_0_1 924 #define XPSR_Q CPSR_Q 925 #define XPSR_V CPSR_V 926 #define XPSR_C CPSR_C 927 #define XPSR_Z CPSR_Z 928 #define XPSR_N CPSR_N 929 #define XPSR_NZCV CPSR_NZCV 930 #define XPSR_IT CPSR_IT 931 932 #define TTBCR_N (7U << 0) /* TTBCR.EAE==0 */ 933 #define TTBCR_T0SZ (7U << 0) /* TTBCR.EAE==1 */ 934 #define TTBCR_PD0 (1U << 4) 935 #define TTBCR_PD1 (1U << 5) 936 #define TTBCR_EPD0 (1U << 7) 937 #define TTBCR_IRGN0 (3U << 8) 938 #define TTBCR_ORGN0 (3U << 10) 939 #define TTBCR_SH0 (3U << 12) 940 #define TTBCR_T1SZ (3U << 16) 941 #define TTBCR_A1 (1U << 22) 942 #define TTBCR_EPD1 (1U << 23) 943 #define TTBCR_IRGN1 (3U << 24) 944 #define TTBCR_ORGN1 (3U << 26) 945 #define TTBCR_SH1 (1U << 28) 946 #define TTBCR_EAE (1U << 31) 947 948 /* Bit definitions for ARMv8 SPSR (PSTATE) format. 949 * Only these are valid when in AArch64 mode; in 950 * AArch32 mode SPSRs are basically CPSR-format. 951 */ 952 #define PSTATE_SP (1U) 953 #define PSTATE_M (0xFU) 954 #define PSTATE_nRW (1U << 4) 955 #define PSTATE_F (1U << 6) 956 #define PSTATE_I (1U << 7) 957 #define PSTATE_A (1U << 8) 958 #define PSTATE_D (1U << 9) 959 #define PSTATE_IL (1U << 20) 960 #define PSTATE_SS (1U << 21) 961 #define PSTATE_V (1U << 28) 962 #define PSTATE_C (1U << 29) 963 #define PSTATE_Z (1U << 30) 964 #define PSTATE_N (1U << 31) 965 #define PSTATE_NZCV (PSTATE_N | PSTATE_Z | PSTATE_C | PSTATE_V) 966 #define PSTATE_DAIF (PSTATE_D | PSTATE_A | PSTATE_I | PSTATE_F) 967 #define CACHED_PSTATE_BITS (PSTATE_NZCV | PSTATE_DAIF) 968 /* Mode values for AArch64 */ 969 #define PSTATE_MODE_EL3h 13 970 #define PSTATE_MODE_EL3t 12 971 #define PSTATE_MODE_EL2h 9 972 #define PSTATE_MODE_EL2t 8 973 #define PSTATE_MODE_EL1h 5 974 #define PSTATE_MODE_EL1t 4 975 #define PSTATE_MODE_EL0t 0 976 977 /* Map EL and handler into a PSTATE_MODE. */ 978 static inline unsigned int aarch64_pstate_mode(unsigned int el, bool handler) 979 { 980 return (el << 2) | handler; 981 } 982 983 /* Return the current PSTATE value. For the moment we don't support 32<->64 bit 984 * interprocessing, so we don't attempt to sync with the cpsr state used by 985 * the 32 bit decoder. 986 */ 987 static inline uint32_t pstate_read(CPUARMState *env) 988 { 989 int ZF; 990 991 ZF = (env->ZF == 0); 992 return (env->NF & 0x80000000) | (ZF << 30) 993 | (env->CF << 29) | ((env->VF & 0x80000000) >> 3) 994 | env->pstate | env->daif; 995 } 996 997 static inline void pstate_write(CPUARMState *env, uint32_t val) 998 { 999 env->ZF = (~val) & PSTATE_Z; 1000 env->NF = val; 1001 env->CF = (val >> 29) & 1; 1002 env->VF = (val << 3) & 0x80000000; 1003 env->daif = val & PSTATE_DAIF; 1004 env->pstate = val & ~CACHED_PSTATE_BITS; 1005 } 1006 1007 /* Return the current CPSR value. */ 1008 uint32_t cpsr_read(CPUARMState *env); 1009 1010 typedef enum CPSRWriteType { 1011 CPSRWriteByInstr = 0, /* from guest MSR or CPS */ 1012 CPSRWriteExceptionReturn = 1, /* from guest exception return insn */ 1013 CPSRWriteRaw = 2, /* trust values, do not switch reg banks */ 1014 CPSRWriteByGDBStub = 3, /* from the GDB stub */ 1015 } CPSRWriteType; 1016 1017 /* Set the CPSR. Note that some bits of mask must be all-set or all-clear.*/ 1018 void cpsr_write(CPUARMState *env, uint32_t val, uint32_t mask, 1019 CPSRWriteType write_type); 1020 1021 /* Return the current xPSR value. */ 1022 static inline uint32_t xpsr_read(CPUARMState *env) 1023 { 1024 int ZF; 1025 ZF = (env->ZF == 0); 1026 return (env->NF & 0x80000000) | (ZF << 30) 1027 | (env->CF << 29) | ((env->VF & 0x80000000) >> 3) | (env->QF << 27) 1028 | (env->thumb << 24) | ((env->condexec_bits & 3) << 25) 1029 | ((env->condexec_bits & 0xfc) << 8) 1030 | env->v7m.exception; 1031 } 1032 1033 /* Set the xPSR. Note that some bits of mask must be all-set or all-clear. */ 1034 static inline void xpsr_write(CPUARMState *env, uint32_t val, uint32_t mask) 1035 { 1036 if (mask & XPSR_NZCV) { 1037 env->ZF = (~val) & XPSR_Z; 1038 env->NF = val; 1039 env->CF = (val >> 29) & 1; 1040 env->VF = (val << 3) & 0x80000000; 1041 } 1042 if (mask & XPSR_Q) { 1043 env->QF = ((val & XPSR_Q) != 0); 1044 } 1045 if (mask & XPSR_T) { 1046 env->thumb = ((val & XPSR_T) != 0); 1047 } 1048 if (mask & XPSR_IT_0_1) { 1049 env->condexec_bits &= ~3; 1050 env->condexec_bits |= (val >> 25) & 3; 1051 } 1052 if (mask & XPSR_IT_2_7) { 1053 env->condexec_bits &= 3; 1054 env->condexec_bits |= (val >> 8) & 0xfc; 1055 } 1056 if (mask & XPSR_EXCP) { 1057 env->v7m.exception = val & XPSR_EXCP; 1058 } 1059 } 1060 1061 #define HCR_VM (1ULL << 0) 1062 #define HCR_SWIO (1ULL << 1) 1063 #define HCR_PTW (1ULL << 2) 1064 #define HCR_FMO (1ULL << 3) 1065 #define HCR_IMO (1ULL << 4) 1066 #define HCR_AMO (1ULL << 5) 1067 #define HCR_VF (1ULL << 6) 1068 #define HCR_VI (1ULL << 7) 1069 #define HCR_VSE (1ULL << 8) 1070 #define HCR_FB (1ULL << 9) 1071 #define HCR_BSU_MASK (3ULL << 10) 1072 #define HCR_DC (1ULL << 12) 1073 #define HCR_TWI (1ULL << 13) 1074 #define HCR_TWE (1ULL << 14) 1075 #define HCR_TID0 (1ULL << 15) 1076 #define HCR_TID1 (1ULL << 16) 1077 #define HCR_TID2 (1ULL << 17) 1078 #define HCR_TID3 (1ULL << 18) 1079 #define HCR_TSC (1ULL << 19) 1080 #define HCR_TIDCP (1ULL << 20) 1081 #define HCR_TACR (1ULL << 21) 1082 #define HCR_TSW (1ULL << 22) 1083 #define HCR_TPC (1ULL << 23) 1084 #define HCR_TPU (1ULL << 24) 1085 #define HCR_TTLB (1ULL << 25) 1086 #define HCR_TVM (1ULL << 26) 1087 #define HCR_TGE (1ULL << 27) 1088 #define HCR_TDZ (1ULL << 28) 1089 #define HCR_HCD (1ULL << 29) 1090 #define HCR_TRVM (1ULL << 30) 1091 #define HCR_RW (1ULL << 31) 1092 #define HCR_CD (1ULL << 32) 1093 #define HCR_ID (1ULL << 33) 1094 #define HCR_MASK ((1ULL << 34) - 1) 1095 1096 #define SCR_NS (1U << 0) 1097 #define SCR_IRQ (1U << 1) 1098 #define SCR_FIQ (1U << 2) 1099 #define SCR_EA (1U << 3) 1100 #define SCR_FW (1U << 4) 1101 #define SCR_AW (1U << 5) 1102 #define SCR_NET (1U << 6) 1103 #define SCR_SMD (1U << 7) 1104 #define SCR_HCE (1U << 8) 1105 #define SCR_SIF (1U << 9) 1106 #define SCR_RW (1U << 10) 1107 #define SCR_ST (1U << 11) 1108 #define SCR_TWI (1U << 12) 1109 #define SCR_TWE (1U << 13) 1110 #define SCR_AARCH32_MASK (0x3fff & ~(SCR_RW | SCR_ST)) 1111 #define SCR_AARCH64_MASK (0x3fff & ~SCR_NET) 1112 1113 /* Return the current FPSCR value. */ 1114 uint32_t vfp_get_fpscr(CPUARMState *env); 1115 void vfp_set_fpscr(CPUARMState *env, uint32_t val); 1116 1117 /* For A64 the FPSCR is split into two logically distinct registers, 1118 * FPCR and FPSR. However since they still use non-overlapping bits 1119 * we store the underlying state in fpscr and just mask on read/write. 1120 */ 1121 #define FPSR_MASK 0xf800009f 1122 #define FPCR_MASK 0x07f79f00 1123 static inline uint32_t vfp_get_fpsr(CPUARMState *env) 1124 { 1125 return vfp_get_fpscr(env) & FPSR_MASK; 1126 } 1127 1128 static inline void vfp_set_fpsr(CPUARMState *env, uint32_t val) 1129 { 1130 uint32_t new_fpscr = (vfp_get_fpscr(env) & ~FPSR_MASK) | (val & FPSR_MASK); 1131 vfp_set_fpscr(env, new_fpscr); 1132 } 1133 1134 static inline uint32_t vfp_get_fpcr(CPUARMState *env) 1135 { 1136 return vfp_get_fpscr(env) & FPCR_MASK; 1137 } 1138 1139 static inline void vfp_set_fpcr(CPUARMState *env, uint32_t val) 1140 { 1141 uint32_t new_fpscr = (vfp_get_fpscr(env) & ~FPCR_MASK) | (val & FPCR_MASK); 1142 vfp_set_fpscr(env, new_fpscr); 1143 } 1144 1145 enum arm_cpu_mode { 1146 ARM_CPU_MODE_USR = 0x10, 1147 ARM_CPU_MODE_FIQ = 0x11, 1148 ARM_CPU_MODE_IRQ = 0x12, 1149 ARM_CPU_MODE_SVC = 0x13, 1150 ARM_CPU_MODE_MON = 0x16, 1151 ARM_CPU_MODE_ABT = 0x17, 1152 ARM_CPU_MODE_HYP = 0x1a, 1153 ARM_CPU_MODE_UND = 0x1b, 1154 ARM_CPU_MODE_SYS = 0x1f 1155 }; 1156 1157 /* VFP system registers. */ 1158 #define ARM_VFP_FPSID 0 1159 #define ARM_VFP_FPSCR 1 1160 #define ARM_VFP_MVFR2 5 1161 #define ARM_VFP_MVFR1 6 1162 #define ARM_VFP_MVFR0 7 1163 #define ARM_VFP_FPEXC 8 1164 #define ARM_VFP_FPINST 9 1165 #define ARM_VFP_FPINST2 10 1166 1167 /* iwMMXt coprocessor control registers. */ 1168 #define ARM_IWMMXT_wCID 0 1169 #define ARM_IWMMXT_wCon 1 1170 #define ARM_IWMMXT_wCSSF 2 1171 #define ARM_IWMMXT_wCASF 3 1172 #define ARM_IWMMXT_wCGR0 8 1173 #define ARM_IWMMXT_wCGR1 9 1174 #define ARM_IWMMXT_wCGR2 10 1175 #define ARM_IWMMXT_wCGR3 11 1176 1177 /* V7M CCR bits */ 1178 FIELD(V7M_CCR, NONBASETHRDENA, 0, 1) 1179 FIELD(V7M_CCR, USERSETMPEND, 1, 1) 1180 FIELD(V7M_CCR, UNALIGN_TRP, 3, 1) 1181 FIELD(V7M_CCR, DIV_0_TRP, 4, 1) 1182 FIELD(V7M_CCR, BFHFNMIGN, 8, 1) 1183 FIELD(V7M_CCR, STKALIGN, 9, 1) 1184 FIELD(V7M_CCR, DC, 16, 1) 1185 FIELD(V7M_CCR, IC, 17, 1) 1186 1187 /* V7M CFSR bits for MMFSR */ 1188 FIELD(V7M_CFSR, IACCVIOL, 0, 1) 1189 FIELD(V7M_CFSR, DACCVIOL, 1, 1) 1190 FIELD(V7M_CFSR, MUNSTKERR, 3, 1) 1191 FIELD(V7M_CFSR, MSTKERR, 4, 1) 1192 FIELD(V7M_CFSR, MLSPERR, 5, 1) 1193 FIELD(V7M_CFSR, MMARVALID, 7, 1) 1194 1195 /* V7M CFSR bits for BFSR */ 1196 FIELD(V7M_CFSR, IBUSERR, 8 + 0, 1) 1197 FIELD(V7M_CFSR, PRECISERR, 8 + 1, 1) 1198 FIELD(V7M_CFSR, IMPRECISERR, 8 + 2, 1) 1199 FIELD(V7M_CFSR, UNSTKERR, 8 + 3, 1) 1200 FIELD(V7M_CFSR, STKERR, 8 + 4, 1) 1201 FIELD(V7M_CFSR, LSPERR, 8 + 5, 1) 1202 FIELD(V7M_CFSR, BFARVALID, 8 + 7, 1) 1203 1204 /* V7M CFSR bits for UFSR */ 1205 FIELD(V7M_CFSR, UNDEFINSTR, 16 + 0, 1) 1206 FIELD(V7M_CFSR, INVSTATE, 16 + 1, 1) 1207 FIELD(V7M_CFSR, INVPC, 16 + 2, 1) 1208 FIELD(V7M_CFSR, NOCP, 16 + 3, 1) 1209 FIELD(V7M_CFSR, UNALIGNED, 16 + 8, 1) 1210 FIELD(V7M_CFSR, DIVBYZERO, 16 + 9, 1) 1211 1212 /* V7M CFSR bit masks covering all of the subregister bits */ 1213 FIELD(V7M_CFSR, MMFSR, 0, 8) 1214 FIELD(V7M_CFSR, BFSR, 8, 8) 1215 FIELD(V7M_CFSR, UFSR, 16, 16) 1216 1217 /* V7M HFSR bits */ 1218 FIELD(V7M_HFSR, VECTTBL, 1, 1) 1219 FIELD(V7M_HFSR, FORCED, 30, 1) 1220 FIELD(V7M_HFSR, DEBUGEVT, 31, 1) 1221 1222 /* V7M DFSR bits */ 1223 FIELD(V7M_DFSR, HALTED, 0, 1) 1224 FIELD(V7M_DFSR, BKPT, 1, 1) 1225 FIELD(V7M_DFSR, DWTTRAP, 2, 1) 1226 FIELD(V7M_DFSR, VCATCH, 3, 1) 1227 FIELD(V7M_DFSR, EXTERNAL, 4, 1) 1228 1229 /* v7M MPU_CTRL bits */ 1230 FIELD(V7M_MPU_CTRL, ENABLE, 0, 1) 1231 FIELD(V7M_MPU_CTRL, HFNMIENA, 1, 1) 1232 FIELD(V7M_MPU_CTRL, PRIVDEFENA, 2, 1) 1233 1234 /* If adding a feature bit which corresponds to a Linux ELF 1235 * HWCAP bit, remember to update the feature-bit-to-hwcap 1236 * mapping in linux-user/elfload.c:get_elf_hwcap(). 1237 */ 1238 enum arm_features { 1239 ARM_FEATURE_VFP, 1240 ARM_FEATURE_AUXCR, /* ARM1026 Auxiliary control register. */ 1241 ARM_FEATURE_XSCALE, /* Intel XScale extensions. */ 1242 ARM_FEATURE_IWMMXT, /* Intel iwMMXt extension. */ 1243 ARM_FEATURE_V6, 1244 ARM_FEATURE_V6K, 1245 ARM_FEATURE_V7, 1246 ARM_FEATURE_THUMB2, 1247 ARM_FEATURE_PMSA, /* no MMU; may have Memory Protection Unit */ 1248 ARM_FEATURE_VFP3, 1249 ARM_FEATURE_VFP_FP16, 1250 ARM_FEATURE_NEON, 1251 ARM_FEATURE_THUMB_DIV, /* divide supported in Thumb encoding */ 1252 ARM_FEATURE_M, /* Microcontroller profile. */ 1253 ARM_FEATURE_OMAPCP, /* OMAP specific CP15 ops handling. */ 1254 ARM_FEATURE_THUMB2EE, 1255 ARM_FEATURE_V7MP, /* v7 Multiprocessing Extensions */ 1256 ARM_FEATURE_V4T, 1257 ARM_FEATURE_V5, 1258 ARM_FEATURE_STRONGARM, 1259 ARM_FEATURE_VAPA, /* cp15 VA to PA lookups */ 1260 ARM_FEATURE_ARM_DIV, /* divide supported in ARM encoding */ 1261 ARM_FEATURE_VFP4, /* VFPv4 (implies that NEON is v2) */ 1262 ARM_FEATURE_GENERIC_TIMER, 1263 ARM_FEATURE_MVFR, /* Media and VFP Feature Registers 0 and 1 */ 1264 ARM_FEATURE_DUMMY_C15_REGS, /* RAZ/WI all of cp15 crn=15 */ 1265 ARM_FEATURE_CACHE_TEST_CLEAN, /* 926/1026 style test-and-clean ops */ 1266 ARM_FEATURE_CACHE_DIRTY_REG, /* 1136/1176 cache dirty status register */ 1267 ARM_FEATURE_CACHE_BLOCK_OPS, /* v6 optional cache block operations */ 1268 ARM_FEATURE_MPIDR, /* has cp15 MPIDR */ 1269 ARM_FEATURE_PXN, /* has Privileged Execute Never bit */ 1270 ARM_FEATURE_LPAE, /* has Large Physical Address Extension */ 1271 ARM_FEATURE_V8, 1272 ARM_FEATURE_AARCH64, /* supports 64 bit mode */ 1273 ARM_FEATURE_V8_AES, /* implements AES part of v8 Crypto Extensions */ 1274 ARM_FEATURE_CBAR, /* has cp15 CBAR */ 1275 ARM_FEATURE_CRC, /* ARMv8 CRC instructions */ 1276 ARM_FEATURE_CBAR_RO, /* has cp15 CBAR and it is read-only */ 1277 ARM_FEATURE_EL2, /* has EL2 Virtualization support */ 1278 ARM_FEATURE_EL3, /* has EL3 Secure monitor support */ 1279 ARM_FEATURE_V8_SHA1, /* implements SHA1 part of v8 Crypto Extensions */ 1280 ARM_FEATURE_V8_SHA256, /* implements SHA256 part of v8 Crypto Extensions */ 1281 ARM_FEATURE_V8_PMULL, /* implements PMULL part of v8 Crypto Extensions */ 1282 ARM_FEATURE_THUMB_DSP, /* DSP insns supported in the Thumb encodings */ 1283 ARM_FEATURE_PMU, /* has PMU support */ 1284 ARM_FEATURE_VBAR, /* has cp15 VBAR */ 1285 ARM_FEATURE_M_SECURITY, /* M profile Security Extension */ 1286 }; 1287 1288 static inline int arm_feature(CPUARMState *env, int feature) 1289 { 1290 return (env->features & (1ULL << feature)) != 0; 1291 } 1292 1293 #if !defined(CONFIG_USER_ONLY) 1294 /* Return true if exception levels below EL3 are in secure state, 1295 * or would be following an exception return to that level. 1296 * Unlike arm_is_secure() (which is always a question about the 1297 * _current_ state of the CPU) this doesn't care about the current 1298 * EL or mode. 1299 */ 1300 static inline bool arm_is_secure_below_el3(CPUARMState *env) 1301 { 1302 if (arm_feature(env, ARM_FEATURE_EL3)) { 1303 return !(env->cp15.scr_el3 & SCR_NS); 1304 } else { 1305 /* If EL3 is not supported then the secure state is implementation 1306 * defined, in which case QEMU defaults to non-secure. 1307 */ 1308 return false; 1309 } 1310 } 1311 1312 /* Return true if the CPU is AArch64 EL3 or AArch32 Mon */ 1313 static inline bool arm_is_el3_or_mon(CPUARMState *env) 1314 { 1315 if (arm_feature(env, ARM_FEATURE_EL3)) { 1316 if (is_a64(env) && extract32(env->pstate, 2, 2) == 3) { 1317 /* CPU currently in AArch64 state and EL3 */ 1318 return true; 1319 } else if (!is_a64(env) && 1320 (env->uncached_cpsr & CPSR_M) == ARM_CPU_MODE_MON) { 1321 /* CPU currently in AArch32 state and monitor mode */ 1322 return true; 1323 } 1324 } 1325 return false; 1326 } 1327 1328 /* Return true if the processor is in secure state */ 1329 static inline bool arm_is_secure(CPUARMState *env) 1330 { 1331 if (arm_is_el3_or_mon(env)) { 1332 return true; 1333 } 1334 return arm_is_secure_below_el3(env); 1335 } 1336 1337 #else 1338 static inline bool arm_is_secure_below_el3(CPUARMState *env) 1339 { 1340 return false; 1341 } 1342 1343 static inline bool arm_is_secure(CPUARMState *env) 1344 { 1345 return false; 1346 } 1347 #endif 1348 1349 /* Return true if the specified exception level is running in AArch64 state. */ 1350 static inline bool arm_el_is_aa64(CPUARMState *env, int el) 1351 { 1352 /* This isn't valid for EL0 (if we're in EL0, is_a64() is what you want, 1353 * and if we're not in EL0 then the state of EL0 isn't well defined.) 1354 */ 1355 assert(el >= 1 && el <= 3); 1356 bool aa64 = arm_feature(env, ARM_FEATURE_AARCH64); 1357 1358 /* The highest exception level is always at the maximum supported 1359 * register width, and then lower levels have a register width controlled 1360 * by bits in the SCR or HCR registers. 1361 */ 1362 if (el == 3) { 1363 return aa64; 1364 } 1365 1366 if (arm_feature(env, ARM_FEATURE_EL3)) { 1367 aa64 = aa64 && (env->cp15.scr_el3 & SCR_RW); 1368 } 1369 1370 if (el == 2) { 1371 return aa64; 1372 } 1373 1374 if (arm_feature(env, ARM_FEATURE_EL2) && !arm_is_secure_below_el3(env)) { 1375 aa64 = aa64 && (env->cp15.hcr_el2 & HCR_RW); 1376 } 1377 1378 return aa64; 1379 } 1380 1381 /* Function for determing whether guest cp register reads and writes should 1382 * access the secure or non-secure bank of a cp register. When EL3 is 1383 * operating in AArch32 state, the NS-bit determines whether the secure 1384 * instance of a cp register should be used. When EL3 is AArch64 (or if 1385 * it doesn't exist at all) then there is no register banking, and all 1386 * accesses are to the non-secure version. 1387 */ 1388 static inline bool access_secure_reg(CPUARMState *env) 1389 { 1390 bool ret = (arm_feature(env, ARM_FEATURE_EL3) && 1391 !arm_el_is_aa64(env, 3) && 1392 !(env->cp15.scr_el3 & SCR_NS)); 1393 1394 return ret; 1395 } 1396 1397 /* Macros for accessing a specified CP register bank */ 1398 #define A32_BANKED_REG_GET(_env, _regname, _secure) \ 1399 ((_secure) ? (_env)->cp15._regname##_s : (_env)->cp15._regname##_ns) 1400 1401 #define A32_BANKED_REG_SET(_env, _regname, _secure, _val) \ 1402 do { \ 1403 if (_secure) { \ 1404 (_env)->cp15._regname##_s = (_val); \ 1405 } else { \ 1406 (_env)->cp15._regname##_ns = (_val); \ 1407 } \ 1408 } while (0) 1409 1410 /* Macros for automatically accessing a specific CP register bank depending on 1411 * the current secure state of the system. These macros are not intended for 1412 * supporting instruction translation reads/writes as these are dependent 1413 * solely on the SCR.NS bit and not the mode. 1414 */ 1415 #define A32_BANKED_CURRENT_REG_GET(_env, _regname) \ 1416 A32_BANKED_REG_GET((_env), _regname, \ 1417 (arm_is_secure(_env) && !arm_el_is_aa64((_env), 3))) 1418 1419 #define A32_BANKED_CURRENT_REG_SET(_env, _regname, _val) \ 1420 A32_BANKED_REG_SET((_env), _regname, \ 1421 (arm_is_secure(_env) && !arm_el_is_aa64((_env), 3)), \ 1422 (_val)) 1423 1424 void arm_cpu_list(FILE *f, fprintf_function cpu_fprintf); 1425 uint32_t arm_phys_excp_target_el(CPUState *cs, uint32_t excp_idx, 1426 uint32_t cur_el, bool secure); 1427 1428 /* Interface between CPU and Interrupt controller. */ 1429 #ifndef CONFIG_USER_ONLY 1430 bool armv7m_nvic_can_take_pending_exception(void *opaque); 1431 #else 1432 static inline bool armv7m_nvic_can_take_pending_exception(void *opaque) 1433 { 1434 return true; 1435 } 1436 #endif 1437 void armv7m_nvic_set_pending(void *opaque, int irq); 1438 void armv7m_nvic_acknowledge_irq(void *opaque); 1439 /** 1440 * armv7m_nvic_complete_irq: complete specified interrupt or exception 1441 * @opaque: the NVIC 1442 * @irq: the exception number to complete 1443 * 1444 * Returns: -1 if the irq was not active 1445 * 1 if completing this irq brought us back to base (no active irqs) 1446 * 0 if there is still an irq active after this one was completed 1447 * (Ignoring -1, this is the same as the RETTOBASE value before completion.) 1448 */ 1449 int armv7m_nvic_complete_irq(void *opaque, int irq); 1450 /** 1451 * armv7m_nvic_raw_execution_priority: return the raw execution priority 1452 * @opaque: the NVIC 1453 * 1454 * Returns: the raw execution priority as defined by the v8M architecture. 1455 * This is the execution priority minus the effects of AIRCR.PRIS, 1456 * and minus any PRIMASK/FAULTMASK/BASEPRI priority boosting. 1457 * (v8M ARM ARM I_PKLD.) 1458 */ 1459 int armv7m_nvic_raw_execution_priority(void *opaque); 1460 1461 /* Interface for defining coprocessor registers. 1462 * Registers are defined in tables of arm_cp_reginfo structs 1463 * which are passed to define_arm_cp_regs(). 1464 */ 1465 1466 /* When looking up a coprocessor register we look for it 1467 * via an integer which encodes all of: 1468 * coprocessor number 1469 * Crn, Crm, opc1, opc2 fields 1470 * 32 or 64 bit register (ie is it accessed via MRC/MCR 1471 * or via MRRC/MCRR?) 1472 * non-secure/secure bank (AArch32 only) 1473 * We allow 4 bits for opc1 because MRRC/MCRR have a 4 bit field. 1474 * (In this case crn and opc2 should be zero.) 1475 * For AArch64, there is no 32/64 bit size distinction; 1476 * instead all registers have a 2 bit op0, 3 bit op1 and op2, 1477 * and 4 bit CRn and CRm. The encoding patterns are chosen 1478 * to be easy to convert to and from the KVM encodings, and also 1479 * so that the hashtable can contain both AArch32 and AArch64 1480 * registers (to allow for interprocessing where we might run 1481 * 32 bit code on a 64 bit core). 1482 */ 1483 /* This bit is private to our hashtable cpreg; in KVM register 1484 * IDs the AArch64/32 distinction is the KVM_REG_ARM/ARM64 1485 * in the upper bits of the 64 bit ID. 1486 */ 1487 #define CP_REG_AA64_SHIFT 28 1488 #define CP_REG_AA64_MASK (1 << CP_REG_AA64_SHIFT) 1489 1490 /* To enable banking of coprocessor registers depending on ns-bit we 1491 * add a bit to distinguish between secure and non-secure cpregs in the 1492 * hashtable. 1493 */ 1494 #define CP_REG_NS_SHIFT 29 1495 #define CP_REG_NS_MASK (1 << CP_REG_NS_SHIFT) 1496 1497 #define ENCODE_CP_REG(cp, is64, ns, crn, crm, opc1, opc2) \ 1498 ((ns) << CP_REG_NS_SHIFT | ((cp) << 16) | ((is64) << 15) | \ 1499 ((crn) << 11) | ((crm) << 7) | ((opc1) << 3) | (opc2)) 1500 1501 #define ENCODE_AA64_CP_REG(cp, crn, crm, op0, op1, op2) \ 1502 (CP_REG_AA64_MASK | \ 1503 ((cp) << CP_REG_ARM_COPROC_SHIFT) | \ 1504 ((op0) << CP_REG_ARM64_SYSREG_OP0_SHIFT) | \ 1505 ((op1) << CP_REG_ARM64_SYSREG_OP1_SHIFT) | \ 1506 ((crn) << CP_REG_ARM64_SYSREG_CRN_SHIFT) | \ 1507 ((crm) << CP_REG_ARM64_SYSREG_CRM_SHIFT) | \ 1508 ((op2) << CP_REG_ARM64_SYSREG_OP2_SHIFT)) 1509 1510 /* Convert a full 64 bit KVM register ID to the truncated 32 bit 1511 * version used as a key for the coprocessor register hashtable 1512 */ 1513 static inline uint32_t kvm_to_cpreg_id(uint64_t kvmid) 1514 { 1515 uint32_t cpregid = kvmid; 1516 if ((kvmid & CP_REG_ARCH_MASK) == CP_REG_ARM64) { 1517 cpregid |= CP_REG_AA64_MASK; 1518 } else { 1519 if ((kvmid & CP_REG_SIZE_MASK) == CP_REG_SIZE_U64) { 1520 cpregid |= (1 << 15); 1521 } 1522 1523 /* KVM is always non-secure so add the NS flag on AArch32 register 1524 * entries. 1525 */ 1526 cpregid |= 1 << CP_REG_NS_SHIFT; 1527 } 1528 return cpregid; 1529 } 1530 1531 /* Convert a truncated 32 bit hashtable key into the full 1532 * 64 bit KVM register ID. 1533 */ 1534 static inline uint64_t cpreg_to_kvm_id(uint32_t cpregid) 1535 { 1536 uint64_t kvmid; 1537 1538 if (cpregid & CP_REG_AA64_MASK) { 1539 kvmid = cpregid & ~CP_REG_AA64_MASK; 1540 kvmid |= CP_REG_SIZE_U64 | CP_REG_ARM64; 1541 } else { 1542 kvmid = cpregid & ~(1 << 15); 1543 if (cpregid & (1 << 15)) { 1544 kvmid |= CP_REG_SIZE_U64 | CP_REG_ARM; 1545 } else { 1546 kvmid |= CP_REG_SIZE_U32 | CP_REG_ARM; 1547 } 1548 } 1549 return kvmid; 1550 } 1551 1552 /* ARMCPRegInfo type field bits. If the SPECIAL bit is set this is a 1553 * special-behaviour cp reg and bits [15..8] indicate what behaviour 1554 * it has. Otherwise it is a simple cp reg, where CONST indicates that 1555 * TCG can assume the value to be constant (ie load at translate time) 1556 * and 64BIT indicates a 64 bit wide coprocessor register. SUPPRESS_TB_END 1557 * indicates that the TB should not be ended after a write to this register 1558 * (the default is that the TB ends after cp writes). OVERRIDE permits 1559 * a register definition to override a previous definition for the 1560 * same (cp, is64, crn, crm, opc1, opc2) tuple: either the new or the 1561 * old must have the OVERRIDE bit set. 1562 * ALIAS indicates that this register is an alias view of some underlying 1563 * state which is also visible via another register, and that the other 1564 * register is handling migration and reset; registers marked ALIAS will not be 1565 * migrated but may have their state set by syncing of register state from KVM. 1566 * NO_RAW indicates that this register has no underlying state and does not 1567 * support raw access for state saving/loading; it will not be used for either 1568 * migration or KVM state synchronization. (Typically this is for "registers" 1569 * which are actually used as instructions for cache maintenance and so on.) 1570 * IO indicates that this register does I/O and therefore its accesses 1571 * need to be surrounded by gen_io_start()/gen_io_end(). In particular, 1572 * registers which implement clocks or timers require this. 1573 */ 1574 #define ARM_CP_SPECIAL 1 1575 #define ARM_CP_CONST 2 1576 #define ARM_CP_64BIT 4 1577 #define ARM_CP_SUPPRESS_TB_END 8 1578 #define ARM_CP_OVERRIDE 16 1579 #define ARM_CP_ALIAS 32 1580 #define ARM_CP_IO 64 1581 #define ARM_CP_NO_RAW 128 1582 #define ARM_CP_NOP (ARM_CP_SPECIAL | (1 << 8)) 1583 #define ARM_CP_WFI (ARM_CP_SPECIAL | (2 << 8)) 1584 #define ARM_CP_NZCV (ARM_CP_SPECIAL | (3 << 8)) 1585 #define ARM_CP_CURRENTEL (ARM_CP_SPECIAL | (4 << 8)) 1586 #define ARM_CP_DC_ZVA (ARM_CP_SPECIAL | (5 << 8)) 1587 #define ARM_LAST_SPECIAL ARM_CP_DC_ZVA 1588 /* Used only as a terminator for ARMCPRegInfo lists */ 1589 #define ARM_CP_SENTINEL 0xffff 1590 /* Mask of only the flag bits in a type field */ 1591 #define ARM_CP_FLAG_MASK 0xff 1592 1593 /* Valid values for ARMCPRegInfo state field, indicating which of 1594 * the AArch32 and AArch64 execution states this register is visible in. 1595 * If the reginfo doesn't explicitly specify then it is AArch32 only. 1596 * If the reginfo is declared to be visible in both states then a second 1597 * reginfo is synthesised for the AArch32 view of the AArch64 register, 1598 * such that the AArch32 view is the lower 32 bits of the AArch64 one. 1599 * Note that we rely on the values of these enums as we iterate through 1600 * the various states in some places. 1601 */ 1602 enum { 1603 ARM_CP_STATE_AA32 = 0, 1604 ARM_CP_STATE_AA64 = 1, 1605 ARM_CP_STATE_BOTH = 2, 1606 }; 1607 1608 /* ARM CP register secure state flags. These flags identify security state 1609 * attributes for a given CP register entry. 1610 * The existence of both or neither secure and non-secure flags indicates that 1611 * the register has both a secure and non-secure hash entry. A single one of 1612 * these flags causes the register to only be hashed for the specified 1613 * security state. 1614 * Although definitions may have any combination of the S/NS bits, each 1615 * registered entry will only have one to identify whether the entry is secure 1616 * or non-secure. 1617 */ 1618 enum { 1619 ARM_CP_SECSTATE_S = (1 << 0), /* bit[0]: Secure state register */ 1620 ARM_CP_SECSTATE_NS = (1 << 1), /* bit[1]: Non-secure state register */ 1621 }; 1622 1623 /* Return true if cptype is a valid type field. This is used to try to 1624 * catch errors where the sentinel has been accidentally left off the end 1625 * of a list of registers. 1626 */ 1627 static inline bool cptype_valid(int cptype) 1628 { 1629 return ((cptype & ~ARM_CP_FLAG_MASK) == 0) 1630 || ((cptype & ARM_CP_SPECIAL) && 1631 ((cptype & ~ARM_CP_FLAG_MASK) <= ARM_LAST_SPECIAL)); 1632 } 1633 1634 /* Access rights: 1635 * We define bits for Read and Write access for what rev C of the v7-AR ARM ARM 1636 * defines as PL0 (user), PL1 (fiq/irq/svc/abt/und/sys, ie privileged), and 1637 * PL2 (hyp). The other level which has Read and Write bits is Secure PL1 1638 * (ie any of the privileged modes in Secure state, or Monitor mode). 1639 * If a register is accessible in one privilege level it's always accessible 1640 * in higher privilege levels too. Since "Secure PL1" also follows this rule 1641 * (ie anything visible in PL2 is visible in S-PL1, some things are only 1642 * visible in S-PL1) but "Secure PL1" is a bit of a mouthful, we bend the 1643 * terminology a little and call this PL3. 1644 * In AArch64 things are somewhat simpler as the PLx bits line up exactly 1645 * with the ELx exception levels. 1646 * 1647 * If access permissions for a register are more complex than can be 1648 * described with these bits, then use a laxer set of restrictions, and 1649 * do the more restrictive/complex check inside a helper function. 1650 */ 1651 #define PL3_R 0x80 1652 #define PL3_W 0x40 1653 #define PL2_R (0x20 | PL3_R) 1654 #define PL2_W (0x10 | PL3_W) 1655 #define PL1_R (0x08 | PL2_R) 1656 #define PL1_W (0x04 | PL2_W) 1657 #define PL0_R (0x02 | PL1_R) 1658 #define PL0_W (0x01 | PL1_W) 1659 1660 #define PL3_RW (PL3_R | PL3_W) 1661 #define PL2_RW (PL2_R | PL2_W) 1662 #define PL1_RW (PL1_R | PL1_W) 1663 #define PL0_RW (PL0_R | PL0_W) 1664 1665 /* Return the highest implemented Exception Level */ 1666 static inline int arm_highest_el(CPUARMState *env) 1667 { 1668 if (arm_feature(env, ARM_FEATURE_EL3)) { 1669 return 3; 1670 } 1671 if (arm_feature(env, ARM_FEATURE_EL2)) { 1672 return 2; 1673 } 1674 return 1; 1675 } 1676 1677 /* Return true if a v7M CPU is in Handler mode */ 1678 static inline bool arm_v7m_is_handler_mode(CPUARMState *env) 1679 { 1680 return env->v7m.exception != 0; 1681 } 1682 1683 /* Return the current Exception Level (as per ARMv8; note that this differs 1684 * from the ARMv7 Privilege Level). 1685 */ 1686 static inline int arm_current_el(CPUARMState *env) 1687 { 1688 if (arm_feature(env, ARM_FEATURE_M)) { 1689 return arm_v7m_is_handler_mode(env) || 1690 !(env->v7m.control[env->v7m.secure] & 1); 1691 } 1692 1693 if (is_a64(env)) { 1694 return extract32(env->pstate, 2, 2); 1695 } 1696 1697 switch (env->uncached_cpsr & 0x1f) { 1698 case ARM_CPU_MODE_USR: 1699 return 0; 1700 case ARM_CPU_MODE_HYP: 1701 return 2; 1702 case ARM_CPU_MODE_MON: 1703 return 3; 1704 default: 1705 if (arm_is_secure(env) && !arm_el_is_aa64(env, 3)) { 1706 /* If EL3 is 32-bit then all secure privileged modes run in 1707 * EL3 1708 */ 1709 return 3; 1710 } 1711 1712 return 1; 1713 } 1714 } 1715 1716 typedef struct ARMCPRegInfo ARMCPRegInfo; 1717 1718 typedef enum CPAccessResult { 1719 /* Access is permitted */ 1720 CP_ACCESS_OK = 0, 1721 /* Access fails due to a configurable trap or enable which would 1722 * result in a categorized exception syndrome giving information about 1723 * the failing instruction (ie syndrome category 0x3, 0x4, 0x5, 0x6, 1724 * 0xc or 0x18). The exception is taken to the usual target EL (EL1 or 1725 * PL1 if in EL0, otherwise to the current EL). 1726 */ 1727 CP_ACCESS_TRAP = 1, 1728 /* Access fails and results in an exception syndrome 0x0 ("uncategorized"). 1729 * Note that this is not a catch-all case -- the set of cases which may 1730 * result in this failure is specifically defined by the architecture. 1731 */ 1732 CP_ACCESS_TRAP_UNCATEGORIZED = 2, 1733 /* As CP_ACCESS_TRAP, but for traps directly to EL2 or EL3 */ 1734 CP_ACCESS_TRAP_EL2 = 3, 1735 CP_ACCESS_TRAP_EL3 = 4, 1736 /* As CP_ACCESS_UNCATEGORIZED, but for traps directly to EL2 or EL3 */ 1737 CP_ACCESS_TRAP_UNCATEGORIZED_EL2 = 5, 1738 CP_ACCESS_TRAP_UNCATEGORIZED_EL3 = 6, 1739 /* Access fails and results in an exception syndrome for an FP access, 1740 * trapped directly to EL2 or EL3 1741 */ 1742 CP_ACCESS_TRAP_FP_EL2 = 7, 1743 CP_ACCESS_TRAP_FP_EL3 = 8, 1744 } CPAccessResult; 1745 1746 /* Access functions for coprocessor registers. These cannot fail and 1747 * may not raise exceptions. 1748 */ 1749 typedef uint64_t CPReadFn(CPUARMState *env, const ARMCPRegInfo *opaque); 1750 typedef void CPWriteFn(CPUARMState *env, const ARMCPRegInfo *opaque, 1751 uint64_t value); 1752 /* Access permission check functions for coprocessor registers. */ 1753 typedef CPAccessResult CPAccessFn(CPUARMState *env, 1754 const ARMCPRegInfo *opaque, 1755 bool isread); 1756 /* Hook function for register reset */ 1757 typedef void CPResetFn(CPUARMState *env, const ARMCPRegInfo *opaque); 1758 1759 #define CP_ANY 0xff 1760 1761 /* Definition of an ARM coprocessor register */ 1762 struct ARMCPRegInfo { 1763 /* Name of register (useful mainly for debugging, need not be unique) */ 1764 const char *name; 1765 /* Location of register: coprocessor number and (crn,crm,opc1,opc2) 1766 * tuple. Any of crm, opc1 and opc2 may be CP_ANY to indicate a 1767 * 'wildcard' field -- any value of that field in the MRC/MCR insn 1768 * will be decoded to this register. The register read and write 1769 * callbacks will be passed an ARMCPRegInfo with the crn/crm/opc1/opc2 1770 * used by the program, so it is possible to register a wildcard and 1771 * then behave differently on read/write if necessary. 1772 * For 64 bit registers, only crm and opc1 are relevant; crn and opc2 1773 * must both be zero. 1774 * For AArch64-visible registers, opc0 is also used. 1775 * Since there are no "coprocessors" in AArch64, cp is purely used as a 1776 * way to distinguish (for KVM's benefit) guest-visible system registers 1777 * from demuxed ones provided to preserve the "no side effects on 1778 * KVM register read/write from QEMU" semantics. cp==0x13 is guest 1779 * visible (to match KVM's encoding); cp==0 will be converted to 1780 * cp==0x13 when the ARMCPRegInfo is registered, for convenience. 1781 */ 1782 uint8_t cp; 1783 uint8_t crn; 1784 uint8_t crm; 1785 uint8_t opc0; 1786 uint8_t opc1; 1787 uint8_t opc2; 1788 /* Execution state in which this register is visible: ARM_CP_STATE_* */ 1789 int state; 1790 /* Register type: ARM_CP_* bits/values */ 1791 int type; 1792 /* Access rights: PL*_[RW] */ 1793 int access; 1794 /* Security state: ARM_CP_SECSTATE_* bits/values */ 1795 int secure; 1796 /* The opaque pointer passed to define_arm_cp_regs_with_opaque() when 1797 * this register was defined: can be used to hand data through to the 1798 * register read/write functions, since they are passed the ARMCPRegInfo*. 1799 */ 1800 void *opaque; 1801 /* Value of this register, if it is ARM_CP_CONST. Otherwise, if 1802 * fieldoffset is non-zero, the reset value of the register. 1803 */ 1804 uint64_t resetvalue; 1805 /* Offset of the field in CPUARMState for this register. 1806 * 1807 * This is not needed if either: 1808 * 1. type is ARM_CP_CONST or one of the ARM_CP_SPECIALs 1809 * 2. both readfn and writefn are specified 1810 */ 1811 ptrdiff_t fieldoffset; /* offsetof(CPUARMState, field) */ 1812 1813 /* Offsets of the secure and non-secure fields in CPUARMState for the 1814 * register if it is banked. These fields are only used during the static 1815 * registration of a register. During hashing the bank associated 1816 * with a given security state is copied to fieldoffset which is used from 1817 * there on out. 1818 * 1819 * It is expected that register definitions use either fieldoffset or 1820 * bank_fieldoffsets in the definition but not both. It is also expected 1821 * that both bank offsets are set when defining a banked register. This 1822 * use indicates that a register is banked. 1823 */ 1824 ptrdiff_t bank_fieldoffsets[2]; 1825 1826 /* Function for making any access checks for this register in addition to 1827 * those specified by the 'access' permissions bits. If NULL, no extra 1828 * checks required. The access check is performed at runtime, not at 1829 * translate time. 1830 */ 1831 CPAccessFn *accessfn; 1832 /* Function for handling reads of this register. If NULL, then reads 1833 * will be done by loading from the offset into CPUARMState specified 1834 * by fieldoffset. 1835 */ 1836 CPReadFn *readfn; 1837 /* Function for handling writes of this register. If NULL, then writes 1838 * will be done by writing to the offset into CPUARMState specified 1839 * by fieldoffset. 1840 */ 1841 CPWriteFn *writefn; 1842 /* Function for doing a "raw" read; used when we need to copy 1843 * coprocessor state to the kernel for KVM or out for 1844 * migration. This only needs to be provided if there is also a 1845 * readfn and it has side effects (for instance clear-on-read bits). 1846 */ 1847 CPReadFn *raw_readfn; 1848 /* Function for doing a "raw" write; used when we need to copy KVM 1849 * kernel coprocessor state into userspace, or for inbound 1850 * migration. This only needs to be provided if there is also a 1851 * writefn and it masks out "unwritable" bits or has write-one-to-clear 1852 * or similar behaviour. 1853 */ 1854 CPWriteFn *raw_writefn; 1855 /* Function for resetting the register. If NULL, then reset will be done 1856 * by writing resetvalue to the field specified in fieldoffset. If 1857 * fieldoffset is 0 then no reset will be done. 1858 */ 1859 CPResetFn *resetfn; 1860 }; 1861 1862 /* Macros which are lvalues for the field in CPUARMState for the 1863 * ARMCPRegInfo *ri. 1864 */ 1865 #define CPREG_FIELD32(env, ri) \ 1866 (*(uint32_t *)((char *)(env) + (ri)->fieldoffset)) 1867 #define CPREG_FIELD64(env, ri) \ 1868 (*(uint64_t *)((char *)(env) + (ri)->fieldoffset)) 1869 1870 #define REGINFO_SENTINEL { .type = ARM_CP_SENTINEL } 1871 1872 void define_arm_cp_regs_with_opaque(ARMCPU *cpu, 1873 const ARMCPRegInfo *regs, void *opaque); 1874 void define_one_arm_cp_reg_with_opaque(ARMCPU *cpu, 1875 const ARMCPRegInfo *regs, void *opaque); 1876 static inline void define_arm_cp_regs(ARMCPU *cpu, const ARMCPRegInfo *regs) 1877 { 1878 define_arm_cp_regs_with_opaque(cpu, regs, 0); 1879 } 1880 static inline void define_one_arm_cp_reg(ARMCPU *cpu, const ARMCPRegInfo *regs) 1881 { 1882 define_one_arm_cp_reg_with_opaque(cpu, regs, 0); 1883 } 1884 const ARMCPRegInfo *get_arm_cp_reginfo(GHashTable *cpregs, uint32_t encoded_cp); 1885 1886 /* CPWriteFn that can be used to implement writes-ignored behaviour */ 1887 void arm_cp_write_ignore(CPUARMState *env, const ARMCPRegInfo *ri, 1888 uint64_t value); 1889 /* CPReadFn that can be used for read-as-zero behaviour */ 1890 uint64_t arm_cp_read_zero(CPUARMState *env, const ARMCPRegInfo *ri); 1891 1892 /* CPResetFn that does nothing, for use if no reset is required even 1893 * if fieldoffset is non zero. 1894 */ 1895 void arm_cp_reset_ignore(CPUARMState *env, const ARMCPRegInfo *opaque); 1896 1897 /* Return true if this reginfo struct's field in the cpu state struct 1898 * is 64 bits wide. 1899 */ 1900 static inline bool cpreg_field_is_64bit(const ARMCPRegInfo *ri) 1901 { 1902 return (ri->state == ARM_CP_STATE_AA64) || (ri->type & ARM_CP_64BIT); 1903 } 1904 1905 static inline bool cp_access_ok(int current_el, 1906 const ARMCPRegInfo *ri, int isread) 1907 { 1908 return (ri->access >> ((current_el * 2) + isread)) & 1; 1909 } 1910 1911 /* Raw read of a coprocessor register (as needed for migration, etc) */ 1912 uint64_t read_raw_cp_reg(CPUARMState *env, const ARMCPRegInfo *ri); 1913 1914 /** 1915 * write_list_to_cpustate 1916 * @cpu: ARMCPU 1917 * 1918 * For each register listed in the ARMCPU cpreg_indexes list, write 1919 * its value from the cpreg_values list into the ARMCPUState structure. 1920 * This updates TCG's working data structures from KVM data or 1921 * from incoming migration state. 1922 * 1923 * Returns: true if all register values were updated correctly, 1924 * false if some register was unknown or could not be written. 1925 * Note that we do not stop early on failure -- we will attempt 1926 * writing all registers in the list. 1927 */ 1928 bool write_list_to_cpustate(ARMCPU *cpu); 1929 1930 /** 1931 * write_cpustate_to_list: 1932 * @cpu: ARMCPU 1933 * 1934 * For each register listed in the ARMCPU cpreg_indexes list, write 1935 * its value from the ARMCPUState structure into the cpreg_values list. 1936 * This is used to copy info from TCG's working data structures into 1937 * KVM or for outbound migration. 1938 * 1939 * Returns: true if all register values were read correctly, 1940 * false if some register was unknown or could not be read. 1941 * Note that we do not stop early on failure -- we will attempt 1942 * reading all registers in the list. 1943 */ 1944 bool write_cpustate_to_list(ARMCPU *cpu); 1945 1946 #define ARM_CPUID_TI915T 0x54029152 1947 #define ARM_CPUID_TI925T 0x54029252 1948 1949 #if defined(CONFIG_USER_ONLY) 1950 #define TARGET_PAGE_BITS 12 1951 #else 1952 /* ARMv7 and later CPUs have 4K pages minimum, but ARMv5 and v6 1953 * have to support 1K tiny pages. 1954 */ 1955 #define TARGET_PAGE_BITS_VARY 1956 #define TARGET_PAGE_BITS_MIN 10 1957 #endif 1958 1959 #if defined(TARGET_AARCH64) 1960 # define TARGET_PHYS_ADDR_SPACE_BITS 48 1961 # define TARGET_VIRT_ADDR_SPACE_BITS 64 1962 #else 1963 # define TARGET_PHYS_ADDR_SPACE_BITS 40 1964 # define TARGET_VIRT_ADDR_SPACE_BITS 32 1965 #endif 1966 1967 static inline bool arm_excp_unmasked(CPUState *cs, unsigned int excp_idx, 1968 unsigned int target_el) 1969 { 1970 CPUARMState *env = cs->env_ptr; 1971 unsigned int cur_el = arm_current_el(env); 1972 bool secure = arm_is_secure(env); 1973 bool pstate_unmasked; 1974 int8_t unmasked = 0; 1975 1976 /* Don't take exceptions if they target a lower EL. 1977 * This check should catch any exceptions that would not be taken but left 1978 * pending. 1979 */ 1980 if (cur_el > target_el) { 1981 return false; 1982 } 1983 1984 switch (excp_idx) { 1985 case EXCP_FIQ: 1986 pstate_unmasked = !(env->daif & PSTATE_F); 1987 break; 1988 1989 case EXCP_IRQ: 1990 pstate_unmasked = !(env->daif & PSTATE_I); 1991 break; 1992 1993 case EXCP_VFIQ: 1994 if (secure || !(env->cp15.hcr_el2 & HCR_FMO)) { 1995 /* VFIQs are only taken when hypervized and non-secure. */ 1996 return false; 1997 } 1998 return !(env->daif & PSTATE_F); 1999 case EXCP_VIRQ: 2000 if (secure || !(env->cp15.hcr_el2 & HCR_IMO)) { 2001 /* VIRQs are only taken when hypervized and non-secure. */ 2002 return false; 2003 } 2004 return !(env->daif & PSTATE_I); 2005 default: 2006 g_assert_not_reached(); 2007 } 2008 2009 /* Use the target EL, current execution state and SCR/HCR settings to 2010 * determine whether the corresponding CPSR bit is used to mask the 2011 * interrupt. 2012 */ 2013 if ((target_el > cur_el) && (target_el != 1)) { 2014 /* Exceptions targeting a higher EL may not be maskable */ 2015 if (arm_feature(env, ARM_FEATURE_AARCH64)) { 2016 /* 64-bit masking rules are simple: exceptions to EL3 2017 * can't be masked, and exceptions to EL2 can only be 2018 * masked from Secure state. The HCR and SCR settings 2019 * don't affect the masking logic, only the interrupt routing. 2020 */ 2021 if (target_el == 3 || !secure) { 2022 unmasked = 1; 2023 } 2024 } else { 2025 /* The old 32-bit-only environment has a more complicated 2026 * masking setup. HCR and SCR bits not only affect interrupt 2027 * routing but also change the behaviour of masking. 2028 */ 2029 bool hcr, scr; 2030 2031 switch (excp_idx) { 2032 case EXCP_FIQ: 2033 /* If FIQs are routed to EL3 or EL2 then there are cases where 2034 * we override the CPSR.F in determining if the exception is 2035 * masked or not. If neither of these are set then we fall back 2036 * to the CPSR.F setting otherwise we further assess the state 2037 * below. 2038 */ 2039 hcr = (env->cp15.hcr_el2 & HCR_FMO); 2040 scr = (env->cp15.scr_el3 & SCR_FIQ); 2041 2042 /* When EL3 is 32-bit, the SCR.FW bit controls whether the 2043 * CPSR.F bit masks FIQ interrupts when taken in non-secure 2044 * state. If SCR.FW is set then FIQs can be masked by CPSR.F 2045 * when non-secure but only when FIQs are only routed to EL3. 2046 */ 2047 scr = scr && !((env->cp15.scr_el3 & SCR_FW) && !hcr); 2048 break; 2049 case EXCP_IRQ: 2050 /* When EL3 execution state is 32-bit, if HCR.IMO is set then 2051 * we may override the CPSR.I masking when in non-secure state. 2052 * The SCR.IRQ setting has already been taken into consideration 2053 * when setting the target EL, so it does not have a further 2054 * affect here. 2055 */ 2056 hcr = (env->cp15.hcr_el2 & HCR_IMO); 2057 scr = false; 2058 break; 2059 default: 2060 g_assert_not_reached(); 2061 } 2062 2063 if ((scr || hcr) && !secure) { 2064 unmasked = 1; 2065 } 2066 } 2067 } 2068 2069 /* The PSTATE bits only mask the interrupt if we have not overriden the 2070 * ability above. 2071 */ 2072 return unmasked || pstate_unmasked; 2073 } 2074 2075 #define cpu_init(cpu_model) cpu_generic_init(TYPE_ARM_CPU, cpu_model) 2076 2077 #define cpu_signal_handler cpu_arm_signal_handler 2078 #define cpu_list arm_cpu_list 2079 2080 /* ARM has the following "translation regimes" (as the ARM ARM calls them): 2081 * 2082 * If EL3 is 64-bit: 2083 * + NonSecure EL1 & 0 stage 1 2084 * + NonSecure EL1 & 0 stage 2 2085 * + NonSecure EL2 2086 * + Secure EL1 & EL0 2087 * + Secure EL3 2088 * If EL3 is 32-bit: 2089 * + NonSecure PL1 & 0 stage 1 2090 * + NonSecure PL1 & 0 stage 2 2091 * + NonSecure PL2 2092 * + Secure PL0 & PL1 2093 * (reminder: for 32 bit EL3, Secure PL1 is *EL3*, not EL1.) 2094 * 2095 * For QEMU, an mmu_idx is not quite the same as a translation regime because: 2096 * 1. we need to split the "EL1 & 0" regimes into two mmu_idxes, because they 2097 * may differ in access permissions even if the VA->PA map is the same 2098 * 2. we want to cache in our TLB the full VA->IPA->PA lookup for a stage 1+2 2099 * translation, which means that we have one mmu_idx that deals with two 2100 * concatenated translation regimes [this sort of combined s1+2 TLB is 2101 * architecturally permitted] 2102 * 3. we don't need to allocate an mmu_idx to translations that we won't be 2103 * handling via the TLB. The only way to do a stage 1 translation without 2104 * the immediate stage 2 translation is via the ATS or AT system insns, 2105 * which can be slow-pathed and always do a page table walk. 2106 * 4. we can also safely fold together the "32 bit EL3" and "64 bit EL3" 2107 * translation regimes, because they map reasonably well to each other 2108 * and they can't both be active at the same time. 2109 * This gives us the following list of mmu_idx values: 2110 * 2111 * NS EL0 (aka NS PL0) stage 1+2 2112 * NS EL1 (aka NS PL1) stage 1+2 2113 * NS EL2 (aka NS PL2) 2114 * S EL3 (aka S PL1) 2115 * S EL0 (aka S PL0) 2116 * S EL1 (not used if EL3 is 32 bit) 2117 * NS EL0+1 stage 2 2118 * 2119 * (The last of these is an mmu_idx because we want to be able to use the TLB 2120 * for the accesses done as part of a stage 1 page table walk, rather than 2121 * having to walk the stage 2 page table over and over.) 2122 * 2123 * R profile CPUs have an MPU, but can use the same set of MMU indexes 2124 * as A profile. They only need to distinguish NS EL0 and NS EL1 (and 2125 * NS EL2 if we ever model a Cortex-R52). 2126 * 2127 * M profile CPUs are rather different as they do not have a true MMU. 2128 * They have the following different MMU indexes: 2129 * User 2130 * Privileged 2131 * Execution priority negative (this is like privileged, but the 2132 * MPU HFNMIENA bit means that it may have different access permission 2133 * check results to normal privileged code, so can't share a TLB). 2134 * If the CPU supports the v8M Security Extension then there are also: 2135 * Secure User 2136 * Secure Privileged 2137 * Secure, execution priority negative 2138 * 2139 * The ARMMMUIdx and the mmu index value used by the core QEMU TLB code 2140 * are not quite the same -- different CPU types (most notably M profile 2141 * vs A/R profile) would like to use MMU indexes with different semantics, 2142 * but since we don't ever need to use all of those in a single CPU we 2143 * can avoid setting NB_MMU_MODES to more than 8. The lower bits of 2144 * ARMMMUIdx are the core TLB mmu index, and the higher bits are always 2145 * the same for any particular CPU. 2146 * Variables of type ARMMUIdx are always full values, and the core 2147 * index values are in variables of type 'int'. 2148 * 2149 * Our enumeration includes at the end some entries which are not "true" 2150 * mmu_idx values in that they don't have corresponding TLBs and are only 2151 * valid for doing slow path page table walks. 2152 * 2153 * The constant names here are patterned after the general style of the names 2154 * of the AT/ATS operations. 2155 * The values used are carefully arranged to make mmu_idx => EL lookup easy. 2156 */ 2157 #define ARM_MMU_IDX_A 0x10 /* A profile */ 2158 #define ARM_MMU_IDX_NOTLB 0x20 /* does not have a TLB */ 2159 #define ARM_MMU_IDX_M 0x40 /* M profile */ 2160 2161 #define ARM_MMU_IDX_TYPE_MASK (~0x7) 2162 #define ARM_MMU_IDX_COREIDX_MASK 0x7 2163 2164 typedef enum ARMMMUIdx { 2165 ARMMMUIdx_S12NSE0 = 0 | ARM_MMU_IDX_A, 2166 ARMMMUIdx_S12NSE1 = 1 | ARM_MMU_IDX_A, 2167 ARMMMUIdx_S1E2 = 2 | ARM_MMU_IDX_A, 2168 ARMMMUIdx_S1E3 = 3 | ARM_MMU_IDX_A, 2169 ARMMMUIdx_S1SE0 = 4 | ARM_MMU_IDX_A, 2170 ARMMMUIdx_S1SE1 = 5 | ARM_MMU_IDX_A, 2171 ARMMMUIdx_S2NS = 6 | ARM_MMU_IDX_A, 2172 ARMMMUIdx_MUser = 0 | ARM_MMU_IDX_M, 2173 ARMMMUIdx_MPriv = 1 | ARM_MMU_IDX_M, 2174 ARMMMUIdx_MNegPri = 2 | ARM_MMU_IDX_M, 2175 ARMMMUIdx_MSUser = 3 | ARM_MMU_IDX_M, 2176 ARMMMUIdx_MSPriv = 4 | ARM_MMU_IDX_M, 2177 ARMMMUIdx_MSNegPri = 5 | ARM_MMU_IDX_M, 2178 /* Indexes below here don't have TLBs and are used only for AT system 2179 * instructions or for the first stage of an S12 page table walk. 2180 */ 2181 ARMMMUIdx_S1NSE0 = 0 | ARM_MMU_IDX_NOTLB, 2182 ARMMMUIdx_S1NSE1 = 1 | ARM_MMU_IDX_NOTLB, 2183 } ARMMMUIdx; 2184 2185 /* Bit macros for the core-mmu-index values for each index, 2186 * for use when calling tlb_flush_by_mmuidx() and friends. 2187 */ 2188 typedef enum ARMMMUIdxBit { 2189 ARMMMUIdxBit_S12NSE0 = 1 << 0, 2190 ARMMMUIdxBit_S12NSE1 = 1 << 1, 2191 ARMMMUIdxBit_S1E2 = 1 << 2, 2192 ARMMMUIdxBit_S1E3 = 1 << 3, 2193 ARMMMUIdxBit_S1SE0 = 1 << 4, 2194 ARMMMUIdxBit_S1SE1 = 1 << 5, 2195 ARMMMUIdxBit_S2NS = 1 << 6, 2196 ARMMMUIdxBit_MUser = 1 << 0, 2197 ARMMMUIdxBit_MPriv = 1 << 1, 2198 ARMMMUIdxBit_MNegPri = 1 << 2, 2199 ARMMMUIdxBit_MSUser = 1 << 3, 2200 ARMMMUIdxBit_MSPriv = 1 << 4, 2201 ARMMMUIdxBit_MSNegPri = 1 << 5, 2202 } ARMMMUIdxBit; 2203 2204 #define MMU_USER_IDX 0 2205 2206 static inline int arm_to_core_mmu_idx(ARMMMUIdx mmu_idx) 2207 { 2208 return mmu_idx & ARM_MMU_IDX_COREIDX_MASK; 2209 } 2210 2211 static inline ARMMMUIdx core_to_arm_mmu_idx(CPUARMState *env, int mmu_idx) 2212 { 2213 if (arm_feature(env, ARM_FEATURE_M)) { 2214 return mmu_idx | ARM_MMU_IDX_M; 2215 } else { 2216 return mmu_idx | ARM_MMU_IDX_A; 2217 } 2218 } 2219 2220 /* Return the exception level we're running at if this is our mmu_idx */ 2221 static inline int arm_mmu_idx_to_el(ARMMMUIdx mmu_idx) 2222 { 2223 switch (mmu_idx & ARM_MMU_IDX_TYPE_MASK) { 2224 case ARM_MMU_IDX_A: 2225 return mmu_idx & 3; 2226 case ARM_MMU_IDX_M: 2227 return (mmu_idx == ARMMMUIdx_MUser || mmu_idx == ARMMMUIdx_MSUser) 2228 ? 0 : 1; 2229 default: 2230 g_assert_not_reached(); 2231 } 2232 } 2233 2234 /* Determine the current mmu_idx to use for normal loads/stores */ 2235 static inline int cpu_mmu_index(CPUARMState *env, bool ifetch) 2236 { 2237 int el = arm_current_el(env); 2238 2239 if (arm_feature(env, ARM_FEATURE_M)) { 2240 ARMMMUIdx mmu_idx = el == 0 ? ARMMMUIdx_MUser : ARMMMUIdx_MPriv; 2241 2242 /* Execution priority is negative if FAULTMASK is set or 2243 * we're in a HardFault or NMI handler. 2244 */ 2245 if ((env->v7m.exception > 0 && env->v7m.exception <= 3) 2246 || env->v7m.faultmask[env->v7m.secure]) { 2247 mmu_idx = ARMMMUIdx_MNegPri; 2248 } 2249 2250 if (env->v7m.secure) { 2251 mmu_idx += ARMMMUIdx_MSUser; 2252 } 2253 2254 return arm_to_core_mmu_idx(mmu_idx); 2255 } 2256 2257 if (el < 2 && arm_is_secure_below_el3(env)) { 2258 return arm_to_core_mmu_idx(ARMMMUIdx_S1SE0 + el); 2259 } 2260 return el; 2261 } 2262 2263 /* Indexes used when registering address spaces with cpu_address_space_init */ 2264 typedef enum ARMASIdx { 2265 ARMASIdx_NS = 0, 2266 ARMASIdx_S = 1, 2267 } ARMASIdx; 2268 2269 /* Return the Exception Level targeted by debug exceptions. */ 2270 static inline int arm_debug_target_el(CPUARMState *env) 2271 { 2272 bool secure = arm_is_secure(env); 2273 bool route_to_el2 = false; 2274 2275 if (arm_feature(env, ARM_FEATURE_EL2) && !secure) { 2276 route_to_el2 = env->cp15.hcr_el2 & HCR_TGE || 2277 env->cp15.mdcr_el2 & (1 << 8); 2278 } 2279 2280 if (route_to_el2) { 2281 return 2; 2282 } else if (arm_feature(env, ARM_FEATURE_EL3) && 2283 !arm_el_is_aa64(env, 3) && secure) { 2284 return 3; 2285 } else { 2286 return 1; 2287 } 2288 } 2289 2290 static inline bool aa64_generate_debug_exceptions(CPUARMState *env) 2291 { 2292 if (arm_is_secure(env)) { 2293 /* MDCR_EL3.SDD disables debug events from Secure state */ 2294 if (extract32(env->cp15.mdcr_el3, 16, 1) != 0 2295 || arm_current_el(env) == 3) { 2296 return false; 2297 } 2298 } 2299 2300 if (arm_current_el(env) == arm_debug_target_el(env)) { 2301 if ((extract32(env->cp15.mdscr_el1, 13, 1) == 0) 2302 || (env->daif & PSTATE_D)) { 2303 return false; 2304 } 2305 } 2306 return true; 2307 } 2308 2309 static inline bool aa32_generate_debug_exceptions(CPUARMState *env) 2310 { 2311 int el = arm_current_el(env); 2312 2313 if (el == 0 && arm_el_is_aa64(env, 1)) { 2314 return aa64_generate_debug_exceptions(env); 2315 } 2316 2317 if (arm_is_secure(env)) { 2318 int spd; 2319 2320 if (el == 0 && (env->cp15.sder & 1)) { 2321 /* SDER.SUIDEN means debug exceptions from Secure EL0 2322 * are always enabled. Otherwise they are controlled by 2323 * SDCR.SPD like those from other Secure ELs. 2324 */ 2325 return true; 2326 } 2327 2328 spd = extract32(env->cp15.mdcr_el3, 14, 2); 2329 switch (spd) { 2330 case 1: 2331 /* SPD == 0b01 is reserved, but behaves as 0b00. */ 2332 case 0: 2333 /* For 0b00 we return true if external secure invasive debug 2334 * is enabled. On real hardware this is controlled by external 2335 * signals to the core. QEMU always permits debug, and behaves 2336 * as if DBGEN, SPIDEN, NIDEN and SPNIDEN are all tied high. 2337 */ 2338 return true; 2339 case 2: 2340 return false; 2341 case 3: 2342 return true; 2343 } 2344 } 2345 2346 return el != 2; 2347 } 2348 2349 /* Return true if debugging exceptions are currently enabled. 2350 * This corresponds to what in ARM ARM pseudocode would be 2351 * if UsingAArch32() then 2352 * return AArch32.GenerateDebugExceptions() 2353 * else 2354 * return AArch64.GenerateDebugExceptions() 2355 * We choose to push the if() down into this function for clarity, 2356 * since the pseudocode has it at all callsites except for the one in 2357 * CheckSoftwareStep(), where it is elided because both branches would 2358 * always return the same value. 2359 * 2360 * Parts of the pseudocode relating to EL2 and EL3 are omitted because we 2361 * don't yet implement those exception levels or their associated trap bits. 2362 */ 2363 static inline bool arm_generate_debug_exceptions(CPUARMState *env) 2364 { 2365 if (env->aarch64) { 2366 return aa64_generate_debug_exceptions(env); 2367 } else { 2368 return aa32_generate_debug_exceptions(env); 2369 } 2370 } 2371 2372 /* Is single-stepping active? (Note that the "is EL_D AArch64?" check 2373 * implicitly means this always returns false in pre-v8 CPUs.) 2374 */ 2375 static inline bool arm_singlestep_active(CPUARMState *env) 2376 { 2377 return extract32(env->cp15.mdscr_el1, 0, 1) 2378 && arm_el_is_aa64(env, arm_debug_target_el(env)) 2379 && arm_generate_debug_exceptions(env); 2380 } 2381 2382 static inline bool arm_sctlr_b(CPUARMState *env) 2383 { 2384 return 2385 /* We need not implement SCTLR.ITD in user-mode emulation, so 2386 * let linux-user ignore the fact that it conflicts with SCTLR_B. 2387 * This lets people run BE32 binaries with "-cpu any". 2388 */ 2389 #ifndef CONFIG_USER_ONLY 2390 !arm_feature(env, ARM_FEATURE_V7) && 2391 #endif 2392 (env->cp15.sctlr_el[1] & SCTLR_B) != 0; 2393 } 2394 2395 /* Return true if the processor is in big-endian mode. */ 2396 static inline bool arm_cpu_data_is_big_endian(CPUARMState *env) 2397 { 2398 int cur_el; 2399 2400 /* In 32bit endianness is determined by looking at CPSR's E bit */ 2401 if (!is_a64(env)) { 2402 return 2403 #ifdef CONFIG_USER_ONLY 2404 /* In system mode, BE32 is modelled in line with the 2405 * architecture (as word-invariant big-endianness), where loads 2406 * and stores are done little endian but from addresses which 2407 * are adjusted by XORing with the appropriate constant. So the 2408 * endianness to use for the raw data access is not affected by 2409 * SCTLR.B. 2410 * In user mode, however, we model BE32 as byte-invariant 2411 * big-endianness (because user-only code cannot tell the 2412 * difference), and so we need to use a data access endianness 2413 * that depends on SCTLR.B. 2414 */ 2415 arm_sctlr_b(env) || 2416 #endif 2417 ((env->uncached_cpsr & CPSR_E) ? 1 : 0); 2418 } 2419 2420 cur_el = arm_current_el(env); 2421 2422 if (cur_el == 0) { 2423 return (env->cp15.sctlr_el[1] & SCTLR_E0E) != 0; 2424 } 2425 2426 return (env->cp15.sctlr_el[cur_el] & SCTLR_EE) != 0; 2427 } 2428 2429 #include "exec/cpu-all.h" 2430 2431 /* Bit usage in the TB flags field: bit 31 indicates whether we are 2432 * in 32 or 64 bit mode. The meaning of the other bits depends on that. 2433 * We put flags which are shared between 32 and 64 bit mode at the top 2434 * of the word, and flags which apply to only one mode at the bottom. 2435 */ 2436 #define ARM_TBFLAG_AARCH64_STATE_SHIFT 31 2437 #define ARM_TBFLAG_AARCH64_STATE_MASK (1U << ARM_TBFLAG_AARCH64_STATE_SHIFT) 2438 #define ARM_TBFLAG_MMUIDX_SHIFT 28 2439 #define ARM_TBFLAG_MMUIDX_MASK (0x7 << ARM_TBFLAG_MMUIDX_SHIFT) 2440 #define ARM_TBFLAG_SS_ACTIVE_SHIFT 27 2441 #define ARM_TBFLAG_SS_ACTIVE_MASK (1 << ARM_TBFLAG_SS_ACTIVE_SHIFT) 2442 #define ARM_TBFLAG_PSTATE_SS_SHIFT 26 2443 #define ARM_TBFLAG_PSTATE_SS_MASK (1 << ARM_TBFLAG_PSTATE_SS_SHIFT) 2444 /* Target EL if we take a floating-point-disabled exception */ 2445 #define ARM_TBFLAG_FPEXC_EL_SHIFT 24 2446 #define ARM_TBFLAG_FPEXC_EL_MASK (0x3 << ARM_TBFLAG_FPEXC_EL_SHIFT) 2447 2448 /* Bit usage when in AArch32 state: */ 2449 #define ARM_TBFLAG_THUMB_SHIFT 0 2450 #define ARM_TBFLAG_THUMB_MASK (1 << ARM_TBFLAG_THUMB_SHIFT) 2451 #define ARM_TBFLAG_VECLEN_SHIFT 1 2452 #define ARM_TBFLAG_VECLEN_MASK (0x7 << ARM_TBFLAG_VECLEN_SHIFT) 2453 #define ARM_TBFLAG_VECSTRIDE_SHIFT 4 2454 #define ARM_TBFLAG_VECSTRIDE_MASK (0x3 << ARM_TBFLAG_VECSTRIDE_SHIFT) 2455 #define ARM_TBFLAG_VFPEN_SHIFT 7 2456 #define ARM_TBFLAG_VFPEN_MASK (1 << ARM_TBFLAG_VFPEN_SHIFT) 2457 #define ARM_TBFLAG_CONDEXEC_SHIFT 8 2458 #define ARM_TBFLAG_CONDEXEC_MASK (0xff << ARM_TBFLAG_CONDEXEC_SHIFT) 2459 #define ARM_TBFLAG_SCTLR_B_SHIFT 16 2460 #define ARM_TBFLAG_SCTLR_B_MASK (1 << ARM_TBFLAG_SCTLR_B_SHIFT) 2461 /* We store the bottom two bits of the CPAR as TB flags and handle 2462 * checks on the other bits at runtime 2463 */ 2464 #define ARM_TBFLAG_XSCALE_CPAR_SHIFT 17 2465 #define ARM_TBFLAG_XSCALE_CPAR_MASK (3 << ARM_TBFLAG_XSCALE_CPAR_SHIFT) 2466 /* Indicates whether cp register reads and writes by guest code should access 2467 * the secure or nonsecure bank of banked registers; note that this is not 2468 * the same thing as the current security state of the processor! 2469 */ 2470 #define ARM_TBFLAG_NS_SHIFT 19 2471 #define ARM_TBFLAG_NS_MASK (1 << ARM_TBFLAG_NS_SHIFT) 2472 #define ARM_TBFLAG_BE_DATA_SHIFT 20 2473 #define ARM_TBFLAG_BE_DATA_MASK (1 << ARM_TBFLAG_BE_DATA_SHIFT) 2474 /* For M profile only, Handler (ie not Thread) mode */ 2475 #define ARM_TBFLAG_HANDLER_SHIFT 21 2476 #define ARM_TBFLAG_HANDLER_MASK (1 << ARM_TBFLAG_HANDLER_SHIFT) 2477 2478 /* Bit usage when in AArch64 state */ 2479 #define ARM_TBFLAG_TBI0_SHIFT 0 /* TBI0 for EL0/1 or TBI for EL2/3 */ 2480 #define ARM_TBFLAG_TBI0_MASK (0x1ull << ARM_TBFLAG_TBI0_SHIFT) 2481 #define ARM_TBFLAG_TBI1_SHIFT 1 /* TBI1 for EL0/1 */ 2482 #define ARM_TBFLAG_TBI1_MASK (0x1ull << ARM_TBFLAG_TBI1_SHIFT) 2483 2484 /* some convenience accessor macros */ 2485 #define ARM_TBFLAG_AARCH64_STATE(F) \ 2486 (((F) & ARM_TBFLAG_AARCH64_STATE_MASK) >> ARM_TBFLAG_AARCH64_STATE_SHIFT) 2487 #define ARM_TBFLAG_MMUIDX(F) \ 2488 (((F) & ARM_TBFLAG_MMUIDX_MASK) >> ARM_TBFLAG_MMUIDX_SHIFT) 2489 #define ARM_TBFLAG_SS_ACTIVE(F) \ 2490 (((F) & ARM_TBFLAG_SS_ACTIVE_MASK) >> ARM_TBFLAG_SS_ACTIVE_SHIFT) 2491 #define ARM_TBFLAG_PSTATE_SS(F) \ 2492 (((F) & ARM_TBFLAG_PSTATE_SS_MASK) >> ARM_TBFLAG_PSTATE_SS_SHIFT) 2493 #define ARM_TBFLAG_FPEXC_EL(F) \ 2494 (((F) & ARM_TBFLAG_FPEXC_EL_MASK) >> ARM_TBFLAG_FPEXC_EL_SHIFT) 2495 #define ARM_TBFLAG_THUMB(F) \ 2496 (((F) & ARM_TBFLAG_THUMB_MASK) >> ARM_TBFLAG_THUMB_SHIFT) 2497 #define ARM_TBFLAG_VECLEN(F) \ 2498 (((F) & ARM_TBFLAG_VECLEN_MASK) >> ARM_TBFLAG_VECLEN_SHIFT) 2499 #define ARM_TBFLAG_VECSTRIDE(F) \ 2500 (((F) & ARM_TBFLAG_VECSTRIDE_MASK) >> ARM_TBFLAG_VECSTRIDE_SHIFT) 2501 #define ARM_TBFLAG_VFPEN(F) \ 2502 (((F) & ARM_TBFLAG_VFPEN_MASK) >> ARM_TBFLAG_VFPEN_SHIFT) 2503 #define ARM_TBFLAG_CONDEXEC(F) \ 2504 (((F) & ARM_TBFLAG_CONDEXEC_MASK) >> ARM_TBFLAG_CONDEXEC_SHIFT) 2505 #define ARM_TBFLAG_SCTLR_B(F) \ 2506 (((F) & ARM_TBFLAG_SCTLR_B_MASK) >> ARM_TBFLAG_SCTLR_B_SHIFT) 2507 #define ARM_TBFLAG_XSCALE_CPAR(F) \ 2508 (((F) & ARM_TBFLAG_XSCALE_CPAR_MASK) >> ARM_TBFLAG_XSCALE_CPAR_SHIFT) 2509 #define ARM_TBFLAG_NS(F) \ 2510 (((F) & ARM_TBFLAG_NS_MASK) >> ARM_TBFLAG_NS_SHIFT) 2511 #define ARM_TBFLAG_BE_DATA(F) \ 2512 (((F) & ARM_TBFLAG_BE_DATA_MASK) >> ARM_TBFLAG_BE_DATA_SHIFT) 2513 #define ARM_TBFLAG_HANDLER(F) \ 2514 (((F) & ARM_TBFLAG_HANDLER_MASK) >> ARM_TBFLAG_HANDLER_SHIFT) 2515 #define ARM_TBFLAG_TBI0(F) \ 2516 (((F) & ARM_TBFLAG_TBI0_MASK) >> ARM_TBFLAG_TBI0_SHIFT) 2517 #define ARM_TBFLAG_TBI1(F) \ 2518 (((F) & ARM_TBFLAG_TBI1_MASK) >> ARM_TBFLAG_TBI1_SHIFT) 2519 2520 static inline bool bswap_code(bool sctlr_b) 2521 { 2522 #ifdef CONFIG_USER_ONLY 2523 /* BE8 (SCTLR.B = 0, TARGET_WORDS_BIGENDIAN = 1) is mixed endian. 2524 * The invalid combination SCTLR.B=1/CPSR.E=1/TARGET_WORDS_BIGENDIAN=0 2525 * would also end up as a mixed-endian mode with BE code, LE data. 2526 */ 2527 return 2528 #ifdef TARGET_WORDS_BIGENDIAN 2529 1 ^ 2530 #endif 2531 sctlr_b; 2532 #else 2533 /* All code access in ARM is little endian, and there are no loaders 2534 * doing swaps that need to be reversed 2535 */ 2536 return 0; 2537 #endif 2538 } 2539 2540 /* Return the exception level to which FP-disabled exceptions should 2541 * be taken, or 0 if FP is enabled. 2542 */ 2543 static inline int fp_exception_el(CPUARMState *env) 2544 { 2545 int fpen; 2546 int cur_el = arm_current_el(env); 2547 2548 /* CPACR and the CPTR registers don't exist before v6, so FP is 2549 * always accessible 2550 */ 2551 if (!arm_feature(env, ARM_FEATURE_V6)) { 2552 return 0; 2553 } 2554 2555 /* The CPACR controls traps to EL1, or PL1 if we're 32 bit: 2556 * 0, 2 : trap EL0 and EL1/PL1 accesses 2557 * 1 : trap only EL0 accesses 2558 * 3 : trap no accesses 2559 */ 2560 fpen = extract32(env->cp15.cpacr_el1, 20, 2); 2561 switch (fpen) { 2562 case 0: 2563 case 2: 2564 if (cur_el == 0 || cur_el == 1) { 2565 /* Trap to PL1, which might be EL1 or EL3 */ 2566 if (arm_is_secure(env) && !arm_el_is_aa64(env, 3)) { 2567 return 3; 2568 } 2569 return 1; 2570 } 2571 if (cur_el == 3 && !is_a64(env)) { 2572 /* Secure PL1 running at EL3 */ 2573 return 3; 2574 } 2575 break; 2576 case 1: 2577 if (cur_el == 0) { 2578 return 1; 2579 } 2580 break; 2581 case 3: 2582 break; 2583 } 2584 2585 /* For the CPTR registers we don't need to guard with an ARM_FEATURE 2586 * check because zero bits in the registers mean "don't trap". 2587 */ 2588 2589 /* CPTR_EL2 : present in v7VE or v8 */ 2590 if (cur_el <= 2 && extract32(env->cp15.cptr_el[2], 10, 1) 2591 && !arm_is_secure_below_el3(env)) { 2592 /* Trap FP ops at EL2, NS-EL1 or NS-EL0 to EL2 */ 2593 return 2; 2594 } 2595 2596 /* CPTR_EL3 : present in v8 */ 2597 if (extract32(env->cp15.cptr_el[3], 10, 1)) { 2598 /* Trap all FP ops to EL3 */ 2599 return 3; 2600 } 2601 2602 return 0; 2603 } 2604 2605 #ifdef CONFIG_USER_ONLY 2606 static inline bool arm_cpu_bswap_data(CPUARMState *env) 2607 { 2608 return 2609 #ifdef TARGET_WORDS_BIGENDIAN 2610 1 ^ 2611 #endif 2612 arm_cpu_data_is_big_endian(env); 2613 } 2614 #endif 2615 2616 #ifndef CONFIG_USER_ONLY 2617 /** 2618 * arm_regime_tbi0: 2619 * @env: CPUARMState 2620 * @mmu_idx: MMU index indicating required translation regime 2621 * 2622 * Extracts the TBI0 value from the appropriate TCR for the current EL 2623 * 2624 * Returns: the TBI0 value. 2625 */ 2626 uint32_t arm_regime_tbi0(CPUARMState *env, ARMMMUIdx mmu_idx); 2627 2628 /** 2629 * arm_regime_tbi1: 2630 * @env: CPUARMState 2631 * @mmu_idx: MMU index indicating required translation regime 2632 * 2633 * Extracts the TBI1 value from the appropriate TCR for the current EL 2634 * 2635 * Returns: the TBI1 value. 2636 */ 2637 uint32_t arm_regime_tbi1(CPUARMState *env, ARMMMUIdx mmu_idx); 2638 #else 2639 /* We can't handle tagged addresses properly in user-only mode */ 2640 static inline uint32_t arm_regime_tbi0(CPUARMState *env, ARMMMUIdx mmu_idx) 2641 { 2642 return 0; 2643 } 2644 2645 static inline uint32_t arm_regime_tbi1(CPUARMState *env, ARMMMUIdx mmu_idx) 2646 { 2647 return 0; 2648 } 2649 #endif 2650 2651 static inline void cpu_get_tb_cpu_state(CPUARMState *env, target_ulong *pc, 2652 target_ulong *cs_base, uint32_t *flags) 2653 { 2654 ARMMMUIdx mmu_idx = core_to_arm_mmu_idx(env, cpu_mmu_index(env, false)); 2655 if (is_a64(env)) { 2656 *pc = env->pc; 2657 *flags = ARM_TBFLAG_AARCH64_STATE_MASK; 2658 /* Get control bits for tagged addresses */ 2659 *flags |= (arm_regime_tbi0(env, mmu_idx) << ARM_TBFLAG_TBI0_SHIFT); 2660 *flags |= (arm_regime_tbi1(env, mmu_idx) << ARM_TBFLAG_TBI1_SHIFT); 2661 } else { 2662 *pc = env->regs[15]; 2663 *flags = (env->thumb << ARM_TBFLAG_THUMB_SHIFT) 2664 | (env->vfp.vec_len << ARM_TBFLAG_VECLEN_SHIFT) 2665 | (env->vfp.vec_stride << ARM_TBFLAG_VECSTRIDE_SHIFT) 2666 | (env->condexec_bits << ARM_TBFLAG_CONDEXEC_SHIFT) 2667 | (arm_sctlr_b(env) << ARM_TBFLAG_SCTLR_B_SHIFT); 2668 if (!(access_secure_reg(env))) { 2669 *flags |= ARM_TBFLAG_NS_MASK; 2670 } 2671 if (env->vfp.xregs[ARM_VFP_FPEXC] & (1 << 30) 2672 || arm_el_is_aa64(env, 1)) { 2673 *flags |= ARM_TBFLAG_VFPEN_MASK; 2674 } 2675 *flags |= (extract32(env->cp15.c15_cpar, 0, 2) 2676 << ARM_TBFLAG_XSCALE_CPAR_SHIFT); 2677 } 2678 2679 *flags |= (arm_to_core_mmu_idx(mmu_idx) << ARM_TBFLAG_MMUIDX_SHIFT); 2680 2681 /* The SS_ACTIVE and PSTATE_SS bits correspond to the state machine 2682 * states defined in the ARM ARM for software singlestep: 2683 * SS_ACTIVE PSTATE.SS State 2684 * 0 x Inactive (the TB flag for SS is always 0) 2685 * 1 0 Active-pending 2686 * 1 1 Active-not-pending 2687 */ 2688 if (arm_singlestep_active(env)) { 2689 *flags |= ARM_TBFLAG_SS_ACTIVE_MASK; 2690 if (is_a64(env)) { 2691 if (env->pstate & PSTATE_SS) { 2692 *flags |= ARM_TBFLAG_PSTATE_SS_MASK; 2693 } 2694 } else { 2695 if (env->uncached_cpsr & PSTATE_SS) { 2696 *flags |= ARM_TBFLAG_PSTATE_SS_MASK; 2697 } 2698 } 2699 } 2700 if (arm_cpu_data_is_big_endian(env)) { 2701 *flags |= ARM_TBFLAG_BE_DATA_MASK; 2702 } 2703 *flags |= fp_exception_el(env) << ARM_TBFLAG_FPEXC_EL_SHIFT; 2704 2705 if (arm_v7m_is_handler_mode(env)) { 2706 *flags |= ARM_TBFLAG_HANDLER_MASK; 2707 } 2708 2709 *cs_base = 0; 2710 } 2711 2712 enum { 2713 QEMU_PSCI_CONDUIT_DISABLED = 0, 2714 QEMU_PSCI_CONDUIT_SMC = 1, 2715 QEMU_PSCI_CONDUIT_HVC = 2, 2716 }; 2717 2718 #ifndef CONFIG_USER_ONLY 2719 /* Return the address space index to use for a memory access */ 2720 static inline int arm_asidx_from_attrs(CPUState *cs, MemTxAttrs attrs) 2721 { 2722 return attrs.secure ? ARMASIdx_S : ARMASIdx_NS; 2723 } 2724 2725 /* Return the AddressSpace to use for a memory access 2726 * (which depends on whether the access is S or NS, and whether 2727 * the board gave us a separate AddressSpace for S accesses). 2728 */ 2729 static inline AddressSpace *arm_addressspace(CPUState *cs, MemTxAttrs attrs) 2730 { 2731 return cpu_get_address_space(cs, arm_asidx_from_attrs(cs, attrs)); 2732 } 2733 #endif 2734 2735 /** 2736 * arm_register_el_change_hook: 2737 * Register a hook function which will be called back whenever this 2738 * CPU changes exception level or mode. The hook function will be 2739 * passed a pointer to the ARMCPU and the opaque data pointer passed 2740 * to this function when the hook was registered. 2741 * 2742 * Note that we currently only support registering a single hook function, 2743 * and will assert if this function is called twice. 2744 * This facility is intended for the use of the GICv3 emulation. 2745 */ 2746 void arm_register_el_change_hook(ARMCPU *cpu, ARMELChangeHook *hook, 2747 void *opaque); 2748 2749 /** 2750 * arm_get_el_change_hook_opaque: 2751 * Return the opaque data that will be used by the el_change_hook 2752 * for this CPU. 2753 */ 2754 static inline void *arm_get_el_change_hook_opaque(ARMCPU *cpu) 2755 { 2756 return cpu->el_change_hook_opaque; 2757 } 2758 2759 #endif 2760