1 /* 2 * ARM virtual CPU header 3 * 4 * Copyright (c) 2003 Fabrice Bellard 5 * 6 * This library is free software; you can redistribute it and/or 7 * modify it under the terms of the GNU Lesser General Public 8 * License as published by the Free Software Foundation; either 9 * version 2 of the License, or (at your option) any later version. 10 * 11 * This library is distributed in the hope that it will be useful, 12 * but WITHOUT ANY WARRANTY; without even the implied warranty of 13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU 14 * Lesser General Public License for more details. 15 * 16 * You should have received a copy of the GNU Lesser General Public 17 * License along with this library; if not, see <http://www.gnu.org/licenses/>. 18 */ 19 20 #ifndef ARM_CPU_H 21 #define ARM_CPU_H 22 23 #include "kvm-consts.h" 24 #include "hw/registerfields.h" 25 26 #if defined(TARGET_AARCH64) 27 /* AArch64 definitions */ 28 # define TARGET_LONG_BITS 64 29 #else 30 # define TARGET_LONG_BITS 32 31 #endif 32 33 /* ARM processors have a weak memory model */ 34 #define TCG_GUEST_DEFAULT_MO (0) 35 36 #define CPUArchState struct CPUARMState 37 38 #include "qemu-common.h" 39 #include "cpu-qom.h" 40 #include "exec/cpu-defs.h" 41 42 #define EXCP_UDEF 1 /* undefined instruction */ 43 #define EXCP_SWI 2 /* software interrupt */ 44 #define EXCP_PREFETCH_ABORT 3 45 #define EXCP_DATA_ABORT 4 46 #define EXCP_IRQ 5 47 #define EXCP_FIQ 6 48 #define EXCP_BKPT 7 49 #define EXCP_EXCEPTION_EXIT 8 /* Return from v7M exception. */ 50 #define EXCP_KERNEL_TRAP 9 /* Jumped to kernel code page. */ 51 #define EXCP_HVC 11 /* HyperVisor Call */ 52 #define EXCP_HYP_TRAP 12 53 #define EXCP_SMC 13 /* Secure Monitor Call */ 54 #define EXCP_VIRQ 14 55 #define EXCP_VFIQ 15 56 #define EXCP_SEMIHOST 16 /* semihosting call */ 57 #define EXCP_NOCP 17 /* v7M NOCP UsageFault */ 58 #define EXCP_INVSTATE 18 /* v7M INVSTATE UsageFault */ 59 #define EXCP_STKOF 19 /* v8M STKOF UsageFault */ 60 /* NB: add new EXCP_ defines to the array in arm_log_exception() too */ 61 62 #define ARMV7M_EXCP_RESET 1 63 #define ARMV7M_EXCP_NMI 2 64 #define ARMV7M_EXCP_HARD 3 65 #define ARMV7M_EXCP_MEM 4 66 #define ARMV7M_EXCP_BUS 5 67 #define ARMV7M_EXCP_USAGE 6 68 #define ARMV7M_EXCP_SECURE 7 69 #define ARMV7M_EXCP_SVC 11 70 #define ARMV7M_EXCP_DEBUG 12 71 #define ARMV7M_EXCP_PENDSV 14 72 #define ARMV7M_EXCP_SYSTICK 15 73 74 /* For M profile, some registers are banked secure vs non-secure; 75 * these are represented as a 2-element array where the first element 76 * is the non-secure copy and the second is the secure copy. 77 * When the CPU does not have implement the security extension then 78 * only the first element is used. 79 * This means that the copy for the current security state can be 80 * accessed via env->registerfield[env->v7m.secure] (whether the security 81 * extension is implemented or not). 82 */ 83 enum { 84 M_REG_NS = 0, 85 M_REG_S = 1, 86 M_REG_NUM_BANKS = 2, 87 }; 88 89 /* ARM-specific interrupt pending bits. */ 90 #define CPU_INTERRUPT_FIQ CPU_INTERRUPT_TGT_EXT_1 91 #define CPU_INTERRUPT_VIRQ CPU_INTERRUPT_TGT_EXT_2 92 #define CPU_INTERRUPT_VFIQ CPU_INTERRUPT_TGT_EXT_3 93 94 /* The usual mapping for an AArch64 system register to its AArch32 95 * counterpart is for the 32 bit world to have access to the lower 96 * half only (with writes leaving the upper half untouched). It's 97 * therefore useful to be able to pass TCG the offset of the least 98 * significant half of a uint64_t struct member. 99 */ 100 #ifdef HOST_WORDS_BIGENDIAN 101 #define offsetoflow32(S, M) (offsetof(S, M) + sizeof(uint32_t)) 102 #define offsetofhigh32(S, M) offsetof(S, M) 103 #else 104 #define offsetoflow32(S, M) offsetof(S, M) 105 #define offsetofhigh32(S, M) (offsetof(S, M) + sizeof(uint32_t)) 106 #endif 107 108 /* Meanings of the ARMCPU object's four inbound GPIO lines */ 109 #define ARM_CPU_IRQ 0 110 #define ARM_CPU_FIQ 1 111 #define ARM_CPU_VIRQ 2 112 #define ARM_CPU_VFIQ 3 113 114 #define NB_MMU_MODES 8 115 /* ARM-specific extra insn start words: 116 * 1: Conditional execution bits 117 * 2: Partial exception syndrome for data aborts 118 */ 119 #define TARGET_INSN_START_EXTRA_WORDS 2 120 121 /* The 2nd extra word holding syndrome info for data aborts does not use 122 * the upper 6 bits nor the lower 14 bits. We mask and shift it down to 123 * help the sleb128 encoder do a better job. 124 * When restoring the CPU state, we shift it back up. 125 */ 126 #define ARM_INSN_START_WORD2_MASK ((1 << 26) - 1) 127 #define ARM_INSN_START_WORD2_SHIFT 14 128 129 /* We currently assume float and double are IEEE single and double 130 precision respectively. 131 Doing runtime conversions is tricky because VFP registers may contain 132 integer values (eg. as the result of a FTOSI instruction). 133 s<2n> maps to the least significant half of d<n> 134 s<2n+1> maps to the most significant half of d<n> 135 */ 136 137 /** 138 * DynamicGDBXMLInfo: 139 * @desc: Contains the XML descriptions. 140 * @num_cpregs: Number of the Coprocessor registers seen by GDB. 141 * @cpregs_keys: Array that contains the corresponding Key of 142 * a given cpreg with the same order of the cpreg in the XML description. 143 */ 144 typedef struct DynamicGDBXMLInfo { 145 char *desc; 146 int num_cpregs; 147 uint32_t *cpregs_keys; 148 } DynamicGDBXMLInfo; 149 150 /* CPU state for each instance of a generic timer (in cp15 c14) */ 151 typedef struct ARMGenericTimer { 152 uint64_t cval; /* Timer CompareValue register */ 153 uint64_t ctl; /* Timer Control register */ 154 } ARMGenericTimer; 155 156 #define GTIMER_PHYS 0 157 #define GTIMER_VIRT 1 158 #define GTIMER_HYP 2 159 #define GTIMER_SEC 3 160 #define NUM_GTIMERS 4 161 162 typedef struct { 163 uint64_t raw_tcr; 164 uint32_t mask; 165 uint32_t base_mask; 166 } TCR; 167 168 /* Define a maximum sized vector register. 169 * For 32-bit, this is a 128-bit NEON/AdvSIMD register. 170 * For 64-bit, this is a 2048-bit SVE register. 171 * 172 * Note that the mapping between S, D, and Q views of the register bank 173 * differs between AArch64 and AArch32. 174 * In AArch32: 175 * Qn = regs[n].d[1]:regs[n].d[0] 176 * Dn = regs[n / 2].d[n & 1] 177 * Sn = regs[n / 4].d[n % 4 / 2], 178 * bits 31..0 for even n, and bits 63..32 for odd n 179 * (and regs[16] to regs[31] are inaccessible) 180 * In AArch64: 181 * Zn = regs[n].d[*] 182 * Qn = regs[n].d[1]:regs[n].d[0] 183 * Dn = regs[n].d[0] 184 * Sn = regs[n].d[0] bits 31..0 185 * Hn = regs[n].d[0] bits 15..0 186 * 187 * This corresponds to the architecturally defined mapping between 188 * the two execution states, and means we do not need to explicitly 189 * map these registers when changing states. 190 * 191 * Align the data for use with TCG host vector operations. 192 */ 193 194 #ifdef TARGET_AARCH64 195 # define ARM_MAX_VQ 16 196 #else 197 # define ARM_MAX_VQ 1 198 #endif 199 200 typedef struct ARMVectorReg { 201 uint64_t d[2 * ARM_MAX_VQ] QEMU_ALIGNED(16); 202 } ARMVectorReg; 203 204 /* In AArch32 mode, predicate registers do not exist at all. */ 205 #ifdef TARGET_AARCH64 206 typedef struct ARMPredicateReg { 207 uint64_t p[2 * ARM_MAX_VQ / 8] QEMU_ALIGNED(16); 208 } ARMPredicateReg; 209 #endif 210 211 212 typedef struct CPUARMState { 213 /* Regs for current mode. */ 214 uint32_t regs[16]; 215 216 /* 32/64 switch only happens when taking and returning from 217 * exceptions so the overlap semantics are taken care of then 218 * instead of having a complicated union. 219 */ 220 /* Regs for A64 mode. */ 221 uint64_t xregs[32]; 222 uint64_t pc; 223 /* PSTATE isn't an architectural register for ARMv8. However, it is 224 * convenient for us to assemble the underlying state into a 32 bit format 225 * identical to the architectural format used for the SPSR. (This is also 226 * what the Linux kernel's 'pstate' field in signal handlers and KVM's 227 * 'pstate' register are.) Of the PSTATE bits: 228 * NZCV are kept in the split out env->CF/VF/NF/ZF, (which have the same 229 * semantics as for AArch32, as described in the comments on each field) 230 * nRW (also known as M[4]) is kept, inverted, in env->aarch64 231 * DAIF (exception masks) are kept in env->daif 232 * all other bits are stored in their correct places in env->pstate 233 */ 234 uint32_t pstate; 235 uint32_t aarch64; /* 1 if CPU is in aarch64 state; inverse of PSTATE.nRW */ 236 237 /* Frequently accessed CPSR bits are stored separately for efficiency. 238 This contains all the other bits. Use cpsr_{read,write} to access 239 the whole CPSR. */ 240 uint32_t uncached_cpsr; 241 uint32_t spsr; 242 243 /* Banked registers. */ 244 uint64_t banked_spsr[8]; 245 uint32_t banked_r13[8]; 246 uint32_t banked_r14[8]; 247 248 /* These hold r8-r12. */ 249 uint32_t usr_regs[5]; 250 uint32_t fiq_regs[5]; 251 252 /* cpsr flag cache for faster execution */ 253 uint32_t CF; /* 0 or 1 */ 254 uint32_t VF; /* V is the bit 31. All other bits are undefined */ 255 uint32_t NF; /* N is bit 31. All other bits are undefined. */ 256 uint32_t ZF; /* Z set if zero. */ 257 uint32_t QF; /* 0 or 1 */ 258 uint32_t GE; /* cpsr[19:16] */ 259 uint32_t thumb; /* cpsr[5]. 0 = arm mode, 1 = thumb mode. */ 260 uint32_t condexec_bits; /* IT bits. cpsr[15:10,26:25]. */ 261 uint64_t daif; /* exception masks, in the bits they are in PSTATE */ 262 263 uint64_t elr_el[4]; /* AArch64 exception link regs */ 264 uint64_t sp_el[4]; /* AArch64 banked stack pointers */ 265 266 /* System control coprocessor (cp15) */ 267 struct { 268 uint32_t c0_cpuid; 269 union { /* Cache size selection */ 270 struct { 271 uint64_t _unused_csselr0; 272 uint64_t csselr_ns; 273 uint64_t _unused_csselr1; 274 uint64_t csselr_s; 275 }; 276 uint64_t csselr_el[4]; 277 }; 278 union { /* System control register. */ 279 struct { 280 uint64_t _unused_sctlr; 281 uint64_t sctlr_ns; 282 uint64_t hsctlr; 283 uint64_t sctlr_s; 284 }; 285 uint64_t sctlr_el[4]; 286 }; 287 uint64_t cpacr_el1; /* Architectural feature access control register */ 288 uint64_t cptr_el[4]; /* ARMv8 feature trap registers */ 289 uint32_t c1_xscaleauxcr; /* XScale auxiliary control register. */ 290 uint64_t sder; /* Secure debug enable register. */ 291 uint32_t nsacr; /* Non-secure access control register. */ 292 union { /* MMU translation table base 0. */ 293 struct { 294 uint64_t _unused_ttbr0_0; 295 uint64_t ttbr0_ns; 296 uint64_t _unused_ttbr0_1; 297 uint64_t ttbr0_s; 298 }; 299 uint64_t ttbr0_el[4]; 300 }; 301 union { /* MMU translation table base 1. */ 302 struct { 303 uint64_t _unused_ttbr1_0; 304 uint64_t ttbr1_ns; 305 uint64_t _unused_ttbr1_1; 306 uint64_t ttbr1_s; 307 }; 308 uint64_t ttbr1_el[4]; 309 }; 310 uint64_t vttbr_el2; /* Virtualization Translation Table Base. */ 311 /* MMU translation table base control. */ 312 TCR tcr_el[4]; 313 TCR vtcr_el2; /* Virtualization Translation Control. */ 314 uint32_t c2_data; /* MPU data cacheable bits. */ 315 uint32_t c2_insn; /* MPU instruction cacheable bits. */ 316 union { /* MMU domain access control register 317 * MPU write buffer control. 318 */ 319 struct { 320 uint64_t dacr_ns; 321 uint64_t dacr_s; 322 }; 323 struct { 324 uint64_t dacr32_el2; 325 }; 326 }; 327 uint32_t pmsav5_data_ap; /* PMSAv5 MPU data access permissions */ 328 uint32_t pmsav5_insn_ap; /* PMSAv5 MPU insn access permissions */ 329 uint64_t hcr_el2; /* Hypervisor configuration register */ 330 uint64_t scr_el3; /* Secure configuration register. */ 331 union { /* Fault status registers. */ 332 struct { 333 uint64_t ifsr_ns; 334 uint64_t ifsr_s; 335 }; 336 struct { 337 uint64_t ifsr32_el2; 338 }; 339 }; 340 union { 341 struct { 342 uint64_t _unused_dfsr; 343 uint64_t dfsr_ns; 344 uint64_t hsr; 345 uint64_t dfsr_s; 346 }; 347 uint64_t esr_el[4]; 348 }; 349 uint32_t c6_region[8]; /* MPU base/size registers. */ 350 union { /* Fault address registers. */ 351 struct { 352 uint64_t _unused_far0; 353 #ifdef HOST_WORDS_BIGENDIAN 354 uint32_t ifar_ns; 355 uint32_t dfar_ns; 356 uint32_t ifar_s; 357 uint32_t dfar_s; 358 #else 359 uint32_t dfar_ns; 360 uint32_t ifar_ns; 361 uint32_t dfar_s; 362 uint32_t ifar_s; 363 #endif 364 uint64_t _unused_far3; 365 }; 366 uint64_t far_el[4]; 367 }; 368 uint64_t hpfar_el2; 369 uint64_t hstr_el2; 370 union { /* Translation result. */ 371 struct { 372 uint64_t _unused_par_0; 373 uint64_t par_ns; 374 uint64_t _unused_par_1; 375 uint64_t par_s; 376 }; 377 uint64_t par_el[4]; 378 }; 379 380 uint32_t c9_insn; /* Cache lockdown registers. */ 381 uint32_t c9_data; 382 uint64_t c9_pmcr; /* performance monitor control register */ 383 uint64_t c9_pmcnten; /* perf monitor counter enables */ 384 uint64_t c9_pmovsr; /* perf monitor overflow status */ 385 uint64_t c9_pmuserenr; /* perf monitor user enable */ 386 uint64_t c9_pmselr; /* perf monitor counter selection register */ 387 uint64_t c9_pminten; /* perf monitor interrupt enables */ 388 union { /* Memory attribute redirection */ 389 struct { 390 #ifdef HOST_WORDS_BIGENDIAN 391 uint64_t _unused_mair_0; 392 uint32_t mair1_ns; 393 uint32_t mair0_ns; 394 uint64_t _unused_mair_1; 395 uint32_t mair1_s; 396 uint32_t mair0_s; 397 #else 398 uint64_t _unused_mair_0; 399 uint32_t mair0_ns; 400 uint32_t mair1_ns; 401 uint64_t _unused_mair_1; 402 uint32_t mair0_s; 403 uint32_t mair1_s; 404 #endif 405 }; 406 uint64_t mair_el[4]; 407 }; 408 union { /* vector base address register */ 409 struct { 410 uint64_t _unused_vbar; 411 uint64_t vbar_ns; 412 uint64_t hvbar; 413 uint64_t vbar_s; 414 }; 415 uint64_t vbar_el[4]; 416 }; 417 uint32_t mvbar; /* (monitor) vector base address register */ 418 struct { /* FCSE PID. */ 419 uint32_t fcseidr_ns; 420 uint32_t fcseidr_s; 421 }; 422 union { /* Context ID. */ 423 struct { 424 uint64_t _unused_contextidr_0; 425 uint64_t contextidr_ns; 426 uint64_t _unused_contextidr_1; 427 uint64_t contextidr_s; 428 }; 429 uint64_t contextidr_el[4]; 430 }; 431 union { /* User RW Thread register. */ 432 struct { 433 uint64_t tpidrurw_ns; 434 uint64_t tpidrprw_ns; 435 uint64_t htpidr; 436 uint64_t _tpidr_el3; 437 }; 438 uint64_t tpidr_el[4]; 439 }; 440 /* The secure banks of these registers don't map anywhere */ 441 uint64_t tpidrurw_s; 442 uint64_t tpidrprw_s; 443 uint64_t tpidruro_s; 444 445 union { /* User RO Thread register. */ 446 uint64_t tpidruro_ns; 447 uint64_t tpidrro_el[1]; 448 }; 449 uint64_t c14_cntfrq; /* Counter Frequency register */ 450 uint64_t c14_cntkctl; /* Timer Control register */ 451 uint32_t cnthctl_el2; /* Counter/Timer Hyp Control register */ 452 uint64_t cntvoff_el2; /* Counter Virtual Offset register */ 453 ARMGenericTimer c14_timer[NUM_GTIMERS]; 454 uint32_t c15_cpar; /* XScale Coprocessor Access Register */ 455 uint32_t c15_ticonfig; /* TI925T configuration byte. */ 456 uint32_t c15_i_max; /* Maximum D-cache dirty line index. */ 457 uint32_t c15_i_min; /* Minimum D-cache dirty line index. */ 458 uint32_t c15_threadid; /* TI debugger thread-ID. */ 459 uint32_t c15_config_base_address; /* SCU base address. */ 460 uint32_t c15_diagnostic; /* diagnostic register */ 461 uint32_t c15_power_diagnostic; 462 uint32_t c15_power_control; /* power control */ 463 uint64_t dbgbvr[16]; /* breakpoint value registers */ 464 uint64_t dbgbcr[16]; /* breakpoint control registers */ 465 uint64_t dbgwvr[16]; /* watchpoint value registers */ 466 uint64_t dbgwcr[16]; /* watchpoint control registers */ 467 uint64_t mdscr_el1; 468 uint64_t oslsr_el1; /* OS Lock Status */ 469 uint64_t mdcr_el2; 470 uint64_t mdcr_el3; 471 /* If the counter is enabled, this stores the last time the counter 472 * was reset. Otherwise it stores the counter value 473 */ 474 uint64_t c15_ccnt; 475 uint64_t pmccfiltr_el0; /* Performance Monitor Filter Register */ 476 uint64_t vpidr_el2; /* Virtualization Processor ID Register */ 477 uint64_t vmpidr_el2; /* Virtualization Multiprocessor ID Register */ 478 } cp15; 479 480 struct { 481 /* M profile has up to 4 stack pointers: 482 * a Main Stack Pointer and a Process Stack Pointer for each 483 * of the Secure and Non-Secure states. (If the CPU doesn't support 484 * the security extension then it has only two SPs.) 485 * In QEMU we always store the currently active SP in regs[13], 486 * and the non-active SP for the current security state in 487 * v7m.other_sp. The stack pointers for the inactive security state 488 * are stored in other_ss_msp and other_ss_psp. 489 * switch_v7m_security_state() is responsible for rearranging them 490 * when we change security state. 491 */ 492 uint32_t other_sp; 493 uint32_t other_ss_msp; 494 uint32_t other_ss_psp; 495 uint32_t vecbase[M_REG_NUM_BANKS]; 496 uint32_t basepri[M_REG_NUM_BANKS]; 497 uint32_t control[M_REG_NUM_BANKS]; 498 uint32_t ccr[M_REG_NUM_BANKS]; /* Configuration and Control */ 499 uint32_t cfsr[M_REG_NUM_BANKS]; /* Configurable Fault Status */ 500 uint32_t hfsr; /* HardFault Status */ 501 uint32_t dfsr; /* Debug Fault Status Register */ 502 uint32_t sfsr; /* Secure Fault Status Register */ 503 uint32_t mmfar[M_REG_NUM_BANKS]; /* MemManage Fault Address */ 504 uint32_t bfar; /* BusFault Address */ 505 uint32_t sfar; /* Secure Fault Address Register */ 506 unsigned mpu_ctrl[M_REG_NUM_BANKS]; /* MPU_CTRL */ 507 int exception; 508 uint32_t primask[M_REG_NUM_BANKS]; 509 uint32_t faultmask[M_REG_NUM_BANKS]; 510 uint32_t aircr; /* only holds r/w state if security extn implemented */ 511 uint32_t secure; /* Is CPU in Secure state? (not guest visible) */ 512 uint32_t csselr[M_REG_NUM_BANKS]; 513 uint32_t scr[M_REG_NUM_BANKS]; 514 uint32_t msplim[M_REG_NUM_BANKS]; 515 uint32_t psplim[M_REG_NUM_BANKS]; 516 } v7m; 517 518 /* Information associated with an exception about to be taken: 519 * code which raises an exception must set cs->exception_index and 520 * the relevant parts of this structure; the cpu_do_interrupt function 521 * will then set the guest-visible registers as part of the exception 522 * entry process. 523 */ 524 struct { 525 uint32_t syndrome; /* AArch64 format syndrome register */ 526 uint32_t fsr; /* AArch32 format fault status register info */ 527 uint64_t vaddress; /* virtual addr associated with exception, if any */ 528 uint32_t target_el; /* EL the exception should be targeted for */ 529 /* If we implement EL2 we will also need to store information 530 * about the intermediate physical address for stage 2 faults. 531 */ 532 } exception; 533 534 /* Information associated with an SError */ 535 struct { 536 uint8_t pending; 537 uint8_t has_esr; 538 uint64_t esr; 539 } serror; 540 541 /* State of our input IRQ/FIQ/VIRQ/VFIQ lines */ 542 uint32_t irq_line_state; 543 544 /* Thumb-2 EE state. */ 545 uint32_t teecr; 546 uint32_t teehbr; 547 548 /* VFP coprocessor state. */ 549 struct { 550 ARMVectorReg zregs[32]; 551 552 #ifdef TARGET_AARCH64 553 /* Store FFR as pregs[16] to make it easier to treat as any other. */ 554 #define FFR_PRED_NUM 16 555 ARMPredicateReg pregs[17]; 556 /* Scratch space for aa64 sve predicate temporary. */ 557 ARMPredicateReg preg_tmp; 558 #endif 559 560 uint32_t xregs[16]; 561 /* We store these fpcsr fields separately for convenience. */ 562 int vec_len; 563 int vec_stride; 564 565 /* Scratch space for aa32 neon expansion. */ 566 uint32_t scratch[8]; 567 568 /* There are a number of distinct float control structures: 569 * 570 * fp_status: is the "normal" fp status. 571 * fp_status_fp16: used for half-precision calculations 572 * standard_fp_status : the ARM "Standard FPSCR Value" 573 * 574 * Half-precision operations are governed by a separate 575 * flush-to-zero control bit in FPSCR:FZ16. We pass a separate 576 * status structure to control this. 577 * 578 * The "Standard FPSCR", ie default-NaN, flush-to-zero, 579 * round-to-nearest and is used by any operations (generally 580 * Neon) which the architecture defines as controlled by the 581 * standard FPSCR value rather than the FPSCR. 582 * 583 * To avoid having to transfer exception bits around, we simply 584 * say that the FPSCR cumulative exception flags are the logical 585 * OR of the flags in the three fp statuses. This relies on the 586 * only thing which needs to read the exception flags being 587 * an explicit FPSCR read. 588 */ 589 float_status fp_status; 590 float_status fp_status_f16; 591 float_status standard_fp_status; 592 593 /* ZCR_EL[1-3] */ 594 uint64_t zcr_el[4]; 595 } vfp; 596 uint64_t exclusive_addr; 597 uint64_t exclusive_val; 598 uint64_t exclusive_high; 599 600 /* iwMMXt coprocessor state. */ 601 struct { 602 uint64_t regs[16]; 603 uint64_t val; 604 605 uint32_t cregs[16]; 606 } iwmmxt; 607 608 #if defined(CONFIG_USER_ONLY) 609 /* For usermode syscall translation. */ 610 int eabi; 611 #endif 612 613 struct CPUBreakpoint *cpu_breakpoint[16]; 614 struct CPUWatchpoint *cpu_watchpoint[16]; 615 616 /* Fields up to this point are cleared by a CPU reset */ 617 struct {} end_reset_fields; 618 619 CPU_COMMON 620 621 /* Fields after CPU_COMMON are preserved across CPU reset. */ 622 623 /* Internal CPU feature flags. */ 624 uint64_t features; 625 626 /* PMSAv7 MPU */ 627 struct { 628 uint32_t *drbar; 629 uint32_t *drsr; 630 uint32_t *dracr; 631 uint32_t rnr[M_REG_NUM_BANKS]; 632 } pmsav7; 633 634 /* PMSAv8 MPU */ 635 struct { 636 /* The PMSAv8 implementation also shares some PMSAv7 config 637 * and state: 638 * pmsav7.rnr (region number register) 639 * pmsav7_dregion (number of configured regions) 640 */ 641 uint32_t *rbar[M_REG_NUM_BANKS]; 642 uint32_t *rlar[M_REG_NUM_BANKS]; 643 uint32_t mair0[M_REG_NUM_BANKS]; 644 uint32_t mair1[M_REG_NUM_BANKS]; 645 } pmsav8; 646 647 /* v8M SAU */ 648 struct { 649 uint32_t *rbar; 650 uint32_t *rlar; 651 uint32_t rnr; 652 uint32_t ctrl; 653 } sau; 654 655 void *nvic; 656 const struct arm_boot_info *boot_info; 657 /* Store GICv3CPUState to access from this struct */ 658 void *gicv3state; 659 } CPUARMState; 660 661 /** 662 * ARMELChangeHookFn: 663 * type of a function which can be registered via arm_register_el_change_hook() 664 * to get callbacks when the CPU changes its exception level or mode. 665 */ 666 typedef void ARMELChangeHookFn(ARMCPU *cpu, void *opaque); 667 typedef struct ARMELChangeHook ARMELChangeHook; 668 struct ARMELChangeHook { 669 ARMELChangeHookFn *hook; 670 void *opaque; 671 QLIST_ENTRY(ARMELChangeHook) node; 672 }; 673 674 /* These values map onto the return values for 675 * QEMU_PSCI_0_2_FN_AFFINITY_INFO */ 676 typedef enum ARMPSCIState { 677 PSCI_ON = 0, 678 PSCI_OFF = 1, 679 PSCI_ON_PENDING = 2 680 } ARMPSCIState; 681 682 typedef struct ARMISARegisters ARMISARegisters; 683 684 /** 685 * ARMCPU: 686 * @env: #CPUARMState 687 * 688 * An ARM CPU core. 689 */ 690 struct ARMCPU { 691 /*< private >*/ 692 CPUState parent_obj; 693 /*< public >*/ 694 695 CPUARMState env; 696 697 /* Coprocessor information */ 698 GHashTable *cp_regs; 699 /* For marshalling (mostly coprocessor) register state between the 700 * kernel and QEMU (for KVM) and between two QEMUs (for migration), 701 * we use these arrays. 702 */ 703 /* List of register indexes managed via these arrays; (full KVM style 704 * 64 bit indexes, not CPRegInfo 32 bit indexes) 705 */ 706 uint64_t *cpreg_indexes; 707 /* Values of the registers (cpreg_indexes[i]'s value is cpreg_values[i]) */ 708 uint64_t *cpreg_values; 709 /* Length of the indexes, values, reset_values arrays */ 710 int32_t cpreg_array_len; 711 /* These are used only for migration: incoming data arrives in 712 * these fields and is sanity checked in post_load before copying 713 * to the working data structures above. 714 */ 715 uint64_t *cpreg_vmstate_indexes; 716 uint64_t *cpreg_vmstate_values; 717 int32_t cpreg_vmstate_array_len; 718 719 DynamicGDBXMLInfo dyn_xml; 720 721 /* Timers used by the generic (architected) timer */ 722 QEMUTimer *gt_timer[NUM_GTIMERS]; 723 /* GPIO outputs for generic timer */ 724 qemu_irq gt_timer_outputs[NUM_GTIMERS]; 725 /* GPIO output for GICv3 maintenance interrupt signal */ 726 qemu_irq gicv3_maintenance_interrupt; 727 /* GPIO output for the PMU interrupt */ 728 qemu_irq pmu_interrupt; 729 730 /* MemoryRegion to use for secure physical accesses */ 731 MemoryRegion *secure_memory; 732 733 /* For v8M, pointer to the IDAU interface provided by board/SoC */ 734 Object *idau; 735 736 /* 'compatible' string for this CPU for Linux device trees */ 737 const char *dtb_compatible; 738 739 /* PSCI version for this CPU 740 * Bits[31:16] = Major Version 741 * Bits[15:0] = Minor Version 742 */ 743 uint32_t psci_version; 744 745 /* Should CPU start in PSCI powered-off state? */ 746 bool start_powered_off; 747 748 /* Current power state, access guarded by BQL */ 749 ARMPSCIState power_state; 750 751 /* CPU has virtualization extension */ 752 bool has_el2; 753 /* CPU has security extension */ 754 bool has_el3; 755 /* CPU has PMU (Performance Monitor Unit) */ 756 bool has_pmu; 757 758 /* CPU has memory protection unit */ 759 bool has_mpu; 760 /* PMSAv7 MPU number of supported regions */ 761 uint32_t pmsav7_dregion; 762 /* v8M SAU number of supported regions */ 763 uint32_t sau_sregion; 764 765 /* PSCI conduit used to invoke PSCI methods 766 * 0 - disabled, 1 - smc, 2 - hvc 767 */ 768 uint32_t psci_conduit; 769 770 /* For v8M, initial value of the Secure VTOR */ 771 uint32_t init_svtor; 772 773 /* [QEMU_]KVM_ARM_TARGET_* constant for this CPU, or 774 * QEMU_KVM_ARM_TARGET_NONE if the kernel doesn't support this CPU type. 775 */ 776 uint32_t kvm_target; 777 778 /* KVM init features for this CPU */ 779 uint32_t kvm_init_features[7]; 780 781 /* Uniprocessor system with MP extensions */ 782 bool mp_is_up; 783 784 /* True if we tried kvm_arm_host_cpu_features() during CPU instance_init 785 * and the probe failed (so we need to report the error in realize) 786 */ 787 bool host_cpu_probe_failed; 788 789 /* Specify the number of cores in this CPU cluster. Used for the L2CTLR 790 * register. 791 */ 792 int32_t core_count; 793 794 /* The instance init functions for implementation-specific subclasses 795 * set these fields to specify the implementation-dependent values of 796 * various constant registers and reset values of non-constant 797 * registers. 798 * Some of these might become QOM properties eventually. 799 * Field names match the official register names as defined in the 800 * ARMv7AR ARM Architecture Reference Manual. A reset_ prefix 801 * is used for reset values of non-constant registers; no reset_ 802 * prefix means a constant register. 803 * Some of these registers are split out into a substructure that 804 * is shared with the translators to control the ISA. 805 */ 806 struct ARMISARegisters { 807 uint32_t id_isar0; 808 uint32_t id_isar1; 809 uint32_t id_isar2; 810 uint32_t id_isar3; 811 uint32_t id_isar4; 812 uint32_t id_isar5; 813 uint32_t id_isar6; 814 uint32_t mvfr0; 815 uint32_t mvfr1; 816 uint32_t mvfr2; 817 uint64_t id_aa64isar0; 818 uint64_t id_aa64isar1; 819 uint64_t id_aa64pfr0; 820 uint64_t id_aa64pfr1; 821 uint64_t id_aa64mmfr0; 822 uint64_t id_aa64mmfr1; 823 } isar; 824 uint32_t midr; 825 uint32_t revidr; 826 uint32_t reset_fpsid; 827 uint32_t ctr; 828 uint32_t reset_sctlr; 829 uint32_t id_pfr0; 830 uint32_t id_pfr1; 831 uint32_t id_dfr0; 832 uint32_t pmceid0; 833 uint32_t pmceid1; 834 uint32_t id_afr0; 835 uint32_t id_mmfr0; 836 uint32_t id_mmfr1; 837 uint32_t id_mmfr2; 838 uint32_t id_mmfr3; 839 uint32_t id_mmfr4; 840 uint64_t id_aa64dfr0; 841 uint64_t id_aa64dfr1; 842 uint64_t id_aa64afr0; 843 uint64_t id_aa64afr1; 844 uint32_t dbgdidr; 845 uint32_t clidr; 846 uint64_t mp_affinity; /* MP ID without feature bits */ 847 /* The elements of this array are the CCSIDR values for each cache, 848 * in the order L1DCache, L1ICache, L2DCache, L2ICache, etc. 849 */ 850 uint32_t ccsidr[16]; 851 uint64_t reset_cbar; 852 uint32_t reset_auxcr; 853 bool reset_hivecs; 854 /* DCZ blocksize, in log_2(words), ie low 4 bits of DCZID_EL0 */ 855 uint32_t dcz_blocksize; 856 uint64_t rvbar; 857 858 /* Configurable aspects of GIC cpu interface (which is part of the CPU) */ 859 int gic_num_lrs; /* number of list registers */ 860 int gic_vpribits; /* number of virtual priority bits */ 861 int gic_vprebits; /* number of virtual preemption bits */ 862 863 /* Whether the cfgend input is high (i.e. this CPU should reset into 864 * big-endian mode). This setting isn't used directly: instead it modifies 865 * the reset_sctlr value to have SCTLR_B or SCTLR_EE set, depending on the 866 * architecture version. 867 */ 868 bool cfgend; 869 870 QLIST_HEAD(, ARMELChangeHook) pre_el_change_hooks; 871 QLIST_HEAD(, ARMELChangeHook) el_change_hooks; 872 873 int32_t node_id; /* NUMA node this CPU belongs to */ 874 875 /* Used to synchronize KVM and QEMU in-kernel device levels */ 876 uint8_t device_irq_level; 877 878 /* Used to set the maximum vector length the cpu will support. */ 879 uint32_t sve_max_vq; 880 }; 881 882 static inline ARMCPU *arm_env_get_cpu(CPUARMState *env) 883 { 884 return container_of(env, ARMCPU, env); 885 } 886 887 void arm_cpu_post_init(Object *obj); 888 889 uint64_t arm_cpu_mp_affinity(int idx, uint8_t clustersz); 890 891 #define ENV_GET_CPU(e) CPU(arm_env_get_cpu(e)) 892 893 #define ENV_OFFSET offsetof(ARMCPU, env) 894 895 #ifndef CONFIG_USER_ONLY 896 extern const struct VMStateDescription vmstate_arm_cpu; 897 #endif 898 899 void arm_cpu_do_interrupt(CPUState *cpu); 900 void arm_v7m_cpu_do_interrupt(CPUState *cpu); 901 bool arm_cpu_exec_interrupt(CPUState *cpu, int int_req); 902 903 void arm_cpu_dump_state(CPUState *cs, FILE *f, fprintf_function cpu_fprintf, 904 int flags); 905 906 hwaddr arm_cpu_get_phys_page_attrs_debug(CPUState *cpu, vaddr addr, 907 MemTxAttrs *attrs); 908 909 int arm_cpu_gdb_read_register(CPUState *cpu, uint8_t *buf, int reg); 910 int arm_cpu_gdb_write_register(CPUState *cpu, uint8_t *buf, int reg); 911 912 /* Dynamically generates for gdb stub an XML description of the sysregs from 913 * the cp_regs hashtable. Returns the registered sysregs number. 914 */ 915 int arm_gen_dynamic_xml(CPUState *cpu); 916 917 /* Returns the dynamically generated XML for the gdb stub. 918 * Returns a pointer to the XML contents for the specified XML file or NULL 919 * if the XML name doesn't match the predefined one. 920 */ 921 const char *arm_gdb_get_dynamic_xml(CPUState *cpu, const char *xmlname); 922 923 int arm_cpu_write_elf64_note(WriteCoreDumpFunction f, CPUState *cs, 924 int cpuid, void *opaque); 925 int arm_cpu_write_elf32_note(WriteCoreDumpFunction f, CPUState *cs, 926 int cpuid, void *opaque); 927 928 #ifdef TARGET_AARCH64 929 int aarch64_cpu_gdb_read_register(CPUState *cpu, uint8_t *buf, int reg); 930 int aarch64_cpu_gdb_write_register(CPUState *cpu, uint8_t *buf, int reg); 931 void aarch64_sve_narrow_vq(CPUARMState *env, unsigned vq); 932 void aarch64_sve_change_el(CPUARMState *env, int old_el, 933 int new_el, bool el0_a64); 934 #else 935 static inline void aarch64_sve_narrow_vq(CPUARMState *env, unsigned vq) { } 936 static inline void aarch64_sve_change_el(CPUARMState *env, int o, 937 int n, bool a) 938 { } 939 #endif 940 941 target_ulong do_arm_semihosting(CPUARMState *env); 942 void aarch64_sync_32_to_64(CPUARMState *env); 943 void aarch64_sync_64_to_32(CPUARMState *env); 944 945 int fp_exception_el(CPUARMState *env, int cur_el); 946 int sve_exception_el(CPUARMState *env, int cur_el); 947 uint32_t sve_zcr_len_for_el(CPUARMState *env, int el); 948 949 static inline bool is_a64(CPUARMState *env) 950 { 951 return env->aarch64; 952 } 953 954 /* you can call this signal handler from your SIGBUS and SIGSEGV 955 signal handlers to inform the virtual CPU of exceptions. non zero 956 is returned if the signal was handled by the virtual CPU. */ 957 int cpu_arm_signal_handler(int host_signum, void *pinfo, 958 void *puc); 959 960 /** 961 * pmccntr_sync 962 * @env: CPUARMState 963 * 964 * Synchronises the counter in the PMCCNTR. This must always be called twice, 965 * once before any action that might affect the timer and again afterwards. 966 * The function is used to swap the state of the register if required. 967 * This only happens when not in user mode (!CONFIG_USER_ONLY) 968 */ 969 void pmccntr_sync(CPUARMState *env); 970 971 /* SCTLR bit meanings. Several bits have been reused in newer 972 * versions of the architecture; in that case we define constants 973 * for both old and new bit meanings. Code which tests against those 974 * bits should probably check or otherwise arrange that the CPU 975 * is the architectural version it expects. 976 */ 977 #define SCTLR_M (1U << 0) 978 #define SCTLR_A (1U << 1) 979 #define SCTLR_C (1U << 2) 980 #define SCTLR_W (1U << 3) /* up to v6; RAO in v7 */ 981 #define SCTLR_SA (1U << 3) 982 #define SCTLR_P (1U << 4) /* up to v5; RAO in v6 and v7 */ 983 #define SCTLR_SA0 (1U << 4) /* v8 onward, AArch64 only */ 984 #define SCTLR_D (1U << 5) /* up to v5; RAO in v6 */ 985 #define SCTLR_CP15BEN (1U << 5) /* v7 onward */ 986 #define SCTLR_L (1U << 6) /* up to v5; RAO in v6 and v7; RAZ in v8 */ 987 #define SCTLR_B (1U << 7) /* up to v6; RAZ in v7 */ 988 #define SCTLR_ITD (1U << 7) /* v8 onward */ 989 #define SCTLR_S (1U << 8) /* up to v6; RAZ in v7 */ 990 #define SCTLR_SED (1U << 8) /* v8 onward */ 991 #define SCTLR_R (1U << 9) /* up to v6; RAZ in v7 */ 992 #define SCTLR_UMA (1U << 9) /* v8 onward, AArch64 only */ 993 #define SCTLR_F (1U << 10) /* up to v6 */ 994 #define SCTLR_SW (1U << 10) /* v7 onward */ 995 #define SCTLR_Z (1U << 11) 996 #define SCTLR_I (1U << 12) 997 #define SCTLR_V (1U << 13) 998 #define SCTLR_RR (1U << 14) /* up to v7 */ 999 #define SCTLR_DZE (1U << 14) /* v8 onward, AArch64 only */ 1000 #define SCTLR_L4 (1U << 15) /* up to v6; RAZ in v7 */ 1001 #define SCTLR_UCT (1U << 15) /* v8 onward, AArch64 only */ 1002 #define SCTLR_DT (1U << 16) /* up to ??, RAO in v6 and v7 */ 1003 #define SCTLR_nTWI (1U << 16) /* v8 onward */ 1004 #define SCTLR_HA (1U << 17) 1005 #define SCTLR_BR (1U << 17) /* PMSA only */ 1006 #define SCTLR_IT (1U << 18) /* up to ??, RAO in v6 and v7 */ 1007 #define SCTLR_nTWE (1U << 18) /* v8 onward */ 1008 #define SCTLR_WXN (1U << 19) 1009 #define SCTLR_ST (1U << 20) /* up to ??, RAZ in v6 */ 1010 #define SCTLR_UWXN (1U << 20) /* v7 onward */ 1011 #define SCTLR_FI (1U << 21) 1012 #define SCTLR_U (1U << 22) 1013 #define SCTLR_XP (1U << 23) /* up to v6; v7 onward RAO */ 1014 #define SCTLR_VE (1U << 24) /* up to v7 */ 1015 #define SCTLR_E0E (1U << 24) /* v8 onward, AArch64 only */ 1016 #define SCTLR_EE (1U << 25) 1017 #define SCTLR_L2 (1U << 26) /* up to v6, RAZ in v7 */ 1018 #define SCTLR_UCI (1U << 26) /* v8 onward, AArch64 only */ 1019 #define SCTLR_NMFI (1U << 27) 1020 #define SCTLR_TRE (1U << 28) 1021 #define SCTLR_AFE (1U << 29) 1022 #define SCTLR_TE (1U << 30) 1023 1024 #define CPTR_TCPAC (1U << 31) 1025 #define CPTR_TTA (1U << 20) 1026 #define CPTR_TFP (1U << 10) 1027 #define CPTR_TZ (1U << 8) /* CPTR_EL2 */ 1028 #define CPTR_EZ (1U << 8) /* CPTR_EL3 */ 1029 1030 #define MDCR_EPMAD (1U << 21) 1031 #define MDCR_EDAD (1U << 20) 1032 #define MDCR_SPME (1U << 17) 1033 #define MDCR_SDD (1U << 16) 1034 #define MDCR_SPD (3U << 14) 1035 #define MDCR_TDRA (1U << 11) 1036 #define MDCR_TDOSA (1U << 10) 1037 #define MDCR_TDA (1U << 9) 1038 #define MDCR_TDE (1U << 8) 1039 #define MDCR_HPME (1U << 7) 1040 #define MDCR_TPM (1U << 6) 1041 #define MDCR_TPMCR (1U << 5) 1042 1043 /* Not all of the MDCR_EL3 bits are present in the 32-bit SDCR */ 1044 #define SDCR_VALID_MASK (MDCR_EPMAD | MDCR_EDAD | MDCR_SPME | MDCR_SPD) 1045 1046 #define CPSR_M (0x1fU) 1047 #define CPSR_T (1U << 5) 1048 #define CPSR_F (1U << 6) 1049 #define CPSR_I (1U << 7) 1050 #define CPSR_A (1U << 8) 1051 #define CPSR_E (1U << 9) 1052 #define CPSR_IT_2_7 (0xfc00U) 1053 #define CPSR_GE (0xfU << 16) 1054 #define CPSR_IL (1U << 20) 1055 /* Note that the RESERVED bits include bit 21, which is PSTATE_SS in 1056 * an AArch64 SPSR but RES0 in AArch32 SPSR and CPSR. In QEMU we use 1057 * env->uncached_cpsr bit 21 to store PSTATE.SS when executing in AArch32, 1058 * where it is live state but not accessible to the AArch32 code. 1059 */ 1060 #define CPSR_RESERVED (0x7U << 21) 1061 #define CPSR_J (1U << 24) 1062 #define CPSR_IT_0_1 (3U << 25) 1063 #define CPSR_Q (1U << 27) 1064 #define CPSR_V (1U << 28) 1065 #define CPSR_C (1U << 29) 1066 #define CPSR_Z (1U << 30) 1067 #define CPSR_N (1U << 31) 1068 #define CPSR_NZCV (CPSR_N | CPSR_Z | CPSR_C | CPSR_V) 1069 #define CPSR_AIF (CPSR_A | CPSR_I | CPSR_F) 1070 1071 #define CPSR_IT (CPSR_IT_0_1 | CPSR_IT_2_7) 1072 #define CACHED_CPSR_BITS (CPSR_T | CPSR_AIF | CPSR_GE | CPSR_IT | CPSR_Q \ 1073 | CPSR_NZCV) 1074 /* Bits writable in user mode. */ 1075 #define CPSR_USER (CPSR_NZCV | CPSR_Q | CPSR_GE) 1076 /* Execution state bits. MRS read as zero, MSR writes ignored. */ 1077 #define CPSR_EXEC (CPSR_T | CPSR_IT | CPSR_J | CPSR_IL) 1078 /* Mask of bits which may be set by exception return copying them from SPSR */ 1079 #define CPSR_ERET_MASK (~CPSR_RESERVED) 1080 1081 /* Bit definitions for M profile XPSR. Most are the same as CPSR. */ 1082 #define XPSR_EXCP 0x1ffU 1083 #define XPSR_SPREALIGN (1U << 9) /* Only set in exception stack frames */ 1084 #define XPSR_IT_2_7 CPSR_IT_2_7 1085 #define XPSR_GE CPSR_GE 1086 #define XPSR_SFPA (1U << 20) /* Only set in exception stack frames */ 1087 #define XPSR_T (1U << 24) /* Not the same as CPSR_T ! */ 1088 #define XPSR_IT_0_1 CPSR_IT_0_1 1089 #define XPSR_Q CPSR_Q 1090 #define XPSR_V CPSR_V 1091 #define XPSR_C CPSR_C 1092 #define XPSR_Z CPSR_Z 1093 #define XPSR_N CPSR_N 1094 #define XPSR_NZCV CPSR_NZCV 1095 #define XPSR_IT CPSR_IT 1096 1097 #define TTBCR_N (7U << 0) /* TTBCR.EAE==0 */ 1098 #define TTBCR_T0SZ (7U << 0) /* TTBCR.EAE==1 */ 1099 #define TTBCR_PD0 (1U << 4) 1100 #define TTBCR_PD1 (1U << 5) 1101 #define TTBCR_EPD0 (1U << 7) 1102 #define TTBCR_IRGN0 (3U << 8) 1103 #define TTBCR_ORGN0 (3U << 10) 1104 #define TTBCR_SH0 (3U << 12) 1105 #define TTBCR_T1SZ (3U << 16) 1106 #define TTBCR_A1 (1U << 22) 1107 #define TTBCR_EPD1 (1U << 23) 1108 #define TTBCR_IRGN1 (3U << 24) 1109 #define TTBCR_ORGN1 (3U << 26) 1110 #define TTBCR_SH1 (1U << 28) 1111 #define TTBCR_EAE (1U << 31) 1112 1113 /* Bit definitions for ARMv8 SPSR (PSTATE) format. 1114 * Only these are valid when in AArch64 mode; in 1115 * AArch32 mode SPSRs are basically CPSR-format. 1116 */ 1117 #define PSTATE_SP (1U) 1118 #define PSTATE_M (0xFU) 1119 #define PSTATE_nRW (1U << 4) 1120 #define PSTATE_F (1U << 6) 1121 #define PSTATE_I (1U << 7) 1122 #define PSTATE_A (1U << 8) 1123 #define PSTATE_D (1U << 9) 1124 #define PSTATE_IL (1U << 20) 1125 #define PSTATE_SS (1U << 21) 1126 #define PSTATE_V (1U << 28) 1127 #define PSTATE_C (1U << 29) 1128 #define PSTATE_Z (1U << 30) 1129 #define PSTATE_N (1U << 31) 1130 #define PSTATE_NZCV (PSTATE_N | PSTATE_Z | PSTATE_C | PSTATE_V) 1131 #define PSTATE_DAIF (PSTATE_D | PSTATE_A | PSTATE_I | PSTATE_F) 1132 #define CACHED_PSTATE_BITS (PSTATE_NZCV | PSTATE_DAIF) 1133 /* Mode values for AArch64 */ 1134 #define PSTATE_MODE_EL3h 13 1135 #define PSTATE_MODE_EL3t 12 1136 #define PSTATE_MODE_EL2h 9 1137 #define PSTATE_MODE_EL2t 8 1138 #define PSTATE_MODE_EL1h 5 1139 #define PSTATE_MODE_EL1t 4 1140 #define PSTATE_MODE_EL0t 0 1141 1142 /* Write a new value to v7m.exception, thus transitioning into or out 1143 * of Handler mode; this may result in a change of active stack pointer. 1144 */ 1145 void write_v7m_exception(CPUARMState *env, uint32_t new_exc); 1146 1147 /* Map EL and handler into a PSTATE_MODE. */ 1148 static inline unsigned int aarch64_pstate_mode(unsigned int el, bool handler) 1149 { 1150 return (el << 2) | handler; 1151 } 1152 1153 /* Return the current PSTATE value. For the moment we don't support 32<->64 bit 1154 * interprocessing, so we don't attempt to sync with the cpsr state used by 1155 * the 32 bit decoder. 1156 */ 1157 static inline uint32_t pstate_read(CPUARMState *env) 1158 { 1159 int ZF; 1160 1161 ZF = (env->ZF == 0); 1162 return (env->NF & 0x80000000) | (ZF << 30) 1163 | (env->CF << 29) | ((env->VF & 0x80000000) >> 3) 1164 | env->pstate | env->daif; 1165 } 1166 1167 static inline void pstate_write(CPUARMState *env, uint32_t val) 1168 { 1169 env->ZF = (~val) & PSTATE_Z; 1170 env->NF = val; 1171 env->CF = (val >> 29) & 1; 1172 env->VF = (val << 3) & 0x80000000; 1173 env->daif = val & PSTATE_DAIF; 1174 env->pstate = val & ~CACHED_PSTATE_BITS; 1175 } 1176 1177 /* Return the current CPSR value. */ 1178 uint32_t cpsr_read(CPUARMState *env); 1179 1180 typedef enum CPSRWriteType { 1181 CPSRWriteByInstr = 0, /* from guest MSR or CPS */ 1182 CPSRWriteExceptionReturn = 1, /* from guest exception return insn */ 1183 CPSRWriteRaw = 2, /* trust values, do not switch reg banks */ 1184 CPSRWriteByGDBStub = 3, /* from the GDB stub */ 1185 } CPSRWriteType; 1186 1187 /* Set the CPSR. Note that some bits of mask must be all-set or all-clear.*/ 1188 void cpsr_write(CPUARMState *env, uint32_t val, uint32_t mask, 1189 CPSRWriteType write_type); 1190 1191 /* Return the current xPSR value. */ 1192 static inline uint32_t xpsr_read(CPUARMState *env) 1193 { 1194 int ZF; 1195 ZF = (env->ZF == 0); 1196 return (env->NF & 0x80000000) | (ZF << 30) 1197 | (env->CF << 29) | ((env->VF & 0x80000000) >> 3) | (env->QF << 27) 1198 | (env->thumb << 24) | ((env->condexec_bits & 3) << 25) 1199 | ((env->condexec_bits & 0xfc) << 8) 1200 | env->v7m.exception; 1201 } 1202 1203 /* Set the xPSR. Note that some bits of mask must be all-set or all-clear. */ 1204 static inline void xpsr_write(CPUARMState *env, uint32_t val, uint32_t mask) 1205 { 1206 if (mask & XPSR_NZCV) { 1207 env->ZF = (~val) & XPSR_Z; 1208 env->NF = val; 1209 env->CF = (val >> 29) & 1; 1210 env->VF = (val << 3) & 0x80000000; 1211 } 1212 if (mask & XPSR_Q) { 1213 env->QF = ((val & XPSR_Q) != 0); 1214 } 1215 if (mask & XPSR_T) { 1216 env->thumb = ((val & XPSR_T) != 0); 1217 } 1218 if (mask & XPSR_IT_0_1) { 1219 env->condexec_bits &= ~3; 1220 env->condexec_bits |= (val >> 25) & 3; 1221 } 1222 if (mask & XPSR_IT_2_7) { 1223 env->condexec_bits &= 3; 1224 env->condexec_bits |= (val >> 8) & 0xfc; 1225 } 1226 if (mask & XPSR_EXCP) { 1227 /* Note that this only happens on exception exit */ 1228 write_v7m_exception(env, val & XPSR_EXCP); 1229 } 1230 } 1231 1232 #define HCR_VM (1ULL << 0) 1233 #define HCR_SWIO (1ULL << 1) 1234 #define HCR_PTW (1ULL << 2) 1235 #define HCR_FMO (1ULL << 3) 1236 #define HCR_IMO (1ULL << 4) 1237 #define HCR_AMO (1ULL << 5) 1238 #define HCR_VF (1ULL << 6) 1239 #define HCR_VI (1ULL << 7) 1240 #define HCR_VSE (1ULL << 8) 1241 #define HCR_FB (1ULL << 9) 1242 #define HCR_BSU_MASK (3ULL << 10) 1243 #define HCR_DC (1ULL << 12) 1244 #define HCR_TWI (1ULL << 13) 1245 #define HCR_TWE (1ULL << 14) 1246 #define HCR_TID0 (1ULL << 15) 1247 #define HCR_TID1 (1ULL << 16) 1248 #define HCR_TID2 (1ULL << 17) 1249 #define HCR_TID3 (1ULL << 18) 1250 #define HCR_TSC (1ULL << 19) 1251 #define HCR_TIDCP (1ULL << 20) 1252 #define HCR_TACR (1ULL << 21) 1253 #define HCR_TSW (1ULL << 22) 1254 #define HCR_TPCP (1ULL << 23) 1255 #define HCR_TPU (1ULL << 24) 1256 #define HCR_TTLB (1ULL << 25) 1257 #define HCR_TVM (1ULL << 26) 1258 #define HCR_TGE (1ULL << 27) 1259 #define HCR_TDZ (1ULL << 28) 1260 #define HCR_HCD (1ULL << 29) 1261 #define HCR_TRVM (1ULL << 30) 1262 #define HCR_RW (1ULL << 31) 1263 #define HCR_CD (1ULL << 32) 1264 #define HCR_ID (1ULL << 33) 1265 #define HCR_E2H (1ULL << 34) 1266 #define HCR_TLOR (1ULL << 35) 1267 #define HCR_TERR (1ULL << 36) 1268 #define HCR_TEA (1ULL << 37) 1269 #define HCR_MIOCNCE (1ULL << 38) 1270 #define HCR_APK (1ULL << 40) 1271 #define HCR_API (1ULL << 41) 1272 #define HCR_NV (1ULL << 42) 1273 #define HCR_NV1 (1ULL << 43) 1274 #define HCR_AT (1ULL << 44) 1275 #define HCR_NV2 (1ULL << 45) 1276 #define HCR_FWB (1ULL << 46) 1277 #define HCR_FIEN (1ULL << 47) 1278 #define HCR_TID4 (1ULL << 49) 1279 #define HCR_TICAB (1ULL << 50) 1280 #define HCR_TOCU (1ULL << 52) 1281 #define HCR_TTLBIS (1ULL << 54) 1282 #define HCR_TTLBOS (1ULL << 55) 1283 #define HCR_ATA (1ULL << 56) 1284 #define HCR_DCT (1ULL << 57) 1285 1286 /* 1287 * When we actually implement ARMv8.1-VHE we should add HCR_E2H to 1288 * HCR_MASK and then clear it again if the feature bit is not set in 1289 * hcr_write(). 1290 */ 1291 #define HCR_MASK ((1ULL << 34) - 1) 1292 1293 #define SCR_NS (1U << 0) 1294 #define SCR_IRQ (1U << 1) 1295 #define SCR_FIQ (1U << 2) 1296 #define SCR_EA (1U << 3) 1297 #define SCR_FW (1U << 4) 1298 #define SCR_AW (1U << 5) 1299 #define SCR_NET (1U << 6) 1300 #define SCR_SMD (1U << 7) 1301 #define SCR_HCE (1U << 8) 1302 #define SCR_SIF (1U << 9) 1303 #define SCR_RW (1U << 10) 1304 #define SCR_ST (1U << 11) 1305 #define SCR_TWI (1U << 12) 1306 #define SCR_TWE (1U << 13) 1307 #define SCR_TLOR (1U << 14) 1308 #define SCR_TERR (1U << 15) 1309 #define SCR_APK (1U << 16) 1310 #define SCR_API (1U << 17) 1311 #define SCR_EEL2 (1U << 18) 1312 #define SCR_EASE (1U << 19) 1313 #define SCR_NMEA (1U << 20) 1314 #define SCR_FIEN (1U << 21) 1315 #define SCR_ENSCXT (1U << 25) 1316 #define SCR_ATA (1U << 26) 1317 1318 /* Return the current FPSCR value. */ 1319 uint32_t vfp_get_fpscr(CPUARMState *env); 1320 void vfp_set_fpscr(CPUARMState *env, uint32_t val); 1321 1322 /* FPCR, Floating Point Control Register 1323 * FPSR, Floating Poiht Status Register 1324 * 1325 * For A64 the FPSCR is split into two logically distinct registers, 1326 * FPCR and FPSR. However since they still use non-overlapping bits 1327 * we store the underlying state in fpscr and just mask on read/write. 1328 */ 1329 #define FPSR_MASK 0xf800009f 1330 #define FPCR_MASK 0x07ff9f00 1331 1332 #define FPCR_FZ16 (1 << 19) /* ARMv8.2+, FP16 flush-to-zero */ 1333 #define FPCR_FZ (1 << 24) /* Flush-to-zero enable bit */ 1334 #define FPCR_DN (1 << 25) /* Default NaN enable bit */ 1335 1336 static inline uint32_t vfp_get_fpsr(CPUARMState *env) 1337 { 1338 return vfp_get_fpscr(env) & FPSR_MASK; 1339 } 1340 1341 static inline void vfp_set_fpsr(CPUARMState *env, uint32_t val) 1342 { 1343 uint32_t new_fpscr = (vfp_get_fpscr(env) & ~FPSR_MASK) | (val & FPSR_MASK); 1344 vfp_set_fpscr(env, new_fpscr); 1345 } 1346 1347 static inline uint32_t vfp_get_fpcr(CPUARMState *env) 1348 { 1349 return vfp_get_fpscr(env) & FPCR_MASK; 1350 } 1351 1352 static inline void vfp_set_fpcr(CPUARMState *env, uint32_t val) 1353 { 1354 uint32_t new_fpscr = (vfp_get_fpscr(env) & ~FPCR_MASK) | (val & FPCR_MASK); 1355 vfp_set_fpscr(env, new_fpscr); 1356 } 1357 1358 enum arm_cpu_mode { 1359 ARM_CPU_MODE_USR = 0x10, 1360 ARM_CPU_MODE_FIQ = 0x11, 1361 ARM_CPU_MODE_IRQ = 0x12, 1362 ARM_CPU_MODE_SVC = 0x13, 1363 ARM_CPU_MODE_MON = 0x16, 1364 ARM_CPU_MODE_ABT = 0x17, 1365 ARM_CPU_MODE_HYP = 0x1a, 1366 ARM_CPU_MODE_UND = 0x1b, 1367 ARM_CPU_MODE_SYS = 0x1f 1368 }; 1369 1370 /* VFP system registers. */ 1371 #define ARM_VFP_FPSID 0 1372 #define ARM_VFP_FPSCR 1 1373 #define ARM_VFP_MVFR2 5 1374 #define ARM_VFP_MVFR1 6 1375 #define ARM_VFP_MVFR0 7 1376 #define ARM_VFP_FPEXC 8 1377 #define ARM_VFP_FPINST 9 1378 #define ARM_VFP_FPINST2 10 1379 1380 /* iwMMXt coprocessor control registers. */ 1381 #define ARM_IWMMXT_wCID 0 1382 #define ARM_IWMMXT_wCon 1 1383 #define ARM_IWMMXT_wCSSF 2 1384 #define ARM_IWMMXT_wCASF 3 1385 #define ARM_IWMMXT_wCGR0 8 1386 #define ARM_IWMMXT_wCGR1 9 1387 #define ARM_IWMMXT_wCGR2 10 1388 #define ARM_IWMMXT_wCGR3 11 1389 1390 /* V7M CCR bits */ 1391 FIELD(V7M_CCR, NONBASETHRDENA, 0, 1) 1392 FIELD(V7M_CCR, USERSETMPEND, 1, 1) 1393 FIELD(V7M_CCR, UNALIGN_TRP, 3, 1) 1394 FIELD(V7M_CCR, DIV_0_TRP, 4, 1) 1395 FIELD(V7M_CCR, BFHFNMIGN, 8, 1) 1396 FIELD(V7M_CCR, STKALIGN, 9, 1) 1397 FIELD(V7M_CCR, STKOFHFNMIGN, 10, 1) 1398 FIELD(V7M_CCR, DC, 16, 1) 1399 FIELD(V7M_CCR, IC, 17, 1) 1400 FIELD(V7M_CCR, BP, 18, 1) 1401 1402 /* V7M SCR bits */ 1403 FIELD(V7M_SCR, SLEEPONEXIT, 1, 1) 1404 FIELD(V7M_SCR, SLEEPDEEP, 2, 1) 1405 FIELD(V7M_SCR, SLEEPDEEPS, 3, 1) 1406 FIELD(V7M_SCR, SEVONPEND, 4, 1) 1407 1408 /* V7M AIRCR bits */ 1409 FIELD(V7M_AIRCR, VECTRESET, 0, 1) 1410 FIELD(V7M_AIRCR, VECTCLRACTIVE, 1, 1) 1411 FIELD(V7M_AIRCR, SYSRESETREQ, 2, 1) 1412 FIELD(V7M_AIRCR, SYSRESETREQS, 3, 1) 1413 FIELD(V7M_AIRCR, PRIGROUP, 8, 3) 1414 FIELD(V7M_AIRCR, BFHFNMINS, 13, 1) 1415 FIELD(V7M_AIRCR, PRIS, 14, 1) 1416 FIELD(V7M_AIRCR, ENDIANNESS, 15, 1) 1417 FIELD(V7M_AIRCR, VECTKEY, 16, 16) 1418 1419 /* V7M CFSR bits for MMFSR */ 1420 FIELD(V7M_CFSR, IACCVIOL, 0, 1) 1421 FIELD(V7M_CFSR, DACCVIOL, 1, 1) 1422 FIELD(V7M_CFSR, MUNSTKERR, 3, 1) 1423 FIELD(V7M_CFSR, MSTKERR, 4, 1) 1424 FIELD(V7M_CFSR, MLSPERR, 5, 1) 1425 FIELD(V7M_CFSR, MMARVALID, 7, 1) 1426 1427 /* V7M CFSR bits for BFSR */ 1428 FIELD(V7M_CFSR, IBUSERR, 8 + 0, 1) 1429 FIELD(V7M_CFSR, PRECISERR, 8 + 1, 1) 1430 FIELD(V7M_CFSR, IMPRECISERR, 8 + 2, 1) 1431 FIELD(V7M_CFSR, UNSTKERR, 8 + 3, 1) 1432 FIELD(V7M_CFSR, STKERR, 8 + 4, 1) 1433 FIELD(V7M_CFSR, LSPERR, 8 + 5, 1) 1434 FIELD(V7M_CFSR, BFARVALID, 8 + 7, 1) 1435 1436 /* V7M CFSR bits for UFSR */ 1437 FIELD(V7M_CFSR, UNDEFINSTR, 16 + 0, 1) 1438 FIELD(V7M_CFSR, INVSTATE, 16 + 1, 1) 1439 FIELD(V7M_CFSR, INVPC, 16 + 2, 1) 1440 FIELD(V7M_CFSR, NOCP, 16 + 3, 1) 1441 FIELD(V7M_CFSR, STKOF, 16 + 4, 1) 1442 FIELD(V7M_CFSR, UNALIGNED, 16 + 8, 1) 1443 FIELD(V7M_CFSR, DIVBYZERO, 16 + 9, 1) 1444 1445 /* V7M CFSR bit masks covering all of the subregister bits */ 1446 FIELD(V7M_CFSR, MMFSR, 0, 8) 1447 FIELD(V7M_CFSR, BFSR, 8, 8) 1448 FIELD(V7M_CFSR, UFSR, 16, 16) 1449 1450 /* V7M HFSR bits */ 1451 FIELD(V7M_HFSR, VECTTBL, 1, 1) 1452 FIELD(V7M_HFSR, FORCED, 30, 1) 1453 FIELD(V7M_HFSR, DEBUGEVT, 31, 1) 1454 1455 /* V7M DFSR bits */ 1456 FIELD(V7M_DFSR, HALTED, 0, 1) 1457 FIELD(V7M_DFSR, BKPT, 1, 1) 1458 FIELD(V7M_DFSR, DWTTRAP, 2, 1) 1459 FIELD(V7M_DFSR, VCATCH, 3, 1) 1460 FIELD(V7M_DFSR, EXTERNAL, 4, 1) 1461 1462 /* V7M SFSR bits */ 1463 FIELD(V7M_SFSR, INVEP, 0, 1) 1464 FIELD(V7M_SFSR, INVIS, 1, 1) 1465 FIELD(V7M_SFSR, INVER, 2, 1) 1466 FIELD(V7M_SFSR, AUVIOL, 3, 1) 1467 FIELD(V7M_SFSR, INVTRAN, 4, 1) 1468 FIELD(V7M_SFSR, LSPERR, 5, 1) 1469 FIELD(V7M_SFSR, SFARVALID, 6, 1) 1470 FIELD(V7M_SFSR, LSERR, 7, 1) 1471 1472 /* v7M MPU_CTRL bits */ 1473 FIELD(V7M_MPU_CTRL, ENABLE, 0, 1) 1474 FIELD(V7M_MPU_CTRL, HFNMIENA, 1, 1) 1475 FIELD(V7M_MPU_CTRL, PRIVDEFENA, 2, 1) 1476 1477 /* v7M CLIDR bits */ 1478 FIELD(V7M_CLIDR, CTYPE_ALL, 0, 21) 1479 FIELD(V7M_CLIDR, LOUIS, 21, 3) 1480 FIELD(V7M_CLIDR, LOC, 24, 3) 1481 FIELD(V7M_CLIDR, LOUU, 27, 3) 1482 FIELD(V7M_CLIDR, ICB, 30, 2) 1483 1484 FIELD(V7M_CSSELR, IND, 0, 1) 1485 FIELD(V7M_CSSELR, LEVEL, 1, 3) 1486 /* We use the combination of InD and Level to index into cpu->ccsidr[]; 1487 * define a mask for this and check that it doesn't permit running off 1488 * the end of the array. 1489 */ 1490 FIELD(V7M_CSSELR, INDEX, 0, 4) 1491 1492 /* 1493 * System register ID fields. 1494 */ 1495 FIELD(ID_ISAR0, SWAP, 0, 4) 1496 FIELD(ID_ISAR0, BITCOUNT, 4, 4) 1497 FIELD(ID_ISAR0, BITFIELD, 8, 4) 1498 FIELD(ID_ISAR0, CMPBRANCH, 12, 4) 1499 FIELD(ID_ISAR0, COPROC, 16, 4) 1500 FIELD(ID_ISAR0, DEBUG, 20, 4) 1501 FIELD(ID_ISAR0, DIVIDE, 24, 4) 1502 1503 FIELD(ID_ISAR1, ENDIAN, 0, 4) 1504 FIELD(ID_ISAR1, EXCEPT, 4, 4) 1505 FIELD(ID_ISAR1, EXCEPT_AR, 8, 4) 1506 FIELD(ID_ISAR1, EXTEND, 12, 4) 1507 FIELD(ID_ISAR1, IFTHEN, 16, 4) 1508 FIELD(ID_ISAR1, IMMEDIATE, 20, 4) 1509 FIELD(ID_ISAR1, INTERWORK, 24, 4) 1510 FIELD(ID_ISAR1, JAZELLE, 28, 4) 1511 1512 FIELD(ID_ISAR2, LOADSTORE, 0, 4) 1513 FIELD(ID_ISAR2, MEMHINT, 4, 4) 1514 FIELD(ID_ISAR2, MULTIACCESSINT, 8, 4) 1515 FIELD(ID_ISAR2, MULT, 12, 4) 1516 FIELD(ID_ISAR2, MULTS, 16, 4) 1517 FIELD(ID_ISAR2, MULTU, 20, 4) 1518 FIELD(ID_ISAR2, PSR_AR, 24, 4) 1519 FIELD(ID_ISAR2, REVERSAL, 28, 4) 1520 1521 FIELD(ID_ISAR3, SATURATE, 0, 4) 1522 FIELD(ID_ISAR3, SIMD, 4, 4) 1523 FIELD(ID_ISAR3, SVC, 8, 4) 1524 FIELD(ID_ISAR3, SYNCHPRIM, 12, 4) 1525 FIELD(ID_ISAR3, TABBRANCH, 16, 4) 1526 FIELD(ID_ISAR3, T32COPY, 20, 4) 1527 FIELD(ID_ISAR3, TRUENOP, 24, 4) 1528 FIELD(ID_ISAR3, T32EE, 28, 4) 1529 1530 FIELD(ID_ISAR4, UNPRIV, 0, 4) 1531 FIELD(ID_ISAR4, WITHSHIFTS, 4, 4) 1532 FIELD(ID_ISAR4, WRITEBACK, 8, 4) 1533 FIELD(ID_ISAR4, SMC, 12, 4) 1534 FIELD(ID_ISAR4, BARRIER, 16, 4) 1535 FIELD(ID_ISAR4, SYNCHPRIM_FRAC, 20, 4) 1536 FIELD(ID_ISAR4, PSR_M, 24, 4) 1537 FIELD(ID_ISAR4, SWP_FRAC, 28, 4) 1538 1539 FIELD(ID_ISAR5, SEVL, 0, 4) 1540 FIELD(ID_ISAR5, AES, 4, 4) 1541 FIELD(ID_ISAR5, SHA1, 8, 4) 1542 FIELD(ID_ISAR5, SHA2, 12, 4) 1543 FIELD(ID_ISAR5, CRC32, 16, 4) 1544 FIELD(ID_ISAR5, RDM, 24, 4) 1545 FIELD(ID_ISAR5, VCMA, 28, 4) 1546 1547 FIELD(ID_ISAR6, JSCVT, 0, 4) 1548 FIELD(ID_ISAR6, DP, 4, 4) 1549 FIELD(ID_ISAR6, FHM, 8, 4) 1550 FIELD(ID_ISAR6, SB, 12, 4) 1551 FIELD(ID_ISAR6, SPECRES, 16, 4) 1552 1553 FIELD(ID_MMFR4, SPECSEI, 0, 4) 1554 FIELD(ID_MMFR4, AC2, 4, 4) 1555 FIELD(ID_MMFR4, XNX, 8, 4) 1556 FIELD(ID_MMFR4, CNP, 12, 4) 1557 FIELD(ID_MMFR4, HPDS, 16, 4) 1558 FIELD(ID_MMFR4, LSM, 20, 4) 1559 FIELD(ID_MMFR4, CCIDX, 24, 4) 1560 FIELD(ID_MMFR4, EVT, 28, 4) 1561 1562 FIELD(ID_AA64ISAR0, AES, 4, 4) 1563 FIELD(ID_AA64ISAR0, SHA1, 8, 4) 1564 FIELD(ID_AA64ISAR0, SHA2, 12, 4) 1565 FIELD(ID_AA64ISAR0, CRC32, 16, 4) 1566 FIELD(ID_AA64ISAR0, ATOMIC, 20, 4) 1567 FIELD(ID_AA64ISAR0, RDM, 28, 4) 1568 FIELD(ID_AA64ISAR0, SHA3, 32, 4) 1569 FIELD(ID_AA64ISAR0, SM3, 36, 4) 1570 FIELD(ID_AA64ISAR0, SM4, 40, 4) 1571 FIELD(ID_AA64ISAR0, DP, 44, 4) 1572 FIELD(ID_AA64ISAR0, FHM, 48, 4) 1573 FIELD(ID_AA64ISAR0, TS, 52, 4) 1574 FIELD(ID_AA64ISAR0, TLB, 56, 4) 1575 FIELD(ID_AA64ISAR0, RNDR, 60, 4) 1576 1577 FIELD(ID_AA64ISAR1, DPB, 0, 4) 1578 FIELD(ID_AA64ISAR1, APA, 4, 4) 1579 FIELD(ID_AA64ISAR1, API, 8, 4) 1580 FIELD(ID_AA64ISAR1, JSCVT, 12, 4) 1581 FIELD(ID_AA64ISAR1, FCMA, 16, 4) 1582 FIELD(ID_AA64ISAR1, LRCPC, 20, 4) 1583 FIELD(ID_AA64ISAR1, GPA, 24, 4) 1584 FIELD(ID_AA64ISAR1, GPI, 28, 4) 1585 FIELD(ID_AA64ISAR1, FRINTTS, 32, 4) 1586 FIELD(ID_AA64ISAR1, SB, 36, 4) 1587 FIELD(ID_AA64ISAR1, SPECRES, 40, 4) 1588 1589 FIELD(ID_AA64PFR0, EL0, 0, 4) 1590 FIELD(ID_AA64PFR0, EL1, 4, 4) 1591 FIELD(ID_AA64PFR0, EL2, 8, 4) 1592 FIELD(ID_AA64PFR0, EL3, 12, 4) 1593 FIELD(ID_AA64PFR0, FP, 16, 4) 1594 FIELD(ID_AA64PFR0, ADVSIMD, 20, 4) 1595 FIELD(ID_AA64PFR0, GIC, 24, 4) 1596 FIELD(ID_AA64PFR0, RAS, 28, 4) 1597 FIELD(ID_AA64PFR0, SVE, 32, 4) 1598 1599 FIELD(ID_AA64MMFR0, PARANGE, 0, 4) 1600 FIELD(ID_AA64MMFR0, ASIDBITS, 4, 4) 1601 FIELD(ID_AA64MMFR0, BIGEND, 8, 4) 1602 FIELD(ID_AA64MMFR0, SNSMEM, 12, 4) 1603 FIELD(ID_AA64MMFR0, BIGENDEL0, 16, 4) 1604 FIELD(ID_AA64MMFR0, TGRAN16, 20, 4) 1605 FIELD(ID_AA64MMFR0, TGRAN64, 24, 4) 1606 FIELD(ID_AA64MMFR0, TGRAN4, 28, 4) 1607 FIELD(ID_AA64MMFR0, TGRAN16_2, 32, 4) 1608 FIELD(ID_AA64MMFR0, TGRAN64_2, 36, 4) 1609 FIELD(ID_AA64MMFR0, TGRAN4_2, 40, 4) 1610 FIELD(ID_AA64MMFR0, EXS, 44, 4) 1611 1612 FIELD(ID_AA64MMFR1, HAFDBS, 0, 4) 1613 FIELD(ID_AA64MMFR1, VMIDBITS, 4, 4) 1614 FIELD(ID_AA64MMFR1, VH, 8, 4) 1615 FIELD(ID_AA64MMFR1, HPDS, 12, 4) 1616 FIELD(ID_AA64MMFR1, LO, 16, 4) 1617 FIELD(ID_AA64MMFR1, PAN, 20, 4) 1618 FIELD(ID_AA64MMFR1, SPECSEI, 24, 4) 1619 FIELD(ID_AA64MMFR1, XNX, 28, 4) 1620 1621 QEMU_BUILD_BUG_ON(ARRAY_SIZE(((ARMCPU *)0)->ccsidr) <= R_V7M_CSSELR_INDEX_MASK); 1622 1623 /* If adding a feature bit which corresponds to a Linux ELF 1624 * HWCAP bit, remember to update the feature-bit-to-hwcap 1625 * mapping in linux-user/elfload.c:get_elf_hwcap(). 1626 */ 1627 enum arm_features { 1628 ARM_FEATURE_VFP, 1629 ARM_FEATURE_AUXCR, /* ARM1026 Auxiliary control register. */ 1630 ARM_FEATURE_XSCALE, /* Intel XScale extensions. */ 1631 ARM_FEATURE_IWMMXT, /* Intel iwMMXt extension. */ 1632 ARM_FEATURE_V6, 1633 ARM_FEATURE_V6K, 1634 ARM_FEATURE_V7, 1635 ARM_FEATURE_THUMB2, 1636 ARM_FEATURE_PMSA, /* no MMU; may have Memory Protection Unit */ 1637 ARM_FEATURE_VFP3, 1638 ARM_FEATURE_VFP_FP16, 1639 ARM_FEATURE_NEON, 1640 ARM_FEATURE_M, /* Microcontroller profile. */ 1641 ARM_FEATURE_OMAPCP, /* OMAP specific CP15 ops handling. */ 1642 ARM_FEATURE_THUMB2EE, 1643 ARM_FEATURE_V7MP, /* v7 Multiprocessing Extensions */ 1644 ARM_FEATURE_V7VE, /* v7 Virtualization Extensions (non-EL2 parts) */ 1645 ARM_FEATURE_V4T, 1646 ARM_FEATURE_V5, 1647 ARM_FEATURE_STRONGARM, 1648 ARM_FEATURE_VAPA, /* cp15 VA to PA lookups */ 1649 ARM_FEATURE_VFP4, /* VFPv4 (implies that NEON is v2) */ 1650 ARM_FEATURE_GENERIC_TIMER, 1651 ARM_FEATURE_MVFR, /* Media and VFP Feature Registers 0 and 1 */ 1652 ARM_FEATURE_DUMMY_C15_REGS, /* RAZ/WI all of cp15 crn=15 */ 1653 ARM_FEATURE_CACHE_TEST_CLEAN, /* 926/1026 style test-and-clean ops */ 1654 ARM_FEATURE_CACHE_DIRTY_REG, /* 1136/1176 cache dirty status register */ 1655 ARM_FEATURE_CACHE_BLOCK_OPS, /* v6 optional cache block operations */ 1656 ARM_FEATURE_MPIDR, /* has cp15 MPIDR */ 1657 ARM_FEATURE_PXN, /* has Privileged Execute Never bit */ 1658 ARM_FEATURE_LPAE, /* has Large Physical Address Extension */ 1659 ARM_FEATURE_V8, 1660 ARM_FEATURE_AARCH64, /* supports 64 bit mode */ 1661 ARM_FEATURE_CBAR, /* has cp15 CBAR */ 1662 ARM_FEATURE_CRC, /* ARMv8 CRC instructions */ 1663 ARM_FEATURE_CBAR_RO, /* has cp15 CBAR and it is read-only */ 1664 ARM_FEATURE_EL2, /* has EL2 Virtualization support */ 1665 ARM_FEATURE_EL3, /* has EL3 Secure monitor support */ 1666 ARM_FEATURE_THUMB_DSP, /* DSP insns supported in the Thumb encodings */ 1667 ARM_FEATURE_PMU, /* has PMU support */ 1668 ARM_FEATURE_VBAR, /* has cp15 VBAR */ 1669 ARM_FEATURE_M_SECURITY, /* M profile Security Extension */ 1670 ARM_FEATURE_M_MAIN, /* M profile Main Extension */ 1671 }; 1672 1673 static inline int arm_feature(CPUARMState *env, int feature) 1674 { 1675 return (env->features & (1ULL << feature)) != 0; 1676 } 1677 1678 #if !defined(CONFIG_USER_ONLY) 1679 /* Return true if exception levels below EL3 are in secure state, 1680 * or would be following an exception return to that level. 1681 * Unlike arm_is_secure() (which is always a question about the 1682 * _current_ state of the CPU) this doesn't care about the current 1683 * EL or mode. 1684 */ 1685 static inline bool arm_is_secure_below_el3(CPUARMState *env) 1686 { 1687 if (arm_feature(env, ARM_FEATURE_EL3)) { 1688 return !(env->cp15.scr_el3 & SCR_NS); 1689 } else { 1690 /* If EL3 is not supported then the secure state is implementation 1691 * defined, in which case QEMU defaults to non-secure. 1692 */ 1693 return false; 1694 } 1695 } 1696 1697 /* Return true if the CPU is AArch64 EL3 or AArch32 Mon */ 1698 static inline bool arm_is_el3_or_mon(CPUARMState *env) 1699 { 1700 if (arm_feature(env, ARM_FEATURE_EL3)) { 1701 if (is_a64(env) && extract32(env->pstate, 2, 2) == 3) { 1702 /* CPU currently in AArch64 state and EL3 */ 1703 return true; 1704 } else if (!is_a64(env) && 1705 (env->uncached_cpsr & CPSR_M) == ARM_CPU_MODE_MON) { 1706 /* CPU currently in AArch32 state and monitor mode */ 1707 return true; 1708 } 1709 } 1710 return false; 1711 } 1712 1713 /* Return true if the processor is in secure state */ 1714 static inline bool arm_is_secure(CPUARMState *env) 1715 { 1716 if (arm_is_el3_or_mon(env)) { 1717 return true; 1718 } 1719 return arm_is_secure_below_el3(env); 1720 } 1721 1722 #else 1723 static inline bool arm_is_secure_below_el3(CPUARMState *env) 1724 { 1725 return false; 1726 } 1727 1728 static inline bool arm_is_secure(CPUARMState *env) 1729 { 1730 return false; 1731 } 1732 #endif 1733 1734 /** 1735 * arm_hcr_el2_eff(): Return the effective value of HCR_EL2. 1736 * E.g. when in secure state, fields in HCR_EL2 are suppressed, 1737 * "for all purposes other than a direct read or write access of HCR_EL2." 1738 * Not included here is HCR_RW. 1739 */ 1740 uint64_t arm_hcr_el2_eff(CPUARMState *env); 1741 1742 /* Return true if the specified exception level is running in AArch64 state. */ 1743 static inline bool arm_el_is_aa64(CPUARMState *env, int el) 1744 { 1745 /* This isn't valid for EL0 (if we're in EL0, is_a64() is what you want, 1746 * and if we're not in EL0 then the state of EL0 isn't well defined.) 1747 */ 1748 assert(el >= 1 && el <= 3); 1749 bool aa64 = arm_feature(env, ARM_FEATURE_AARCH64); 1750 1751 /* The highest exception level is always at the maximum supported 1752 * register width, and then lower levels have a register width controlled 1753 * by bits in the SCR or HCR registers. 1754 */ 1755 if (el == 3) { 1756 return aa64; 1757 } 1758 1759 if (arm_feature(env, ARM_FEATURE_EL3)) { 1760 aa64 = aa64 && (env->cp15.scr_el3 & SCR_RW); 1761 } 1762 1763 if (el == 2) { 1764 return aa64; 1765 } 1766 1767 if (arm_feature(env, ARM_FEATURE_EL2) && !arm_is_secure_below_el3(env)) { 1768 aa64 = aa64 && (env->cp15.hcr_el2 & HCR_RW); 1769 } 1770 1771 return aa64; 1772 } 1773 1774 /* Function for determing whether guest cp register reads and writes should 1775 * access the secure or non-secure bank of a cp register. When EL3 is 1776 * operating in AArch32 state, the NS-bit determines whether the secure 1777 * instance of a cp register should be used. When EL3 is AArch64 (or if 1778 * it doesn't exist at all) then there is no register banking, and all 1779 * accesses are to the non-secure version. 1780 */ 1781 static inline bool access_secure_reg(CPUARMState *env) 1782 { 1783 bool ret = (arm_feature(env, ARM_FEATURE_EL3) && 1784 !arm_el_is_aa64(env, 3) && 1785 !(env->cp15.scr_el3 & SCR_NS)); 1786 1787 return ret; 1788 } 1789 1790 /* Macros for accessing a specified CP register bank */ 1791 #define A32_BANKED_REG_GET(_env, _regname, _secure) \ 1792 ((_secure) ? (_env)->cp15._regname##_s : (_env)->cp15._regname##_ns) 1793 1794 #define A32_BANKED_REG_SET(_env, _regname, _secure, _val) \ 1795 do { \ 1796 if (_secure) { \ 1797 (_env)->cp15._regname##_s = (_val); \ 1798 } else { \ 1799 (_env)->cp15._regname##_ns = (_val); \ 1800 } \ 1801 } while (0) 1802 1803 /* Macros for automatically accessing a specific CP register bank depending on 1804 * the current secure state of the system. These macros are not intended for 1805 * supporting instruction translation reads/writes as these are dependent 1806 * solely on the SCR.NS bit and not the mode. 1807 */ 1808 #define A32_BANKED_CURRENT_REG_GET(_env, _regname) \ 1809 A32_BANKED_REG_GET((_env), _regname, \ 1810 (arm_is_secure(_env) && !arm_el_is_aa64((_env), 3))) 1811 1812 #define A32_BANKED_CURRENT_REG_SET(_env, _regname, _val) \ 1813 A32_BANKED_REG_SET((_env), _regname, \ 1814 (arm_is_secure(_env) && !arm_el_is_aa64((_env), 3)), \ 1815 (_val)) 1816 1817 void arm_cpu_list(FILE *f, fprintf_function cpu_fprintf); 1818 uint32_t arm_phys_excp_target_el(CPUState *cs, uint32_t excp_idx, 1819 uint32_t cur_el, bool secure); 1820 1821 /* Interface between CPU and Interrupt controller. */ 1822 #ifndef CONFIG_USER_ONLY 1823 bool armv7m_nvic_can_take_pending_exception(void *opaque); 1824 #else 1825 static inline bool armv7m_nvic_can_take_pending_exception(void *opaque) 1826 { 1827 return true; 1828 } 1829 #endif 1830 /** 1831 * armv7m_nvic_set_pending: mark the specified exception as pending 1832 * @opaque: the NVIC 1833 * @irq: the exception number to mark pending 1834 * @secure: false for non-banked exceptions or for the nonsecure 1835 * version of a banked exception, true for the secure version of a banked 1836 * exception. 1837 * 1838 * Marks the specified exception as pending. Note that we will assert() 1839 * if @secure is true and @irq does not specify one of the fixed set 1840 * of architecturally banked exceptions. 1841 */ 1842 void armv7m_nvic_set_pending(void *opaque, int irq, bool secure); 1843 /** 1844 * armv7m_nvic_set_pending_derived: mark this derived exception as pending 1845 * @opaque: the NVIC 1846 * @irq: the exception number to mark pending 1847 * @secure: false for non-banked exceptions or for the nonsecure 1848 * version of a banked exception, true for the secure version of a banked 1849 * exception. 1850 * 1851 * Similar to armv7m_nvic_set_pending(), but specifically for derived 1852 * exceptions (exceptions generated in the course of trying to take 1853 * a different exception). 1854 */ 1855 void armv7m_nvic_set_pending_derived(void *opaque, int irq, bool secure); 1856 /** 1857 * armv7m_nvic_get_pending_irq_info: return highest priority pending 1858 * exception, and whether it targets Secure state 1859 * @opaque: the NVIC 1860 * @pirq: set to pending exception number 1861 * @ptargets_secure: set to whether pending exception targets Secure 1862 * 1863 * This function writes the number of the highest priority pending 1864 * exception (the one which would be made active by 1865 * armv7m_nvic_acknowledge_irq()) to @pirq, and sets @ptargets_secure 1866 * to true if the current highest priority pending exception should 1867 * be taken to Secure state, false for NS. 1868 */ 1869 void armv7m_nvic_get_pending_irq_info(void *opaque, int *pirq, 1870 bool *ptargets_secure); 1871 /** 1872 * armv7m_nvic_acknowledge_irq: make highest priority pending exception active 1873 * @opaque: the NVIC 1874 * 1875 * Move the current highest priority pending exception from the pending 1876 * state to the active state, and update v7m.exception to indicate that 1877 * it is the exception currently being handled. 1878 */ 1879 void armv7m_nvic_acknowledge_irq(void *opaque); 1880 /** 1881 * armv7m_nvic_complete_irq: complete specified interrupt or exception 1882 * @opaque: the NVIC 1883 * @irq: the exception number to complete 1884 * @secure: true if this exception was secure 1885 * 1886 * Returns: -1 if the irq was not active 1887 * 1 if completing this irq brought us back to base (no active irqs) 1888 * 0 if there is still an irq active after this one was completed 1889 * (Ignoring -1, this is the same as the RETTOBASE value before completion.) 1890 */ 1891 int armv7m_nvic_complete_irq(void *opaque, int irq, bool secure); 1892 /** 1893 * armv7m_nvic_raw_execution_priority: return the raw execution priority 1894 * @opaque: the NVIC 1895 * 1896 * Returns: the raw execution priority as defined by the v8M architecture. 1897 * This is the execution priority minus the effects of AIRCR.PRIS, 1898 * and minus any PRIMASK/FAULTMASK/BASEPRI priority boosting. 1899 * (v8M ARM ARM I_PKLD.) 1900 */ 1901 int armv7m_nvic_raw_execution_priority(void *opaque); 1902 /** 1903 * armv7m_nvic_neg_prio_requested: return true if the requested execution 1904 * priority is negative for the specified security state. 1905 * @opaque: the NVIC 1906 * @secure: the security state to test 1907 * This corresponds to the pseudocode IsReqExecPriNeg(). 1908 */ 1909 #ifndef CONFIG_USER_ONLY 1910 bool armv7m_nvic_neg_prio_requested(void *opaque, bool secure); 1911 #else 1912 static inline bool armv7m_nvic_neg_prio_requested(void *opaque, bool secure) 1913 { 1914 return false; 1915 } 1916 #endif 1917 1918 /* Interface for defining coprocessor registers. 1919 * Registers are defined in tables of arm_cp_reginfo structs 1920 * which are passed to define_arm_cp_regs(). 1921 */ 1922 1923 /* When looking up a coprocessor register we look for it 1924 * via an integer which encodes all of: 1925 * coprocessor number 1926 * Crn, Crm, opc1, opc2 fields 1927 * 32 or 64 bit register (ie is it accessed via MRC/MCR 1928 * or via MRRC/MCRR?) 1929 * non-secure/secure bank (AArch32 only) 1930 * We allow 4 bits for opc1 because MRRC/MCRR have a 4 bit field. 1931 * (In this case crn and opc2 should be zero.) 1932 * For AArch64, there is no 32/64 bit size distinction; 1933 * instead all registers have a 2 bit op0, 3 bit op1 and op2, 1934 * and 4 bit CRn and CRm. The encoding patterns are chosen 1935 * to be easy to convert to and from the KVM encodings, and also 1936 * so that the hashtable can contain both AArch32 and AArch64 1937 * registers (to allow for interprocessing where we might run 1938 * 32 bit code on a 64 bit core). 1939 */ 1940 /* This bit is private to our hashtable cpreg; in KVM register 1941 * IDs the AArch64/32 distinction is the KVM_REG_ARM/ARM64 1942 * in the upper bits of the 64 bit ID. 1943 */ 1944 #define CP_REG_AA64_SHIFT 28 1945 #define CP_REG_AA64_MASK (1 << CP_REG_AA64_SHIFT) 1946 1947 /* To enable banking of coprocessor registers depending on ns-bit we 1948 * add a bit to distinguish between secure and non-secure cpregs in the 1949 * hashtable. 1950 */ 1951 #define CP_REG_NS_SHIFT 29 1952 #define CP_REG_NS_MASK (1 << CP_REG_NS_SHIFT) 1953 1954 #define ENCODE_CP_REG(cp, is64, ns, crn, crm, opc1, opc2) \ 1955 ((ns) << CP_REG_NS_SHIFT | ((cp) << 16) | ((is64) << 15) | \ 1956 ((crn) << 11) | ((crm) << 7) | ((opc1) << 3) | (opc2)) 1957 1958 #define ENCODE_AA64_CP_REG(cp, crn, crm, op0, op1, op2) \ 1959 (CP_REG_AA64_MASK | \ 1960 ((cp) << CP_REG_ARM_COPROC_SHIFT) | \ 1961 ((op0) << CP_REG_ARM64_SYSREG_OP0_SHIFT) | \ 1962 ((op1) << CP_REG_ARM64_SYSREG_OP1_SHIFT) | \ 1963 ((crn) << CP_REG_ARM64_SYSREG_CRN_SHIFT) | \ 1964 ((crm) << CP_REG_ARM64_SYSREG_CRM_SHIFT) | \ 1965 ((op2) << CP_REG_ARM64_SYSREG_OP2_SHIFT)) 1966 1967 /* Convert a full 64 bit KVM register ID to the truncated 32 bit 1968 * version used as a key for the coprocessor register hashtable 1969 */ 1970 static inline uint32_t kvm_to_cpreg_id(uint64_t kvmid) 1971 { 1972 uint32_t cpregid = kvmid; 1973 if ((kvmid & CP_REG_ARCH_MASK) == CP_REG_ARM64) { 1974 cpregid |= CP_REG_AA64_MASK; 1975 } else { 1976 if ((kvmid & CP_REG_SIZE_MASK) == CP_REG_SIZE_U64) { 1977 cpregid |= (1 << 15); 1978 } 1979 1980 /* KVM is always non-secure so add the NS flag on AArch32 register 1981 * entries. 1982 */ 1983 cpregid |= 1 << CP_REG_NS_SHIFT; 1984 } 1985 return cpregid; 1986 } 1987 1988 /* Convert a truncated 32 bit hashtable key into the full 1989 * 64 bit KVM register ID. 1990 */ 1991 static inline uint64_t cpreg_to_kvm_id(uint32_t cpregid) 1992 { 1993 uint64_t kvmid; 1994 1995 if (cpregid & CP_REG_AA64_MASK) { 1996 kvmid = cpregid & ~CP_REG_AA64_MASK; 1997 kvmid |= CP_REG_SIZE_U64 | CP_REG_ARM64; 1998 } else { 1999 kvmid = cpregid & ~(1 << 15); 2000 if (cpregid & (1 << 15)) { 2001 kvmid |= CP_REG_SIZE_U64 | CP_REG_ARM; 2002 } else { 2003 kvmid |= CP_REG_SIZE_U32 | CP_REG_ARM; 2004 } 2005 } 2006 return kvmid; 2007 } 2008 2009 /* ARMCPRegInfo type field bits. If the SPECIAL bit is set this is a 2010 * special-behaviour cp reg and bits [11..8] indicate what behaviour 2011 * it has. Otherwise it is a simple cp reg, where CONST indicates that 2012 * TCG can assume the value to be constant (ie load at translate time) 2013 * and 64BIT indicates a 64 bit wide coprocessor register. SUPPRESS_TB_END 2014 * indicates that the TB should not be ended after a write to this register 2015 * (the default is that the TB ends after cp writes). OVERRIDE permits 2016 * a register definition to override a previous definition for the 2017 * same (cp, is64, crn, crm, opc1, opc2) tuple: either the new or the 2018 * old must have the OVERRIDE bit set. 2019 * ALIAS indicates that this register is an alias view of some underlying 2020 * state which is also visible via another register, and that the other 2021 * register is handling migration and reset; registers marked ALIAS will not be 2022 * migrated but may have their state set by syncing of register state from KVM. 2023 * NO_RAW indicates that this register has no underlying state and does not 2024 * support raw access for state saving/loading; it will not be used for either 2025 * migration or KVM state synchronization. (Typically this is for "registers" 2026 * which are actually used as instructions for cache maintenance and so on.) 2027 * IO indicates that this register does I/O and therefore its accesses 2028 * need to be surrounded by gen_io_start()/gen_io_end(). In particular, 2029 * registers which implement clocks or timers require this. 2030 */ 2031 #define ARM_CP_SPECIAL 0x0001 2032 #define ARM_CP_CONST 0x0002 2033 #define ARM_CP_64BIT 0x0004 2034 #define ARM_CP_SUPPRESS_TB_END 0x0008 2035 #define ARM_CP_OVERRIDE 0x0010 2036 #define ARM_CP_ALIAS 0x0020 2037 #define ARM_CP_IO 0x0040 2038 #define ARM_CP_NO_RAW 0x0080 2039 #define ARM_CP_NOP (ARM_CP_SPECIAL | 0x0100) 2040 #define ARM_CP_WFI (ARM_CP_SPECIAL | 0x0200) 2041 #define ARM_CP_NZCV (ARM_CP_SPECIAL | 0x0300) 2042 #define ARM_CP_CURRENTEL (ARM_CP_SPECIAL | 0x0400) 2043 #define ARM_CP_DC_ZVA (ARM_CP_SPECIAL | 0x0500) 2044 #define ARM_LAST_SPECIAL ARM_CP_DC_ZVA 2045 #define ARM_CP_FPU 0x1000 2046 #define ARM_CP_SVE 0x2000 2047 #define ARM_CP_NO_GDB 0x4000 2048 /* Used only as a terminator for ARMCPRegInfo lists */ 2049 #define ARM_CP_SENTINEL 0xffff 2050 /* Mask of only the flag bits in a type field */ 2051 #define ARM_CP_FLAG_MASK 0x70ff 2052 2053 /* Valid values for ARMCPRegInfo state field, indicating which of 2054 * the AArch32 and AArch64 execution states this register is visible in. 2055 * If the reginfo doesn't explicitly specify then it is AArch32 only. 2056 * If the reginfo is declared to be visible in both states then a second 2057 * reginfo is synthesised for the AArch32 view of the AArch64 register, 2058 * such that the AArch32 view is the lower 32 bits of the AArch64 one. 2059 * Note that we rely on the values of these enums as we iterate through 2060 * the various states in some places. 2061 */ 2062 enum { 2063 ARM_CP_STATE_AA32 = 0, 2064 ARM_CP_STATE_AA64 = 1, 2065 ARM_CP_STATE_BOTH = 2, 2066 }; 2067 2068 /* ARM CP register secure state flags. These flags identify security state 2069 * attributes for a given CP register entry. 2070 * The existence of both or neither secure and non-secure flags indicates that 2071 * the register has both a secure and non-secure hash entry. A single one of 2072 * these flags causes the register to only be hashed for the specified 2073 * security state. 2074 * Although definitions may have any combination of the S/NS bits, each 2075 * registered entry will only have one to identify whether the entry is secure 2076 * or non-secure. 2077 */ 2078 enum { 2079 ARM_CP_SECSTATE_S = (1 << 0), /* bit[0]: Secure state register */ 2080 ARM_CP_SECSTATE_NS = (1 << 1), /* bit[1]: Non-secure state register */ 2081 }; 2082 2083 /* Return true if cptype is a valid type field. This is used to try to 2084 * catch errors where the sentinel has been accidentally left off the end 2085 * of a list of registers. 2086 */ 2087 static inline bool cptype_valid(int cptype) 2088 { 2089 return ((cptype & ~ARM_CP_FLAG_MASK) == 0) 2090 || ((cptype & ARM_CP_SPECIAL) && 2091 ((cptype & ~ARM_CP_FLAG_MASK) <= ARM_LAST_SPECIAL)); 2092 } 2093 2094 /* Access rights: 2095 * We define bits for Read and Write access for what rev C of the v7-AR ARM ARM 2096 * defines as PL0 (user), PL1 (fiq/irq/svc/abt/und/sys, ie privileged), and 2097 * PL2 (hyp). The other level which has Read and Write bits is Secure PL1 2098 * (ie any of the privileged modes in Secure state, or Monitor mode). 2099 * If a register is accessible in one privilege level it's always accessible 2100 * in higher privilege levels too. Since "Secure PL1" also follows this rule 2101 * (ie anything visible in PL2 is visible in S-PL1, some things are only 2102 * visible in S-PL1) but "Secure PL1" is a bit of a mouthful, we bend the 2103 * terminology a little and call this PL3. 2104 * In AArch64 things are somewhat simpler as the PLx bits line up exactly 2105 * with the ELx exception levels. 2106 * 2107 * If access permissions for a register are more complex than can be 2108 * described with these bits, then use a laxer set of restrictions, and 2109 * do the more restrictive/complex check inside a helper function. 2110 */ 2111 #define PL3_R 0x80 2112 #define PL3_W 0x40 2113 #define PL2_R (0x20 | PL3_R) 2114 #define PL2_W (0x10 | PL3_W) 2115 #define PL1_R (0x08 | PL2_R) 2116 #define PL1_W (0x04 | PL2_W) 2117 #define PL0_R (0x02 | PL1_R) 2118 #define PL0_W (0x01 | PL1_W) 2119 2120 #define PL3_RW (PL3_R | PL3_W) 2121 #define PL2_RW (PL2_R | PL2_W) 2122 #define PL1_RW (PL1_R | PL1_W) 2123 #define PL0_RW (PL0_R | PL0_W) 2124 2125 /* Return the highest implemented Exception Level */ 2126 static inline int arm_highest_el(CPUARMState *env) 2127 { 2128 if (arm_feature(env, ARM_FEATURE_EL3)) { 2129 return 3; 2130 } 2131 if (arm_feature(env, ARM_FEATURE_EL2)) { 2132 return 2; 2133 } 2134 return 1; 2135 } 2136 2137 /* Return true if a v7M CPU is in Handler mode */ 2138 static inline bool arm_v7m_is_handler_mode(CPUARMState *env) 2139 { 2140 return env->v7m.exception != 0; 2141 } 2142 2143 /* Return the current Exception Level (as per ARMv8; note that this differs 2144 * from the ARMv7 Privilege Level). 2145 */ 2146 static inline int arm_current_el(CPUARMState *env) 2147 { 2148 if (arm_feature(env, ARM_FEATURE_M)) { 2149 return arm_v7m_is_handler_mode(env) || 2150 !(env->v7m.control[env->v7m.secure] & 1); 2151 } 2152 2153 if (is_a64(env)) { 2154 return extract32(env->pstate, 2, 2); 2155 } 2156 2157 switch (env->uncached_cpsr & 0x1f) { 2158 case ARM_CPU_MODE_USR: 2159 return 0; 2160 case ARM_CPU_MODE_HYP: 2161 return 2; 2162 case ARM_CPU_MODE_MON: 2163 return 3; 2164 default: 2165 if (arm_is_secure(env) && !arm_el_is_aa64(env, 3)) { 2166 /* If EL3 is 32-bit then all secure privileged modes run in 2167 * EL3 2168 */ 2169 return 3; 2170 } 2171 2172 return 1; 2173 } 2174 } 2175 2176 typedef struct ARMCPRegInfo ARMCPRegInfo; 2177 2178 typedef enum CPAccessResult { 2179 /* Access is permitted */ 2180 CP_ACCESS_OK = 0, 2181 /* Access fails due to a configurable trap or enable which would 2182 * result in a categorized exception syndrome giving information about 2183 * the failing instruction (ie syndrome category 0x3, 0x4, 0x5, 0x6, 2184 * 0xc or 0x18). The exception is taken to the usual target EL (EL1 or 2185 * PL1 if in EL0, otherwise to the current EL). 2186 */ 2187 CP_ACCESS_TRAP = 1, 2188 /* Access fails and results in an exception syndrome 0x0 ("uncategorized"). 2189 * Note that this is not a catch-all case -- the set of cases which may 2190 * result in this failure is specifically defined by the architecture. 2191 */ 2192 CP_ACCESS_TRAP_UNCATEGORIZED = 2, 2193 /* As CP_ACCESS_TRAP, but for traps directly to EL2 or EL3 */ 2194 CP_ACCESS_TRAP_EL2 = 3, 2195 CP_ACCESS_TRAP_EL3 = 4, 2196 /* As CP_ACCESS_UNCATEGORIZED, but for traps directly to EL2 or EL3 */ 2197 CP_ACCESS_TRAP_UNCATEGORIZED_EL2 = 5, 2198 CP_ACCESS_TRAP_UNCATEGORIZED_EL3 = 6, 2199 /* Access fails and results in an exception syndrome for an FP access, 2200 * trapped directly to EL2 or EL3 2201 */ 2202 CP_ACCESS_TRAP_FP_EL2 = 7, 2203 CP_ACCESS_TRAP_FP_EL3 = 8, 2204 } CPAccessResult; 2205 2206 /* Access functions for coprocessor registers. These cannot fail and 2207 * may not raise exceptions. 2208 */ 2209 typedef uint64_t CPReadFn(CPUARMState *env, const ARMCPRegInfo *opaque); 2210 typedef void CPWriteFn(CPUARMState *env, const ARMCPRegInfo *opaque, 2211 uint64_t value); 2212 /* Access permission check functions for coprocessor registers. */ 2213 typedef CPAccessResult CPAccessFn(CPUARMState *env, 2214 const ARMCPRegInfo *opaque, 2215 bool isread); 2216 /* Hook function for register reset */ 2217 typedef void CPResetFn(CPUARMState *env, const ARMCPRegInfo *opaque); 2218 2219 #define CP_ANY 0xff 2220 2221 /* Definition of an ARM coprocessor register */ 2222 struct ARMCPRegInfo { 2223 /* Name of register (useful mainly for debugging, need not be unique) */ 2224 const char *name; 2225 /* Location of register: coprocessor number and (crn,crm,opc1,opc2) 2226 * tuple. Any of crm, opc1 and opc2 may be CP_ANY to indicate a 2227 * 'wildcard' field -- any value of that field in the MRC/MCR insn 2228 * will be decoded to this register. The register read and write 2229 * callbacks will be passed an ARMCPRegInfo with the crn/crm/opc1/opc2 2230 * used by the program, so it is possible to register a wildcard and 2231 * then behave differently on read/write if necessary. 2232 * For 64 bit registers, only crm and opc1 are relevant; crn and opc2 2233 * must both be zero. 2234 * For AArch64-visible registers, opc0 is also used. 2235 * Since there are no "coprocessors" in AArch64, cp is purely used as a 2236 * way to distinguish (for KVM's benefit) guest-visible system registers 2237 * from demuxed ones provided to preserve the "no side effects on 2238 * KVM register read/write from QEMU" semantics. cp==0x13 is guest 2239 * visible (to match KVM's encoding); cp==0 will be converted to 2240 * cp==0x13 when the ARMCPRegInfo is registered, for convenience. 2241 */ 2242 uint8_t cp; 2243 uint8_t crn; 2244 uint8_t crm; 2245 uint8_t opc0; 2246 uint8_t opc1; 2247 uint8_t opc2; 2248 /* Execution state in which this register is visible: ARM_CP_STATE_* */ 2249 int state; 2250 /* Register type: ARM_CP_* bits/values */ 2251 int type; 2252 /* Access rights: PL*_[RW] */ 2253 int access; 2254 /* Security state: ARM_CP_SECSTATE_* bits/values */ 2255 int secure; 2256 /* The opaque pointer passed to define_arm_cp_regs_with_opaque() when 2257 * this register was defined: can be used to hand data through to the 2258 * register read/write functions, since they are passed the ARMCPRegInfo*. 2259 */ 2260 void *opaque; 2261 /* Value of this register, if it is ARM_CP_CONST. Otherwise, if 2262 * fieldoffset is non-zero, the reset value of the register. 2263 */ 2264 uint64_t resetvalue; 2265 /* Offset of the field in CPUARMState for this register. 2266 * 2267 * This is not needed if either: 2268 * 1. type is ARM_CP_CONST or one of the ARM_CP_SPECIALs 2269 * 2. both readfn and writefn are specified 2270 */ 2271 ptrdiff_t fieldoffset; /* offsetof(CPUARMState, field) */ 2272 2273 /* Offsets of the secure and non-secure fields in CPUARMState for the 2274 * register if it is banked. These fields are only used during the static 2275 * registration of a register. During hashing the bank associated 2276 * with a given security state is copied to fieldoffset which is used from 2277 * there on out. 2278 * 2279 * It is expected that register definitions use either fieldoffset or 2280 * bank_fieldoffsets in the definition but not both. It is also expected 2281 * that both bank offsets are set when defining a banked register. This 2282 * use indicates that a register is banked. 2283 */ 2284 ptrdiff_t bank_fieldoffsets[2]; 2285 2286 /* Function for making any access checks for this register in addition to 2287 * those specified by the 'access' permissions bits. If NULL, no extra 2288 * checks required. The access check is performed at runtime, not at 2289 * translate time. 2290 */ 2291 CPAccessFn *accessfn; 2292 /* Function for handling reads of this register. If NULL, then reads 2293 * will be done by loading from the offset into CPUARMState specified 2294 * by fieldoffset. 2295 */ 2296 CPReadFn *readfn; 2297 /* Function for handling writes of this register. If NULL, then writes 2298 * will be done by writing to the offset into CPUARMState specified 2299 * by fieldoffset. 2300 */ 2301 CPWriteFn *writefn; 2302 /* Function for doing a "raw" read; used when we need to copy 2303 * coprocessor state to the kernel for KVM or out for 2304 * migration. This only needs to be provided if there is also a 2305 * readfn and it has side effects (for instance clear-on-read bits). 2306 */ 2307 CPReadFn *raw_readfn; 2308 /* Function for doing a "raw" write; used when we need to copy KVM 2309 * kernel coprocessor state into userspace, or for inbound 2310 * migration. This only needs to be provided if there is also a 2311 * writefn and it masks out "unwritable" bits or has write-one-to-clear 2312 * or similar behaviour. 2313 */ 2314 CPWriteFn *raw_writefn; 2315 /* Function for resetting the register. If NULL, then reset will be done 2316 * by writing resetvalue to the field specified in fieldoffset. If 2317 * fieldoffset is 0 then no reset will be done. 2318 */ 2319 CPResetFn *resetfn; 2320 }; 2321 2322 /* Macros which are lvalues for the field in CPUARMState for the 2323 * ARMCPRegInfo *ri. 2324 */ 2325 #define CPREG_FIELD32(env, ri) \ 2326 (*(uint32_t *)((char *)(env) + (ri)->fieldoffset)) 2327 #define CPREG_FIELD64(env, ri) \ 2328 (*(uint64_t *)((char *)(env) + (ri)->fieldoffset)) 2329 2330 #define REGINFO_SENTINEL { .type = ARM_CP_SENTINEL } 2331 2332 void define_arm_cp_regs_with_opaque(ARMCPU *cpu, 2333 const ARMCPRegInfo *regs, void *opaque); 2334 void define_one_arm_cp_reg_with_opaque(ARMCPU *cpu, 2335 const ARMCPRegInfo *regs, void *opaque); 2336 static inline void define_arm_cp_regs(ARMCPU *cpu, const ARMCPRegInfo *regs) 2337 { 2338 define_arm_cp_regs_with_opaque(cpu, regs, 0); 2339 } 2340 static inline void define_one_arm_cp_reg(ARMCPU *cpu, const ARMCPRegInfo *regs) 2341 { 2342 define_one_arm_cp_reg_with_opaque(cpu, regs, 0); 2343 } 2344 const ARMCPRegInfo *get_arm_cp_reginfo(GHashTable *cpregs, uint32_t encoded_cp); 2345 2346 /* CPWriteFn that can be used to implement writes-ignored behaviour */ 2347 void arm_cp_write_ignore(CPUARMState *env, const ARMCPRegInfo *ri, 2348 uint64_t value); 2349 /* CPReadFn that can be used for read-as-zero behaviour */ 2350 uint64_t arm_cp_read_zero(CPUARMState *env, const ARMCPRegInfo *ri); 2351 2352 /* CPResetFn that does nothing, for use if no reset is required even 2353 * if fieldoffset is non zero. 2354 */ 2355 void arm_cp_reset_ignore(CPUARMState *env, const ARMCPRegInfo *opaque); 2356 2357 /* Return true if this reginfo struct's field in the cpu state struct 2358 * is 64 bits wide. 2359 */ 2360 static inline bool cpreg_field_is_64bit(const ARMCPRegInfo *ri) 2361 { 2362 return (ri->state == ARM_CP_STATE_AA64) || (ri->type & ARM_CP_64BIT); 2363 } 2364 2365 static inline bool cp_access_ok(int current_el, 2366 const ARMCPRegInfo *ri, int isread) 2367 { 2368 return (ri->access >> ((current_el * 2) + isread)) & 1; 2369 } 2370 2371 /* Raw read of a coprocessor register (as needed for migration, etc) */ 2372 uint64_t read_raw_cp_reg(CPUARMState *env, const ARMCPRegInfo *ri); 2373 2374 /** 2375 * write_list_to_cpustate 2376 * @cpu: ARMCPU 2377 * 2378 * For each register listed in the ARMCPU cpreg_indexes list, write 2379 * its value from the cpreg_values list into the ARMCPUState structure. 2380 * This updates TCG's working data structures from KVM data or 2381 * from incoming migration state. 2382 * 2383 * Returns: true if all register values were updated correctly, 2384 * false if some register was unknown or could not be written. 2385 * Note that we do not stop early on failure -- we will attempt 2386 * writing all registers in the list. 2387 */ 2388 bool write_list_to_cpustate(ARMCPU *cpu); 2389 2390 /** 2391 * write_cpustate_to_list: 2392 * @cpu: ARMCPU 2393 * 2394 * For each register listed in the ARMCPU cpreg_indexes list, write 2395 * its value from the ARMCPUState structure into the cpreg_values list. 2396 * This is used to copy info from TCG's working data structures into 2397 * KVM or for outbound migration. 2398 * 2399 * Returns: true if all register values were read correctly, 2400 * false if some register was unknown or could not be read. 2401 * Note that we do not stop early on failure -- we will attempt 2402 * reading all registers in the list. 2403 */ 2404 bool write_cpustate_to_list(ARMCPU *cpu); 2405 2406 #define ARM_CPUID_TI915T 0x54029152 2407 #define ARM_CPUID_TI925T 0x54029252 2408 2409 #if defined(CONFIG_USER_ONLY) 2410 #define TARGET_PAGE_BITS 12 2411 #else 2412 /* ARMv7 and later CPUs have 4K pages minimum, but ARMv5 and v6 2413 * have to support 1K tiny pages. 2414 */ 2415 #define TARGET_PAGE_BITS_VARY 2416 #define TARGET_PAGE_BITS_MIN 10 2417 #endif 2418 2419 #if defined(TARGET_AARCH64) 2420 # define TARGET_PHYS_ADDR_SPACE_BITS 48 2421 # define TARGET_VIRT_ADDR_SPACE_BITS 64 2422 #else 2423 # define TARGET_PHYS_ADDR_SPACE_BITS 40 2424 # define TARGET_VIRT_ADDR_SPACE_BITS 32 2425 #endif 2426 2427 static inline bool arm_excp_unmasked(CPUState *cs, unsigned int excp_idx, 2428 unsigned int target_el) 2429 { 2430 CPUARMState *env = cs->env_ptr; 2431 unsigned int cur_el = arm_current_el(env); 2432 bool secure = arm_is_secure(env); 2433 bool pstate_unmasked; 2434 int8_t unmasked = 0; 2435 uint64_t hcr_el2; 2436 2437 /* Don't take exceptions if they target a lower EL. 2438 * This check should catch any exceptions that would not be taken but left 2439 * pending. 2440 */ 2441 if (cur_el > target_el) { 2442 return false; 2443 } 2444 2445 hcr_el2 = arm_hcr_el2_eff(env); 2446 2447 switch (excp_idx) { 2448 case EXCP_FIQ: 2449 pstate_unmasked = !(env->daif & PSTATE_F); 2450 break; 2451 2452 case EXCP_IRQ: 2453 pstate_unmasked = !(env->daif & PSTATE_I); 2454 break; 2455 2456 case EXCP_VFIQ: 2457 if (secure || !(hcr_el2 & HCR_FMO) || (hcr_el2 & HCR_TGE)) { 2458 /* VFIQs are only taken when hypervized and non-secure. */ 2459 return false; 2460 } 2461 return !(env->daif & PSTATE_F); 2462 case EXCP_VIRQ: 2463 if (secure || !(hcr_el2 & HCR_IMO) || (hcr_el2 & HCR_TGE)) { 2464 /* VIRQs are only taken when hypervized and non-secure. */ 2465 return false; 2466 } 2467 return !(env->daif & PSTATE_I); 2468 default: 2469 g_assert_not_reached(); 2470 } 2471 2472 /* Use the target EL, current execution state and SCR/HCR settings to 2473 * determine whether the corresponding CPSR bit is used to mask the 2474 * interrupt. 2475 */ 2476 if ((target_el > cur_el) && (target_el != 1)) { 2477 /* Exceptions targeting a higher EL may not be maskable */ 2478 if (arm_feature(env, ARM_FEATURE_AARCH64)) { 2479 /* 64-bit masking rules are simple: exceptions to EL3 2480 * can't be masked, and exceptions to EL2 can only be 2481 * masked from Secure state. The HCR and SCR settings 2482 * don't affect the masking logic, only the interrupt routing. 2483 */ 2484 if (target_el == 3 || !secure) { 2485 unmasked = 1; 2486 } 2487 } else { 2488 /* The old 32-bit-only environment has a more complicated 2489 * masking setup. HCR and SCR bits not only affect interrupt 2490 * routing but also change the behaviour of masking. 2491 */ 2492 bool hcr, scr; 2493 2494 switch (excp_idx) { 2495 case EXCP_FIQ: 2496 /* If FIQs are routed to EL3 or EL2 then there are cases where 2497 * we override the CPSR.F in determining if the exception is 2498 * masked or not. If neither of these are set then we fall back 2499 * to the CPSR.F setting otherwise we further assess the state 2500 * below. 2501 */ 2502 hcr = hcr_el2 & HCR_FMO; 2503 scr = (env->cp15.scr_el3 & SCR_FIQ); 2504 2505 /* When EL3 is 32-bit, the SCR.FW bit controls whether the 2506 * CPSR.F bit masks FIQ interrupts when taken in non-secure 2507 * state. If SCR.FW is set then FIQs can be masked by CPSR.F 2508 * when non-secure but only when FIQs are only routed to EL3. 2509 */ 2510 scr = scr && !((env->cp15.scr_el3 & SCR_FW) && !hcr); 2511 break; 2512 case EXCP_IRQ: 2513 /* When EL3 execution state is 32-bit, if HCR.IMO is set then 2514 * we may override the CPSR.I masking when in non-secure state. 2515 * The SCR.IRQ setting has already been taken into consideration 2516 * when setting the target EL, so it does not have a further 2517 * affect here. 2518 */ 2519 hcr = hcr_el2 & HCR_IMO; 2520 scr = false; 2521 break; 2522 default: 2523 g_assert_not_reached(); 2524 } 2525 2526 if ((scr || hcr) && !secure) { 2527 unmasked = 1; 2528 } 2529 } 2530 } 2531 2532 /* The PSTATE bits only mask the interrupt if we have not overriden the 2533 * ability above. 2534 */ 2535 return unmasked || pstate_unmasked; 2536 } 2537 2538 #define ARM_CPU_TYPE_SUFFIX "-" TYPE_ARM_CPU 2539 #define ARM_CPU_TYPE_NAME(name) (name ARM_CPU_TYPE_SUFFIX) 2540 #define CPU_RESOLVING_TYPE TYPE_ARM_CPU 2541 2542 #define cpu_signal_handler cpu_arm_signal_handler 2543 #define cpu_list arm_cpu_list 2544 2545 /* ARM has the following "translation regimes" (as the ARM ARM calls them): 2546 * 2547 * If EL3 is 64-bit: 2548 * + NonSecure EL1 & 0 stage 1 2549 * + NonSecure EL1 & 0 stage 2 2550 * + NonSecure EL2 2551 * + Secure EL1 & EL0 2552 * + Secure EL3 2553 * If EL3 is 32-bit: 2554 * + NonSecure PL1 & 0 stage 1 2555 * + NonSecure PL1 & 0 stage 2 2556 * + NonSecure PL2 2557 * + Secure PL0 & PL1 2558 * (reminder: for 32 bit EL3, Secure PL1 is *EL3*, not EL1.) 2559 * 2560 * For QEMU, an mmu_idx is not quite the same as a translation regime because: 2561 * 1. we need to split the "EL1 & 0" regimes into two mmu_idxes, because they 2562 * may differ in access permissions even if the VA->PA map is the same 2563 * 2. we want to cache in our TLB the full VA->IPA->PA lookup for a stage 1+2 2564 * translation, which means that we have one mmu_idx that deals with two 2565 * concatenated translation regimes [this sort of combined s1+2 TLB is 2566 * architecturally permitted] 2567 * 3. we don't need to allocate an mmu_idx to translations that we won't be 2568 * handling via the TLB. The only way to do a stage 1 translation without 2569 * the immediate stage 2 translation is via the ATS or AT system insns, 2570 * which can be slow-pathed and always do a page table walk. 2571 * 4. we can also safely fold together the "32 bit EL3" and "64 bit EL3" 2572 * translation regimes, because they map reasonably well to each other 2573 * and they can't both be active at the same time. 2574 * This gives us the following list of mmu_idx values: 2575 * 2576 * NS EL0 (aka NS PL0) stage 1+2 2577 * NS EL1 (aka NS PL1) stage 1+2 2578 * NS EL2 (aka NS PL2) 2579 * S EL3 (aka S PL1) 2580 * S EL0 (aka S PL0) 2581 * S EL1 (not used if EL3 is 32 bit) 2582 * NS EL0+1 stage 2 2583 * 2584 * (The last of these is an mmu_idx because we want to be able to use the TLB 2585 * for the accesses done as part of a stage 1 page table walk, rather than 2586 * having to walk the stage 2 page table over and over.) 2587 * 2588 * R profile CPUs have an MPU, but can use the same set of MMU indexes 2589 * as A profile. They only need to distinguish NS EL0 and NS EL1 (and 2590 * NS EL2 if we ever model a Cortex-R52). 2591 * 2592 * M profile CPUs are rather different as they do not have a true MMU. 2593 * They have the following different MMU indexes: 2594 * User 2595 * Privileged 2596 * User, execution priority negative (ie the MPU HFNMIENA bit may apply) 2597 * Privileged, execution priority negative (ditto) 2598 * If the CPU supports the v8M Security Extension then there are also: 2599 * Secure User 2600 * Secure Privileged 2601 * Secure User, execution priority negative 2602 * Secure Privileged, execution priority negative 2603 * 2604 * The ARMMMUIdx and the mmu index value used by the core QEMU TLB code 2605 * are not quite the same -- different CPU types (most notably M profile 2606 * vs A/R profile) would like to use MMU indexes with different semantics, 2607 * but since we don't ever need to use all of those in a single CPU we 2608 * can avoid setting NB_MMU_MODES to more than 8. The lower bits of 2609 * ARMMMUIdx are the core TLB mmu index, and the higher bits are always 2610 * the same for any particular CPU. 2611 * Variables of type ARMMUIdx are always full values, and the core 2612 * index values are in variables of type 'int'. 2613 * 2614 * Our enumeration includes at the end some entries which are not "true" 2615 * mmu_idx values in that they don't have corresponding TLBs and are only 2616 * valid for doing slow path page table walks. 2617 * 2618 * The constant names here are patterned after the general style of the names 2619 * of the AT/ATS operations. 2620 * The values used are carefully arranged to make mmu_idx => EL lookup easy. 2621 * For M profile we arrange them to have a bit for priv, a bit for negpri 2622 * and a bit for secure. 2623 */ 2624 #define ARM_MMU_IDX_A 0x10 /* A profile */ 2625 #define ARM_MMU_IDX_NOTLB 0x20 /* does not have a TLB */ 2626 #define ARM_MMU_IDX_M 0x40 /* M profile */ 2627 2628 /* meanings of the bits for M profile mmu idx values */ 2629 #define ARM_MMU_IDX_M_PRIV 0x1 2630 #define ARM_MMU_IDX_M_NEGPRI 0x2 2631 #define ARM_MMU_IDX_M_S 0x4 2632 2633 #define ARM_MMU_IDX_TYPE_MASK (~0x7) 2634 #define ARM_MMU_IDX_COREIDX_MASK 0x7 2635 2636 typedef enum ARMMMUIdx { 2637 ARMMMUIdx_S12NSE0 = 0 | ARM_MMU_IDX_A, 2638 ARMMMUIdx_S12NSE1 = 1 | ARM_MMU_IDX_A, 2639 ARMMMUIdx_S1E2 = 2 | ARM_MMU_IDX_A, 2640 ARMMMUIdx_S1E3 = 3 | ARM_MMU_IDX_A, 2641 ARMMMUIdx_S1SE0 = 4 | ARM_MMU_IDX_A, 2642 ARMMMUIdx_S1SE1 = 5 | ARM_MMU_IDX_A, 2643 ARMMMUIdx_S2NS = 6 | ARM_MMU_IDX_A, 2644 ARMMMUIdx_MUser = 0 | ARM_MMU_IDX_M, 2645 ARMMMUIdx_MPriv = 1 | ARM_MMU_IDX_M, 2646 ARMMMUIdx_MUserNegPri = 2 | ARM_MMU_IDX_M, 2647 ARMMMUIdx_MPrivNegPri = 3 | ARM_MMU_IDX_M, 2648 ARMMMUIdx_MSUser = 4 | ARM_MMU_IDX_M, 2649 ARMMMUIdx_MSPriv = 5 | ARM_MMU_IDX_M, 2650 ARMMMUIdx_MSUserNegPri = 6 | ARM_MMU_IDX_M, 2651 ARMMMUIdx_MSPrivNegPri = 7 | ARM_MMU_IDX_M, 2652 /* Indexes below here don't have TLBs and are used only for AT system 2653 * instructions or for the first stage of an S12 page table walk. 2654 */ 2655 ARMMMUIdx_S1NSE0 = 0 | ARM_MMU_IDX_NOTLB, 2656 ARMMMUIdx_S1NSE1 = 1 | ARM_MMU_IDX_NOTLB, 2657 } ARMMMUIdx; 2658 2659 /* Bit macros for the core-mmu-index values for each index, 2660 * for use when calling tlb_flush_by_mmuidx() and friends. 2661 */ 2662 typedef enum ARMMMUIdxBit { 2663 ARMMMUIdxBit_S12NSE0 = 1 << 0, 2664 ARMMMUIdxBit_S12NSE1 = 1 << 1, 2665 ARMMMUIdxBit_S1E2 = 1 << 2, 2666 ARMMMUIdxBit_S1E3 = 1 << 3, 2667 ARMMMUIdxBit_S1SE0 = 1 << 4, 2668 ARMMMUIdxBit_S1SE1 = 1 << 5, 2669 ARMMMUIdxBit_S2NS = 1 << 6, 2670 ARMMMUIdxBit_MUser = 1 << 0, 2671 ARMMMUIdxBit_MPriv = 1 << 1, 2672 ARMMMUIdxBit_MUserNegPri = 1 << 2, 2673 ARMMMUIdxBit_MPrivNegPri = 1 << 3, 2674 ARMMMUIdxBit_MSUser = 1 << 4, 2675 ARMMMUIdxBit_MSPriv = 1 << 5, 2676 ARMMMUIdxBit_MSUserNegPri = 1 << 6, 2677 ARMMMUIdxBit_MSPrivNegPri = 1 << 7, 2678 } ARMMMUIdxBit; 2679 2680 #define MMU_USER_IDX 0 2681 2682 static inline int arm_to_core_mmu_idx(ARMMMUIdx mmu_idx) 2683 { 2684 return mmu_idx & ARM_MMU_IDX_COREIDX_MASK; 2685 } 2686 2687 static inline ARMMMUIdx core_to_arm_mmu_idx(CPUARMState *env, int mmu_idx) 2688 { 2689 if (arm_feature(env, ARM_FEATURE_M)) { 2690 return mmu_idx | ARM_MMU_IDX_M; 2691 } else { 2692 return mmu_idx | ARM_MMU_IDX_A; 2693 } 2694 } 2695 2696 /* Return the exception level we're running at if this is our mmu_idx */ 2697 static inline int arm_mmu_idx_to_el(ARMMMUIdx mmu_idx) 2698 { 2699 switch (mmu_idx & ARM_MMU_IDX_TYPE_MASK) { 2700 case ARM_MMU_IDX_A: 2701 return mmu_idx & 3; 2702 case ARM_MMU_IDX_M: 2703 return mmu_idx & ARM_MMU_IDX_M_PRIV; 2704 default: 2705 g_assert_not_reached(); 2706 } 2707 } 2708 2709 /* Return the MMU index for a v7M CPU in the specified security and 2710 * privilege state 2711 */ 2712 static inline ARMMMUIdx arm_v7m_mmu_idx_for_secstate_and_priv(CPUARMState *env, 2713 bool secstate, 2714 bool priv) 2715 { 2716 ARMMMUIdx mmu_idx = ARM_MMU_IDX_M; 2717 2718 if (priv) { 2719 mmu_idx |= ARM_MMU_IDX_M_PRIV; 2720 } 2721 2722 if (armv7m_nvic_neg_prio_requested(env->nvic, secstate)) { 2723 mmu_idx |= ARM_MMU_IDX_M_NEGPRI; 2724 } 2725 2726 if (secstate) { 2727 mmu_idx |= ARM_MMU_IDX_M_S; 2728 } 2729 2730 return mmu_idx; 2731 } 2732 2733 /* Return the MMU index for a v7M CPU in the specified security state */ 2734 static inline ARMMMUIdx arm_v7m_mmu_idx_for_secstate(CPUARMState *env, 2735 bool secstate) 2736 { 2737 bool priv = arm_current_el(env) != 0; 2738 2739 return arm_v7m_mmu_idx_for_secstate_and_priv(env, secstate, priv); 2740 } 2741 2742 /* Determine the current mmu_idx to use for normal loads/stores */ 2743 static inline int cpu_mmu_index(CPUARMState *env, bool ifetch) 2744 { 2745 int el = arm_current_el(env); 2746 2747 if (arm_feature(env, ARM_FEATURE_M)) { 2748 ARMMMUIdx mmu_idx = arm_v7m_mmu_idx_for_secstate(env, env->v7m.secure); 2749 2750 return arm_to_core_mmu_idx(mmu_idx); 2751 } 2752 2753 if (el < 2 && arm_is_secure_below_el3(env)) { 2754 return arm_to_core_mmu_idx(ARMMMUIdx_S1SE0 + el); 2755 } 2756 return el; 2757 } 2758 2759 /* Indexes used when registering address spaces with cpu_address_space_init */ 2760 typedef enum ARMASIdx { 2761 ARMASIdx_NS = 0, 2762 ARMASIdx_S = 1, 2763 } ARMASIdx; 2764 2765 /* Return the Exception Level targeted by debug exceptions. */ 2766 static inline int arm_debug_target_el(CPUARMState *env) 2767 { 2768 bool secure = arm_is_secure(env); 2769 bool route_to_el2 = false; 2770 2771 if (arm_feature(env, ARM_FEATURE_EL2) && !secure) { 2772 route_to_el2 = env->cp15.hcr_el2 & HCR_TGE || 2773 env->cp15.mdcr_el2 & MDCR_TDE; 2774 } 2775 2776 if (route_to_el2) { 2777 return 2; 2778 } else if (arm_feature(env, ARM_FEATURE_EL3) && 2779 !arm_el_is_aa64(env, 3) && secure) { 2780 return 3; 2781 } else { 2782 return 1; 2783 } 2784 } 2785 2786 static inline bool arm_v7m_csselr_razwi(ARMCPU *cpu) 2787 { 2788 /* If all the CLIDR.Ctypem bits are 0 there are no caches, and 2789 * CSSELR is RAZ/WI. 2790 */ 2791 return (cpu->clidr & R_V7M_CLIDR_CTYPE_ALL_MASK) != 0; 2792 } 2793 2794 /* See AArch64.GenerateDebugExceptionsFrom() in ARM ARM pseudocode */ 2795 static inline bool aa64_generate_debug_exceptions(CPUARMState *env) 2796 { 2797 int cur_el = arm_current_el(env); 2798 int debug_el; 2799 2800 if (cur_el == 3) { 2801 return false; 2802 } 2803 2804 /* MDCR_EL3.SDD disables debug events from Secure state */ 2805 if (arm_is_secure_below_el3(env) 2806 && extract32(env->cp15.mdcr_el3, 16, 1)) { 2807 return false; 2808 } 2809 2810 /* 2811 * Same EL to same EL debug exceptions need MDSCR_KDE enabled 2812 * while not masking the (D)ebug bit in DAIF. 2813 */ 2814 debug_el = arm_debug_target_el(env); 2815 2816 if (cur_el == debug_el) { 2817 return extract32(env->cp15.mdscr_el1, 13, 1) 2818 && !(env->daif & PSTATE_D); 2819 } 2820 2821 /* Otherwise the debug target needs to be a higher EL */ 2822 return debug_el > cur_el; 2823 } 2824 2825 static inline bool aa32_generate_debug_exceptions(CPUARMState *env) 2826 { 2827 int el = arm_current_el(env); 2828 2829 if (el == 0 && arm_el_is_aa64(env, 1)) { 2830 return aa64_generate_debug_exceptions(env); 2831 } 2832 2833 if (arm_is_secure(env)) { 2834 int spd; 2835 2836 if (el == 0 && (env->cp15.sder & 1)) { 2837 /* SDER.SUIDEN means debug exceptions from Secure EL0 2838 * are always enabled. Otherwise they are controlled by 2839 * SDCR.SPD like those from other Secure ELs. 2840 */ 2841 return true; 2842 } 2843 2844 spd = extract32(env->cp15.mdcr_el3, 14, 2); 2845 switch (spd) { 2846 case 1: 2847 /* SPD == 0b01 is reserved, but behaves as 0b00. */ 2848 case 0: 2849 /* For 0b00 we return true if external secure invasive debug 2850 * is enabled. On real hardware this is controlled by external 2851 * signals to the core. QEMU always permits debug, and behaves 2852 * as if DBGEN, SPIDEN, NIDEN and SPNIDEN are all tied high. 2853 */ 2854 return true; 2855 case 2: 2856 return false; 2857 case 3: 2858 return true; 2859 } 2860 } 2861 2862 return el != 2; 2863 } 2864 2865 /* Return true if debugging exceptions are currently enabled. 2866 * This corresponds to what in ARM ARM pseudocode would be 2867 * if UsingAArch32() then 2868 * return AArch32.GenerateDebugExceptions() 2869 * else 2870 * return AArch64.GenerateDebugExceptions() 2871 * We choose to push the if() down into this function for clarity, 2872 * since the pseudocode has it at all callsites except for the one in 2873 * CheckSoftwareStep(), where it is elided because both branches would 2874 * always return the same value. 2875 */ 2876 static inline bool arm_generate_debug_exceptions(CPUARMState *env) 2877 { 2878 if (env->aarch64) { 2879 return aa64_generate_debug_exceptions(env); 2880 } else { 2881 return aa32_generate_debug_exceptions(env); 2882 } 2883 } 2884 2885 /* Is single-stepping active? (Note that the "is EL_D AArch64?" check 2886 * implicitly means this always returns false in pre-v8 CPUs.) 2887 */ 2888 static inline bool arm_singlestep_active(CPUARMState *env) 2889 { 2890 return extract32(env->cp15.mdscr_el1, 0, 1) 2891 && arm_el_is_aa64(env, arm_debug_target_el(env)) 2892 && arm_generate_debug_exceptions(env); 2893 } 2894 2895 static inline bool arm_sctlr_b(CPUARMState *env) 2896 { 2897 return 2898 /* We need not implement SCTLR.ITD in user-mode emulation, so 2899 * let linux-user ignore the fact that it conflicts with SCTLR_B. 2900 * This lets people run BE32 binaries with "-cpu any". 2901 */ 2902 #ifndef CONFIG_USER_ONLY 2903 !arm_feature(env, ARM_FEATURE_V7) && 2904 #endif 2905 (env->cp15.sctlr_el[1] & SCTLR_B) != 0; 2906 } 2907 2908 /* Return true if the processor is in big-endian mode. */ 2909 static inline bool arm_cpu_data_is_big_endian(CPUARMState *env) 2910 { 2911 int cur_el; 2912 2913 /* In 32bit endianness is determined by looking at CPSR's E bit */ 2914 if (!is_a64(env)) { 2915 return 2916 #ifdef CONFIG_USER_ONLY 2917 /* In system mode, BE32 is modelled in line with the 2918 * architecture (as word-invariant big-endianness), where loads 2919 * and stores are done little endian but from addresses which 2920 * are adjusted by XORing with the appropriate constant. So the 2921 * endianness to use for the raw data access is not affected by 2922 * SCTLR.B. 2923 * In user mode, however, we model BE32 as byte-invariant 2924 * big-endianness (because user-only code cannot tell the 2925 * difference), and so we need to use a data access endianness 2926 * that depends on SCTLR.B. 2927 */ 2928 arm_sctlr_b(env) || 2929 #endif 2930 ((env->uncached_cpsr & CPSR_E) ? 1 : 0); 2931 } 2932 2933 cur_el = arm_current_el(env); 2934 2935 if (cur_el == 0) { 2936 return (env->cp15.sctlr_el[1] & SCTLR_E0E) != 0; 2937 } 2938 2939 return (env->cp15.sctlr_el[cur_el] & SCTLR_EE) != 0; 2940 } 2941 2942 #include "exec/cpu-all.h" 2943 2944 /* Bit usage in the TB flags field: bit 31 indicates whether we are 2945 * in 32 or 64 bit mode. The meaning of the other bits depends on that. 2946 * We put flags which are shared between 32 and 64 bit mode at the top 2947 * of the word, and flags which apply to only one mode at the bottom. 2948 */ 2949 FIELD(TBFLAG_ANY, AARCH64_STATE, 31, 1) 2950 FIELD(TBFLAG_ANY, MMUIDX, 28, 3) 2951 FIELD(TBFLAG_ANY, SS_ACTIVE, 27, 1) 2952 FIELD(TBFLAG_ANY, PSTATE_SS, 26, 1) 2953 /* Target EL if we take a floating-point-disabled exception */ 2954 FIELD(TBFLAG_ANY, FPEXC_EL, 24, 2) 2955 FIELD(TBFLAG_ANY, BE_DATA, 23, 1) 2956 2957 /* Bit usage when in AArch32 state: */ 2958 FIELD(TBFLAG_A32, THUMB, 0, 1) 2959 FIELD(TBFLAG_A32, VECLEN, 1, 3) 2960 FIELD(TBFLAG_A32, VECSTRIDE, 4, 2) 2961 FIELD(TBFLAG_A32, VFPEN, 7, 1) 2962 FIELD(TBFLAG_A32, CONDEXEC, 8, 8) 2963 FIELD(TBFLAG_A32, SCTLR_B, 16, 1) 2964 /* We store the bottom two bits of the CPAR as TB flags and handle 2965 * checks on the other bits at runtime 2966 */ 2967 FIELD(TBFLAG_A32, XSCALE_CPAR, 17, 2) 2968 /* Indicates whether cp register reads and writes by guest code should access 2969 * the secure or nonsecure bank of banked registers; note that this is not 2970 * the same thing as the current security state of the processor! 2971 */ 2972 FIELD(TBFLAG_A32, NS, 19, 1) 2973 /* For M profile only, Handler (ie not Thread) mode */ 2974 FIELD(TBFLAG_A32, HANDLER, 21, 1) 2975 /* For M profile only, whether we should generate stack-limit checks */ 2976 FIELD(TBFLAG_A32, STACKCHECK, 22, 1) 2977 2978 /* Bit usage when in AArch64 state */ 2979 FIELD(TBFLAG_A64, TBI0, 0, 1) 2980 FIELD(TBFLAG_A64, TBI1, 1, 1) 2981 FIELD(TBFLAG_A64, SVEEXC_EL, 2, 2) 2982 FIELD(TBFLAG_A64, ZCR_LEN, 4, 4) 2983 2984 static inline bool bswap_code(bool sctlr_b) 2985 { 2986 #ifdef CONFIG_USER_ONLY 2987 /* BE8 (SCTLR.B = 0, TARGET_WORDS_BIGENDIAN = 1) is mixed endian. 2988 * The invalid combination SCTLR.B=1/CPSR.E=1/TARGET_WORDS_BIGENDIAN=0 2989 * would also end up as a mixed-endian mode with BE code, LE data. 2990 */ 2991 return 2992 #ifdef TARGET_WORDS_BIGENDIAN 2993 1 ^ 2994 #endif 2995 sctlr_b; 2996 #else 2997 /* All code access in ARM is little endian, and there are no loaders 2998 * doing swaps that need to be reversed 2999 */ 3000 return 0; 3001 #endif 3002 } 3003 3004 #ifdef CONFIG_USER_ONLY 3005 static inline bool arm_cpu_bswap_data(CPUARMState *env) 3006 { 3007 return 3008 #ifdef TARGET_WORDS_BIGENDIAN 3009 1 ^ 3010 #endif 3011 arm_cpu_data_is_big_endian(env); 3012 } 3013 #endif 3014 3015 #ifndef CONFIG_USER_ONLY 3016 /** 3017 * arm_regime_tbi0: 3018 * @env: CPUARMState 3019 * @mmu_idx: MMU index indicating required translation regime 3020 * 3021 * Extracts the TBI0 value from the appropriate TCR for the current EL 3022 * 3023 * Returns: the TBI0 value. 3024 */ 3025 uint32_t arm_regime_tbi0(CPUARMState *env, ARMMMUIdx mmu_idx); 3026 3027 /** 3028 * arm_regime_tbi1: 3029 * @env: CPUARMState 3030 * @mmu_idx: MMU index indicating required translation regime 3031 * 3032 * Extracts the TBI1 value from the appropriate TCR for the current EL 3033 * 3034 * Returns: the TBI1 value. 3035 */ 3036 uint32_t arm_regime_tbi1(CPUARMState *env, ARMMMUIdx mmu_idx); 3037 #else 3038 /* We can't handle tagged addresses properly in user-only mode */ 3039 static inline uint32_t arm_regime_tbi0(CPUARMState *env, ARMMMUIdx mmu_idx) 3040 { 3041 return 0; 3042 } 3043 3044 static inline uint32_t arm_regime_tbi1(CPUARMState *env, ARMMMUIdx mmu_idx) 3045 { 3046 return 0; 3047 } 3048 #endif 3049 3050 void cpu_get_tb_cpu_state(CPUARMState *env, target_ulong *pc, 3051 target_ulong *cs_base, uint32_t *flags); 3052 3053 enum { 3054 QEMU_PSCI_CONDUIT_DISABLED = 0, 3055 QEMU_PSCI_CONDUIT_SMC = 1, 3056 QEMU_PSCI_CONDUIT_HVC = 2, 3057 }; 3058 3059 #ifndef CONFIG_USER_ONLY 3060 /* Return the address space index to use for a memory access */ 3061 static inline int arm_asidx_from_attrs(CPUState *cs, MemTxAttrs attrs) 3062 { 3063 return attrs.secure ? ARMASIdx_S : ARMASIdx_NS; 3064 } 3065 3066 /* Return the AddressSpace to use for a memory access 3067 * (which depends on whether the access is S or NS, and whether 3068 * the board gave us a separate AddressSpace for S accesses). 3069 */ 3070 static inline AddressSpace *arm_addressspace(CPUState *cs, MemTxAttrs attrs) 3071 { 3072 return cpu_get_address_space(cs, arm_asidx_from_attrs(cs, attrs)); 3073 } 3074 #endif 3075 3076 /** 3077 * arm_register_pre_el_change_hook: 3078 * Register a hook function which will be called immediately before this 3079 * CPU changes exception level or mode. The hook function will be 3080 * passed a pointer to the ARMCPU and the opaque data pointer passed 3081 * to this function when the hook was registered. 3082 * 3083 * Note that if a pre-change hook is called, any registered post-change hooks 3084 * are guaranteed to subsequently be called. 3085 */ 3086 void arm_register_pre_el_change_hook(ARMCPU *cpu, ARMELChangeHookFn *hook, 3087 void *opaque); 3088 /** 3089 * arm_register_el_change_hook: 3090 * Register a hook function which will be called immediately after this 3091 * CPU changes exception level or mode. The hook function will be 3092 * passed a pointer to the ARMCPU and the opaque data pointer passed 3093 * to this function when the hook was registered. 3094 * 3095 * Note that any registered hooks registered here are guaranteed to be called 3096 * if pre-change hooks have been. 3097 */ 3098 void arm_register_el_change_hook(ARMCPU *cpu, ARMELChangeHookFn *hook, void 3099 *opaque); 3100 3101 /** 3102 * aa32_vfp_dreg: 3103 * Return a pointer to the Dn register within env in 32-bit mode. 3104 */ 3105 static inline uint64_t *aa32_vfp_dreg(CPUARMState *env, unsigned regno) 3106 { 3107 return &env->vfp.zregs[regno >> 1].d[regno & 1]; 3108 } 3109 3110 /** 3111 * aa32_vfp_qreg: 3112 * Return a pointer to the Qn register within env in 32-bit mode. 3113 */ 3114 static inline uint64_t *aa32_vfp_qreg(CPUARMState *env, unsigned regno) 3115 { 3116 return &env->vfp.zregs[regno].d[0]; 3117 } 3118 3119 /** 3120 * aa64_vfp_qreg: 3121 * Return a pointer to the Qn register within env in 64-bit mode. 3122 */ 3123 static inline uint64_t *aa64_vfp_qreg(CPUARMState *env, unsigned regno) 3124 { 3125 return &env->vfp.zregs[regno].d[0]; 3126 } 3127 3128 /* Shared between translate-sve.c and sve_helper.c. */ 3129 extern const uint64_t pred_esz_masks[4]; 3130 3131 /* 3132 * 32-bit feature tests via id registers. 3133 */ 3134 static inline bool isar_feature_thumb_div(const ARMISARegisters *id) 3135 { 3136 return FIELD_EX32(id->id_isar0, ID_ISAR0, DIVIDE) != 0; 3137 } 3138 3139 static inline bool isar_feature_arm_div(const ARMISARegisters *id) 3140 { 3141 return FIELD_EX32(id->id_isar0, ID_ISAR0, DIVIDE) > 1; 3142 } 3143 3144 static inline bool isar_feature_jazelle(const ARMISARegisters *id) 3145 { 3146 return FIELD_EX32(id->id_isar1, ID_ISAR1, JAZELLE) != 0; 3147 } 3148 3149 static inline bool isar_feature_aa32_aes(const ARMISARegisters *id) 3150 { 3151 return FIELD_EX32(id->id_isar5, ID_ISAR5, AES) != 0; 3152 } 3153 3154 static inline bool isar_feature_aa32_pmull(const ARMISARegisters *id) 3155 { 3156 return FIELD_EX32(id->id_isar5, ID_ISAR5, AES) > 1; 3157 } 3158 3159 static inline bool isar_feature_aa32_sha1(const ARMISARegisters *id) 3160 { 3161 return FIELD_EX32(id->id_isar5, ID_ISAR5, SHA1) != 0; 3162 } 3163 3164 static inline bool isar_feature_aa32_sha2(const ARMISARegisters *id) 3165 { 3166 return FIELD_EX32(id->id_isar5, ID_ISAR5, SHA2) != 0; 3167 } 3168 3169 static inline bool isar_feature_aa32_crc32(const ARMISARegisters *id) 3170 { 3171 return FIELD_EX32(id->id_isar5, ID_ISAR5, CRC32) != 0; 3172 } 3173 3174 static inline bool isar_feature_aa32_rdm(const ARMISARegisters *id) 3175 { 3176 return FIELD_EX32(id->id_isar5, ID_ISAR5, RDM) != 0; 3177 } 3178 3179 static inline bool isar_feature_aa32_vcma(const ARMISARegisters *id) 3180 { 3181 return FIELD_EX32(id->id_isar5, ID_ISAR5, VCMA) != 0; 3182 } 3183 3184 static inline bool isar_feature_aa32_dp(const ARMISARegisters *id) 3185 { 3186 return FIELD_EX32(id->id_isar6, ID_ISAR6, DP) != 0; 3187 } 3188 3189 static inline bool isar_feature_aa32_fp16_arith(const ARMISARegisters *id) 3190 { 3191 /* 3192 * This is a placeholder for use by VCMA until the rest of 3193 * the ARMv8.2-FP16 extension is implemented for aa32 mode. 3194 * At which point we can properly set and check MVFR1.FPHP. 3195 */ 3196 return FIELD_EX64(id->id_aa64pfr0, ID_AA64PFR0, FP) == 1; 3197 } 3198 3199 /* 3200 * 64-bit feature tests via id registers. 3201 */ 3202 static inline bool isar_feature_aa64_aes(const ARMISARegisters *id) 3203 { 3204 return FIELD_EX64(id->id_aa64isar0, ID_AA64ISAR0, AES) != 0; 3205 } 3206 3207 static inline bool isar_feature_aa64_pmull(const ARMISARegisters *id) 3208 { 3209 return FIELD_EX64(id->id_aa64isar0, ID_AA64ISAR0, AES) > 1; 3210 } 3211 3212 static inline bool isar_feature_aa64_sha1(const ARMISARegisters *id) 3213 { 3214 return FIELD_EX64(id->id_aa64isar0, ID_AA64ISAR0, SHA1) != 0; 3215 } 3216 3217 static inline bool isar_feature_aa64_sha256(const ARMISARegisters *id) 3218 { 3219 return FIELD_EX64(id->id_aa64isar0, ID_AA64ISAR0, SHA2) != 0; 3220 } 3221 3222 static inline bool isar_feature_aa64_sha512(const ARMISARegisters *id) 3223 { 3224 return FIELD_EX64(id->id_aa64isar0, ID_AA64ISAR0, SHA2) > 1; 3225 } 3226 3227 static inline bool isar_feature_aa64_crc32(const ARMISARegisters *id) 3228 { 3229 return FIELD_EX64(id->id_aa64isar0, ID_AA64ISAR0, CRC32) != 0; 3230 } 3231 3232 static inline bool isar_feature_aa64_atomics(const ARMISARegisters *id) 3233 { 3234 return FIELD_EX64(id->id_aa64isar0, ID_AA64ISAR0, ATOMIC) != 0; 3235 } 3236 3237 static inline bool isar_feature_aa64_rdm(const ARMISARegisters *id) 3238 { 3239 return FIELD_EX64(id->id_aa64isar0, ID_AA64ISAR0, RDM) != 0; 3240 } 3241 3242 static inline bool isar_feature_aa64_sha3(const ARMISARegisters *id) 3243 { 3244 return FIELD_EX64(id->id_aa64isar0, ID_AA64ISAR0, SHA3) != 0; 3245 } 3246 3247 static inline bool isar_feature_aa64_sm3(const ARMISARegisters *id) 3248 { 3249 return FIELD_EX64(id->id_aa64isar0, ID_AA64ISAR0, SM3) != 0; 3250 } 3251 3252 static inline bool isar_feature_aa64_sm4(const ARMISARegisters *id) 3253 { 3254 return FIELD_EX64(id->id_aa64isar0, ID_AA64ISAR0, SM4) != 0; 3255 } 3256 3257 static inline bool isar_feature_aa64_dp(const ARMISARegisters *id) 3258 { 3259 return FIELD_EX64(id->id_aa64isar0, ID_AA64ISAR0, DP) != 0; 3260 } 3261 3262 static inline bool isar_feature_aa64_fcma(const ARMISARegisters *id) 3263 { 3264 return FIELD_EX64(id->id_aa64isar1, ID_AA64ISAR1, FCMA) != 0; 3265 } 3266 3267 static inline bool isar_feature_aa64_fp16(const ARMISARegisters *id) 3268 { 3269 /* We always set the AdvSIMD and FP fields identically wrt FP16. */ 3270 return FIELD_EX64(id->id_aa64pfr0, ID_AA64PFR0, FP) == 1; 3271 } 3272 3273 static inline bool isar_feature_aa64_aa32(const ARMISARegisters *id) 3274 { 3275 return FIELD_EX64(id->id_aa64pfr0, ID_AA64PFR0, EL0) >= 2; 3276 } 3277 3278 static inline bool isar_feature_aa64_sve(const ARMISARegisters *id) 3279 { 3280 return FIELD_EX64(id->id_aa64pfr0, ID_AA64PFR0, SVE) != 0; 3281 } 3282 3283 static inline bool isar_feature_aa64_lor(const ARMISARegisters *id) 3284 { 3285 return FIELD_EX64(id->id_aa64mmfr1, ID_AA64MMFR1, LO) != 0; 3286 } 3287 3288 /* 3289 * Forward to the above feature tests given an ARMCPU pointer. 3290 */ 3291 #define cpu_isar_feature(name, cpu) \ 3292 ({ ARMCPU *cpu_ = (cpu); isar_feature_##name(&cpu_->isar); }) 3293 3294 #endif 3295