1 /* 2 * ARM virtual CPU header 3 * 4 * Copyright (c) 2003 Fabrice Bellard 5 * 6 * This library is free software; you can redistribute it and/or 7 * modify it under the terms of the GNU Lesser General Public 8 * License as published by the Free Software Foundation; either 9 * version 2 of the License, or (at your option) any later version. 10 * 11 * This library is distributed in the hope that it will be useful, 12 * but WITHOUT ANY WARRANTY; without even the implied warranty of 13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU 14 * Lesser General Public License for more details. 15 * 16 * You should have received a copy of the GNU Lesser General Public 17 * License along with this library; if not, see <http://www.gnu.org/licenses/>. 18 */ 19 20 #ifndef ARM_CPU_H 21 #define ARM_CPU_H 22 23 #include "kvm-consts.h" 24 #include "hw/registerfields.h" 25 #include "cpu-qom.h" 26 #include "exec/cpu-defs.h" 27 28 /* ARM processors have a weak memory model */ 29 #define TCG_GUEST_DEFAULT_MO (0) 30 31 #ifdef TARGET_AARCH64 32 #define KVM_HAVE_MCE_INJECTION 1 33 #endif 34 35 #define EXCP_UDEF 1 /* undefined instruction */ 36 #define EXCP_SWI 2 /* software interrupt */ 37 #define EXCP_PREFETCH_ABORT 3 38 #define EXCP_DATA_ABORT 4 39 #define EXCP_IRQ 5 40 #define EXCP_FIQ 6 41 #define EXCP_BKPT 7 42 #define EXCP_EXCEPTION_EXIT 8 /* Return from v7M exception. */ 43 #define EXCP_KERNEL_TRAP 9 /* Jumped to kernel code page. */ 44 #define EXCP_HVC 11 /* HyperVisor Call */ 45 #define EXCP_HYP_TRAP 12 46 #define EXCP_SMC 13 /* Secure Monitor Call */ 47 #define EXCP_VIRQ 14 48 #define EXCP_VFIQ 15 49 #define EXCP_SEMIHOST 16 /* semihosting call */ 50 #define EXCP_NOCP 17 /* v7M NOCP UsageFault */ 51 #define EXCP_INVSTATE 18 /* v7M INVSTATE UsageFault */ 52 #define EXCP_STKOF 19 /* v8M STKOF UsageFault */ 53 #define EXCP_LAZYFP 20 /* v7M fault during lazy FP stacking */ 54 #define EXCP_LSERR 21 /* v8M LSERR SecureFault */ 55 #define EXCP_UNALIGNED 22 /* v7M UNALIGNED UsageFault */ 56 /* NB: add new EXCP_ defines to the array in arm_log_exception() too */ 57 58 #define ARMV7M_EXCP_RESET 1 59 #define ARMV7M_EXCP_NMI 2 60 #define ARMV7M_EXCP_HARD 3 61 #define ARMV7M_EXCP_MEM 4 62 #define ARMV7M_EXCP_BUS 5 63 #define ARMV7M_EXCP_USAGE 6 64 #define ARMV7M_EXCP_SECURE 7 65 #define ARMV7M_EXCP_SVC 11 66 #define ARMV7M_EXCP_DEBUG 12 67 #define ARMV7M_EXCP_PENDSV 14 68 #define ARMV7M_EXCP_SYSTICK 15 69 70 /* For M profile, some registers are banked secure vs non-secure; 71 * these are represented as a 2-element array where the first element 72 * is the non-secure copy and the second is the secure copy. 73 * When the CPU does not have implement the security extension then 74 * only the first element is used. 75 * This means that the copy for the current security state can be 76 * accessed via env->registerfield[env->v7m.secure] (whether the security 77 * extension is implemented or not). 78 */ 79 enum { 80 M_REG_NS = 0, 81 M_REG_S = 1, 82 M_REG_NUM_BANKS = 2, 83 }; 84 85 /* ARM-specific interrupt pending bits. */ 86 #define CPU_INTERRUPT_FIQ CPU_INTERRUPT_TGT_EXT_1 87 #define CPU_INTERRUPT_VIRQ CPU_INTERRUPT_TGT_EXT_2 88 #define CPU_INTERRUPT_VFIQ CPU_INTERRUPT_TGT_EXT_3 89 90 /* The usual mapping for an AArch64 system register to its AArch32 91 * counterpart is for the 32 bit world to have access to the lower 92 * half only (with writes leaving the upper half untouched). It's 93 * therefore useful to be able to pass TCG the offset of the least 94 * significant half of a uint64_t struct member. 95 */ 96 #ifdef HOST_WORDS_BIGENDIAN 97 #define offsetoflow32(S, M) (offsetof(S, M) + sizeof(uint32_t)) 98 #define offsetofhigh32(S, M) offsetof(S, M) 99 #else 100 #define offsetoflow32(S, M) offsetof(S, M) 101 #define offsetofhigh32(S, M) (offsetof(S, M) + sizeof(uint32_t)) 102 #endif 103 104 /* Meanings of the ARMCPU object's four inbound GPIO lines */ 105 #define ARM_CPU_IRQ 0 106 #define ARM_CPU_FIQ 1 107 #define ARM_CPU_VIRQ 2 108 #define ARM_CPU_VFIQ 3 109 110 /* ARM-specific extra insn start words: 111 * 1: Conditional execution bits 112 * 2: Partial exception syndrome for data aborts 113 */ 114 #define TARGET_INSN_START_EXTRA_WORDS 2 115 116 /* The 2nd extra word holding syndrome info for data aborts does not use 117 * the upper 6 bits nor the lower 14 bits. We mask and shift it down to 118 * help the sleb128 encoder do a better job. 119 * When restoring the CPU state, we shift it back up. 120 */ 121 #define ARM_INSN_START_WORD2_MASK ((1 << 26) - 1) 122 #define ARM_INSN_START_WORD2_SHIFT 14 123 124 /* We currently assume float and double are IEEE single and double 125 precision respectively. 126 Doing runtime conversions is tricky because VFP registers may contain 127 integer values (eg. as the result of a FTOSI instruction). 128 s<2n> maps to the least significant half of d<n> 129 s<2n+1> maps to the most significant half of d<n> 130 */ 131 132 /** 133 * DynamicGDBXMLInfo: 134 * @desc: Contains the XML descriptions. 135 * @num: Number of the registers in this XML seen by GDB. 136 * @data: A union with data specific to the set of registers 137 * @cpregs_keys: Array that contains the corresponding Key of 138 * a given cpreg with the same order of the cpreg 139 * in the XML description. 140 */ 141 typedef struct DynamicGDBXMLInfo { 142 char *desc; 143 int num; 144 union { 145 struct { 146 uint32_t *keys; 147 } cpregs; 148 } data; 149 } DynamicGDBXMLInfo; 150 151 /* CPU state for each instance of a generic timer (in cp15 c14) */ 152 typedef struct ARMGenericTimer { 153 uint64_t cval; /* Timer CompareValue register */ 154 uint64_t ctl; /* Timer Control register */ 155 } ARMGenericTimer; 156 157 #define GTIMER_PHYS 0 158 #define GTIMER_VIRT 1 159 #define GTIMER_HYP 2 160 #define GTIMER_SEC 3 161 #define GTIMER_HYPVIRT 4 162 #define NUM_GTIMERS 5 163 164 typedef struct { 165 uint64_t raw_tcr; 166 uint32_t mask; 167 uint32_t base_mask; 168 } TCR; 169 170 /* Define a maximum sized vector register. 171 * For 32-bit, this is a 128-bit NEON/AdvSIMD register. 172 * For 64-bit, this is a 2048-bit SVE register. 173 * 174 * Note that the mapping between S, D, and Q views of the register bank 175 * differs between AArch64 and AArch32. 176 * In AArch32: 177 * Qn = regs[n].d[1]:regs[n].d[0] 178 * Dn = regs[n / 2].d[n & 1] 179 * Sn = regs[n / 4].d[n % 4 / 2], 180 * bits 31..0 for even n, and bits 63..32 for odd n 181 * (and regs[16] to regs[31] are inaccessible) 182 * In AArch64: 183 * Zn = regs[n].d[*] 184 * Qn = regs[n].d[1]:regs[n].d[0] 185 * Dn = regs[n].d[0] 186 * Sn = regs[n].d[0] bits 31..0 187 * Hn = regs[n].d[0] bits 15..0 188 * 189 * This corresponds to the architecturally defined mapping between 190 * the two execution states, and means we do not need to explicitly 191 * map these registers when changing states. 192 * 193 * Align the data for use with TCG host vector operations. 194 */ 195 196 #ifdef TARGET_AARCH64 197 # define ARM_MAX_VQ 16 198 void arm_cpu_sve_finalize(ARMCPU *cpu, Error **errp); 199 #else 200 # define ARM_MAX_VQ 1 201 static inline void arm_cpu_sve_finalize(ARMCPU *cpu, Error **errp) { } 202 #endif 203 204 typedef struct ARMVectorReg { 205 uint64_t d[2 * ARM_MAX_VQ] QEMU_ALIGNED(16); 206 } ARMVectorReg; 207 208 #ifdef TARGET_AARCH64 209 /* In AArch32 mode, predicate registers do not exist at all. */ 210 typedef struct ARMPredicateReg { 211 uint64_t p[DIV_ROUND_UP(2 * ARM_MAX_VQ, 8)] QEMU_ALIGNED(16); 212 } ARMPredicateReg; 213 214 /* In AArch32 mode, PAC keys do not exist at all. */ 215 typedef struct ARMPACKey { 216 uint64_t lo, hi; 217 } ARMPACKey; 218 #endif 219 220 221 typedef struct CPUARMState { 222 /* Regs for current mode. */ 223 uint32_t regs[16]; 224 225 /* 32/64 switch only happens when taking and returning from 226 * exceptions so the overlap semantics are taken care of then 227 * instead of having a complicated union. 228 */ 229 /* Regs for A64 mode. */ 230 uint64_t xregs[32]; 231 uint64_t pc; 232 /* PSTATE isn't an architectural register for ARMv8. However, it is 233 * convenient for us to assemble the underlying state into a 32 bit format 234 * identical to the architectural format used for the SPSR. (This is also 235 * what the Linux kernel's 'pstate' field in signal handlers and KVM's 236 * 'pstate' register are.) Of the PSTATE bits: 237 * NZCV are kept in the split out env->CF/VF/NF/ZF, (which have the same 238 * semantics as for AArch32, as described in the comments on each field) 239 * nRW (also known as M[4]) is kept, inverted, in env->aarch64 240 * DAIF (exception masks) are kept in env->daif 241 * BTYPE is kept in env->btype 242 * all other bits are stored in their correct places in env->pstate 243 */ 244 uint32_t pstate; 245 uint32_t aarch64; /* 1 if CPU is in aarch64 state; inverse of PSTATE.nRW */ 246 247 /* Cached TBFLAGS state. See below for which bits are included. */ 248 uint32_t hflags; 249 250 /* Frequently accessed CPSR bits are stored separately for efficiency. 251 This contains all the other bits. Use cpsr_{read,write} to access 252 the whole CPSR. */ 253 uint32_t uncached_cpsr; 254 uint32_t spsr; 255 256 /* Banked registers. */ 257 uint64_t banked_spsr[8]; 258 uint32_t banked_r13[8]; 259 uint32_t banked_r14[8]; 260 261 /* These hold r8-r12. */ 262 uint32_t usr_regs[5]; 263 uint32_t fiq_regs[5]; 264 265 /* cpsr flag cache for faster execution */ 266 uint32_t CF; /* 0 or 1 */ 267 uint32_t VF; /* V is the bit 31. All other bits are undefined */ 268 uint32_t NF; /* N is bit 31. All other bits are undefined. */ 269 uint32_t ZF; /* Z set if zero. */ 270 uint32_t QF; /* 0 or 1 */ 271 uint32_t GE; /* cpsr[19:16] */ 272 uint32_t thumb; /* cpsr[5]. 0 = arm mode, 1 = thumb mode. */ 273 uint32_t condexec_bits; /* IT bits. cpsr[15:10,26:25]. */ 274 uint32_t btype; /* BTI branch type. spsr[11:10]. */ 275 uint64_t daif; /* exception masks, in the bits they are in PSTATE */ 276 277 uint64_t elr_el[4]; /* AArch64 exception link regs */ 278 uint64_t sp_el[4]; /* AArch64 banked stack pointers */ 279 280 /* System control coprocessor (cp15) */ 281 struct { 282 uint32_t c0_cpuid; 283 union { /* Cache size selection */ 284 struct { 285 uint64_t _unused_csselr0; 286 uint64_t csselr_ns; 287 uint64_t _unused_csselr1; 288 uint64_t csselr_s; 289 }; 290 uint64_t csselr_el[4]; 291 }; 292 union { /* System control register. */ 293 struct { 294 uint64_t _unused_sctlr; 295 uint64_t sctlr_ns; 296 uint64_t hsctlr; 297 uint64_t sctlr_s; 298 }; 299 uint64_t sctlr_el[4]; 300 }; 301 uint64_t cpacr_el1; /* Architectural feature access control register */ 302 uint64_t cptr_el[4]; /* ARMv8 feature trap registers */ 303 uint32_t c1_xscaleauxcr; /* XScale auxiliary control register. */ 304 uint64_t sder; /* Secure debug enable register. */ 305 uint32_t nsacr; /* Non-secure access control register. */ 306 union { /* MMU translation table base 0. */ 307 struct { 308 uint64_t _unused_ttbr0_0; 309 uint64_t ttbr0_ns; 310 uint64_t _unused_ttbr0_1; 311 uint64_t ttbr0_s; 312 }; 313 uint64_t ttbr0_el[4]; 314 }; 315 union { /* MMU translation table base 1. */ 316 struct { 317 uint64_t _unused_ttbr1_0; 318 uint64_t ttbr1_ns; 319 uint64_t _unused_ttbr1_1; 320 uint64_t ttbr1_s; 321 }; 322 uint64_t ttbr1_el[4]; 323 }; 324 uint64_t vttbr_el2; /* Virtualization Translation Table Base. */ 325 /* MMU translation table base control. */ 326 TCR tcr_el[4]; 327 TCR vtcr_el2; /* Virtualization Translation Control. */ 328 uint32_t c2_data; /* MPU data cacheable bits. */ 329 uint32_t c2_insn; /* MPU instruction cacheable bits. */ 330 union { /* MMU domain access control register 331 * MPU write buffer control. 332 */ 333 struct { 334 uint64_t dacr_ns; 335 uint64_t dacr_s; 336 }; 337 struct { 338 uint64_t dacr32_el2; 339 }; 340 }; 341 uint32_t pmsav5_data_ap; /* PMSAv5 MPU data access permissions */ 342 uint32_t pmsav5_insn_ap; /* PMSAv5 MPU insn access permissions */ 343 uint64_t hcr_el2; /* Hypervisor configuration register */ 344 uint64_t scr_el3; /* Secure configuration register. */ 345 union { /* Fault status registers. */ 346 struct { 347 uint64_t ifsr_ns; 348 uint64_t ifsr_s; 349 }; 350 struct { 351 uint64_t ifsr32_el2; 352 }; 353 }; 354 union { 355 struct { 356 uint64_t _unused_dfsr; 357 uint64_t dfsr_ns; 358 uint64_t hsr; 359 uint64_t dfsr_s; 360 }; 361 uint64_t esr_el[4]; 362 }; 363 uint32_t c6_region[8]; /* MPU base/size registers. */ 364 union { /* Fault address registers. */ 365 struct { 366 uint64_t _unused_far0; 367 #ifdef HOST_WORDS_BIGENDIAN 368 uint32_t ifar_ns; 369 uint32_t dfar_ns; 370 uint32_t ifar_s; 371 uint32_t dfar_s; 372 #else 373 uint32_t dfar_ns; 374 uint32_t ifar_ns; 375 uint32_t dfar_s; 376 uint32_t ifar_s; 377 #endif 378 uint64_t _unused_far3; 379 }; 380 uint64_t far_el[4]; 381 }; 382 uint64_t hpfar_el2; 383 uint64_t hstr_el2; 384 union { /* Translation result. */ 385 struct { 386 uint64_t _unused_par_0; 387 uint64_t par_ns; 388 uint64_t _unused_par_1; 389 uint64_t par_s; 390 }; 391 uint64_t par_el[4]; 392 }; 393 394 uint32_t c9_insn; /* Cache lockdown registers. */ 395 uint32_t c9_data; 396 uint64_t c9_pmcr; /* performance monitor control register */ 397 uint64_t c9_pmcnten; /* perf monitor counter enables */ 398 uint64_t c9_pmovsr; /* perf monitor overflow status */ 399 uint64_t c9_pmuserenr; /* perf monitor user enable */ 400 uint64_t c9_pmselr; /* perf monitor counter selection register */ 401 uint64_t c9_pminten; /* perf monitor interrupt enables */ 402 union { /* Memory attribute redirection */ 403 struct { 404 #ifdef HOST_WORDS_BIGENDIAN 405 uint64_t _unused_mair_0; 406 uint32_t mair1_ns; 407 uint32_t mair0_ns; 408 uint64_t _unused_mair_1; 409 uint32_t mair1_s; 410 uint32_t mair0_s; 411 #else 412 uint64_t _unused_mair_0; 413 uint32_t mair0_ns; 414 uint32_t mair1_ns; 415 uint64_t _unused_mair_1; 416 uint32_t mair0_s; 417 uint32_t mair1_s; 418 #endif 419 }; 420 uint64_t mair_el[4]; 421 }; 422 union { /* vector base address register */ 423 struct { 424 uint64_t _unused_vbar; 425 uint64_t vbar_ns; 426 uint64_t hvbar; 427 uint64_t vbar_s; 428 }; 429 uint64_t vbar_el[4]; 430 }; 431 uint32_t mvbar; /* (monitor) vector base address register */ 432 struct { /* FCSE PID. */ 433 uint32_t fcseidr_ns; 434 uint32_t fcseidr_s; 435 }; 436 union { /* Context ID. */ 437 struct { 438 uint64_t _unused_contextidr_0; 439 uint64_t contextidr_ns; 440 uint64_t _unused_contextidr_1; 441 uint64_t contextidr_s; 442 }; 443 uint64_t contextidr_el[4]; 444 }; 445 union { /* User RW Thread register. */ 446 struct { 447 uint64_t tpidrurw_ns; 448 uint64_t tpidrprw_ns; 449 uint64_t htpidr; 450 uint64_t _tpidr_el3; 451 }; 452 uint64_t tpidr_el[4]; 453 }; 454 /* The secure banks of these registers don't map anywhere */ 455 uint64_t tpidrurw_s; 456 uint64_t tpidrprw_s; 457 uint64_t tpidruro_s; 458 459 union { /* User RO Thread register. */ 460 uint64_t tpidruro_ns; 461 uint64_t tpidrro_el[1]; 462 }; 463 uint64_t c14_cntfrq; /* Counter Frequency register */ 464 uint64_t c14_cntkctl; /* Timer Control register */ 465 uint32_t cnthctl_el2; /* Counter/Timer Hyp Control register */ 466 uint64_t cntvoff_el2; /* Counter Virtual Offset register */ 467 ARMGenericTimer c14_timer[NUM_GTIMERS]; 468 uint32_t c15_cpar; /* XScale Coprocessor Access Register */ 469 uint32_t c15_ticonfig; /* TI925T configuration byte. */ 470 uint32_t c15_i_max; /* Maximum D-cache dirty line index. */ 471 uint32_t c15_i_min; /* Minimum D-cache dirty line index. */ 472 uint32_t c15_threadid; /* TI debugger thread-ID. */ 473 uint32_t c15_config_base_address; /* SCU base address. */ 474 uint32_t c15_diagnostic; /* diagnostic register */ 475 uint32_t c15_power_diagnostic; 476 uint32_t c15_power_control; /* power control */ 477 uint64_t dbgbvr[16]; /* breakpoint value registers */ 478 uint64_t dbgbcr[16]; /* breakpoint control registers */ 479 uint64_t dbgwvr[16]; /* watchpoint value registers */ 480 uint64_t dbgwcr[16]; /* watchpoint control registers */ 481 uint64_t mdscr_el1; 482 uint64_t oslsr_el1; /* OS Lock Status */ 483 uint64_t mdcr_el2; 484 uint64_t mdcr_el3; 485 /* Stores the architectural value of the counter *the last time it was 486 * updated* by pmccntr_op_start. Accesses should always be surrounded 487 * by pmccntr_op_start/pmccntr_op_finish to guarantee the latest 488 * architecturally-correct value is being read/set. 489 */ 490 uint64_t c15_ccnt; 491 /* Stores the delta between the architectural value and the underlying 492 * cycle count during normal operation. It is used to update c15_ccnt 493 * to be the correct architectural value before accesses. During 494 * accesses, c15_ccnt_delta contains the underlying count being used 495 * for the access, after which it reverts to the delta value in 496 * pmccntr_op_finish. 497 */ 498 uint64_t c15_ccnt_delta; 499 uint64_t c14_pmevcntr[31]; 500 uint64_t c14_pmevcntr_delta[31]; 501 uint64_t c14_pmevtyper[31]; 502 uint64_t pmccfiltr_el0; /* Performance Monitor Filter Register */ 503 uint64_t vpidr_el2; /* Virtualization Processor ID Register */ 504 uint64_t vmpidr_el2; /* Virtualization Multiprocessor ID Register */ 505 } cp15; 506 507 struct { 508 /* M profile has up to 4 stack pointers: 509 * a Main Stack Pointer and a Process Stack Pointer for each 510 * of the Secure and Non-Secure states. (If the CPU doesn't support 511 * the security extension then it has only two SPs.) 512 * In QEMU we always store the currently active SP in regs[13], 513 * and the non-active SP for the current security state in 514 * v7m.other_sp. The stack pointers for the inactive security state 515 * are stored in other_ss_msp and other_ss_psp. 516 * switch_v7m_security_state() is responsible for rearranging them 517 * when we change security state. 518 */ 519 uint32_t other_sp; 520 uint32_t other_ss_msp; 521 uint32_t other_ss_psp; 522 uint32_t vecbase[M_REG_NUM_BANKS]; 523 uint32_t basepri[M_REG_NUM_BANKS]; 524 uint32_t control[M_REG_NUM_BANKS]; 525 uint32_t ccr[M_REG_NUM_BANKS]; /* Configuration and Control */ 526 uint32_t cfsr[M_REG_NUM_BANKS]; /* Configurable Fault Status */ 527 uint32_t hfsr; /* HardFault Status */ 528 uint32_t dfsr; /* Debug Fault Status Register */ 529 uint32_t sfsr; /* Secure Fault Status Register */ 530 uint32_t mmfar[M_REG_NUM_BANKS]; /* MemManage Fault Address */ 531 uint32_t bfar; /* BusFault Address */ 532 uint32_t sfar; /* Secure Fault Address Register */ 533 unsigned mpu_ctrl[M_REG_NUM_BANKS]; /* MPU_CTRL */ 534 int exception; 535 uint32_t primask[M_REG_NUM_BANKS]; 536 uint32_t faultmask[M_REG_NUM_BANKS]; 537 uint32_t aircr; /* only holds r/w state if security extn implemented */ 538 uint32_t secure; /* Is CPU in Secure state? (not guest visible) */ 539 uint32_t csselr[M_REG_NUM_BANKS]; 540 uint32_t scr[M_REG_NUM_BANKS]; 541 uint32_t msplim[M_REG_NUM_BANKS]; 542 uint32_t psplim[M_REG_NUM_BANKS]; 543 uint32_t fpcar[M_REG_NUM_BANKS]; 544 uint32_t fpccr[M_REG_NUM_BANKS]; 545 uint32_t fpdscr[M_REG_NUM_BANKS]; 546 uint32_t cpacr[M_REG_NUM_BANKS]; 547 uint32_t nsacr; 548 } v7m; 549 550 /* Information associated with an exception about to be taken: 551 * code which raises an exception must set cs->exception_index and 552 * the relevant parts of this structure; the cpu_do_interrupt function 553 * will then set the guest-visible registers as part of the exception 554 * entry process. 555 */ 556 struct { 557 uint32_t syndrome; /* AArch64 format syndrome register */ 558 uint32_t fsr; /* AArch32 format fault status register info */ 559 uint64_t vaddress; /* virtual addr associated with exception, if any */ 560 uint32_t target_el; /* EL the exception should be targeted for */ 561 /* If we implement EL2 we will also need to store information 562 * about the intermediate physical address for stage 2 faults. 563 */ 564 } exception; 565 566 /* Information associated with an SError */ 567 struct { 568 uint8_t pending; 569 uint8_t has_esr; 570 uint64_t esr; 571 } serror; 572 573 /* State of our input IRQ/FIQ/VIRQ/VFIQ lines */ 574 uint32_t irq_line_state; 575 576 /* Thumb-2 EE state. */ 577 uint32_t teecr; 578 uint32_t teehbr; 579 580 /* VFP coprocessor state. */ 581 struct { 582 ARMVectorReg zregs[32]; 583 584 #ifdef TARGET_AARCH64 585 /* Store FFR as pregs[16] to make it easier to treat as any other. */ 586 #define FFR_PRED_NUM 16 587 ARMPredicateReg pregs[17]; 588 /* Scratch space for aa64 sve predicate temporary. */ 589 ARMPredicateReg preg_tmp; 590 #endif 591 592 /* We store these fpcsr fields separately for convenience. */ 593 uint32_t qc[4] QEMU_ALIGNED(16); 594 int vec_len; 595 int vec_stride; 596 597 uint32_t xregs[16]; 598 599 /* Scratch space for aa32 neon expansion. */ 600 uint32_t scratch[8]; 601 602 /* There are a number of distinct float control structures: 603 * 604 * fp_status: is the "normal" fp status. 605 * fp_status_fp16: used for half-precision calculations 606 * standard_fp_status : the ARM "Standard FPSCR Value" 607 * 608 * Half-precision operations are governed by a separate 609 * flush-to-zero control bit in FPSCR:FZ16. We pass a separate 610 * status structure to control this. 611 * 612 * The "Standard FPSCR", ie default-NaN, flush-to-zero, 613 * round-to-nearest and is used by any operations (generally 614 * Neon) which the architecture defines as controlled by the 615 * standard FPSCR value rather than the FPSCR. 616 * 617 * To avoid having to transfer exception bits around, we simply 618 * say that the FPSCR cumulative exception flags are the logical 619 * OR of the flags in the three fp statuses. This relies on the 620 * only thing which needs to read the exception flags being 621 * an explicit FPSCR read. 622 */ 623 float_status fp_status; 624 float_status fp_status_f16; 625 float_status standard_fp_status; 626 627 /* ZCR_EL[1-3] */ 628 uint64_t zcr_el[4]; 629 } vfp; 630 uint64_t exclusive_addr; 631 uint64_t exclusive_val; 632 uint64_t exclusive_high; 633 634 /* iwMMXt coprocessor state. */ 635 struct { 636 uint64_t regs[16]; 637 uint64_t val; 638 639 uint32_t cregs[16]; 640 } iwmmxt; 641 642 #ifdef TARGET_AARCH64 643 struct { 644 ARMPACKey apia; 645 ARMPACKey apib; 646 ARMPACKey apda; 647 ARMPACKey apdb; 648 ARMPACKey apga; 649 } keys; 650 #endif 651 652 #if defined(CONFIG_USER_ONLY) 653 /* For usermode syscall translation. */ 654 int eabi; 655 #endif 656 657 struct CPUBreakpoint *cpu_breakpoint[16]; 658 struct CPUWatchpoint *cpu_watchpoint[16]; 659 660 /* Fields up to this point are cleared by a CPU reset */ 661 struct {} end_reset_fields; 662 663 /* Fields after this point are preserved across CPU reset. */ 664 665 /* Internal CPU feature flags. */ 666 uint64_t features; 667 668 /* PMSAv7 MPU */ 669 struct { 670 uint32_t *drbar; 671 uint32_t *drsr; 672 uint32_t *dracr; 673 uint32_t rnr[M_REG_NUM_BANKS]; 674 } pmsav7; 675 676 /* PMSAv8 MPU */ 677 struct { 678 /* The PMSAv8 implementation also shares some PMSAv7 config 679 * and state: 680 * pmsav7.rnr (region number register) 681 * pmsav7_dregion (number of configured regions) 682 */ 683 uint32_t *rbar[M_REG_NUM_BANKS]; 684 uint32_t *rlar[M_REG_NUM_BANKS]; 685 uint32_t mair0[M_REG_NUM_BANKS]; 686 uint32_t mair1[M_REG_NUM_BANKS]; 687 } pmsav8; 688 689 /* v8M SAU */ 690 struct { 691 uint32_t *rbar; 692 uint32_t *rlar; 693 uint32_t rnr; 694 uint32_t ctrl; 695 } sau; 696 697 void *nvic; 698 const struct arm_boot_info *boot_info; 699 /* Store GICv3CPUState to access from this struct */ 700 void *gicv3state; 701 } CPUARMState; 702 703 static inline void set_feature(CPUARMState *env, int feature) 704 { 705 env->features |= 1ULL << feature; 706 } 707 708 static inline void unset_feature(CPUARMState *env, int feature) 709 { 710 env->features &= ~(1ULL << feature); 711 } 712 713 /** 714 * ARMELChangeHookFn: 715 * type of a function which can be registered via arm_register_el_change_hook() 716 * to get callbacks when the CPU changes its exception level or mode. 717 */ 718 typedef void ARMELChangeHookFn(ARMCPU *cpu, void *opaque); 719 typedef struct ARMELChangeHook ARMELChangeHook; 720 struct ARMELChangeHook { 721 ARMELChangeHookFn *hook; 722 void *opaque; 723 QLIST_ENTRY(ARMELChangeHook) node; 724 }; 725 726 /* These values map onto the return values for 727 * QEMU_PSCI_0_2_FN_AFFINITY_INFO */ 728 typedef enum ARMPSCIState { 729 PSCI_ON = 0, 730 PSCI_OFF = 1, 731 PSCI_ON_PENDING = 2 732 } ARMPSCIState; 733 734 typedef struct ARMISARegisters ARMISARegisters; 735 736 /** 737 * ARMCPU: 738 * @env: #CPUARMState 739 * 740 * An ARM CPU core. 741 */ 742 struct ARMCPU { 743 /*< private >*/ 744 CPUState parent_obj; 745 /*< public >*/ 746 747 CPUNegativeOffsetState neg; 748 CPUARMState env; 749 750 /* Coprocessor information */ 751 GHashTable *cp_regs; 752 /* For marshalling (mostly coprocessor) register state between the 753 * kernel and QEMU (for KVM) and between two QEMUs (for migration), 754 * we use these arrays. 755 */ 756 /* List of register indexes managed via these arrays; (full KVM style 757 * 64 bit indexes, not CPRegInfo 32 bit indexes) 758 */ 759 uint64_t *cpreg_indexes; 760 /* Values of the registers (cpreg_indexes[i]'s value is cpreg_values[i]) */ 761 uint64_t *cpreg_values; 762 /* Length of the indexes, values, reset_values arrays */ 763 int32_t cpreg_array_len; 764 /* These are used only for migration: incoming data arrives in 765 * these fields and is sanity checked in post_load before copying 766 * to the working data structures above. 767 */ 768 uint64_t *cpreg_vmstate_indexes; 769 uint64_t *cpreg_vmstate_values; 770 int32_t cpreg_vmstate_array_len; 771 772 DynamicGDBXMLInfo dyn_sysreg_xml; 773 DynamicGDBXMLInfo dyn_svereg_xml; 774 775 /* Timers used by the generic (architected) timer */ 776 QEMUTimer *gt_timer[NUM_GTIMERS]; 777 /* 778 * Timer used by the PMU. Its state is restored after migration by 779 * pmu_op_finish() - it does not need other handling during migration 780 */ 781 QEMUTimer *pmu_timer; 782 /* GPIO outputs for generic timer */ 783 qemu_irq gt_timer_outputs[NUM_GTIMERS]; 784 /* GPIO output for GICv3 maintenance interrupt signal */ 785 qemu_irq gicv3_maintenance_interrupt; 786 /* GPIO output for the PMU interrupt */ 787 qemu_irq pmu_interrupt; 788 789 /* MemoryRegion to use for secure physical accesses */ 790 MemoryRegion *secure_memory; 791 792 /* For v8M, pointer to the IDAU interface provided by board/SoC */ 793 Object *idau; 794 795 /* 'compatible' string for this CPU for Linux device trees */ 796 const char *dtb_compatible; 797 798 /* PSCI version for this CPU 799 * Bits[31:16] = Major Version 800 * Bits[15:0] = Minor Version 801 */ 802 uint32_t psci_version; 803 804 /* Should CPU start in PSCI powered-off state? */ 805 bool start_powered_off; 806 807 /* Current power state, access guarded by BQL */ 808 ARMPSCIState power_state; 809 810 /* CPU has virtualization extension */ 811 bool has_el2; 812 /* CPU has security extension */ 813 bool has_el3; 814 /* CPU has PMU (Performance Monitor Unit) */ 815 bool has_pmu; 816 /* CPU has VFP */ 817 bool has_vfp; 818 /* CPU has Neon */ 819 bool has_neon; 820 /* CPU has M-profile DSP extension */ 821 bool has_dsp; 822 823 /* CPU has memory protection unit */ 824 bool has_mpu; 825 /* PMSAv7 MPU number of supported regions */ 826 uint32_t pmsav7_dregion; 827 /* v8M SAU number of supported regions */ 828 uint32_t sau_sregion; 829 830 /* PSCI conduit used to invoke PSCI methods 831 * 0 - disabled, 1 - smc, 2 - hvc 832 */ 833 uint32_t psci_conduit; 834 835 /* For v8M, initial value of the Secure VTOR */ 836 uint32_t init_svtor; 837 838 /* [QEMU_]KVM_ARM_TARGET_* constant for this CPU, or 839 * QEMU_KVM_ARM_TARGET_NONE if the kernel doesn't support this CPU type. 840 */ 841 uint32_t kvm_target; 842 843 /* KVM init features for this CPU */ 844 uint32_t kvm_init_features[7]; 845 846 /* KVM CPU state */ 847 848 /* KVM virtual time adjustment */ 849 bool kvm_adjvtime; 850 bool kvm_vtime_dirty; 851 uint64_t kvm_vtime; 852 853 /* Uniprocessor system with MP extensions */ 854 bool mp_is_up; 855 856 /* True if we tried kvm_arm_host_cpu_features() during CPU instance_init 857 * and the probe failed (so we need to report the error in realize) 858 */ 859 bool host_cpu_probe_failed; 860 861 /* Specify the number of cores in this CPU cluster. Used for the L2CTLR 862 * register. 863 */ 864 int32_t core_count; 865 866 /* The instance init functions for implementation-specific subclasses 867 * set these fields to specify the implementation-dependent values of 868 * various constant registers and reset values of non-constant 869 * registers. 870 * Some of these might become QOM properties eventually. 871 * Field names match the official register names as defined in the 872 * ARMv7AR ARM Architecture Reference Manual. A reset_ prefix 873 * is used for reset values of non-constant registers; no reset_ 874 * prefix means a constant register. 875 * Some of these registers are split out into a substructure that 876 * is shared with the translators to control the ISA. 877 * 878 * Note that if you add an ID register to the ARMISARegisters struct 879 * you need to also update the 32-bit and 64-bit versions of the 880 * kvm_arm_get_host_cpu_features() function to correctly populate the 881 * field by reading the value from the KVM vCPU. 882 */ 883 struct ARMISARegisters { 884 uint32_t id_isar0; 885 uint32_t id_isar1; 886 uint32_t id_isar2; 887 uint32_t id_isar3; 888 uint32_t id_isar4; 889 uint32_t id_isar5; 890 uint32_t id_isar6; 891 uint32_t id_mmfr0; 892 uint32_t id_mmfr1; 893 uint32_t id_mmfr2; 894 uint32_t id_mmfr3; 895 uint32_t id_mmfr4; 896 uint32_t mvfr0; 897 uint32_t mvfr1; 898 uint32_t mvfr2; 899 uint32_t id_dfr0; 900 uint32_t dbgdidr; 901 uint64_t id_aa64isar0; 902 uint64_t id_aa64isar1; 903 uint64_t id_aa64pfr0; 904 uint64_t id_aa64pfr1; 905 uint64_t id_aa64mmfr0; 906 uint64_t id_aa64mmfr1; 907 uint64_t id_aa64mmfr2; 908 uint64_t id_aa64dfr0; 909 uint64_t id_aa64dfr1; 910 } isar; 911 uint64_t midr; 912 uint32_t revidr; 913 uint32_t reset_fpsid; 914 uint32_t ctr; 915 uint32_t reset_sctlr; 916 uint32_t id_pfr0; 917 uint32_t id_pfr1; 918 uint64_t pmceid0; 919 uint64_t pmceid1; 920 uint32_t id_afr0; 921 uint64_t id_aa64afr0; 922 uint64_t id_aa64afr1; 923 uint32_t clidr; 924 uint64_t mp_affinity; /* MP ID without feature bits */ 925 /* The elements of this array are the CCSIDR values for each cache, 926 * in the order L1DCache, L1ICache, L2DCache, L2ICache, etc. 927 */ 928 uint64_t ccsidr[16]; 929 uint64_t reset_cbar; 930 uint32_t reset_auxcr; 931 bool reset_hivecs; 932 /* DCZ blocksize, in log_2(words), ie low 4 bits of DCZID_EL0 */ 933 uint32_t dcz_blocksize; 934 uint64_t rvbar; 935 936 /* Configurable aspects of GIC cpu interface (which is part of the CPU) */ 937 int gic_num_lrs; /* number of list registers */ 938 int gic_vpribits; /* number of virtual priority bits */ 939 int gic_vprebits; /* number of virtual preemption bits */ 940 941 /* Whether the cfgend input is high (i.e. this CPU should reset into 942 * big-endian mode). This setting isn't used directly: instead it modifies 943 * the reset_sctlr value to have SCTLR_B or SCTLR_EE set, depending on the 944 * architecture version. 945 */ 946 bool cfgend; 947 948 QLIST_HEAD(, ARMELChangeHook) pre_el_change_hooks; 949 QLIST_HEAD(, ARMELChangeHook) el_change_hooks; 950 951 int32_t node_id; /* NUMA node this CPU belongs to */ 952 953 /* Used to synchronize KVM and QEMU in-kernel device levels */ 954 uint8_t device_irq_level; 955 956 /* Used to set the maximum vector length the cpu will support. */ 957 uint32_t sve_max_vq; 958 959 /* 960 * In sve_vq_map each set bit is a supported vector length of 961 * (bit-number + 1) * 16 bytes, i.e. each bit number + 1 is the vector 962 * length in quadwords. 963 * 964 * While processing properties during initialization, corresponding 965 * sve_vq_init bits are set for bits in sve_vq_map that have been 966 * set by properties. 967 */ 968 DECLARE_BITMAP(sve_vq_map, ARM_MAX_VQ); 969 DECLARE_BITMAP(sve_vq_init, ARM_MAX_VQ); 970 971 /* Generic timer counter frequency, in Hz */ 972 uint64_t gt_cntfrq_hz; 973 }; 974 975 unsigned int gt_cntfrq_period_ns(ARMCPU *cpu); 976 977 void arm_cpu_post_init(Object *obj); 978 979 uint64_t arm_cpu_mp_affinity(int idx, uint8_t clustersz); 980 981 #ifndef CONFIG_USER_ONLY 982 extern const VMStateDescription vmstate_arm_cpu; 983 #endif 984 985 void arm_cpu_do_interrupt(CPUState *cpu); 986 void arm_v7m_cpu_do_interrupt(CPUState *cpu); 987 bool arm_cpu_exec_interrupt(CPUState *cpu, int int_req); 988 989 hwaddr arm_cpu_get_phys_page_attrs_debug(CPUState *cpu, vaddr addr, 990 MemTxAttrs *attrs); 991 992 int arm_cpu_gdb_read_register(CPUState *cpu, GByteArray *buf, int reg); 993 int arm_cpu_gdb_write_register(CPUState *cpu, uint8_t *buf, int reg); 994 995 /* 996 * Helpers to dynamically generates XML descriptions of the sysregs 997 * and SVE registers. Returns the number of registers in each set. 998 */ 999 int arm_gen_dynamic_sysreg_xml(CPUState *cpu, int base_reg); 1000 int arm_gen_dynamic_svereg_xml(CPUState *cpu, int base_reg); 1001 1002 /* Returns the dynamically generated XML for the gdb stub. 1003 * Returns a pointer to the XML contents for the specified XML file or NULL 1004 * if the XML name doesn't match the predefined one. 1005 */ 1006 const char *arm_gdb_get_dynamic_xml(CPUState *cpu, const char *xmlname); 1007 1008 int arm_cpu_write_elf64_note(WriteCoreDumpFunction f, CPUState *cs, 1009 int cpuid, void *opaque); 1010 int arm_cpu_write_elf32_note(WriteCoreDumpFunction f, CPUState *cs, 1011 int cpuid, void *opaque); 1012 1013 #ifdef TARGET_AARCH64 1014 int aarch64_cpu_gdb_read_register(CPUState *cpu, GByteArray *buf, int reg); 1015 int aarch64_cpu_gdb_write_register(CPUState *cpu, uint8_t *buf, int reg); 1016 void aarch64_sve_narrow_vq(CPUARMState *env, unsigned vq); 1017 void aarch64_sve_change_el(CPUARMState *env, int old_el, 1018 int new_el, bool el0_a64); 1019 void aarch64_add_sve_properties(Object *obj); 1020 1021 /* 1022 * SVE registers are encoded in KVM's memory in an endianness-invariant format. 1023 * The byte at offset i from the start of the in-memory representation contains 1024 * the bits [(7 + 8 * i) : (8 * i)] of the register value. As this means the 1025 * lowest offsets are stored in the lowest memory addresses, then that nearly 1026 * matches QEMU's representation, which is to use an array of host-endian 1027 * uint64_t's, where the lower offsets are at the lower indices. To complete 1028 * the translation we just need to byte swap the uint64_t's on big-endian hosts. 1029 */ 1030 static inline uint64_t *sve_bswap64(uint64_t *dst, uint64_t *src, int nr) 1031 { 1032 #ifdef HOST_WORDS_BIGENDIAN 1033 int i; 1034 1035 for (i = 0; i < nr; ++i) { 1036 dst[i] = bswap64(src[i]); 1037 } 1038 1039 return dst; 1040 #else 1041 return src; 1042 #endif 1043 } 1044 1045 #else 1046 static inline void aarch64_sve_narrow_vq(CPUARMState *env, unsigned vq) { } 1047 static inline void aarch64_sve_change_el(CPUARMState *env, int o, 1048 int n, bool a) 1049 { } 1050 static inline void aarch64_add_sve_properties(Object *obj) { } 1051 #endif 1052 1053 #if !defined(CONFIG_TCG) 1054 static inline target_ulong do_arm_semihosting(CPUARMState *env) 1055 { 1056 g_assert_not_reached(); 1057 } 1058 #else 1059 target_ulong do_arm_semihosting(CPUARMState *env); 1060 #endif 1061 void aarch64_sync_32_to_64(CPUARMState *env); 1062 void aarch64_sync_64_to_32(CPUARMState *env); 1063 1064 int fp_exception_el(CPUARMState *env, int cur_el); 1065 int sve_exception_el(CPUARMState *env, int cur_el); 1066 uint32_t sve_zcr_len_for_el(CPUARMState *env, int el); 1067 1068 static inline bool is_a64(CPUARMState *env) 1069 { 1070 return env->aarch64; 1071 } 1072 1073 /* you can call this signal handler from your SIGBUS and SIGSEGV 1074 signal handlers to inform the virtual CPU of exceptions. non zero 1075 is returned if the signal was handled by the virtual CPU. */ 1076 int cpu_arm_signal_handler(int host_signum, void *pinfo, 1077 void *puc); 1078 1079 /** 1080 * pmu_op_start/finish 1081 * @env: CPUARMState 1082 * 1083 * Convert all PMU counters between their delta form (the typical mode when 1084 * they are enabled) and the guest-visible values. These two calls must 1085 * surround any action which might affect the counters. 1086 */ 1087 void pmu_op_start(CPUARMState *env); 1088 void pmu_op_finish(CPUARMState *env); 1089 1090 /* 1091 * Called when a PMU counter is due to overflow 1092 */ 1093 void arm_pmu_timer_cb(void *opaque); 1094 1095 /** 1096 * Functions to register as EL change hooks for PMU mode filtering 1097 */ 1098 void pmu_pre_el_change(ARMCPU *cpu, void *ignored); 1099 void pmu_post_el_change(ARMCPU *cpu, void *ignored); 1100 1101 /* 1102 * pmu_init 1103 * @cpu: ARMCPU 1104 * 1105 * Initialize the CPU's PMCEID[01]_EL0 registers and associated internal state 1106 * for the current configuration 1107 */ 1108 void pmu_init(ARMCPU *cpu); 1109 1110 /* SCTLR bit meanings. Several bits have been reused in newer 1111 * versions of the architecture; in that case we define constants 1112 * for both old and new bit meanings. Code which tests against those 1113 * bits should probably check or otherwise arrange that the CPU 1114 * is the architectural version it expects. 1115 */ 1116 #define SCTLR_M (1U << 0) 1117 #define SCTLR_A (1U << 1) 1118 #define SCTLR_C (1U << 2) 1119 #define SCTLR_W (1U << 3) /* up to v6; RAO in v7 */ 1120 #define SCTLR_nTLSMD_32 (1U << 3) /* v8.2-LSMAOC, AArch32 only */ 1121 #define SCTLR_SA (1U << 3) /* AArch64 only */ 1122 #define SCTLR_P (1U << 4) /* up to v5; RAO in v6 and v7 */ 1123 #define SCTLR_LSMAOE_32 (1U << 4) /* v8.2-LSMAOC, AArch32 only */ 1124 #define SCTLR_SA0 (1U << 4) /* v8 onward, AArch64 only */ 1125 #define SCTLR_D (1U << 5) /* up to v5; RAO in v6 */ 1126 #define SCTLR_CP15BEN (1U << 5) /* v7 onward */ 1127 #define SCTLR_L (1U << 6) /* up to v5; RAO in v6 and v7; RAZ in v8 */ 1128 #define SCTLR_nAA (1U << 6) /* when v8.4-LSE is implemented */ 1129 #define SCTLR_B (1U << 7) /* up to v6; RAZ in v7 */ 1130 #define SCTLR_ITD (1U << 7) /* v8 onward */ 1131 #define SCTLR_S (1U << 8) /* up to v6; RAZ in v7 */ 1132 #define SCTLR_SED (1U << 8) /* v8 onward */ 1133 #define SCTLR_R (1U << 9) /* up to v6; RAZ in v7 */ 1134 #define SCTLR_UMA (1U << 9) /* v8 onward, AArch64 only */ 1135 #define SCTLR_F (1U << 10) /* up to v6 */ 1136 #define SCTLR_SW (1U << 10) /* v7 */ 1137 #define SCTLR_EnRCTX (1U << 10) /* in v8.0-PredInv */ 1138 #define SCTLR_Z (1U << 11) /* in v7, RES1 in v8 */ 1139 #define SCTLR_EOS (1U << 11) /* v8.5-ExS */ 1140 #define SCTLR_I (1U << 12) 1141 #define SCTLR_V (1U << 13) /* AArch32 only */ 1142 #define SCTLR_EnDB (1U << 13) /* v8.3, AArch64 only */ 1143 #define SCTLR_RR (1U << 14) /* up to v7 */ 1144 #define SCTLR_DZE (1U << 14) /* v8 onward, AArch64 only */ 1145 #define SCTLR_L4 (1U << 15) /* up to v6; RAZ in v7 */ 1146 #define SCTLR_UCT (1U << 15) /* v8 onward, AArch64 only */ 1147 #define SCTLR_DT (1U << 16) /* up to ??, RAO in v6 and v7 */ 1148 #define SCTLR_nTWI (1U << 16) /* v8 onward */ 1149 #define SCTLR_HA (1U << 17) /* up to v7, RES0 in v8 */ 1150 #define SCTLR_BR (1U << 17) /* PMSA only */ 1151 #define SCTLR_IT (1U << 18) /* up to ??, RAO in v6 and v7 */ 1152 #define SCTLR_nTWE (1U << 18) /* v8 onward */ 1153 #define SCTLR_WXN (1U << 19) 1154 #define SCTLR_ST (1U << 20) /* up to ??, RAZ in v6 */ 1155 #define SCTLR_UWXN (1U << 20) /* v7 onward, AArch32 only */ 1156 #define SCTLR_FI (1U << 21) /* up to v7, v8 RES0 */ 1157 #define SCTLR_IESB (1U << 21) /* v8.2-IESB, AArch64 only */ 1158 #define SCTLR_U (1U << 22) /* up to v6, RAO in v7 */ 1159 #define SCTLR_EIS (1U << 22) /* v8.5-ExS */ 1160 #define SCTLR_XP (1U << 23) /* up to v6; v7 onward RAO */ 1161 #define SCTLR_SPAN (1U << 23) /* v8.1-PAN */ 1162 #define SCTLR_VE (1U << 24) /* up to v7 */ 1163 #define SCTLR_E0E (1U << 24) /* v8 onward, AArch64 only */ 1164 #define SCTLR_EE (1U << 25) 1165 #define SCTLR_L2 (1U << 26) /* up to v6, RAZ in v7 */ 1166 #define SCTLR_UCI (1U << 26) /* v8 onward, AArch64 only */ 1167 #define SCTLR_NMFI (1U << 27) /* up to v7, RAZ in v7VE and v8 */ 1168 #define SCTLR_EnDA (1U << 27) /* v8.3, AArch64 only */ 1169 #define SCTLR_TRE (1U << 28) /* AArch32 only */ 1170 #define SCTLR_nTLSMD_64 (1U << 28) /* v8.2-LSMAOC, AArch64 only */ 1171 #define SCTLR_AFE (1U << 29) /* AArch32 only */ 1172 #define SCTLR_LSMAOE_64 (1U << 29) /* v8.2-LSMAOC, AArch64 only */ 1173 #define SCTLR_TE (1U << 30) /* AArch32 only */ 1174 #define SCTLR_EnIB (1U << 30) /* v8.3, AArch64 only */ 1175 #define SCTLR_EnIA (1U << 31) /* v8.3, AArch64 only */ 1176 #define SCTLR_BT0 (1ULL << 35) /* v8.5-BTI */ 1177 #define SCTLR_BT1 (1ULL << 36) /* v8.5-BTI */ 1178 #define SCTLR_ITFSB (1ULL << 37) /* v8.5-MemTag */ 1179 #define SCTLR_TCF0 (3ULL << 38) /* v8.5-MemTag */ 1180 #define SCTLR_TCF (3ULL << 40) /* v8.5-MemTag */ 1181 #define SCTLR_ATA0 (1ULL << 42) /* v8.5-MemTag */ 1182 #define SCTLR_ATA (1ULL << 43) /* v8.5-MemTag */ 1183 #define SCTLR_DSSBS (1ULL << 44) /* v8.5 */ 1184 1185 #define CPTR_TCPAC (1U << 31) 1186 #define CPTR_TTA (1U << 20) 1187 #define CPTR_TFP (1U << 10) 1188 #define CPTR_TZ (1U << 8) /* CPTR_EL2 */ 1189 #define CPTR_EZ (1U << 8) /* CPTR_EL3 */ 1190 1191 #define MDCR_EPMAD (1U << 21) 1192 #define MDCR_EDAD (1U << 20) 1193 #define MDCR_SPME (1U << 17) /* MDCR_EL3 */ 1194 #define MDCR_HPMD (1U << 17) /* MDCR_EL2 */ 1195 #define MDCR_SDD (1U << 16) 1196 #define MDCR_SPD (3U << 14) 1197 #define MDCR_TDRA (1U << 11) 1198 #define MDCR_TDOSA (1U << 10) 1199 #define MDCR_TDA (1U << 9) 1200 #define MDCR_TDE (1U << 8) 1201 #define MDCR_HPME (1U << 7) 1202 #define MDCR_TPM (1U << 6) 1203 #define MDCR_TPMCR (1U << 5) 1204 #define MDCR_HPMN (0x1fU) 1205 1206 /* Not all of the MDCR_EL3 bits are present in the 32-bit SDCR */ 1207 #define SDCR_VALID_MASK (MDCR_EPMAD | MDCR_EDAD | MDCR_SPME | MDCR_SPD) 1208 1209 #define CPSR_M (0x1fU) 1210 #define CPSR_T (1U << 5) 1211 #define CPSR_F (1U << 6) 1212 #define CPSR_I (1U << 7) 1213 #define CPSR_A (1U << 8) 1214 #define CPSR_E (1U << 9) 1215 #define CPSR_IT_2_7 (0xfc00U) 1216 #define CPSR_GE (0xfU << 16) 1217 #define CPSR_IL (1U << 20) 1218 #define CPSR_PAN (1U << 22) 1219 #define CPSR_J (1U << 24) 1220 #define CPSR_IT_0_1 (3U << 25) 1221 #define CPSR_Q (1U << 27) 1222 #define CPSR_V (1U << 28) 1223 #define CPSR_C (1U << 29) 1224 #define CPSR_Z (1U << 30) 1225 #define CPSR_N (1U << 31) 1226 #define CPSR_NZCV (CPSR_N | CPSR_Z | CPSR_C | CPSR_V) 1227 #define CPSR_AIF (CPSR_A | CPSR_I | CPSR_F) 1228 1229 #define CPSR_IT (CPSR_IT_0_1 | CPSR_IT_2_7) 1230 #define CACHED_CPSR_BITS (CPSR_T | CPSR_AIF | CPSR_GE | CPSR_IT | CPSR_Q \ 1231 | CPSR_NZCV) 1232 /* Bits writable in user mode. */ 1233 #define CPSR_USER (CPSR_NZCV | CPSR_Q | CPSR_GE) 1234 /* Execution state bits. MRS read as zero, MSR writes ignored. */ 1235 #define CPSR_EXEC (CPSR_T | CPSR_IT | CPSR_J | CPSR_IL) 1236 1237 /* Bit definitions for M profile XPSR. Most are the same as CPSR. */ 1238 #define XPSR_EXCP 0x1ffU 1239 #define XPSR_SPREALIGN (1U << 9) /* Only set in exception stack frames */ 1240 #define XPSR_IT_2_7 CPSR_IT_2_7 1241 #define XPSR_GE CPSR_GE 1242 #define XPSR_SFPA (1U << 20) /* Only set in exception stack frames */ 1243 #define XPSR_T (1U << 24) /* Not the same as CPSR_T ! */ 1244 #define XPSR_IT_0_1 CPSR_IT_0_1 1245 #define XPSR_Q CPSR_Q 1246 #define XPSR_V CPSR_V 1247 #define XPSR_C CPSR_C 1248 #define XPSR_Z CPSR_Z 1249 #define XPSR_N CPSR_N 1250 #define XPSR_NZCV CPSR_NZCV 1251 #define XPSR_IT CPSR_IT 1252 1253 #define TTBCR_N (7U << 0) /* TTBCR.EAE==0 */ 1254 #define TTBCR_T0SZ (7U << 0) /* TTBCR.EAE==1 */ 1255 #define TTBCR_PD0 (1U << 4) 1256 #define TTBCR_PD1 (1U << 5) 1257 #define TTBCR_EPD0 (1U << 7) 1258 #define TTBCR_IRGN0 (3U << 8) 1259 #define TTBCR_ORGN0 (3U << 10) 1260 #define TTBCR_SH0 (3U << 12) 1261 #define TTBCR_T1SZ (3U << 16) 1262 #define TTBCR_A1 (1U << 22) 1263 #define TTBCR_EPD1 (1U << 23) 1264 #define TTBCR_IRGN1 (3U << 24) 1265 #define TTBCR_ORGN1 (3U << 26) 1266 #define TTBCR_SH1 (1U << 28) 1267 #define TTBCR_EAE (1U << 31) 1268 1269 /* Bit definitions for ARMv8 SPSR (PSTATE) format. 1270 * Only these are valid when in AArch64 mode; in 1271 * AArch32 mode SPSRs are basically CPSR-format. 1272 */ 1273 #define PSTATE_SP (1U) 1274 #define PSTATE_M (0xFU) 1275 #define PSTATE_nRW (1U << 4) 1276 #define PSTATE_F (1U << 6) 1277 #define PSTATE_I (1U << 7) 1278 #define PSTATE_A (1U << 8) 1279 #define PSTATE_D (1U << 9) 1280 #define PSTATE_BTYPE (3U << 10) 1281 #define PSTATE_IL (1U << 20) 1282 #define PSTATE_SS (1U << 21) 1283 #define PSTATE_PAN (1U << 22) 1284 #define PSTATE_UAO (1U << 23) 1285 #define PSTATE_V (1U << 28) 1286 #define PSTATE_C (1U << 29) 1287 #define PSTATE_Z (1U << 30) 1288 #define PSTATE_N (1U << 31) 1289 #define PSTATE_NZCV (PSTATE_N | PSTATE_Z | PSTATE_C | PSTATE_V) 1290 #define PSTATE_DAIF (PSTATE_D | PSTATE_A | PSTATE_I | PSTATE_F) 1291 #define CACHED_PSTATE_BITS (PSTATE_NZCV | PSTATE_DAIF | PSTATE_BTYPE) 1292 /* Mode values for AArch64 */ 1293 #define PSTATE_MODE_EL3h 13 1294 #define PSTATE_MODE_EL3t 12 1295 #define PSTATE_MODE_EL2h 9 1296 #define PSTATE_MODE_EL2t 8 1297 #define PSTATE_MODE_EL1h 5 1298 #define PSTATE_MODE_EL1t 4 1299 #define PSTATE_MODE_EL0t 0 1300 1301 /* Write a new value to v7m.exception, thus transitioning into or out 1302 * of Handler mode; this may result in a change of active stack pointer. 1303 */ 1304 void write_v7m_exception(CPUARMState *env, uint32_t new_exc); 1305 1306 /* Map EL and handler into a PSTATE_MODE. */ 1307 static inline unsigned int aarch64_pstate_mode(unsigned int el, bool handler) 1308 { 1309 return (el << 2) | handler; 1310 } 1311 1312 /* Return the current PSTATE value. For the moment we don't support 32<->64 bit 1313 * interprocessing, so we don't attempt to sync with the cpsr state used by 1314 * the 32 bit decoder. 1315 */ 1316 static inline uint32_t pstate_read(CPUARMState *env) 1317 { 1318 int ZF; 1319 1320 ZF = (env->ZF == 0); 1321 return (env->NF & 0x80000000) | (ZF << 30) 1322 | (env->CF << 29) | ((env->VF & 0x80000000) >> 3) 1323 | env->pstate | env->daif | (env->btype << 10); 1324 } 1325 1326 static inline void pstate_write(CPUARMState *env, uint32_t val) 1327 { 1328 env->ZF = (~val) & PSTATE_Z; 1329 env->NF = val; 1330 env->CF = (val >> 29) & 1; 1331 env->VF = (val << 3) & 0x80000000; 1332 env->daif = val & PSTATE_DAIF; 1333 env->btype = (val >> 10) & 3; 1334 env->pstate = val & ~CACHED_PSTATE_BITS; 1335 } 1336 1337 /* Return the current CPSR value. */ 1338 uint32_t cpsr_read(CPUARMState *env); 1339 1340 typedef enum CPSRWriteType { 1341 CPSRWriteByInstr = 0, /* from guest MSR or CPS */ 1342 CPSRWriteExceptionReturn = 1, /* from guest exception return insn */ 1343 CPSRWriteRaw = 2, /* trust values, do not switch reg banks */ 1344 CPSRWriteByGDBStub = 3, /* from the GDB stub */ 1345 } CPSRWriteType; 1346 1347 /* Set the CPSR. Note that some bits of mask must be all-set or all-clear.*/ 1348 void cpsr_write(CPUARMState *env, uint32_t val, uint32_t mask, 1349 CPSRWriteType write_type); 1350 1351 /* Return the current xPSR value. */ 1352 static inline uint32_t xpsr_read(CPUARMState *env) 1353 { 1354 int ZF; 1355 ZF = (env->ZF == 0); 1356 return (env->NF & 0x80000000) | (ZF << 30) 1357 | (env->CF << 29) | ((env->VF & 0x80000000) >> 3) | (env->QF << 27) 1358 | (env->thumb << 24) | ((env->condexec_bits & 3) << 25) 1359 | ((env->condexec_bits & 0xfc) << 8) 1360 | (env->GE << 16) 1361 | env->v7m.exception; 1362 } 1363 1364 /* Set the xPSR. Note that some bits of mask must be all-set or all-clear. */ 1365 static inline void xpsr_write(CPUARMState *env, uint32_t val, uint32_t mask) 1366 { 1367 if (mask & XPSR_NZCV) { 1368 env->ZF = (~val) & XPSR_Z; 1369 env->NF = val; 1370 env->CF = (val >> 29) & 1; 1371 env->VF = (val << 3) & 0x80000000; 1372 } 1373 if (mask & XPSR_Q) { 1374 env->QF = ((val & XPSR_Q) != 0); 1375 } 1376 if (mask & XPSR_GE) { 1377 env->GE = (val & XPSR_GE) >> 16; 1378 } 1379 #ifndef CONFIG_USER_ONLY 1380 if (mask & XPSR_T) { 1381 env->thumb = ((val & XPSR_T) != 0); 1382 } 1383 if (mask & XPSR_IT_0_1) { 1384 env->condexec_bits &= ~3; 1385 env->condexec_bits |= (val >> 25) & 3; 1386 } 1387 if (mask & XPSR_IT_2_7) { 1388 env->condexec_bits &= 3; 1389 env->condexec_bits |= (val >> 8) & 0xfc; 1390 } 1391 if (mask & XPSR_EXCP) { 1392 /* Note that this only happens on exception exit */ 1393 write_v7m_exception(env, val & XPSR_EXCP); 1394 } 1395 #endif 1396 } 1397 1398 #define HCR_VM (1ULL << 0) 1399 #define HCR_SWIO (1ULL << 1) 1400 #define HCR_PTW (1ULL << 2) 1401 #define HCR_FMO (1ULL << 3) 1402 #define HCR_IMO (1ULL << 4) 1403 #define HCR_AMO (1ULL << 5) 1404 #define HCR_VF (1ULL << 6) 1405 #define HCR_VI (1ULL << 7) 1406 #define HCR_VSE (1ULL << 8) 1407 #define HCR_FB (1ULL << 9) 1408 #define HCR_BSU_MASK (3ULL << 10) 1409 #define HCR_DC (1ULL << 12) 1410 #define HCR_TWI (1ULL << 13) 1411 #define HCR_TWE (1ULL << 14) 1412 #define HCR_TID0 (1ULL << 15) 1413 #define HCR_TID1 (1ULL << 16) 1414 #define HCR_TID2 (1ULL << 17) 1415 #define HCR_TID3 (1ULL << 18) 1416 #define HCR_TSC (1ULL << 19) 1417 #define HCR_TIDCP (1ULL << 20) 1418 #define HCR_TACR (1ULL << 21) 1419 #define HCR_TSW (1ULL << 22) 1420 #define HCR_TPCP (1ULL << 23) 1421 #define HCR_TPU (1ULL << 24) 1422 #define HCR_TTLB (1ULL << 25) 1423 #define HCR_TVM (1ULL << 26) 1424 #define HCR_TGE (1ULL << 27) 1425 #define HCR_TDZ (1ULL << 28) 1426 #define HCR_HCD (1ULL << 29) 1427 #define HCR_TRVM (1ULL << 30) 1428 #define HCR_RW (1ULL << 31) 1429 #define HCR_CD (1ULL << 32) 1430 #define HCR_ID (1ULL << 33) 1431 #define HCR_E2H (1ULL << 34) 1432 #define HCR_TLOR (1ULL << 35) 1433 #define HCR_TERR (1ULL << 36) 1434 #define HCR_TEA (1ULL << 37) 1435 #define HCR_MIOCNCE (1ULL << 38) 1436 /* RES0 bit 39 */ 1437 #define HCR_APK (1ULL << 40) 1438 #define HCR_API (1ULL << 41) 1439 #define HCR_NV (1ULL << 42) 1440 #define HCR_NV1 (1ULL << 43) 1441 #define HCR_AT (1ULL << 44) 1442 #define HCR_NV2 (1ULL << 45) 1443 #define HCR_FWB (1ULL << 46) 1444 #define HCR_FIEN (1ULL << 47) 1445 /* RES0 bit 48 */ 1446 #define HCR_TID4 (1ULL << 49) 1447 #define HCR_TICAB (1ULL << 50) 1448 #define HCR_AMVOFFEN (1ULL << 51) 1449 #define HCR_TOCU (1ULL << 52) 1450 #define HCR_ENSCXT (1ULL << 53) 1451 #define HCR_TTLBIS (1ULL << 54) 1452 #define HCR_TTLBOS (1ULL << 55) 1453 #define HCR_ATA (1ULL << 56) 1454 #define HCR_DCT (1ULL << 57) 1455 #define HCR_TID5 (1ULL << 58) 1456 #define HCR_TWEDEN (1ULL << 59) 1457 #define HCR_TWEDEL MAKE_64BIT_MASK(60, 4) 1458 1459 #define SCR_NS (1U << 0) 1460 #define SCR_IRQ (1U << 1) 1461 #define SCR_FIQ (1U << 2) 1462 #define SCR_EA (1U << 3) 1463 #define SCR_FW (1U << 4) 1464 #define SCR_AW (1U << 5) 1465 #define SCR_NET (1U << 6) 1466 #define SCR_SMD (1U << 7) 1467 #define SCR_HCE (1U << 8) 1468 #define SCR_SIF (1U << 9) 1469 #define SCR_RW (1U << 10) 1470 #define SCR_ST (1U << 11) 1471 #define SCR_TWI (1U << 12) 1472 #define SCR_TWE (1U << 13) 1473 #define SCR_TLOR (1U << 14) 1474 #define SCR_TERR (1U << 15) 1475 #define SCR_APK (1U << 16) 1476 #define SCR_API (1U << 17) 1477 #define SCR_EEL2 (1U << 18) 1478 #define SCR_EASE (1U << 19) 1479 #define SCR_NMEA (1U << 20) 1480 #define SCR_FIEN (1U << 21) 1481 #define SCR_ENSCXT (1U << 25) 1482 #define SCR_ATA (1U << 26) 1483 1484 /* Return the current FPSCR value. */ 1485 uint32_t vfp_get_fpscr(CPUARMState *env); 1486 void vfp_set_fpscr(CPUARMState *env, uint32_t val); 1487 1488 /* FPCR, Floating Point Control Register 1489 * FPSR, Floating Poiht Status Register 1490 * 1491 * For A64 the FPSCR is split into two logically distinct registers, 1492 * FPCR and FPSR. However since they still use non-overlapping bits 1493 * we store the underlying state in fpscr and just mask on read/write. 1494 */ 1495 #define FPSR_MASK 0xf800009f 1496 #define FPCR_MASK 0x07ff9f00 1497 1498 #define FPCR_IOE (1 << 8) /* Invalid Operation exception trap enable */ 1499 #define FPCR_DZE (1 << 9) /* Divide by Zero exception trap enable */ 1500 #define FPCR_OFE (1 << 10) /* Overflow exception trap enable */ 1501 #define FPCR_UFE (1 << 11) /* Underflow exception trap enable */ 1502 #define FPCR_IXE (1 << 12) /* Inexact exception trap enable */ 1503 #define FPCR_IDE (1 << 15) /* Input Denormal exception trap enable */ 1504 #define FPCR_FZ16 (1 << 19) /* ARMv8.2+, FP16 flush-to-zero */ 1505 #define FPCR_FZ (1 << 24) /* Flush-to-zero enable bit */ 1506 #define FPCR_DN (1 << 25) /* Default NaN enable bit */ 1507 #define FPCR_QC (1 << 27) /* Cumulative saturation bit */ 1508 1509 static inline uint32_t vfp_get_fpsr(CPUARMState *env) 1510 { 1511 return vfp_get_fpscr(env) & FPSR_MASK; 1512 } 1513 1514 static inline void vfp_set_fpsr(CPUARMState *env, uint32_t val) 1515 { 1516 uint32_t new_fpscr = (vfp_get_fpscr(env) & ~FPSR_MASK) | (val & FPSR_MASK); 1517 vfp_set_fpscr(env, new_fpscr); 1518 } 1519 1520 static inline uint32_t vfp_get_fpcr(CPUARMState *env) 1521 { 1522 return vfp_get_fpscr(env) & FPCR_MASK; 1523 } 1524 1525 static inline void vfp_set_fpcr(CPUARMState *env, uint32_t val) 1526 { 1527 uint32_t new_fpscr = (vfp_get_fpscr(env) & ~FPCR_MASK) | (val & FPCR_MASK); 1528 vfp_set_fpscr(env, new_fpscr); 1529 } 1530 1531 enum arm_cpu_mode { 1532 ARM_CPU_MODE_USR = 0x10, 1533 ARM_CPU_MODE_FIQ = 0x11, 1534 ARM_CPU_MODE_IRQ = 0x12, 1535 ARM_CPU_MODE_SVC = 0x13, 1536 ARM_CPU_MODE_MON = 0x16, 1537 ARM_CPU_MODE_ABT = 0x17, 1538 ARM_CPU_MODE_HYP = 0x1a, 1539 ARM_CPU_MODE_UND = 0x1b, 1540 ARM_CPU_MODE_SYS = 0x1f 1541 }; 1542 1543 /* VFP system registers. */ 1544 #define ARM_VFP_FPSID 0 1545 #define ARM_VFP_FPSCR 1 1546 #define ARM_VFP_MVFR2 5 1547 #define ARM_VFP_MVFR1 6 1548 #define ARM_VFP_MVFR0 7 1549 #define ARM_VFP_FPEXC 8 1550 #define ARM_VFP_FPINST 9 1551 #define ARM_VFP_FPINST2 10 1552 1553 /* iwMMXt coprocessor control registers. */ 1554 #define ARM_IWMMXT_wCID 0 1555 #define ARM_IWMMXT_wCon 1 1556 #define ARM_IWMMXT_wCSSF 2 1557 #define ARM_IWMMXT_wCASF 3 1558 #define ARM_IWMMXT_wCGR0 8 1559 #define ARM_IWMMXT_wCGR1 9 1560 #define ARM_IWMMXT_wCGR2 10 1561 #define ARM_IWMMXT_wCGR3 11 1562 1563 /* V7M CCR bits */ 1564 FIELD(V7M_CCR, NONBASETHRDENA, 0, 1) 1565 FIELD(V7M_CCR, USERSETMPEND, 1, 1) 1566 FIELD(V7M_CCR, UNALIGN_TRP, 3, 1) 1567 FIELD(V7M_CCR, DIV_0_TRP, 4, 1) 1568 FIELD(V7M_CCR, BFHFNMIGN, 8, 1) 1569 FIELD(V7M_CCR, STKALIGN, 9, 1) 1570 FIELD(V7M_CCR, STKOFHFNMIGN, 10, 1) 1571 FIELD(V7M_CCR, DC, 16, 1) 1572 FIELD(V7M_CCR, IC, 17, 1) 1573 FIELD(V7M_CCR, BP, 18, 1) 1574 1575 /* V7M SCR bits */ 1576 FIELD(V7M_SCR, SLEEPONEXIT, 1, 1) 1577 FIELD(V7M_SCR, SLEEPDEEP, 2, 1) 1578 FIELD(V7M_SCR, SLEEPDEEPS, 3, 1) 1579 FIELD(V7M_SCR, SEVONPEND, 4, 1) 1580 1581 /* V7M AIRCR bits */ 1582 FIELD(V7M_AIRCR, VECTRESET, 0, 1) 1583 FIELD(V7M_AIRCR, VECTCLRACTIVE, 1, 1) 1584 FIELD(V7M_AIRCR, SYSRESETREQ, 2, 1) 1585 FIELD(V7M_AIRCR, SYSRESETREQS, 3, 1) 1586 FIELD(V7M_AIRCR, PRIGROUP, 8, 3) 1587 FIELD(V7M_AIRCR, BFHFNMINS, 13, 1) 1588 FIELD(V7M_AIRCR, PRIS, 14, 1) 1589 FIELD(V7M_AIRCR, ENDIANNESS, 15, 1) 1590 FIELD(V7M_AIRCR, VECTKEY, 16, 16) 1591 1592 /* V7M CFSR bits for MMFSR */ 1593 FIELD(V7M_CFSR, IACCVIOL, 0, 1) 1594 FIELD(V7M_CFSR, DACCVIOL, 1, 1) 1595 FIELD(V7M_CFSR, MUNSTKERR, 3, 1) 1596 FIELD(V7M_CFSR, MSTKERR, 4, 1) 1597 FIELD(V7M_CFSR, MLSPERR, 5, 1) 1598 FIELD(V7M_CFSR, MMARVALID, 7, 1) 1599 1600 /* V7M CFSR bits for BFSR */ 1601 FIELD(V7M_CFSR, IBUSERR, 8 + 0, 1) 1602 FIELD(V7M_CFSR, PRECISERR, 8 + 1, 1) 1603 FIELD(V7M_CFSR, IMPRECISERR, 8 + 2, 1) 1604 FIELD(V7M_CFSR, UNSTKERR, 8 + 3, 1) 1605 FIELD(V7M_CFSR, STKERR, 8 + 4, 1) 1606 FIELD(V7M_CFSR, LSPERR, 8 + 5, 1) 1607 FIELD(V7M_CFSR, BFARVALID, 8 + 7, 1) 1608 1609 /* V7M CFSR bits for UFSR */ 1610 FIELD(V7M_CFSR, UNDEFINSTR, 16 + 0, 1) 1611 FIELD(V7M_CFSR, INVSTATE, 16 + 1, 1) 1612 FIELD(V7M_CFSR, INVPC, 16 + 2, 1) 1613 FIELD(V7M_CFSR, NOCP, 16 + 3, 1) 1614 FIELD(V7M_CFSR, STKOF, 16 + 4, 1) 1615 FIELD(V7M_CFSR, UNALIGNED, 16 + 8, 1) 1616 FIELD(V7M_CFSR, DIVBYZERO, 16 + 9, 1) 1617 1618 /* V7M CFSR bit masks covering all of the subregister bits */ 1619 FIELD(V7M_CFSR, MMFSR, 0, 8) 1620 FIELD(V7M_CFSR, BFSR, 8, 8) 1621 FIELD(V7M_CFSR, UFSR, 16, 16) 1622 1623 /* V7M HFSR bits */ 1624 FIELD(V7M_HFSR, VECTTBL, 1, 1) 1625 FIELD(V7M_HFSR, FORCED, 30, 1) 1626 FIELD(V7M_HFSR, DEBUGEVT, 31, 1) 1627 1628 /* V7M DFSR bits */ 1629 FIELD(V7M_DFSR, HALTED, 0, 1) 1630 FIELD(V7M_DFSR, BKPT, 1, 1) 1631 FIELD(V7M_DFSR, DWTTRAP, 2, 1) 1632 FIELD(V7M_DFSR, VCATCH, 3, 1) 1633 FIELD(V7M_DFSR, EXTERNAL, 4, 1) 1634 1635 /* V7M SFSR bits */ 1636 FIELD(V7M_SFSR, INVEP, 0, 1) 1637 FIELD(V7M_SFSR, INVIS, 1, 1) 1638 FIELD(V7M_SFSR, INVER, 2, 1) 1639 FIELD(V7M_SFSR, AUVIOL, 3, 1) 1640 FIELD(V7M_SFSR, INVTRAN, 4, 1) 1641 FIELD(V7M_SFSR, LSPERR, 5, 1) 1642 FIELD(V7M_SFSR, SFARVALID, 6, 1) 1643 FIELD(V7M_SFSR, LSERR, 7, 1) 1644 1645 /* v7M MPU_CTRL bits */ 1646 FIELD(V7M_MPU_CTRL, ENABLE, 0, 1) 1647 FIELD(V7M_MPU_CTRL, HFNMIENA, 1, 1) 1648 FIELD(V7M_MPU_CTRL, PRIVDEFENA, 2, 1) 1649 1650 /* v7M CLIDR bits */ 1651 FIELD(V7M_CLIDR, CTYPE_ALL, 0, 21) 1652 FIELD(V7M_CLIDR, LOUIS, 21, 3) 1653 FIELD(V7M_CLIDR, LOC, 24, 3) 1654 FIELD(V7M_CLIDR, LOUU, 27, 3) 1655 FIELD(V7M_CLIDR, ICB, 30, 2) 1656 1657 FIELD(V7M_CSSELR, IND, 0, 1) 1658 FIELD(V7M_CSSELR, LEVEL, 1, 3) 1659 /* We use the combination of InD and Level to index into cpu->ccsidr[]; 1660 * define a mask for this and check that it doesn't permit running off 1661 * the end of the array. 1662 */ 1663 FIELD(V7M_CSSELR, INDEX, 0, 4) 1664 1665 /* v7M FPCCR bits */ 1666 FIELD(V7M_FPCCR, LSPACT, 0, 1) 1667 FIELD(V7M_FPCCR, USER, 1, 1) 1668 FIELD(V7M_FPCCR, S, 2, 1) 1669 FIELD(V7M_FPCCR, THREAD, 3, 1) 1670 FIELD(V7M_FPCCR, HFRDY, 4, 1) 1671 FIELD(V7M_FPCCR, MMRDY, 5, 1) 1672 FIELD(V7M_FPCCR, BFRDY, 6, 1) 1673 FIELD(V7M_FPCCR, SFRDY, 7, 1) 1674 FIELD(V7M_FPCCR, MONRDY, 8, 1) 1675 FIELD(V7M_FPCCR, SPLIMVIOL, 9, 1) 1676 FIELD(V7M_FPCCR, UFRDY, 10, 1) 1677 FIELD(V7M_FPCCR, RES0, 11, 15) 1678 FIELD(V7M_FPCCR, TS, 26, 1) 1679 FIELD(V7M_FPCCR, CLRONRETS, 27, 1) 1680 FIELD(V7M_FPCCR, CLRONRET, 28, 1) 1681 FIELD(V7M_FPCCR, LSPENS, 29, 1) 1682 FIELD(V7M_FPCCR, LSPEN, 30, 1) 1683 FIELD(V7M_FPCCR, ASPEN, 31, 1) 1684 /* These bits are banked. Others are non-banked and live in the M_REG_S bank */ 1685 #define R_V7M_FPCCR_BANKED_MASK \ 1686 (R_V7M_FPCCR_LSPACT_MASK | \ 1687 R_V7M_FPCCR_USER_MASK | \ 1688 R_V7M_FPCCR_THREAD_MASK | \ 1689 R_V7M_FPCCR_MMRDY_MASK | \ 1690 R_V7M_FPCCR_SPLIMVIOL_MASK | \ 1691 R_V7M_FPCCR_UFRDY_MASK | \ 1692 R_V7M_FPCCR_ASPEN_MASK) 1693 1694 /* 1695 * System register ID fields. 1696 */ 1697 FIELD(MIDR_EL1, REVISION, 0, 4) 1698 FIELD(MIDR_EL1, PARTNUM, 4, 12) 1699 FIELD(MIDR_EL1, ARCHITECTURE, 16, 4) 1700 FIELD(MIDR_EL1, VARIANT, 20, 4) 1701 FIELD(MIDR_EL1, IMPLEMENTER, 24, 8) 1702 1703 FIELD(ID_ISAR0, SWAP, 0, 4) 1704 FIELD(ID_ISAR0, BITCOUNT, 4, 4) 1705 FIELD(ID_ISAR0, BITFIELD, 8, 4) 1706 FIELD(ID_ISAR0, CMPBRANCH, 12, 4) 1707 FIELD(ID_ISAR0, COPROC, 16, 4) 1708 FIELD(ID_ISAR0, DEBUG, 20, 4) 1709 FIELD(ID_ISAR0, DIVIDE, 24, 4) 1710 1711 FIELD(ID_ISAR1, ENDIAN, 0, 4) 1712 FIELD(ID_ISAR1, EXCEPT, 4, 4) 1713 FIELD(ID_ISAR1, EXCEPT_AR, 8, 4) 1714 FIELD(ID_ISAR1, EXTEND, 12, 4) 1715 FIELD(ID_ISAR1, IFTHEN, 16, 4) 1716 FIELD(ID_ISAR1, IMMEDIATE, 20, 4) 1717 FIELD(ID_ISAR1, INTERWORK, 24, 4) 1718 FIELD(ID_ISAR1, JAZELLE, 28, 4) 1719 1720 FIELD(ID_ISAR2, LOADSTORE, 0, 4) 1721 FIELD(ID_ISAR2, MEMHINT, 4, 4) 1722 FIELD(ID_ISAR2, MULTIACCESSINT, 8, 4) 1723 FIELD(ID_ISAR2, MULT, 12, 4) 1724 FIELD(ID_ISAR2, MULTS, 16, 4) 1725 FIELD(ID_ISAR2, MULTU, 20, 4) 1726 FIELD(ID_ISAR2, PSR_AR, 24, 4) 1727 FIELD(ID_ISAR2, REVERSAL, 28, 4) 1728 1729 FIELD(ID_ISAR3, SATURATE, 0, 4) 1730 FIELD(ID_ISAR3, SIMD, 4, 4) 1731 FIELD(ID_ISAR3, SVC, 8, 4) 1732 FIELD(ID_ISAR3, SYNCHPRIM, 12, 4) 1733 FIELD(ID_ISAR3, TABBRANCH, 16, 4) 1734 FIELD(ID_ISAR3, T32COPY, 20, 4) 1735 FIELD(ID_ISAR3, TRUENOP, 24, 4) 1736 FIELD(ID_ISAR3, T32EE, 28, 4) 1737 1738 FIELD(ID_ISAR4, UNPRIV, 0, 4) 1739 FIELD(ID_ISAR4, WITHSHIFTS, 4, 4) 1740 FIELD(ID_ISAR4, WRITEBACK, 8, 4) 1741 FIELD(ID_ISAR4, SMC, 12, 4) 1742 FIELD(ID_ISAR4, BARRIER, 16, 4) 1743 FIELD(ID_ISAR4, SYNCHPRIM_FRAC, 20, 4) 1744 FIELD(ID_ISAR4, PSR_M, 24, 4) 1745 FIELD(ID_ISAR4, SWP_FRAC, 28, 4) 1746 1747 FIELD(ID_ISAR5, SEVL, 0, 4) 1748 FIELD(ID_ISAR5, AES, 4, 4) 1749 FIELD(ID_ISAR5, SHA1, 8, 4) 1750 FIELD(ID_ISAR5, SHA2, 12, 4) 1751 FIELD(ID_ISAR5, CRC32, 16, 4) 1752 FIELD(ID_ISAR5, RDM, 24, 4) 1753 FIELD(ID_ISAR5, VCMA, 28, 4) 1754 1755 FIELD(ID_ISAR6, JSCVT, 0, 4) 1756 FIELD(ID_ISAR6, DP, 4, 4) 1757 FIELD(ID_ISAR6, FHM, 8, 4) 1758 FIELD(ID_ISAR6, SB, 12, 4) 1759 FIELD(ID_ISAR6, SPECRES, 16, 4) 1760 1761 FIELD(ID_MMFR3, CMAINTVA, 0, 4) 1762 FIELD(ID_MMFR3, CMAINTSW, 4, 4) 1763 FIELD(ID_MMFR3, BPMAINT, 8, 4) 1764 FIELD(ID_MMFR3, MAINTBCST, 12, 4) 1765 FIELD(ID_MMFR3, PAN, 16, 4) 1766 FIELD(ID_MMFR3, COHWALK, 20, 4) 1767 FIELD(ID_MMFR3, CMEMSZ, 24, 4) 1768 FIELD(ID_MMFR3, SUPERSEC, 28, 4) 1769 1770 FIELD(ID_MMFR4, SPECSEI, 0, 4) 1771 FIELD(ID_MMFR4, AC2, 4, 4) 1772 FIELD(ID_MMFR4, XNX, 8, 4) 1773 FIELD(ID_MMFR4, CNP, 12, 4) 1774 FIELD(ID_MMFR4, HPDS, 16, 4) 1775 FIELD(ID_MMFR4, LSM, 20, 4) 1776 FIELD(ID_MMFR4, CCIDX, 24, 4) 1777 FIELD(ID_MMFR4, EVT, 28, 4) 1778 1779 FIELD(ID_AA64ISAR0, AES, 4, 4) 1780 FIELD(ID_AA64ISAR0, SHA1, 8, 4) 1781 FIELD(ID_AA64ISAR0, SHA2, 12, 4) 1782 FIELD(ID_AA64ISAR0, CRC32, 16, 4) 1783 FIELD(ID_AA64ISAR0, ATOMIC, 20, 4) 1784 FIELD(ID_AA64ISAR0, RDM, 28, 4) 1785 FIELD(ID_AA64ISAR0, SHA3, 32, 4) 1786 FIELD(ID_AA64ISAR0, SM3, 36, 4) 1787 FIELD(ID_AA64ISAR0, SM4, 40, 4) 1788 FIELD(ID_AA64ISAR0, DP, 44, 4) 1789 FIELD(ID_AA64ISAR0, FHM, 48, 4) 1790 FIELD(ID_AA64ISAR0, TS, 52, 4) 1791 FIELD(ID_AA64ISAR0, TLB, 56, 4) 1792 FIELD(ID_AA64ISAR0, RNDR, 60, 4) 1793 1794 FIELD(ID_AA64ISAR1, DPB, 0, 4) 1795 FIELD(ID_AA64ISAR1, APA, 4, 4) 1796 FIELD(ID_AA64ISAR1, API, 8, 4) 1797 FIELD(ID_AA64ISAR1, JSCVT, 12, 4) 1798 FIELD(ID_AA64ISAR1, FCMA, 16, 4) 1799 FIELD(ID_AA64ISAR1, LRCPC, 20, 4) 1800 FIELD(ID_AA64ISAR1, GPA, 24, 4) 1801 FIELD(ID_AA64ISAR1, GPI, 28, 4) 1802 FIELD(ID_AA64ISAR1, FRINTTS, 32, 4) 1803 FIELD(ID_AA64ISAR1, SB, 36, 4) 1804 FIELD(ID_AA64ISAR1, SPECRES, 40, 4) 1805 1806 FIELD(ID_AA64PFR0, EL0, 0, 4) 1807 FIELD(ID_AA64PFR0, EL1, 4, 4) 1808 FIELD(ID_AA64PFR0, EL2, 8, 4) 1809 FIELD(ID_AA64PFR0, EL3, 12, 4) 1810 FIELD(ID_AA64PFR0, FP, 16, 4) 1811 FIELD(ID_AA64PFR0, ADVSIMD, 20, 4) 1812 FIELD(ID_AA64PFR0, GIC, 24, 4) 1813 FIELD(ID_AA64PFR0, RAS, 28, 4) 1814 FIELD(ID_AA64PFR0, SVE, 32, 4) 1815 1816 FIELD(ID_AA64PFR1, BT, 0, 4) 1817 FIELD(ID_AA64PFR1, SBSS, 4, 4) 1818 FIELD(ID_AA64PFR1, MTE, 8, 4) 1819 FIELD(ID_AA64PFR1, RAS_FRAC, 12, 4) 1820 1821 FIELD(ID_AA64MMFR0, PARANGE, 0, 4) 1822 FIELD(ID_AA64MMFR0, ASIDBITS, 4, 4) 1823 FIELD(ID_AA64MMFR0, BIGEND, 8, 4) 1824 FIELD(ID_AA64MMFR0, SNSMEM, 12, 4) 1825 FIELD(ID_AA64MMFR0, BIGENDEL0, 16, 4) 1826 FIELD(ID_AA64MMFR0, TGRAN16, 20, 4) 1827 FIELD(ID_AA64MMFR0, TGRAN64, 24, 4) 1828 FIELD(ID_AA64MMFR0, TGRAN4, 28, 4) 1829 FIELD(ID_AA64MMFR0, TGRAN16_2, 32, 4) 1830 FIELD(ID_AA64MMFR0, TGRAN64_2, 36, 4) 1831 FIELD(ID_AA64MMFR0, TGRAN4_2, 40, 4) 1832 FIELD(ID_AA64MMFR0, EXS, 44, 4) 1833 1834 FIELD(ID_AA64MMFR1, HAFDBS, 0, 4) 1835 FIELD(ID_AA64MMFR1, VMIDBITS, 4, 4) 1836 FIELD(ID_AA64MMFR1, VH, 8, 4) 1837 FIELD(ID_AA64MMFR1, HPDS, 12, 4) 1838 FIELD(ID_AA64MMFR1, LO, 16, 4) 1839 FIELD(ID_AA64MMFR1, PAN, 20, 4) 1840 FIELD(ID_AA64MMFR1, SPECSEI, 24, 4) 1841 FIELD(ID_AA64MMFR1, XNX, 28, 4) 1842 1843 FIELD(ID_AA64MMFR2, CNP, 0, 4) 1844 FIELD(ID_AA64MMFR2, UAO, 4, 4) 1845 FIELD(ID_AA64MMFR2, LSM, 8, 4) 1846 FIELD(ID_AA64MMFR2, IESB, 12, 4) 1847 FIELD(ID_AA64MMFR2, VARANGE, 16, 4) 1848 FIELD(ID_AA64MMFR2, CCIDX, 20, 4) 1849 FIELD(ID_AA64MMFR2, NV, 24, 4) 1850 FIELD(ID_AA64MMFR2, ST, 28, 4) 1851 FIELD(ID_AA64MMFR2, AT, 32, 4) 1852 FIELD(ID_AA64MMFR2, IDS, 36, 4) 1853 FIELD(ID_AA64MMFR2, FWB, 40, 4) 1854 FIELD(ID_AA64MMFR2, TTL, 48, 4) 1855 FIELD(ID_AA64MMFR2, BBM, 52, 4) 1856 FIELD(ID_AA64MMFR2, EVT, 56, 4) 1857 FIELD(ID_AA64MMFR2, E0PD, 60, 4) 1858 1859 FIELD(ID_AA64DFR0, DEBUGVER, 0, 4) 1860 FIELD(ID_AA64DFR0, TRACEVER, 4, 4) 1861 FIELD(ID_AA64DFR0, PMUVER, 8, 4) 1862 FIELD(ID_AA64DFR0, BRPS, 12, 4) 1863 FIELD(ID_AA64DFR0, WRPS, 20, 4) 1864 FIELD(ID_AA64DFR0, CTX_CMPS, 28, 4) 1865 FIELD(ID_AA64DFR0, PMSVER, 32, 4) 1866 FIELD(ID_AA64DFR0, DOUBLELOCK, 36, 4) 1867 FIELD(ID_AA64DFR0, TRACEFILT, 40, 4) 1868 1869 FIELD(ID_DFR0, COPDBG, 0, 4) 1870 FIELD(ID_DFR0, COPSDBG, 4, 4) 1871 FIELD(ID_DFR0, MMAPDBG, 8, 4) 1872 FIELD(ID_DFR0, COPTRC, 12, 4) 1873 FIELD(ID_DFR0, MMAPTRC, 16, 4) 1874 FIELD(ID_DFR0, MPROFDBG, 20, 4) 1875 FIELD(ID_DFR0, PERFMON, 24, 4) 1876 FIELD(ID_DFR0, TRACEFILT, 28, 4) 1877 1878 FIELD(DBGDIDR, SE_IMP, 12, 1) 1879 FIELD(DBGDIDR, NSUHD_IMP, 14, 1) 1880 FIELD(DBGDIDR, VERSION, 16, 4) 1881 FIELD(DBGDIDR, CTX_CMPS, 20, 4) 1882 FIELD(DBGDIDR, BRPS, 24, 4) 1883 FIELD(DBGDIDR, WRPS, 28, 4) 1884 1885 FIELD(MVFR0, SIMDREG, 0, 4) 1886 FIELD(MVFR0, FPSP, 4, 4) 1887 FIELD(MVFR0, FPDP, 8, 4) 1888 FIELD(MVFR0, FPTRAP, 12, 4) 1889 FIELD(MVFR0, FPDIVIDE, 16, 4) 1890 FIELD(MVFR0, FPSQRT, 20, 4) 1891 FIELD(MVFR0, FPSHVEC, 24, 4) 1892 FIELD(MVFR0, FPROUND, 28, 4) 1893 1894 FIELD(MVFR1, FPFTZ, 0, 4) 1895 FIELD(MVFR1, FPDNAN, 4, 4) 1896 FIELD(MVFR1, SIMDLS, 8, 4) 1897 FIELD(MVFR1, SIMDINT, 12, 4) 1898 FIELD(MVFR1, SIMDSP, 16, 4) 1899 FIELD(MVFR1, SIMDHP, 20, 4) 1900 FIELD(MVFR1, FPHP, 24, 4) 1901 FIELD(MVFR1, SIMDFMAC, 28, 4) 1902 1903 FIELD(MVFR2, SIMDMISC, 0, 4) 1904 FIELD(MVFR2, FPMISC, 4, 4) 1905 1906 QEMU_BUILD_BUG_ON(ARRAY_SIZE(((ARMCPU *)0)->ccsidr) <= R_V7M_CSSELR_INDEX_MASK); 1907 1908 /* If adding a feature bit which corresponds to a Linux ELF 1909 * HWCAP bit, remember to update the feature-bit-to-hwcap 1910 * mapping in linux-user/elfload.c:get_elf_hwcap(). 1911 */ 1912 enum arm_features { 1913 ARM_FEATURE_AUXCR, /* ARM1026 Auxiliary control register. */ 1914 ARM_FEATURE_XSCALE, /* Intel XScale extensions. */ 1915 ARM_FEATURE_IWMMXT, /* Intel iwMMXt extension. */ 1916 ARM_FEATURE_V6, 1917 ARM_FEATURE_V6K, 1918 ARM_FEATURE_V7, 1919 ARM_FEATURE_THUMB2, 1920 ARM_FEATURE_PMSA, /* no MMU; may have Memory Protection Unit */ 1921 ARM_FEATURE_NEON, 1922 ARM_FEATURE_M, /* Microcontroller profile. */ 1923 ARM_FEATURE_OMAPCP, /* OMAP specific CP15 ops handling. */ 1924 ARM_FEATURE_THUMB2EE, 1925 ARM_FEATURE_V7MP, /* v7 Multiprocessing Extensions */ 1926 ARM_FEATURE_V7VE, /* v7 Virtualization Extensions (non-EL2 parts) */ 1927 ARM_FEATURE_V4T, 1928 ARM_FEATURE_V5, 1929 ARM_FEATURE_STRONGARM, 1930 ARM_FEATURE_VAPA, /* cp15 VA to PA lookups */ 1931 ARM_FEATURE_GENERIC_TIMER, 1932 ARM_FEATURE_MVFR, /* Media and VFP Feature Registers 0 and 1 */ 1933 ARM_FEATURE_DUMMY_C15_REGS, /* RAZ/WI all of cp15 crn=15 */ 1934 ARM_FEATURE_CACHE_TEST_CLEAN, /* 926/1026 style test-and-clean ops */ 1935 ARM_FEATURE_CACHE_DIRTY_REG, /* 1136/1176 cache dirty status register */ 1936 ARM_FEATURE_CACHE_BLOCK_OPS, /* v6 optional cache block operations */ 1937 ARM_FEATURE_MPIDR, /* has cp15 MPIDR */ 1938 ARM_FEATURE_PXN, /* has Privileged Execute Never bit */ 1939 ARM_FEATURE_LPAE, /* has Large Physical Address Extension */ 1940 ARM_FEATURE_V8, 1941 ARM_FEATURE_AARCH64, /* supports 64 bit mode */ 1942 ARM_FEATURE_CBAR, /* has cp15 CBAR */ 1943 ARM_FEATURE_CRC, /* ARMv8 CRC instructions */ 1944 ARM_FEATURE_CBAR_RO, /* has cp15 CBAR and it is read-only */ 1945 ARM_FEATURE_EL2, /* has EL2 Virtualization support */ 1946 ARM_FEATURE_EL3, /* has EL3 Secure monitor support */ 1947 ARM_FEATURE_THUMB_DSP, /* DSP insns supported in the Thumb encodings */ 1948 ARM_FEATURE_PMU, /* has PMU support */ 1949 ARM_FEATURE_VBAR, /* has cp15 VBAR */ 1950 ARM_FEATURE_M_SECURITY, /* M profile Security Extension */ 1951 ARM_FEATURE_M_MAIN, /* M profile Main Extension */ 1952 }; 1953 1954 static inline int arm_feature(CPUARMState *env, int feature) 1955 { 1956 return (env->features & (1ULL << feature)) != 0; 1957 } 1958 1959 void arm_cpu_finalize_features(ARMCPU *cpu, Error **errp); 1960 1961 #if !defined(CONFIG_USER_ONLY) 1962 /* Return true if exception levels below EL3 are in secure state, 1963 * or would be following an exception return to that level. 1964 * Unlike arm_is_secure() (which is always a question about the 1965 * _current_ state of the CPU) this doesn't care about the current 1966 * EL or mode. 1967 */ 1968 static inline bool arm_is_secure_below_el3(CPUARMState *env) 1969 { 1970 if (arm_feature(env, ARM_FEATURE_EL3)) { 1971 return !(env->cp15.scr_el3 & SCR_NS); 1972 } else { 1973 /* If EL3 is not supported then the secure state is implementation 1974 * defined, in which case QEMU defaults to non-secure. 1975 */ 1976 return false; 1977 } 1978 } 1979 1980 /* Return true if the CPU is AArch64 EL3 or AArch32 Mon */ 1981 static inline bool arm_is_el3_or_mon(CPUARMState *env) 1982 { 1983 if (arm_feature(env, ARM_FEATURE_EL3)) { 1984 if (is_a64(env) && extract32(env->pstate, 2, 2) == 3) { 1985 /* CPU currently in AArch64 state and EL3 */ 1986 return true; 1987 } else if (!is_a64(env) && 1988 (env->uncached_cpsr & CPSR_M) == ARM_CPU_MODE_MON) { 1989 /* CPU currently in AArch32 state and monitor mode */ 1990 return true; 1991 } 1992 } 1993 return false; 1994 } 1995 1996 /* Return true if the processor is in secure state */ 1997 static inline bool arm_is_secure(CPUARMState *env) 1998 { 1999 if (arm_is_el3_or_mon(env)) { 2000 return true; 2001 } 2002 return arm_is_secure_below_el3(env); 2003 } 2004 2005 #else 2006 static inline bool arm_is_secure_below_el3(CPUARMState *env) 2007 { 2008 return false; 2009 } 2010 2011 static inline bool arm_is_secure(CPUARMState *env) 2012 { 2013 return false; 2014 } 2015 #endif 2016 2017 /** 2018 * arm_hcr_el2_eff(): Return the effective value of HCR_EL2. 2019 * E.g. when in secure state, fields in HCR_EL2 are suppressed, 2020 * "for all purposes other than a direct read or write access of HCR_EL2." 2021 * Not included here is HCR_RW. 2022 */ 2023 uint64_t arm_hcr_el2_eff(CPUARMState *env); 2024 2025 /* Return true if the specified exception level is running in AArch64 state. */ 2026 static inline bool arm_el_is_aa64(CPUARMState *env, int el) 2027 { 2028 /* This isn't valid for EL0 (if we're in EL0, is_a64() is what you want, 2029 * and if we're not in EL0 then the state of EL0 isn't well defined.) 2030 */ 2031 assert(el >= 1 && el <= 3); 2032 bool aa64 = arm_feature(env, ARM_FEATURE_AARCH64); 2033 2034 /* The highest exception level is always at the maximum supported 2035 * register width, and then lower levels have a register width controlled 2036 * by bits in the SCR or HCR registers. 2037 */ 2038 if (el == 3) { 2039 return aa64; 2040 } 2041 2042 if (arm_feature(env, ARM_FEATURE_EL3)) { 2043 aa64 = aa64 && (env->cp15.scr_el3 & SCR_RW); 2044 } 2045 2046 if (el == 2) { 2047 return aa64; 2048 } 2049 2050 if (arm_feature(env, ARM_FEATURE_EL2) && !arm_is_secure_below_el3(env)) { 2051 aa64 = aa64 && (env->cp15.hcr_el2 & HCR_RW); 2052 } 2053 2054 return aa64; 2055 } 2056 2057 /* Function for determing whether guest cp register reads and writes should 2058 * access the secure or non-secure bank of a cp register. When EL3 is 2059 * operating in AArch32 state, the NS-bit determines whether the secure 2060 * instance of a cp register should be used. When EL3 is AArch64 (or if 2061 * it doesn't exist at all) then there is no register banking, and all 2062 * accesses are to the non-secure version. 2063 */ 2064 static inline bool access_secure_reg(CPUARMState *env) 2065 { 2066 bool ret = (arm_feature(env, ARM_FEATURE_EL3) && 2067 !arm_el_is_aa64(env, 3) && 2068 !(env->cp15.scr_el3 & SCR_NS)); 2069 2070 return ret; 2071 } 2072 2073 /* Macros for accessing a specified CP register bank */ 2074 #define A32_BANKED_REG_GET(_env, _regname, _secure) \ 2075 ((_secure) ? (_env)->cp15._regname##_s : (_env)->cp15._regname##_ns) 2076 2077 #define A32_BANKED_REG_SET(_env, _regname, _secure, _val) \ 2078 do { \ 2079 if (_secure) { \ 2080 (_env)->cp15._regname##_s = (_val); \ 2081 } else { \ 2082 (_env)->cp15._regname##_ns = (_val); \ 2083 } \ 2084 } while (0) 2085 2086 /* Macros for automatically accessing a specific CP register bank depending on 2087 * the current secure state of the system. These macros are not intended for 2088 * supporting instruction translation reads/writes as these are dependent 2089 * solely on the SCR.NS bit and not the mode. 2090 */ 2091 #define A32_BANKED_CURRENT_REG_GET(_env, _regname) \ 2092 A32_BANKED_REG_GET((_env), _regname, \ 2093 (arm_is_secure(_env) && !arm_el_is_aa64((_env), 3))) 2094 2095 #define A32_BANKED_CURRENT_REG_SET(_env, _regname, _val) \ 2096 A32_BANKED_REG_SET((_env), _regname, \ 2097 (arm_is_secure(_env) && !arm_el_is_aa64((_env), 3)), \ 2098 (_val)) 2099 2100 void arm_cpu_list(void); 2101 uint32_t arm_phys_excp_target_el(CPUState *cs, uint32_t excp_idx, 2102 uint32_t cur_el, bool secure); 2103 2104 /* Interface between CPU and Interrupt controller. */ 2105 #ifndef CONFIG_USER_ONLY 2106 bool armv7m_nvic_can_take_pending_exception(void *opaque); 2107 #else 2108 static inline bool armv7m_nvic_can_take_pending_exception(void *opaque) 2109 { 2110 return true; 2111 } 2112 #endif 2113 /** 2114 * armv7m_nvic_set_pending: mark the specified exception as pending 2115 * @opaque: the NVIC 2116 * @irq: the exception number to mark pending 2117 * @secure: false for non-banked exceptions or for the nonsecure 2118 * version of a banked exception, true for the secure version of a banked 2119 * exception. 2120 * 2121 * Marks the specified exception as pending. Note that we will assert() 2122 * if @secure is true and @irq does not specify one of the fixed set 2123 * of architecturally banked exceptions. 2124 */ 2125 void armv7m_nvic_set_pending(void *opaque, int irq, bool secure); 2126 /** 2127 * armv7m_nvic_set_pending_derived: mark this derived exception as pending 2128 * @opaque: the NVIC 2129 * @irq: the exception number to mark pending 2130 * @secure: false for non-banked exceptions or for the nonsecure 2131 * version of a banked exception, true for the secure version of a banked 2132 * exception. 2133 * 2134 * Similar to armv7m_nvic_set_pending(), but specifically for derived 2135 * exceptions (exceptions generated in the course of trying to take 2136 * a different exception). 2137 */ 2138 void armv7m_nvic_set_pending_derived(void *opaque, int irq, bool secure); 2139 /** 2140 * armv7m_nvic_set_pending_lazyfp: mark this lazy FP exception as pending 2141 * @opaque: the NVIC 2142 * @irq: the exception number to mark pending 2143 * @secure: false for non-banked exceptions or for the nonsecure 2144 * version of a banked exception, true for the secure version of a banked 2145 * exception. 2146 * 2147 * Similar to armv7m_nvic_set_pending(), but specifically for exceptions 2148 * generated in the course of lazy stacking of FP registers. 2149 */ 2150 void armv7m_nvic_set_pending_lazyfp(void *opaque, int irq, bool secure); 2151 /** 2152 * armv7m_nvic_get_pending_irq_info: return highest priority pending 2153 * exception, and whether it targets Secure state 2154 * @opaque: the NVIC 2155 * @pirq: set to pending exception number 2156 * @ptargets_secure: set to whether pending exception targets Secure 2157 * 2158 * This function writes the number of the highest priority pending 2159 * exception (the one which would be made active by 2160 * armv7m_nvic_acknowledge_irq()) to @pirq, and sets @ptargets_secure 2161 * to true if the current highest priority pending exception should 2162 * be taken to Secure state, false for NS. 2163 */ 2164 void armv7m_nvic_get_pending_irq_info(void *opaque, int *pirq, 2165 bool *ptargets_secure); 2166 /** 2167 * armv7m_nvic_acknowledge_irq: make highest priority pending exception active 2168 * @opaque: the NVIC 2169 * 2170 * Move the current highest priority pending exception from the pending 2171 * state to the active state, and update v7m.exception to indicate that 2172 * it is the exception currently being handled. 2173 */ 2174 void armv7m_nvic_acknowledge_irq(void *opaque); 2175 /** 2176 * armv7m_nvic_complete_irq: complete specified interrupt or exception 2177 * @opaque: the NVIC 2178 * @irq: the exception number to complete 2179 * @secure: true if this exception was secure 2180 * 2181 * Returns: -1 if the irq was not active 2182 * 1 if completing this irq brought us back to base (no active irqs) 2183 * 0 if there is still an irq active after this one was completed 2184 * (Ignoring -1, this is the same as the RETTOBASE value before completion.) 2185 */ 2186 int armv7m_nvic_complete_irq(void *opaque, int irq, bool secure); 2187 /** 2188 * armv7m_nvic_get_ready_status(void *opaque, int irq, bool secure) 2189 * @opaque: the NVIC 2190 * @irq: the exception number to mark pending 2191 * @secure: false for non-banked exceptions or for the nonsecure 2192 * version of a banked exception, true for the secure version of a banked 2193 * exception. 2194 * 2195 * Return whether an exception is "ready", i.e. whether the exception is 2196 * enabled and is configured at a priority which would allow it to 2197 * interrupt the current execution priority. This controls whether the 2198 * RDY bit for it in the FPCCR is set. 2199 */ 2200 bool armv7m_nvic_get_ready_status(void *opaque, int irq, bool secure); 2201 /** 2202 * armv7m_nvic_raw_execution_priority: return the raw execution priority 2203 * @opaque: the NVIC 2204 * 2205 * Returns: the raw execution priority as defined by the v8M architecture. 2206 * This is the execution priority minus the effects of AIRCR.PRIS, 2207 * and minus any PRIMASK/FAULTMASK/BASEPRI priority boosting. 2208 * (v8M ARM ARM I_PKLD.) 2209 */ 2210 int armv7m_nvic_raw_execution_priority(void *opaque); 2211 /** 2212 * armv7m_nvic_neg_prio_requested: return true if the requested execution 2213 * priority is negative for the specified security state. 2214 * @opaque: the NVIC 2215 * @secure: the security state to test 2216 * This corresponds to the pseudocode IsReqExecPriNeg(). 2217 */ 2218 #ifndef CONFIG_USER_ONLY 2219 bool armv7m_nvic_neg_prio_requested(void *opaque, bool secure); 2220 #else 2221 static inline bool armv7m_nvic_neg_prio_requested(void *opaque, bool secure) 2222 { 2223 return false; 2224 } 2225 #endif 2226 2227 /* Interface for defining coprocessor registers. 2228 * Registers are defined in tables of arm_cp_reginfo structs 2229 * which are passed to define_arm_cp_regs(). 2230 */ 2231 2232 /* When looking up a coprocessor register we look for it 2233 * via an integer which encodes all of: 2234 * coprocessor number 2235 * Crn, Crm, opc1, opc2 fields 2236 * 32 or 64 bit register (ie is it accessed via MRC/MCR 2237 * or via MRRC/MCRR?) 2238 * non-secure/secure bank (AArch32 only) 2239 * We allow 4 bits for opc1 because MRRC/MCRR have a 4 bit field. 2240 * (In this case crn and opc2 should be zero.) 2241 * For AArch64, there is no 32/64 bit size distinction; 2242 * instead all registers have a 2 bit op0, 3 bit op1 and op2, 2243 * and 4 bit CRn and CRm. The encoding patterns are chosen 2244 * to be easy to convert to and from the KVM encodings, and also 2245 * so that the hashtable can contain both AArch32 and AArch64 2246 * registers (to allow for interprocessing where we might run 2247 * 32 bit code on a 64 bit core). 2248 */ 2249 /* This bit is private to our hashtable cpreg; in KVM register 2250 * IDs the AArch64/32 distinction is the KVM_REG_ARM/ARM64 2251 * in the upper bits of the 64 bit ID. 2252 */ 2253 #define CP_REG_AA64_SHIFT 28 2254 #define CP_REG_AA64_MASK (1 << CP_REG_AA64_SHIFT) 2255 2256 /* To enable banking of coprocessor registers depending on ns-bit we 2257 * add a bit to distinguish between secure and non-secure cpregs in the 2258 * hashtable. 2259 */ 2260 #define CP_REG_NS_SHIFT 29 2261 #define CP_REG_NS_MASK (1 << CP_REG_NS_SHIFT) 2262 2263 #define ENCODE_CP_REG(cp, is64, ns, crn, crm, opc1, opc2) \ 2264 ((ns) << CP_REG_NS_SHIFT | ((cp) << 16) | ((is64) << 15) | \ 2265 ((crn) << 11) | ((crm) << 7) | ((opc1) << 3) | (opc2)) 2266 2267 #define ENCODE_AA64_CP_REG(cp, crn, crm, op0, op1, op2) \ 2268 (CP_REG_AA64_MASK | \ 2269 ((cp) << CP_REG_ARM_COPROC_SHIFT) | \ 2270 ((op0) << CP_REG_ARM64_SYSREG_OP0_SHIFT) | \ 2271 ((op1) << CP_REG_ARM64_SYSREG_OP1_SHIFT) | \ 2272 ((crn) << CP_REG_ARM64_SYSREG_CRN_SHIFT) | \ 2273 ((crm) << CP_REG_ARM64_SYSREG_CRM_SHIFT) | \ 2274 ((op2) << CP_REG_ARM64_SYSREG_OP2_SHIFT)) 2275 2276 /* Convert a full 64 bit KVM register ID to the truncated 32 bit 2277 * version used as a key for the coprocessor register hashtable 2278 */ 2279 static inline uint32_t kvm_to_cpreg_id(uint64_t kvmid) 2280 { 2281 uint32_t cpregid = kvmid; 2282 if ((kvmid & CP_REG_ARCH_MASK) == CP_REG_ARM64) { 2283 cpregid |= CP_REG_AA64_MASK; 2284 } else { 2285 if ((kvmid & CP_REG_SIZE_MASK) == CP_REG_SIZE_U64) { 2286 cpregid |= (1 << 15); 2287 } 2288 2289 /* KVM is always non-secure so add the NS flag on AArch32 register 2290 * entries. 2291 */ 2292 cpregid |= 1 << CP_REG_NS_SHIFT; 2293 } 2294 return cpregid; 2295 } 2296 2297 /* Convert a truncated 32 bit hashtable key into the full 2298 * 64 bit KVM register ID. 2299 */ 2300 static inline uint64_t cpreg_to_kvm_id(uint32_t cpregid) 2301 { 2302 uint64_t kvmid; 2303 2304 if (cpregid & CP_REG_AA64_MASK) { 2305 kvmid = cpregid & ~CP_REG_AA64_MASK; 2306 kvmid |= CP_REG_SIZE_U64 | CP_REG_ARM64; 2307 } else { 2308 kvmid = cpregid & ~(1 << 15); 2309 if (cpregid & (1 << 15)) { 2310 kvmid |= CP_REG_SIZE_U64 | CP_REG_ARM; 2311 } else { 2312 kvmid |= CP_REG_SIZE_U32 | CP_REG_ARM; 2313 } 2314 } 2315 return kvmid; 2316 } 2317 2318 /* ARMCPRegInfo type field bits. If the SPECIAL bit is set this is a 2319 * special-behaviour cp reg and bits [11..8] indicate what behaviour 2320 * it has. Otherwise it is a simple cp reg, where CONST indicates that 2321 * TCG can assume the value to be constant (ie load at translate time) 2322 * and 64BIT indicates a 64 bit wide coprocessor register. SUPPRESS_TB_END 2323 * indicates that the TB should not be ended after a write to this register 2324 * (the default is that the TB ends after cp writes). OVERRIDE permits 2325 * a register definition to override a previous definition for the 2326 * same (cp, is64, crn, crm, opc1, opc2) tuple: either the new or the 2327 * old must have the OVERRIDE bit set. 2328 * ALIAS indicates that this register is an alias view of some underlying 2329 * state which is also visible via another register, and that the other 2330 * register is handling migration and reset; registers marked ALIAS will not be 2331 * migrated but may have their state set by syncing of register state from KVM. 2332 * NO_RAW indicates that this register has no underlying state and does not 2333 * support raw access for state saving/loading; it will not be used for either 2334 * migration or KVM state synchronization. (Typically this is for "registers" 2335 * which are actually used as instructions for cache maintenance and so on.) 2336 * IO indicates that this register does I/O and therefore its accesses 2337 * need to be surrounded by gen_io_start()/gen_io_end(). In particular, 2338 * registers which implement clocks or timers require this. 2339 * RAISES_EXC is for when the read or write hook might raise an exception; 2340 * the generated code will synchronize the CPU state before calling the hook 2341 * so that it is safe for the hook to call raise_exception(). 2342 * NEWEL is for writes to registers that might change the exception 2343 * level - typically on older ARM chips. For those cases we need to 2344 * re-read the new el when recomputing the translation flags. 2345 */ 2346 #define ARM_CP_SPECIAL 0x0001 2347 #define ARM_CP_CONST 0x0002 2348 #define ARM_CP_64BIT 0x0004 2349 #define ARM_CP_SUPPRESS_TB_END 0x0008 2350 #define ARM_CP_OVERRIDE 0x0010 2351 #define ARM_CP_ALIAS 0x0020 2352 #define ARM_CP_IO 0x0040 2353 #define ARM_CP_NO_RAW 0x0080 2354 #define ARM_CP_NOP (ARM_CP_SPECIAL | 0x0100) 2355 #define ARM_CP_WFI (ARM_CP_SPECIAL | 0x0200) 2356 #define ARM_CP_NZCV (ARM_CP_SPECIAL | 0x0300) 2357 #define ARM_CP_CURRENTEL (ARM_CP_SPECIAL | 0x0400) 2358 #define ARM_CP_DC_ZVA (ARM_CP_SPECIAL | 0x0500) 2359 #define ARM_LAST_SPECIAL ARM_CP_DC_ZVA 2360 #define ARM_CP_FPU 0x1000 2361 #define ARM_CP_SVE 0x2000 2362 #define ARM_CP_NO_GDB 0x4000 2363 #define ARM_CP_RAISES_EXC 0x8000 2364 #define ARM_CP_NEWEL 0x10000 2365 /* Used only as a terminator for ARMCPRegInfo lists */ 2366 #define ARM_CP_SENTINEL 0xfffff 2367 /* Mask of only the flag bits in a type field */ 2368 #define ARM_CP_FLAG_MASK 0x1f0ff 2369 2370 /* Valid values for ARMCPRegInfo state field, indicating which of 2371 * the AArch32 and AArch64 execution states this register is visible in. 2372 * If the reginfo doesn't explicitly specify then it is AArch32 only. 2373 * If the reginfo is declared to be visible in both states then a second 2374 * reginfo is synthesised for the AArch32 view of the AArch64 register, 2375 * such that the AArch32 view is the lower 32 bits of the AArch64 one. 2376 * Note that we rely on the values of these enums as we iterate through 2377 * the various states in some places. 2378 */ 2379 enum { 2380 ARM_CP_STATE_AA32 = 0, 2381 ARM_CP_STATE_AA64 = 1, 2382 ARM_CP_STATE_BOTH = 2, 2383 }; 2384 2385 /* ARM CP register secure state flags. These flags identify security state 2386 * attributes for a given CP register entry. 2387 * The existence of both or neither secure and non-secure flags indicates that 2388 * the register has both a secure and non-secure hash entry. A single one of 2389 * these flags causes the register to only be hashed for the specified 2390 * security state. 2391 * Although definitions may have any combination of the S/NS bits, each 2392 * registered entry will only have one to identify whether the entry is secure 2393 * or non-secure. 2394 */ 2395 enum { 2396 ARM_CP_SECSTATE_S = (1 << 0), /* bit[0]: Secure state register */ 2397 ARM_CP_SECSTATE_NS = (1 << 1), /* bit[1]: Non-secure state register */ 2398 }; 2399 2400 /* Return true if cptype is a valid type field. This is used to try to 2401 * catch errors where the sentinel has been accidentally left off the end 2402 * of a list of registers. 2403 */ 2404 static inline bool cptype_valid(int cptype) 2405 { 2406 return ((cptype & ~ARM_CP_FLAG_MASK) == 0) 2407 || ((cptype & ARM_CP_SPECIAL) && 2408 ((cptype & ~ARM_CP_FLAG_MASK) <= ARM_LAST_SPECIAL)); 2409 } 2410 2411 /* Access rights: 2412 * We define bits for Read and Write access for what rev C of the v7-AR ARM ARM 2413 * defines as PL0 (user), PL1 (fiq/irq/svc/abt/und/sys, ie privileged), and 2414 * PL2 (hyp). The other level which has Read and Write bits is Secure PL1 2415 * (ie any of the privileged modes in Secure state, or Monitor mode). 2416 * If a register is accessible in one privilege level it's always accessible 2417 * in higher privilege levels too. Since "Secure PL1" also follows this rule 2418 * (ie anything visible in PL2 is visible in S-PL1, some things are only 2419 * visible in S-PL1) but "Secure PL1" is a bit of a mouthful, we bend the 2420 * terminology a little and call this PL3. 2421 * In AArch64 things are somewhat simpler as the PLx bits line up exactly 2422 * with the ELx exception levels. 2423 * 2424 * If access permissions for a register are more complex than can be 2425 * described with these bits, then use a laxer set of restrictions, and 2426 * do the more restrictive/complex check inside a helper function. 2427 */ 2428 #define PL3_R 0x80 2429 #define PL3_W 0x40 2430 #define PL2_R (0x20 | PL3_R) 2431 #define PL2_W (0x10 | PL3_W) 2432 #define PL1_R (0x08 | PL2_R) 2433 #define PL1_W (0x04 | PL2_W) 2434 #define PL0_R (0x02 | PL1_R) 2435 #define PL0_W (0x01 | PL1_W) 2436 2437 /* 2438 * For user-mode some registers are accessible to EL0 via a kernel 2439 * trap-and-emulate ABI. In this case we define the read permissions 2440 * as actually being PL0_R. However some bits of any given register 2441 * may still be masked. 2442 */ 2443 #ifdef CONFIG_USER_ONLY 2444 #define PL0U_R PL0_R 2445 #else 2446 #define PL0U_R PL1_R 2447 #endif 2448 2449 #define PL3_RW (PL3_R | PL3_W) 2450 #define PL2_RW (PL2_R | PL2_W) 2451 #define PL1_RW (PL1_R | PL1_W) 2452 #define PL0_RW (PL0_R | PL0_W) 2453 2454 /* Return the highest implemented Exception Level */ 2455 static inline int arm_highest_el(CPUARMState *env) 2456 { 2457 if (arm_feature(env, ARM_FEATURE_EL3)) { 2458 return 3; 2459 } 2460 if (arm_feature(env, ARM_FEATURE_EL2)) { 2461 return 2; 2462 } 2463 return 1; 2464 } 2465 2466 /* Return true if a v7M CPU is in Handler mode */ 2467 static inline bool arm_v7m_is_handler_mode(CPUARMState *env) 2468 { 2469 return env->v7m.exception != 0; 2470 } 2471 2472 /* Return the current Exception Level (as per ARMv8; note that this differs 2473 * from the ARMv7 Privilege Level). 2474 */ 2475 static inline int arm_current_el(CPUARMState *env) 2476 { 2477 if (arm_feature(env, ARM_FEATURE_M)) { 2478 return arm_v7m_is_handler_mode(env) || 2479 !(env->v7m.control[env->v7m.secure] & 1); 2480 } 2481 2482 if (is_a64(env)) { 2483 return extract32(env->pstate, 2, 2); 2484 } 2485 2486 switch (env->uncached_cpsr & 0x1f) { 2487 case ARM_CPU_MODE_USR: 2488 return 0; 2489 case ARM_CPU_MODE_HYP: 2490 return 2; 2491 case ARM_CPU_MODE_MON: 2492 return 3; 2493 default: 2494 if (arm_is_secure(env) && !arm_el_is_aa64(env, 3)) { 2495 /* If EL3 is 32-bit then all secure privileged modes run in 2496 * EL3 2497 */ 2498 return 3; 2499 } 2500 2501 return 1; 2502 } 2503 } 2504 2505 typedef struct ARMCPRegInfo ARMCPRegInfo; 2506 2507 typedef enum CPAccessResult { 2508 /* Access is permitted */ 2509 CP_ACCESS_OK = 0, 2510 /* Access fails due to a configurable trap or enable which would 2511 * result in a categorized exception syndrome giving information about 2512 * the failing instruction (ie syndrome category 0x3, 0x4, 0x5, 0x6, 2513 * 0xc or 0x18). The exception is taken to the usual target EL (EL1 or 2514 * PL1 if in EL0, otherwise to the current EL). 2515 */ 2516 CP_ACCESS_TRAP = 1, 2517 /* Access fails and results in an exception syndrome 0x0 ("uncategorized"). 2518 * Note that this is not a catch-all case -- the set of cases which may 2519 * result in this failure is specifically defined by the architecture. 2520 */ 2521 CP_ACCESS_TRAP_UNCATEGORIZED = 2, 2522 /* As CP_ACCESS_TRAP, but for traps directly to EL2 or EL3 */ 2523 CP_ACCESS_TRAP_EL2 = 3, 2524 CP_ACCESS_TRAP_EL3 = 4, 2525 /* As CP_ACCESS_UNCATEGORIZED, but for traps directly to EL2 or EL3 */ 2526 CP_ACCESS_TRAP_UNCATEGORIZED_EL2 = 5, 2527 CP_ACCESS_TRAP_UNCATEGORIZED_EL3 = 6, 2528 /* Access fails and results in an exception syndrome for an FP access, 2529 * trapped directly to EL2 or EL3 2530 */ 2531 CP_ACCESS_TRAP_FP_EL2 = 7, 2532 CP_ACCESS_TRAP_FP_EL3 = 8, 2533 } CPAccessResult; 2534 2535 /* Access functions for coprocessor registers. These cannot fail and 2536 * may not raise exceptions. 2537 */ 2538 typedef uint64_t CPReadFn(CPUARMState *env, const ARMCPRegInfo *opaque); 2539 typedef void CPWriteFn(CPUARMState *env, const ARMCPRegInfo *opaque, 2540 uint64_t value); 2541 /* Access permission check functions for coprocessor registers. */ 2542 typedef CPAccessResult CPAccessFn(CPUARMState *env, 2543 const ARMCPRegInfo *opaque, 2544 bool isread); 2545 /* Hook function for register reset */ 2546 typedef void CPResetFn(CPUARMState *env, const ARMCPRegInfo *opaque); 2547 2548 #define CP_ANY 0xff 2549 2550 /* Definition of an ARM coprocessor register */ 2551 struct ARMCPRegInfo { 2552 /* Name of register (useful mainly for debugging, need not be unique) */ 2553 const char *name; 2554 /* Location of register: coprocessor number and (crn,crm,opc1,opc2) 2555 * tuple. Any of crm, opc1 and opc2 may be CP_ANY to indicate a 2556 * 'wildcard' field -- any value of that field in the MRC/MCR insn 2557 * will be decoded to this register. The register read and write 2558 * callbacks will be passed an ARMCPRegInfo with the crn/crm/opc1/opc2 2559 * used by the program, so it is possible to register a wildcard and 2560 * then behave differently on read/write if necessary. 2561 * For 64 bit registers, only crm and opc1 are relevant; crn and opc2 2562 * must both be zero. 2563 * For AArch64-visible registers, opc0 is also used. 2564 * Since there are no "coprocessors" in AArch64, cp is purely used as a 2565 * way to distinguish (for KVM's benefit) guest-visible system registers 2566 * from demuxed ones provided to preserve the "no side effects on 2567 * KVM register read/write from QEMU" semantics. cp==0x13 is guest 2568 * visible (to match KVM's encoding); cp==0 will be converted to 2569 * cp==0x13 when the ARMCPRegInfo is registered, for convenience. 2570 */ 2571 uint8_t cp; 2572 uint8_t crn; 2573 uint8_t crm; 2574 uint8_t opc0; 2575 uint8_t opc1; 2576 uint8_t opc2; 2577 /* Execution state in which this register is visible: ARM_CP_STATE_* */ 2578 int state; 2579 /* Register type: ARM_CP_* bits/values */ 2580 int type; 2581 /* Access rights: PL*_[RW] */ 2582 int access; 2583 /* Security state: ARM_CP_SECSTATE_* bits/values */ 2584 int secure; 2585 /* The opaque pointer passed to define_arm_cp_regs_with_opaque() when 2586 * this register was defined: can be used to hand data through to the 2587 * register read/write functions, since they are passed the ARMCPRegInfo*. 2588 */ 2589 void *opaque; 2590 /* Value of this register, if it is ARM_CP_CONST. Otherwise, if 2591 * fieldoffset is non-zero, the reset value of the register. 2592 */ 2593 uint64_t resetvalue; 2594 /* Offset of the field in CPUARMState for this register. 2595 * 2596 * This is not needed if either: 2597 * 1. type is ARM_CP_CONST or one of the ARM_CP_SPECIALs 2598 * 2. both readfn and writefn are specified 2599 */ 2600 ptrdiff_t fieldoffset; /* offsetof(CPUARMState, field) */ 2601 2602 /* Offsets of the secure and non-secure fields in CPUARMState for the 2603 * register if it is banked. These fields are only used during the static 2604 * registration of a register. During hashing the bank associated 2605 * with a given security state is copied to fieldoffset which is used from 2606 * there on out. 2607 * 2608 * It is expected that register definitions use either fieldoffset or 2609 * bank_fieldoffsets in the definition but not both. It is also expected 2610 * that both bank offsets are set when defining a banked register. This 2611 * use indicates that a register is banked. 2612 */ 2613 ptrdiff_t bank_fieldoffsets[2]; 2614 2615 /* Function for making any access checks for this register in addition to 2616 * those specified by the 'access' permissions bits. If NULL, no extra 2617 * checks required. The access check is performed at runtime, not at 2618 * translate time. 2619 */ 2620 CPAccessFn *accessfn; 2621 /* Function for handling reads of this register. If NULL, then reads 2622 * will be done by loading from the offset into CPUARMState specified 2623 * by fieldoffset. 2624 */ 2625 CPReadFn *readfn; 2626 /* Function for handling writes of this register. If NULL, then writes 2627 * will be done by writing to the offset into CPUARMState specified 2628 * by fieldoffset. 2629 */ 2630 CPWriteFn *writefn; 2631 /* Function for doing a "raw" read; used when we need to copy 2632 * coprocessor state to the kernel for KVM or out for 2633 * migration. This only needs to be provided if there is also a 2634 * readfn and it has side effects (for instance clear-on-read bits). 2635 */ 2636 CPReadFn *raw_readfn; 2637 /* Function for doing a "raw" write; used when we need to copy KVM 2638 * kernel coprocessor state into userspace, or for inbound 2639 * migration. This only needs to be provided if there is also a 2640 * writefn and it masks out "unwritable" bits or has write-one-to-clear 2641 * or similar behaviour. 2642 */ 2643 CPWriteFn *raw_writefn; 2644 /* Function for resetting the register. If NULL, then reset will be done 2645 * by writing resetvalue to the field specified in fieldoffset. If 2646 * fieldoffset is 0 then no reset will be done. 2647 */ 2648 CPResetFn *resetfn; 2649 2650 /* 2651 * "Original" writefn and readfn. 2652 * For ARMv8.1-VHE register aliases, we overwrite the read/write 2653 * accessor functions of various EL1/EL0 to perform the runtime 2654 * check for which sysreg should actually be modified, and then 2655 * forwards the operation. Before overwriting the accessors, 2656 * the original function is copied here, so that accesses that 2657 * really do go to the EL1/EL0 version proceed normally. 2658 * (The corresponding EL2 register is linked via opaque.) 2659 */ 2660 CPReadFn *orig_readfn; 2661 CPWriteFn *orig_writefn; 2662 }; 2663 2664 /* Macros which are lvalues for the field in CPUARMState for the 2665 * ARMCPRegInfo *ri. 2666 */ 2667 #define CPREG_FIELD32(env, ri) \ 2668 (*(uint32_t *)((char *)(env) + (ri)->fieldoffset)) 2669 #define CPREG_FIELD64(env, ri) \ 2670 (*(uint64_t *)((char *)(env) + (ri)->fieldoffset)) 2671 2672 #define REGINFO_SENTINEL { .type = ARM_CP_SENTINEL } 2673 2674 void define_arm_cp_regs_with_opaque(ARMCPU *cpu, 2675 const ARMCPRegInfo *regs, void *opaque); 2676 void define_one_arm_cp_reg_with_opaque(ARMCPU *cpu, 2677 const ARMCPRegInfo *regs, void *opaque); 2678 static inline void define_arm_cp_regs(ARMCPU *cpu, const ARMCPRegInfo *regs) 2679 { 2680 define_arm_cp_regs_with_opaque(cpu, regs, 0); 2681 } 2682 static inline void define_one_arm_cp_reg(ARMCPU *cpu, const ARMCPRegInfo *regs) 2683 { 2684 define_one_arm_cp_reg_with_opaque(cpu, regs, 0); 2685 } 2686 const ARMCPRegInfo *get_arm_cp_reginfo(GHashTable *cpregs, uint32_t encoded_cp); 2687 2688 /* 2689 * Definition of an ARM co-processor register as viewed from 2690 * userspace. This is used for presenting sanitised versions of 2691 * registers to userspace when emulating the Linux AArch64 CPU 2692 * ID/feature ABI (advertised as HWCAP_CPUID). 2693 */ 2694 typedef struct ARMCPRegUserSpaceInfo { 2695 /* Name of register */ 2696 const char *name; 2697 2698 /* Is the name actually a glob pattern */ 2699 bool is_glob; 2700 2701 /* Only some bits are exported to user space */ 2702 uint64_t exported_bits; 2703 2704 /* Fixed bits are applied after the mask */ 2705 uint64_t fixed_bits; 2706 } ARMCPRegUserSpaceInfo; 2707 2708 #define REGUSERINFO_SENTINEL { .name = NULL } 2709 2710 void modify_arm_cp_regs(ARMCPRegInfo *regs, const ARMCPRegUserSpaceInfo *mods); 2711 2712 /* CPWriteFn that can be used to implement writes-ignored behaviour */ 2713 void arm_cp_write_ignore(CPUARMState *env, const ARMCPRegInfo *ri, 2714 uint64_t value); 2715 /* CPReadFn that can be used for read-as-zero behaviour */ 2716 uint64_t arm_cp_read_zero(CPUARMState *env, const ARMCPRegInfo *ri); 2717 2718 /* CPResetFn that does nothing, for use if no reset is required even 2719 * if fieldoffset is non zero. 2720 */ 2721 void arm_cp_reset_ignore(CPUARMState *env, const ARMCPRegInfo *opaque); 2722 2723 /* Return true if this reginfo struct's field in the cpu state struct 2724 * is 64 bits wide. 2725 */ 2726 static inline bool cpreg_field_is_64bit(const ARMCPRegInfo *ri) 2727 { 2728 return (ri->state == ARM_CP_STATE_AA64) || (ri->type & ARM_CP_64BIT); 2729 } 2730 2731 static inline bool cp_access_ok(int current_el, 2732 const ARMCPRegInfo *ri, int isread) 2733 { 2734 return (ri->access >> ((current_el * 2) + isread)) & 1; 2735 } 2736 2737 /* Raw read of a coprocessor register (as needed for migration, etc) */ 2738 uint64_t read_raw_cp_reg(CPUARMState *env, const ARMCPRegInfo *ri); 2739 2740 /** 2741 * write_list_to_cpustate 2742 * @cpu: ARMCPU 2743 * 2744 * For each register listed in the ARMCPU cpreg_indexes list, write 2745 * its value from the cpreg_values list into the ARMCPUState structure. 2746 * This updates TCG's working data structures from KVM data or 2747 * from incoming migration state. 2748 * 2749 * Returns: true if all register values were updated correctly, 2750 * false if some register was unknown or could not be written. 2751 * Note that we do not stop early on failure -- we will attempt 2752 * writing all registers in the list. 2753 */ 2754 bool write_list_to_cpustate(ARMCPU *cpu); 2755 2756 /** 2757 * write_cpustate_to_list: 2758 * @cpu: ARMCPU 2759 * @kvm_sync: true if this is for syncing back to KVM 2760 * 2761 * For each register listed in the ARMCPU cpreg_indexes list, write 2762 * its value from the ARMCPUState structure into the cpreg_values list. 2763 * This is used to copy info from TCG's working data structures into 2764 * KVM or for outbound migration. 2765 * 2766 * @kvm_sync is true if we are doing this in order to sync the 2767 * register state back to KVM. In this case we will only update 2768 * values in the list if the previous list->cpustate sync actually 2769 * successfully wrote the CPU state. Otherwise we will keep the value 2770 * that is in the list. 2771 * 2772 * Returns: true if all register values were read correctly, 2773 * false if some register was unknown or could not be read. 2774 * Note that we do not stop early on failure -- we will attempt 2775 * reading all registers in the list. 2776 */ 2777 bool write_cpustate_to_list(ARMCPU *cpu, bool kvm_sync); 2778 2779 #define ARM_CPUID_TI915T 0x54029152 2780 #define ARM_CPUID_TI925T 0x54029252 2781 2782 #define ARM_CPU_TYPE_SUFFIX "-" TYPE_ARM_CPU 2783 #define ARM_CPU_TYPE_NAME(name) (name ARM_CPU_TYPE_SUFFIX) 2784 #define CPU_RESOLVING_TYPE TYPE_ARM_CPU 2785 2786 #define cpu_signal_handler cpu_arm_signal_handler 2787 #define cpu_list arm_cpu_list 2788 2789 /* ARM has the following "translation regimes" (as the ARM ARM calls them): 2790 * 2791 * If EL3 is 64-bit: 2792 * + NonSecure EL1 & 0 stage 1 2793 * + NonSecure EL1 & 0 stage 2 2794 * + NonSecure EL2 2795 * + NonSecure EL2 & 0 (ARMv8.1-VHE) 2796 * + Secure EL1 & 0 2797 * + Secure EL3 2798 * If EL3 is 32-bit: 2799 * + NonSecure PL1 & 0 stage 1 2800 * + NonSecure PL1 & 0 stage 2 2801 * + NonSecure PL2 2802 * + Secure PL0 2803 * + Secure PL1 2804 * (reminder: for 32 bit EL3, Secure PL1 is *EL3*, not EL1.) 2805 * 2806 * For QEMU, an mmu_idx is not quite the same as a translation regime because: 2807 * 1. we need to split the "EL1 & 0" and "EL2 & 0" regimes into two mmu_idxes, 2808 * because they may differ in access permissions even if the VA->PA map is 2809 * the same 2810 * 2. we want to cache in our TLB the full VA->IPA->PA lookup for a stage 1+2 2811 * translation, which means that we have one mmu_idx that deals with two 2812 * concatenated translation regimes [this sort of combined s1+2 TLB is 2813 * architecturally permitted] 2814 * 3. we don't need to allocate an mmu_idx to translations that we won't be 2815 * handling via the TLB. The only way to do a stage 1 translation without 2816 * the immediate stage 2 translation is via the ATS or AT system insns, 2817 * which can be slow-pathed and always do a page table walk. 2818 * The only use of stage 2 translations is either as part of an s1+2 2819 * lookup or when loading the descriptors during a stage 1 page table walk, 2820 * and in both those cases we don't use the TLB. 2821 * 4. we can also safely fold together the "32 bit EL3" and "64 bit EL3" 2822 * translation regimes, because they map reasonably well to each other 2823 * and they can't both be active at the same time. 2824 * 5. we want to be able to use the TLB for accesses done as part of a 2825 * stage1 page table walk, rather than having to walk the stage2 page 2826 * table over and over. 2827 * 6. we need separate EL1/EL2 mmu_idx for handling the Privileged Access 2828 * Never (PAN) bit within PSTATE. 2829 * 2830 * This gives us the following list of cases: 2831 * 2832 * NS EL0 EL1&0 stage 1+2 (aka NS PL0) 2833 * NS EL1 EL1&0 stage 1+2 (aka NS PL1) 2834 * NS EL1 EL1&0 stage 1+2 +PAN 2835 * NS EL0 EL2&0 2836 * NS EL2 EL2&0 2837 * NS EL2 EL2&0 +PAN 2838 * NS EL2 (aka NS PL2) 2839 * S EL0 EL1&0 (aka S PL0) 2840 * S EL1 EL1&0 (not used if EL3 is 32 bit) 2841 * S EL1 EL1&0 +PAN 2842 * S EL3 (aka S PL1) 2843 * 2844 * for a total of 11 different mmu_idx. 2845 * 2846 * R profile CPUs have an MPU, but can use the same set of MMU indexes 2847 * as A profile. They only need to distinguish NS EL0 and NS EL1 (and 2848 * NS EL2 if we ever model a Cortex-R52). 2849 * 2850 * M profile CPUs are rather different as they do not have a true MMU. 2851 * They have the following different MMU indexes: 2852 * User 2853 * Privileged 2854 * User, execution priority negative (ie the MPU HFNMIENA bit may apply) 2855 * Privileged, execution priority negative (ditto) 2856 * If the CPU supports the v8M Security Extension then there are also: 2857 * Secure User 2858 * Secure Privileged 2859 * Secure User, execution priority negative 2860 * Secure Privileged, execution priority negative 2861 * 2862 * The ARMMMUIdx and the mmu index value used by the core QEMU TLB code 2863 * are not quite the same -- different CPU types (most notably M profile 2864 * vs A/R profile) would like to use MMU indexes with different semantics, 2865 * but since we don't ever need to use all of those in a single CPU we 2866 * can avoid having to set NB_MMU_MODES to "total number of A profile MMU 2867 * modes + total number of M profile MMU modes". The lower bits of 2868 * ARMMMUIdx are the core TLB mmu index, and the higher bits are always 2869 * the same for any particular CPU. 2870 * Variables of type ARMMUIdx are always full values, and the core 2871 * index values are in variables of type 'int'. 2872 * 2873 * Our enumeration includes at the end some entries which are not "true" 2874 * mmu_idx values in that they don't have corresponding TLBs and are only 2875 * valid for doing slow path page table walks. 2876 * 2877 * The constant names here are patterned after the general style of the names 2878 * of the AT/ATS operations. 2879 * The values used are carefully arranged to make mmu_idx => EL lookup easy. 2880 * For M profile we arrange them to have a bit for priv, a bit for negpri 2881 * and a bit for secure. 2882 */ 2883 #define ARM_MMU_IDX_A 0x10 /* A profile */ 2884 #define ARM_MMU_IDX_NOTLB 0x20 /* does not have a TLB */ 2885 #define ARM_MMU_IDX_M 0x40 /* M profile */ 2886 2887 /* Meanings of the bits for M profile mmu idx values */ 2888 #define ARM_MMU_IDX_M_PRIV 0x1 2889 #define ARM_MMU_IDX_M_NEGPRI 0x2 2890 #define ARM_MMU_IDX_M_S 0x4 /* Secure */ 2891 2892 #define ARM_MMU_IDX_TYPE_MASK \ 2893 (ARM_MMU_IDX_A | ARM_MMU_IDX_M | ARM_MMU_IDX_NOTLB) 2894 #define ARM_MMU_IDX_COREIDX_MASK 0xf 2895 2896 typedef enum ARMMMUIdx { 2897 /* 2898 * A-profile. 2899 */ 2900 ARMMMUIdx_E10_0 = 0 | ARM_MMU_IDX_A, 2901 ARMMMUIdx_E20_0 = 1 | ARM_MMU_IDX_A, 2902 2903 ARMMMUIdx_E10_1 = 2 | ARM_MMU_IDX_A, 2904 ARMMMUIdx_E10_1_PAN = 3 | ARM_MMU_IDX_A, 2905 2906 ARMMMUIdx_E2 = 4 | ARM_MMU_IDX_A, 2907 ARMMMUIdx_E20_2 = 5 | ARM_MMU_IDX_A, 2908 ARMMMUIdx_E20_2_PAN = 6 | ARM_MMU_IDX_A, 2909 2910 ARMMMUIdx_SE10_0 = 7 | ARM_MMU_IDX_A, 2911 ARMMMUIdx_SE10_1 = 8 | ARM_MMU_IDX_A, 2912 ARMMMUIdx_SE10_1_PAN = 9 | ARM_MMU_IDX_A, 2913 ARMMMUIdx_SE3 = 10 | ARM_MMU_IDX_A, 2914 2915 /* 2916 * These are not allocated TLBs and are used only for AT system 2917 * instructions or for the first stage of an S12 page table walk. 2918 */ 2919 ARMMMUIdx_Stage1_E0 = 0 | ARM_MMU_IDX_NOTLB, 2920 ARMMMUIdx_Stage1_E1 = 1 | ARM_MMU_IDX_NOTLB, 2921 ARMMMUIdx_Stage1_E1_PAN = 2 | ARM_MMU_IDX_NOTLB, 2922 /* 2923 * Not allocated a TLB: used only for second stage of an S12 page 2924 * table walk, or for descriptor loads during first stage of an S1 2925 * page table walk. Note that if we ever want to have a TLB for this 2926 * then various TLB flush insns which currently are no-ops or flush 2927 * only stage 1 MMU indexes will need to change to flush stage 2. 2928 */ 2929 ARMMMUIdx_Stage2 = 3 | ARM_MMU_IDX_NOTLB, 2930 2931 /* 2932 * M-profile. 2933 */ 2934 ARMMMUIdx_MUser = ARM_MMU_IDX_M, 2935 ARMMMUIdx_MPriv = ARM_MMU_IDX_M | ARM_MMU_IDX_M_PRIV, 2936 ARMMMUIdx_MUserNegPri = ARMMMUIdx_MUser | ARM_MMU_IDX_M_NEGPRI, 2937 ARMMMUIdx_MPrivNegPri = ARMMMUIdx_MPriv | ARM_MMU_IDX_M_NEGPRI, 2938 ARMMMUIdx_MSUser = ARMMMUIdx_MUser | ARM_MMU_IDX_M_S, 2939 ARMMMUIdx_MSPriv = ARMMMUIdx_MPriv | ARM_MMU_IDX_M_S, 2940 ARMMMUIdx_MSUserNegPri = ARMMMUIdx_MUserNegPri | ARM_MMU_IDX_M_S, 2941 ARMMMUIdx_MSPrivNegPri = ARMMMUIdx_MPrivNegPri | ARM_MMU_IDX_M_S, 2942 } ARMMMUIdx; 2943 2944 /* 2945 * Bit macros for the core-mmu-index values for each index, 2946 * for use when calling tlb_flush_by_mmuidx() and friends. 2947 */ 2948 #define TO_CORE_BIT(NAME) \ 2949 ARMMMUIdxBit_##NAME = 1 << (ARMMMUIdx_##NAME & ARM_MMU_IDX_COREIDX_MASK) 2950 2951 typedef enum ARMMMUIdxBit { 2952 TO_CORE_BIT(E10_0), 2953 TO_CORE_BIT(E20_0), 2954 TO_CORE_BIT(E10_1), 2955 TO_CORE_BIT(E10_1_PAN), 2956 TO_CORE_BIT(E2), 2957 TO_CORE_BIT(E20_2), 2958 TO_CORE_BIT(E20_2_PAN), 2959 TO_CORE_BIT(SE10_0), 2960 TO_CORE_BIT(SE10_1), 2961 TO_CORE_BIT(SE10_1_PAN), 2962 TO_CORE_BIT(SE3), 2963 2964 TO_CORE_BIT(MUser), 2965 TO_CORE_BIT(MPriv), 2966 TO_CORE_BIT(MUserNegPri), 2967 TO_CORE_BIT(MPrivNegPri), 2968 TO_CORE_BIT(MSUser), 2969 TO_CORE_BIT(MSPriv), 2970 TO_CORE_BIT(MSUserNegPri), 2971 TO_CORE_BIT(MSPrivNegPri), 2972 } ARMMMUIdxBit; 2973 2974 #undef TO_CORE_BIT 2975 2976 #define MMU_USER_IDX 0 2977 2978 /* Indexes used when registering address spaces with cpu_address_space_init */ 2979 typedef enum ARMASIdx { 2980 ARMASIdx_NS = 0, 2981 ARMASIdx_S = 1, 2982 } ARMASIdx; 2983 2984 /* Return the Exception Level targeted by debug exceptions. */ 2985 static inline int arm_debug_target_el(CPUARMState *env) 2986 { 2987 bool secure = arm_is_secure(env); 2988 bool route_to_el2 = false; 2989 2990 if (arm_feature(env, ARM_FEATURE_EL2) && !secure) { 2991 route_to_el2 = env->cp15.hcr_el2 & HCR_TGE || 2992 env->cp15.mdcr_el2 & MDCR_TDE; 2993 } 2994 2995 if (route_to_el2) { 2996 return 2; 2997 } else if (arm_feature(env, ARM_FEATURE_EL3) && 2998 !arm_el_is_aa64(env, 3) && secure) { 2999 return 3; 3000 } else { 3001 return 1; 3002 } 3003 } 3004 3005 static inline bool arm_v7m_csselr_razwi(ARMCPU *cpu) 3006 { 3007 /* If all the CLIDR.Ctypem bits are 0 there are no caches, and 3008 * CSSELR is RAZ/WI. 3009 */ 3010 return (cpu->clidr & R_V7M_CLIDR_CTYPE_ALL_MASK) != 0; 3011 } 3012 3013 /* See AArch64.GenerateDebugExceptionsFrom() in ARM ARM pseudocode */ 3014 static inline bool aa64_generate_debug_exceptions(CPUARMState *env) 3015 { 3016 int cur_el = arm_current_el(env); 3017 int debug_el; 3018 3019 if (cur_el == 3) { 3020 return false; 3021 } 3022 3023 /* MDCR_EL3.SDD disables debug events from Secure state */ 3024 if (arm_is_secure_below_el3(env) 3025 && extract32(env->cp15.mdcr_el3, 16, 1)) { 3026 return false; 3027 } 3028 3029 /* 3030 * Same EL to same EL debug exceptions need MDSCR_KDE enabled 3031 * while not masking the (D)ebug bit in DAIF. 3032 */ 3033 debug_el = arm_debug_target_el(env); 3034 3035 if (cur_el == debug_el) { 3036 return extract32(env->cp15.mdscr_el1, 13, 1) 3037 && !(env->daif & PSTATE_D); 3038 } 3039 3040 /* Otherwise the debug target needs to be a higher EL */ 3041 return debug_el > cur_el; 3042 } 3043 3044 static inline bool aa32_generate_debug_exceptions(CPUARMState *env) 3045 { 3046 int el = arm_current_el(env); 3047 3048 if (el == 0 && arm_el_is_aa64(env, 1)) { 3049 return aa64_generate_debug_exceptions(env); 3050 } 3051 3052 if (arm_is_secure(env)) { 3053 int spd; 3054 3055 if (el == 0 && (env->cp15.sder & 1)) { 3056 /* SDER.SUIDEN means debug exceptions from Secure EL0 3057 * are always enabled. Otherwise they are controlled by 3058 * SDCR.SPD like those from other Secure ELs. 3059 */ 3060 return true; 3061 } 3062 3063 spd = extract32(env->cp15.mdcr_el3, 14, 2); 3064 switch (spd) { 3065 case 1: 3066 /* SPD == 0b01 is reserved, but behaves as 0b00. */ 3067 case 0: 3068 /* For 0b00 we return true if external secure invasive debug 3069 * is enabled. On real hardware this is controlled by external 3070 * signals to the core. QEMU always permits debug, and behaves 3071 * as if DBGEN, SPIDEN, NIDEN and SPNIDEN are all tied high. 3072 */ 3073 return true; 3074 case 2: 3075 return false; 3076 case 3: 3077 return true; 3078 } 3079 } 3080 3081 return el != 2; 3082 } 3083 3084 /* Return true if debugging exceptions are currently enabled. 3085 * This corresponds to what in ARM ARM pseudocode would be 3086 * if UsingAArch32() then 3087 * return AArch32.GenerateDebugExceptions() 3088 * else 3089 * return AArch64.GenerateDebugExceptions() 3090 * We choose to push the if() down into this function for clarity, 3091 * since the pseudocode has it at all callsites except for the one in 3092 * CheckSoftwareStep(), where it is elided because both branches would 3093 * always return the same value. 3094 */ 3095 static inline bool arm_generate_debug_exceptions(CPUARMState *env) 3096 { 3097 if (env->aarch64) { 3098 return aa64_generate_debug_exceptions(env); 3099 } else { 3100 return aa32_generate_debug_exceptions(env); 3101 } 3102 } 3103 3104 /* Is single-stepping active? (Note that the "is EL_D AArch64?" check 3105 * implicitly means this always returns false in pre-v8 CPUs.) 3106 */ 3107 static inline bool arm_singlestep_active(CPUARMState *env) 3108 { 3109 return extract32(env->cp15.mdscr_el1, 0, 1) 3110 && arm_el_is_aa64(env, arm_debug_target_el(env)) 3111 && arm_generate_debug_exceptions(env); 3112 } 3113 3114 static inline bool arm_sctlr_b(CPUARMState *env) 3115 { 3116 return 3117 /* We need not implement SCTLR.ITD in user-mode emulation, so 3118 * let linux-user ignore the fact that it conflicts with SCTLR_B. 3119 * This lets people run BE32 binaries with "-cpu any". 3120 */ 3121 #ifndef CONFIG_USER_ONLY 3122 !arm_feature(env, ARM_FEATURE_V7) && 3123 #endif 3124 (env->cp15.sctlr_el[1] & SCTLR_B) != 0; 3125 } 3126 3127 uint64_t arm_sctlr(CPUARMState *env, int el); 3128 3129 static inline bool arm_cpu_data_is_big_endian_a32(CPUARMState *env, 3130 bool sctlr_b) 3131 { 3132 #ifdef CONFIG_USER_ONLY 3133 /* 3134 * In system mode, BE32 is modelled in line with the 3135 * architecture (as word-invariant big-endianness), where loads 3136 * and stores are done little endian but from addresses which 3137 * are adjusted by XORing with the appropriate constant. So the 3138 * endianness to use for the raw data access is not affected by 3139 * SCTLR.B. 3140 * In user mode, however, we model BE32 as byte-invariant 3141 * big-endianness (because user-only code cannot tell the 3142 * difference), and so we need to use a data access endianness 3143 * that depends on SCTLR.B. 3144 */ 3145 if (sctlr_b) { 3146 return true; 3147 } 3148 #endif 3149 /* In 32bit endianness is determined by looking at CPSR's E bit */ 3150 return env->uncached_cpsr & CPSR_E; 3151 } 3152 3153 static inline bool arm_cpu_data_is_big_endian_a64(int el, uint64_t sctlr) 3154 { 3155 return sctlr & (el ? SCTLR_EE : SCTLR_E0E); 3156 } 3157 3158 /* Return true if the processor is in big-endian mode. */ 3159 static inline bool arm_cpu_data_is_big_endian(CPUARMState *env) 3160 { 3161 if (!is_a64(env)) { 3162 return arm_cpu_data_is_big_endian_a32(env, arm_sctlr_b(env)); 3163 } else { 3164 int cur_el = arm_current_el(env); 3165 uint64_t sctlr = arm_sctlr(env, cur_el); 3166 return arm_cpu_data_is_big_endian_a64(cur_el, sctlr); 3167 } 3168 } 3169 3170 typedef CPUARMState CPUArchState; 3171 typedef ARMCPU ArchCPU; 3172 3173 #include "exec/cpu-all.h" 3174 3175 /* 3176 * Bit usage in the TB flags field: bit 31 indicates whether we are 3177 * in 32 or 64 bit mode. The meaning of the other bits depends on that. 3178 * We put flags which are shared between 32 and 64 bit mode at the top 3179 * of the word, and flags which apply to only one mode at the bottom. 3180 * 3181 * 31 20 18 14 9 0 3182 * +--------------+-----+-----+----------+--------------+ 3183 * | | | TBFLAG_A32 | | 3184 * | | +-----+----------+ TBFLAG_AM32 | 3185 * | TBFLAG_ANY | |TBFLAG_M32| | 3186 * | | +-+----------+--------------| 3187 * | | | TBFLAG_A64 | 3188 * +--------------+---------+---------------------------+ 3189 * 31 20 15 0 3190 * 3191 * Unless otherwise noted, these bits are cached in env->hflags. 3192 */ 3193 FIELD(TBFLAG_ANY, AARCH64_STATE, 31, 1) 3194 FIELD(TBFLAG_ANY, SS_ACTIVE, 30, 1) 3195 FIELD(TBFLAG_ANY, PSTATE_SS, 29, 1) /* Not cached. */ 3196 FIELD(TBFLAG_ANY, BE_DATA, 28, 1) 3197 FIELD(TBFLAG_ANY, MMUIDX, 24, 4) 3198 /* Target EL if we take a floating-point-disabled exception */ 3199 FIELD(TBFLAG_ANY, FPEXC_EL, 22, 2) 3200 /* For A-profile only, target EL for debug exceptions. */ 3201 FIELD(TBFLAG_ANY, DEBUG_TARGET_EL, 20, 2) 3202 3203 /* 3204 * Bit usage when in AArch32 state, both A- and M-profile. 3205 */ 3206 FIELD(TBFLAG_AM32, CONDEXEC, 0, 8) /* Not cached. */ 3207 FIELD(TBFLAG_AM32, THUMB, 8, 1) /* Not cached. */ 3208 3209 /* 3210 * Bit usage when in AArch32 state, for A-profile only. 3211 */ 3212 FIELD(TBFLAG_A32, VECLEN, 9, 3) /* Not cached. */ 3213 FIELD(TBFLAG_A32, VECSTRIDE, 12, 2) /* Not cached. */ 3214 /* 3215 * We store the bottom two bits of the CPAR as TB flags and handle 3216 * checks on the other bits at runtime. This shares the same bits as 3217 * VECSTRIDE, which is OK as no XScale CPU has VFP. 3218 * Not cached, because VECLEN+VECSTRIDE are not cached. 3219 */ 3220 FIELD(TBFLAG_A32, XSCALE_CPAR, 12, 2) 3221 FIELD(TBFLAG_A32, VFPEN, 14, 1) /* Partially cached, minus FPEXC. */ 3222 FIELD(TBFLAG_A32, SCTLR_B, 15, 1) 3223 FIELD(TBFLAG_A32, HSTR_ACTIVE, 16, 1) 3224 /* 3225 * Indicates whether cp register reads and writes by guest code should access 3226 * the secure or nonsecure bank of banked registers; note that this is not 3227 * the same thing as the current security state of the processor! 3228 */ 3229 FIELD(TBFLAG_A32, NS, 17, 1) 3230 3231 /* 3232 * Bit usage when in AArch32 state, for M-profile only. 3233 */ 3234 /* Handler (ie not Thread) mode */ 3235 FIELD(TBFLAG_M32, HANDLER, 9, 1) 3236 /* Whether we should generate stack-limit checks */ 3237 FIELD(TBFLAG_M32, STACKCHECK, 10, 1) 3238 /* Set if FPCCR.LSPACT is set */ 3239 FIELD(TBFLAG_M32, LSPACT, 11, 1) /* Not cached. */ 3240 /* Set if we must create a new FP context */ 3241 FIELD(TBFLAG_M32, NEW_FP_CTXT_NEEDED, 12, 1) /* Not cached. */ 3242 /* Set if FPCCR.S does not match current security state */ 3243 FIELD(TBFLAG_M32, FPCCR_S_WRONG, 13, 1) /* Not cached. */ 3244 3245 /* 3246 * Bit usage when in AArch64 state 3247 */ 3248 FIELD(TBFLAG_A64, TBII, 0, 2) 3249 FIELD(TBFLAG_A64, SVEEXC_EL, 2, 2) 3250 FIELD(TBFLAG_A64, ZCR_LEN, 4, 4) 3251 FIELD(TBFLAG_A64, PAUTH_ACTIVE, 8, 1) 3252 FIELD(TBFLAG_A64, BT, 9, 1) 3253 FIELD(TBFLAG_A64, BTYPE, 10, 2) /* Not cached. */ 3254 FIELD(TBFLAG_A64, TBID, 12, 2) 3255 FIELD(TBFLAG_A64, UNPRIV, 14, 1) 3256 3257 /** 3258 * cpu_mmu_index: 3259 * @env: The cpu environment 3260 * @ifetch: True for code access, false for data access. 3261 * 3262 * Return the core mmu index for the current translation regime. 3263 * This function is used by generic TCG code paths. 3264 */ 3265 static inline int cpu_mmu_index(CPUARMState *env, bool ifetch) 3266 { 3267 return FIELD_EX32(env->hflags, TBFLAG_ANY, MMUIDX); 3268 } 3269 3270 static inline bool bswap_code(bool sctlr_b) 3271 { 3272 #ifdef CONFIG_USER_ONLY 3273 /* BE8 (SCTLR.B = 0, TARGET_WORDS_BIGENDIAN = 1) is mixed endian. 3274 * The invalid combination SCTLR.B=1/CPSR.E=1/TARGET_WORDS_BIGENDIAN=0 3275 * would also end up as a mixed-endian mode with BE code, LE data. 3276 */ 3277 return 3278 #ifdef TARGET_WORDS_BIGENDIAN 3279 1 ^ 3280 #endif 3281 sctlr_b; 3282 #else 3283 /* All code access in ARM is little endian, and there are no loaders 3284 * doing swaps that need to be reversed 3285 */ 3286 return 0; 3287 #endif 3288 } 3289 3290 #ifdef CONFIG_USER_ONLY 3291 static inline bool arm_cpu_bswap_data(CPUARMState *env) 3292 { 3293 return 3294 #ifdef TARGET_WORDS_BIGENDIAN 3295 1 ^ 3296 #endif 3297 arm_cpu_data_is_big_endian(env); 3298 } 3299 #endif 3300 3301 void cpu_get_tb_cpu_state(CPUARMState *env, target_ulong *pc, 3302 target_ulong *cs_base, uint32_t *flags); 3303 3304 enum { 3305 QEMU_PSCI_CONDUIT_DISABLED = 0, 3306 QEMU_PSCI_CONDUIT_SMC = 1, 3307 QEMU_PSCI_CONDUIT_HVC = 2, 3308 }; 3309 3310 #ifndef CONFIG_USER_ONLY 3311 /* Return the address space index to use for a memory access */ 3312 static inline int arm_asidx_from_attrs(CPUState *cs, MemTxAttrs attrs) 3313 { 3314 return attrs.secure ? ARMASIdx_S : ARMASIdx_NS; 3315 } 3316 3317 /* Return the AddressSpace to use for a memory access 3318 * (which depends on whether the access is S or NS, and whether 3319 * the board gave us a separate AddressSpace for S accesses). 3320 */ 3321 static inline AddressSpace *arm_addressspace(CPUState *cs, MemTxAttrs attrs) 3322 { 3323 return cpu_get_address_space(cs, arm_asidx_from_attrs(cs, attrs)); 3324 } 3325 #endif 3326 3327 /** 3328 * arm_register_pre_el_change_hook: 3329 * Register a hook function which will be called immediately before this 3330 * CPU changes exception level or mode. The hook function will be 3331 * passed a pointer to the ARMCPU and the opaque data pointer passed 3332 * to this function when the hook was registered. 3333 * 3334 * Note that if a pre-change hook is called, any registered post-change hooks 3335 * are guaranteed to subsequently be called. 3336 */ 3337 void arm_register_pre_el_change_hook(ARMCPU *cpu, ARMELChangeHookFn *hook, 3338 void *opaque); 3339 /** 3340 * arm_register_el_change_hook: 3341 * Register a hook function which will be called immediately after this 3342 * CPU changes exception level or mode. The hook function will be 3343 * passed a pointer to the ARMCPU and the opaque data pointer passed 3344 * to this function when the hook was registered. 3345 * 3346 * Note that any registered hooks registered here are guaranteed to be called 3347 * if pre-change hooks have been. 3348 */ 3349 void arm_register_el_change_hook(ARMCPU *cpu, ARMELChangeHookFn *hook, void 3350 *opaque); 3351 3352 /** 3353 * arm_rebuild_hflags: 3354 * Rebuild the cached TBFLAGS for arbitrary changed processor state. 3355 */ 3356 void arm_rebuild_hflags(CPUARMState *env); 3357 3358 /** 3359 * aa32_vfp_dreg: 3360 * Return a pointer to the Dn register within env in 32-bit mode. 3361 */ 3362 static inline uint64_t *aa32_vfp_dreg(CPUARMState *env, unsigned regno) 3363 { 3364 return &env->vfp.zregs[regno >> 1].d[regno & 1]; 3365 } 3366 3367 /** 3368 * aa32_vfp_qreg: 3369 * Return a pointer to the Qn register within env in 32-bit mode. 3370 */ 3371 static inline uint64_t *aa32_vfp_qreg(CPUARMState *env, unsigned regno) 3372 { 3373 return &env->vfp.zregs[regno].d[0]; 3374 } 3375 3376 /** 3377 * aa64_vfp_qreg: 3378 * Return a pointer to the Qn register within env in 64-bit mode. 3379 */ 3380 static inline uint64_t *aa64_vfp_qreg(CPUARMState *env, unsigned regno) 3381 { 3382 return &env->vfp.zregs[regno].d[0]; 3383 } 3384 3385 /* Shared between translate-sve.c and sve_helper.c. */ 3386 extern const uint64_t pred_esz_masks[4]; 3387 3388 /* 3389 * Naming convention for isar_feature functions: 3390 * Functions which test 32-bit ID registers should have _aa32_ in 3391 * their name. Functions which test 64-bit ID registers should have 3392 * _aa64_ in their name. These must only be used in code where we 3393 * know for certain that the CPU has AArch32 or AArch64 respectively 3394 * or where the correct answer for a CPU which doesn't implement that 3395 * CPU state is "false" (eg when generating A32 or A64 code, if adding 3396 * system registers that are specific to that CPU state, for "should 3397 * we let this system register bit be set" tests where the 32-bit 3398 * flavour of the register doesn't have the bit, and so on). 3399 * Functions which simply ask "does this feature exist at all" have 3400 * _any_ in their name, and always return the logical OR of the _aa64_ 3401 * and the _aa32_ function. 3402 */ 3403 3404 /* 3405 * 32-bit feature tests via id registers. 3406 */ 3407 static inline bool isar_feature_aa32_thumb_div(const ARMISARegisters *id) 3408 { 3409 return FIELD_EX32(id->id_isar0, ID_ISAR0, DIVIDE) != 0; 3410 } 3411 3412 static inline bool isar_feature_aa32_arm_div(const ARMISARegisters *id) 3413 { 3414 return FIELD_EX32(id->id_isar0, ID_ISAR0, DIVIDE) > 1; 3415 } 3416 3417 static inline bool isar_feature_aa32_jazelle(const ARMISARegisters *id) 3418 { 3419 return FIELD_EX32(id->id_isar1, ID_ISAR1, JAZELLE) != 0; 3420 } 3421 3422 static inline bool isar_feature_aa32_aes(const ARMISARegisters *id) 3423 { 3424 return FIELD_EX32(id->id_isar5, ID_ISAR5, AES) != 0; 3425 } 3426 3427 static inline bool isar_feature_aa32_pmull(const ARMISARegisters *id) 3428 { 3429 return FIELD_EX32(id->id_isar5, ID_ISAR5, AES) > 1; 3430 } 3431 3432 static inline bool isar_feature_aa32_sha1(const ARMISARegisters *id) 3433 { 3434 return FIELD_EX32(id->id_isar5, ID_ISAR5, SHA1) != 0; 3435 } 3436 3437 static inline bool isar_feature_aa32_sha2(const ARMISARegisters *id) 3438 { 3439 return FIELD_EX32(id->id_isar5, ID_ISAR5, SHA2) != 0; 3440 } 3441 3442 static inline bool isar_feature_aa32_crc32(const ARMISARegisters *id) 3443 { 3444 return FIELD_EX32(id->id_isar5, ID_ISAR5, CRC32) != 0; 3445 } 3446 3447 static inline bool isar_feature_aa32_rdm(const ARMISARegisters *id) 3448 { 3449 return FIELD_EX32(id->id_isar5, ID_ISAR5, RDM) != 0; 3450 } 3451 3452 static inline bool isar_feature_aa32_vcma(const ARMISARegisters *id) 3453 { 3454 return FIELD_EX32(id->id_isar5, ID_ISAR5, VCMA) != 0; 3455 } 3456 3457 static inline bool isar_feature_aa32_jscvt(const ARMISARegisters *id) 3458 { 3459 return FIELD_EX32(id->id_isar6, ID_ISAR6, JSCVT) != 0; 3460 } 3461 3462 static inline bool isar_feature_aa32_dp(const ARMISARegisters *id) 3463 { 3464 return FIELD_EX32(id->id_isar6, ID_ISAR6, DP) != 0; 3465 } 3466 3467 static inline bool isar_feature_aa32_fhm(const ARMISARegisters *id) 3468 { 3469 return FIELD_EX32(id->id_isar6, ID_ISAR6, FHM) != 0; 3470 } 3471 3472 static inline bool isar_feature_aa32_sb(const ARMISARegisters *id) 3473 { 3474 return FIELD_EX32(id->id_isar6, ID_ISAR6, SB) != 0; 3475 } 3476 3477 static inline bool isar_feature_aa32_predinv(const ARMISARegisters *id) 3478 { 3479 return FIELD_EX32(id->id_isar6, ID_ISAR6, SPECRES) != 0; 3480 } 3481 3482 static inline bool isar_feature_aa32_fp16_arith(const ARMISARegisters *id) 3483 { 3484 /* 3485 * This is a placeholder for use by VCMA until the rest of 3486 * the ARMv8.2-FP16 extension is implemented for aa32 mode. 3487 * At which point we can properly set and check MVFR1.FPHP. 3488 */ 3489 return FIELD_EX64(id->id_aa64pfr0, ID_AA64PFR0, FP) == 1; 3490 } 3491 3492 static inline bool isar_feature_aa32_vfp_simd(const ARMISARegisters *id) 3493 { 3494 /* 3495 * Return true if either VFP or SIMD is implemented. 3496 * In this case, a minimum of VFP w/ D0-D15. 3497 */ 3498 return FIELD_EX32(id->mvfr0, MVFR0, SIMDREG) > 0; 3499 } 3500 3501 static inline bool isar_feature_aa32_simd_r32(const ARMISARegisters *id) 3502 { 3503 /* Return true if D16-D31 are implemented */ 3504 return FIELD_EX32(id->mvfr0, MVFR0, SIMDREG) >= 2; 3505 } 3506 3507 static inline bool isar_feature_aa32_fpshvec(const ARMISARegisters *id) 3508 { 3509 return FIELD_EX32(id->mvfr0, MVFR0, FPSHVEC) > 0; 3510 } 3511 3512 static inline bool isar_feature_aa32_fpsp_v2(const ARMISARegisters *id) 3513 { 3514 /* Return true if CPU supports single precision floating point, VFPv2 */ 3515 return FIELD_EX32(id->mvfr0, MVFR0, FPSP) > 0; 3516 } 3517 3518 static inline bool isar_feature_aa32_fpsp_v3(const ARMISARegisters *id) 3519 { 3520 /* Return true if CPU supports single precision floating point, VFPv3 */ 3521 return FIELD_EX32(id->mvfr0, MVFR0, FPSP) >= 2; 3522 } 3523 3524 static inline bool isar_feature_aa32_fpdp_v2(const ARMISARegisters *id) 3525 { 3526 /* Return true if CPU supports double precision floating point, VFPv2 */ 3527 return FIELD_EX32(id->mvfr0, MVFR0, FPDP) > 0; 3528 } 3529 3530 static inline bool isar_feature_aa32_fpdp_v3(const ARMISARegisters *id) 3531 { 3532 /* Return true if CPU supports double precision floating point, VFPv3 */ 3533 return FIELD_EX32(id->mvfr0, MVFR0, FPDP) >= 2; 3534 } 3535 3536 static inline bool isar_feature_aa32_vfp(const ARMISARegisters *id) 3537 { 3538 return isar_feature_aa32_fpsp_v2(id) || isar_feature_aa32_fpdp_v2(id); 3539 } 3540 3541 /* 3542 * We always set the FP and SIMD FP16 fields to indicate identical 3543 * levels of support (assuming SIMD is implemented at all), so 3544 * we only need one set of accessors. 3545 */ 3546 static inline bool isar_feature_aa32_fp16_spconv(const ARMISARegisters *id) 3547 { 3548 return FIELD_EX32(id->mvfr1, MVFR1, FPHP) > 0; 3549 } 3550 3551 static inline bool isar_feature_aa32_fp16_dpconv(const ARMISARegisters *id) 3552 { 3553 return FIELD_EX32(id->mvfr1, MVFR1, FPHP) > 1; 3554 } 3555 3556 /* 3557 * Note that this ID register field covers both VFP and Neon FMAC, 3558 * so should usually be tested in combination with some other 3559 * check that confirms the presence of whichever of VFP or Neon is 3560 * relevant, to avoid accidentally enabling a Neon feature on 3561 * a VFP-no-Neon core or vice-versa. 3562 */ 3563 static inline bool isar_feature_aa32_simdfmac(const ARMISARegisters *id) 3564 { 3565 return FIELD_EX32(id->mvfr1, MVFR1, SIMDFMAC) != 0; 3566 } 3567 3568 static inline bool isar_feature_aa32_vsel(const ARMISARegisters *id) 3569 { 3570 return FIELD_EX32(id->mvfr2, MVFR2, FPMISC) >= 1; 3571 } 3572 3573 static inline bool isar_feature_aa32_vcvt_dr(const ARMISARegisters *id) 3574 { 3575 return FIELD_EX32(id->mvfr2, MVFR2, FPMISC) >= 2; 3576 } 3577 3578 static inline bool isar_feature_aa32_vrint(const ARMISARegisters *id) 3579 { 3580 return FIELD_EX32(id->mvfr2, MVFR2, FPMISC) >= 3; 3581 } 3582 3583 static inline bool isar_feature_aa32_vminmaxnm(const ARMISARegisters *id) 3584 { 3585 return FIELD_EX32(id->mvfr2, MVFR2, FPMISC) >= 4; 3586 } 3587 3588 static inline bool isar_feature_aa32_pan(const ARMISARegisters *id) 3589 { 3590 return FIELD_EX32(id->id_mmfr3, ID_MMFR3, PAN) != 0; 3591 } 3592 3593 static inline bool isar_feature_aa32_ats1e1(const ARMISARegisters *id) 3594 { 3595 return FIELD_EX32(id->id_mmfr3, ID_MMFR3, PAN) >= 2; 3596 } 3597 3598 static inline bool isar_feature_aa32_pmu_8_1(const ARMISARegisters *id) 3599 { 3600 /* 0xf means "non-standard IMPDEF PMU" */ 3601 return FIELD_EX32(id->id_dfr0, ID_DFR0, PERFMON) >= 4 && 3602 FIELD_EX32(id->id_dfr0, ID_DFR0, PERFMON) != 0xf; 3603 } 3604 3605 static inline bool isar_feature_aa32_pmu_8_4(const ARMISARegisters *id) 3606 { 3607 /* 0xf means "non-standard IMPDEF PMU" */ 3608 return FIELD_EX32(id->id_dfr0, ID_DFR0, PERFMON) >= 5 && 3609 FIELD_EX32(id->id_dfr0, ID_DFR0, PERFMON) != 0xf; 3610 } 3611 3612 static inline bool isar_feature_aa32_hpd(const ARMISARegisters *id) 3613 { 3614 return FIELD_EX32(id->id_mmfr4, ID_MMFR4, HPDS) != 0; 3615 } 3616 3617 static inline bool isar_feature_aa32_ac2(const ARMISARegisters *id) 3618 { 3619 return FIELD_EX32(id->id_mmfr4, ID_MMFR4, AC2) != 0; 3620 } 3621 3622 static inline bool isar_feature_aa32_ccidx(const ARMISARegisters *id) 3623 { 3624 return FIELD_EX32(id->id_mmfr4, ID_MMFR4, CCIDX) != 0; 3625 } 3626 3627 static inline bool isar_feature_aa32_tts2uxn(const ARMISARegisters *id) 3628 { 3629 return FIELD_EX32(id->id_mmfr4, ID_MMFR4, XNX) != 0; 3630 } 3631 3632 /* 3633 * 64-bit feature tests via id registers. 3634 */ 3635 static inline bool isar_feature_aa64_aes(const ARMISARegisters *id) 3636 { 3637 return FIELD_EX64(id->id_aa64isar0, ID_AA64ISAR0, AES) != 0; 3638 } 3639 3640 static inline bool isar_feature_aa64_pmull(const ARMISARegisters *id) 3641 { 3642 return FIELD_EX64(id->id_aa64isar0, ID_AA64ISAR0, AES) > 1; 3643 } 3644 3645 static inline bool isar_feature_aa64_sha1(const ARMISARegisters *id) 3646 { 3647 return FIELD_EX64(id->id_aa64isar0, ID_AA64ISAR0, SHA1) != 0; 3648 } 3649 3650 static inline bool isar_feature_aa64_sha256(const ARMISARegisters *id) 3651 { 3652 return FIELD_EX64(id->id_aa64isar0, ID_AA64ISAR0, SHA2) != 0; 3653 } 3654 3655 static inline bool isar_feature_aa64_sha512(const ARMISARegisters *id) 3656 { 3657 return FIELD_EX64(id->id_aa64isar0, ID_AA64ISAR0, SHA2) > 1; 3658 } 3659 3660 static inline bool isar_feature_aa64_crc32(const ARMISARegisters *id) 3661 { 3662 return FIELD_EX64(id->id_aa64isar0, ID_AA64ISAR0, CRC32) != 0; 3663 } 3664 3665 static inline bool isar_feature_aa64_atomics(const ARMISARegisters *id) 3666 { 3667 return FIELD_EX64(id->id_aa64isar0, ID_AA64ISAR0, ATOMIC) != 0; 3668 } 3669 3670 static inline bool isar_feature_aa64_rdm(const ARMISARegisters *id) 3671 { 3672 return FIELD_EX64(id->id_aa64isar0, ID_AA64ISAR0, RDM) != 0; 3673 } 3674 3675 static inline bool isar_feature_aa64_sha3(const ARMISARegisters *id) 3676 { 3677 return FIELD_EX64(id->id_aa64isar0, ID_AA64ISAR0, SHA3) != 0; 3678 } 3679 3680 static inline bool isar_feature_aa64_sm3(const ARMISARegisters *id) 3681 { 3682 return FIELD_EX64(id->id_aa64isar0, ID_AA64ISAR0, SM3) != 0; 3683 } 3684 3685 static inline bool isar_feature_aa64_sm4(const ARMISARegisters *id) 3686 { 3687 return FIELD_EX64(id->id_aa64isar0, ID_AA64ISAR0, SM4) != 0; 3688 } 3689 3690 static inline bool isar_feature_aa64_dp(const ARMISARegisters *id) 3691 { 3692 return FIELD_EX64(id->id_aa64isar0, ID_AA64ISAR0, DP) != 0; 3693 } 3694 3695 static inline bool isar_feature_aa64_fhm(const ARMISARegisters *id) 3696 { 3697 return FIELD_EX64(id->id_aa64isar0, ID_AA64ISAR0, FHM) != 0; 3698 } 3699 3700 static inline bool isar_feature_aa64_condm_4(const ARMISARegisters *id) 3701 { 3702 return FIELD_EX64(id->id_aa64isar0, ID_AA64ISAR0, TS) != 0; 3703 } 3704 3705 static inline bool isar_feature_aa64_condm_5(const ARMISARegisters *id) 3706 { 3707 return FIELD_EX64(id->id_aa64isar0, ID_AA64ISAR0, TS) >= 2; 3708 } 3709 3710 static inline bool isar_feature_aa64_rndr(const ARMISARegisters *id) 3711 { 3712 return FIELD_EX64(id->id_aa64isar0, ID_AA64ISAR0, RNDR) != 0; 3713 } 3714 3715 static inline bool isar_feature_aa64_jscvt(const ARMISARegisters *id) 3716 { 3717 return FIELD_EX64(id->id_aa64isar1, ID_AA64ISAR1, JSCVT) != 0; 3718 } 3719 3720 static inline bool isar_feature_aa64_fcma(const ARMISARegisters *id) 3721 { 3722 return FIELD_EX64(id->id_aa64isar1, ID_AA64ISAR1, FCMA) != 0; 3723 } 3724 3725 static inline bool isar_feature_aa64_pauth(const ARMISARegisters *id) 3726 { 3727 /* 3728 * Note that while QEMU will only implement the architected algorithm 3729 * QARMA, and thus APA+GPA, the host cpu for kvm may use implementation 3730 * defined algorithms, and thus API+GPI, and this predicate controls 3731 * migration of the 128-bit keys. 3732 */ 3733 return (id->id_aa64isar1 & 3734 (FIELD_DP64(0, ID_AA64ISAR1, APA, 0xf) | 3735 FIELD_DP64(0, ID_AA64ISAR1, API, 0xf) | 3736 FIELD_DP64(0, ID_AA64ISAR1, GPA, 0xf) | 3737 FIELD_DP64(0, ID_AA64ISAR1, GPI, 0xf))) != 0; 3738 } 3739 3740 static inline bool isar_feature_aa64_sb(const ARMISARegisters *id) 3741 { 3742 return FIELD_EX64(id->id_aa64isar1, ID_AA64ISAR1, SB) != 0; 3743 } 3744 3745 static inline bool isar_feature_aa64_predinv(const ARMISARegisters *id) 3746 { 3747 return FIELD_EX64(id->id_aa64isar1, ID_AA64ISAR1, SPECRES) != 0; 3748 } 3749 3750 static inline bool isar_feature_aa64_frint(const ARMISARegisters *id) 3751 { 3752 return FIELD_EX64(id->id_aa64isar1, ID_AA64ISAR1, FRINTTS) != 0; 3753 } 3754 3755 static inline bool isar_feature_aa64_dcpop(const ARMISARegisters *id) 3756 { 3757 return FIELD_EX64(id->id_aa64isar1, ID_AA64ISAR1, DPB) != 0; 3758 } 3759 3760 static inline bool isar_feature_aa64_dcpodp(const ARMISARegisters *id) 3761 { 3762 return FIELD_EX64(id->id_aa64isar1, ID_AA64ISAR1, DPB) >= 2; 3763 } 3764 3765 static inline bool isar_feature_aa64_fp_simd(const ARMISARegisters *id) 3766 { 3767 /* We always set the AdvSIMD and FP fields identically. */ 3768 return FIELD_EX64(id->id_aa64pfr0, ID_AA64PFR0, FP) != 0xf; 3769 } 3770 3771 static inline bool isar_feature_aa64_fp16(const ARMISARegisters *id) 3772 { 3773 /* We always set the AdvSIMD and FP fields identically wrt FP16. */ 3774 return FIELD_EX64(id->id_aa64pfr0, ID_AA64PFR0, FP) == 1; 3775 } 3776 3777 static inline bool isar_feature_aa64_aa32(const ARMISARegisters *id) 3778 { 3779 return FIELD_EX64(id->id_aa64pfr0, ID_AA64PFR0, EL0) >= 2; 3780 } 3781 3782 static inline bool isar_feature_aa64_sve(const ARMISARegisters *id) 3783 { 3784 return FIELD_EX64(id->id_aa64pfr0, ID_AA64PFR0, SVE) != 0; 3785 } 3786 3787 static inline bool isar_feature_aa64_vh(const ARMISARegisters *id) 3788 { 3789 return FIELD_EX64(id->id_aa64mmfr1, ID_AA64MMFR1, VH) != 0; 3790 } 3791 3792 static inline bool isar_feature_aa64_lor(const ARMISARegisters *id) 3793 { 3794 return FIELD_EX64(id->id_aa64mmfr1, ID_AA64MMFR1, LO) != 0; 3795 } 3796 3797 static inline bool isar_feature_aa64_pan(const ARMISARegisters *id) 3798 { 3799 return FIELD_EX64(id->id_aa64mmfr1, ID_AA64MMFR1, PAN) != 0; 3800 } 3801 3802 static inline bool isar_feature_aa64_ats1e1(const ARMISARegisters *id) 3803 { 3804 return FIELD_EX64(id->id_aa64mmfr1, ID_AA64MMFR1, PAN) >= 2; 3805 } 3806 3807 static inline bool isar_feature_aa64_uao(const ARMISARegisters *id) 3808 { 3809 return FIELD_EX64(id->id_aa64mmfr2, ID_AA64MMFR2, UAO) != 0; 3810 } 3811 3812 static inline bool isar_feature_aa64_bti(const ARMISARegisters *id) 3813 { 3814 return FIELD_EX64(id->id_aa64pfr1, ID_AA64PFR1, BT) != 0; 3815 } 3816 3817 static inline bool isar_feature_aa64_pmu_8_1(const ARMISARegisters *id) 3818 { 3819 return FIELD_EX64(id->id_aa64dfr0, ID_AA64DFR0, PMUVER) >= 4 && 3820 FIELD_EX64(id->id_aa64dfr0, ID_AA64DFR0, PMUVER) != 0xf; 3821 } 3822 3823 static inline bool isar_feature_aa64_pmu_8_4(const ARMISARegisters *id) 3824 { 3825 return FIELD_EX64(id->id_aa64dfr0, ID_AA64DFR0, PMUVER) >= 5 && 3826 FIELD_EX64(id->id_aa64dfr0, ID_AA64DFR0, PMUVER) != 0xf; 3827 } 3828 3829 static inline bool isar_feature_aa64_rcpc_8_3(const ARMISARegisters *id) 3830 { 3831 return FIELD_EX64(id->id_aa64isar1, ID_AA64ISAR1, LRCPC) != 0; 3832 } 3833 3834 static inline bool isar_feature_aa64_rcpc_8_4(const ARMISARegisters *id) 3835 { 3836 return FIELD_EX64(id->id_aa64isar1, ID_AA64ISAR1, LRCPC) >= 2; 3837 } 3838 3839 static inline bool isar_feature_aa64_ccidx(const ARMISARegisters *id) 3840 { 3841 return FIELD_EX64(id->id_aa64mmfr2, ID_AA64MMFR2, CCIDX) != 0; 3842 } 3843 3844 static inline bool isar_feature_aa64_tts2uxn(const ARMISARegisters *id) 3845 { 3846 return FIELD_EX64(id->id_aa64mmfr1, ID_AA64MMFR1, XNX) != 0; 3847 } 3848 3849 /* 3850 * Feature tests for "does this exist in either 32-bit or 64-bit?" 3851 */ 3852 static inline bool isar_feature_any_fp16(const ARMISARegisters *id) 3853 { 3854 return isar_feature_aa64_fp16(id) || isar_feature_aa32_fp16_arith(id); 3855 } 3856 3857 static inline bool isar_feature_any_predinv(const ARMISARegisters *id) 3858 { 3859 return isar_feature_aa64_predinv(id) || isar_feature_aa32_predinv(id); 3860 } 3861 3862 static inline bool isar_feature_any_pmu_8_1(const ARMISARegisters *id) 3863 { 3864 return isar_feature_aa64_pmu_8_1(id) || isar_feature_aa32_pmu_8_1(id); 3865 } 3866 3867 static inline bool isar_feature_any_pmu_8_4(const ARMISARegisters *id) 3868 { 3869 return isar_feature_aa64_pmu_8_4(id) || isar_feature_aa32_pmu_8_4(id); 3870 } 3871 3872 static inline bool isar_feature_any_ccidx(const ARMISARegisters *id) 3873 { 3874 return isar_feature_aa64_ccidx(id) || isar_feature_aa32_ccidx(id); 3875 } 3876 3877 static inline bool isar_feature_any_tts2uxn(const ARMISARegisters *id) 3878 { 3879 return isar_feature_aa64_tts2uxn(id) || isar_feature_aa32_tts2uxn(id); 3880 } 3881 3882 /* 3883 * Forward to the above feature tests given an ARMCPU pointer. 3884 */ 3885 #define cpu_isar_feature(name, cpu) \ 3886 ({ ARMCPU *cpu_ = (cpu); isar_feature_##name(&cpu_->isar); }) 3887 3888 #endif 3889