1 /* 2 * ARM virtual CPU header 3 * 4 * Copyright (c) 2003 Fabrice Bellard 5 * 6 * This library is free software; you can redistribute it and/or 7 * modify it under the terms of the GNU Lesser General Public 8 * License as published by the Free Software Foundation; either 9 * version 2.1 of the License, or (at your option) any later version. 10 * 11 * This library is distributed in the hope that it will be useful, 12 * but WITHOUT ANY WARRANTY; without even the implied warranty of 13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU 14 * Lesser General Public License for more details. 15 * 16 * You should have received a copy of the GNU Lesser General Public 17 * License along with this library; if not, see <http://www.gnu.org/licenses/>. 18 */ 19 20 #ifndef ARM_CPU_H 21 #define ARM_CPU_H 22 23 #include "kvm-consts.h" 24 #include "qemu/cpu-float.h" 25 #include "hw/registerfields.h" 26 #include "cpu-qom.h" 27 #include "exec/cpu-defs.h" 28 #include "exec/gdbstub.h" 29 #include "exec/page-protection.h" 30 #include "qapi/qapi-types-common.h" 31 #include "target/arm/multiprocessing.h" 32 #include "target/arm/gtimer.h" 33 34 #ifdef TARGET_AARCH64 35 #define KVM_HAVE_MCE_INJECTION 1 36 #endif 37 38 #define EXCP_UDEF 1 /* undefined instruction */ 39 #define EXCP_SWI 2 /* software interrupt */ 40 #define EXCP_PREFETCH_ABORT 3 41 #define EXCP_DATA_ABORT 4 42 #define EXCP_IRQ 5 43 #define EXCP_FIQ 6 44 #define EXCP_BKPT 7 45 #define EXCP_EXCEPTION_EXIT 8 /* Return from v7M exception. */ 46 #define EXCP_KERNEL_TRAP 9 /* Jumped to kernel code page. */ 47 #define EXCP_HVC 11 /* HyperVisor Call */ 48 #define EXCP_HYP_TRAP 12 49 #define EXCP_SMC 13 /* Secure Monitor Call */ 50 #define EXCP_VIRQ 14 51 #define EXCP_VFIQ 15 52 #define EXCP_SEMIHOST 16 /* semihosting call */ 53 #define EXCP_NOCP 17 /* v7M NOCP UsageFault */ 54 #define EXCP_INVSTATE 18 /* v7M INVSTATE UsageFault */ 55 #define EXCP_STKOF 19 /* v8M STKOF UsageFault */ 56 #define EXCP_LAZYFP 20 /* v7M fault during lazy FP stacking */ 57 #define EXCP_LSERR 21 /* v8M LSERR SecureFault */ 58 #define EXCP_UNALIGNED 22 /* v7M UNALIGNED UsageFault */ 59 #define EXCP_DIVBYZERO 23 /* v7M DIVBYZERO UsageFault */ 60 #define EXCP_VSERR 24 61 #define EXCP_GPC 25 /* v9 Granule Protection Check Fault */ 62 #define EXCP_NMI 26 63 #define EXCP_VINMI 27 64 #define EXCP_VFNMI 28 65 /* NB: add new EXCP_ defines to the array in arm_log_exception() too */ 66 67 #define ARMV7M_EXCP_RESET 1 68 #define ARMV7M_EXCP_NMI 2 69 #define ARMV7M_EXCP_HARD 3 70 #define ARMV7M_EXCP_MEM 4 71 #define ARMV7M_EXCP_BUS 5 72 #define ARMV7M_EXCP_USAGE 6 73 #define ARMV7M_EXCP_SECURE 7 74 #define ARMV7M_EXCP_SVC 11 75 #define ARMV7M_EXCP_DEBUG 12 76 #define ARMV7M_EXCP_PENDSV 14 77 #define ARMV7M_EXCP_SYSTICK 15 78 79 /* ARM-specific interrupt pending bits. */ 80 #define CPU_INTERRUPT_FIQ CPU_INTERRUPT_TGT_EXT_1 81 #define CPU_INTERRUPT_VIRQ CPU_INTERRUPT_TGT_EXT_2 82 #define CPU_INTERRUPT_VFIQ CPU_INTERRUPT_TGT_EXT_3 83 #define CPU_INTERRUPT_VSERR CPU_INTERRUPT_TGT_INT_0 84 #define CPU_INTERRUPT_NMI CPU_INTERRUPT_TGT_EXT_4 85 #define CPU_INTERRUPT_VINMI CPU_INTERRUPT_TGT_EXT_0 86 #define CPU_INTERRUPT_VFNMI CPU_INTERRUPT_TGT_INT_1 87 88 /* The usual mapping for an AArch64 system register to its AArch32 89 * counterpart is for the 32 bit world to have access to the lower 90 * half only (with writes leaving the upper half untouched). It's 91 * therefore useful to be able to pass TCG the offset of the least 92 * significant half of a uint64_t struct member. 93 */ 94 #if HOST_BIG_ENDIAN 95 #define offsetoflow32(S, M) (offsetof(S, M) + sizeof(uint32_t)) 96 #define offsetofhigh32(S, M) offsetof(S, M) 97 #else 98 #define offsetoflow32(S, M) offsetof(S, M) 99 #define offsetofhigh32(S, M) (offsetof(S, M) + sizeof(uint32_t)) 100 #endif 101 102 /* ARM-specific extra insn start words: 103 * 1: Conditional execution bits 104 * 2: Partial exception syndrome for data aborts 105 */ 106 #define TARGET_INSN_START_EXTRA_WORDS 2 107 108 /* The 2nd extra word holding syndrome info for data aborts does not use 109 * the upper 6 bits nor the lower 13 bits. We mask and shift it down to 110 * help the sleb128 encoder do a better job. 111 * When restoring the CPU state, we shift it back up. 112 */ 113 #define ARM_INSN_START_WORD2_MASK ((1 << 26) - 1) 114 #define ARM_INSN_START_WORD2_SHIFT 13 115 116 /* We currently assume float and double are IEEE single and double 117 precision respectively. 118 Doing runtime conversions is tricky because VFP registers may contain 119 integer values (eg. as the result of a FTOSI instruction). 120 s<2n> maps to the least significant half of d<n> 121 s<2n+1> maps to the most significant half of d<n> 122 */ 123 124 /** 125 * DynamicGDBFeatureInfo: 126 * @desc: Contains the feature descriptions. 127 * @data: A union with data specific to the set of registers 128 * @cpregs_keys: Array that contains the corresponding Key of 129 * a given cpreg with the same order of the cpreg 130 * in the XML description. 131 */ 132 typedef struct DynamicGDBFeatureInfo { 133 GDBFeature desc; 134 union { 135 struct { 136 uint32_t *keys; 137 } cpregs; 138 } data; 139 } DynamicGDBFeatureInfo; 140 141 /* CPU state for each instance of a generic timer (in cp15 c14) */ 142 typedef struct ARMGenericTimer { 143 uint64_t cval; /* Timer CompareValue register */ 144 uint64_t ctl; /* Timer Control register */ 145 } ARMGenericTimer; 146 147 /* Define a maximum sized vector register. 148 * For 32-bit, this is a 128-bit NEON/AdvSIMD register. 149 * For 64-bit, this is a 2048-bit SVE register. 150 * 151 * Note that the mapping between S, D, and Q views of the register bank 152 * differs between AArch64 and AArch32. 153 * In AArch32: 154 * Qn = regs[n].d[1]:regs[n].d[0] 155 * Dn = regs[n / 2].d[n & 1] 156 * Sn = regs[n / 4].d[n % 4 / 2], 157 * bits 31..0 for even n, and bits 63..32 for odd n 158 * (and regs[16] to regs[31] are inaccessible) 159 * In AArch64: 160 * Zn = regs[n].d[*] 161 * Qn = regs[n].d[1]:regs[n].d[0] 162 * Dn = regs[n].d[0] 163 * Sn = regs[n].d[0] bits 31..0 164 * Hn = regs[n].d[0] bits 15..0 165 * 166 * This corresponds to the architecturally defined mapping between 167 * the two execution states, and means we do not need to explicitly 168 * map these registers when changing states. 169 * 170 * Align the data for use with TCG host vector operations. 171 */ 172 173 #ifdef TARGET_AARCH64 174 # define ARM_MAX_VQ 16 175 #else 176 # define ARM_MAX_VQ 1 177 #endif 178 179 typedef struct ARMVectorReg { 180 uint64_t d[2 * ARM_MAX_VQ] QEMU_ALIGNED(16); 181 } ARMVectorReg; 182 183 #ifdef TARGET_AARCH64 184 /* In AArch32 mode, predicate registers do not exist at all. */ 185 typedef struct ARMPredicateReg { 186 uint64_t p[DIV_ROUND_UP(2 * ARM_MAX_VQ, 8)] QEMU_ALIGNED(16); 187 } ARMPredicateReg; 188 189 /* In AArch32 mode, PAC keys do not exist at all. */ 190 typedef struct ARMPACKey { 191 uint64_t lo, hi; 192 } ARMPACKey; 193 #endif 194 195 /* See the commentary above the TBFLAG field definitions. */ 196 typedef struct CPUARMTBFlags { 197 uint32_t flags; 198 target_ulong flags2; 199 } CPUARMTBFlags; 200 201 typedef struct ARMMMUFaultInfo ARMMMUFaultInfo; 202 203 typedef struct NVICState NVICState; 204 205 typedef struct CPUArchState { 206 /* Regs for current mode. */ 207 uint32_t regs[16]; 208 209 /* 32/64 switch only happens when taking and returning from 210 * exceptions so the overlap semantics are taken care of then 211 * instead of having a complicated union. 212 */ 213 /* Regs for A64 mode. */ 214 uint64_t xregs[32]; 215 uint64_t pc; 216 /* PSTATE isn't an architectural register for ARMv8. However, it is 217 * convenient for us to assemble the underlying state into a 32 bit format 218 * identical to the architectural format used for the SPSR. (This is also 219 * what the Linux kernel's 'pstate' field in signal handlers and KVM's 220 * 'pstate' register are.) Of the PSTATE bits: 221 * NZCV are kept in the split out env->CF/VF/NF/ZF, (which have the same 222 * semantics as for AArch32, as described in the comments on each field) 223 * nRW (also known as M[4]) is kept, inverted, in env->aarch64 224 * DAIF (exception masks) are kept in env->daif 225 * BTYPE is kept in env->btype 226 * SM and ZA are kept in env->svcr 227 * all other bits are stored in their correct places in env->pstate 228 */ 229 uint32_t pstate; 230 bool aarch64; /* True if CPU is in aarch64 state; inverse of PSTATE.nRW */ 231 bool thumb; /* True if CPU is in thumb mode; cpsr[5] */ 232 233 /* Cached TBFLAGS state. See below for which bits are included. */ 234 CPUARMTBFlags hflags; 235 236 /* Frequently accessed CPSR bits are stored separately for efficiency. 237 This contains all the other bits. Use cpsr_{read,write} to access 238 the whole CPSR. */ 239 uint32_t uncached_cpsr; 240 uint32_t spsr; 241 242 /* Banked registers. */ 243 uint64_t banked_spsr[8]; 244 uint32_t banked_r13[8]; 245 uint32_t banked_r14[8]; 246 247 /* These hold r8-r12. */ 248 uint32_t usr_regs[5]; 249 uint32_t fiq_regs[5]; 250 251 /* cpsr flag cache for faster execution */ 252 uint32_t CF; /* 0 or 1 */ 253 uint32_t VF; /* V is the bit 31. All other bits are undefined */ 254 uint32_t NF; /* N is bit 31. All other bits are undefined. */ 255 uint32_t ZF; /* Z set if zero. */ 256 uint32_t QF; /* 0 or 1 */ 257 uint32_t GE; /* cpsr[19:16] */ 258 uint32_t condexec_bits; /* IT bits. cpsr[15:10,26:25]. */ 259 uint32_t btype; /* BTI branch type. spsr[11:10]. */ 260 uint64_t daif; /* exception masks, in the bits they are in PSTATE */ 261 uint64_t svcr; /* PSTATE.{SM,ZA} in the bits they are in SVCR */ 262 263 uint64_t elr_el[4]; /* AArch64 exception link regs */ 264 uint64_t sp_el[4]; /* AArch64 banked stack pointers */ 265 266 /* System control coprocessor (cp15) */ 267 struct { 268 uint32_t c0_cpuid; 269 union { /* Cache size selection */ 270 struct { 271 uint64_t _unused_csselr0; 272 uint64_t csselr_ns; 273 uint64_t _unused_csselr1; 274 uint64_t csselr_s; 275 }; 276 uint64_t csselr_el[4]; 277 }; 278 union { /* System control register. */ 279 struct { 280 uint64_t _unused_sctlr; 281 uint64_t sctlr_ns; 282 uint64_t hsctlr; 283 uint64_t sctlr_s; 284 }; 285 uint64_t sctlr_el[4]; 286 }; 287 uint64_t vsctlr; /* Virtualization System control register. */ 288 uint64_t cpacr_el1; /* Architectural feature access control register */ 289 uint64_t cptr_el[4]; /* ARMv8 feature trap registers */ 290 uint32_t c1_xscaleauxcr; /* XScale auxiliary control register. */ 291 uint64_t sder; /* Secure debug enable register. */ 292 uint32_t nsacr; /* Non-secure access control register. */ 293 union { /* MMU translation table base 0. */ 294 struct { 295 uint64_t _unused_ttbr0_0; 296 uint64_t ttbr0_ns; 297 uint64_t _unused_ttbr0_1; 298 uint64_t ttbr0_s; 299 }; 300 uint64_t ttbr0_el[4]; 301 }; 302 union { /* MMU translation table base 1. */ 303 struct { 304 uint64_t _unused_ttbr1_0; 305 uint64_t ttbr1_ns; 306 uint64_t _unused_ttbr1_1; 307 uint64_t ttbr1_s; 308 }; 309 uint64_t ttbr1_el[4]; 310 }; 311 uint64_t vttbr_el2; /* Virtualization Translation Table Base. */ 312 uint64_t vsttbr_el2; /* Secure Virtualization Translation Table. */ 313 /* MMU translation table base control. */ 314 uint64_t tcr_el[4]; 315 uint64_t vtcr_el2; /* Virtualization Translation Control. */ 316 uint64_t vstcr_el2; /* Secure Virtualization Translation Control. */ 317 uint32_t c2_data; /* MPU data cacheable bits. */ 318 uint32_t c2_insn; /* MPU instruction cacheable bits. */ 319 union { /* MMU domain access control register 320 * MPU write buffer control. 321 */ 322 struct { 323 uint64_t dacr_ns; 324 uint64_t dacr_s; 325 }; 326 struct { 327 uint64_t dacr32_el2; 328 }; 329 }; 330 uint32_t pmsav5_data_ap; /* PMSAv5 MPU data access permissions */ 331 uint32_t pmsav5_insn_ap; /* PMSAv5 MPU insn access permissions */ 332 uint64_t hcr_el2; /* Hypervisor configuration register */ 333 uint64_t hcrx_el2; /* Extended Hypervisor configuration register */ 334 uint64_t scr_el3; /* Secure configuration register. */ 335 union { /* Fault status registers. */ 336 struct { 337 uint64_t ifsr_ns; 338 uint64_t ifsr_s; 339 }; 340 struct { 341 uint64_t ifsr32_el2; 342 }; 343 }; 344 union { 345 struct { 346 uint64_t _unused_dfsr; 347 uint64_t dfsr_ns; 348 uint64_t hsr; 349 uint64_t dfsr_s; 350 }; 351 uint64_t esr_el[4]; 352 }; 353 uint32_t c6_region[8]; /* MPU base/size registers. */ 354 union { /* Fault address registers. */ 355 struct { 356 uint64_t _unused_far0; 357 #if HOST_BIG_ENDIAN 358 uint32_t ifar_ns; 359 uint32_t dfar_ns; 360 uint32_t ifar_s; 361 uint32_t dfar_s; 362 #else 363 uint32_t dfar_ns; 364 uint32_t ifar_ns; 365 uint32_t dfar_s; 366 uint32_t ifar_s; 367 #endif 368 uint64_t _unused_far3; 369 }; 370 uint64_t far_el[4]; 371 }; 372 uint64_t hpfar_el2; 373 uint64_t hstr_el2; 374 union { /* Translation result. */ 375 struct { 376 uint64_t _unused_par_0; 377 uint64_t par_ns; 378 uint64_t _unused_par_1; 379 uint64_t par_s; 380 }; 381 uint64_t par_el[4]; 382 }; 383 384 uint32_t c9_insn; /* Cache lockdown registers. */ 385 uint32_t c9_data; 386 uint64_t c9_pmcr; /* performance monitor control register */ 387 uint64_t c9_pmcnten; /* perf monitor counter enables */ 388 uint64_t c9_pmovsr; /* perf monitor overflow status */ 389 uint64_t c9_pmuserenr; /* perf monitor user enable */ 390 uint64_t c9_pmselr; /* perf monitor counter selection register */ 391 uint64_t c9_pminten; /* perf monitor interrupt enables */ 392 union { /* Memory attribute redirection */ 393 struct { 394 #if HOST_BIG_ENDIAN 395 uint64_t _unused_mair_0; 396 uint32_t mair1_ns; 397 uint32_t mair0_ns; 398 uint64_t _unused_mair_1; 399 uint32_t mair1_s; 400 uint32_t mair0_s; 401 #else 402 uint64_t _unused_mair_0; 403 uint32_t mair0_ns; 404 uint32_t mair1_ns; 405 uint64_t _unused_mair_1; 406 uint32_t mair0_s; 407 uint32_t mair1_s; 408 #endif 409 }; 410 uint64_t mair_el[4]; 411 }; 412 union { /* vector base address register */ 413 struct { 414 uint64_t _unused_vbar; 415 uint64_t vbar_ns; 416 uint64_t hvbar; 417 uint64_t vbar_s; 418 }; 419 uint64_t vbar_el[4]; 420 }; 421 uint32_t mvbar; /* (monitor) vector base address register */ 422 uint64_t rvbar; /* rvbar sampled from rvbar property at reset */ 423 struct { /* FCSE PID. */ 424 uint32_t fcseidr_ns; 425 uint32_t fcseidr_s; 426 }; 427 union { /* Context ID. */ 428 struct { 429 uint64_t _unused_contextidr_0; 430 uint64_t contextidr_ns; 431 uint64_t _unused_contextidr_1; 432 uint64_t contextidr_s; 433 }; 434 uint64_t contextidr_el[4]; 435 }; 436 union { /* User RW Thread register. */ 437 struct { 438 uint64_t tpidrurw_ns; 439 uint64_t tpidrprw_ns; 440 uint64_t htpidr; 441 uint64_t _tpidr_el3; 442 }; 443 uint64_t tpidr_el[4]; 444 }; 445 uint64_t tpidr2_el0; 446 /* The secure banks of these registers don't map anywhere */ 447 uint64_t tpidrurw_s; 448 uint64_t tpidrprw_s; 449 uint64_t tpidruro_s; 450 451 union { /* User RO Thread register. */ 452 uint64_t tpidruro_ns; 453 uint64_t tpidrro_el[1]; 454 }; 455 uint64_t c14_cntfrq; /* Counter Frequency register */ 456 uint64_t c14_cntkctl; /* Timer Control register */ 457 uint64_t cnthctl_el2; /* Counter/Timer Hyp Control register */ 458 uint64_t cntvoff_el2; /* Counter Virtual Offset register */ 459 uint64_t cntpoff_el2; /* Counter Physical Offset register */ 460 ARMGenericTimer c14_timer[NUM_GTIMERS]; 461 uint32_t c15_cpar; /* XScale Coprocessor Access Register */ 462 uint32_t c15_ticonfig; /* TI925T configuration byte. */ 463 uint32_t c15_i_max; /* Maximum D-cache dirty line index. */ 464 uint32_t c15_i_min; /* Minimum D-cache dirty line index. */ 465 uint32_t c15_threadid; /* TI debugger thread-ID. */ 466 uint32_t c15_config_base_address; /* SCU base address. */ 467 uint32_t c15_diagnostic; /* diagnostic register */ 468 uint32_t c15_power_diagnostic; 469 uint32_t c15_power_control; /* power control */ 470 uint64_t dbgbvr[16]; /* breakpoint value registers */ 471 uint64_t dbgbcr[16]; /* breakpoint control registers */ 472 uint64_t dbgwvr[16]; /* watchpoint value registers */ 473 uint64_t dbgwcr[16]; /* watchpoint control registers */ 474 uint64_t dbgclaim; /* DBGCLAIM bits */ 475 uint64_t mdscr_el1; 476 uint64_t oslsr_el1; /* OS Lock Status */ 477 uint64_t osdlr_el1; /* OS DoubleLock status */ 478 uint64_t mdcr_el2; 479 uint64_t mdcr_el3; 480 /* Stores the architectural value of the counter *the last time it was 481 * updated* by pmccntr_op_start. Accesses should always be surrounded 482 * by pmccntr_op_start/pmccntr_op_finish to guarantee the latest 483 * architecturally-correct value is being read/set. 484 */ 485 uint64_t c15_ccnt; 486 /* Stores the delta between the architectural value and the underlying 487 * cycle count during normal operation. It is used to update c15_ccnt 488 * to be the correct architectural value before accesses. During 489 * accesses, c15_ccnt_delta contains the underlying count being used 490 * for the access, after which it reverts to the delta value in 491 * pmccntr_op_finish. 492 */ 493 uint64_t c15_ccnt_delta; 494 uint64_t c14_pmevcntr[31]; 495 uint64_t c14_pmevcntr_delta[31]; 496 uint64_t c14_pmevtyper[31]; 497 uint64_t pmccfiltr_el0; /* Performance Monitor Filter Register */ 498 uint64_t vpidr_el2; /* Virtualization Processor ID Register */ 499 uint64_t vmpidr_el2; /* Virtualization Multiprocessor ID Register */ 500 uint64_t tfsr_el[4]; /* tfsre0_el1 is index 0. */ 501 uint64_t gcr_el1; 502 uint64_t rgsr_el1; 503 504 /* Minimal RAS registers */ 505 uint64_t disr_el1; 506 uint64_t vdisr_el2; 507 uint64_t vsesr_el2; 508 509 /* 510 * Fine-Grained Trap registers. We store these as arrays so the 511 * access checking code doesn't have to manually select 512 * HFGRTR_EL2 vs HFDFGRTR_EL2 etc when looking up the bit to test. 513 * FEAT_FGT2 will add more elements to these arrays. 514 */ 515 uint64_t fgt_read[2]; /* HFGRTR, HDFGRTR */ 516 uint64_t fgt_write[2]; /* HFGWTR, HDFGWTR */ 517 uint64_t fgt_exec[1]; /* HFGITR */ 518 519 /* RME registers */ 520 uint64_t gpccr_el3; 521 uint64_t gptbr_el3; 522 uint64_t mfar_el3; 523 524 /* NV2 register */ 525 uint64_t vncr_el2; 526 } cp15; 527 528 struct { 529 /* M profile has up to 4 stack pointers: 530 * a Main Stack Pointer and a Process Stack Pointer for each 531 * of the Secure and Non-Secure states. (If the CPU doesn't support 532 * the security extension then it has only two SPs.) 533 * In QEMU we always store the currently active SP in regs[13], 534 * and the non-active SP for the current security state in 535 * v7m.other_sp. The stack pointers for the inactive security state 536 * are stored in other_ss_msp and other_ss_psp. 537 * switch_v7m_security_state() is responsible for rearranging them 538 * when we change security state. 539 */ 540 uint32_t other_sp; 541 uint32_t other_ss_msp; 542 uint32_t other_ss_psp; 543 uint32_t vecbase[M_REG_NUM_BANKS]; 544 uint32_t basepri[M_REG_NUM_BANKS]; 545 uint32_t control[M_REG_NUM_BANKS]; 546 uint32_t ccr[M_REG_NUM_BANKS]; /* Configuration and Control */ 547 uint32_t cfsr[M_REG_NUM_BANKS]; /* Configurable Fault Status */ 548 uint32_t hfsr; /* HardFault Status */ 549 uint32_t dfsr; /* Debug Fault Status Register */ 550 uint32_t sfsr; /* Secure Fault Status Register */ 551 uint32_t mmfar[M_REG_NUM_BANKS]; /* MemManage Fault Address */ 552 uint32_t bfar; /* BusFault Address */ 553 uint32_t sfar; /* Secure Fault Address Register */ 554 unsigned mpu_ctrl[M_REG_NUM_BANKS]; /* MPU_CTRL */ 555 int exception; 556 uint32_t primask[M_REG_NUM_BANKS]; 557 uint32_t faultmask[M_REG_NUM_BANKS]; 558 uint32_t aircr; /* only holds r/w state if security extn implemented */ 559 uint32_t secure; /* Is CPU in Secure state? (not guest visible) */ 560 uint32_t csselr[M_REG_NUM_BANKS]; 561 uint32_t scr[M_REG_NUM_BANKS]; 562 uint32_t msplim[M_REG_NUM_BANKS]; 563 uint32_t psplim[M_REG_NUM_BANKS]; 564 uint32_t fpcar[M_REG_NUM_BANKS]; 565 uint32_t fpccr[M_REG_NUM_BANKS]; 566 uint32_t fpdscr[M_REG_NUM_BANKS]; 567 uint32_t cpacr[M_REG_NUM_BANKS]; 568 uint32_t nsacr; 569 uint32_t ltpsize; 570 uint32_t vpr; 571 } v7m; 572 573 /* Information associated with an exception about to be taken: 574 * code which raises an exception must set cs->exception_index and 575 * the relevant parts of this structure; the cpu_do_interrupt function 576 * will then set the guest-visible registers as part of the exception 577 * entry process. 578 */ 579 struct { 580 uint32_t syndrome; /* AArch64 format syndrome register */ 581 uint32_t fsr; /* AArch32 format fault status register info */ 582 uint64_t vaddress; /* virtual addr associated with exception, if any */ 583 uint32_t target_el; /* EL the exception should be targeted for */ 584 /* If we implement EL2 we will also need to store information 585 * about the intermediate physical address for stage 2 faults. 586 */ 587 } exception; 588 589 /* Information associated with an SError */ 590 struct { 591 uint8_t pending; 592 uint8_t has_esr; 593 uint64_t esr; 594 } serror; 595 596 uint8_t ext_dabt_raised; /* Tracking/verifying injection of ext DABT */ 597 598 /* State of our input IRQ/FIQ/VIRQ/VFIQ lines */ 599 uint32_t irq_line_state; 600 601 /* Thumb-2 EE state. */ 602 uint32_t teecr; 603 uint32_t teehbr; 604 605 /* VFP coprocessor state. */ 606 struct { 607 ARMVectorReg zregs[32]; 608 609 #ifdef TARGET_AARCH64 610 /* Store FFR as pregs[16] to make it easier to treat as any other. */ 611 #define FFR_PRED_NUM 16 612 ARMPredicateReg pregs[17]; 613 /* Scratch space for aa64 sve predicate temporary. */ 614 ARMPredicateReg preg_tmp; 615 #endif 616 617 /* We store these fpcsr fields separately for convenience. */ 618 uint32_t qc[4] QEMU_ALIGNED(16); 619 int vec_len; 620 int vec_stride; 621 622 /* 623 * Floating point status and control registers. Some bits are 624 * stored separately in other fields or in the float_status below. 625 */ 626 uint64_t fpsr; 627 uint64_t fpcr; 628 629 uint32_t xregs[16]; 630 631 /* Scratch space for aa32 neon expansion. */ 632 uint32_t scratch[8]; 633 634 /* There are a number of distinct float control structures: 635 * 636 * fp_status: is the "normal" fp status. 637 * fp_status_fp16: used for half-precision calculations 638 * standard_fp_status : the ARM "Standard FPSCR Value" 639 * standard_fp_status_fp16 : used for half-precision 640 * calculations with the ARM "Standard FPSCR Value" 641 * 642 * Half-precision operations are governed by a separate 643 * flush-to-zero control bit in FPSCR:FZ16. We pass a separate 644 * status structure to control this. 645 * 646 * The "Standard FPSCR", ie default-NaN, flush-to-zero, 647 * round-to-nearest and is used by any operations (generally 648 * Neon) which the architecture defines as controlled by the 649 * standard FPSCR value rather than the FPSCR. 650 * 651 * The "standard FPSCR but for fp16 ops" is needed because 652 * the "standard FPSCR" tracks the FPSCR.FZ16 bit rather than 653 * using a fixed value for it. 654 * 655 * To avoid having to transfer exception bits around, we simply 656 * say that the FPSCR cumulative exception flags are the logical 657 * OR of the flags in the four fp statuses. This relies on the 658 * only thing which needs to read the exception flags being 659 * an explicit FPSCR read. 660 */ 661 float_status fp_status; 662 float_status fp_status_f16; 663 float_status standard_fp_status; 664 float_status standard_fp_status_f16; 665 666 uint64_t zcr_el[4]; /* ZCR_EL[1-3] */ 667 uint64_t smcr_el[4]; /* SMCR_EL[1-3] */ 668 } vfp; 669 670 uint64_t exclusive_addr; 671 uint64_t exclusive_val; 672 /* 673 * Contains the 'val' for the second 64-bit register of LDXP, which comes 674 * from the higher address, not the high part of a complete 128-bit value. 675 * In some ways it might be more convenient to record the exclusive value 676 * as the low and high halves of a 128 bit data value, but the current 677 * semantics of these fields are baked into the migration format. 678 */ 679 uint64_t exclusive_high; 680 681 /* iwMMXt coprocessor state. */ 682 struct { 683 uint64_t regs[16]; 684 uint64_t val; 685 686 uint32_t cregs[16]; 687 } iwmmxt; 688 689 #ifdef TARGET_AARCH64 690 struct { 691 ARMPACKey apia; 692 ARMPACKey apib; 693 ARMPACKey apda; 694 ARMPACKey apdb; 695 ARMPACKey apga; 696 } keys; 697 698 uint64_t scxtnum_el[4]; 699 700 /* 701 * SME ZA storage -- 256 x 256 byte array, with bytes in host word order, 702 * as we do with vfp.zregs[]. This corresponds to the architectural ZA 703 * array, where ZA[N] is in the least-significant bytes of env->zarray[N]. 704 * When SVL is less than the architectural maximum, the accessible 705 * storage is restricted, such that if the SVL is X bytes the guest can 706 * see only the bottom X elements of zarray[], and only the least 707 * significant X bytes of each element of the array. (In other words, 708 * the observable part is always square.) 709 * 710 * The ZA storage can also be considered as a set of square tiles of 711 * elements of different sizes. The mapping from tiles to the ZA array 712 * is architecturally defined, such that for tiles of elements of esz 713 * bytes, the Nth row (or "horizontal slice") of tile T is in 714 * ZA[T + N * esz]. Note that this means that each tile is not contiguous 715 * in the ZA storage, because its rows are striped through the ZA array. 716 * 717 * Because this is so large, keep this toward the end of the reset area, 718 * to keep the offsets into the rest of the structure smaller. 719 */ 720 ARMVectorReg zarray[ARM_MAX_VQ * 16]; 721 #endif 722 723 struct CPUBreakpoint *cpu_breakpoint[16]; 724 struct CPUWatchpoint *cpu_watchpoint[16]; 725 726 /* Optional fault info across tlb lookup. */ 727 ARMMMUFaultInfo *tlb_fi; 728 729 /* Fields up to this point are cleared by a CPU reset */ 730 struct {} end_reset_fields; 731 732 /* Fields after this point are preserved across CPU reset. */ 733 734 /* Internal CPU feature flags. */ 735 uint64_t features; 736 737 /* PMSAv7 MPU */ 738 struct { 739 uint32_t *drbar; 740 uint32_t *drsr; 741 uint32_t *dracr; 742 uint32_t rnr[M_REG_NUM_BANKS]; 743 } pmsav7; 744 745 /* PMSAv8 MPU */ 746 struct { 747 /* The PMSAv8 implementation also shares some PMSAv7 config 748 * and state: 749 * pmsav7.rnr (region number register) 750 * pmsav7_dregion (number of configured regions) 751 */ 752 uint32_t *rbar[M_REG_NUM_BANKS]; 753 uint32_t *rlar[M_REG_NUM_BANKS]; 754 uint32_t *hprbar; 755 uint32_t *hprlar; 756 uint32_t mair0[M_REG_NUM_BANKS]; 757 uint32_t mair1[M_REG_NUM_BANKS]; 758 uint32_t hprselr; 759 } pmsav8; 760 761 /* v8M SAU */ 762 struct { 763 uint32_t *rbar; 764 uint32_t *rlar; 765 uint32_t rnr; 766 uint32_t ctrl; 767 } sau; 768 769 #if !defined(CONFIG_USER_ONLY) 770 NVICState *nvic; 771 const struct arm_boot_info *boot_info; 772 /* Store GICv3CPUState to access from this struct */ 773 void *gicv3state; 774 #else /* CONFIG_USER_ONLY */ 775 /* For usermode syscall translation. */ 776 bool eabi; 777 #endif /* CONFIG_USER_ONLY */ 778 779 #ifdef TARGET_TAGGED_ADDRESSES 780 /* Linux syscall tagged address support */ 781 bool tagged_addr_enable; 782 #endif 783 } CPUARMState; 784 785 static inline void set_feature(CPUARMState *env, int feature) 786 { 787 env->features |= 1ULL << feature; 788 } 789 790 static inline void unset_feature(CPUARMState *env, int feature) 791 { 792 env->features &= ~(1ULL << feature); 793 } 794 795 /** 796 * ARMELChangeHookFn: 797 * type of a function which can be registered via arm_register_el_change_hook() 798 * to get callbacks when the CPU changes its exception level or mode. 799 */ 800 typedef void ARMELChangeHookFn(ARMCPU *cpu, void *opaque); 801 typedef struct ARMELChangeHook ARMELChangeHook; 802 struct ARMELChangeHook { 803 ARMELChangeHookFn *hook; 804 void *opaque; 805 QLIST_ENTRY(ARMELChangeHook) node; 806 }; 807 808 /* These values map onto the return values for 809 * QEMU_PSCI_0_2_FN_AFFINITY_INFO */ 810 typedef enum ARMPSCIState { 811 PSCI_ON = 0, 812 PSCI_OFF = 1, 813 PSCI_ON_PENDING = 2 814 } ARMPSCIState; 815 816 typedef struct ARMISARegisters ARMISARegisters; 817 818 /* 819 * In map, each set bit is a supported vector length of (bit-number + 1) * 16 820 * bytes, i.e. each bit number + 1 is the vector length in quadwords. 821 * 822 * While processing properties during initialization, corresponding init bits 823 * are set for bits in sve_vq_map that have been set by properties. 824 * 825 * Bits set in supported represent valid vector lengths for the CPU type. 826 */ 827 typedef struct { 828 uint32_t map, init, supported; 829 } ARMVQMap; 830 831 /** 832 * ARMCPU: 833 * @env: #CPUARMState 834 * 835 * An ARM CPU core. 836 */ 837 struct ArchCPU { 838 CPUState parent_obj; 839 840 CPUARMState env; 841 842 /* Coprocessor information */ 843 GHashTable *cp_regs; 844 /* For marshalling (mostly coprocessor) register state between the 845 * kernel and QEMU (for KVM) and between two QEMUs (for migration), 846 * we use these arrays. 847 */ 848 /* List of register indexes managed via these arrays; (full KVM style 849 * 64 bit indexes, not CPRegInfo 32 bit indexes) 850 */ 851 uint64_t *cpreg_indexes; 852 /* Values of the registers (cpreg_indexes[i]'s value is cpreg_values[i]) */ 853 uint64_t *cpreg_values; 854 /* Length of the indexes, values, reset_values arrays */ 855 int32_t cpreg_array_len; 856 /* These are used only for migration: incoming data arrives in 857 * these fields and is sanity checked in post_load before copying 858 * to the working data structures above. 859 */ 860 uint64_t *cpreg_vmstate_indexes; 861 uint64_t *cpreg_vmstate_values; 862 int32_t cpreg_vmstate_array_len; 863 864 DynamicGDBFeatureInfo dyn_sysreg_feature; 865 DynamicGDBFeatureInfo dyn_svereg_feature; 866 DynamicGDBFeatureInfo dyn_m_systemreg_feature; 867 DynamicGDBFeatureInfo dyn_m_secextreg_feature; 868 869 /* Timers used by the generic (architected) timer */ 870 QEMUTimer *gt_timer[NUM_GTIMERS]; 871 /* 872 * Timer used by the PMU. Its state is restored after migration by 873 * pmu_op_finish() - it does not need other handling during migration 874 */ 875 QEMUTimer *pmu_timer; 876 /* Timer used for WFxT timeouts */ 877 QEMUTimer *wfxt_timer; 878 879 /* GPIO outputs for generic timer */ 880 qemu_irq gt_timer_outputs[NUM_GTIMERS]; 881 /* GPIO output for GICv3 maintenance interrupt signal */ 882 qemu_irq gicv3_maintenance_interrupt; 883 /* GPIO output for the PMU interrupt */ 884 qemu_irq pmu_interrupt; 885 886 /* MemoryRegion to use for secure physical accesses */ 887 MemoryRegion *secure_memory; 888 889 /* MemoryRegion to use for allocation tag accesses */ 890 MemoryRegion *tag_memory; 891 MemoryRegion *secure_tag_memory; 892 893 /* For v8M, pointer to the IDAU interface provided by board/SoC */ 894 Object *idau; 895 896 /* 'compatible' string for this CPU for Linux device trees */ 897 const char *dtb_compatible; 898 899 /* PSCI version for this CPU 900 * Bits[31:16] = Major Version 901 * Bits[15:0] = Minor Version 902 */ 903 uint32_t psci_version; 904 905 /* Current power state, access guarded by BQL */ 906 ARMPSCIState power_state; 907 908 /* CPU has virtualization extension */ 909 bool has_el2; 910 /* CPU has security extension */ 911 bool has_el3; 912 /* CPU has PMU (Performance Monitor Unit) */ 913 bool has_pmu; 914 /* CPU has VFP */ 915 bool has_vfp; 916 /* CPU has 32 VFP registers */ 917 bool has_vfp_d32; 918 /* CPU has Neon */ 919 bool has_neon; 920 /* CPU has M-profile DSP extension */ 921 bool has_dsp; 922 923 /* CPU has memory protection unit */ 924 bool has_mpu; 925 /* PMSAv7 MPU number of supported regions */ 926 uint32_t pmsav7_dregion; 927 /* PMSAv8 MPU number of supported hyp regions */ 928 uint32_t pmsav8r_hdregion; 929 /* v8M SAU number of supported regions */ 930 uint32_t sau_sregion; 931 932 /* PSCI conduit used to invoke PSCI methods 933 * 0 - disabled, 1 - smc, 2 - hvc 934 */ 935 uint32_t psci_conduit; 936 937 /* For v8M, initial value of the Secure VTOR */ 938 uint32_t init_svtor; 939 /* For v8M, initial value of the Non-secure VTOR */ 940 uint32_t init_nsvtor; 941 942 /* [QEMU_]KVM_ARM_TARGET_* constant for this CPU, or 943 * QEMU_KVM_ARM_TARGET_NONE if the kernel doesn't support this CPU type. 944 */ 945 uint32_t kvm_target; 946 947 #ifdef CONFIG_KVM 948 /* KVM init features for this CPU */ 949 uint32_t kvm_init_features[7]; 950 951 /* KVM CPU state */ 952 953 /* KVM virtual time adjustment */ 954 bool kvm_adjvtime; 955 bool kvm_vtime_dirty; 956 uint64_t kvm_vtime; 957 958 /* KVM steal time */ 959 OnOffAuto kvm_steal_time; 960 #endif /* CONFIG_KVM */ 961 962 /* Uniprocessor system with MP extensions */ 963 bool mp_is_up; 964 965 /* True if we tried kvm_arm_host_cpu_features() during CPU instance_init 966 * and the probe failed (so we need to report the error in realize) 967 */ 968 bool host_cpu_probe_failed; 969 970 /* QOM property to indicate we should use the back-compat CNTFRQ default */ 971 bool backcompat_cntfrq; 972 973 /* Specify the number of cores in this CPU cluster. Used for the L2CTLR 974 * register. 975 */ 976 int32_t core_count; 977 978 /* The instance init functions for implementation-specific subclasses 979 * set these fields to specify the implementation-dependent values of 980 * various constant registers and reset values of non-constant 981 * registers. 982 * Some of these might become QOM properties eventually. 983 * Field names match the official register names as defined in the 984 * ARMv7AR ARM Architecture Reference Manual. A reset_ prefix 985 * is used for reset values of non-constant registers; no reset_ 986 * prefix means a constant register. 987 * Some of these registers are split out into a substructure that 988 * is shared with the translators to control the ISA. 989 * 990 * Note that if you add an ID register to the ARMISARegisters struct 991 * you need to also update the 32-bit and 64-bit versions of the 992 * kvm_arm_get_host_cpu_features() function to correctly populate the 993 * field by reading the value from the KVM vCPU. 994 */ 995 struct ARMISARegisters { 996 uint32_t id_isar0; 997 uint32_t id_isar1; 998 uint32_t id_isar2; 999 uint32_t id_isar3; 1000 uint32_t id_isar4; 1001 uint32_t id_isar5; 1002 uint32_t id_isar6; 1003 uint32_t id_mmfr0; 1004 uint32_t id_mmfr1; 1005 uint32_t id_mmfr2; 1006 uint32_t id_mmfr3; 1007 uint32_t id_mmfr4; 1008 uint32_t id_mmfr5; 1009 uint32_t id_pfr0; 1010 uint32_t id_pfr1; 1011 uint32_t id_pfr2; 1012 uint32_t mvfr0; 1013 uint32_t mvfr1; 1014 uint32_t mvfr2; 1015 uint32_t id_dfr0; 1016 uint32_t id_dfr1; 1017 uint32_t dbgdidr; 1018 uint32_t dbgdevid; 1019 uint32_t dbgdevid1; 1020 uint64_t id_aa64isar0; 1021 uint64_t id_aa64isar1; 1022 uint64_t id_aa64isar2; 1023 uint64_t id_aa64pfr0; 1024 uint64_t id_aa64pfr1; 1025 uint64_t id_aa64mmfr0; 1026 uint64_t id_aa64mmfr1; 1027 uint64_t id_aa64mmfr2; 1028 uint64_t id_aa64mmfr3; 1029 uint64_t id_aa64dfr0; 1030 uint64_t id_aa64dfr1; 1031 uint64_t id_aa64zfr0; 1032 uint64_t id_aa64smfr0; 1033 uint64_t reset_pmcr_el0; 1034 } isar; 1035 uint64_t midr; 1036 uint32_t revidr; 1037 uint32_t reset_fpsid; 1038 uint64_t ctr; 1039 uint32_t reset_sctlr; 1040 uint64_t pmceid0; 1041 uint64_t pmceid1; 1042 uint32_t id_afr0; 1043 uint64_t id_aa64afr0; 1044 uint64_t id_aa64afr1; 1045 uint64_t clidr; 1046 uint64_t mp_affinity; /* MP ID without feature bits */ 1047 /* The elements of this array are the CCSIDR values for each cache, 1048 * in the order L1DCache, L1ICache, L2DCache, L2ICache, etc. 1049 */ 1050 uint64_t ccsidr[16]; 1051 uint64_t reset_cbar; 1052 uint32_t reset_auxcr; 1053 bool reset_hivecs; 1054 uint8_t reset_l0gptsz; 1055 1056 /* 1057 * Intermediate values used during property parsing. 1058 * Once finalized, the values should be read from ID_AA64*. 1059 */ 1060 bool prop_pauth; 1061 bool prop_pauth_impdef; 1062 bool prop_pauth_qarma3; 1063 bool prop_lpa2; 1064 1065 /* DCZ blocksize, in log_2(words), ie low 4 bits of DCZID_EL0 */ 1066 uint8_t dcz_blocksize; 1067 /* GM blocksize, in log_2(words), ie low 4 bits of GMID_EL0 */ 1068 uint8_t gm_blocksize; 1069 1070 uint64_t rvbar_prop; /* Property/input signals. */ 1071 1072 /* Configurable aspects of GIC cpu interface (which is part of the CPU) */ 1073 int gic_num_lrs; /* number of list registers */ 1074 int gic_vpribits; /* number of virtual priority bits */ 1075 int gic_vprebits; /* number of virtual preemption bits */ 1076 int gic_pribits; /* number of physical priority bits */ 1077 1078 /* Whether the cfgend input is high (i.e. this CPU should reset into 1079 * big-endian mode). This setting isn't used directly: instead it modifies 1080 * the reset_sctlr value to have SCTLR_B or SCTLR_EE set, depending on the 1081 * architecture version. 1082 */ 1083 bool cfgend; 1084 1085 QLIST_HEAD(, ARMELChangeHook) pre_el_change_hooks; 1086 QLIST_HEAD(, ARMELChangeHook) el_change_hooks; 1087 1088 int32_t node_id; /* NUMA node this CPU belongs to */ 1089 1090 /* Used to synchronize KVM and QEMU in-kernel device levels */ 1091 uint8_t device_irq_level; 1092 1093 /* Used to set the maximum vector length the cpu will support. */ 1094 uint32_t sve_max_vq; 1095 1096 #ifdef CONFIG_USER_ONLY 1097 /* Used to set the default vector length at process start. */ 1098 uint32_t sve_default_vq; 1099 uint32_t sme_default_vq; 1100 #endif 1101 1102 ARMVQMap sve_vq; 1103 ARMVQMap sme_vq; 1104 1105 /* Generic timer counter frequency, in Hz */ 1106 uint64_t gt_cntfrq_hz; 1107 }; 1108 1109 typedef struct ARMCPUInfo { 1110 const char *name; 1111 void (*initfn)(Object *obj); 1112 void (*class_init)(ObjectClass *oc, void *data); 1113 } ARMCPUInfo; 1114 1115 /** 1116 * ARMCPUClass: 1117 * @parent_realize: The parent class' realize handler. 1118 * @parent_phases: The parent class' reset phase handlers. 1119 * 1120 * An ARM CPU model. 1121 */ 1122 struct ARMCPUClass { 1123 CPUClass parent_class; 1124 1125 const ARMCPUInfo *info; 1126 DeviceRealize parent_realize; 1127 ResettablePhases parent_phases; 1128 }; 1129 1130 struct AArch64CPUClass { 1131 ARMCPUClass parent_class; 1132 }; 1133 1134 /* Callback functions for the generic timer's timers. */ 1135 void arm_gt_ptimer_cb(void *opaque); 1136 void arm_gt_vtimer_cb(void *opaque); 1137 void arm_gt_htimer_cb(void *opaque); 1138 void arm_gt_stimer_cb(void *opaque); 1139 void arm_gt_hvtimer_cb(void *opaque); 1140 1141 unsigned int gt_cntfrq_period_ns(ARMCPU *cpu); 1142 void gt_rme_post_el_change(ARMCPU *cpu, void *opaque); 1143 1144 void arm_cpu_post_init(Object *obj); 1145 1146 #define ARM_AFF0_SHIFT 0 1147 #define ARM_AFF0_MASK (0xFFULL << ARM_AFF0_SHIFT) 1148 #define ARM_AFF1_SHIFT 8 1149 #define ARM_AFF1_MASK (0xFFULL << ARM_AFF1_SHIFT) 1150 #define ARM_AFF2_SHIFT 16 1151 #define ARM_AFF2_MASK (0xFFULL << ARM_AFF2_SHIFT) 1152 #define ARM_AFF3_SHIFT 32 1153 #define ARM_AFF3_MASK (0xFFULL << ARM_AFF3_SHIFT) 1154 #define ARM_DEFAULT_CPUS_PER_CLUSTER 8 1155 1156 #define ARM32_AFFINITY_MASK (ARM_AFF0_MASK | ARM_AFF1_MASK | ARM_AFF2_MASK) 1157 #define ARM64_AFFINITY_MASK \ 1158 (ARM_AFF0_MASK | ARM_AFF1_MASK | ARM_AFF2_MASK | ARM_AFF3_MASK) 1159 #define ARM64_AFFINITY_INVALID (~ARM64_AFFINITY_MASK) 1160 1161 uint64_t arm_build_mp_affinity(int idx, uint8_t clustersz); 1162 1163 #ifndef CONFIG_USER_ONLY 1164 extern const VMStateDescription vmstate_arm_cpu; 1165 1166 void arm_cpu_do_interrupt(CPUState *cpu); 1167 void arm_v7m_cpu_do_interrupt(CPUState *cpu); 1168 1169 hwaddr arm_cpu_get_phys_page_attrs_debug(CPUState *cpu, vaddr addr, 1170 MemTxAttrs *attrs); 1171 #endif /* !CONFIG_USER_ONLY */ 1172 1173 int arm_cpu_gdb_read_register(CPUState *cpu, GByteArray *buf, int reg); 1174 int arm_cpu_gdb_write_register(CPUState *cpu, uint8_t *buf, int reg); 1175 1176 int arm_cpu_write_elf64_note(WriteCoreDumpFunction f, CPUState *cs, 1177 int cpuid, DumpState *s); 1178 int arm_cpu_write_elf32_note(WriteCoreDumpFunction f, CPUState *cs, 1179 int cpuid, DumpState *s); 1180 1181 /** 1182 * arm_emulate_firmware_reset: Emulate firmware CPU reset handling 1183 * @cpu: CPU (which must have been freshly reset) 1184 * @target_el: exception level to put the CPU into 1185 * @secure: whether to put the CPU in secure state 1186 * 1187 * When QEMU is directly running a guest kernel at a lower level than 1188 * EL3 it implicitly emulates some aspects of the guest firmware. 1189 * This includes that on reset we need to configure the parts of the 1190 * CPU corresponding to EL3 so that the real guest code can run at its 1191 * lower exception level. This function does that post-reset CPU setup, 1192 * for when we do direct boot of a guest kernel, and for when we 1193 * emulate PSCI and similar firmware interfaces starting a CPU at a 1194 * lower exception level. 1195 * 1196 * @target_el must be an EL implemented by the CPU between 1 and 3. 1197 * We do not support dropping into a Secure EL other than 3. 1198 * 1199 * It is the responsibility of the caller to call arm_rebuild_hflags(). 1200 */ 1201 void arm_emulate_firmware_reset(CPUState *cpustate, int target_el); 1202 1203 #ifdef TARGET_AARCH64 1204 int aarch64_cpu_gdb_read_register(CPUState *cpu, GByteArray *buf, int reg); 1205 int aarch64_cpu_gdb_write_register(CPUState *cpu, uint8_t *buf, int reg); 1206 void aarch64_sve_narrow_vq(CPUARMState *env, unsigned vq); 1207 void aarch64_sve_change_el(CPUARMState *env, int old_el, 1208 int new_el, bool el0_a64); 1209 void aarch64_set_svcr(CPUARMState *env, uint64_t new, uint64_t mask); 1210 1211 /* 1212 * SVE registers are encoded in KVM's memory in an endianness-invariant format. 1213 * The byte at offset i from the start of the in-memory representation contains 1214 * the bits [(7 + 8 * i) : (8 * i)] of the register value. As this means the 1215 * lowest offsets are stored in the lowest memory addresses, then that nearly 1216 * matches QEMU's representation, which is to use an array of host-endian 1217 * uint64_t's, where the lower offsets are at the lower indices. To complete 1218 * the translation we just need to byte swap the uint64_t's on big-endian hosts. 1219 */ 1220 static inline uint64_t *sve_bswap64(uint64_t *dst, uint64_t *src, int nr) 1221 { 1222 #if HOST_BIG_ENDIAN 1223 int i; 1224 1225 for (i = 0; i < nr; ++i) { 1226 dst[i] = bswap64(src[i]); 1227 } 1228 1229 return dst; 1230 #else 1231 return src; 1232 #endif 1233 } 1234 1235 #else 1236 static inline void aarch64_sve_narrow_vq(CPUARMState *env, unsigned vq) { } 1237 static inline void aarch64_sve_change_el(CPUARMState *env, int o, 1238 int n, bool a) 1239 { } 1240 #endif 1241 1242 void aarch64_sync_32_to_64(CPUARMState *env); 1243 void aarch64_sync_64_to_32(CPUARMState *env); 1244 1245 int fp_exception_el(CPUARMState *env, int cur_el); 1246 int sve_exception_el(CPUARMState *env, int cur_el); 1247 int sme_exception_el(CPUARMState *env, int cur_el); 1248 1249 /** 1250 * sve_vqm1_for_el_sm: 1251 * @env: CPUARMState 1252 * @el: exception level 1253 * @sm: streaming mode 1254 * 1255 * Compute the current vector length for @el & @sm, in units of 1256 * Quadwords Minus 1 -- the same scale used for ZCR_ELx.LEN. 1257 * If @sm, compute for SVL, otherwise NVL. 1258 */ 1259 uint32_t sve_vqm1_for_el_sm(CPUARMState *env, int el, bool sm); 1260 1261 /* Likewise, but using @sm = PSTATE.SM. */ 1262 uint32_t sve_vqm1_for_el(CPUARMState *env, int el); 1263 1264 static inline bool is_a64(CPUARMState *env) 1265 { 1266 return env->aarch64; 1267 } 1268 1269 /** 1270 * pmu_op_start/finish 1271 * @env: CPUARMState 1272 * 1273 * Convert all PMU counters between their delta form (the typical mode when 1274 * they are enabled) and the guest-visible values. These two calls must 1275 * surround any action which might affect the counters. 1276 */ 1277 void pmu_op_start(CPUARMState *env); 1278 void pmu_op_finish(CPUARMState *env); 1279 1280 /* 1281 * Called when a PMU counter is due to overflow 1282 */ 1283 void arm_pmu_timer_cb(void *opaque); 1284 1285 /** 1286 * Functions to register as EL change hooks for PMU mode filtering 1287 */ 1288 void pmu_pre_el_change(ARMCPU *cpu, void *ignored); 1289 void pmu_post_el_change(ARMCPU *cpu, void *ignored); 1290 1291 /* 1292 * pmu_init 1293 * @cpu: ARMCPU 1294 * 1295 * Initialize the CPU's PMCEID[01]_EL0 registers and associated internal state 1296 * for the current configuration 1297 */ 1298 void pmu_init(ARMCPU *cpu); 1299 1300 /* SCTLR bit meanings. Several bits have been reused in newer 1301 * versions of the architecture; in that case we define constants 1302 * for both old and new bit meanings. Code which tests against those 1303 * bits should probably check or otherwise arrange that the CPU 1304 * is the architectural version it expects. 1305 */ 1306 #define SCTLR_M (1U << 0) 1307 #define SCTLR_A (1U << 1) 1308 #define SCTLR_C (1U << 2) 1309 #define SCTLR_W (1U << 3) /* up to v6; RAO in v7 */ 1310 #define SCTLR_nTLSMD_32 (1U << 3) /* v8.2-LSMAOC, AArch32 only */ 1311 #define SCTLR_SA (1U << 3) /* AArch64 only */ 1312 #define SCTLR_P (1U << 4) /* up to v5; RAO in v6 and v7 */ 1313 #define SCTLR_LSMAOE_32 (1U << 4) /* v8.2-LSMAOC, AArch32 only */ 1314 #define SCTLR_SA0 (1U << 4) /* v8 onward, AArch64 only */ 1315 #define SCTLR_D (1U << 5) /* up to v5; RAO in v6 */ 1316 #define SCTLR_CP15BEN (1U << 5) /* v7 onward */ 1317 #define SCTLR_L (1U << 6) /* up to v5; RAO in v6 and v7; RAZ in v8 */ 1318 #define SCTLR_nAA (1U << 6) /* when FEAT_LSE2 is implemented */ 1319 #define SCTLR_B (1U << 7) /* up to v6; RAZ in v7 */ 1320 #define SCTLR_ITD (1U << 7) /* v8 onward */ 1321 #define SCTLR_S (1U << 8) /* up to v6; RAZ in v7 */ 1322 #define SCTLR_SED (1U << 8) /* v8 onward */ 1323 #define SCTLR_R (1U << 9) /* up to v6; RAZ in v7 */ 1324 #define SCTLR_UMA (1U << 9) /* v8 onward, AArch64 only */ 1325 #define SCTLR_F (1U << 10) /* up to v6 */ 1326 #define SCTLR_SW (1U << 10) /* v7 */ 1327 #define SCTLR_EnRCTX (1U << 10) /* in v8.0-PredInv */ 1328 #define SCTLR_Z (1U << 11) /* in v7, RES1 in v8 */ 1329 #define SCTLR_EOS (1U << 11) /* v8.5-ExS */ 1330 #define SCTLR_I (1U << 12) 1331 #define SCTLR_V (1U << 13) /* AArch32 only */ 1332 #define SCTLR_EnDB (1U << 13) /* v8.3, AArch64 only */ 1333 #define SCTLR_RR (1U << 14) /* up to v7 */ 1334 #define SCTLR_DZE (1U << 14) /* v8 onward, AArch64 only */ 1335 #define SCTLR_L4 (1U << 15) /* up to v6; RAZ in v7 */ 1336 #define SCTLR_UCT (1U << 15) /* v8 onward, AArch64 only */ 1337 #define SCTLR_DT (1U << 16) /* up to ??, RAO in v6 and v7 */ 1338 #define SCTLR_nTWI (1U << 16) /* v8 onward */ 1339 #define SCTLR_HA (1U << 17) /* up to v7, RES0 in v8 */ 1340 #define SCTLR_BR (1U << 17) /* PMSA only */ 1341 #define SCTLR_IT (1U << 18) /* up to ??, RAO in v6 and v7 */ 1342 #define SCTLR_nTWE (1U << 18) /* v8 onward */ 1343 #define SCTLR_WXN (1U << 19) 1344 #define SCTLR_ST (1U << 20) /* up to ??, RAZ in v6 */ 1345 #define SCTLR_UWXN (1U << 20) /* v7 onward, AArch32 only */ 1346 #define SCTLR_TSCXT (1U << 20) /* FEAT_CSV2_1p2, AArch64 only */ 1347 #define SCTLR_FI (1U << 21) /* up to v7, v8 RES0 */ 1348 #define SCTLR_IESB (1U << 21) /* v8.2-IESB, AArch64 only */ 1349 #define SCTLR_U (1U << 22) /* up to v6, RAO in v7 */ 1350 #define SCTLR_EIS (1U << 22) /* v8.5-ExS */ 1351 #define SCTLR_XP (1U << 23) /* up to v6; v7 onward RAO */ 1352 #define SCTLR_SPAN (1U << 23) /* v8.1-PAN */ 1353 #define SCTLR_VE (1U << 24) /* up to v7 */ 1354 #define SCTLR_E0E (1U << 24) /* v8 onward, AArch64 only */ 1355 #define SCTLR_EE (1U << 25) 1356 #define SCTLR_L2 (1U << 26) /* up to v6, RAZ in v7 */ 1357 #define SCTLR_UCI (1U << 26) /* v8 onward, AArch64 only */ 1358 #define SCTLR_NMFI (1U << 27) /* up to v7, RAZ in v7VE and v8 */ 1359 #define SCTLR_EnDA (1U << 27) /* v8.3, AArch64 only */ 1360 #define SCTLR_TRE (1U << 28) /* AArch32 only */ 1361 #define SCTLR_nTLSMD_64 (1U << 28) /* v8.2-LSMAOC, AArch64 only */ 1362 #define SCTLR_AFE (1U << 29) /* AArch32 only */ 1363 #define SCTLR_LSMAOE_64 (1U << 29) /* v8.2-LSMAOC, AArch64 only */ 1364 #define SCTLR_TE (1U << 30) /* AArch32 only */ 1365 #define SCTLR_EnIB (1U << 30) /* v8.3, AArch64 only */ 1366 #define SCTLR_EnIA (1U << 31) /* v8.3, AArch64 only */ 1367 #define SCTLR_DSSBS_32 (1U << 31) /* v8.5, AArch32 only */ 1368 #define SCTLR_MSCEN (1ULL << 33) /* FEAT_MOPS */ 1369 #define SCTLR_BT0 (1ULL << 35) /* v8.5-BTI */ 1370 #define SCTLR_BT1 (1ULL << 36) /* v8.5-BTI */ 1371 #define SCTLR_ITFSB (1ULL << 37) /* v8.5-MemTag */ 1372 #define SCTLR_TCF0 (3ULL << 38) /* v8.5-MemTag */ 1373 #define SCTLR_TCF (3ULL << 40) /* v8.5-MemTag */ 1374 #define SCTLR_ATA0 (1ULL << 42) /* v8.5-MemTag */ 1375 #define SCTLR_ATA (1ULL << 43) /* v8.5-MemTag */ 1376 #define SCTLR_DSSBS_64 (1ULL << 44) /* v8.5, AArch64 only */ 1377 #define SCTLR_TWEDEn (1ULL << 45) /* FEAT_TWED */ 1378 #define SCTLR_TWEDEL MAKE_64_MASK(46, 4) /* FEAT_TWED */ 1379 #define SCTLR_TMT0 (1ULL << 50) /* FEAT_TME */ 1380 #define SCTLR_TMT (1ULL << 51) /* FEAT_TME */ 1381 #define SCTLR_TME0 (1ULL << 52) /* FEAT_TME */ 1382 #define SCTLR_TME (1ULL << 53) /* FEAT_TME */ 1383 #define SCTLR_EnASR (1ULL << 54) /* FEAT_LS64_V */ 1384 #define SCTLR_EnAS0 (1ULL << 55) /* FEAT_LS64_ACCDATA */ 1385 #define SCTLR_EnALS (1ULL << 56) /* FEAT_LS64 */ 1386 #define SCTLR_EPAN (1ULL << 57) /* FEAT_PAN3 */ 1387 #define SCTLR_EnTP2 (1ULL << 60) /* FEAT_SME */ 1388 #define SCTLR_NMI (1ULL << 61) /* FEAT_NMI */ 1389 #define SCTLR_SPINTMASK (1ULL << 62) /* FEAT_NMI */ 1390 #define SCTLR_TIDCP (1ULL << 63) /* FEAT_TIDCP1 */ 1391 1392 #define CPSR_M (0x1fU) 1393 #define CPSR_T (1U << 5) 1394 #define CPSR_F (1U << 6) 1395 #define CPSR_I (1U << 7) 1396 #define CPSR_A (1U << 8) 1397 #define CPSR_E (1U << 9) 1398 #define CPSR_IT_2_7 (0xfc00U) 1399 #define CPSR_GE (0xfU << 16) 1400 #define CPSR_IL (1U << 20) 1401 #define CPSR_DIT (1U << 21) 1402 #define CPSR_PAN (1U << 22) 1403 #define CPSR_SSBS (1U << 23) 1404 #define CPSR_J (1U << 24) 1405 #define CPSR_IT_0_1 (3U << 25) 1406 #define CPSR_Q (1U << 27) 1407 #define CPSR_V (1U << 28) 1408 #define CPSR_C (1U << 29) 1409 #define CPSR_Z (1U << 30) 1410 #define CPSR_N (1U << 31) 1411 #define CPSR_NZCV (CPSR_N | CPSR_Z | CPSR_C | CPSR_V) 1412 #define CPSR_AIF (CPSR_A | CPSR_I | CPSR_F) 1413 #define ISR_FS (1U << 9) 1414 #define ISR_IS (1U << 10) 1415 1416 #define CPSR_IT (CPSR_IT_0_1 | CPSR_IT_2_7) 1417 #define CACHED_CPSR_BITS (CPSR_T | CPSR_AIF | CPSR_GE | CPSR_IT | CPSR_Q \ 1418 | CPSR_NZCV) 1419 /* Bits writable in user mode. */ 1420 #define CPSR_USER (CPSR_NZCV | CPSR_Q | CPSR_GE | CPSR_E) 1421 /* Execution state bits. MRS read as zero, MSR writes ignored. */ 1422 #define CPSR_EXEC (CPSR_T | CPSR_IT | CPSR_J | CPSR_IL) 1423 1424 /* Bit definitions for M profile XPSR. Most are the same as CPSR. */ 1425 #define XPSR_EXCP 0x1ffU 1426 #define XPSR_SPREALIGN (1U << 9) /* Only set in exception stack frames */ 1427 #define XPSR_IT_2_7 CPSR_IT_2_7 1428 #define XPSR_GE CPSR_GE 1429 #define XPSR_SFPA (1U << 20) /* Only set in exception stack frames */ 1430 #define XPSR_T (1U << 24) /* Not the same as CPSR_T ! */ 1431 #define XPSR_IT_0_1 CPSR_IT_0_1 1432 #define XPSR_Q CPSR_Q 1433 #define XPSR_V CPSR_V 1434 #define XPSR_C CPSR_C 1435 #define XPSR_Z CPSR_Z 1436 #define XPSR_N CPSR_N 1437 #define XPSR_NZCV CPSR_NZCV 1438 #define XPSR_IT CPSR_IT 1439 1440 /* Bit definitions for ARMv8 SPSR (PSTATE) format. 1441 * Only these are valid when in AArch64 mode; in 1442 * AArch32 mode SPSRs are basically CPSR-format. 1443 */ 1444 #define PSTATE_SP (1U) 1445 #define PSTATE_M (0xFU) 1446 #define PSTATE_nRW (1U << 4) 1447 #define PSTATE_F (1U << 6) 1448 #define PSTATE_I (1U << 7) 1449 #define PSTATE_A (1U << 8) 1450 #define PSTATE_D (1U << 9) 1451 #define PSTATE_BTYPE (3U << 10) 1452 #define PSTATE_SSBS (1U << 12) 1453 #define PSTATE_ALLINT (1U << 13) 1454 #define PSTATE_IL (1U << 20) 1455 #define PSTATE_SS (1U << 21) 1456 #define PSTATE_PAN (1U << 22) 1457 #define PSTATE_UAO (1U << 23) 1458 #define PSTATE_DIT (1U << 24) 1459 #define PSTATE_TCO (1U << 25) 1460 #define PSTATE_V (1U << 28) 1461 #define PSTATE_C (1U << 29) 1462 #define PSTATE_Z (1U << 30) 1463 #define PSTATE_N (1U << 31) 1464 #define PSTATE_NZCV (PSTATE_N | PSTATE_Z | PSTATE_C | PSTATE_V) 1465 #define PSTATE_DAIF (PSTATE_D | PSTATE_A | PSTATE_I | PSTATE_F) 1466 #define CACHED_PSTATE_BITS (PSTATE_NZCV | PSTATE_DAIF | PSTATE_BTYPE) 1467 /* Mode values for AArch64 */ 1468 #define PSTATE_MODE_EL3h 13 1469 #define PSTATE_MODE_EL3t 12 1470 #define PSTATE_MODE_EL2h 9 1471 #define PSTATE_MODE_EL2t 8 1472 #define PSTATE_MODE_EL1h 5 1473 #define PSTATE_MODE_EL1t 4 1474 #define PSTATE_MODE_EL0t 0 1475 1476 /* PSTATE bits that are accessed via SVCR and not stored in SPSR_ELx. */ 1477 FIELD(SVCR, SM, 0, 1) 1478 FIELD(SVCR, ZA, 1, 1) 1479 1480 /* Fields for SMCR_ELx. */ 1481 FIELD(SMCR, LEN, 0, 4) 1482 FIELD(SMCR, FA64, 31, 1) 1483 1484 /* Write a new value to v7m.exception, thus transitioning into or out 1485 * of Handler mode; this may result in a change of active stack pointer. 1486 */ 1487 void write_v7m_exception(CPUARMState *env, uint32_t new_exc); 1488 1489 /* Map EL and handler into a PSTATE_MODE. */ 1490 static inline unsigned int aarch64_pstate_mode(unsigned int el, bool handler) 1491 { 1492 return (el << 2) | handler; 1493 } 1494 1495 /* Return the current PSTATE value. For the moment we don't support 32<->64 bit 1496 * interprocessing, so we don't attempt to sync with the cpsr state used by 1497 * the 32 bit decoder. 1498 */ 1499 static inline uint32_t pstate_read(CPUARMState *env) 1500 { 1501 int ZF; 1502 1503 ZF = (env->ZF == 0); 1504 return (env->NF & 0x80000000) | (ZF << 30) 1505 | (env->CF << 29) | ((env->VF & 0x80000000) >> 3) 1506 | env->pstate | env->daif | (env->btype << 10); 1507 } 1508 1509 static inline void pstate_write(CPUARMState *env, uint32_t val) 1510 { 1511 env->ZF = (~val) & PSTATE_Z; 1512 env->NF = val; 1513 env->CF = (val >> 29) & 1; 1514 env->VF = (val << 3) & 0x80000000; 1515 env->daif = val & PSTATE_DAIF; 1516 env->btype = (val >> 10) & 3; 1517 env->pstate = val & ~CACHED_PSTATE_BITS; 1518 } 1519 1520 /* Return the current CPSR value. */ 1521 uint32_t cpsr_read(CPUARMState *env); 1522 1523 typedef enum CPSRWriteType { 1524 CPSRWriteByInstr = 0, /* from guest MSR or CPS */ 1525 CPSRWriteExceptionReturn = 1, /* from guest exception return insn */ 1526 CPSRWriteRaw = 2, 1527 /* trust values, no reg bank switch, no hflags rebuild */ 1528 CPSRWriteByGDBStub = 3, /* from the GDB stub */ 1529 } CPSRWriteType; 1530 1531 /* 1532 * Set the CPSR. Note that some bits of mask must be all-set or all-clear. 1533 * This will do an arm_rebuild_hflags() if any of the bits in @mask 1534 * correspond to TB flags bits cached in the hflags, unless @write_type 1535 * is CPSRWriteRaw. 1536 */ 1537 void cpsr_write(CPUARMState *env, uint32_t val, uint32_t mask, 1538 CPSRWriteType write_type); 1539 1540 /* Return the current xPSR value. */ 1541 static inline uint32_t xpsr_read(CPUARMState *env) 1542 { 1543 int ZF; 1544 ZF = (env->ZF == 0); 1545 return (env->NF & 0x80000000) | (ZF << 30) 1546 | (env->CF << 29) | ((env->VF & 0x80000000) >> 3) | (env->QF << 27) 1547 | (env->thumb << 24) | ((env->condexec_bits & 3) << 25) 1548 | ((env->condexec_bits & 0xfc) << 8) 1549 | (env->GE << 16) 1550 | env->v7m.exception; 1551 } 1552 1553 /* Set the xPSR. Note that some bits of mask must be all-set or all-clear. */ 1554 static inline void xpsr_write(CPUARMState *env, uint32_t val, uint32_t mask) 1555 { 1556 if (mask & XPSR_NZCV) { 1557 env->ZF = (~val) & XPSR_Z; 1558 env->NF = val; 1559 env->CF = (val >> 29) & 1; 1560 env->VF = (val << 3) & 0x80000000; 1561 } 1562 if (mask & XPSR_Q) { 1563 env->QF = ((val & XPSR_Q) != 0); 1564 } 1565 if (mask & XPSR_GE) { 1566 env->GE = (val & XPSR_GE) >> 16; 1567 } 1568 #ifndef CONFIG_USER_ONLY 1569 if (mask & XPSR_T) { 1570 env->thumb = ((val & XPSR_T) != 0); 1571 } 1572 if (mask & XPSR_IT_0_1) { 1573 env->condexec_bits &= ~3; 1574 env->condexec_bits |= (val >> 25) & 3; 1575 } 1576 if (mask & XPSR_IT_2_7) { 1577 env->condexec_bits &= 3; 1578 env->condexec_bits |= (val >> 8) & 0xfc; 1579 } 1580 if (mask & XPSR_EXCP) { 1581 /* Note that this only happens on exception exit */ 1582 write_v7m_exception(env, val & XPSR_EXCP); 1583 } 1584 #endif 1585 } 1586 1587 #define HCR_VM (1ULL << 0) 1588 #define HCR_SWIO (1ULL << 1) 1589 #define HCR_PTW (1ULL << 2) 1590 #define HCR_FMO (1ULL << 3) 1591 #define HCR_IMO (1ULL << 4) 1592 #define HCR_AMO (1ULL << 5) 1593 #define HCR_VF (1ULL << 6) 1594 #define HCR_VI (1ULL << 7) 1595 #define HCR_VSE (1ULL << 8) 1596 #define HCR_FB (1ULL << 9) 1597 #define HCR_BSU_MASK (3ULL << 10) 1598 #define HCR_DC (1ULL << 12) 1599 #define HCR_TWI (1ULL << 13) 1600 #define HCR_TWE (1ULL << 14) 1601 #define HCR_TID0 (1ULL << 15) 1602 #define HCR_TID1 (1ULL << 16) 1603 #define HCR_TID2 (1ULL << 17) 1604 #define HCR_TID3 (1ULL << 18) 1605 #define HCR_TSC (1ULL << 19) 1606 #define HCR_TIDCP (1ULL << 20) 1607 #define HCR_TACR (1ULL << 21) 1608 #define HCR_TSW (1ULL << 22) 1609 #define HCR_TPCP (1ULL << 23) 1610 #define HCR_TPU (1ULL << 24) 1611 #define HCR_TTLB (1ULL << 25) 1612 #define HCR_TVM (1ULL << 26) 1613 #define HCR_TGE (1ULL << 27) 1614 #define HCR_TDZ (1ULL << 28) 1615 #define HCR_HCD (1ULL << 29) 1616 #define HCR_TRVM (1ULL << 30) 1617 #define HCR_RW (1ULL << 31) 1618 #define HCR_CD (1ULL << 32) 1619 #define HCR_ID (1ULL << 33) 1620 #define HCR_E2H (1ULL << 34) 1621 #define HCR_TLOR (1ULL << 35) 1622 #define HCR_TERR (1ULL << 36) 1623 #define HCR_TEA (1ULL << 37) 1624 #define HCR_MIOCNCE (1ULL << 38) 1625 #define HCR_TME (1ULL << 39) 1626 #define HCR_APK (1ULL << 40) 1627 #define HCR_API (1ULL << 41) 1628 #define HCR_NV (1ULL << 42) 1629 #define HCR_NV1 (1ULL << 43) 1630 #define HCR_AT (1ULL << 44) 1631 #define HCR_NV2 (1ULL << 45) 1632 #define HCR_FWB (1ULL << 46) 1633 #define HCR_FIEN (1ULL << 47) 1634 #define HCR_GPF (1ULL << 48) 1635 #define HCR_TID4 (1ULL << 49) 1636 #define HCR_TICAB (1ULL << 50) 1637 #define HCR_AMVOFFEN (1ULL << 51) 1638 #define HCR_TOCU (1ULL << 52) 1639 #define HCR_ENSCXT (1ULL << 53) 1640 #define HCR_TTLBIS (1ULL << 54) 1641 #define HCR_TTLBOS (1ULL << 55) 1642 #define HCR_ATA (1ULL << 56) 1643 #define HCR_DCT (1ULL << 57) 1644 #define HCR_TID5 (1ULL << 58) 1645 #define HCR_TWEDEN (1ULL << 59) 1646 #define HCR_TWEDEL MAKE_64BIT_MASK(60, 4) 1647 1648 #define SCR_NS (1ULL << 0) 1649 #define SCR_IRQ (1ULL << 1) 1650 #define SCR_FIQ (1ULL << 2) 1651 #define SCR_EA (1ULL << 3) 1652 #define SCR_FW (1ULL << 4) 1653 #define SCR_AW (1ULL << 5) 1654 #define SCR_NET (1ULL << 6) 1655 #define SCR_SMD (1ULL << 7) 1656 #define SCR_HCE (1ULL << 8) 1657 #define SCR_SIF (1ULL << 9) 1658 #define SCR_RW (1ULL << 10) 1659 #define SCR_ST (1ULL << 11) 1660 #define SCR_TWI (1ULL << 12) 1661 #define SCR_TWE (1ULL << 13) 1662 #define SCR_TLOR (1ULL << 14) 1663 #define SCR_TERR (1ULL << 15) 1664 #define SCR_APK (1ULL << 16) 1665 #define SCR_API (1ULL << 17) 1666 #define SCR_EEL2 (1ULL << 18) 1667 #define SCR_EASE (1ULL << 19) 1668 #define SCR_NMEA (1ULL << 20) 1669 #define SCR_FIEN (1ULL << 21) 1670 #define SCR_ENSCXT (1ULL << 25) 1671 #define SCR_ATA (1ULL << 26) 1672 #define SCR_FGTEN (1ULL << 27) 1673 #define SCR_ECVEN (1ULL << 28) 1674 #define SCR_TWEDEN (1ULL << 29) 1675 #define SCR_TWEDEL MAKE_64BIT_MASK(30, 4) 1676 #define SCR_TME (1ULL << 34) 1677 #define SCR_AMVOFFEN (1ULL << 35) 1678 #define SCR_ENAS0 (1ULL << 36) 1679 #define SCR_ADEN (1ULL << 37) 1680 #define SCR_HXEN (1ULL << 38) 1681 #define SCR_TRNDR (1ULL << 40) 1682 #define SCR_ENTP2 (1ULL << 41) 1683 #define SCR_GPF (1ULL << 48) 1684 #define SCR_NSE (1ULL << 62) 1685 1686 /* Return the current FPSCR value. */ 1687 uint32_t vfp_get_fpscr(CPUARMState *env); 1688 void vfp_set_fpscr(CPUARMState *env, uint32_t val); 1689 1690 /* 1691 * FPCR, Floating Point Control Register 1692 * FPSR, Floating Point Status Register 1693 * 1694 * For A64 floating point control and status bits are stored in 1695 * two logically distinct registers, FPCR and FPSR. We store these 1696 * in QEMU in vfp.fpcr and vfp.fpsr. 1697 * For A32 there was only one register, FPSCR. The bits are arranged 1698 * such that FPSCR bits map to FPCR or FPSR bits in the same bit positions, 1699 * so we can use appropriate masking to handle FPSCR reads and writes. 1700 * Note that the FPCR has some bits which are not visible in the 1701 * AArch32 view (for FEAT_AFP). Writing the FPSCR leaves these unchanged. 1702 */ 1703 1704 /* FPCR bits */ 1705 #define FPCR_IOE (1 << 8) /* Invalid Operation exception trap enable */ 1706 #define FPCR_DZE (1 << 9) /* Divide by Zero exception trap enable */ 1707 #define FPCR_OFE (1 << 10) /* Overflow exception trap enable */ 1708 #define FPCR_UFE (1 << 11) /* Underflow exception trap enable */ 1709 #define FPCR_IXE (1 << 12) /* Inexact exception trap enable */ 1710 #define FPCR_EBF (1 << 13) /* Extended BFloat16 behaviors */ 1711 #define FPCR_IDE (1 << 15) /* Input Denormal exception trap enable */ 1712 #define FPCR_LEN_MASK (7 << 16) /* LEN, A-profile only */ 1713 #define FPCR_FZ16 (1 << 19) /* ARMv8.2+, FP16 flush-to-zero */ 1714 #define FPCR_STRIDE_MASK (3 << 20) /* Stride */ 1715 #define FPCR_RMODE_MASK (3 << 22) /* Rounding mode */ 1716 #define FPCR_FZ (1 << 24) /* Flush-to-zero enable bit */ 1717 #define FPCR_DN (1 << 25) /* Default NaN enable bit */ 1718 #define FPCR_AHP (1 << 26) /* Alternative half-precision */ 1719 1720 #define FPCR_LTPSIZE_SHIFT 16 /* LTPSIZE, M-profile only */ 1721 #define FPCR_LTPSIZE_MASK (7 << FPCR_LTPSIZE_SHIFT) 1722 #define FPCR_LTPSIZE_LENGTH 3 1723 1724 /* Cumulative exception trap enable bits */ 1725 #define FPCR_EEXC_MASK (FPCR_IOE | FPCR_DZE | FPCR_OFE | FPCR_UFE | FPCR_IXE | FPCR_IDE) 1726 1727 /* FPSR bits */ 1728 #define FPSR_IOC (1 << 0) /* Invalid Operation cumulative exception */ 1729 #define FPSR_DZC (1 << 1) /* Divide by Zero cumulative exception */ 1730 #define FPSR_OFC (1 << 2) /* Overflow cumulative exception */ 1731 #define FPSR_UFC (1 << 3) /* Underflow cumulative exception */ 1732 #define FPSR_IXC (1 << 4) /* Inexact cumulative exception */ 1733 #define FPSR_IDC (1 << 7) /* Input Denormal cumulative exception */ 1734 #define FPSR_QC (1 << 27) /* Cumulative saturation bit */ 1735 #define FPSR_V (1 << 28) /* FP overflow flag */ 1736 #define FPSR_C (1 << 29) /* FP carry flag */ 1737 #define FPSR_Z (1 << 30) /* FP zero flag */ 1738 #define FPSR_N (1 << 31) /* FP negative flag */ 1739 1740 /* Cumulative exception status bits */ 1741 #define FPSR_CEXC_MASK (FPSR_IOC | FPSR_DZC | FPSR_OFC | FPSR_UFC | FPSR_IXC | FPSR_IDC) 1742 1743 #define FPSR_NZCV_MASK (FPSR_N | FPSR_Z | FPSR_C | FPSR_V) 1744 #define FPSR_NZCVQC_MASK (FPSR_NZCV_MASK | FPSR_QC) 1745 1746 /* A32 FPSCR bits which architecturally map to FPSR bits */ 1747 #define FPSCR_FPSR_MASK (FPSR_NZCVQC_MASK | FPSR_CEXC_MASK) 1748 /* A32 FPSCR bits which architecturally map to FPCR bits */ 1749 #define FPSCR_FPCR_MASK (FPCR_EEXC_MASK | FPCR_LEN_MASK | FPCR_FZ16 | \ 1750 FPCR_STRIDE_MASK | FPCR_RMODE_MASK | \ 1751 FPCR_FZ | FPCR_DN | FPCR_AHP) 1752 /* These masks don't overlap: each bit lives in only one place */ 1753 QEMU_BUILD_BUG_ON(FPSCR_FPSR_MASK & FPSCR_FPCR_MASK); 1754 1755 /** 1756 * vfp_get_fpsr: read the AArch64 FPSR 1757 * @env: CPU context 1758 * 1759 * Return the current AArch64 FPSR value 1760 */ 1761 uint32_t vfp_get_fpsr(CPUARMState *env); 1762 1763 /** 1764 * vfp_get_fpcr: read the AArch64 FPCR 1765 * @env: CPU context 1766 * 1767 * Return the current AArch64 FPCR value 1768 */ 1769 uint32_t vfp_get_fpcr(CPUARMState *env); 1770 1771 /** 1772 * vfp_set_fpsr: write the AArch64 FPSR 1773 * @env: CPU context 1774 * @value: new value 1775 */ 1776 void vfp_set_fpsr(CPUARMState *env, uint32_t value); 1777 1778 /** 1779 * vfp_set_fpcr: write the AArch64 FPCR 1780 * @env: CPU context 1781 * @value: new value 1782 */ 1783 void vfp_set_fpcr(CPUARMState *env, uint32_t value); 1784 1785 enum arm_cpu_mode { 1786 ARM_CPU_MODE_USR = 0x10, 1787 ARM_CPU_MODE_FIQ = 0x11, 1788 ARM_CPU_MODE_IRQ = 0x12, 1789 ARM_CPU_MODE_SVC = 0x13, 1790 ARM_CPU_MODE_MON = 0x16, 1791 ARM_CPU_MODE_ABT = 0x17, 1792 ARM_CPU_MODE_HYP = 0x1a, 1793 ARM_CPU_MODE_UND = 0x1b, 1794 ARM_CPU_MODE_SYS = 0x1f 1795 }; 1796 1797 /* VFP system registers. */ 1798 #define ARM_VFP_FPSID 0 1799 #define ARM_VFP_FPSCR 1 1800 #define ARM_VFP_MVFR2 5 1801 #define ARM_VFP_MVFR1 6 1802 #define ARM_VFP_MVFR0 7 1803 #define ARM_VFP_FPEXC 8 1804 #define ARM_VFP_FPINST 9 1805 #define ARM_VFP_FPINST2 10 1806 /* These ones are M-profile only */ 1807 #define ARM_VFP_FPSCR_NZCVQC 2 1808 #define ARM_VFP_VPR 12 1809 #define ARM_VFP_P0 13 1810 #define ARM_VFP_FPCXT_NS 14 1811 #define ARM_VFP_FPCXT_S 15 1812 1813 /* QEMU-internal value meaning "FPSCR, but we care only about NZCV" */ 1814 #define QEMU_VFP_FPSCR_NZCV 0xffff 1815 1816 /* iwMMXt coprocessor control registers. */ 1817 #define ARM_IWMMXT_wCID 0 1818 #define ARM_IWMMXT_wCon 1 1819 #define ARM_IWMMXT_wCSSF 2 1820 #define ARM_IWMMXT_wCASF 3 1821 #define ARM_IWMMXT_wCGR0 8 1822 #define ARM_IWMMXT_wCGR1 9 1823 #define ARM_IWMMXT_wCGR2 10 1824 #define ARM_IWMMXT_wCGR3 11 1825 1826 /* V7M CCR bits */ 1827 FIELD(V7M_CCR, NONBASETHRDENA, 0, 1) 1828 FIELD(V7M_CCR, USERSETMPEND, 1, 1) 1829 FIELD(V7M_CCR, UNALIGN_TRP, 3, 1) 1830 FIELD(V7M_CCR, DIV_0_TRP, 4, 1) 1831 FIELD(V7M_CCR, BFHFNMIGN, 8, 1) 1832 FIELD(V7M_CCR, STKALIGN, 9, 1) 1833 FIELD(V7M_CCR, STKOFHFNMIGN, 10, 1) 1834 FIELD(V7M_CCR, DC, 16, 1) 1835 FIELD(V7M_CCR, IC, 17, 1) 1836 FIELD(V7M_CCR, BP, 18, 1) 1837 FIELD(V7M_CCR, LOB, 19, 1) 1838 FIELD(V7M_CCR, TRD, 20, 1) 1839 1840 /* V7M SCR bits */ 1841 FIELD(V7M_SCR, SLEEPONEXIT, 1, 1) 1842 FIELD(V7M_SCR, SLEEPDEEP, 2, 1) 1843 FIELD(V7M_SCR, SLEEPDEEPS, 3, 1) 1844 FIELD(V7M_SCR, SEVONPEND, 4, 1) 1845 1846 /* V7M AIRCR bits */ 1847 FIELD(V7M_AIRCR, VECTRESET, 0, 1) 1848 FIELD(V7M_AIRCR, VECTCLRACTIVE, 1, 1) 1849 FIELD(V7M_AIRCR, SYSRESETREQ, 2, 1) 1850 FIELD(V7M_AIRCR, SYSRESETREQS, 3, 1) 1851 FIELD(V7M_AIRCR, PRIGROUP, 8, 3) 1852 FIELD(V7M_AIRCR, BFHFNMINS, 13, 1) 1853 FIELD(V7M_AIRCR, PRIS, 14, 1) 1854 FIELD(V7M_AIRCR, ENDIANNESS, 15, 1) 1855 FIELD(V7M_AIRCR, VECTKEY, 16, 16) 1856 1857 /* V7M CFSR bits for MMFSR */ 1858 FIELD(V7M_CFSR, IACCVIOL, 0, 1) 1859 FIELD(V7M_CFSR, DACCVIOL, 1, 1) 1860 FIELD(V7M_CFSR, MUNSTKERR, 3, 1) 1861 FIELD(V7M_CFSR, MSTKERR, 4, 1) 1862 FIELD(V7M_CFSR, MLSPERR, 5, 1) 1863 FIELD(V7M_CFSR, MMARVALID, 7, 1) 1864 1865 /* V7M CFSR bits for BFSR */ 1866 FIELD(V7M_CFSR, IBUSERR, 8 + 0, 1) 1867 FIELD(V7M_CFSR, PRECISERR, 8 + 1, 1) 1868 FIELD(V7M_CFSR, IMPRECISERR, 8 + 2, 1) 1869 FIELD(V7M_CFSR, UNSTKERR, 8 + 3, 1) 1870 FIELD(V7M_CFSR, STKERR, 8 + 4, 1) 1871 FIELD(V7M_CFSR, LSPERR, 8 + 5, 1) 1872 FIELD(V7M_CFSR, BFARVALID, 8 + 7, 1) 1873 1874 /* V7M CFSR bits for UFSR */ 1875 FIELD(V7M_CFSR, UNDEFINSTR, 16 + 0, 1) 1876 FIELD(V7M_CFSR, INVSTATE, 16 + 1, 1) 1877 FIELD(V7M_CFSR, INVPC, 16 + 2, 1) 1878 FIELD(V7M_CFSR, NOCP, 16 + 3, 1) 1879 FIELD(V7M_CFSR, STKOF, 16 + 4, 1) 1880 FIELD(V7M_CFSR, UNALIGNED, 16 + 8, 1) 1881 FIELD(V7M_CFSR, DIVBYZERO, 16 + 9, 1) 1882 1883 /* V7M CFSR bit masks covering all of the subregister bits */ 1884 FIELD(V7M_CFSR, MMFSR, 0, 8) 1885 FIELD(V7M_CFSR, BFSR, 8, 8) 1886 FIELD(V7M_CFSR, UFSR, 16, 16) 1887 1888 /* V7M HFSR bits */ 1889 FIELD(V7M_HFSR, VECTTBL, 1, 1) 1890 FIELD(V7M_HFSR, FORCED, 30, 1) 1891 FIELD(V7M_HFSR, DEBUGEVT, 31, 1) 1892 1893 /* V7M DFSR bits */ 1894 FIELD(V7M_DFSR, HALTED, 0, 1) 1895 FIELD(V7M_DFSR, BKPT, 1, 1) 1896 FIELD(V7M_DFSR, DWTTRAP, 2, 1) 1897 FIELD(V7M_DFSR, VCATCH, 3, 1) 1898 FIELD(V7M_DFSR, EXTERNAL, 4, 1) 1899 1900 /* V7M SFSR bits */ 1901 FIELD(V7M_SFSR, INVEP, 0, 1) 1902 FIELD(V7M_SFSR, INVIS, 1, 1) 1903 FIELD(V7M_SFSR, INVER, 2, 1) 1904 FIELD(V7M_SFSR, AUVIOL, 3, 1) 1905 FIELD(V7M_SFSR, INVTRAN, 4, 1) 1906 FIELD(V7M_SFSR, LSPERR, 5, 1) 1907 FIELD(V7M_SFSR, SFARVALID, 6, 1) 1908 FIELD(V7M_SFSR, LSERR, 7, 1) 1909 1910 /* v7M MPU_CTRL bits */ 1911 FIELD(V7M_MPU_CTRL, ENABLE, 0, 1) 1912 FIELD(V7M_MPU_CTRL, HFNMIENA, 1, 1) 1913 FIELD(V7M_MPU_CTRL, PRIVDEFENA, 2, 1) 1914 1915 /* v7M CLIDR bits */ 1916 FIELD(V7M_CLIDR, CTYPE_ALL, 0, 21) 1917 FIELD(V7M_CLIDR, LOUIS, 21, 3) 1918 FIELD(V7M_CLIDR, LOC, 24, 3) 1919 FIELD(V7M_CLIDR, LOUU, 27, 3) 1920 FIELD(V7M_CLIDR, ICB, 30, 2) 1921 1922 FIELD(V7M_CSSELR, IND, 0, 1) 1923 FIELD(V7M_CSSELR, LEVEL, 1, 3) 1924 /* We use the combination of InD and Level to index into cpu->ccsidr[]; 1925 * define a mask for this and check that it doesn't permit running off 1926 * the end of the array. 1927 */ 1928 FIELD(V7M_CSSELR, INDEX, 0, 4) 1929 1930 /* v7M FPCCR bits */ 1931 FIELD(V7M_FPCCR, LSPACT, 0, 1) 1932 FIELD(V7M_FPCCR, USER, 1, 1) 1933 FIELD(V7M_FPCCR, S, 2, 1) 1934 FIELD(V7M_FPCCR, THREAD, 3, 1) 1935 FIELD(V7M_FPCCR, HFRDY, 4, 1) 1936 FIELD(V7M_FPCCR, MMRDY, 5, 1) 1937 FIELD(V7M_FPCCR, BFRDY, 6, 1) 1938 FIELD(V7M_FPCCR, SFRDY, 7, 1) 1939 FIELD(V7M_FPCCR, MONRDY, 8, 1) 1940 FIELD(V7M_FPCCR, SPLIMVIOL, 9, 1) 1941 FIELD(V7M_FPCCR, UFRDY, 10, 1) 1942 FIELD(V7M_FPCCR, RES0, 11, 15) 1943 FIELD(V7M_FPCCR, TS, 26, 1) 1944 FIELD(V7M_FPCCR, CLRONRETS, 27, 1) 1945 FIELD(V7M_FPCCR, CLRONRET, 28, 1) 1946 FIELD(V7M_FPCCR, LSPENS, 29, 1) 1947 FIELD(V7M_FPCCR, LSPEN, 30, 1) 1948 FIELD(V7M_FPCCR, ASPEN, 31, 1) 1949 /* These bits are banked. Others are non-banked and live in the M_REG_S bank */ 1950 #define R_V7M_FPCCR_BANKED_MASK \ 1951 (R_V7M_FPCCR_LSPACT_MASK | \ 1952 R_V7M_FPCCR_USER_MASK | \ 1953 R_V7M_FPCCR_THREAD_MASK | \ 1954 R_V7M_FPCCR_MMRDY_MASK | \ 1955 R_V7M_FPCCR_SPLIMVIOL_MASK | \ 1956 R_V7M_FPCCR_UFRDY_MASK | \ 1957 R_V7M_FPCCR_ASPEN_MASK) 1958 1959 /* v7M VPR bits */ 1960 FIELD(V7M_VPR, P0, 0, 16) 1961 FIELD(V7M_VPR, MASK01, 16, 4) 1962 FIELD(V7M_VPR, MASK23, 20, 4) 1963 1964 /* 1965 * System register ID fields. 1966 */ 1967 FIELD(CLIDR_EL1, CTYPE1, 0, 3) 1968 FIELD(CLIDR_EL1, CTYPE2, 3, 3) 1969 FIELD(CLIDR_EL1, CTYPE3, 6, 3) 1970 FIELD(CLIDR_EL1, CTYPE4, 9, 3) 1971 FIELD(CLIDR_EL1, CTYPE5, 12, 3) 1972 FIELD(CLIDR_EL1, CTYPE6, 15, 3) 1973 FIELD(CLIDR_EL1, CTYPE7, 18, 3) 1974 FIELD(CLIDR_EL1, LOUIS, 21, 3) 1975 FIELD(CLIDR_EL1, LOC, 24, 3) 1976 FIELD(CLIDR_EL1, LOUU, 27, 3) 1977 FIELD(CLIDR_EL1, ICB, 30, 3) 1978 1979 /* When FEAT_CCIDX is implemented */ 1980 FIELD(CCSIDR_EL1, CCIDX_LINESIZE, 0, 3) 1981 FIELD(CCSIDR_EL1, CCIDX_ASSOCIATIVITY, 3, 21) 1982 FIELD(CCSIDR_EL1, CCIDX_NUMSETS, 32, 24) 1983 1984 /* When FEAT_CCIDX is not implemented */ 1985 FIELD(CCSIDR_EL1, LINESIZE, 0, 3) 1986 FIELD(CCSIDR_EL1, ASSOCIATIVITY, 3, 10) 1987 FIELD(CCSIDR_EL1, NUMSETS, 13, 15) 1988 1989 FIELD(CTR_EL0, IMINLINE, 0, 4) 1990 FIELD(CTR_EL0, L1IP, 14, 2) 1991 FIELD(CTR_EL0, DMINLINE, 16, 4) 1992 FIELD(CTR_EL0, ERG, 20, 4) 1993 FIELD(CTR_EL0, CWG, 24, 4) 1994 FIELD(CTR_EL0, IDC, 28, 1) 1995 FIELD(CTR_EL0, DIC, 29, 1) 1996 FIELD(CTR_EL0, TMINLINE, 32, 6) 1997 1998 FIELD(MIDR_EL1, REVISION, 0, 4) 1999 FIELD(MIDR_EL1, PARTNUM, 4, 12) 2000 FIELD(MIDR_EL1, ARCHITECTURE, 16, 4) 2001 FIELD(MIDR_EL1, VARIANT, 20, 4) 2002 FIELD(MIDR_EL1, IMPLEMENTER, 24, 8) 2003 2004 FIELD(ID_ISAR0, SWAP, 0, 4) 2005 FIELD(ID_ISAR0, BITCOUNT, 4, 4) 2006 FIELD(ID_ISAR0, BITFIELD, 8, 4) 2007 FIELD(ID_ISAR0, CMPBRANCH, 12, 4) 2008 FIELD(ID_ISAR0, COPROC, 16, 4) 2009 FIELD(ID_ISAR0, DEBUG, 20, 4) 2010 FIELD(ID_ISAR0, DIVIDE, 24, 4) 2011 2012 FIELD(ID_ISAR1, ENDIAN, 0, 4) 2013 FIELD(ID_ISAR1, EXCEPT, 4, 4) 2014 FIELD(ID_ISAR1, EXCEPT_AR, 8, 4) 2015 FIELD(ID_ISAR1, EXTEND, 12, 4) 2016 FIELD(ID_ISAR1, IFTHEN, 16, 4) 2017 FIELD(ID_ISAR1, IMMEDIATE, 20, 4) 2018 FIELD(ID_ISAR1, INTERWORK, 24, 4) 2019 FIELD(ID_ISAR1, JAZELLE, 28, 4) 2020 2021 FIELD(ID_ISAR2, LOADSTORE, 0, 4) 2022 FIELD(ID_ISAR2, MEMHINT, 4, 4) 2023 FIELD(ID_ISAR2, MULTIACCESSINT, 8, 4) 2024 FIELD(ID_ISAR2, MULT, 12, 4) 2025 FIELD(ID_ISAR2, MULTS, 16, 4) 2026 FIELD(ID_ISAR2, MULTU, 20, 4) 2027 FIELD(ID_ISAR2, PSR_AR, 24, 4) 2028 FIELD(ID_ISAR2, REVERSAL, 28, 4) 2029 2030 FIELD(ID_ISAR3, SATURATE, 0, 4) 2031 FIELD(ID_ISAR3, SIMD, 4, 4) 2032 FIELD(ID_ISAR3, SVC, 8, 4) 2033 FIELD(ID_ISAR3, SYNCHPRIM, 12, 4) 2034 FIELD(ID_ISAR3, TABBRANCH, 16, 4) 2035 FIELD(ID_ISAR3, T32COPY, 20, 4) 2036 FIELD(ID_ISAR3, TRUENOP, 24, 4) 2037 FIELD(ID_ISAR3, T32EE, 28, 4) 2038 2039 FIELD(ID_ISAR4, UNPRIV, 0, 4) 2040 FIELD(ID_ISAR4, WITHSHIFTS, 4, 4) 2041 FIELD(ID_ISAR4, WRITEBACK, 8, 4) 2042 FIELD(ID_ISAR4, SMC, 12, 4) 2043 FIELD(ID_ISAR4, BARRIER, 16, 4) 2044 FIELD(ID_ISAR4, SYNCHPRIM_FRAC, 20, 4) 2045 FIELD(ID_ISAR4, PSR_M, 24, 4) 2046 FIELD(ID_ISAR4, SWP_FRAC, 28, 4) 2047 2048 FIELD(ID_ISAR5, SEVL, 0, 4) 2049 FIELD(ID_ISAR5, AES, 4, 4) 2050 FIELD(ID_ISAR5, SHA1, 8, 4) 2051 FIELD(ID_ISAR5, SHA2, 12, 4) 2052 FIELD(ID_ISAR5, CRC32, 16, 4) 2053 FIELD(ID_ISAR5, RDM, 24, 4) 2054 FIELD(ID_ISAR5, VCMA, 28, 4) 2055 2056 FIELD(ID_ISAR6, JSCVT, 0, 4) 2057 FIELD(ID_ISAR6, DP, 4, 4) 2058 FIELD(ID_ISAR6, FHM, 8, 4) 2059 FIELD(ID_ISAR6, SB, 12, 4) 2060 FIELD(ID_ISAR6, SPECRES, 16, 4) 2061 FIELD(ID_ISAR6, BF16, 20, 4) 2062 FIELD(ID_ISAR6, I8MM, 24, 4) 2063 2064 FIELD(ID_MMFR0, VMSA, 0, 4) 2065 FIELD(ID_MMFR0, PMSA, 4, 4) 2066 FIELD(ID_MMFR0, OUTERSHR, 8, 4) 2067 FIELD(ID_MMFR0, SHARELVL, 12, 4) 2068 FIELD(ID_MMFR0, TCM, 16, 4) 2069 FIELD(ID_MMFR0, AUXREG, 20, 4) 2070 FIELD(ID_MMFR0, FCSE, 24, 4) 2071 FIELD(ID_MMFR0, INNERSHR, 28, 4) 2072 2073 FIELD(ID_MMFR1, L1HVDVA, 0, 4) 2074 FIELD(ID_MMFR1, L1UNIVA, 4, 4) 2075 FIELD(ID_MMFR1, L1HVDSW, 8, 4) 2076 FIELD(ID_MMFR1, L1UNISW, 12, 4) 2077 FIELD(ID_MMFR1, L1HVD, 16, 4) 2078 FIELD(ID_MMFR1, L1UNI, 20, 4) 2079 FIELD(ID_MMFR1, L1TSTCLN, 24, 4) 2080 FIELD(ID_MMFR1, BPRED, 28, 4) 2081 2082 FIELD(ID_MMFR2, L1HVDFG, 0, 4) 2083 FIELD(ID_MMFR2, L1HVDBG, 4, 4) 2084 FIELD(ID_MMFR2, L1HVDRNG, 8, 4) 2085 FIELD(ID_MMFR2, HVDTLB, 12, 4) 2086 FIELD(ID_MMFR2, UNITLB, 16, 4) 2087 FIELD(ID_MMFR2, MEMBARR, 20, 4) 2088 FIELD(ID_MMFR2, WFISTALL, 24, 4) 2089 FIELD(ID_MMFR2, HWACCFLG, 28, 4) 2090 2091 FIELD(ID_MMFR3, CMAINTVA, 0, 4) 2092 FIELD(ID_MMFR3, CMAINTSW, 4, 4) 2093 FIELD(ID_MMFR3, BPMAINT, 8, 4) 2094 FIELD(ID_MMFR3, MAINTBCST, 12, 4) 2095 FIELD(ID_MMFR3, PAN, 16, 4) 2096 FIELD(ID_MMFR3, COHWALK, 20, 4) 2097 FIELD(ID_MMFR3, CMEMSZ, 24, 4) 2098 FIELD(ID_MMFR3, SUPERSEC, 28, 4) 2099 2100 FIELD(ID_MMFR4, SPECSEI, 0, 4) 2101 FIELD(ID_MMFR4, AC2, 4, 4) 2102 FIELD(ID_MMFR4, XNX, 8, 4) 2103 FIELD(ID_MMFR4, CNP, 12, 4) 2104 FIELD(ID_MMFR4, HPDS, 16, 4) 2105 FIELD(ID_MMFR4, LSM, 20, 4) 2106 FIELD(ID_MMFR4, CCIDX, 24, 4) 2107 FIELD(ID_MMFR4, EVT, 28, 4) 2108 2109 FIELD(ID_MMFR5, ETS, 0, 4) 2110 FIELD(ID_MMFR5, NTLBPA, 4, 4) 2111 2112 FIELD(ID_PFR0, STATE0, 0, 4) 2113 FIELD(ID_PFR0, STATE1, 4, 4) 2114 FIELD(ID_PFR0, STATE2, 8, 4) 2115 FIELD(ID_PFR0, STATE3, 12, 4) 2116 FIELD(ID_PFR0, CSV2, 16, 4) 2117 FIELD(ID_PFR0, AMU, 20, 4) 2118 FIELD(ID_PFR0, DIT, 24, 4) 2119 FIELD(ID_PFR0, RAS, 28, 4) 2120 2121 FIELD(ID_PFR1, PROGMOD, 0, 4) 2122 FIELD(ID_PFR1, SECURITY, 4, 4) 2123 FIELD(ID_PFR1, MPROGMOD, 8, 4) 2124 FIELD(ID_PFR1, VIRTUALIZATION, 12, 4) 2125 FIELD(ID_PFR1, GENTIMER, 16, 4) 2126 FIELD(ID_PFR1, SEC_FRAC, 20, 4) 2127 FIELD(ID_PFR1, VIRT_FRAC, 24, 4) 2128 FIELD(ID_PFR1, GIC, 28, 4) 2129 2130 FIELD(ID_PFR2, CSV3, 0, 4) 2131 FIELD(ID_PFR2, SSBS, 4, 4) 2132 FIELD(ID_PFR2, RAS_FRAC, 8, 4) 2133 2134 FIELD(ID_AA64ISAR0, AES, 4, 4) 2135 FIELD(ID_AA64ISAR0, SHA1, 8, 4) 2136 FIELD(ID_AA64ISAR0, SHA2, 12, 4) 2137 FIELD(ID_AA64ISAR0, CRC32, 16, 4) 2138 FIELD(ID_AA64ISAR0, ATOMIC, 20, 4) 2139 FIELD(ID_AA64ISAR0, TME, 24, 4) 2140 FIELD(ID_AA64ISAR0, RDM, 28, 4) 2141 FIELD(ID_AA64ISAR0, SHA3, 32, 4) 2142 FIELD(ID_AA64ISAR0, SM3, 36, 4) 2143 FIELD(ID_AA64ISAR0, SM4, 40, 4) 2144 FIELD(ID_AA64ISAR0, DP, 44, 4) 2145 FIELD(ID_AA64ISAR0, FHM, 48, 4) 2146 FIELD(ID_AA64ISAR0, TS, 52, 4) 2147 FIELD(ID_AA64ISAR0, TLB, 56, 4) 2148 FIELD(ID_AA64ISAR0, RNDR, 60, 4) 2149 2150 FIELD(ID_AA64ISAR1, DPB, 0, 4) 2151 FIELD(ID_AA64ISAR1, APA, 4, 4) 2152 FIELD(ID_AA64ISAR1, API, 8, 4) 2153 FIELD(ID_AA64ISAR1, JSCVT, 12, 4) 2154 FIELD(ID_AA64ISAR1, FCMA, 16, 4) 2155 FIELD(ID_AA64ISAR1, LRCPC, 20, 4) 2156 FIELD(ID_AA64ISAR1, GPA, 24, 4) 2157 FIELD(ID_AA64ISAR1, GPI, 28, 4) 2158 FIELD(ID_AA64ISAR1, FRINTTS, 32, 4) 2159 FIELD(ID_AA64ISAR1, SB, 36, 4) 2160 FIELD(ID_AA64ISAR1, SPECRES, 40, 4) 2161 FIELD(ID_AA64ISAR1, BF16, 44, 4) 2162 FIELD(ID_AA64ISAR1, DGH, 48, 4) 2163 FIELD(ID_AA64ISAR1, I8MM, 52, 4) 2164 FIELD(ID_AA64ISAR1, XS, 56, 4) 2165 FIELD(ID_AA64ISAR1, LS64, 60, 4) 2166 2167 FIELD(ID_AA64ISAR2, WFXT, 0, 4) 2168 FIELD(ID_AA64ISAR2, RPRES, 4, 4) 2169 FIELD(ID_AA64ISAR2, GPA3, 8, 4) 2170 FIELD(ID_AA64ISAR2, APA3, 12, 4) 2171 FIELD(ID_AA64ISAR2, MOPS, 16, 4) 2172 FIELD(ID_AA64ISAR2, BC, 20, 4) 2173 FIELD(ID_AA64ISAR2, PAC_FRAC, 24, 4) 2174 FIELD(ID_AA64ISAR2, CLRBHB, 28, 4) 2175 FIELD(ID_AA64ISAR2, SYSREG_128, 32, 4) 2176 FIELD(ID_AA64ISAR2, SYSINSTR_128, 36, 4) 2177 FIELD(ID_AA64ISAR2, PRFMSLC, 40, 4) 2178 FIELD(ID_AA64ISAR2, RPRFM, 48, 4) 2179 FIELD(ID_AA64ISAR2, CSSC, 52, 4) 2180 FIELD(ID_AA64ISAR2, ATS1A, 60, 4) 2181 2182 FIELD(ID_AA64PFR0, EL0, 0, 4) 2183 FIELD(ID_AA64PFR0, EL1, 4, 4) 2184 FIELD(ID_AA64PFR0, EL2, 8, 4) 2185 FIELD(ID_AA64PFR0, EL3, 12, 4) 2186 FIELD(ID_AA64PFR0, FP, 16, 4) 2187 FIELD(ID_AA64PFR0, ADVSIMD, 20, 4) 2188 FIELD(ID_AA64PFR0, GIC, 24, 4) 2189 FIELD(ID_AA64PFR0, RAS, 28, 4) 2190 FIELD(ID_AA64PFR0, SVE, 32, 4) 2191 FIELD(ID_AA64PFR0, SEL2, 36, 4) 2192 FIELD(ID_AA64PFR0, MPAM, 40, 4) 2193 FIELD(ID_AA64PFR0, AMU, 44, 4) 2194 FIELD(ID_AA64PFR0, DIT, 48, 4) 2195 FIELD(ID_AA64PFR0, RME, 52, 4) 2196 FIELD(ID_AA64PFR0, CSV2, 56, 4) 2197 FIELD(ID_AA64PFR0, CSV3, 60, 4) 2198 2199 FIELD(ID_AA64PFR1, BT, 0, 4) 2200 FIELD(ID_AA64PFR1, SSBS, 4, 4) 2201 FIELD(ID_AA64PFR1, MTE, 8, 4) 2202 FIELD(ID_AA64PFR1, RAS_FRAC, 12, 4) 2203 FIELD(ID_AA64PFR1, MPAM_FRAC, 16, 4) 2204 FIELD(ID_AA64PFR1, SME, 24, 4) 2205 FIELD(ID_AA64PFR1, RNDR_TRAP, 28, 4) 2206 FIELD(ID_AA64PFR1, CSV2_FRAC, 32, 4) 2207 FIELD(ID_AA64PFR1, NMI, 36, 4) 2208 FIELD(ID_AA64PFR1, MTE_FRAC, 40, 4) 2209 FIELD(ID_AA64PFR1, GCS, 44, 4) 2210 FIELD(ID_AA64PFR1, THE, 48, 4) 2211 FIELD(ID_AA64PFR1, MTEX, 52, 4) 2212 FIELD(ID_AA64PFR1, DF2, 56, 4) 2213 FIELD(ID_AA64PFR1, PFAR, 60, 4) 2214 2215 FIELD(ID_AA64MMFR0, PARANGE, 0, 4) 2216 FIELD(ID_AA64MMFR0, ASIDBITS, 4, 4) 2217 FIELD(ID_AA64MMFR0, BIGEND, 8, 4) 2218 FIELD(ID_AA64MMFR0, SNSMEM, 12, 4) 2219 FIELD(ID_AA64MMFR0, BIGENDEL0, 16, 4) 2220 FIELD(ID_AA64MMFR0, TGRAN16, 20, 4) 2221 FIELD(ID_AA64MMFR0, TGRAN64, 24, 4) 2222 FIELD(ID_AA64MMFR0, TGRAN4, 28, 4) 2223 FIELD(ID_AA64MMFR0, TGRAN16_2, 32, 4) 2224 FIELD(ID_AA64MMFR0, TGRAN64_2, 36, 4) 2225 FIELD(ID_AA64MMFR0, TGRAN4_2, 40, 4) 2226 FIELD(ID_AA64MMFR0, EXS, 44, 4) 2227 FIELD(ID_AA64MMFR0, FGT, 56, 4) 2228 FIELD(ID_AA64MMFR0, ECV, 60, 4) 2229 2230 FIELD(ID_AA64MMFR1, HAFDBS, 0, 4) 2231 FIELD(ID_AA64MMFR1, VMIDBITS, 4, 4) 2232 FIELD(ID_AA64MMFR1, VH, 8, 4) 2233 FIELD(ID_AA64MMFR1, HPDS, 12, 4) 2234 FIELD(ID_AA64MMFR1, LO, 16, 4) 2235 FIELD(ID_AA64MMFR1, PAN, 20, 4) 2236 FIELD(ID_AA64MMFR1, SPECSEI, 24, 4) 2237 FIELD(ID_AA64MMFR1, XNX, 28, 4) 2238 FIELD(ID_AA64MMFR1, TWED, 32, 4) 2239 FIELD(ID_AA64MMFR1, ETS, 36, 4) 2240 FIELD(ID_AA64MMFR1, HCX, 40, 4) 2241 FIELD(ID_AA64MMFR1, AFP, 44, 4) 2242 FIELD(ID_AA64MMFR1, NTLBPA, 48, 4) 2243 FIELD(ID_AA64MMFR1, TIDCP1, 52, 4) 2244 FIELD(ID_AA64MMFR1, CMOW, 56, 4) 2245 FIELD(ID_AA64MMFR1, ECBHB, 60, 4) 2246 2247 FIELD(ID_AA64MMFR2, CNP, 0, 4) 2248 FIELD(ID_AA64MMFR2, UAO, 4, 4) 2249 FIELD(ID_AA64MMFR2, LSM, 8, 4) 2250 FIELD(ID_AA64MMFR2, IESB, 12, 4) 2251 FIELD(ID_AA64MMFR2, VARANGE, 16, 4) 2252 FIELD(ID_AA64MMFR2, CCIDX, 20, 4) 2253 FIELD(ID_AA64MMFR2, NV, 24, 4) 2254 FIELD(ID_AA64MMFR2, ST, 28, 4) 2255 FIELD(ID_AA64MMFR2, AT, 32, 4) 2256 FIELD(ID_AA64MMFR2, IDS, 36, 4) 2257 FIELD(ID_AA64MMFR2, FWB, 40, 4) 2258 FIELD(ID_AA64MMFR2, TTL, 48, 4) 2259 FIELD(ID_AA64MMFR2, BBM, 52, 4) 2260 FIELD(ID_AA64MMFR2, EVT, 56, 4) 2261 FIELD(ID_AA64MMFR2, E0PD, 60, 4) 2262 2263 FIELD(ID_AA64MMFR3, TCRX, 0, 4) 2264 FIELD(ID_AA64MMFR3, SCTLRX, 4, 4) 2265 FIELD(ID_AA64MMFR3, S1PIE, 8, 4) 2266 FIELD(ID_AA64MMFR3, S2PIE, 12, 4) 2267 FIELD(ID_AA64MMFR3, S1POE, 16, 4) 2268 FIELD(ID_AA64MMFR3, S2POE, 20, 4) 2269 FIELD(ID_AA64MMFR3, AIE, 24, 4) 2270 FIELD(ID_AA64MMFR3, MEC, 28, 4) 2271 FIELD(ID_AA64MMFR3, D128, 32, 4) 2272 FIELD(ID_AA64MMFR3, D128_2, 36, 4) 2273 FIELD(ID_AA64MMFR3, SNERR, 40, 4) 2274 FIELD(ID_AA64MMFR3, ANERR, 44, 4) 2275 FIELD(ID_AA64MMFR3, SDERR, 52, 4) 2276 FIELD(ID_AA64MMFR3, ADERR, 56, 4) 2277 FIELD(ID_AA64MMFR3, SPEC_FPACC, 60, 4) 2278 2279 FIELD(ID_AA64DFR0, DEBUGVER, 0, 4) 2280 FIELD(ID_AA64DFR0, TRACEVER, 4, 4) 2281 FIELD(ID_AA64DFR0, PMUVER, 8, 4) 2282 FIELD(ID_AA64DFR0, BRPS, 12, 4) 2283 FIELD(ID_AA64DFR0, PMSS, 16, 4) 2284 FIELD(ID_AA64DFR0, WRPS, 20, 4) 2285 FIELD(ID_AA64DFR0, SEBEP, 24, 4) 2286 FIELD(ID_AA64DFR0, CTX_CMPS, 28, 4) 2287 FIELD(ID_AA64DFR0, PMSVER, 32, 4) 2288 FIELD(ID_AA64DFR0, DOUBLELOCK, 36, 4) 2289 FIELD(ID_AA64DFR0, TRACEFILT, 40, 4) 2290 FIELD(ID_AA64DFR0, TRACEBUFFER, 44, 4) 2291 FIELD(ID_AA64DFR0, MTPMU, 48, 4) 2292 FIELD(ID_AA64DFR0, BRBE, 52, 4) 2293 FIELD(ID_AA64DFR0, EXTTRCBUFF, 56, 4) 2294 FIELD(ID_AA64DFR0, HPMN0, 60, 4) 2295 2296 FIELD(ID_AA64ZFR0, SVEVER, 0, 4) 2297 FIELD(ID_AA64ZFR0, AES, 4, 4) 2298 FIELD(ID_AA64ZFR0, BITPERM, 16, 4) 2299 FIELD(ID_AA64ZFR0, BFLOAT16, 20, 4) 2300 FIELD(ID_AA64ZFR0, B16B16, 24, 4) 2301 FIELD(ID_AA64ZFR0, SHA3, 32, 4) 2302 FIELD(ID_AA64ZFR0, SM4, 40, 4) 2303 FIELD(ID_AA64ZFR0, I8MM, 44, 4) 2304 FIELD(ID_AA64ZFR0, F32MM, 52, 4) 2305 FIELD(ID_AA64ZFR0, F64MM, 56, 4) 2306 2307 FIELD(ID_AA64SMFR0, F32F32, 32, 1) 2308 FIELD(ID_AA64SMFR0, BI32I32, 33, 1) 2309 FIELD(ID_AA64SMFR0, B16F32, 34, 1) 2310 FIELD(ID_AA64SMFR0, F16F32, 35, 1) 2311 FIELD(ID_AA64SMFR0, I8I32, 36, 4) 2312 FIELD(ID_AA64SMFR0, F16F16, 42, 1) 2313 FIELD(ID_AA64SMFR0, B16B16, 43, 1) 2314 FIELD(ID_AA64SMFR0, I16I32, 44, 4) 2315 FIELD(ID_AA64SMFR0, F64F64, 48, 1) 2316 FIELD(ID_AA64SMFR0, I16I64, 52, 4) 2317 FIELD(ID_AA64SMFR0, SMEVER, 56, 4) 2318 FIELD(ID_AA64SMFR0, FA64, 63, 1) 2319 2320 FIELD(ID_DFR0, COPDBG, 0, 4) 2321 FIELD(ID_DFR0, COPSDBG, 4, 4) 2322 FIELD(ID_DFR0, MMAPDBG, 8, 4) 2323 FIELD(ID_DFR0, COPTRC, 12, 4) 2324 FIELD(ID_DFR0, MMAPTRC, 16, 4) 2325 FIELD(ID_DFR0, MPROFDBG, 20, 4) 2326 FIELD(ID_DFR0, PERFMON, 24, 4) 2327 FIELD(ID_DFR0, TRACEFILT, 28, 4) 2328 2329 FIELD(ID_DFR1, MTPMU, 0, 4) 2330 FIELD(ID_DFR1, HPMN0, 4, 4) 2331 2332 FIELD(DBGDIDR, SE_IMP, 12, 1) 2333 FIELD(DBGDIDR, NSUHD_IMP, 14, 1) 2334 FIELD(DBGDIDR, VERSION, 16, 4) 2335 FIELD(DBGDIDR, CTX_CMPS, 20, 4) 2336 FIELD(DBGDIDR, BRPS, 24, 4) 2337 FIELD(DBGDIDR, WRPS, 28, 4) 2338 2339 FIELD(DBGDEVID, PCSAMPLE, 0, 4) 2340 FIELD(DBGDEVID, WPADDRMASK, 4, 4) 2341 FIELD(DBGDEVID, BPADDRMASK, 8, 4) 2342 FIELD(DBGDEVID, VECTORCATCH, 12, 4) 2343 FIELD(DBGDEVID, VIRTEXTNS, 16, 4) 2344 FIELD(DBGDEVID, DOUBLELOCK, 20, 4) 2345 FIELD(DBGDEVID, AUXREGS, 24, 4) 2346 FIELD(DBGDEVID, CIDMASK, 28, 4) 2347 2348 FIELD(DBGDEVID1, PCSROFFSET, 0, 4) 2349 2350 FIELD(MVFR0, SIMDREG, 0, 4) 2351 FIELD(MVFR0, FPSP, 4, 4) 2352 FIELD(MVFR0, FPDP, 8, 4) 2353 FIELD(MVFR0, FPTRAP, 12, 4) 2354 FIELD(MVFR0, FPDIVIDE, 16, 4) 2355 FIELD(MVFR0, FPSQRT, 20, 4) 2356 FIELD(MVFR0, FPSHVEC, 24, 4) 2357 FIELD(MVFR0, FPROUND, 28, 4) 2358 2359 FIELD(MVFR1, FPFTZ, 0, 4) 2360 FIELD(MVFR1, FPDNAN, 4, 4) 2361 FIELD(MVFR1, SIMDLS, 8, 4) /* A-profile only */ 2362 FIELD(MVFR1, SIMDINT, 12, 4) /* A-profile only */ 2363 FIELD(MVFR1, SIMDSP, 16, 4) /* A-profile only */ 2364 FIELD(MVFR1, SIMDHP, 20, 4) /* A-profile only */ 2365 FIELD(MVFR1, MVE, 8, 4) /* M-profile only */ 2366 FIELD(MVFR1, FP16, 20, 4) /* M-profile only */ 2367 FIELD(MVFR1, FPHP, 24, 4) 2368 FIELD(MVFR1, SIMDFMAC, 28, 4) 2369 2370 FIELD(MVFR2, SIMDMISC, 0, 4) 2371 FIELD(MVFR2, FPMISC, 4, 4) 2372 2373 FIELD(GPCCR, PPS, 0, 3) 2374 FIELD(GPCCR, IRGN, 8, 2) 2375 FIELD(GPCCR, ORGN, 10, 2) 2376 FIELD(GPCCR, SH, 12, 2) 2377 FIELD(GPCCR, PGS, 14, 2) 2378 FIELD(GPCCR, GPC, 16, 1) 2379 FIELD(GPCCR, GPCP, 17, 1) 2380 FIELD(GPCCR, L0GPTSZ, 20, 4) 2381 2382 FIELD(MFAR, FPA, 12, 40) 2383 FIELD(MFAR, NSE, 62, 1) 2384 FIELD(MFAR, NS, 63, 1) 2385 2386 QEMU_BUILD_BUG_ON(ARRAY_SIZE(((ARMCPU *)0)->ccsidr) <= R_V7M_CSSELR_INDEX_MASK); 2387 2388 /* If adding a feature bit which corresponds to a Linux ELF 2389 * HWCAP bit, remember to update the feature-bit-to-hwcap 2390 * mapping in linux-user/elfload.c:get_elf_hwcap(). 2391 */ 2392 enum arm_features { 2393 ARM_FEATURE_AUXCR, /* ARM1026 Auxiliary control register. */ 2394 ARM_FEATURE_XSCALE, /* Intel XScale extensions. */ 2395 ARM_FEATURE_IWMMXT, /* Intel iwMMXt extension. */ 2396 ARM_FEATURE_V6, 2397 ARM_FEATURE_V6K, 2398 ARM_FEATURE_V7, 2399 ARM_FEATURE_THUMB2, 2400 ARM_FEATURE_PMSA, /* no MMU; may have Memory Protection Unit */ 2401 ARM_FEATURE_NEON, 2402 ARM_FEATURE_M, /* Microcontroller profile. */ 2403 ARM_FEATURE_OMAPCP, /* OMAP specific CP15 ops handling. */ 2404 ARM_FEATURE_THUMB2EE, 2405 ARM_FEATURE_V7MP, /* v7 Multiprocessing Extensions */ 2406 ARM_FEATURE_V7VE, /* v7 Virtualization Extensions (non-EL2 parts) */ 2407 ARM_FEATURE_V4T, 2408 ARM_FEATURE_V5, 2409 ARM_FEATURE_STRONGARM, 2410 ARM_FEATURE_VAPA, /* cp15 VA to PA lookups */ 2411 ARM_FEATURE_GENERIC_TIMER, 2412 ARM_FEATURE_MVFR, /* Media and VFP Feature Registers 0 and 1 */ 2413 ARM_FEATURE_DUMMY_C15_REGS, /* RAZ/WI all of cp15 crn=15 */ 2414 ARM_FEATURE_CACHE_TEST_CLEAN, /* 926/1026 style test-and-clean ops */ 2415 ARM_FEATURE_CACHE_DIRTY_REG, /* 1136/1176 cache dirty status register */ 2416 ARM_FEATURE_CACHE_BLOCK_OPS, /* v6 optional cache block operations */ 2417 ARM_FEATURE_MPIDR, /* has cp15 MPIDR */ 2418 ARM_FEATURE_LPAE, /* has Large Physical Address Extension */ 2419 ARM_FEATURE_V8, 2420 ARM_FEATURE_AARCH64, /* supports 64 bit mode */ 2421 ARM_FEATURE_CBAR, /* has cp15 CBAR */ 2422 ARM_FEATURE_CBAR_RO, /* has cp15 CBAR and it is read-only */ 2423 ARM_FEATURE_EL2, /* has EL2 Virtualization support */ 2424 ARM_FEATURE_EL3, /* has EL3 Secure monitor support */ 2425 ARM_FEATURE_THUMB_DSP, /* DSP insns supported in the Thumb encodings */ 2426 ARM_FEATURE_PMU, /* has PMU support */ 2427 ARM_FEATURE_VBAR, /* has cp15 VBAR */ 2428 ARM_FEATURE_M_SECURITY, /* M profile Security Extension */ 2429 ARM_FEATURE_M_MAIN, /* M profile Main Extension */ 2430 ARM_FEATURE_V8_1M, /* M profile extras only in v8.1M and later */ 2431 /* 2432 * ARM_FEATURE_BACKCOMPAT_CNTFRQ makes the CPU default cntfrq be 62.5MHz 2433 * if the board doesn't set a value, instead of 1GHz. It is for backwards 2434 * compatibility and used only with CPU definitions that were already 2435 * in QEMU before we changed the default. It should not be set on any 2436 * CPU types added in future. 2437 */ 2438 ARM_FEATURE_BACKCOMPAT_CNTFRQ, /* 62.5MHz timer default */ 2439 }; 2440 2441 static inline int arm_feature(CPUARMState *env, int feature) 2442 { 2443 return (env->features & (1ULL << feature)) != 0; 2444 } 2445 2446 void arm_cpu_finalize_features(ARMCPU *cpu, Error **errp); 2447 2448 /* 2449 * ARM v9 security states. 2450 * The ordering of the enumeration corresponds to the low 2 bits 2451 * of the GPI value, and (except for Root) the concat of NSE:NS. 2452 */ 2453 2454 typedef enum ARMSecuritySpace { 2455 ARMSS_Secure = 0, 2456 ARMSS_NonSecure = 1, 2457 ARMSS_Root = 2, 2458 ARMSS_Realm = 3, 2459 } ARMSecuritySpace; 2460 2461 /* Return true if @space is secure, in the pre-v9 sense. */ 2462 static inline bool arm_space_is_secure(ARMSecuritySpace space) 2463 { 2464 return space == ARMSS_Secure || space == ARMSS_Root; 2465 } 2466 2467 /* Return the ARMSecuritySpace for @secure, assuming !RME or EL[0-2]. */ 2468 static inline ARMSecuritySpace arm_secure_to_space(bool secure) 2469 { 2470 return secure ? ARMSS_Secure : ARMSS_NonSecure; 2471 } 2472 2473 #if !defined(CONFIG_USER_ONLY) 2474 /** 2475 * arm_security_space_below_el3: 2476 * @env: cpu context 2477 * 2478 * Return the security space of exception levels below EL3, following 2479 * an exception return to those levels. Unlike arm_security_space, 2480 * this doesn't care about the current EL. 2481 */ 2482 ARMSecuritySpace arm_security_space_below_el3(CPUARMState *env); 2483 2484 /** 2485 * arm_is_secure_below_el3: 2486 * @env: cpu context 2487 * 2488 * Return true if exception levels below EL3 are in secure state, 2489 * or would be following an exception return to those levels. 2490 */ 2491 static inline bool arm_is_secure_below_el3(CPUARMState *env) 2492 { 2493 ARMSecuritySpace ss = arm_security_space_below_el3(env); 2494 return ss == ARMSS_Secure; 2495 } 2496 2497 /* Return true if the CPU is AArch64 EL3 or AArch32 Mon */ 2498 static inline bool arm_is_el3_or_mon(CPUARMState *env) 2499 { 2500 assert(!arm_feature(env, ARM_FEATURE_M)); 2501 if (arm_feature(env, ARM_FEATURE_EL3)) { 2502 if (is_a64(env) && extract32(env->pstate, 2, 2) == 3) { 2503 /* CPU currently in AArch64 state and EL3 */ 2504 return true; 2505 } else if (!is_a64(env) && 2506 (env->uncached_cpsr & CPSR_M) == ARM_CPU_MODE_MON) { 2507 /* CPU currently in AArch32 state and monitor mode */ 2508 return true; 2509 } 2510 } 2511 return false; 2512 } 2513 2514 /** 2515 * arm_security_space: 2516 * @env: cpu context 2517 * 2518 * Return the current security space of the cpu. 2519 */ 2520 ARMSecuritySpace arm_security_space(CPUARMState *env); 2521 2522 /** 2523 * arm_is_secure: 2524 * @env: cpu context 2525 * 2526 * Return true if the processor is in secure state. 2527 */ 2528 static inline bool arm_is_secure(CPUARMState *env) 2529 { 2530 return arm_space_is_secure(arm_security_space(env)); 2531 } 2532 2533 /* 2534 * Return true if the current security state has AArch64 EL2 or AArch32 Hyp. 2535 * This corresponds to the pseudocode EL2Enabled(). 2536 */ 2537 static inline bool arm_is_el2_enabled_secstate(CPUARMState *env, 2538 ARMSecuritySpace space) 2539 { 2540 assert(space != ARMSS_Root); 2541 return arm_feature(env, ARM_FEATURE_EL2) 2542 && (space != ARMSS_Secure || (env->cp15.scr_el3 & SCR_EEL2)); 2543 } 2544 2545 static inline bool arm_is_el2_enabled(CPUARMState *env) 2546 { 2547 return arm_is_el2_enabled_secstate(env, arm_security_space_below_el3(env)); 2548 } 2549 2550 #else 2551 static inline ARMSecuritySpace arm_security_space_below_el3(CPUARMState *env) 2552 { 2553 return ARMSS_NonSecure; 2554 } 2555 2556 static inline bool arm_is_secure_below_el3(CPUARMState *env) 2557 { 2558 return false; 2559 } 2560 2561 static inline ARMSecuritySpace arm_security_space(CPUARMState *env) 2562 { 2563 return ARMSS_NonSecure; 2564 } 2565 2566 static inline bool arm_is_secure(CPUARMState *env) 2567 { 2568 return false; 2569 } 2570 2571 static inline bool arm_is_el2_enabled_secstate(CPUARMState *env, 2572 ARMSecuritySpace space) 2573 { 2574 return false; 2575 } 2576 2577 static inline bool arm_is_el2_enabled(CPUARMState *env) 2578 { 2579 return false; 2580 } 2581 #endif 2582 2583 /** 2584 * arm_hcr_el2_eff(): Return the effective value of HCR_EL2. 2585 * E.g. when in secure state, fields in HCR_EL2 are suppressed, 2586 * "for all purposes other than a direct read or write access of HCR_EL2." 2587 * Not included here is HCR_RW. 2588 */ 2589 uint64_t arm_hcr_el2_eff_secstate(CPUARMState *env, ARMSecuritySpace space); 2590 uint64_t arm_hcr_el2_eff(CPUARMState *env); 2591 uint64_t arm_hcrx_el2_eff(CPUARMState *env); 2592 2593 /* Return true if the specified exception level is running in AArch64 state. */ 2594 static inline bool arm_el_is_aa64(CPUARMState *env, int el) 2595 { 2596 /* This isn't valid for EL0 (if we're in EL0, is_a64() is what you want, 2597 * and if we're not in EL0 then the state of EL0 isn't well defined.) 2598 */ 2599 assert(el >= 1 && el <= 3); 2600 bool aa64 = arm_feature(env, ARM_FEATURE_AARCH64); 2601 2602 /* The highest exception level is always at the maximum supported 2603 * register width, and then lower levels have a register width controlled 2604 * by bits in the SCR or HCR registers. 2605 */ 2606 if (el == 3) { 2607 return aa64; 2608 } 2609 2610 if (arm_feature(env, ARM_FEATURE_EL3) && 2611 ((env->cp15.scr_el3 & SCR_NS) || !(env->cp15.scr_el3 & SCR_EEL2))) { 2612 aa64 = aa64 && (env->cp15.scr_el3 & SCR_RW); 2613 } 2614 2615 if (el == 2) { 2616 return aa64; 2617 } 2618 2619 if (arm_is_el2_enabled(env)) { 2620 aa64 = aa64 && (env->cp15.hcr_el2 & HCR_RW); 2621 } 2622 2623 return aa64; 2624 } 2625 2626 /* Function for determining whether guest cp register reads and writes should 2627 * access the secure or non-secure bank of a cp register. When EL3 is 2628 * operating in AArch32 state, the NS-bit determines whether the secure 2629 * instance of a cp register should be used. When EL3 is AArch64 (or if 2630 * it doesn't exist at all) then there is no register banking, and all 2631 * accesses are to the non-secure version. 2632 */ 2633 static inline bool access_secure_reg(CPUARMState *env) 2634 { 2635 bool ret = (arm_feature(env, ARM_FEATURE_EL3) && 2636 !arm_el_is_aa64(env, 3) && 2637 !(env->cp15.scr_el3 & SCR_NS)); 2638 2639 return ret; 2640 } 2641 2642 /* Macros for accessing a specified CP register bank */ 2643 #define A32_BANKED_REG_GET(_env, _regname, _secure) \ 2644 ((_secure) ? (_env)->cp15._regname##_s : (_env)->cp15._regname##_ns) 2645 2646 #define A32_BANKED_REG_SET(_env, _regname, _secure, _val) \ 2647 do { \ 2648 if (_secure) { \ 2649 (_env)->cp15._regname##_s = (_val); \ 2650 } else { \ 2651 (_env)->cp15._regname##_ns = (_val); \ 2652 } \ 2653 } while (0) 2654 2655 /* Macros for automatically accessing a specific CP register bank depending on 2656 * the current secure state of the system. These macros are not intended for 2657 * supporting instruction translation reads/writes as these are dependent 2658 * solely on the SCR.NS bit and not the mode. 2659 */ 2660 #define A32_BANKED_CURRENT_REG_GET(_env, _regname) \ 2661 A32_BANKED_REG_GET((_env), _regname, \ 2662 (arm_is_secure(_env) && !arm_el_is_aa64((_env), 3))) 2663 2664 #define A32_BANKED_CURRENT_REG_SET(_env, _regname, _val) \ 2665 A32_BANKED_REG_SET((_env), _regname, \ 2666 (arm_is_secure(_env) && !arm_el_is_aa64((_env), 3)), \ 2667 (_val)) 2668 2669 uint32_t arm_phys_excp_target_el(CPUState *cs, uint32_t excp_idx, 2670 uint32_t cur_el, bool secure); 2671 2672 /* Return the highest implemented Exception Level */ 2673 static inline int arm_highest_el(CPUARMState *env) 2674 { 2675 if (arm_feature(env, ARM_FEATURE_EL3)) { 2676 return 3; 2677 } 2678 if (arm_feature(env, ARM_FEATURE_EL2)) { 2679 return 2; 2680 } 2681 return 1; 2682 } 2683 2684 /* Return true if a v7M CPU is in Handler mode */ 2685 static inline bool arm_v7m_is_handler_mode(CPUARMState *env) 2686 { 2687 return env->v7m.exception != 0; 2688 } 2689 2690 /* Return the current Exception Level (as per ARMv8; note that this differs 2691 * from the ARMv7 Privilege Level). 2692 */ 2693 static inline int arm_current_el(CPUARMState *env) 2694 { 2695 if (arm_feature(env, ARM_FEATURE_M)) { 2696 return arm_v7m_is_handler_mode(env) || 2697 !(env->v7m.control[env->v7m.secure] & 1); 2698 } 2699 2700 if (is_a64(env)) { 2701 return extract32(env->pstate, 2, 2); 2702 } 2703 2704 switch (env->uncached_cpsr & 0x1f) { 2705 case ARM_CPU_MODE_USR: 2706 return 0; 2707 case ARM_CPU_MODE_HYP: 2708 return 2; 2709 case ARM_CPU_MODE_MON: 2710 return 3; 2711 default: 2712 if (arm_is_secure(env) && !arm_el_is_aa64(env, 3)) { 2713 /* If EL3 is 32-bit then all secure privileged modes run in 2714 * EL3 2715 */ 2716 return 3; 2717 } 2718 2719 return 1; 2720 } 2721 } 2722 2723 /** 2724 * write_list_to_cpustate 2725 * @cpu: ARMCPU 2726 * 2727 * For each register listed in the ARMCPU cpreg_indexes list, write 2728 * its value from the cpreg_values list into the ARMCPUState structure. 2729 * This updates TCG's working data structures from KVM data or 2730 * from incoming migration state. 2731 * 2732 * Returns: true if all register values were updated correctly, 2733 * false if some register was unknown or could not be written. 2734 * Note that we do not stop early on failure -- we will attempt 2735 * writing all registers in the list. 2736 */ 2737 bool write_list_to_cpustate(ARMCPU *cpu); 2738 2739 /** 2740 * write_cpustate_to_list: 2741 * @cpu: ARMCPU 2742 * @kvm_sync: true if this is for syncing back to KVM 2743 * 2744 * For each register listed in the ARMCPU cpreg_indexes list, write 2745 * its value from the ARMCPUState structure into the cpreg_values list. 2746 * This is used to copy info from TCG's working data structures into 2747 * KVM or for outbound migration. 2748 * 2749 * @kvm_sync is true if we are doing this in order to sync the 2750 * register state back to KVM. In this case we will only update 2751 * values in the list if the previous list->cpustate sync actually 2752 * successfully wrote the CPU state. Otherwise we will keep the value 2753 * that is in the list. 2754 * 2755 * Returns: true if all register values were read correctly, 2756 * false if some register was unknown or could not be read. 2757 * Note that we do not stop early on failure -- we will attempt 2758 * reading all registers in the list. 2759 */ 2760 bool write_cpustate_to_list(ARMCPU *cpu, bool kvm_sync); 2761 2762 #define ARM_CPUID_TI915T 0x54029152 2763 #define ARM_CPUID_TI925T 0x54029252 2764 2765 #define CPU_RESOLVING_TYPE TYPE_ARM_CPU 2766 2767 #define TYPE_ARM_HOST_CPU "host-" TYPE_ARM_CPU 2768 2769 /* ARM has the following "translation regimes" (as the ARM ARM calls them): 2770 * 2771 * If EL3 is 64-bit: 2772 * + NonSecure EL1 & 0 stage 1 2773 * + NonSecure EL1 & 0 stage 2 2774 * + NonSecure EL2 2775 * + NonSecure EL2 & 0 (ARMv8.1-VHE) 2776 * + Secure EL1 & 0 stage 1 2777 * + Secure EL1 & 0 stage 2 (FEAT_SEL2) 2778 * + Secure EL2 (FEAT_SEL2) 2779 * + Secure EL2 & 0 (FEAT_SEL2) 2780 * + Realm EL1 & 0 stage 1 (FEAT_RME) 2781 * + Realm EL1 & 0 stage 2 (FEAT_RME) 2782 * + Realm EL2 (FEAT_RME) 2783 * + EL3 2784 * If EL3 is 32-bit: 2785 * + NonSecure PL1 & 0 stage 1 2786 * + NonSecure PL1 & 0 stage 2 2787 * + NonSecure PL2 2788 * + Secure PL1 & 0 2789 * (reminder: for 32 bit EL3, Secure PL1 is *EL3*, not EL1.) 2790 * 2791 * For QEMU, an mmu_idx is not quite the same as a translation regime because: 2792 * 1. we need to split the "EL1 & 0" and "EL2 & 0" regimes into two mmu_idxes, 2793 * because they may differ in access permissions even if the VA->PA map is 2794 * the same 2795 * 2. we want to cache in our TLB the full VA->IPA->PA lookup for a stage 1+2 2796 * translation, which means that we have one mmu_idx that deals with two 2797 * concatenated translation regimes [this sort of combined s1+2 TLB is 2798 * architecturally permitted] 2799 * 3. we don't need to allocate an mmu_idx to translations that we won't be 2800 * handling via the TLB. The only way to do a stage 1 translation without 2801 * the immediate stage 2 translation is via the ATS or AT system insns, 2802 * which can be slow-pathed and always do a page table walk. 2803 * The only use of stage 2 translations is either as part of an s1+2 2804 * lookup or when loading the descriptors during a stage 1 page table walk, 2805 * and in both those cases we don't use the TLB. 2806 * 4. we want to be able to use the TLB for accesses done as part of a 2807 * stage1 page table walk, rather than having to walk the stage2 page 2808 * table over and over. 2809 * 5. we need separate EL1/EL2 mmu_idx for handling the Privileged Access 2810 * Never (PAN) bit within PSTATE. 2811 * 6. we fold together most secure and non-secure regimes for A-profile, 2812 * because there are no banked system registers for aarch64, so the 2813 * process of switching between secure and non-secure is 2814 * already heavyweight. 2815 * 7. we cannot fold together Stage 2 Secure and Stage 2 NonSecure, 2816 * because both are in use simultaneously for Secure EL2. 2817 * 2818 * This gives us the following list of cases: 2819 * 2820 * EL0 EL1&0 stage 1+2 (or AArch32 PL0 PL1&0 stage 1+2) 2821 * EL1 EL1&0 stage 1+2 (or AArch32 PL1 PL1&0 stage 1+2) 2822 * EL1 EL1&0 stage 1+2 +PAN (or AArch32 PL1 PL1&0 stage 1+2 +PAN) 2823 * EL0 EL2&0 2824 * EL2 EL2&0 2825 * EL2 EL2&0 +PAN 2826 * EL2 (aka NS PL2) 2827 * EL3 (not used when EL3 is AArch32) 2828 * Stage2 Secure 2829 * Stage2 NonSecure 2830 * plus one TLB per Physical address space: S, NS, Realm, Root 2831 * 2832 * for a total of 14 different mmu_idx. 2833 * 2834 * Note that when EL3 is AArch32, the usage is potentially confusing 2835 * because the MMU indexes are named for their AArch64 use, so code 2836 * using the ARMMMUIdx_E10_1 might be at EL3, not EL1. This is because 2837 * Secure PL1 is always at EL3. 2838 * 2839 * R profile CPUs have an MPU, but can use the same set of MMU indexes 2840 * as A profile. They only need to distinguish EL0 and EL1 (and 2841 * EL2 for cores like the Cortex-R52). 2842 * 2843 * M profile CPUs are rather different as they do not have a true MMU. 2844 * They have the following different MMU indexes: 2845 * User 2846 * Privileged 2847 * User, execution priority negative (ie the MPU HFNMIENA bit may apply) 2848 * Privileged, execution priority negative (ditto) 2849 * If the CPU supports the v8M Security Extension then there are also: 2850 * Secure User 2851 * Secure Privileged 2852 * Secure User, execution priority negative 2853 * Secure Privileged, execution priority negative 2854 * 2855 * The ARMMMUIdx and the mmu index value used by the core QEMU TLB code 2856 * are not quite the same -- different CPU types (most notably M profile 2857 * vs A/R profile) would like to use MMU indexes with different semantics, 2858 * but since we don't ever need to use all of those in a single CPU we 2859 * can avoid having to set NB_MMU_MODES to "total number of A profile MMU 2860 * modes + total number of M profile MMU modes". The lower bits of 2861 * ARMMMUIdx are the core TLB mmu index, and the higher bits are always 2862 * the same for any particular CPU. 2863 * Variables of type ARMMUIdx are always full values, and the core 2864 * index values are in variables of type 'int'. 2865 * 2866 * Our enumeration includes at the end some entries which are not "true" 2867 * mmu_idx values in that they don't have corresponding TLBs and are only 2868 * valid for doing slow path page table walks. 2869 * 2870 * The constant names here are patterned after the general style of the names 2871 * of the AT/ATS operations. 2872 * The values used are carefully arranged to make mmu_idx => EL lookup easy. 2873 * For M profile we arrange them to have a bit for priv, a bit for negpri 2874 * and a bit for secure. 2875 */ 2876 #define ARM_MMU_IDX_A 0x10 /* A profile */ 2877 #define ARM_MMU_IDX_NOTLB 0x20 /* does not have a TLB */ 2878 #define ARM_MMU_IDX_M 0x40 /* M profile */ 2879 2880 /* Meanings of the bits for M profile mmu idx values */ 2881 #define ARM_MMU_IDX_M_PRIV 0x1 2882 #define ARM_MMU_IDX_M_NEGPRI 0x2 2883 #define ARM_MMU_IDX_M_S 0x4 /* Secure */ 2884 2885 #define ARM_MMU_IDX_TYPE_MASK \ 2886 (ARM_MMU_IDX_A | ARM_MMU_IDX_M | ARM_MMU_IDX_NOTLB) 2887 #define ARM_MMU_IDX_COREIDX_MASK 0xf 2888 2889 typedef enum ARMMMUIdx { 2890 /* 2891 * A-profile. 2892 */ 2893 ARMMMUIdx_E10_0 = 0 | ARM_MMU_IDX_A, 2894 ARMMMUIdx_E20_0 = 1 | ARM_MMU_IDX_A, 2895 ARMMMUIdx_E10_1 = 2 | ARM_MMU_IDX_A, 2896 ARMMMUIdx_E20_2 = 3 | ARM_MMU_IDX_A, 2897 ARMMMUIdx_E10_1_PAN = 4 | ARM_MMU_IDX_A, 2898 ARMMMUIdx_E20_2_PAN = 5 | ARM_MMU_IDX_A, 2899 ARMMMUIdx_E2 = 6 | ARM_MMU_IDX_A, 2900 ARMMMUIdx_E3 = 7 | ARM_MMU_IDX_A, 2901 2902 /* 2903 * Used for second stage of an S12 page table walk, or for descriptor 2904 * loads during first stage of an S1 page table walk. Note that both 2905 * are in use simultaneously for SecureEL2: the security state for 2906 * the S2 ptw is selected by the NS bit from the S1 ptw. 2907 */ 2908 ARMMMUIdx_Stage2_S = 8 | ARM_MMU_IDX_A, 2909 ARMMMUIdx_Stage2 = 9 | ARM_MMU_IDX_A, 2910 2911 /* TLBs with 1-1 mapping to the physical address spaces. */ 2912 ARMMMUIdx_Phys_S = 10 | ARM_MMU_IDX_A, 2913 ARMMMUIdx_Phys_NS = 11 | ARM_MMU_IDX_A, 2914 ARMMMUIdx_Phys_Root = 12 | ARM_MMU_IDX_A, 2915 ARMMMUIdx_Phys_Realm = 13 | ARM_MMU_IDX_A, 2916 2917 /* 2918 * These are not allocated TLBs and are used only for AT system 2919 * instructions or for the first stage of an S12 page table walk. 2920 */ 2921 ARMMMUIdx_Stage1_E0 = 0 | ARM_MMU_IDX_NOTLB, 2922 ARMMMUIdx_Stage1_E1 = 1 | ARM_MMU_IDX_NOTLB, 2923 ARMMMUIdx_Stage1_E1_PAN = 2 | ARM_MMU_IDX_NOTLB, 2924 2925 /* 2926 * M-profile. 2927 */ 2928 ARMMMUIdx_MUser = ARM_MMU_IDX_M, 2929 ARMMMUIdx_MPriv = ARM_MMU_IDX_M | ARM_MMU_IDX_M_PRIV, 2930 ARMMMUIdx_MUserNegPri = ARMMMUIdx_MUser | ARM_MMU_IDX_M_NEGPRI, 2931 ARMMMUIdx_MPrivNegPri = ARMMMUIdx_MPriv | ARM_MMU_IDX_M_NEGPRI, 2932 ARMMMUIdx_MSUser = ARMMMUIdx_MUser | ARM_MMU_IDX_M_S, 2933 ARMMMUIdx_MSPriv = ARMMMUIdx_MPriv | ARM_MMU_IDX_M_S, 2934 ARMMMUIdx_MSUserNegPri = ARMMMUIdx_MUserNegPri | ARM_MMU_IDX_M_S, 2935 ARMMMUIdx_MSPrivNegPri = ARMMMUIdx_MPrivNegPri | ARM_MMU_IDX_M_S, 2936 } ARMMMUIdx; 2937 2938 /* 2939 * Bit macros for the core-mmu-index values for each index, 2940 * for use when calling tlb_flush_by_mmuidx() and friends. 2941 */ 2942 #define TO_CORE_BIT(NAME) \ 2943 ARMMMUIdxBit_##NAME = 1 << (ARMMMUIdx_##NAME & ARM_MMU_IDX_COREIDX_MASK) 2944 2945 typedef enum ARMMMUIdxBit { 2946 TO_CORE_BIT(E10_0), 2947 TO_CORE_BIT(E20_0), 2948 TO_CORE_BIT(E10_1), 2949 TO_CORE_BIT(E10_1_PAN), 2950 TO_CORE_BIT(E2), 2951 TO_CORE_BIT(E20_2), 2952 TO_CORE_BIT(E20_2_PAN), 2953 TO_CORE_BIT(E3), 2954 TO_CORE_BIT(Stage2), 2955 TO_CORE_BIT(Stage2_S), 2956 2957 TO_CORE_BIT(MUser), 2958 TO_CORE_BIT(MPriv), 2959 TO_CORE_BIT(MUserNegPri), 2960 TO_CORE_BIT(MPrivNegPri), 2961 TO_CORE_BIT(MSUser), 2962 TO_CORE_BIT(MSPriv), 2963 TO_CORE_BIT(MSUserNegPri), 2964 TO_CORE_BIT(MSPrivNegPri), 2965 } ARMMMUIdxBit; 2966 2967 #undef TO_CORE_BIT 2968 2969 #define MMU_USER_IDX 0 2970 2971 /* Indexes used when registering address spaces with cpu_address_space_init */ 2972 typedef enum ARMASIdx { 2973 ARMASIdx_NS = 0, 2974 ARMASIdx_S = 1, 2975 ARMASIdx_TagNS = 2, 2976 ARMASIdx_TagS = 3, 2977 } ARMASIdx; 2978 2979 static inline ARMMMUIdx arm_space_to_phys(ARMSecuritySpace space) 2980 { 2981 /* Assert the relative order of the physical mmu indexes. */ 2982 QEMU_BUILD_BUG_ON(ARMSS_Secure != 0); 2983 QEMU_BUILD_BUG_ON(ARMMMUIdx_Phys_NS != ARMMMUIdx_Phys_S + ARMSS_NonSecure); 2984 QEMU_BUILD_BUG_ON(ARMMMUIdx_Phys_Root != ARMMMUIdx_Phys_S + ARMSS_Root); 2985 QEMU_BUILD_BUG_ON(ARMMMUIdx_Phys_Realm != ARMMMUIdx_Phys_S + ARMSS_Realm); 2986 2987 return ARMMMUIdx_Phys_S + space; 2988 } 2989 2990 static inline ARMSecuritySpace arm_phys_to_space(ARMMMUIdx idx) 2991 { 2992 assert(idx >= ARMMMUIdx_Phys_S && idx <= ARMMMUIdx_Phys_Realm); 2993 return idx - ARMMMUIdx_Phys_S; 2994 } 2995 2996 static inline bool arm_v7m_csselr_razwi(ARMCPU *cpu) 2997 { 2998 /* If all the CLIDR.Ctypem bits are 0 there are no caches, and 2999 * CSSELR is RAZ/WI. 3000 */ 3001 return (cpu->clidr & R_V7M_CLIDR_CTYPE_ALL_MASK) != 0; 3002 } 3003 3004 static inline bool arm_sctlr_b(CPUARMState *env) 3005 { 3006 return 3007 /* We need not implement SCTLR.ITD in user-mode emulation, so 3008 * let linux-user ignore the fact that it conflicts with SCTLR_B. 3009 * This lets people run BE32 binaries with "-cpu any". 3010 */ 3011 #ifndef CONFIG_USER_ONLY 3012 !arm_feature(env, ARM_FEATURE_V7) && 3013 #endif 3014 (env->cp15.sctlr_el[1] & SCTLR_B) != 0; 3015 } 3016 3017 uint64_t arm_sctlr(CPUARMState *env, int el); 3018 3019 static inline bool arm_cpu_data_is_big_endian_a32(CPUARMState *env, 3020 bool sctlr_b) 3021 { 3022 #ifdef CONFIG_USER_ONLY 3023 /* 3024 * In system mode, BE32 is modelled in line with the 3025 * architecture (as word-invariant big-endianness), where loads 3026 * and stores are done little endian but from addresses which 3027 * are adjusted by XORing with the appropriate constant. So the 3028 * endianness to use for the raw data access is not affected by 3029 * SCTLR.B. 3030 * In user mode, however, we model BE32 as byte-invariant 3031 * big-endianness (because user-only code cannot tell the 3032 * difference), and so we need to use a data access endianness 3033 * that depends on SCTLR.B. 3034 */ 3035 if (sctlr_b) { 3036 return true; 3037 } 3038 #endif 3039 /* In 32bit endianness is determined by looking at CPSR's E bit */ 3040 return env->uncached_cpsr & CPSR_E; 3041 } 3042 3043 static inline bool arm_cpu_data_is_big_endian_a64(int el, uint64_t sctlr) 3044 { 3045 return sctlr & (el ? SCTLR_EE : SCTLR_E0E); 3046 } 3047 3048 /* Return true if the processor is in big-endian mode. */ 3049 static inline bool arm_cpu_data_is_big_endian(CPUARMState *env) 3050 { 3051 if (!is_a64(env)) { 3052 return arm_cpu_data_is_big_endian_a32(env, arm_sctlr_b(env)); 3053 } else { 3054 int cur_el = arm_current_el(env); 3055 uint64_t sctlr = arm_sctlr(env, cur_el); 3056 return arm_cpu_data_is_big_endian_a64(cur_el, sctlr); 3057 } 3058 } 3059 3060 #include "exec/cpu-all.h" 3061 3062 /* 3063 * We have more than 32-bits worth of state per TB, so we split the data 3064 * between tb->flags and tb->cs_base, which is otherwise unused for ARM. 3065 * We collect these two parts in CPUARMTBFlags where they are named 3066 * flags and flags2 respectively. 3067 * 3068 * The flags that are shared between all execution modes, TBFLAG_ANY, 3069 * are stored in flags. The flags that are specific to a given mode 3070 * are stores in flags2. Since cs_base is sized on the configured 3071 * address size, flags2 always has 64-bits for A64, and a minimum of 3072 * 32-bits for A32 and M32. 3073 * 3074 * The bits for 32-bit A-profile and M-profile partially overlap: 3075 * 3076 * 31 23 11 10 0 3077 * +-------------+----------+----------------+ 3078 * | | | TBFLAG_A32 | 3079 * | TBFLAG_AM32 | +-----+----------+ 3080 * | | |TBFLAG_M32| 3081 * +-------------+----------------+----------+ 3082 * 31 23 6 5 0 3083 * 3084 * Unless otherwise noted, these bits are cached in env->hflags. 3085 */ 3086 FIELD(TBFLAG_ANY, AARCH64_STATE, 0, 1) 3087 FIELD(TBFLAG_ANY, SS_ACTIVE, 1, 1) 3088 FIELD(TBFLAG_ANY, PSTATE__SS, 2, 1) /* Not cached. */ 3089 FIELD(TBFLAG_ANY, BE_DATA, 3, 1) 3090 FIELD(TBFLAG_ANY, MMUIDX, 4, 4) 3091 /* Target EL if we take a floating-point-disabled exception */ 3092 FIELD(TBFLAG_ANY, FPEXC_EL, 8, 2) 3093 /* Memory operations require alignment: SCTLR_ELx.A or CCR.UNALIGN_TRP */ 3094 FIELD(TBFLAG_ANY, ALIGN_MEM, 10, 1) 3095 FIELD(TBFLAG_ANY, PSTATE__IL, 11, 1) 3096 FIELD(TBFLAG_ANY, FGT_ACTIVE, 12, 1) 3097 FIELD(TBFLAG_ANY, FGT_SVC, 13, 1) 3098 3099 /* 3100 * Bit usage when in AArch32 state, both A- and M-profile. 3101 */ 3102 FIELD(TBFLAG_AM32, CONDEXEC, 24, 8) /* Not cached. */ 3103 FIELD(TBFLAG_AM32, THUMB, 23, 1) /* Not cached. */ 3104 3105 /* 3106 * Bit usage when in AArch32 state, for A-profile only. 3107 */ 3108 FIELD(TBFLAG_A32, VECLEN, 0, 3) /* Not cached. */ 3109 FIELD(TBFLAG_A32, VECSTRIDE, 3, 2) /* Not cached. */ 3110 /* 3111 * We store the bottom two bits of the CPAR as TB flags and handle 3112 * checks on the other bits at runtime. This shares the same bits as 3113 * VECSTRIDE, which is OK as no XScale CPU has VFP. 3114 * Not cached, because VECLEN+VECSTRIDE are not cached. 3115 */ 3116 FIELD(TBFLAG_A32, XSCALE_CPAR, 5, 2) 3117 FIELD(TBFLAG_A32, VFPEN, 7, 1) /* Partially cached, minus FPEXC. */ 3118 FIELD(TBFLAG_A32, SCTLR__B, 8, 1) /* Cannot overlap with SCTLR_B */ 3119 FIELD(TBFLAG_A32, HSTR_ACTIVE, 9, 1) 3120 /* 3121 * Indicates whether cp register reads and writes by guest code should access 3122 * the secure or nonsecure bank of banked registers; note that this is not 3123 * the same thing as the current security state of the processor! 3124 */ 3125 FIELD(TBFLAG_A32, NS, 10, 1) 3126 /* 3127 * Indicates that SME Streaming mode is active, and SMCR_ELx.FA64 is not. 3128 * This requires an SME trap from AArch32 mode when using NEON. 3129 */ 3130 FIELD(TBFLAG_A32, SME_TRAP_NONSTREAMING, 11, 1) 3131 /* 3132 * Indicates whether we are in the Secure PL1&0 translation regime 3133 */ 3134 FIELD(TBFLAG_A32, S_PL1_0, 12, 1) 3135 3136 /* 3137 * Bit usage when in AArch32 state, for M-profile only. 3138 */ 3139 /* Handler (ie not Thread) mode */ 3140 FIELD(TBFLAG_M32, HANDLER, 0, 1) 3141 /* Whether we should generate stack-limit checks */ 3142 FIELD(TBFLAG_M32, STACKCHECK, 1, 1) 3143 /* Set if FPCCR.LSPACT is set */ 3144 FIELD(TBFLAG_M32, LSPACT, 2, 1) /* Not cached. */ 3145 /* Set if we must create a new FP context */ 3146 FIELD(TBFLAG_M32, NEW_FP_CTXT_NEEDED, 3, 1) /* Not cached. */ 3147 /* Set if FPCCR.S does not match current security state */ 3148 FIELD(TBFLAG_M32, FPCCR_S_WRONG, 4, 1) /* Not cached. */ 3149 /* Set if MVE insns are definitely not predicated by VPR or LTPSIZE */ 3150 FIELD(TBFLAG_M32, MVE_NO_PRED, 5, 1) /* Not cached. */ 3151 /* Set if in secure mode */ 3152 FIELD(TBFLAG_M32, SECURE, 6, 1) 3153 3154 /* 3155 * Bit usage when in AArch64 state 3156 */ 3157 FIELD(TBFLAG_A64, TBII, 0, 2) 3158 FIELD(TBFLAG_A64, SVEEXC_EL, 2, 2) 3159 /* The current vector length, either NVL or SVL. */ 3160 FIELD(TBFLAG_A64, VL, 4, 4) 3161 FIELD(TBFLAG_A64, PAUTH_ACTIVE, 8, 1) 3162 FIELD(TBFLAG_A64, BT, 9, 1) 3163 FIELD(TBFLAG_A64, BTYPE, 10, 2) /* Not cached. */ 3164 FIELD(TBFLAG_A64, TBID, 12, 2) 3165 FIELD(TBFLAG_A64, UNPRIV, 14, 1) 3166 FIELD(TBFLAG_A64, ATA, 15, 1) 3167 FIELD(TBFLAG_A64, TCMA, 16, 2) 3168 FIELD(TBFLAG_A64, MTE_ACTIVE, 18, 1) 3169 FIELD(TBFLAG_A64, MTE0_ACTIVE, 19, 1) 3170 FIELD(TBFLAG_A64, SMEEXC_EL, 20, 2) 3171 FIELD(TBFLAG_A64, PSTATE_SM, 22, 1) 3172 FIELD(TBFLAG_A64, PSTATE_ZA, 23, 1) 3173 FIELD(TBFLAG_A64, SVL, 24, 4) 3174 /* Indicates that SME Streaming mode is active, and SMCR_ELx.FA64 is not. */ 3175 FIELD(TBFLAG_A64, SME_TRAP_NONSTREAMING, 28, 1) 3176 FIELD(TBFLAG_A64, TRAP_ERET, 29, 1) 3177 FIELD(TBFLAG_A64, NAA, 30, 1) 3178 FIELD(TBFLAG_A64, ATA0, 31, 1) 3179 FIELD(TBFLAG_A64, NV, 32, 1) 3180 FIELD(TBFLAG_A64, NV1, 33, 1) 3181 FIELD(TBFLAG_A64, NV2, 34, 1) 3182 /* Set if FEAT_NV2 RAM accesses use the EL2&0 translation regime */ 3183 FIELD(TBFLAG_A64, NV2_MEM_E20, 35, 1) 3184 /* Set if FEAT_NV2 RAM accesses are big-endian */ 3185 FIELD(TBFLAG_A64, NV2_MEM_BE, 36, 1) 3186 3187 /* 3188 * Helpers for using the above. Note that only the A64 accessors use 3189 * FIELD_DP64() and FIELD_EX64(), because in the other cases the flags 3190 * word either is or might be 32 bits only. 3191 */ 3192 #define DP_TBFLAG_ANY(DST, WHICH, VAL) \ 3193 (DST.flags = FIELD_DP32(DST.flags, TBFLAG_ANY, WHICH, VAL)) 3194 #define DP_TBFLAG_A64(DST, WHICH, VAL) \ 3195 (DST.flags2 = FIELD_DP64(DST.flags2, TBFLAG_A64, WHICH, VAL)) 3196 #define DP_TBFLAG_A32(DST, WHICH, VAL) \ 3197 (DST.flags2 = FIELD_DP32(DST.flags2, TBFLAG_A32, WHICH, VAL)) 3198 #define DP_TBFLAG_M32(DST, WHICH, VAL) \ 3199 (DST.flags2 = FIELD_DP32(DST.flags2, TBFLAG_M32, WHICH, VAL)) 3200 #define DP_TBFLAG_AM32(DST, WHICH, VAL) \ 3201 (DST.flags2 = FIELD_DP32(DST.flags2, TBFLAG_AM32, WHICH, VAL)) 3202 3203 #define EX_TBFLAG_ANY(IN, WHICH) FIELD_EX32(IN.flags, TBFLAG_ANY, WHICH) 3204 #define EX_TBFLAG_A64(IN, WHICH) FIELD_EX64(IN.flags2, TBFLAG_A64, WHICH) 3205 #define EX_TBFLAG_A32(IN, WHICH) FIELD_EX32(IN.flags2, TBFLAG_A32, WHICH) 3206 #define EX_TBFLAG_M32(IN, WHICH) FIELD_EX32(IN.flags2, TBFLAG_M32, WHICH) 3207 #define EX_TBFLAG_AM32(IN, WHICH) FIELD_EX32(IN.flags2, TBFLAG_AM32, WHICH) 3208 3209 /** 3210 * sve_vq 3211 * @env: the cpu context 3212 * 3213 * Return the VL cached within env->hflags, in units of quadwords. 3214 */ 3215 static inline int sve_vq(CPUARMState *env) 3216 { 3217 return EX_TBFLAG_A64(env->hflags, VL) + 1; 3218 } 3219 3220 /** 3221 * sme_vq 3222 * @env: the cpu context 3223 * 3224 * Return the SVL cached within env->hflags, in units of quadwords. 3225 */ 3226 static inline int sme_vq(CPUARMState *env) 3227 { 3228 return EX_TBFLAG_A64(env->hflags, SVL) + 1; 3229 } 3230 3231 static inline bool bswap_code(bool sctlr_b) 3232 { 3233 #ifdef CONFIG_USER_ONLY 3234 /* BE8 (SCTLR.B = 0, TARGET_BIG_ENDIAN = 1) is mixed endian. 3235 * The invalid combination SCTLR.B=1/CPSR.E=1/TARGET_BIG_ENDIAN=0 3236 * would also end up as a mixed-endian mode with BE code, LE data. 3237 */ 3238 return TARGET_BIG_ENDIAN ^ sctlr_b; 3239 #else 3240 /* All code access in ARM is little endian, and there are no loaders 3241 * doing swaps that need to be reversed 3242 */ 3243 return 0; 3244 #endif 3245 } 3246 3247 #ifdef CONFIG_USER_ONLY 3248 static inline bool arm_cpu_bswap_data(CPUARMState *env) 3249 { 3250 return TARGET_BIG_ENDIAN ^ arm_cpu_data_is_big_endian(env); 3251 } 3252 #endif 3253 3254 void cpu_get_tb_cpu_state(CPUARMState *env, vaddr *pc, 3255 uint64_t *cs_base, uint32_t *flags); 3256 3257 enum { 3258 QEMU_PSCI_CONDUIT_DISABLED = 0, 3259 QEMU_PSCI_CONDUIT_SMC = 1, 3260 QEMU_PSCI_CONDUIT_HVC = 2, 3261 }; 3262 3263 #ifndef CONFIG_USER_ONLY 3264 /* Return the address space index to use for a memory access */ 3265 static inline int arm_asidx_from_attrs(CPUState *cs, MemTxAttrs attrs) 3266 { 3267 return attrs.secure ? ARMASIdx_S : ARMASIdx_NS; 3268 } 3269 3270 /* Return the AddressSpace to use for a memory access 3271 * (which depends on whether the access is S or NS, and whether 3272 * the board gave us a separate AddressSpace for S accesses). 3273 */ 3274 static inline AddressSpace *arm_addressspace(CPUState *cs, MemTxAttrs attrs) 3275 { 3276 return cpu_get_address_space(cs, arm_asidx_from_attrs(cs, attrs)); 3277 } 3278 #endif 3279 3280 /** 3281 * arm_register_pre_el_change_hook: 3282 * Register a hook function which will be called immediately before this 3283 * CPU changes exception level or mode. The hook function will be 3284 * passed a pointer to the ARMCPU and the opaque data pointer passed 3285 * to this function when the hook was registered. 3286 * 3287 * Note that if a pre-change hook is called, any registered post-change hooks 3288 * are guaranteed to subsequently be called. 3289 */ 3290 void arm_register_pre_el_change_hook(ARMCPU *cpu, ARMELChangeHookFn *hook, 3291 void *opaque); 3292 /** 3293 * arm_register_el_change_hook: 3294 * Register a hook function which will be called immediately after this 3295 * CPU changes exception level or mode. The hook function will be 3296 * passed a pointer to the ARMCPU and the opaque data pointer passed 3297 * to this function when the hook was registered. 3298 * 3299 * Note that any registered hooks registered here are guaranteed to be called 3300 * if pre-change hooks have been. 3301 */ 3302 void arm_register_el_change_hook(ARMCPU *cpu, ARMELChangeHookFn *hook, void 3303 *opaque); 3304 3305 /** 3306 * arm_rebuild_hflags: 3307 * Rebuild the cached TBFLAGS for arbitrary changed processor state. 3308 */ 3309 void arm_rebuild_hflags(CPUARMState *env); 3310 3311 /** 3312 * aa32_vfp_dreg: 3313 * Return a pointer to the Dn register within env in 32-bit mode. 3314 */ 3315 static inline uint64_t *aa32_vfp_dreg(CPUARMState *env, unsigned regno) 3316 { 3317 return &env->vfp.zregs[regno >> 1].d[regno & 1]; 3318 } 3319 3320 /** 3321 * aa32_vfp_qreg: 3322 * Return a pointer to the Qn register within env in 32-bit mode. 3323 */ 3324 static inline uint64_t *aa32_vfp_qreg(CPUARMState *env, unsigned regno) 3325 { 3326 return &env->vfp.zregs[regno].d[0]; 3327 } 3328 3329 /** 3330 * aa64_vfp_qreg: 3331 * Return a pointer to the Qn register within env in 64-bit mode. 3332 */ 3333 static inline uint64_t *aa64_vfp_qreg(CPUARMState *env, unsigned regno) 3334 { 3335 return &env->vfp.zregs[regno].d[0]; 3336 } 3337 3338 /* Shared between translate-sve.c and sve_helper.c. */ 3339 extern const uint64_t pred_esz_masks[5]; 3340 3341 /* 3342 * AArch64 usage of the PAGE_TARGET_* bits for linux-user. 3343 * Note that with the Linux kernel, PROT_MTE may not be cleared by mprotect 3344 * mprotect but PROT_BTI may be cleared. C.f. the kernel's VM_ARCH_CLEAR. 3345 */ 3346 #define PAGE_BTI PAGE_TARGET_1 3347 #define PAGE_MTE PAGE_TARGET_2 3348 #define PAGE_TARGET_STICKY PAGE_MTE 3349 3350 /* We associate one allocation tag per 16 bytes, the minimum. */ 3351 #define LOG2_TAG_GRANULE 4 3352 #define TAG_GRANULE (1 << LOG2_TAG_GRANULE) 3353 3354 #ifdef CONFIG_USER_ONLY 3355 #define TARGET_PAGE_DATA_SIZE (TARGET_PAGE_SIZE >> (LOG2_TAG_GRANULE + 1)) 3356 #endif 3357 3358 #ifdef TARGET_TAGGED_ADDRESSES 3359 /** 3360 * cpu_untagged_addr: 3361 * @cs: CPU context 3362 * @x: tagged address 3363 * 3364 * Remove any address tag from @x. This is explicitly related to the 3365 * linux syscall TIF_TAGGED_ADDR setting, not TBI in general. 3366 * 3367 * There should be a better place to put this, but we need this in 3368 * include/exec/cpu_ldst.h, and not some place linux-user specific. 3369 */ 3370 static inline target_ulong cpu_untagged_addr(CPUState *cs, target_ulong x) 3371 { 3372 CPUARMState *env = cpu_env(cs); 3373 if (env->tagged_addr_enable) { 3374 /* 3375 * TBI is enabled for userspace but not kernelspace addresses. 3376 * Only clear the tag if bit 55 is clear. 3377 */ 3378 x &= sextract64(x, 0, 56); 3379 } 3380 return x; 3381 } 3382 #endif 3383 3384 #endif 3385