1 /* 2 * ARM virtual CPU header 3 * 4 * Copyright (c) 2003 Fabrice Bellard 5 * 6 * This library is free software; you can redistribute it and/or 7 * modify it under the terms of the GNU Lesser General Public 8 * License as published by the Free Software Foundation; either 9 * version 2 of the License, or (at your option) any later version. 10 * 11 * This library is distributed in the hope that it will be useful, 12 * but WITHOUT ANY WARRANTY; without even the implied warranty of 13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU 14 * Lesser General Public License for more details. 15 * 16 * You should have received a copy of the GNU Lesser General Public 17 * License along with this library; if not, see <http://www.gnu.org/licenses/>. 18 */ 19 20 #ifndef ARM_CPU_H 21 #define ARM_CPU_H 22 23 #include "kvm-consts.h" 24 #include "hw/registerfields.h" 25 26 #if defined(TARGET_AARCH64) 27 /* AArch64 definitions */ 28 # define TARGET_LONG_BITS 64 29 #else 30 # define TARGET_LONG_BITS 32 31 #endif 32 33 /* ARM processors have a weak memory model */ 34 #define TCG_GUEST_DEFAULT_MO (0) 35 36 #define CPUArchState struct CPUARMState 37 38 #include "qemu-common.h" 39 #include "cpu-qom.h" 40 #include "exec/cpu-defs.h" 41 42 #include "fpu/softfloat.h" 43 44 #define EXCP_UDEF 1 /* undefined instruction */ 45 #define EXCP_SWI 2 /* software interrupt */ 46 #define EXCP_PREFETCH_ABORT 3 47 #define EXCP_DATA_ABORT 4 48 #define EXCP_IRQ 5 49 #define EXCP_FIQ 6 50 #define EXCP_BKPT 7 51 #define EXCP_EXCEPTION_EXIT 8 /* Return from v7M exception. */ 52 #define EXCP_KERNEL_TRAP 9 /* Jumped to kernel code page. */ 53 #define EXCP_HVC 11 /* HyperVisor Call */ 54 #define EXCP_HYP_TRAP 12 55 #define EXCP_SMC 13 /* Secure Monitor Call */ 56 #define EXCP_VIRQ 14 57 #define EXCP_VFIQ 15 58 #define EXCP_SEMIHOST 16 /* semihosting call */ 59 #define EXCP_NOCP 17 /* v7M NOCP UsageFault */ 60 #define EXCP_INVSTATE 18 /* v7M INVSTATE UsageFault */ 61 /* NB: add new EXCP_ defines to the array in arm_log_exception() too */ 62 63 #define ARMV7M_EXCP_RESET 1 64 #define ARMV7M_EXCP_NMI 2 65 #define ARMV7M_EXCP_HARD 3 66 #define ARMV7M_EXCP_MEM 4 67 #define ARMV7M_EXCP_BUS 5 68 #define ARMV7M_EXCP_USAGE 6 69 #define ARMV7M_EXCP_SECURE 7 70 #define ARMV7M_EXCP_SVC 11 71 #define ARMV7M_EXCP_DEBUG 12 72 #define ARMV7M_EXCP_PENDSV 14 73 #define ARMV7M_EXCP_SYSTICK 15 74 75 /* For M profile, some registers are banked secure vs non-secure; 76 * these are represented as a 2-element array where the first element 77 * is the non-secure copy and the second is the secure copy. 78 * When the CPU does not have implement the security extension then 79 * only the first element is used. 80 * This means that the copy for the current security state can be 81 * accessed via env->registerfield[env->v7m.secure] (whether the security 82 * extension is implemented or not). 83 */ 84 enum { 85 M_REG_NS = 0, 86 M_REG_S = 1, 87 M_REG_NUM_BANKS = 2, 88 }; 89 90 /* ARM-specific interrupt pending bits. */ 91 #define CPU_INTERRUPT_FIQ CPU_INTERRUPT_TGT_EXT_1 92 #define CPU_INTERRUPT_VIRQ CPU_INTERRUPT_TGT_EXT_2 93 #define CPU_INTERRUPT_VFIQ CPU_INTERRUPT_TGT_EXT_3 94 95 /* The usual mapping for an AArch64 system register to its AArch32 96 * counterpart is for the 32 bit world to have access to the lower 97 * half only (with writes leaving the upper half untouched). It's 98 * therefore useful to be able to pass TCG the offset of the least 99 * significant half of a uint64_t struct member. 100 */ 101 #ifdef HOST_WORDS_BIGENDIAN 102 #define offsetoflow32(S, M) (offsetof(S, M) + sizeof(uint32_t)) 103 #define offsetofhigh32(S, M) offsetof(S, M) 104 #else 105 #define offsetoflow32(S, M) offsetof(S, M) 106 #define offsetofhigh32(S, M) (offsetof(S, M) + sizeof(uint32_t)) 107 #endif 108 109 /* Meanings of the ARMCPU object's four inbound GPIO lines */ 110 #define ARM_CPU_IRQ 0 111 #define ARM_CPU_FIQ 1 112 #define ARM_CPU_VIRQ 2 113 #define ARM_CPU_VFIQ 3 114 115 #define NB_MMU_MODES 7 116 /* ARM-specific extra insn start words: 117 * 1: Conditional execution bits 118 * 2: Partial exception syndrome for data aborts 119 */ 120 #define TARGET_INSN_START_EXTRA_WORDS 2 121 122 /* The 2nd extra word holding syndrome info for data aborts does not use 123 * the upper 6 bits nor the lower 14 bits. We mask and shift it down to 124 * help the sleb128 encoder do a better job. 125 * When restoring the CPU state, we shift it back up. 126 */ 127 #define ARM_INSN_START_WORD2_MASK ((1 << 26) - 1) 128 #define ARM_INSN_START_WORD2_SHIFT 14 129 130 /* We currently assume float and double are IEEE single and double 131 precision respectively. 132 Doing runtime conversions is tricky because VFP registers may contain 133 integer values (eg. as the result of a FTOSI instruction). 134 s<2n> maps to the least significant half of d<n> 135 s<2n+1> maps to the most significant half of d<n> 136 */ 137 138 /* CPU state for each instance of a generic timer (in cp15 c14) */ 139 typedef struct ARMGenericTimer { 140 uint64_t cval; /* Timer CompareValue register */ 141 uint64_t ctl; /* Timer Control register */ 142 } ARMGenericTimer; 143 144 #define GTIMER_PHYS 0 145 #define GTIMER_VIRT 1 146 #define GTIMER_HYP 2 147 #define GTIMER_SEC 3 148 #define NUM_GTIMERS 4 149 150 typedef struct { 151 uint64_t raw_tcr; 152 uint32_t mask; 153 uint32_t base_mask; 154 } TCR; 155 156 typedef struct CPUARMState { 157 /* Regs for current mode. */ 158 uint32_t regs[16]; 159 160 /* 32/64 switch only happens when taking and returning from 161 * exceptions so the overlap semantics are taken care of then 162 * instead of having a complicated union. 163 */ 164 /* Regs for A64 mode. */ 165 uint64_t xregs[32]; 166 uint64_t pc; 167 /* PSTATE isn't an architectural register for ARMv8. However, it is 168 * convenient for us to assemble the underlying state into a 32 bit format 169 * identical to the architectural format used for the SPSR. (This is also 170 * what the Linux kernel's 'pstate' field in signal handlers and KVM's 171 * 'pstate' register are.) Of the PSTATE bits: 172 * NZCV are kept in the split out env->CF/VF/NF/ZF, (which have the same 173 * semantics as for AArch32, as described in the comments on each field) 174 * nRW (also known as M[4]) is kept, inverted, in env->aarch64 175 * DAIF (exception masks) are kept in env->daif 176 * all other bits are stored in their correct places in env->pstate 177 */ 178 uint32_t pstate; 179 uint32_t aarch64; /* 1 if CPU is in aarch64 state; inverse of PSTATE.nRW */ 180 181 /* Frequently accessed CPSR bits are stored separately for efficiency. 182 This contains all the other bits. Use cpsr_{read,write} to access 183 the whole CPSR. */ 184 uint32_t uncached_cpsr; 185 uint32_t spsr; 186 187 /* Banked registers. */ 188 uint64_t banked_spsr[8]; 189 uint32_t banked_r13[8]; 190 uint32_t banked_r14[8]; 191 192 /* These hold r8-r12. */ 193 uint32_t usr_regs[5]; 194 uint32_t fiq_regs[5]; 195 196 /* cpsr flag cache for faster execution */ 197 uint32_t CF; /* 0 or 1 */ 198 uint32_t VF; /* V is the bit 31. All other bits are undefined */ 199 uint32_t NF; /* N is bit 31. All other bits are undefined. */ 200 uint32_t ZF; /* Z set if zero. */ 201 uint32_t QF; /* 0 or 1 */ 202 uint32_t GE; /* cpsr[19:16] */ 203 uint32_t thumb; /* cpsr[5]. 0 = arm mode, 1 = thumb mode. */ 204 uint32_t condexec_bits; /* IT bits. cpsr[15:10,26:25]. */ 205 uint64_t daif; /* exception masks, in the bits they are in PSTATE */ 206 207 uint64_t elr_el[4]; /* AArch64 exception link regs */ 208 uint64_t sp_el[4]; /* AArch64 banked stack pointers */ 209 210 /* System control coprocessor (cp15) */ 211 struct { 212 uint32_t c0_cpuid; 213 union { /* Cache size selection */ 214 struct { 215 uint64_t _unused_csselr0; 216 uint64_t csselr_ns; 217 uint64_t _unused_csselr1; 218 uint64_t csselr_s; 219 }; 220 uint64_t csselr_el[4]; 221 }; 222 union { /* System control register. */ 223 struct { 224 uint64_t _unused_sctlr; 225 uint64_t sctlr_ns; 226 uint64_t hsctlr; 227 uint64_t sctlr_s; 228 }; 229 uint64_t sctlr_el[4]; 230 }; 231 uint64_t cpacr_el1; /* Architectural feature access control register */ 232 uint64_t cptr_el[4]; /* ARMv8 feature trap registers */ 233 uint32_t c1_xscaleauxcr; /* XScale auxiliary control register. */ 234 uint64_t sder; /* Secure debug enable register. */ 235 uint32_t nsacr; /* Non-secure access control register. */ 236 union { /* MMU translation table base 0. */ 237 struct { 238 uint64_t _unused_ttbr0_0; 239 uint64_t ttbr0_ns; 240 uint64_t _unused_ttbr0_1; 241 uint64_t ttbr0_s; 242 }; 243 uint64_t ttbr0_el[4]; 244 }; 245 union { /* MMU translation table base 1. */ 246 struct { 247 uint64_t _unused_ttbr1_0; 248 uint64_t ttbr1_ns; 249 uint64_t _unused_ttbr1_1; 250 uint64_t ttbr1_s; 251 }; 252 uint64_t ttbr1_el[4]; 253 }; 254 uint64_t vttbr_el2; /* Virtualization Translation Table Base. */ 255 /* MMU translation table base control. */ 256 TCR tcr_el[4]; 257 TCR vtcr_el2; /* Virtualization Translation Control. */ 258 uint32_t c2_data; /* MPU data cacheable bits. */ 259 uint32_t c2_insn; /* MPU instruction cacheable bits. */ 260 union { /* MMU domain access control register 261 * MPU write buffer control. 262 */ 263 struct { 264 uint64_t dacr_ns; 265 uint64_t dacr_s; 266 }; 267 struct { 268 uint64_t dacr32_el2; 269 }; 270 }; 271 uint32_t pmsav5_data_ap; /* PMSAv5 MPU data access permissions */ 272 uint32_t pmsav5_insn_ap; /* PMSAv5 MPU insn access permissions */ 273 uint64_t hcr_el2; /* Hypervisor configuration register */ 274 uint64_t scr_el3; /* Secure configuration register. */ 275 union { /* Fault status registers. */ 276 struct { 277 uint64_t ifsr_ns; 278 uint64_t ifsr_s; 279 }; 280 struct { 281 uint64_t ifsr32_el2; 282 }; 283 }; 284 union { 285 struct { 286 uint64_t _unused_dfsr; 287 uint64_t dfsr_ns; 288 uint64_t hsr; 289 uint64_t dfsr_s; 290 }; 291 uint64_t esr_el[4]; 292 }; 293 uint32_t c6_region[8]; /* MPU base/size registers. */ 294 union { /* Fault address registers. */ 295 struct { 296 uint64_t _unused_far0; 297 #ifdef HOST_WORDS_BIGENDIAN 298 uint32_t ifar_ns; 299 uint32_t dfar_ns; 300 uint32_t ifar_s; 301 uint32_t dfar_s; 302 #else 303 uint32_t dfar_ns; 304 uint32_t ifar_ns; 305 uint32_t dfar_s; 306 uint32_t ifar_s; 307 #endif 308 uint64_t _unused_far3; 309 }; 310 uint64_t far_el[4]; 311 }; 312 uint64_t hpfar_el2; 313 uint64_t hstr_el2; 314 union { /* Translation result. */ 315 struct { 316 uint64_t _unused_par_0; 317 uint64_t par_ns; 318 uint64_t _unused_par_1; 319 uint64_t par_s; 320 }; 321 uint64_t par_el[4]; 322 }; 323 324 uint32_t c9_insn; /* Cache lockdown registers. */ 325 uint32_t c9_data; 326 uint64_t c9_pmcr; /* performance monitor control register */ 327 uint64_t c9_pmcnten; /* perf monitor counter enables */ 328 uint32_t c9_pmovsr; /* perf monitor overflow status */ 329 uint32_t c9_pmuserenr; /* perf monitor user enable */ 330 uint64_t c9_pmselr; /* perf monitor counter selection register */ 331 uint64_t c9_pminten; /* perf monitor interrupt enables */ 332 union { /* Memory attribute redirection */ 333 struct { 334 #ifdef HOST_WORDS_BIGENDIAN 335 uint64_t _unused_mair_0; 336 uint32_t mair1_ns; 337 uint32_t mair0_ns; 338 uint64_t _unused_mair_1; 339 uint32_t mair1_s; 340 uint32_t mair0_s; 341 #else 342 uint64_t _unused_mair_0; 343 uint32_t mair0_ns; 344 uint32_t mair1_ns; 345 uint64_t _unused_mair_1; 346 uint32_t mair0_s; 347 uint32_t mair1_s; 348 #endif 349 }; 350 uint64_t mair_el[4]; 351 }; 352 union { /* vector base address register */ 353 struct { 354 uint64_t _unused_vbar; 355 uint64_t vbar_ns; 356 uint64_t hvbar; 357 uint64_t vbar_s; 358 }; 359 uint64_t vbar_el[4]; 360 }; 361 uint32_t mvbar; /* (monitor) vector base address register */ 362 struct { /* FCSE PID. */ 363 uint32_t fcseidr_ns; 364 uint32_t fcseidr_s; 365 }; 366 union { /* Context ID. */ 367 struct { 368 uint64_t _unused_contextidr_0; 369 uint64_t contextidr_ns; 370 uint64_t _unused_contextidr_1; 371 uint64_t contextidr_s; 372 }; 373 uint64_t contextidr_el[4]; 374 }; 375 union { /* User RW Thread register. */ 376 struct { 377 uint64_t tpidrurw_ns; 378 uint64_t tpidrprw_ns; 379 uint64_t htpidr; 380 uint64_t _tpidr_el3; 381 }; 382 uint64_t tpidr_el[4]; 383 }; 384 /* The secure banks of these registers don't map anywhere */ 385 uint64_t tpidrurw_s; 386 uint64_t tpidrprw_s; 387 uint64_t tpidruro_s; 388 389 union { /* User RO Thread register. */ 390 uint64_t tpidruro_ns; 391 uint64_t tpidrro_el[1]; 392 }; 393 uint64_t c14_cntfrq; /* Counter Frequency register */ 394 uint64_t c14_cntkctl; /* Timer Control register */ 395 uint32_t cnthctl_el2; /* Counter/Timer Hyp Control register */ 396 uint64_t cntvoff_el2; /* Counter Virtual Offset register */ 397 ARMGenericTimer c14_timer[NUM_GTIMERS]; 398 uint32_t c15_cpar; /* XScale Coprocessor Access Register */ 399 uint32_t c15_ticonfig; /* TI925T configuration byte. */ 400 uint32_t c15_i_max; /* Maximum D-cache dirty line index. */ 401 uint32_t c15_i_min; /* Minimum D-cache dirty line index. */ 402 uint32_t c15_threadid; /* TI debugger thread-ID. */ 403 uint32_t c15_config_base_address; /* SCU base address. */ 404 uint32_t c15_diagnostic; /* diagnostic register */ 405 uint32_t c15_power_diagnostic; 406 uint32_t c15_power_control; /* power control */ 407 uint64_t dbgbvr[16]; /* breakpoint value registers */ 408 uint64_t dbgbcr[16]; /* breakpoint control registers */ 409 uint64_t dbgwvr[16]; /* watchpoint value registers */ 410 uint64_t dbgwcr[16]; /* watchpoint control registers */ 411 uint64_t mdscr_el1; 412 uint64_t oslsr_el1; /* OS Lock Status */ 413 uint64_t mdcr_el2; 414 uint64_t mdcr_el3; 415 /* If the counter is enabled, this stores the last time the counter 416 * was reset. Otherwise it stores the counter value 417 */ 418 uint64_t c15_ccnt; 419 uint64_t pmccfiltr_el0; /* Performance Monitor Filter Register */ 420 uint64_t vpidr_el2; /* Virtualization Processor ID Register */ 421 uint64_t vmpidr_el2; /* Virtualization Multiprocessor ID Register */ 422 } cp15; 423 424 struct { 425 /* M profile has up to 4 stack pointers: 426 * a Main Stack Pointer and a Process Stack Pointer for each 427 * of the Secure and Non-Secure states. (If the CPU doesn't support 428 * the security extension then it has only two SPs.) 429 * In QEMU we always store the currently active SP in regs[13], 430 * and the non-active SP for the current security state in 431 * v7m.other_sp. The stack pointers for the inactive security state 432 * are stored in other_ss_msp and other_ss_psp. 433 * switch_v7m_security_state() is responsible for rearranging them 434 * when we change security state. 435 */ 436 uint32_t other_sp; 437 uint32_t other_ss_msp; 438 uint32_t other_ss_psp; 439 uint32_t vecbase[M_REG_NUM_BANKS]; 440 uint32_t basepri[M_REG_NUM_BANKS]; 441 uint32_t control[M_REG_NUM_BANKS]; 442 uint32_t ccr[M_REG_NUM_BANKS]; /* Configuration and Control */ 443 uint32_t cfsr[M_REG_NUM_BANKS]; /* Configurable Fault Status */ 444 uint32_t hfsr; /* HardFault Status */ 445 uint32_t dfsr; /* Debug Fault Status Register */ 446 uint32_t mmfar[M_REG_NUM_BANKS]; /* MemManage Fault Address */ 447 uint32_t bfar; /* BusFault Address */ 448 unsigned mpu_ctrl[M_REG_NUM_BANKS]; /* MPU_CTRL */ 449 int exception; 450 uint32_t primask[M_REG_NUM_BANKS]; 451 uint32_t faultmask[M_REG_NUM_BANKS]; 452 uint32_t aircr; /* only holds r/w state if security extn implemented */ 453 uint32_t secure; /* Is CPU in Secure state? (not guest visible) */ 454 } v7m; 455 456 /* Information associated with an exception about to be taken: 457 * code which raises an exception must set cs->exception_index and 458 * the relevant parts of this structure; the cpu_do_interrupt function 459 * will then set the guest-visible registers as part of the exception 460 * entry process. 461 */ 462 struct { 463 uint32_t syndrome; /* AArch64 format syndrome register */ 464 uint32_t fsr; /* AArch32 format fault status register info */ 465 uint64_t vaddress; /* virtual addr associated with exception, if any */ 466 uint32_t target_el; /* EL the exception should be targeted for */ 467 /* If we implement EL2 we will also need to store information 468 * about the intermediate physical address for stage 2 faults. 469 */ 470 } exception; 471 472 /* Thumb-2 EE state. */ 473 uint32_t teecr; 474 uint32_t teehbr; 475 476 /* VFP coprocessor state. */ 477 struct { 478 /* VFP/Neon register state. Note that the mapping between S, D and Q 479 * views of the register bank differs between AArch64 and AArch32: 480 * In AArch32: 481 * Qn = regs[2n+1]:regs[2n] 482 * Dn = regs[n] 483 * Sn = regs[n/2] bits 31..0 for even n, and bits 63..32 for odd n 484 * (and regs[32] to regs[63] are inaccessible) 485 * In AArch64: 486 * Qn = regs[2n+1]:regs[2n] 487 * Dn = regs[2n] 488 * Sn = regs[2n] bits 31..0 489 * This corresponds to the architecturally defined mapping between 490 * the two execution states, and means we do not need to explicitly 491 * map these registers when changing states. 492 */ 493 float64 regs[64]; 494 495 uint32_t xregs[16]; 496 /* We store these fpcsr fields separately for convenience. */ 497 int vec_len; 498 int vec_stride; 499 500 /* scratch space when Tn are not sufficient. */ 501 uint32_t scratch[8]; 502 503 /* fp_status is the "normal" fp status. standard_fp_status retains 504 * values corresponding to the ARM "Standard FPSCR Value", ie 505 * default-NaN, flush-to-zero, round-to-nearest and is used by 506 * any operations (generally Neon) which the architecture defines 507 * as controlled by the standard FPSCR value rather than the FPSCR. 508 * 509 * To avoid having to transfer exception bits around, we simply 510 * say that the FPSCR cumulative exception flags are the logical 511 * OR of the flags in the two fp statuses. This relies on the 512 * only thing which needs to read the exception flags being 513 * an explicit FPSCR read. 514 */ 515 float_status fp_status; 516 float_status standard_fp_status; 517 } vfp; 518 uint64_t exclusive_addr; 519 uint64_t exclusive_val; 520 uint64_t exclusive_high; 521 522 /* iwMMXt coprocessor state. */ 523 struct { 524 uint64_t regs[16]; 525 uint64_t val; 526 527 uint32_t cregs[16]; 528 } iwmmxt; 529 530 #if defined(CONFIG_USER_ONLY) 531 /* For usermode syscall translation. */ 532 int eabi; 533 #endif 534 535 struct CPUBreakpoint *cpu_breakpoint[16]; 536 struct CPUWatchpoint *cpu_watchpoint[16]; 537 538 /* Fields up to this point are cleared by a CPU reset */ 539 struct {} end_reset_fields; 540 541 CPU_COMMON 542 543 /* Fields after CPU_COMMON are preserved across CPU reset. */ 544 545 /* Internal CPU feature flags. */ 546 uint64_t features; 547 548 /* PMSAv7 MPU */ 549 struct { 550 uint32_t *drbar; 551 uint32_t *drsr; 552 uint32_t *dracr; 553 uint32_t rnr[M_REG_NUM_BANKS]; 554 } pmsav7; 555 556 /* PMSAv8 MPU */ 557 struct { 558 /* The PMSAv8 implementation also shares some PMSAv7 config 559 * and state: 560 * pmsav7.rnr (region number register) 561 * pmsav7_dregion (number of configured regions) 562 */ 563 uint32_t *rbar[M_REG_NUM_BANKS]; 564 uint32_t *rlar[M_REG_NUM_BANKS]; 565 uint32_t mair0[M_REG_NUM_BANKS]; 566 uint32_t mair1[M_REG_NUM_BANKS]; 567 } pmsav8; 568 569 void *nvic; 570 const struct arm_boot_info *boot_info; 571 /* Store GICv3CPUState to access from this struct */ 572 void *gicv3state; 573 } CPUARMState; 574 575 /** 576 * ARMELChangeHook: 577 * type of a function which can be registered via arm_register_el_change_hook() 578 * to get callbacks when the CPU changes its exception level or mode. 579 */ 580 typedef void ARMELChangeHook(ARMCPU *cpu, void *opaque); 581 582 583 /* These values map onto the return values for 584 * QEMU_PSCI_0_2_FN_AFFINITY_INFO */ 585 typedef enum ARMPSCIState { 586 PSCI_ON = 0, 587 PSCI_OFF = 1, 588 PSCI_ON_PENDING = 2 589 } ARMPSCIState; 590 591 /** 592 * ARMCPU: 593 * @env: #CPUARMState 594 * 595 * An ARM CPU core. 596 */ 597 struct ARMCPU { 598 /*< private >*/ 599 CPUState parent_obj; 600 /*< public >*/ 601 602 CPUARMState env; 603 604 /* Coprocessor information */ 605 GHashTable *cp_regs; 606 /* For marshalling (mostly coprocessor) register state between the 607 * kernel and QEMU (for KVM) and between two QEMUs (for migration), 608 * we use these arrays. 609 */ 610 /* List of register indexes managed via these arrays; (full KVM style 611 * 64 bit indexes, not CPRegInfo 32 bit indexes) 612 */ 613 uint64_t *cpreg_indexes; 614 /* Values of the registers (cpreg_indexes[i]'s value is cpreg_values[i]) */ 615 uint64_t *cpreg_values; 616 /* Length of the indexes, values, reset_values arrays */ 617 int32_t cpreg_array_len; 618 /* These are used only for migration: incoming data arrives in 619 * these fields and is sanity checked in post_load before copying 620 * to the working data structures above. 621 */ 622 uint64_t *cpreg_vmstate_indexes; 623 uint64_t *cpreg_vmstate_values; 624 int32_t cpreg_vmstate_array_len; 625 626 /* Timers used by the generic (architected) timer */ 627 QEMUTimer *gt_timer[NUM_GTIMERS]; 628 /* GPIO outputs for generic timer */ 629 qemu_irq gt_timer_outputs[NUM_GTIMERS]; 630 /* GPIO output for GICv3 maintenance interrupt signal */ 631 qemu_irq gicv3_maintenance_interrupt; 632 /* GPIO output for the PMU interrupt */ 633 qemu_irq pmu_interrupt; 634 635 /* MemoryRegion to use for secure physical accesses */ 636 MemoryRegion *secure_memory; 637 638 /* 'compatible' string for this CPU for Linux device trees */ 639 const char *dtb_compatible; 640 641 /* PSCI version for this CPU 642 * Bits[31:16] = Major Version 643 * Bits[15:0] = Minor Version 644 */ 645 uint32_t psci_version; 646 647 /* Should CPU start in PSCI powered-off state? */ 648 bool start_powered_off; 649 650 /* Current power state, access guarded by BQL */ 651 ARMPSCIState power_state; 652 653 /* CPU has virtualization extension */ 654 bool has_el2; 655 /* CPU has security extension */ 656 bool has_el3; 657 /* CPU has PMU (Performance Monitor Unit) */ 658 bool has_pmu; 659 660 /* CPU has memory protection unit */ 661 bool has_mpu; 662 /* PMSAv7 MPU number of supported regions */ 663 uint32_t pmsav7_dregion; 664 665 /* PSCI conduit used to invoke PSCI methods 666 * 0 - disabled, 1 - smc, 2 - hvc 667 */ 668 uint32_t psci_conduit; 669 670 /* [QEMU_]KVM_ARM_TARGET_* constant for this CPU, or 671 * QEMU_KVM_ARM_TARGET_NONE if the kernel doesn't support this CPU type. 672 */ 673 uint32_t kvm_target; 674 675 /* KVM init features for this CPU */ 676 uint32_t kvm_init_features[7]; 677 678 /* Uniprocessor system with MP extensions */ 679 bool mp_is_up; 680 681 /* The instance init functions for implementation-specific subclasses 682 * set these fields to specify the implementation-dependent values of 683 * various constant registers and reset values of non-constant 684 * registers. 685 * Some of these might become QOM properties eventually. 686 * Field names match the official register names as defined in the 687 * ARMv7AR ARM Architecture Reference Manual. A reset_ prefix 688 * is used for reset values of non-constant registers; no reset_ 689 * prefix means a constant register. 690 */ 691 uint32_t midr; 692 uint32_t revidr; 693 uint32_t reset_fpsid; 694 uint32_t mvfr0; 695 uint32_t mvfr1; 696 uint32_t mvfr2; 697 uint32_t ctr; 698 uint32_t reset_sctlr; 699 uint32_t id_pfr0; 700 uint32_t id_pfr1; 701 uint32_t id_dfr0; 702 uint32_t pmceid0; 703 uint32_t pmceid1; 704 uint32_t id_afr0; 705 uint32_t id_mmfr0; 706 uint32_t id_mmfr1; 707 uint32_t id_mmfr2; 708 uint32_t id_mmfr3; 709 uint32_t id_mmfr4; 710 uint32_t id_isar0; 711 uint32_t id_isar1; 712 uint32_t id_isar2; 713 uint32_t id_isar3; 714 uint32_t id_isar4; 715 uint32_t id_isar5; 716 uint64_t id_aa64pfr0; 717 uint64_t id_aa64pfr1; 718 uint64_t id_aa64dfr0; 719 uint64_t id_aa64dfr1; 720 uint64_t id_aa64afr0; 721 uint64_t id_aa64afr1; 722 uint64_t id_aa64isar0; 723 uint64_t id_aa64isar1; 724 uint64_t id_aa64mmfr0; 725 uint64_t id_aa64mmfr1; 726 uint32_t dbgdidr; 727 uint32_t clidr; 728 uint64_t mp_affinity; /* MP ID without feature bits */ 729 /* The elements of this array are the CCSIDR values for each cache, 730 * in the order L1DCache, L1ICache, L2DCache, L2ICache, etc. 731 */ 732 uint32_t ccsidr[16]; 733 uint64_t reset_cbar; 734 uint32_t reset_auxcr; 735 bool reset_hivecs; 736 /* DCZ blocksize, in log_2(words), ie low 4 bits of DCZID_EL0 */ 737 uint32_t dcz_blocksize; 738 uint64_t rvbar; 739 740 /* Configurable aspects of GIC cpu interface (which is part of the CPU) */ 741 int gic_num_lrs; /* number of list registers */ 742 int gic_vpribits; /* number of virtual priority bits */ 743 int gic_vprebits; /* number of virtual preemption bits */ 744 745 /* Whether the cfgend input is high (i.e. this CPU should reset into 746 * big-endian mode). This setting isn't used directly: instead it modifies 747 * the reset_sctlr value to have SCTLR_B or SCTLR_EE set, depending on the 748 * architecture version. 749 */ 750 bool cfgend; 751 752 ARMELChangeHook *el_change_hook; 753 void *el_change_hook_opaque; 754 755 int32_t node_id; /* NUMA node this CPU belongs to */ 756 757 /* Used to synchronize KVM and QEMU in-kernel device levels */ 758 uint8_t device_irq_level; 759 }; 760 761 static inline ARMCPU *arm_env_get_cpu(CPUARMState *env) 762 { 763 return container_of(env, ARMCPU, env); 764 } 765 766 uint64_t arm_cpu_mp_affinity(int idx, uint8_t clustersz); 767 768 #define ENV_GET_CPU(e) CPU(arm_env_get_cpu(e)) 769 770 #define ENV_OFFSET offsetof(ARMCPU, env) 771 772 #ifndef CONFIG_USER_ONLY 773 extern const struct VMStateDescription vmstate_arm_cpu; 774 #endif 775 776 void arm_cpu_do_interrupt(CPUState *cpu); 777 void arm_v7m_cpu_do_interrupt(CPUState *cpu); 778 bool arm_cpu_exec_interrupt(CPUState *cpu, int int_req); 779 780 void arm_cpu_dump_state(CPUState *cs, FILE *f, fprintf_function cpu_fprintf, 781 int flags); 782 783 hwaddr arm_cpu_get_phys_page_attrs_debug(CPUState *cpu, vaddr addr, 784 MemTxAttrs *attrs); 785 786 int arm_cpu_gdb_read_register(CPUState *cpu, uint8_t *buf, int reg); 787 int arm_cpu_gdb_write_register(CPUState *cpu, uint8_t *buf, int reg); 788 789 int arm_cpu_write_elf64_note(WriteCoreDumpFunction f, CPUState *cs, 790 int cpuid, void *opaque); 791 int arm_cpu_write_elf32_note(WriteCoreDumpFunction f, CPUState *cs, 792 int cpuid, void *opaque); 793 794 #ifdef TARGET_AARCH64 795 int aarch64_cpu_gdb_read_register(CPUState *cpu, uint8_t *buf, int reg); 796 int aarch64_cpu_gdb_write_register(CPUState *cpu, uint8_t *buf, int reg); 797 #endif 798 799 target_ulong do_arm_semihosting(CPUARMState *env); 800 void aarch64_sync_32_to_64(CPUARMState *env); 801 void aarch64_sync_64_to_32(CPUARMState *env); 802 803 static inline bool is_a64(CPUARMState *env) 804 { 805 return env->aarch64; 806 } 807 808 /* you can call this signal handler from your SIGBUS and SIGSEGV 809 signal handlers to inform the virtual CPU of exceptions. non zero 810 is returned if the signal was handled by the virtual CPU. */ 811 int cpu_arm_signal_handler(int host_signum, void *pinfo, 812 void *puc); 813 814 /** 815 * pmccntr_sync 816 * @env: CPUARMState 817 * 818 * Synchronises the counter in the PMCCNTR. This must always be called twice, 819 * once before any action that might affect the timer and again afterwards. 820 * The function is used to swap the state of the register if required. 821 * This only happens when not in user mode (!CONFIG_USER_ONLY) 822 */ 823 void pmccntr_sync(CPUARMState *env); 824 825 /* SCTLR bit meanings. Several bits have been reused in newer 826 * versions of the architecture; in that case we define constants 827 * for both old and new bit meanings. Code which tests against those 828 * bits should probably check or otherwise arrange that the CPU 829 * is the architectural version it expects. 830 */ 831 #define SCTLR_M (1U << 0) 832 #define SCTLR_A (1U << 1) 833 #define SCTLR_C (1U << 2) 834 #define SCTLR_W (1U << 3) /* up to v6; RAO in v7 */ 835 #define SCTLR_SA (1U << 3) 836 #define SCTLR_P (1U << 4) /* up to v5; RAO in v6 and v7 */ 837 #define SCTLR_SA0 (1U << 4) /* v8 onward, AArch64 only */ 838 #define SCTLR_D (1U << 5) /* up to v5; RAO in v6 */ 839 #define SCTLR_CP15BEN (1U << 5) /* v7 onward */ 840 #define SCTLR_L (1U << 6) /* up to v5; RAO in v6 and v7; RAZ in v8 */ 841 #define SCTLR_B (1U << 7) /* up to v6; RAZ in v7 */ 842 #define SCTLR_ITD (1U << 7) /* v8 onward */ 843 #define SCTLR_S (1U << 8) /* up to v6; RAZ in v7 */ 844 #define SCTLR_SED (1U << 8) /* v8 onward */ 845 #define SCTLR_R (1U << 9) /* up to v6; RAZ in v7 */ 846 #define SCTLR_UMA (1U << 9) /* v8 onward, AArch64 only */ 847 #define SCTLR_F (1U << 10) /* up to v6 */ 848 #define SCTLR_SW (1U << 10) /* v7 onward */ 849 #define SCTLR_Z (1U << 11) 850 #define SCTLR_I (1U << 12) 851 #define SCTLR_V (1U << 13) 852 #define SCTLR_RR (1U << 14) /* up to v7 */ 853 #define SCTLR_DZE (1U << 14) /* v8 onward, AArch64 only */ 854 #define SCTLR_L4 (1U << 15) /* up to v6; RAZ in v7 */ 855 #define SCTLR_UCT (1U << 15) /* v8 onward, AArch64 only */ 856 #define SCTLR_DT (1U << 16) /* up to ??, RAO in v6 and v7 */ 857 #define SCTLR_nTWI (1U << 16) /* v8 onward */ 858 #define SCTLR_HA (1U << 17) 859 #define SCTLR_BR (1U << 17) /* PMSA only */ 860 #define SCTLR_IT (1U << 18) /* up to ??, RAO in v6 and v7 */ 861 #define SCTLR_nTWE (1U << 18) /* v8 onward */ 862 #define SCTLR_WXN (1U << 19) 863 #define SCTLR_ST (1U << 20) /* up to ??, RAZ in v6 */ 864 #define SCTLR_UWXN (1U << 20) /* v7 onward */ 865 #define SCTLR_FI (1U << 21) 866 #define SCTLR_U (1U << 22) 867 #define SCTLR_XP (1U << 23) /* up to v6; v7 onward RAO */ 868 #define SCTLR_VE (1U << 24) /* up to v7 */ 869 #define SCTLR_E0E (1U << 24) /* v8 onward, AArch64 only */ 870 #define SCTLR_EE (1U << 25) 871 #define SCTLR_L2 (1U << 26) /* up to v6, RAZ in v7 */ 872 #define SCTLR_UCI (1U << 26) /* v8 onward, AArch64 only */ 873 #define SCTLR_NMFI (1U << 27) 874 #define SCTLR_TRE (1U << 28) 875 #define SCTLR_AFE (1U << 29) 876 #define SCTLR_TE (1U << 30) 877 878 #define CPTR_TCPAC (1U << 31) 879 #define CPTR_TTA (1U << 20) 880 #define CPTR_TFP (1U << 10) 881 882 #define MDCR_EPMAD (1U << 21) 883 #define MDCR_EDAD (1U << 20) 884 #define MDCR_SPME (1U << 17) 885 #define MDCR_SDD (1U << 16) 886 #define MDCR_SPD (3U << 14) 887 #define MDCR_TDRA (1U << 11) 888 #define MDCR_TDOSA (1U << 10) 889 #define MDCR_TDA (1U << 9) 890 #define MDCR_TDE (1U << 8) 891 #define MDCR_HPME (1U << 7) 892 #define MDCR_TPM (1U << 6) 893 #define MDCR_TPMCR (1U << 5) 894 895 /* Not all of the MDCR_EL3 bits are present in the 32-bit SDCR */ 896 #define SDCR_VALID_MASK (MDCR_EPMAD | MDCR_EDAD | MDCR_SPME | MDCR_SPD) 897 898 #define CPSR_M (0x1fU) 899 #define CPSR_T (1U << 5) 900 #define CPSR_F (1U << 6) 901 #define CPSR_I (1U << 7) 902 #define CPSR_A (1U << 8) 903 #define CPSR_E (1U << 9) 904 #define CPSR_IT_2_7 (0xfc00U) 905 #define CPSR_GE (0xfU << 16) 906 #define CPSR_IL (1U << 20) 907 /* Note that the RESERVED bits include bit 21, which is PSTATE_SS in 908 * an AArch64 SPSR but RES0 in AArch32 SPSR and CPSR. In QEMU we use 909 * env->uncached_cpsr bit 21 to store PSTATE.SS when executing in AArch32, 910 * where it is live state but not accessible to the AArch32 code. 911 */ 912 #define CPSR_RESERVED (0x7U << 21) 913 #define CPSR_J (1U << 24) 914 #define CPSR_IT_0_1 (3U << 25) 915 #define CPSR_Q (1U << 27) 916 #define CPSR_V (1U << 28) 917 #define CPSR_C (1U << 29) 918 #define CPSR_Z (1U << 30) 919 #define CPSR_N (1U << 31) 920 #define CPSR_NZCV (CPSR_N | CPSR_Z | CPSR_C | CPSR_V) 921 #define CPSR_AIF (CPSR_A | CPSR_I | CPSR_F) 922 923 #define CPSR_IT (CPSR_IT_0_1 | CPSR_IT_2_7) 924 #define CACHED_CPSR_BITS (CPSR_T | CPSR_AIF | CPSR_GE | CPSR_IT | CPSR_Q \ 925 | CPSR_NZCV) 926 /* Bits writable in user mode. */ 927 #define CPSR_USER (CPSR_NZCV | CPSR_Q | CPSR_GE) 928 /* Execution state bits. MRS read as zero, MSR writes ignored. */ 929 #define CPSR_EXEC (CPSR_T | CPSR_IT | CPSR_J | CPSR_IL) 930 /* Mask of bits which may be set by exception return copying them from SPSR */ 931 #define CPSR_ERET_MASK (~CPSR_RESERVED) 932 933 /* Bit definitions for M profile XPSR. Most are the same as CPSR. */ 934 #define XPSR_EXCP 0x1ffU 935 #define XPSR_SPREALIGN (1U << 9) /* Only set in exception stack frames */ 936 #define XPSR_IT_2_7 CPSR_IT_2_7 937 #define XPSR_GE CPSR_GE 938 #define XPSR_SFPA (1U << 20) /* Only set in exception stack frames */ 939 #define XPSR_T (1U << 24) /* Not the same as CPSR_T ! */ 940 #define XPSR_IT_0_1 CPSR_IT_0_1 941 #define XPSR_Q CPSR_Q 942 #define XPSR_V CPSR_V 943 #define XPSR_C CPSR_C 944 #define XPSR_Z CPSR_Z 945 #define XPSR_N CPSR_N 946 #define XPSR_NZCV CPSR_NZCV 947 #define XPSR_IT CPSR_IT 948 949 #define TTBCR_N (7U << 0) /* TTBCR.EAE==0 */ 950 #define TTBCR_T0SZ (7U << 0) /* TTBCR.EAE==1 */ 951 #define TTBCR_PD0 (1U << 4) 952 #define TTBCR_PD1 (1U << 5) 953 #define TTBCR_EPD0 (1U << 7) 954 #define TTBCR_IRGN0 (3U << 8) 955 #define TTBCR_ORGN0 (3U << 10) 956 #define TTBCR_SH0 (3U << 12) 957 #define TTBCR_T1SZ (3U << 16) 958 #define TTBCR_A1 (1U << 22) 959 #define TTBCR_EPD1 (1U << 23) 960 #define TTBCR_IRGN1 (3U << 24) 961 #define TTBCR_ORGN1 (3U << 26) 962 #define TTBCR_SH1 (1U << 28) 963 #define TTBCR_EAE (1U << 31) 964 965 /* Bit definitions for ARMv8 SPSR (PSTATE) format. 966 * Only these are valid when in AArch64 mode; in 967 * AArch32 mode SPSRs are basically CPSR-format. 968 */ 969 #define PSTATE_SP (1U) 970 #define PSTATE_M (0xFU) 971 #define PSTATE_nRW (1U << 4) 972 #define PSTATE_F (1U << 6) 973 #define PSTATE_I (1U << 7) 974 #define PSTATE_A (1U << 8) 975 #define PSTATE_D (1U << 9) 976 #define PSTATE_IL (1U << 20) 977 #define PSTATE_SS (1U << 21) 978 #define PSTATE_V (1U << 28) 979 #define PSTATE_C (1U << 29) 980 #define PSTATE_Z (1U << 30) 981 #define PSTATE_N (1U << 31) 982 #define PSTATE_NZCV (PSTATE_N | PSTATE_Z | PSTATE_C | PSTATE_V) 983 #define PSTATE_DAIF (PSTATE_D | PSTATE_A | PSTATE_I | PSTATE_F) 984 #define CACHED_PSTATE_BITS (PSTATE_NZCV | PSTATE_DAIF) 985 /* Mode values for AArch64 */ 986 #define PSTATE_MODE_EL3h 13 987 #define PSTATE_MODE_EL3t 12 988 #define PSTATE_MODE_EL2h 9 989 #define PSTATE_MODE_EL2t 8 990 #define PSTATE_MODE_EL1h 5 991 #define PSTATE_MODE_EL1t 4 992 #define PSTATE_MODE_EL0t 0 993 994 /* Map EL and handler into a PSTATE_MODE. */ 995 static inline unsigned int aarch64_pstate_mode(unsigned int el, bool handler) 996 { 997 return (el << 2) | handler; 998 } 999 1000 /* Return the current PSTATE value. For the moment we don't support 32<->64 bit 1001 * interprocessing, so we don't attempt to sync with the cpsr state used by 1002 * the 32 bit decoder. 1003 */ 1004 static inline uint32_t pstate_read(CPUARMState *env) 1005 { 1006 int ZF; 1007 1008 ZF = (env->ZF == 0); 1009 return (env->NF & 0x80000000) | (ZF << 30) 1010 | (env->CF << 29) | ((env->VF & 0x80000000) >> 3) 1011 | env->pstate | env->daif; 1012 } 1013 1014 static inline void pstate_write(CPUARMState *env, uint32_t val) 1015 { 1016 env->ZF = (~val) & PSTATE_Z; 1017 env->NF = val; 1018 env->CF = (val >> 29) & 1; 1019 env->VF = (val << 3) & 0x80000000; 1020 env->daif = val & PSTATE_DAIF; 1021 env->pstate = val & ~CACHED_PSTATE_BITS; 1022 } 1023 1024 /* Return the current CPSR value. */ 1025 uint32_t cpsr_read(CPUARMState *env); 1026 1027 typedef enum CPSRWriteType { 1028 CPSRWriteByInstr = 0, /* from guest MSR or CPS */ 1029 CPSRWriteExceptionReturn = 1, /* from guest exception return insn */ 1030 CPSRWriteRaw = 2, /* trust values, do not switch reg banks */ 1031 CPSRWriteByGDBStub = 3, /* from the GDB stub */ 1032 } CPSRWriteType; 1033 1034 /* Set the CPSR. Note that some bits of mask must be all-set or all-clear.*/ 1035 void cpsr_write(CPUARMState *env, uint32_t val, uint32_t mask, 1036 CPSRWriteType write_type); 1037 1038 /* Return the current xPSR value. */ 1039 static inline uint32_t xpsr_read(CPUARMState *env) 1040 { 1041 int ZF; 1042 ZF = (env->ZF == 0); 1043 return (env->NF & 0x80000000) | (ZF << 30) 1044 | (env->CF << 29) | ((env->VF & 0x80000000) >> 3) | (env->QF << 27) 1045 | (env->thumb << 24) | ((env->condexec_bits & 3) << 25) 1046 | ((env->condexec_bits & 0xfc) << 8) 1047 | env->v7m.exception; 1048 } 1049 1050 /* Set the xPSR. Note that some bits of mask must be all-set or all-clear. */ 1051 static inline void xpsr_write(CPUARMState *env, uint32_t val, uint32_t mask) 1052 { 1053 if (mask & XPSR_NZCV) { 1054 env->ZF = (~val) & XPSR_Z; 1055 env->NF = val; 1056 env->CF = (val >> 29) & 1; 1057 env->VF = (val << 3) & 0x80000000; 1058 } 1059 if (mask & XPSR_Q) { 1060 env->QF = ((val & XPSR_Q) != 0); 1061 } 1062 if (mask & XPSR_T) { 1063 env->thumb = ((val & XPSR_T) != 0); 1064 } 1065 if (mask & XPSR_IT_0_1) { 1066 env->condexec_bits &= ~3; 1067 env->condexec_bits |= (val >> 25) & 3; 1068 } 1069 if (mask & XPSR_IT_2_7) { 1070 env->condexec_bits &= 3; 1071 env->condexec_bits |= (val >> 8) & 0xfc; 1072 } 1073 if (mask & XPSR_EXCP) { 1074 env->v7m.exception = val & XPSR_EXCP; 1075 } 1076 } 1077 1078 #define HCR_VM (1ULL << 0) 1079 #define HCR_SWIO (1ULL << 1) 1080 #define HCR_PTW (1ULL << 2) 1081 #define HCR_FMO (1ULL << 3) 1082 #define HCR_IMO (1ULL << 4) 1083 #define HCR_AMO (1ULL << 5) 1084 #define HCR_VF (1ULL << 6) 1085 #define HCR_VI (1ULL << 7) 1086 #define HCR_VSE (1ULL << 8) 1087 #define HCR_FB (1ULL << 9) 1088 #define HCR_BSU_MASK (3ULL << 10) 1089 #define HCR_DC (1ULL << 12) 1090 #define HCR_TWI (1ULL << 13) 1091 #define HCR_TWE (1ULL << 14) 1092 #define HCR_TID0 (1ULL << 15) 1093 #define HCR_TID1 (1ULL << 16) 1094 #define HCR_TID2 (1ULL << 17) 1095 #define HCR_TID3 (1ULL << 18) 1096 #define HCR_TSC (1ULL << 19) 1097 #define HCR_TIDCP (1ULL << 20) 1098 #define HCR_TACR (1ULL << 21) 1099 #define HCR_TSW (1ULL << 22) 1100 #define HCR_TPC (1ULL << 23) 1101 #define HCR_TPU (1ULL << 24) 1102 #define HCR_TTLB (1ULL << 25) 1103 #define HCR_TVM (1ULL << 26) 1104 #define HCR_TGE (1ULL << 27) 1105 #define HCR_TDZ (1ULL << 28) 1106 #define HCR_HCD (1ULL << 29) 1107 #define HCR_TRVM (1ULL << 30) 1108 #define HCR_RW (1ULL << 31) 1109 #define HCR_CD (1ULL << 32) 1110 #define HCR_ID (1ULL << 33) 1111 #define HCR_MASK ((1ULL << 34) - 1) 1112 1113 #define SCR_NS (1U << 0) 1114 #define SCR_IRQ (1U << 1) 1115 #define SCR_FIQ (1U << 2) 1116 #define SCR_EA (1U << 3) 1117 #define SCR_FW (1U << 4) 1118 #define SCR_AW (1U << 5) 1119 #define SCR_NET (1U << 6) 1120 #define SCR_SMD (1U << 7) 1121 #define SCR_HCE (1U << 8) 1122 #define SCR_SIF (1U << 9) 1123 #define SCR_RW (1U << 10) 1124 #define SCR_ST (1U << 11) 1125 #define SCR_TWI (1U << 12) 1126 #define SCR_TWE (1U << 13) 1127 #define SCR_AARCH32_MASK (0x3fff & ~(SCR_RW | SCR_ST)) 1128 #define SCR_AARCH64_MASK (0x3fff & ~SCR_NET) 1129 1130 /* Return the current FPSCR value. */ 1131 uint32_t vfp_get_fpscr(CPUARMState *env); 1132 void vfp_set_fpscr(CPUARMState *env, uint32_t val); 1133 1134 /* For A64 the FPSCR is split into two logically distinct registers, 1135 * FPCR and FPSR. However since they still use non-overlapping bits 1136 * we store the underlying state in fpscr and just mask on read/write. 1137 */ 1138 #define FPSR_MASK 0xf800009f 1139 #define FPCR_MASK 0x07f79f00 1140 static inline uint32_t vfp_get_fpsr(CPUARMState *env) 1141 { 1142 return vfp_get_fpscr(env) & FPSR_MASK; 1143 } 1144 1145 static inline void vfp_set_fpsr(CPUARMState *env, uint32_t val) 1146 { 1147 uint32_t new_fpscr = (vfp_get_fpscr(env) & ~FPSR_MASK) | (val & FPSR_MASK); 1148 vfp_set_fpscr(env, new_fpscr); 1149 } 1150 1151 static inline uint32_t vfp_get_fpcr(CPUARMState *env) 1152 { 1153 return vfp_get_fpscr(env) & FPCR_MASK; 1154 } 1155 1156 static inline void vfp_set_fpcr(CPUARMState *env, uint32_t val) 1157 { 1158 uint32_t new_fpscr = (vfp_get_fpscr(env) & ~FPCR_MASK) | (val & FPCR_MASK); 1159 vfp_set_fpscr(env, new_fpscr); 1160 } 1161 1162 enum arm_cpu_mode { 1163 ARM_CPU_MODE_USR = 0x10, 1164 ARM_CPU_MODE_FIQ = 0x11, 1165 ARM_CPU_MODE_IRQ = 0x12, 1166 ARM_CPU_MODE_SVC = 0x13, 1167 ARM_CPU_MODE_MON = 0x16, 1168 ARM_CPU_MODE_ABT = 0x17, 1169 ARM_CPU_MODE_HYP = 0x1a, 1170 ARM_CPU_MODE_UND = 0x1b, 1171 ARM_CPU_MODE_SYS = 0x1f 1172 }; 1173 1174 /* VFP system registers. */ 1175 #define ARM_VFP_FPSID 0 1176 #define ARM_VFP_FPSCR 1 1177 #define ARM_VFP_MVFR2 5 1178 #define ARM_VFP_MVFR1 6 1179 #define ARM_VFP_MVFR0 7 1180 #define ARM_VFP_FPEXC 8 1181 #define ARM_VFP_FPINST 9 1182 #define ARM_VFP_FPINST2 10 1183 1184 /* iwMMXt coprocessor control registers. */ 1185 #define ARM_IWMMXT_wCID 0 1186 #define ARM_IWMMXT_wCon 1 1187 #define ARM_IWMMXT_wCSSF 2 1188 #define ARM_IWMMXT_wCASF 3 1189 #define ARM_IWMMXT_wCGR0 8 1190 #define ARM_IWMMXT_wCGR1 9 1191 #define ARM_IWMMXT_wCGR2 10 1192 #define ARM_IWMMXT_wCGR3 11 1193 1194 /* V7M CCR bits */ 1195 FIELD(V7M_CCR, NONBASETHRDENA, 0, 1) 1196 FIELD(V7M_CCR, USERSETMPEND, 1, 1) 1197 FIELD(V7M_CCR, UNALIGN_TRP, 3, 1) 1198 FIELD(V7M_CCR, DIV_0_TRP, 4, 1) 1199 FIELD(V7M_CCR, BFHFNMIGN, 8, 1) 1200 FIELD(V7M_CCR, STKALIGN, 9, 1) 1201 FIELD(V7M_CCR, DC, 16, 1) 1202 FIELD(V7M_CCR, IC, 17, 1) 1203 1204 /* V7M AIRCR bits */ 1205 FIELD(V7M_AIRCR, VECTRESET, 0, 1) 1206 FIELD(V7M_AIRCR, VECTCLRACTIVE, 1, 1) 1207 FIELD(V7M_AIRCR, SYSRESETREQ, 2, 1) 1208 FIELD(V7M_AIRCR, SYSRESETREQS, 3, 1) 1209 FIELD(V7M_AIRCR, PRIGROUP, 8, 3) 1210 FIELD(V7M_AIRCR, BFHFNMINS, 13, 1) 1211 FIELD(V7M_AIRCR, PRIS, 14, 1) 1212 FIELD(V7M_AIRCR, ENDIANNESS, 15, 1) 1213 FIELD(V7M_AIRCR, VECTKEY, 16, 16) 1214 1215 /* V7M CFSR bits for MMFSR */ 1216 FIELD(V7M_CFSR, IACCVIOL, 0, 1) 1217 FIELD(V7M_CFSR, DACCVIOL, 1, 1) 1218 FIELD(V7M_CFSR, MUNSTKERR, 3, 1) 1219 FIELD(V7M_CFSR, MSTKERR, 4, 1) 1220 FIELD(V7M_CFSR, MLSPERR, 5, 1) 1221 FIELD(V7M_CFSR, MMARVALID, 7, 1) 1222 1223 /* V7M CFSR bits for BFSR */ 1224 FIELD(V7M_CFSR, IBUSERR, 8 + 0, 1) 1225 FIELD(V7M_CFSR, PRECISERR, 8 + 1, 1) 1226 FIELD(V7M_CFSR, IMPRECISERR, 8 + 2, 1) 1227 FIELD(V7M_CFSR, UNSTKERR, 8 + 3, 1) 1228 FIELD(V7M_CFSR, STKERR, 8 + 4, 1) 1229 FIELD(V7M_CFSR, LSPERR, 8 + 5, 1) 1230 FIELD(V7M_CFSR, BFARVALID, 8 + 7, 1) 1231 1232 /* V7M CFSR bits for UFSR */ 1233 FIELD(V7M_CFSR, UNDEFINSTR, 16 + 0, 1) 1234 FIELD(V7M_CFSR, INVSTATE, 16 + 1, 1) 1235 FIELD(V7M_CFSR, INVPC, 16 + 2, 1) 1236 FIELD(V7M_CFSR, NOCP, 16 + 3, 1) 1237 FIELD(V7M_CFSR, UNALIGNED, 16 + 8, 1) 1238 FIELD(V7M_CFSR, DIVBYZERO, 16 + 9, 1) 1239 1240 /* V7M CFSR bit masks covering all of the subregister bits */ 1241 FIELD(V7M_CFSR, MMFSR, 0, 8) 1242 FIELD(V7M_CFSR, BFSR, 8, 8) 1243 FIELD(V7M_CFSR, UFSR, 16, 16) 1244 1245 /* V7M HFSR bits */ 1246 FIELD(V7M_HFSR, VECTTBL, 1, 1) 1247 FIELD(V7M_HFSR, FORCED, 30, 1) 1248 FIELD(V7M_HFSR, DEBUGEVT, 31, 1) 1249 1250 /* V7M DFSR bits */ 1251 FIELD(V7M_DFSR, HALTED, 0, 1) 1252 FIELD(V7M_DFSR, BKPT, 1, 1) 1253 FIELD(V7M_DFSR, DWTTRAP, 2, 1) 1254 FIELD(V7M_DFSR, VCATCH, 3, 1) 1255 FIELD(V7M_DFSR, EXTERNAL, 4, 1) 1256 1257 /* v7M MPU_CTRL bits */ 1258 FIELD(V7M_MPU_CTRL, ENABLE, 0, 1) 1259 FIELD(V7M_MPU_CTRL, HFNMIENA, 1, 1) 1260 FIELD(V7M_MPU_CTRL, PRIVDEFENA, 2, 1) 1261 1262 /* If adding a feature bit which corresponds to a Linux ELF 1263 * HWCAP bit, remember to update the feature-bit-to-hwcap 1264 * mapping in linux-user/elfload.c:get_elf_hwcap(). 1265 */ 1266 enum arm_features { 1267 ARM_FEATURE_VFP, 1268 ARM_FEATURE_AUXCR, /* ARM1026 Auxiliary control register. */ 1269 ARM_FEATURE_XSCALE, /* Intel XScale extensions. */ 1270 ARM_FEATURE_IWMMXT, /* Intel iwMMXt extension. */ 1271 ARM_FEATURE_V6, 1272 ARM_FEATURE_V6K, 1273 ARM_FEATURE_V7, 1274 ARM_FEATURE_THUMB2, 1275 ARM_FEATURE_PMSA, /* no MMU; may have Memory Protection Unit */ 1276 ARM_FEATURE_VFP3, 1277 ARM_FEATURE_VFP_FP16, 1278 ARM_FEATURE_NEON, 1279 ARM_FEATURE_THUMB_DIV, /* divide supported in Thumb encoding */ 1280 ARM_FEATURE_M, /* Microcontroller profile. */ 1281 ARM_FEATURE_OMAPCP, /* OMAP specific CP15 ops handling. */ 1282 ARM_FEATURE_THUMB2EE, 1283 ARM_FEATURE_V7MP, /* v7 Multiprocessing Extensions */ 1284 ARM_FEATURE_V4T, 1285 ARM_FEATURE_V5, 1286 ARM_FEATURE_STRONGARM, 1287 ARM_FEATURE_VAPA, /* cp15 VA to PA lookups */ 1288 ARM_FEATURE_ARM_DIV, /* divide supported in ARM encoding */ 1289 ARM_FEATURE_VFP4, /* VFPv4 (implies that NEON is v2) */ 1290 ARM_FEATURE_GENERIC_TIMER, 1291 ARM_FEATURE_MVFR, /* Media and VFP Feature Registers 0 and 1 */ 1292 ARM_FEATURE_DUMMY_C15_REGS, /* RAZ/WI all of cp15 crn=15 */ 1293 ARM_FEATURE_CACHE_TEST_CLEAN, /* 926/1026 style test-and-clean ops */ 1294 ARM_FEATURE_CACHE_DIRTY_REG, /* 1136/1176 cache dirty status register */ 1295 ARM_FEATURE_CACHE_BLOCK_OPS, /* v6 optional cache block operations */ 1296 ARM_FEATURE_MPIDR, /* has cp15 MPIDR */ 1297 ARM_FEATURE_PXN, /* has Privileged Execute Never bit */ 1298 ARM_FEATURE_LPAE, /* has Large Physical Address Extension */ 1299 ARM_FEATURE_V8, 1300 ARM_FEATURE_AARCH64, /* supports 64 bit mode */ 1301 ARM_FEATURE_V8_AES, /* implements AES part of v8 Crypto Extensions */ 1302 ARM_FEATURE_CBAR, /* has cp15 CBAR */ 1303 ARM_FEATURE_CRC, /* ARMv8 CRC instructions */ 1304 ARM_FEATURE_CBAR_RO, /* has cp15 CBAR and it is read-only */ 1305 ARM_FEATURE_EL2, /* has EL2 Virtualization support */ 1306 ARM_FEATURE_EL3, /* has EL3 Secure monitor support */ 1307 ARM_FEATURE_V8_SHA1, /* implements SHA1 part of v8 Crypto Extensions */ 1308 ARM_FEATURE_V8_SHA256, /* implements SHA256 part of v8 Crypto Extensions */ 1309 ARM_FEATURE_V8_PMULL, /* implements PMULL part of v8 Crypto Extensions */ 1310 ARM_FEATURE_THUMB_DSP, /* DSP insns supported in the Thumb encodings */ 1311 ARM_FEATURE_PMU, /* has PMU support */ 1312 ARM_FEATURE_VBAR, /* has cp15 VBAR */ 1313 ARM_FEATURE_M_SECURITY, /* M profile Security Extension */ 1314 ARM_FEATURE_JAZELLE, /* has (trivial) Jazelle implementation */ 1315 }; 1316 1317 static inline int arm_feature(CPUARMState *env, int feature) 1318 { 1319 return (env->features & (1ULL << feature)) != 0; 1320 } 1321 1322 #if !defined(CONFIG_USER_ONLY) 1323 /* Return true if exception levels below EL3 are in secure state, 1324 * or would be following an exception return to that level. 1325 * Unlike arm_is_secure() (which is always a question about the 1326 * _current_ state of the CPU) this doesn't care about the current 1327 * EL or mode. 1328 */ 1329 static inline bool arm_is_secure_below_el3(CPUARMState *env) 1330 { 1331 if (arm_feature(env, ARM_FEATURE_EL3)) { 1332 return !(env->cp15.scr_el3 & SCR_NS); 1333 } else { 1334 /* If EL3 is not supported then the secure state is implementation 1335 * defined, in which case QEMU defaults to non-secure. 1336 */ 1337 return false; 1338 } 1339 } 1340 1341 /* Return true if the CPU is AArch64 EL3 or AArch32 Mon */ 1342 static inline bool arm_is_el3_or_mon(CPUARMState *env) 1343 { 1344 if (arm_feature(env, ARM_FEATURE_EL3)) { 1345 if (is_a64(env) && extract32(env->pstate, 2, 2) == 3) { 1346 /* CPU currently in AArch64 state and EL3 */ 1347 return true; 1348 } else if (!is_a64(env) && 1349 (env->uncached_cpsr & CPSR_M) == ARM_CPU_MODE_MON) { 1350 /* CPU currently in AArch32 state and monitor mode */ 1351 return true; 1352 } 1353 } 1354 return false; 1355 } 1356 1357 /* Return true if the processor is in secure state */ 1358 static inline bool arm_is_secure(CPUARMState *env) 1359 { 1360 if (arm_is_el3_or_mon(env)) { 1361 return true; 1362 } 1363 return arm_is_secure_below_el3(env); 1364 } 1365 1366 #else 1367 static inline bool arm_is_secure_below_el3(CPUARMState *env) 1368 { 1369 return false; 1370 } 1371 1372 static inline bool arm_is_secure(CPUARMState *env) 1373 { 1374 return false; 1375 } 1376 #endif 1377 1378 /* Return true if the specified exception level is running in AArch64 state. */ 1379 static inline bool arm_el_is_aa64(CPUARMState *env, int el) 1380 { 1381 /* This isn't valid for EL0 (if we're in EL0, is_a64() is what you want, 1382 * and if we're not in EL0 then the state of EL0 isn't well defined.) 1383 */ 1384 assert(el >= 1 && el <= 3); 1385 bool aa64 = arm_feature(env, ARM_FEATURE_AARCH64); 1386 1387 /* The highest exception level is always at the maximum supported 1388 * register width, and then lower levels have a register width controlled 1389 * by bits in the SCR or HCR registers. 1390 */ 1391 if (el == 3) { 1392 return aa64; 1393 } 1394 1395 if (arm_feature(env, ARM_FEATURE_EL3)) { 1396 aa64 = aa64 && (env->cp15.scr_el3 & SCR_RW); 1397 } 1398 1399 if (el == 2) { 1400 return aa64; 1401 } 1402 1403 if (arm_feature(env, ARM_FEATURE_EL2) && !arm_is_secure_below_el3(env)) { 1404 aa64 = aa64 && (env->cp15.hcr_el2 & HCR_RW); 1405 } 1406 1407 return aa64; 1408 } 1409 1410 /* Function for determing whether guest cp register reads and writes should 1411 * access the secure or non-secure bank of a cp register. When EL3 is 1412 * operating in AArch32 state, the NS-bit determines whether the secure 1413 * instance of a cp register should be used. When EL3 is AArch64 (or if 1414 * it doesn't exist at all) then there is no register banking, and all 1415 * accesses are to the non-secure version. 1416 */ 1417 static inline bool access_secure_reg(CPUARMState *env) 1418 { 1419 bool ret = (arm_feature(env, ARM_FEATURE_EL3) && 1420 !arm_el_is_aa64(env, 3) && 1421 !(env->cp15.scr_el3 & SCR_NS)); 1422 1423 return ret; 1424 } 1425 1426 /* Macros for accessing a specified CP register bank */ 1427 #define A32_BANKED_REG_GET(_env, _regname, _secure) \ 1428 ((_secure) ? (_env)->cp15._regname##_s : (_env)->cp15._regname##_ns) 1429 1430 #define A32_BANKED_REG_SET(_env, _regname, _secure, _val) \ 1431 do { \ 1432 if (_secure) { \ 1433 (_env)->cp15._regname##_s = (_val); \ 1434 } else { \ 1435 (_env)->cp15._regname##_ns = (_val); \ 1436 } \ 1437 } while (0) 1438 1439 /* Macros for automatically accessing a specific CP register bank depending on 1440 * the current secure state of the system. These macros are not intended for 1441 * supporting instruction translation reads/writes as these are dependent 1442 * solely on the SCR.NS bit and not the mode. 1443 */ 1444 #define A32_BANKED_CURRENT_REG_GET(_env, _regname) \ 1445 A32_BANKED_REG_GET((_env), _regname, \ 1446 (arm_is_secure(_env) && !arm_el_is_aa64((_env), 3))) 1447 1448 #define A32_BANKED_CURRENT_REG_SET(_env, _regname, _val) \ 1449 A32_BANKED_REG_SET((_env), _regname, \ 1450 (arm_is_secure(_env) && !arm_el_is_aa64((_env), 3)), \ 1451 (_val)) 1452 1453 void arm_cpu_list(FILE *f, fprintf_function cpu_fprintf); 1454 uint32_t arm_phys_excp_target_el(CPUState *cs, uint32_t excp_idx, 1455 uint32_t cur_el, bool secure); 1456 1457 /* Interface between CPU and Interrupt controller. */ 1458 #ifndef CONFIG_USER_ONLY 1459 bool armv7m_nvic_can_take_pending_exception(void *opaque); 1460 #else 1461 static inline bool armv7m_nvic_can_take_pending_exception(void *opaque) 1462 { 1463 return true; 1464 } 1465 #endif 1466 /** 1467 * armv7m_nvic_set_pending: mark the specified exception as pending 1468 * @opaque: the NVIC 1469 * @irq: the exception number to mark pending 1470 * @secure: false for non-banked exceptions or for the nonsecure 1471 * version of a banked exception, true for the secure version of a banked 1472 * exception. 1473 * 1474 * Marks the specified exception as pending. Note that we will assert() 1475 * if @secure is true and @irq does not specify one of the fixed set 1476 * of architecturally banked exceptions. 1477 */ 1478 void armv7m_nvic_set_pending(void *opaque, int irq, bool secure); 1479 /** 1480 * armv7m_nvic_acknowledge_irq: make highest priority pending exception active 1481 * @opaque: the NVIC 1482 * 1483 * Move the current highest priority pending exception from the pending 1484 * state to the active state, and update v7m.exception to indicate that 1485 * it is the exception currently being handled. 1486 * 1487 * Returns: true if exception should be taken to Secure state, false for NS 1488 */ 1489 bool armv7m_nvic_acknowledge_irq(void *opaque); 1490 /** 1491 * armv7m_nvic_complete_irq: complete specified interrupt or exception 1492 * @opaque: the NVIC 1493 * @irq: the exception number to complete 1494 * @secure: true if this exception was secure 1495 * 1496 * Returns: -1 if the irq was not active 1497 * 1 if completing this irq brought us back to base (no active irqs) 1498 * 0 if there is still an irq active after this one was completed 1499 * (Ignoring -1, this is the same as the RETTOBASE value before completion.) 1500 */ 1501 int armv7m_nvic_complete_irq(void *opaque, int irq, bool secure); 1502 /** 1503 * armv7m_nvic_raw_execution_priority: return the raw execution priority 1504 * @opaque: the NVIC 1505 * 1506 * Returns: the raw execution priority as defined by the v8M architecture. 1507 * This is the execution priority minus the effects of AIRCR.PRIS, 1508 * and minus any PRIMASK/FAULTMASK/BASEPRI priority boosting. 1509 * (v8M ARM ARM I_PKLD.) 1510 */ 1511 int armv7m_nvic_raw_execution_priority(void *opaque); 1512 /** 1513 * armv7m_nvic_neg_prio_requested: return true if the requested execution 1514 * priority is negative for the specified security state. 1515 * @opaque: the NVIC 1516 * @secure: the security state to test 1517 * This corresponds to the pseudocode IsReqExecPriNeg(). 1518 */ 1519 #ifndef CONFIG_USER_ONLY 1520 bool armv7m_nvic_neg_prio_requested(void *opaque, bool secure); 1521 #else 1522 static inline bool armv7m_nvic_neg_prio_requested(void *opaque, bool secure) 1523 { 1524 return false; 1525 } 1526 #endif 1527 1528 /* Interface for defining coprocessor registers. 1529 * Registers are defined in tables of arm_cp_reginfo structs 1530 * which are passed to define_arm_cp_regs(). 1531 */ 1532 1533 /* When looking up a coprocessor register we look for it 1534 * via an integer which encodes all of: 1535 * coprocessor number 1536 * Crn, Crm, opc1, opc2 fields 1537 * 32 or 64 bit register (ie is it accessed via MRC/MCR 1538 * or via MRRC/MCRR?) 1539 * non-secure/secure bank (AArch32 only) 1540 * We allow 4 bits for opc1 because MRRC/MCRR have a 4 bit field. 1541 * (In this case crn and opc2 should be zero.) 1542 * For AArch64, there is no 32/64 bit size distinction; 1543 * instead all registers have a 2 bit op0, 3 bit op1 and op2, 1544 * and 4 bit CRn and CRm. The encoding patterns are chosen 1545 * to be easy to convert to and from the KVM encodings, and also 1546 * so that the hashtable can contain both AArch32 and AArch64 1547 * registers (to allow for interprocessing where we might run 1548 * 32 bit code on a 64 bit core). 1549 */ 1550 /* This bit is private to our hashtable cpreg; in KVM register 1551 * IDs the AArch64/32 distinction is the KVM_REG_ARM/ARM64 1552 * in the upper bits of the 64 bit ID. 1553 */ 1554 #define CP_REG_AA64_SHIFT 28 1555 #define CP_REG_AA64_MASK (1 << CP_REG_AA64_SHIFT) 1556 1557 /* To enable banking of coprocessor registers depending on ns-bit we 1558 * add a bit to distinguish between secure and non-secure cpregs in the 1559 * hashtable. 1560 */ 1561 #define CP_REG_NS_SHIFT 29 1562 #define CP_REG_NS_MASK (1 << CP_REG_NS_SHIFT) 1563 1564 #define ENCODE_CP_REG(cp, is64, ns, crn, crm, opc1, opc2) \ 1565 ((ns) << CP_REG_NS_SHIFT | ((cp) << 16) | ((is64) << 15) | \ 1566 ((crn) << 11) | ((crm) << 7) | ((opc1) << 3) | (opc2)) 1567 1568 #define ENCODE_AA64_CP_REG(cp, crn, crm, op0, op1, op2) \ 1569 (CP_REG_AA64_MASK | \ 1570 ((cp) << CP_REG_ARM_COPROC_SHIFT) | \ 1571 ((op0) << CP_REG_ARM64_SYSREG_OP0_SHIFT) | \ 1572 ((op1) << CP_REG_ARM64_SYSREG_OP1_SHIFT) | \ 1573 ((crn) << CP_REG_ARM64_SYSREG_CRN_SHIFT) | \ 1574 ((crm) << CP_REG_ARM64_SYSREG_CRM_SHIFT) | \ 1575 ((op2) << CP_REG_ARM64_SYSREG_OP2_SHIFT)) 1576 1577 /* Convert a full 64 bit KVM register ID to the truncated 32 bit 1578 * version used as a key for the coprocessor register hashtable 1579 */ 1580 static inline uint32_t kvm_to_cpreg_id(uint64_t kvmid) 1581 { 1582 uint32_t cpregid = kvmid; 1583 if ((kvmid & CP_REG_ARCH_MASK) == CP_REG_ARM64) { 1584 cpregid |= CP_REG_AA64_MASK; 1585 } else { 1586 if ((kvmid & CP_REG_SIZE_MASK) == CP_REG_SIZE_U64) { 1587 cpregid |= (1 << 15); 1588 } 1589 1590 /* KVM is always non-secure so add the NS flag on AArch32 register 1591 * entries. 1592 */ 1593 cpregid |= 1 << CP_REG_NS_SHIFT; 1594 } 1595 return cpregid; 1596 } 1597 1598 /* Convert a truncated 32 bit hashtable key into the full 1599 * 64 bit KVM register ID. 1600 */ 1601 static inline uint64_t cpreg_to_kvm_id(uint32_t cpregid) 1602 { 1603 uint64_t kvmid; 1604 1605 if (cpregid & CP_REG_AA64_MASK) { 1606 kvmid = cpregid & ~CP_REG_AA64_MASK; 1607 kvmid |= CP_REG_SIZE_U64 | CP_REG_ARM64; 1608 } else { 1609 kvmid = cpregid & ~(1 << 15); 1610 if (cpregid & (1 << 15)) { 1611 kvmid |= CP_REG_SIZE_U64 | CP_REG_ARM; 1612 } else { 1613 kvmid |= CP_REG_SIZE_U32 | CP_REG_ARM; 1614 } 1615 } 1616 return kvmid; 1617 } 1618 1619 /* ARMCPRegInfo type field bits. If the SPECIAL bit is set this is a 1620 * special-behaviour cp reg and bits [15..8] indicate what behaviour 1621 * it has. Otherwise it is a simple cp reg, where CONST indicates that 1622 * TCG can assume the value to be constant (ie load at translate time) 1623 * and 64BIT indicates a 64 bit wide coprocessor register. SUPPRESS_TB_END 1624 * indicates that the TB should not be ended after a write to this register 1625 * (the default is that the TB ends after cp writes). OVERRIDE permits 1626 * a register definition to override a previous definition for the 1627 * same (cp, is64, crn, crm, opc1, opc2) tuple: either the new or the 1628 * old must have the OVERRIDE bit set. 1629 * ALIAS indicates that this register is an alias view of some underlying 1630 * state which is also visible via another register, and that the other 1631 * register is handling migration and reset; registers marked ALIAS will not be 1632 * migrated but may have their state set by syncing of register state from KVM. 1633 * NO_RAW indicates that this register has no underlying state and does not 1634 * support raw access for state saving/loading; it will not be used for either 1635 * migration or KVM state synchronization. (Typically this is for "registers" 1636 * which are actually used as instructions for cache maintenance and so on.) 1637 * IO indicates that this register does I/O and therefore its accesses 1638 * need to be surrounded by gen_io_start()/gen_io_end(). In particular, 1639 * registers which implement clocks or timers require this. 1640 */ 1641 #define ARM_CP_SPECIAL 1 1642 #define ARM_CP_CONST 2 1643 #define ARM_CP_64BIT 4 1644 #define ARM_CP_SUPPRESS_TB_END 8 1645 #define ARM_CP_OVERRIDE 16 1646 #define ARM_CP_ALIAS 32 1647 #define ARM_CP_IO 64 1648 #define ARM_CP_NO_RAW 128 1649 #define ARM_CP_NOP (ARM_CP_SPECIAL | (1 << 8)) 1650 #define ARM_CP_WFI (ARM_CP_SPECIAL | (2 << 8)) 1651 #define ARM_CP_NZCV (ARM_CP_SPECIAL | (3 << 8)) 1652 #define ARM_CP_CURRENTEL (ARM_CP_SPECIAL | (4 << 8)) 1653 #define ARM_CP_DC_ZVA (ARM_CP_SPECIAL | (5 << 8)) 1654 #define ARM_LAST_SPECIAL ARM_CP_DC_ZVA 1655 /* Used only as a terminator for ARMCPRegInfo lists */ 1656 #define ARM_CP_SENTINEL 0xffff 1657 /* Mask of only the flag bits in a type field */ 1658 #define ARM_CP_FLAG_MASK 0xff 1659 1660 /* Valid values for ARMCPRegInfo state field, indicating which of 1661 * the AArch32 and AArch64 execution states this register is visible in. 1662 * If the reginfo doesn't explicitly specify then it is AArch32 only. 1663 * If the reginfo is declared to be visible in both states then a second 1664 * reginfo is synthesised for the AArch32 view of the AArch64 register, 1665 * such that the AArch32 view is the lower 32 bits of the AArch64 one. 1666 * Note that we rely on the values of these enums as we iterate through 1667 * the various states in some places. 1668 */ 1669 enum { 1670 ARM_CP_STATE_AA32 = 0, 1671 ARM_CP_STATE_AA64 = 1, 1672 ARM_CP_STATE_BOTH = 2, 1673 }; 1674 1675 /* ARM CP register secure state flags. These flags identify security state 1676 * attributes for a given CP register entry. 1677 * The existence of both or neither secure and non-secure flags indicates that 1678 * the register has both a secure and non-secure hash entry. A single one of 1679 * these flags causes the register to only be hashed for the specified 1680 * security state. 1681 * Although definitions may have any combination of the S/NS bits, each 1682 * registered entry will only have one to identify whether the entry is secure 1683 * or non-secure. 1684 */ 1685 enum { 1686 ARM_CP_SECSTATE_S = (1 << 0), /* bit[0]: Secure state register */ 1687 ARM_CP_SECSTATE_NS = (1 << 1), /* bit[1]: Non-secure state register */ 1688 }; 1689 1690 /* Return true if cptype is a valid type field. This is used to try to 1691 * catch errors where the sentinel has been accidentally left off the end 1692 * of a list of registers. 1693 */ 1694 static inline bool cptype_valid(int cptype) 1695 { 1696 return ((cptype & ~ARM_CP_FLAG_MASK) == 0) 1697 || ((cptype & ARM_CP_SPECIAL) && 1698 ((cptype & ~ARM_CP_FLAG_MASK) <= ARM_LAST_SPECIAL)); 1699 } 1700 1701 /* Access rights: 1702 * We define bits for Read and Write access for what rev C of the v7-AR ARM ARM 1703 * defines as PL0 (user), PL1 (fiq/irq/svc/abt/und/sys, ie privileged), and 1704 * PL2 (hyp). The other level which has Read and Write bits is Secure PL1 1705 * (ie any of the privileged modes in Secure state, or Monitor mode). 1706 * If a register is accessible in one privilege level it's always accessible 1707 * in higher privilege levels too. Since "Secure PL1" also follows this rule 1708 * (ie anything visible in PL2 is visible in S-PL1, some things are only 1709 * visible in S-PL1) but "Secure PL1" is a bit of a mouthful, we bend the 1710 * terminology a little and call this PL3. 1711 * In AArch64 things are somewhat simpler as the PLx bits line up exactly 1712 * with the ELx exception levels. 1713 * 1714 * If access permissions for a register are more complex than can be 1715 * described with these bits, then use a laxer set of restrictions, and 1716 * do the more restrictive/complex check inside a helper function. 1717 */ 1718 #define PL3_R 0x80 1719 #define PL3_W 0x40 1720 #define PL2_R (0x20 | PL3_R) 1721 #define PL2_W (0x10 | PL3_W) 1722 #define PL1_R (0x08 | PL2_R) 1723 #define PL1_W (0x04 | PL2_W) 1724 #define PL0_R (0x02 | PL1_R) 1725 #define PL0_W (0x01 | PL1_W) 1726 1727 #define PL3_RW (PL3_R | PL3_W) 1728 #define PL2_RW (PL2_R | PL2_W) 1729 #define PL1_RW (PL1_R | PL1_W) 1730 #define PL0_RW (PL0_R | PL0_W) 1731 1732 /* Return the highest implemented Exception Level */ 1733 static inline int arm_highest_el(CPUARMState *env) 1734 { 1735 if (arm_feature(env, ARM_FEATURE_EL3)) { 1736 return 3; 1737 } 1738 if (arm_feature(env, ARM_FEATURE_EL2)) { 1739 return 2; 1740 } 1741 return 1; 1742 } 1743 1744 /* Return true if a v7M CPU is in Handler mode */ 1745 static inline bool arm_v7m_is_handler_mode(CPUARMState *env) 1746 { 1747 return env->v7m.exception != 0; 1748 } 1749 1750 /* Return the current Exception Level (as per ARMv8; note that this differs 1751 * from the ARMv7 Privilege Level). 1752 */ 1753 static inline int arm_current_el(CPUARMState *env) 1754 { 1755 if (arm_feature(env, ARM_FEATURE_M)) { 1756 return arm_v7m_is_handler_mode(env) || 1757 !(env->v7m.control[env->v7m.secure] & 1); 1758 } 1759 1760 if (is_a64(env)) { 1761 return extract32(env->pstate, 2, 2); 1762 } 1763 1764 switch (env->uncached_cpsr & 0x1f) { 1765 case ARM_CPU_MODE_USR: 1766 return 0; 1767 case ARM_CPU_MODE_HYP: 1768 return 2; 1769 case ARM_CPU_MODE_MON: 1770 return 3; 1771 default: 1772 if (arm_is_secure(env) && !arm_el_is_aa64(env, 3)) { 1773 /* If EL3 is 32-bit then all secure privileged modes run in 1774 * EL3 1775 */ 1776 return 3; 1777 } 1778 1779 return 1; 1780 } 1781 } 1782 1783 typedef struct ARMCPRegInfo ARMCPRegInfo; 1784 1785 typedef enum CPAccessResult { 1786 /* Access is permitted */ 1787 CP_ACCESS_OK = 0, 1788 /* Access fails due to a configurable trap or enable which would 1789 * result in a categorized exception syndrome giving information about 1790 * the failing instruction (ie syndrome category 0x3, 0x4, 0x5, 0x6, 1791 * 0xc or 0x18). The exception is taken to the usual target EL (EL1 or 1792 * PL1 if in EL0, otherwise to the current EL). 1793 */ 1794 CP_ACCESS_TRAP = 1, 1795 /* Access fails and results in an exception syndrome 0x0 ("uncategorized"). 1796 * Note that this is not a catch-all case -- the set of cases which may 1797 * result in this failure is specifically defined by the architecture. 1798 */ 1799 CP_ACCESS_TRAP_UNCATEGORIZED = 2, 1800 /* As CP_ACCESS_TRAP, but for traps directly to EL2 or EL3 */ 1801 CP_ACCESS_TRAP_EL2 = 3, 1802 CP_ACCESS_TRAP_EL3 = 4, 1803 /* As CP_ACCESS_UNCATEGORIZED, but for traps directly to EL2 or EL3 */ 1804 CP_ACCESS_TRAP_UNCATEGORIZED_EL2 = 5, 1805 CP_ACCESS_TRAP_UNCATEGORIZED_EL3 = 6, 1806 /* Access fails and results in an exception syndrome for an FP access, 1807 * trapped directly to EL2 or EL3 1808 */ 1809 CP_ACCESS_TRAP_FP_EL2 = 7, 1810 CP_ACCESS_TRAP_FP_EL3 = 8, 1811 } CPAccessResult; 1812 1813 /* Access functions for coprocessor registers. These cannot fail and 1814 * may not raise exceptions. 1815 */ 1816 typedef uint64_t CPReadFn(CPUARMState *env, const ARMCPRegInfo *opaque); 1817 typedef void CPWriteFn(CPUARMState *env, const ARMCPRegInfo *opaque, 1818 uint64_t value); 1819 /* Access permission check functions for coprocessor registers. */ 1820 typedef CPAccessResult CPAccessFn(CPUARMState *env, 1821 const ARMCPRegInfo *opaque, 1822 bool isread); 1823 /* Hook function for register reset */ 1824 typedef void CPResetFn(CPUARMState *env, const ARMCPRegInfo *opaque); 1825 1826 #define CP_ANY 0xff 1827 1828 /* Definition of an ARM coprocessor register */ 1829 struct ARMCPRegInfo { 1830 /* Name of register (useful mainly for debugging, need not be unique) */ 1831 const char *name; 1832 /* Location of register: coprocessor number and (crn,crm,opc1,opc2) 1833 * tuple. Any of crm, opc1 and opc2 may be CP_ANY to indicate a 1834 * 'wildcard' field -- any value of that field in the MRC/MCR insn 1835 * will be decoded to this register. The register read and write 1836 * callbacks will be passed an ARMCPRegInfo with the crn/crm/opc1/opc2 1837 * used by the program, so it is possible to register a wildcard and 1838 * then behave differently on read/write if necessary. 1839 * For 64 bit registers, only crm and opc1 are relevant; crn and opc2 1840 * must both be zero. 1841 * For AArch64-visible registers, opc0 is also used. 1842 * Since there are no "coprocessors" in AArch64, cp is purely used as a 1843 * way to distinguish (for KVM's benefit) guest-visible system registers 1844 * from demuxed ones provided to preserve the "no side effects on 1845 * KVM register read/write from QEMU" semantics. cp==0x13 is guest 1846 * visible (to match KVM's encoding); cp==0 will be converted to 1847 * cp==0x13 when the ARMCPRegInfo is registered, for convenience. 1848 */ 1849 uint8_t cp; 1850 uint8_t crn; 1851 uint8_t crm; 1852 uint8_t opc0; 1853 uint8_t opc1; 1854 uint8_t opc2; 1855 /* Execution state in which this register is visible: ARM_CP_STATE_* */ 1856 int state; 1857 /* Register type: ARM_CP_* bits/values */ 1858 int type; 1859 /* Access rights: PL*_[RW] */ 1860 int access; 1861 /* Security state: ARM_CP_SECSTATE_* bits/values */ 1862 int secure; 1863 /* The opaque pointer passed to define_arm_cp_regs_with_opaque() when 1864 * this register was defined: can be used to hand data through to the 1865 * register read/write functions, since they are passed the ARMCPRegInfo*. 1866 */ 1867 void *opaque; 1868 /* Value of this register, if it is ARM_CP_CONST. Otherwise, if 1869 * fieldoffset is non-zero, the reset value of the register. 1870 */ 1871 uint64_t resetvalue; 1872 /* Offset of the field in CPUARMState for this register. 1873 * 1874 * This is not needed if either: 1875 * 1. type is ARM_CP_CONST or one of the ARM_CP_SPECIALs 1876 * 2. both readfn and writefn are specified 1877 */ 1878 ptrdiff_t fieldoffset; /* offsetof(CPUARMState, field) */ 1879 1880 /* Offsets of the secure and non-secure fields in CPUARMState for the 1881 * register if it is banked. These fields are only used during the static 1882 * registration of a register. During hashing the bank associated 1883 * with a given security state is copied to fieldoffset which is used from 1884 * there on out. 1885 * 1886 * It is expected that register definitions use either fieldoffset or 1887 * bank_fieldoffsets in the definition but not both. It is also expected 1888 * that both bank offsets are set when defining a banked register. This 1889 * use indicates that a register is banked. 1890 */ 1891 ptrdiff_t bank_fieldoffsets[2]; 1892 1893 /* Function for making any access checks for this register in addition to 1894 * those specified by the 'access' permissions bits. If NULL, no extra 1895 * checks required. The access check is performed at runtime, not at 1896 * translate time. 1897 */ 1898 CPAccessFn *accessfn; 1899 /* Function for handling reads of this register. If NULL, then reads 1900 * will be done by loading from the offset into CPUARMState specified 1901 * by fieldoffset. 1902 */ 1903 CPReadFn *readfn; 1904 /* Function for handling writes of this register. If NULL, then writes 1905 * will be done by writing to the offset into CPUARMState specified 1906 * by fieldoffset. 1907 */ 1908 CPWriteFn *writefn; 1909 /* Function for doing a "raw" read; used when we need to copy 1910 * coprocessor state to the kernel for KVM or out for 1911 * migration. This only needs to be provided if there is also a 1912 * readfn and it has side effects (for instance clear-on-read bits). 1913 */ 1914 CPReadFn *raw_readfn; 1915 /* Function for doing a "raw" write; used when we need to copy KVM 1916 * kernel coprocessor state into userspace, or for inbound 1917 * migration. This only needs to be provided if there is also a 1918 * writefn and it masks out "unwritable" bits or has write-one-to-clear 1919 * or similar behaviour. 1920 */ 1921 CPWriteFn *raw_writefn; 1922 /* Function for resetting the register. If NULL, then reset will be done 1923 * by writing resetvalue to the field specified in fieldoffset. If 1924 * fieldoffset is 0 then no reset will be done. 1925 */ 1926 CPResetFn *resetfn; 1927 }; 1928 1929 /* Macros which are lvalues for the field in CPUARMState for the 1930 * ARMCPRegInfo *ri. 1931 */ 1932 #define CPREG_FIELD32(env, ri) \ 1933 (*(uint32_t *)((char *)(env) + (ri)->fieldoffset)) 1934 #define CPREG_FIELD64(env, ri) \ 1935 (*(uint64_t *)((char *)(env) + (ri)->fieldoffset)) 1936 1937 #define REGINFO_SENTINEL { .type = ARM_CP_SENTINEL } 1938 1939 void define_arm_cp_regs_with_opaque(ARMCPU *cpu, 1940 const ARMCPRegInfo *regs, void *opaque); 1941 void define_one_arm_cp_reg_with_opaque(ARMCPU *cpu, 1942 const ARMCPRegInfo *regs, void *opaque); 1943 static inline void define_arm_cp_regs(ARMCPU *cpu, const ARMCPRegInfo *regs) 1944 { 1945 define_arm_cp_regs_with_opaque(cpu, regs, 0); 1946 } 1947 static inline void define_one_arm_cp_reg(ARMCPU *cpu, const ARMCPRegInfo *regs) 1948 { 1949 define_one_arm_cp_reg_with_opaque(cpu, regs, 0); 1950 } 1951 const ARMCPRegInfo *get_arm_cp_reginfo(GHashTable *cpregs, uint32_t encoded_cp); 1952 1953 /* CPWriteFn that can be used to implement writes-ignored behaviour */ 1954 void arm_cp_write_ignore(CPUARMState *env, const ARMCPRegInfo *ri, 1955 uint64_t value); 1956 /* CPReadFn that can be used for read-as-zero behaviour */ 1957 uint64_t arm_cp_read_zero(CPUARMState *env, const ARMCPRegInfo *ri); 1958 1959 /* CPResetFn that does nothing, for use if no reset is required even 1960 * if fieldoffset is non zero. 1961 */ 1962 void arm_cp_reset_ignore(CPUARMState *env, const ARMCPRegInfo *opaque); 1963 1964 /* Return true if this reginfo struct's field in the cpu state struct 1965 * is 64 bits wide. 1966 */ 1967 static inline bool cpreg_field_is_64bit(const ARMCPRegInfo *ri) 1968 { 1969 return (ri->state == ARM_CP_STATE_AA64) || (ri->type & ARM_CP_64BIT); 1970 } 1971 1972 static inline bool cp_access_ok(int current_el, 1973 const ARMCPRegInfo *ri, int isread) 1974 { 1975 return (ri->access >> ((current_el * 2) + isread)) & 1; 1976 } 1977 1978 /* Raw read of a coprocessor register (as needed for migration, etc) */ 1979 uint64_t read_raw_cp_reg(CPUARMState *env, const ARMCPRegInfo *ri); 1980 1981 /** 1982 * write_list_to_cpustate 1983 * @cpu: ARMCPU 1984 * 1985 * For each register listed in the ARMCPU cpreg_indexes list, write 1986 * its value from the cpreg_values list into the ARMCPUState structure. 1987 * This updates TCG's working data structures from KVM data or 1988 * from incoming migration state. 1989 * 1990 * Returns: true if all register values were updated correctly, 1991 * false if some register was unknown or could not be written. 1992 * Note that we do not stop early on failure -- we will attempt 1993 * writing all registers in the list. 1994 */ 1995 bool write_list_to_cpustate(ARMCPU *cpu); 1996 1997 /** 1998 * write_cpustate_to_list: 1999 * @cpu: ARMCPU 2000 * 2001 * For each register listed in the ARMCPU cpreg_indexes list, write 2002 * its value from the ARMCPUState structure into the cpreg_values list. 2003 * This is used to copy info from TCG's working data structures into 2004 * KVM or for outbound migration. 2005 * 2006 * Returns: true if all register values were read correctly, 2007 * false if some register was unknown or could not be read. 2008 * Note that we do not stop early on failure -- we will attempt 2009 * reading all registers in the list. 2010 */ 2011 bool write_cpustate_to_list(ARMCPU *cpu); 2012 2013 #define ARM_CPUID_TI915T 0x54029152 2014 #define ARM_CPUID_TI925T 0x54029252 2015 2016 #if defined(CONFIG_USER_ONLY) 2017 #define TARGET_PAGE_BITS 12 2018 #else 2019 /* ARMv7 and later CPUs have 4K pages minimum, but ARMv5 and v6 2020 * have to support 1K tiny pages. 2021 */ 2022 #define TARGET_PAGE_BITS_VARY 2023 #define TARGET_PAGE_BITS_MIN 10 2024 #endif 2025 2026 #if defined(TARGET_AARCH64) 2027 # define TARGET_PHYS_ADDR_SPACE_BITS 48 2028 # define TARGET_VIRT_ADDR_SPACE_BITS 64 2029 #else 2030 # define TARGET_PHYS_ADDR_SPACE_BITS 40 2031 # define TARGET_VIRT_ADDR_SPACE_BITS 32 2032 #endif 2033 2034 static inline bool arm_excp_unmasked(CPUState *cs, unsigned int excp_idx, 2035 unsigned int target_el) 2036 { 2037 CPUARMState *env = cs->env_ptr; 2038 unsigned int cur_el = arm_current_el(env); 2039 bool secure = arm_is_secure(env); 2040 bool pstate_unmasked; 2041 int8_t unmasked = 0; 2042 2043 /* Don't take exceptions if they target a lower EL. 2044 * This check should catch any exceptions that would not be taken but left 2045 * pending. 2046 */ 2047 if (cur_el > target_el) { 2048 return false; 2049 } 2050 2051 switch (excp_idx) { 2052 case EXCP_FIQ: 2053 pstate_unmasked = !(env->daif & PSTATE_F); 2054 break; 2055 2056 case EXCP_IRQ: 2057 pstate_unmasked = !(env->daif & PSTATE_I); 2058 break; 2059 2060 case EXCP_VFIQ: 2061 if (secure || !(env->cp15.hcr_el2 & HCR_FMO)) { 2062 /* VFIQs are only taken when hypervized and non-secure. */ 2063 return false; 2064 } 2065 return !(env->daif & PSTATE_F); 2066 case EXCP_VIRQ: 2067 if (secure || !(env->cp15.hcr_el2 & HCR_IMO)) { 2068 /* VIRQs are only taken when hypervized and non-secure. */ 2069 return false; 2070 } 2071 return !(env->daif & PSTATE_I); 2072 default: 2073 g_assert_not_reached(); 2074 } 2075 2076 /* Use the target EL, current execution state and SCR/HCR settings to 2077 * determine whether the corresponding CPSR bit is used to mask the 2078 * interrupt. 2079 */ 2080 if ((target_el > cur_el) && (target_el != 1)) { 2081 /* Exceptions targeting a higher EL may not be maskable */ 2082 if (arm_feature(env, ARM_FEATURE_AARCH64)) { 2083 /* 64-bit masking rules are simple: exceptions to EL3 2084 * can't be masked, and exceptions to EL2 can only be 2085 * masked from Secure state. The HCR and SCR settings 2086 * don't affect the masking logic, only the interrupt routing. 2087 */ 2088 if (target_el == 3 || !secure) { 2089 unmasked = 1; 2090 } 2091 } else { 2092 /* The old 32-bit-only environment has a more complicated 2093 * masking setup. HCR and SCR bits not only affect interrupt 2094 * routing but also change the behaviour of masking. 2095 */ 2096 bool hcr, scr; 2097 2098 switch (excp_idx) { 2099 case EXCP_FIQ: 2100 /* If FIQs are routed to EL3 or EL2 then there are cases where 2101 * we override the CPSR.F in determining if the exception is 2102 * masked or not. If neither of these are set then we fall back 2103 * to the CPSR.F setting otherwise we further assess the state 2104 * below. 2105 */ 2106 hcr = (env->cp15.hcr_el2 & HCR_FMO); 2107 scr = (env->cp15.scr_el3 & SCR_FIQ); 2108 2109 /* When EL3 is 32-bit, the SCR.FW bit controls whether the 2110 * CPSR.F bit masks FIQ interrupts when taken in non-secure 2111 * state. If SCR.FW is set then FIQs can be masked by CPSR.F 2112 * when non-secure but only when FIQs are only routed to EL3. 2113 */ 2114 scr = scr && !((env->cp15.scr_el3 & SCR_FW) && !hcr); 2115 break; 2116 case EXCP_IRQ: 2117 /* When EL3 execution state is 32-bit, if HCR.IMO is set then 2118 * we may override the CPSR.I masking when in non-secure state. 2119 * The SCR.IRQ setting has already been taken into consideration 2120 * when setting the target EL, so it does not have a further 2121 * affect here. 2122 */ 2123 hcr = (env->cp15.hcr_el2 & HCR_IMO); 2124 scr = false; 2125 break; 2126 default: 2127 g_assert_not_reached(); 2128 } 2129 2130 if ((scr || hcr) && !secure) { 2131 unmasked = 1; 2132 } 2133 } 2134 } 2135 2136 /* The PSTATE bits only mask the interrupt if we have not overriden the 2137 * ability above. 2138 */ 2139 return unmasked || pstate_unmasked; 2140 } 2141 2142 #define cpu_init(cpu_model) cpu_generic_init(TYPE_ARM_CPU, cpu_model) 2143 2144 #define ARM_CPU_TYPE_SUFFIX "-" TYPE_ARM_CPU 2145 #define ARM_CPU_TYPE_NAME(name) (name ARM_CPU_TYPE_SUFFIX) 2146 2147 #define cpu_signal_handler cpu_arm_signal_handler 2148 #define cpu_list arm_cpu_list 2149 2150 /* ARM has the following "translation regimes" (as the ARM ARM calls them): 2151 * 2152 * If EL3 is 64-bit: 2153 * + NonSecure EL1 & 0 stage 1 2154 * + NonSecure EL1 & 0 stage 2 2155 * + NonSecure EL2 2156 * + Secure EL1 & EL0 2157 * + Secure EL3 2158 * If EL3 is 32-bit: 2159 * + NonSecure PL1 & 0 stage 1 2160 * + NonSecure PL1 & 0 stage 2 2161 * + NonSecure PL2 2162 * + Secure PL0 & PL1 2163 * (reminder: for 32 bit EL3, Secure PL1 is *EL3*, not EL1.) 2164 * 2165 * For QEMU, an mmu_idx is not quite the same as a translation regime because: 2166 * 1. we need to split the "EL1 & 0" regimes into two mmu_idxes, because they 2167 * may differ in access permissions even if the VA->PA map is the same 2168 * 2. we want to cache in our TLB the full VA->IPA->PA lookup for a stage 1+2 2169 * translation, which means that we have one mmu_idx that deals with two 2170 * concatenated translation regimes [this sort of combined s1+2 TLB is 2171 * architecturally permitted] 2172 * 3. we don't need to allocate an mmu_idx to translations that we won't be 2173 * handling via the TLB. The only way to do a stage 1 translation without 2174 * the immediate stage 2 translation is via the ATS or AT system insns, 2175 * which can be slow-pathed and always do a page table walk. 2176 * 4. we can also safely fold together the "32 bit EL3" and "64 bit EL3" 2177 * translation regimes, because they map reasonably well to each other 2178 * and they can't both be active at the same time. 2179 * This gives us the following list of mmu_idx values: 2180 * 2181 * NS EL0 (aka NS PL0) stage 1+2 2182 * NS EL1 (aka NS PL1) stage 1+2 2183 * NS EL2 (aka NS PL2) 2184 * S EL3 (aka S PL1) 2185 * S EL0 (aka S PL0) 2186 * S EL1 (not used if EL3 is 32 bit) 2187 * NS EL0+1 stage 2 2188 * 2189 * (The last of these is an mmu_idx because we want to be able to use the TLB 2190 * for the accesses done as part of a stage 1 page table walk, rather than 2191 * having to walk the stage 2 page table over and over.) 2192 * 2193 * R profile CPUs have an MPU, but can use the same set of MMU indexes 2194 * as A profile. They only need to distinguish NS EL0 and NS EL1 (and 2195 * NS EL2 if we ever model a Cortex-R52). 2196 * 2197 * M profile CPUs are rather different as they do not have a true MMU. 2198 * They have the following different MMU indexes: 2199 * User 2200 * Privileged 2201 * Execution priority negative (this is like privileged, but the 2202 * MPU HFNMIENA bit means that it may have different access permission 2203 * check results to normal privileged code, so can't share a TLB). 2204 * If the CPU supports the v8M Security Extension then there are also: 2205 * Secure User 2206 * Secure Privileged 2207 * Secure, execution priority negative 2208 * 2209 * The ARMMMUIdx and the mmu index value used by the core QEMU TLB code 2210 * are not quite the same -- different CPU types (most notably M profile 2211 * vs A/R profile) would like to use MMU indexes with different semantics, 2212 * but since we don't ever need to use all of those in a single CPU we 2213 * can avoid setting NB_MMU_MODES to more than 8. The lower bits of 2214 * ARMMMUIdx are the core TLB mmu index, and the higher bits are always 2215 * the same for any particular CPU. 2216 * Variables of type ARMMUIdx are always full values, and the core 2217 * index values are in variables of type 'int'. 2218 * 2219 * Our enumeration includes at the end some entries which are not "true" 2220 * mmu_idx values in that they don't have corresponding TLBs and are only 2221 * valid for doing slow path page table walks. 2222 * 2223 * The constant names here are patterned after the general style of the names 2224 * of the AT/ATS operations. 2225 * The values used are carefully arranged to make mmu_idx => EL lookup easy. 2226 */ 2227 #define ARM_MMU_IDX_A 0x10 /* A profile */ 2228 #define ARM_MMU_IDX_NOTLB 0x20 /* does not have a TLB */ 2229 #define ARM_MMU_IDX_M 0x40 /* M profile */ 2230 2231 #define ARM_MMU_IDX_TYPE_MASK (~0x7) 2232 #define ARM_MMU_IDX_COREIDX_MASK 0x7 2233 2234 typedef enum ARMMMUIdx { 2235 ARMMMUIdx_S12NSE0 = 0 | ARM_MMU_IDX_A, 2236 ARMMMUIdx_S12NSE1 = 1 | ARM_MMU_IDX_A, 2237 ARMMMUIdx_S1E2 = 2 | ARM_MMU_IDX_A, 2238 ARMMMUIdx_S1E3 = 3 | ARM_MMU_IDX_A, 2239 ARMMMUIdx_S1SE0 = 4 | ARM_MMU_IDX_A, 2240 ARMMMUIdx_S1SE1 = 5 | ARM_MMU_IDX_A, 2241 ARMMMUIdx_S2NS = 6 | ARM_MMU_IDX_A, 2242 ARMMMUIdx_MUser = 0 | ARM_MMU_IDX_M, 2243 ARMMMUIdx_MPriv = 1 | ARM_MMU_IDX_M, 2244 ARMMMUIdx_MNegPri = 2 | ARM_MMU_IDX_M, 2245 ARMMMUIdx_MSUser = 3 | ARM_MMU_IDX_M, 2246 ARMMMUIdx_MSPriv = 4 | ARM_MMU_IDX_M, 2247 ARMMMUIdx_MSNegPri = 5 | ARM_MMU_IDX_M, 2248 /* Indexes below here don't have TLBs and are used only for AT system 2249 * instructions or for the first stage of an S12 page table walk. 2250 */ 2251 ARMMMUIdx_S1NSE0 = 0 | ARM_MMU_IDX_NOTLB, 2252 ARMMMUIdx_S1NSE1 = 1 | ARM_MMU_IDX_NOTLB, 2253 } ARMMMUIdx; 2254 2255 /* Bit macros for the core-mmu-index values for each index, 2256 * for use when calling tlb_flush_by_mmuidx() and friends. 2257 */ 2258 typedef enum ARMMMUIdxBit { 2259 ARMMMUIdxBit_S12NSE0 = 1 << 0, 2260 ARMMMUIdxBit_S12NSE1 = 1 << 1, 2261 ARMMMUIdxBit_S1E2 = 1 << 2, 2262 ARMMMUIdxBit_S1E3 = 1 << 3, 2263 ARMMMUIdxBit_S1SE0 = 1 << 4, 2264 ARMMMUIdxBit_S1SE1 = 1 << 5, 2265 ARMMMUIdxBit_S2NS = 1 << 6, 2266 ARMMMUIdxBit_MUser = 1 << 0, 2267 ARMMMUIdxBit_MPriv = 1 << 1, 2268 ARMMMUIdxBit_MNegPri = 1 << 2, 2269 ARMMMUIdxBit_MSUser = 1 << 3, 2270 ARMMMUIdxBit_MSPriv = 1 << 4, 2271 ARMMMUIdxBit_MSNegPri = 1 << 5, 2272 } ARMMMUIdxBit; 2273 2274 #define MMU_USER_IDX 0 2275 2276 static inline int arm_to_core_mmu_idx(ARMMMUIdx mmu_idx) 2277 { 2278 return mmu_idx & ARM_MMU_IDX_COREIDX_MASK; 2279 } 2280 2281 static inline ARMMMUIdx core_to_arm_mmu_idx(CPUARMState *env, int mmu_idx) 2282 { 2283 if (arm_feature(env, ARM_FEATURE_M)) { 2284 return mmu_idx | ARM_MMU_IDX_M; 2285 } else { 2286 return mmu_idx | ARM_MMU_IDX_A; 2287 } 2288 } 2289 2290 /* Return the exception level we're running at if this is our mmu_idx */ 2291 static inline int arm_mmu_idx_to_el(ARMMMUIdx mmu_idx) 2292 { 2293 switch (mmu_idx & ARM_MMU_IDX_TYPE_MASK) { 2294 case ARM_MMU_IDX_A: 2295 return mmu_idx & 3; 2296 case ARM_MMU_IDX_M: 2297 return (mmu_idx == ARMMMUIdx_MUser || mmu_idx == ARMMMUIdx_MSUser) 2298 ? 0 : 1; 2299 default: 2300 g_assert_not_reached(); 2301 } 2302 } 2303 2304 /* Determine the current mmu_idx to use for normal loads/stores */ 2305 static inline int cpu_mmu_index(CPUARMState *env, bool ifetch) 2306 { 2307 int el = arm_current_el(env); 2308 2309 if (arm_feature(env, ARM_FEATURE_M)) { 2310 ARMMMUIdx mmu_idx = el == 0 ? ARMMMUIdx_MUser : ARMMMUIdx_MPriv; 2311 2312 if (armv7m_nvic_neg_prio_requested(env->nvic, env->v7m.secure)) { 2313 mmu_idx = ARMMMUIdx_MNegPri; 2314 } 2315 2316 if (env->v7m.secure) { 2317 mmu_idx += ARMMMUIdx_MSUser; 2318 } 2319 2320 return arm_to_core_mmu_idx(mmu_idx); 2321 } 2322 2323 if (el < 2 && arm_is_secure_below_el3(env)) { 2324 return arm_to_core_mmu_idx(ARMMMUIdx_S1SE0 + el); 2325 } 2326 return el; 2327 } 2328 2329 /* Indexes used when registering address spaces with cpu_address_space_init */ 2330 typedef enum ARMASIdx { 2331 ARMASIdx_NS = 0, 2332 ARMASIdx_S = 1, 2333 } ARMASIdx; 2334 2335 /* Return the Exception Level targeted by debug exceptions. */ 2336 static inline int arm_debug_target_el(CPUARMState *env) 2337 { 2338 bool secure = arm_is_secure(env); 2339 bool route_to_el2 = false; 2340 2341 if (arm_feature(env, ARM_FEATURE_EL2) && !secure) { 2342 route_to_el2 = env->cp15.hcr_el2 & HCR_TGE || 2343 env->cp15.mdcr_el2 & (1 << 8); 2344 } 2345 2346 if (route_to_el2) { 2347 return 2; 2348 } else if (arm_feature(env, ARM_FEATURE_EL3) && 2349 !arm_el_is_aa64(env, 3) && secure) { 2350 return 3; 2351 } else { 2352 return 1; 2353 } 2354 } 2355 2356 static inline bool aa64_generate_debug_exceptions(CPUARMState *env) 2357 { 2358 if (arm_is_secure(env)) { 2359 /* MDCR_EL3.SDD disables debug events from Secure state */ 2360 if (extract32(env->cp15.mdcr_el3, 16, 1) != 0 2361 || arm_current_el(env) == 3) { 2362 return false; 2363 } 2364 } 2365 2366 if (arm_current_el(env) == arm_debug_target_el(env)) { 2367 if ((extract32(env->cp15.mdscr_el1, 13, 1) == 0) 2368 || (env->daif & PSTATE_D)) { 2369 return false; 2370 } 2371 } 2372 return true; 2373 } 2374 2375 static inline bool aa32_generate_debug_exceptions(CPUARMState *env) 2376 { 2377 int el = arm_current_el(env); 2378 2379 if (el == 0 && arm_el_is_aa64(env, 1)) { 2380 return aa64_generate_debug_exceptions(env); 2381 } 2382 2383 if (arm_is_secure(env)) { 2384 int spd; 2385 2386 if (el == 0 && (env->cp15.sder & 1)) { 2387 /* SDER.SUIDEN means debug exceptions from Secure EL0 2388 * are always enabled. Otherwise they are controlled by 2389 * SDCR.SPD like those from other Secure ELs. 2390 */ 2391 return true; 2392 } 2393 2394 spd = extract32(env->cp15.mdcr_el3, 14, 2); 2395 switch (spd) { 2396 case 1: 2397 /* SPD == 0b01 is reserved, but behaves as 0b00. */ 2398 case 0: 2399 /* For 0b00 we return true if external secure invasive debug 2400 * is enabled. On real hardware this is controlled by external 2401 * signals to the core. QEMU always permits debug, and behaves 2402 * as if DBGEN, SPIDEN, NIDEN and SPNIDEN are all tied high. 2403 */ 2404 return true; 2405 case 2: 2406 return false; 2407 case 3: 2408 return true; 2409 } 2410 } 2411 2412 return el != 2; 2413 } 2414 2415 /* Return true if debugging exceptions are currently enabled. 2416 * This corresponds to what in ARM ARM pseudocode would be 2417 * if UsingAArch32() then 2418 * return AArch32.GenerateDebugExceptions() 2419 * else 2420 * return AArch64.GenerateDebugExceptions() 2421 * We choose to push the if() down into this function for clarity, 2422 * since the pseudocode has it at all callsites except for the one in 2423 * CheckSoftwareStep(), where it is elided because both branches would 2424 * always return the same value. 2425 * 2426 * Parts of the pseudocode relating to EL2 and EL3 are omitted because we 2427 * don't yet implement those exception levels or their associated trap bits. 2428 */ 2429 static inline bool arm_generate_debug_exceptions(CPUARMState *env) 2430 { 2431 if (env->aarch64) { 2432 return aa64_generate_debug_exceptions(env); 2433 } else { 2434 return aa32_generate_debug_exceptions(env); 2435 } 2436 } 2437 2438 /* Is single-stepping active? (Note that the "is EL_D AArch64?" check 2439 * implicitly means this always returns false in pre-v8 CPUs.) 2440 */ 2441 static inline bool arm_singlestep_active(CPUARMState *env) 2442 { 2443 return extract32(env->cp15.mdscr_el1, 0, 1) 2444 && arm_el_is_aa64(env, arm_debug_target_el(env)) 2445 && arm_generate_debug_exceptions(env); 2446 } 2447 2448 static inline bool arm_sctlr_b(CPUARMState *env) 2449 { 2450 return 2451 /* We need not implement SCTLR.ITD in user-mode emulation, so 2452 * let linux-user ignore the fact that it conflicts with SCTLR_B. 2453 * This lets people run BE32 binaries with "-cpu any". 2454 */ 2455 #ifndef CONFIG_USER_ONLY 2456 !arm_feature(env, ARM_FEATURE_V7) && 2457 #endif 2458 (env->cp15.sctlr_el[1] & SCTLR_B) != 0; 2459 } 2460 2461 /* Return true if the processor is in big-endian mode. */ 2462 static inline bool arm_cpu_data_is_big_endian(CPUARMState *env) 2463 { 2464 int cur_el; 2465 2466 /* In 32bit endianness is determined by looking at CPSR's E bit */ 2467 if (!is_a64(env)) { 2468 return 2469 #ifdef CONFIG_USER_ONLY 2470 /* In system mode, BE32 is modelled in line with the 2471 * architecture (as word-invariant big-endianness), where loads 2472 * and stores are done little endian but from addresses which 2473 * are adjusted by XORing with the appropriate constant. So the 2474 * endianness to use for the raw data access is not affected by 2475 * SCTLR.B. 2476 * In user mode, however, we model BE32 as byte-invariant 2477 * big-endianness (because user-only code cannot tell the 2478 * difference), and so we need to use a data access endianness 2479 * that depends on SCTLR.B. 2480 */ 2481 arm_sctlr_b(env) || 2482 #endif 2483 ((env->uncached_cpsr & CPSR_E) ? 1 : 0); 2484 } 2485 2486 cur_el = arm_current_el(env); 2487 2488 if (cur_el == 0) { 2489 return (env->cp15.sctlr_el[1] & SCTLR_E0E) != 0; 2490 } 2491 2492 return (env->cp15.sctlr_el[cur_el] & SCTLR_EE) != 0; 2493 } 2494 2495 #include "exec/cpu-all.h" 2496 2497 /* Bit usage in the TB flags field: bit 31 indicates whether we are 2498 * in 32 or 64 bit mode. The meaning of the other bits depends on that. 2499 * We put flags which are shared between 32 and 64 bit mode at the top 2500 * of the word, and flags which apply to only one mode at the bottom. 2501 */ 2502 #define ARM_TBFLAG_AARCH64_STATE_SHIFT 31 2503 #define ARM_TBFLAG_AARCH64_STATE_MASK (1U << ARM_TBFLAG_AARCH64_STATE_SHIFT) 2504 #define ARM_TBFLAG_MMUIDX_SHIFT 28 2505 #define ARM_TBFLAG_MMUIDX_MASK (0x7 << ARM_TBFLAG_MMUIDX_SHIFT) 2506 #define ARM_TBFLAG_SS_ACTIVE_SHIFT 27 2507 #define ARM_TBFLAG_SS_ACTIVE_MASK (1 << ARM_TBFLAG_SS_ACTIVE_SHIFT) 2508 #define ARM_TBFLAG_PSTATE_SS_SHIFT 26 2509 #define ARM_TBFLAG_PSTATE_SS_MASK (1 << ARM_TBFLAG_PSTATE_SS_SHIFT) 2510 /* Target EL if we take a floating-point-disabled exception */ 2511 #define ARM_TBFLAG_FPEXC_EL_SHIFT 24 2512 #define ARM_TBFLAG_FPEXC_EL_MASK (0x3 << ARM_TBFLAG_FPEXC_EL_SHIFT) 2513 2514 /* Bit usage when in AArch32 state: */ 2515 #define ARM_TBFLAG_THUMB_SHIFT 0 2516 #define ARM_TBFLAG_THUMB_MASK (1 << ARM_TBFLAG_THUMB_SHIFT) 2517 #define ARM_TBFLAG_VECLEN_SHIFT 1 2518 #define ARM_TBFLAG_VECLEN_MASK (0x7 << ARM_TBFLAG_VECLEN_SHIFT) 2519 #define ARM_TBFLAG_VECSTRIDE_SHIFT 4 2520 #define ARM_TBFLAG_VECSTRIDE_MASK (0x3 << ARM_TBFLAG_VECSTRIDE_SHIFT) 2521 #define ARM_TBFLAG_VFPEN_SHIFT 7 2522 #define ARM_TBFLAG_VFPEN_MASK (1 << ARM_TBFLAG_VFPEN_SHIFT) 2523 #define ARM_TBFLAG_CONDEXEC_SHIFT 8 2524 #define ARM_TBFLAG_CONDEXEC_MASK (0xff << ARM_TBFLAG_CONDEXEC_SHIFT) 2525 #define ARM_TBFLAG_SCTLR_B_SHIFT 16 2526 #define ARM_TBFLAG_SCTLR_B_MASK (1 << ARM_TBFLAG_SCTLR_B_SHIFT) 2527 /* We store the bottom two bits of the CPAR as TB flags and handle 2528 * checks on the other bits at runtime 2529 */ 2530 #define ARM_TBFLAG_XSCALE_CPAR_SHIFT 17 2531 #define ARM_TBFLAG_XSCALE_CPAR_MASK (3 << ARM_TBFLAG_XSCALE_CPAR_SHIFT) 2532 /* Indicates whether cp register reads and writes by guest code should access 2533 * the secure or nonsecure bank of banked registers; note that this is not 2534 * the same thing as the current security state of the processor! 2535 */ 2536 #define ARM_TBFLAG_NS_SHIFT 19 2537 #define ARM_TBFLAG_NS_MASK (1 << ARM_TBFLAG_NS_SHIFT) 2538 #define ARM_TBFLAG_BE_DATA_SHIFT 20 2539 #define ARM_TBFLAG_BE_DATA_MASK (1 << ARM_TBFLAG_BE_DATA_SHIFT) 2540 /* For M profile only, Handler (ie not Thread) mode */ 2541 #define ARM_TBFLAG_HANDLER_SHIFT 21 2542 #define ARM_TBFLAG_HANDLER_MASK (1 << ARM_TBFLAG_HANDLER_SHIFT) 2543 2544 /* Bit usage when in AArch64 state */ 2545 #define ARM_TBFLAG_TBI0_SHIFT 0 /* TBI0 for EL0/1 or TBI for EL2/3 */ 2546 #define ARM_TBFLAG_TBI0_MASK (0x1ull << ARM_TBFLAG_TBI0_SHIFT) 2547 #define ARM_TBFLAG_TBI1_SHIFT 1 /* TBI1 for EL0/1 */ 2548 #define ARM_TBFLAG_TBI1_MASK (0x1ull << ARM_TBFLAG_TBI1_SHIFT) 2549 2550 /* some convenience accessor macros */ 2551 #define ARM_TBFLAG_AARCH64_STATE(F) \ 2552 (((F) & ARM_TBFLAG_AARCH64_STATE_MASK) >> ARM_TBFLAG_AARCH64_STATE_SHIFT) 2553 #define ARM_TBFLAG_MMUIDX(F) \ 2554 (((F) & ARM_TBFLAG_MMUIDX_MASK) >> ARM_TBFLAG_MMUIDX_SHIFT) 2555 #define ARM_TBFLAG_SS_ACTIVE(F) \ 2556 (((F) & ARM_TBFLAG_SS_ACTIVE_MASK) >> ARM_TBFLAG_SS_ACTIVE_SHIFT) 2557 #define ARM_TBFLAG_PSTATE_SS(F) \ 2558 (((F) & ARM_TBFLAG_PSTATE_SS_MASK) >> ARM_TBFLAG_PSTATE_SS_SHIFT) 2559 #define ARM_TBFLAG_FPEXC_EL(F) \ 2560 (((F) & ARM_TBFLAG_FPEXC_EL_MASK) >> ARM_TBFLAG_FPEXC_EL_SHIFT) 2561 #define ARM_TBFLAG_THUMB(F) \ 2562 (((F) & ARM_TBFLAG_THUMB_MASK) >> ARM_TBFLAG_THUMB_SHIFT) 2563 #define ARM_TBFLAG_VECLEN(F) \ 2564 (((F) & ARM_TBFLAG_VECLEN_MASK) >> ARM_TBFLAG_VECLEN_SHIFT) 2565 #define ARM_TBFLAG_VECSTRIDE(F) \ 2566 (((F) & ARM_TBFLAG_VECSTRIDE_MASK) >> ARM_TBFLAG_VECSTRIDE_SHIFT) 2567 #define ARM_TBFLAG_VFPEN(F) \ 2568 (((F) & ARM_TBFLAG_VFPEN_MASK) >> ARM_TBFLAG_VFPEN_SHIFT) 2569 #define ARM_TBFLAG_CONDEXEC(F) \ 2570 (((F) & ARM_TBFLAG_CONDEXEC_MASK) >> ARM_TBFLAG_CONDEXEC_SHIFT) 2571 #define ARM_TBFLAG_SCTLR_B(F) \ 2572 (((F) & ARM_TBFLAG_SCTLR_B_MASK) >> ARM_TBFLAG_SCTLR_B_SHIFT) 2573 #define ARM_TBFLAG_XSCALE_CPAR(F) \ 2574 (((F) & ARM_TBFLAG_XSCALE_CPAR_MASK) >> ARM_TBFLAG_XSCALE_CPAR_SHIFT) 2575 #define ARM_TBFLAG_NS(F) \ 2576 (((F) & ARM_TBFLAG_NS_MASK) >> ARM_TBFLAG_NS_SHIFT) 2577 #define ARM_TBFLAG_BE_DATA(F) \ 2578 (((F) & ARM_TBFLAG_BE_DATA_MASK) >> ARM_TBFLAG_BE_DATA_SHIFT) 2579 #define ARM_TBFLAG_HANDLER(F) \ 2580 (((F) & ARM_TBFLAG_HANDLER_MASK) >> ARM_TBFLAG_HANDLER_SHIFT) 2581 #define ARM_TBFLAG_TBI0(F) \ 2582 (((F) & ARM_TBFLAG_TBI0_MASK) >> ARM_TBFLAG_TBI0_SHIFT) 2583 #define ARM_TBFLAG_TBI1(F) \ 2584 (((F) & ARM_TBFLAG_TBI1_MASK) >> ARM_TBFLAG_TBI1_SHIFT) 2585 2586 static inline bool bswap_code(bool sctlr_b) 2587 { 2588 #ifdef CONFIG_USER_ONLY 2589 /* BE8 (SCTLR.B = 0, TARGET_WORDS_BIGENDIAN = 1) is mixed endian. 2590 * The invalid combination SCTLR.B=1/CPSR.E=1/TARGET_WORDS_BIGENDIAN=0 2591 * would also end up as a mixed-endian mode with BE code, LE data. 2592 */ 2593 return 2594 #ifdef TARGET_WORDS_BIGENDIAN 2595 1 ^ 2596 #endif 2597 sctlr_b; 2598 #else 2599 /* All code access in ARM is little endian, and there are no loaders 2600 * doing swaps that need to be reversed 2601 */ 2602 return 0; 2603 #endif 2604 } 2605 2606 /* Return the exception level to which FP-disabled exceptions should 2607 * be taken, or 0 if FP is enabled. 2608 */ 2609 static inline int fp_exception_el(CPUARMState *env) 2610 { 2611 int fpen; 2612 int cur_el = arm_current_el(env); 2613 2614 /* CPACR and the CPTR registers don't exist before v6, so FP is 2615 * always accessible 2616 */ 2617 if (!arm_feature(env, ARM_FEATURE_V6)) { 2618 return 0; 2619 } 2620 2621 /* The CPACR controls traps to EL1, or PL1 if we're 32 bit: 2622 * 0, 2 : trap EL0 and EL1/PL1 accesses 2623 * 1 : trap only EL0 accesses 2624 * 3 : trap no accesses 2625 */ 2626 fpen = extract32(env->cp15.cpacr_el1, 20, 2); 2627 switch (fpen) { 2628 case 0: 2629 case 2: 2630 if (cur_el == 0 || cur_el == 1) { 2631 /* Trap to PL1, which might be EL1 or EL3 */ 2632 if (arm_is_secure(env) && !arm_el_is_aa64(env, 3)) { 2633 return 3; 2634 } 2635 return 1; 2636 } 2637 if (cur_el == 3 && !is_a64(env)) { 2638 /* Secure PL1 running at EL3 */ 2639 return 3; 2640 } 2641 break; 2642 case 1: 2643 if (cur_el == 0) { 2644 return 1; 2645 } 2646 break; 2647 case 3: 2648 break; 2649 } 2650 2651 /* For the CPTR registers we don't need to guard with an ARM_FEATURE 2652 * check because zero bits in the registers mean "don't trap". 2653 */ 2654 2655 /* CPTR_EL2 : present in v7VE or v8 */ 2656 if (cur_el <= 2 && extract32(env->cp15.cptr_el[2], 10, 1) 2657 && !arm_is_secure_below_el3(env)) { 2658 /* Trap FP ops at EL2, NS-EL1 or NS-EL0 to EL2 */ 2659 return 2; 2660 } 2661 2662 /* CPTR_EL3 : present in v8 */ 2663 if (extract32(env->cp15.cptr_el[3], 10, 1)) { 2664 /* Trap all FP ops to EL3 */ 2665 return 3; 2666 } 2667 2668 return 0; 2669 } 2670 2671 #ifdef CONFIG_USER_ONLY 2672 static inline bool arm_cpu_bswap_data(CPUARMState *env) 2673 { 2674 return 2675 #ifdef TARGET_WORDS_BIGENDIAN 2676 1 ^ 2677 #endif 2678 arm_cpu_data_is_big_endian(env); 2679 } 2680 #endif 2681 2682 #ifndef CONFIG_USER_ONLY 2683 /** 2684 * arm_regime_tbi0: 2685 * @env: CPUARMState 2686 * @mmu_idx: MMU index indicating required translation regime 2687 * 2688 * Extracts the TBI0 value from the appropriate TCR for the current EL 2689 * 2690 * Returns: the TBI0 value. 2691 */ 2692 uint32_t arm_regime_tbi0(CPUARMState *env, ARMMMUIdx mmu_idx); 2693 2694 /** 2695 * arm_regime_tbi1: 2696 * @env: CPUARMState 2697 * @mmu_idx: MMU index indicating required translation regime 2698 * 2699 * Extracts the TBI1 value from the appropriate TCR for the current EL 2700 * 2701 * Returns: the TBI1 value. 2702 */ 2703 uint32_t arm_regime_tbi1(CPUARMState *env, ARMMMUIdx mmu_idx); 2704 #else 2705 /* We can't handle tagged addresses properly in user-only mode */ 2706 static inline uint32_t arm_regime_tbi0(CPUARMState *env, ARMMMUIdx mmu_idx) 2707 { 2708 return 0; 2709 } 2710 2711 static inline uint32_t arm_regime_tbi1(CPUARMState *env, ARMMMUIdx mmu_idx) 2712 { 2713 return 0; 2714 } 2715 #endif 2716 2717 static inline void cpu_get_tb_cpu_state(CPUARMState *env, target_ulong *pc, 2718 target_ulong *cs_base, uint32_t *flags) 2719 { 2720 ARMMMUIdx mmu_idx = core_to_arm_mmu_idx(env, cpu_mmu_index(env, false)); 2721 if (is_a64(env)) { 2722 *pc = env->pc; 2723 *flags = ARM_TBFLAG_AARCH64_STATE_MASK; 2724 /* Get control bits for tagged addresses */ 2725 *flags |= (arm_regime_tbi0(env, mmu_idx) << ARM_TBFLAG_TBI0_SHIFT); 2726 *flags |= (arm_regime_tbi1(env, mmu_idx) << ARM_TBFLAG_TBI1_SHIFT); 2727 } else { 2728 *pc = env->regs[15]; 2729 *flags = (env->thumb << ARM_TBFLAG_THUMB_SHIFT) 2730 | (env->vfp.vec_len << ARM_TBFLAG_VECLEN_SHIFT) 2731 | (env->vfp.vec_stride << ARM_TBFLAG_VECSTRIDE_SHIFT) 2732 | (env->condexec_bits << ARM_TBFLAG_CONDEXEC_SHIFT) 2733 | (arm_sctlr_b(env) << ARM_TBFLAG_SCTLR_B_SHIFT); 2734 if (!(access_secure_reg(env))) { 2735 *flags |= ARM_TBFLAG_NS_MASK; 2736 } 2737 if (env->vfp.xregs[ARM_VFP_FPEXC] & (1 << 30) 2738 || arm_el_is_aa64(env, 1)) { 2739 *flags |= ARM_TBFLAG_VFPEN_MASK; 2740 } 2741 *flags |= (extract32(env->cp15.c15_cpar, 0, 2) 2742 << ARM_TBFLAG_XSCALE_CPAR_SHIFT); 2743 } 2744 2745 *flags |= (arm_to_core_mmu_idx(mmu_idx) << ARM_TBFLAG_MMUIDX_SHIFT); 2746 2747 /* The SS_ACTIVE and PSTATE_SS bits correspond to the state machine 2748 * states defined in the ARM ARM for software singlestep: 2749 * SS_ACTIVE PSTATE.SS State 2750 * 0 x Inactive (the TB flag for SS is always 0) 2751 * 1 0 Active-pending 2752 * 1 1 Active-not-pending 2753 */ 2754 if (arm_singlestep_active(env)) { 2755 *flags |= ARM_TBFLAG_SS_ACTIVE_MASK; 2756 if (is_a64(env)) { 2757 if (env->pstate & PSTATE_SS) { 2758 *flags |= ARM_TBFLAG_PSTATE_SS_MASK; 2759 } 2760 } else { 2761 if (env->uncached_cpsr & PSTATE_SS) { 2762 *flags |= ARM_TBFLAG_PSTATE_SS_MASK; 2763 } 2764 } 2765 } 2766 if (arm_cpu_data_is_big_endian(env)) { 2767 *flags |= ARM_TBFLAG_BE_DATA_MASK; 2768 } 2769 *flags |= fp_exception_el(env) << ARM_TBFLAG_FPEXC_EL_SHIFT; 2770 2771 if (arm_v7m_is_handler_mode(env)) { 2772 *flags |= ARM_TBFLAG_HANDLER_MASK; 2773 } 2774 2775 *cs_base = 0; 2776 } 2777 2778 enum { 2779 QEMU_PSCI_CONDUIT_DISABLED = 0, 2780 QEMU_PSCI_CONDUIT_SMC = 1, 2781 QEMU_PSCI_CONDUIT_HVC = 2, 2782 }; 2783 2784 #ifndef CONFIG_USER_ONLY 2785 /* Return the address space index to use for a memory access */ 2786 static inline int arm_asidx_from_attrs(CPUState *cs, MemTxAttrs attrs) 2787 { 2788 return attrs.secure ? ARMASIdx_S : ARMASIdx_NS; 2789 } 2790 2791 /* Return the AddressSpace to use for a memory access 2792 * (which depends on whether the access is S or NS, and whether 2793 * the board gave us a separate AddressSpace for S accesses). 2794 */ 2795 static inline AddressSpace *arm_addressspace(CPUState *cs, MemTxAttrs attrs) 2796 { 2797 return cpu_get_address_space(cs, arm_asidx_from_attrs(cs, attrs)); 2798 } 2799 #endif 2800 2801 /** 2802 * arm_register_el_change_hook: 2803 * Register a hook function which will be called back whenever this 2804 * CPU changes exception level or mode. The hook function will be 2805 * passed a pointer to the ARMCPU and the opaque data pointer passed 2806 * to this function when the hook was registered. 2807 * 2808 * Note that we currently only support registering a single hook function, 2809 * and will assert if this function is called twice. 2810 * This facility is intended for the use of the GICv3 emulation. 2811 */ 2812 void arm_register_el_change_hook(ARMCPU *cpu, ARMELChangeHook *hook, 2813 void *opaque); 2814 2815 /** 2816 * arm_get_el_change_hook_opaque: 2817 * Return the opaque data that will be used by the el_change_hook 2818 * for this CPU. 2819 */ 2820 static inline void *arm_get_el_change_hook_opaque(ARMCPU *cpu) 2821 { 2822 return cpu->el_change_hook_opaque; 2823 } 2824 2825 #endif 2826