1 /* 2 * ARM virtual CPU header 3 * 4 * Copyright (c) 2003 Fabrice Bellard 5 * 6 * This library is free software; you can redistribute it and/or 7 * modify it under the terms of the GNU Lesser General Public 8 * License as published by the Free Software Foundation; either 9 * version 2.1 of the License, or (at your option) any later version. 10 * 11 * This library is distributed in the hope that it will be useful, 12 * but WITHOUT ANY WARRANTY; without even the implied warranty of 13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU 14 * Lesser General Public License for more details. 15 * 16 * You should have received a copy of the GNU Lesser General Public 17 * License along with this library; if not, see <http://www.gnu.org/licenses/>. 18 */ 19 20 #ifndef ARM_CPU_H 21 #define ARM_CPU_H 22 23 #include "kvm-consts.h" 24 #include "qemu/cpu-float.h" 25 #include "hw/registerfields.h" 26 #include "cpu-qom.h" 27 #include "exec/cpu-defs.h" 28 #include "exec/gdbstub.h" 29 #include "exec/page-protection.h" 30 #include "qapi/qapi-types-common.h" 31 #include "target/arm/multiprocessing.h" 32 #include "target/arm/gtimer.h" 33 34 #ifdef TARGET_AARCH64 35 #define KVM_HAVE_MCE_INJECTION 1 36 #endif 37 38 #define EXCP_UDEF 1 /* undefined instruction */ 39 #define EXCP_SWI 2 /* software interrupt */ 40 #define EXCP_PREFETCH_ABORT 3 41 #define EXCP_DATA_ABORT 4 42 #define EXCP_IRQ 5 43 #define EXCP_FIQ 6 44 #define EXCP_BKPT 7 45 #define EXCP_EXCEPTION_EXIT 8 /* Return from v7M exception. */ 46 #define EXCP_KERNEL_TRAP 9 /* Jumped to kernel code page. */ 47 #define EXCP_HVC 11 /* HyperVisor Call */ 48 #define EXCP_HYP_TRAP 12 49 #define EXCP_SMC 13 /* Secure Monitor Call */ 50 #define EXCP_VIRQ 14 51 #define EXCP_VFIQ 15 52 #define EXCP_SEMIHOST 16 /* semihosting call */ 53 #define EXCP_NOCP 17 /* v7M NOCP UsageFault */ 54 #define EXCP_INVSTATE 18 /* v7M INVSTATE UsageFault */ 55 #define EXCP_STKOF 19 /* v8M STKOF UsageFault */ 56 #define EXCP_LAZYFP 20 /* v7M fault during lazy FP stacking */ 57 #define EXCP_LSERR 21 /* v8M LSERR SecureFault */ 58 #define EXCP_UNALIGNED 22 /* v7M UNALIGNED UsageFault */ 59 #define EXCP_DIVBYZERO 23 /* v7M DIVBYZERO UsageFault */ 60 #define EXCP_VSERR 24 61 #define EXCP_GPC 25 /* v9 Granule Protection Check Fault */ 62 #define EXCP_NMI 26 63 #define EXCP_VINMI 27 64 #define EXCP_VFNMI 28 65 /* NB: add new EXCP_ defines to the array in arm_log_exception() too */ 66 67 #define ARMV7M_EXCP_RESET 1 68 #define ARMV7M_EXCP_NMI 2 69 #define ARMV7M_EXCP_HARD 3 70 #define ARMV7M_EXCP_MEM 4 71 #define ARMV7M_EXCP_BUS 5 72 #define ARMV7M_EXCP_USAGE 6 73 #define ARMV7M_EXCP_SECURE 7 74 #define ARMV7M_EXCP_SVC 11 75 #define ARMV7M_EXCP_DEBUG 12 76 #define ARMV7M_EXCP_PENDSV 14 77 #define ARMV7M_EXCP_SYSTICK 15 78 79 /* ARM-specific interrupt pending bits. */ 80 #define CPU_INTERRUPT_FIQ CPU_INTERRUPT_TGT_EXT_1 81 #define CPU_INTERRUPT_VIRQ CPU_INTERRUPT_TGT_EXT_2 82 #define CPU_INTERRUPT_VFIQ CPU_INTERRUPT_TGT_EXT_3 83 #define CPU_INTERRUPT_VSERR CPU_INTERRUPT_TGT_INT_0 84 #define CPU_INTERRUPT_NMI CPU_INTERRUPT_TGT_EXT_4 85 #define CPU_INTERRUPT_VINMI CPU_INTERRUPT_TGT_EXT_0 86 #define CPU_INTERRUPT_VFNMI CPU_INTERRUPT_TGT_INT_1 87 88 /* The usual mapping for an AArch64 system register to its AArch32 89 * counterpart is for the 32 bit world to have access to the lower 90 * half only (with writes leaving the upper half untouched). It's 91 * therefore useful to be able to pass TCG the offset of the least 92 * significant half of a uint64_t struct member. 93 */ 94 #if HOST_BIG_ENDIAN 95 #define offsetoflow32(S, M) (offsetof(S, M) + sizeof(uint32_t)) 96 #define offsetofhigh32(S, M) offsetof(S, M) 97 #else 98 #define offsetoflow32(S, M) offsetof(S, M) 99 #define offsetofhigh32(S, M) (offsetof(S, M) + sizeof(uint32_t)) 100 #endif 101 102 /* ARM-specific extra insn start words: 103 * 1: Conditional execution bits 104 * 2: Partial exception syndrome for data aborts 105 */ 106 #define TARGET_INSN_START_EXTRA_WORDS 2 107 108 /* The 2nd extra word holding syndrome info for data aborts does not use 109 * the upper 6 bits nor the lower 13 bits. We mask and shift it down to 110 * help the sleb128 encoder do a better job. 111 * When restoring the CPU state, we shift it back up. 112 */ 113 #define ARM_INSN_START_WORD2_MASK ((1 << 26) - 1) 114 #define ARM_INSN_START_WORD2_SHIFT 13 115 116 /* We currently assume float and double are IEEE single and double 117 precision respectively. 118 Doing runtime conversions is tricky because VFP registers may contain 119 integer values (eg. as the result of a FTOSI instruction). 120 s<2n> maps to the least significant half of d<n> 121 s<2n+1> maps to the most significant half of d<n> 122 */ 123 124 /** 125 * DynamicGDBFeatureInfo: 126 * @desc: Contains the feature descriptions. 127 * @data: A union with data specific to the set of registers 128 * @cpregs_keys: Array that contains the corresponding Key of 129 * a given cpreg with the same order of the cpreg 130 * in the XML description. 131 */ 132 typedef struct DynamicGDBFeatureInfo { 133 GDBFeature desc; 134 union { 135 struct { 136 uint32_t *keys; 137 } cpregs; 138 } data; 139 } DynamicGDBFeatureInfo; 140 141 /* CPU state for each instance of a generic timer (in cp15 c14) */ 142 typedef struct ARMGenericTimer { 143 uint64_t cval; /* Timer CompareValue register */ 144 uint64_t ctl; /* Timer Control register */ 145 } ARMGenericTimer; 146 147 /* Define a maximum sized vector register. 148 * For 32-bit, this is a 128-bit NEON/AdvSIMD register. 149 * For 64-bit, this is a 2048-bit SVE register. 150 * 151 * Note that the mapping between S, D, and Q views of the register bank 152 * differs between AArch64 and AArch32. 153 * In AArch32: 154 * Qn = regs[n].d[1]:regs[n].d[0] 155 * Dn = regs[n / 2].d[n & 1] 156 * Sn = regs[n / 4].d[n % 4 / 2], 157 * bits 31..0 for even n, and bits 63..32 for odd n 158 * (and regs[16] to regs[31] are inaccessible) 159 * In AArch64: 160 * Zn = regs[n].d[*] 161 * Qn = regs[n].d[1]:regs[n].d[0] 162 * Dn = regs[n].d[0] 163 * Sn = regs[n].d[0] bits 31..0 164 * Hn = regs[n].d[0] bits 15..0 165 * 166 * This corresponds to the architecturally defined mapping between 167 * the two execution states, and means we do not need to explicitly 168 * map these registers when changing states. 169 * 170 * Align the data for use with TCG host vector operations. 171 */ 172 173 #ifdef TARGET_AARCH64 174 # define ARM_MAX_VQ 16 175 #else 176 # define ARM_MAX_VQ 1 177 #endif 178 179 typedef struct ARMVectorReg { 180 uint64_t d[2 * ARM_MAX_VQ] QEMU_ALIGNED(16); 181 } ARMVectorReg; 182 183 #ifdef TARGET_AARCH64 184 /* In AArch32 mode, predicate registers do not exist at all. */ 185 typedef struct ARMPredicateReg { 186 uint64_t p[DIV_ROUND_UP(2 * ARM_MAX_VQ, 8)] QEMU_ALIGNED(16); 187 } ARMPredicateReg; 188 189 /* In AArch32 mode, PAC keys do not exist at all. */ 190 typedef struct ARMPACKey { 191 uint64_t lo, hi; 192 } ARMPACKey; 193 #endif 194 195 /* See the commentary above the TBFLAG field definitions. */ 196 typedef struct CPUARMTBFlags { 197 uint32_t flags; 198 target_ulong flags2; 199 } CPUARMTBFlags; 200 201 typedef struct ARMMMUFaultInfo ARMMMUFaultInfo; 202 203 typedef struct NVICState NVICState; 204 205 typedef struct CPUArchState { 206 /* Regs for current mode. */ 207 uint32_t regs[16]; 208 209 /* 32/64 switch only happens when taking and returning from 210 * exceptions so the overlap semantics are taken care of then 211 * instead of having a complicated union. 212 */ 213 /* Regs for A64 mode. */ 214 uint64_t xregs[32]; 215 uint64_t pc; 216 /* PSTATE isn't an architectural register for ARMv8. However, it is 217 * convenient for us to assemble the underlying state into a 32 bit format 218 * identical to the architectural format used for the SPSR. (This is also 219 * what the Linux kernel's 'pstate' field in signal handlers and KVM's 220 * 'pstate' register are.) Of the PSTATE bits: 221 * NZCV are kept in the split out env->CF/VF/NF/ZF, (which have the same 222 * semantics as for AArch32, as described in the comments on each field) 223 * nRW (also known as M[4]) is kept, inverted, in env->aarch64 224 * DAIF (exception masks) are kept in env->daif 225 * BTYPE is kept in env->btype 226 * SM and ZA are kept in env->svcr 227 * all other bits are stored in their correct places in env->pstate 228 */ 229 uint32_t pstate; 230 bool aarch64; /* True if CPU is in aarch64 state; inverse of PSTATE.nRW */ 231 bool thumb; /* True if CPU is in thumb mode; cpsr[5] */ 232 233 /* Cached TBFLAGS state. See below for which bits are included. */ 234 CPUARMTBFlags hflags; 235 236 /* Frequently accessed CPSR bits are stored separately for efficiency. 237 This contains all the other bits. Use cpsr_{read,write} to access 238 the whole CPSR. */ 239 uint32_t uncached_cpsr; 240 uint32_t spsr; 241 242 /* Banked registers. */ 243 uint64_t banked_spsr[8]; 244 uint32_t banked_r13[8]; 245 uint32_t banked_r14[8]; 246 247 /* These hold r8-r12. */ 248 uint32_t usr_regs[5]; 249 uint32_t fiq_regs[5]; 250 251 /* cpsr flag cache for faster execution */ 252 uint32_t CF; /* 0 or 1 */ 253 uint32_t VF; /* V is the bit 31. All other bits are undefined */ 254 uint32_t NF; /* N is bit 31. All other bits are undefined. */ 255 uint32_t ZF; /* Z set if zero. */ 256 uint32_t QF; /* 0 or 1 */ 257 uint32_t GE; /* cpsr[19:16] */ 258 uint32_t condexec_bits; /* IT bits. cpsr[15:10,26:25]. */ 259 uint32_t btype; /* BTI branch type. spsr[11:10]. */ 260 uint64_t daif; /* exception masks, in the bits they are in PSTATE */ 261 uint64_t svcr; /* PSTATE.{SM,ZA} in the bits they are in SVCR */ 262 263 uint64_t elr_el[4]; /* AArch64 exception link regs */ 264 uint64_t sp_el[4]; /* AArch64 banked stack pointers */ 265 266 /* System control coprocessor (cp15) */ 267 struct { 268 uint32_t c0_cpuid; 269 union { /* Cache size selection */ 270 struct { 271 uint64_t _unused_csselr0; 272 uint64_t csselr_ns; 273 uint64_t _unused_csselr1; 274 uint64_t csselr_s; 275 }; 276 uint64_t csselr_el[4]; 277 }; 278 union { /* System control register. */ 279 struct { 280 uint64_t _unused_sctlr; 281 uint64_t sctlr_ns; 282 uint64_t hsctlr; 283 uint64_t sctlr_s; 284 }; 285 uint64_t sctlr_el[4]; 286 }; 287 uint64_t vsctlr; /* Virtualization System control register. */ 288 uint64_t cpacr_el1; /* Architectural feature access control register */ 289 uint64_t cptr_el[4]; /* ARMv8 feature trap registers */ 290 uint32_t c1_xscaleauxcr; /* XScale auxiliary control register. */ 291 uint64_t sder; /* Secure debug enable register. */ 292 uint32_t nsacr; /* Non-secure access control register. */ 293 union { /* MMU translation table base 0. */ 294 struct { 295 uint64_t _unused_ttbr0_0; 296 uint64_t ttbr0_ns; 297 uint64_t _unused_ttbr0_1; 298 uint64_t ttbr0_s; 299 }; 300 uint64_t ttbr0_el[4]; 301 }; 302 union { /* MMU translation table base 1. */ 303 struct { 304 uint64_t _unused_ttbr1_0; 305 uint64_t ttbr1_ns; 306 uint64_t _unused_ttbr1_1; 307 uint64_t ttbr1_s; 308 }; 309 uint64_t ttbr1_el[4]; 310 }; 311 uint64_t vttbr_el2; /* Virtualization Translation Table Base. */ 312 uint64_t vsttbr_el2; /* Secure Virtualization Translation Table. */ 313 /* MMU translation table base control. */ 314 uint64_t tcr_el[4]; 315 uint64_t vtcr_el2; /* Virtualization Translation Control. */ 316 uint64_t vstcr_el2; /* Secure Virtualization Translation Control. */ 317 uint32_t c2_data; /* MPU data cacheable bits. */ 318 uint32_t c2_insn; /* MPU instruction cacheable bits. */ 319 union { /* MMU domain access control register 320 * MPU write buffer control. 321 */ 322 struct { 323 uint64_t dacr_ns; 324 uint64_t dacr_s; 325 }; 326 struct { 327 uint64_t dacr32_el2; 328 }; 329 }; 330 uint32_t pmsav5_data_ap; /* PMSAv5 MPU data access permissions */ 331 uint32_t pmsav5_insn_ap; /* PMSAv5 MPU insn access permissions */ 332 uint64_t hcr_el2; /* Hypervisor configuration register */ 333 uint64_t hcrx_el2; /* Extended Hypervisor configuration register */ 334 uint64_t scr_el3; /* Secure configuration register. */ 335 union { /* Fault status registers. */ 336 struct { 337 uint64_t ifsr_ns; 338 uint64_t ifsr_s; 339 }; 340 struct { 341 uint64_t ifsr32_el2; 342 }; 343 }; 344 union { 345 struct { 346 uint64_t _unused_dfsr; 347 uint64_t dfsr_ns; 348 uint64_t hsr; 349 uint64_t dfsr_s; 350 }; 351 uint64_t esr_el[4]; 352 }; 353 uint32_t c6_region[8]; /* MPU base/size registers. */ 354 union { /* Fault address registers. */ 355 struct { 356 uint64_t _unused_far0; 357 #if HOST_BIG_ENDIAN 358 uint32_t ifar_ns; 359 uint32_t dfar_ns; 360 uint32_t ifar_s; 361 uint32_t dfar_s; 362 #else 363 uint32_t dfar_ns; 364 uint32_t ifar_ns; 365 uint32_t dfar_s; 366 uint32_t ifar_s; 367 #endif 368 uint64_t _unused_far3; 369 }; 370 uint64_t far_el[4]; 371 }; 372 uint64_t hpfar_el2; 373 uint64_t hstr_el2; 374 union { /* Translation result. */ 375 struct { 376 uint64_t _unused_par_0; 377 uint64_t par_ns; 378 uint64_t _unused_par_1; 379 uint64_t par_s; 380 }; 381 uint64_t par_el[4]; 382 }; 383 384 uint32_t c9_insn; /* Cache lockdown registers. */ 385 uint32_t c9_data; 386 uint64_t c9_pmcr; /* performance monitor control register */ 387 uint64_t c9_pmcnten; /* perf monitor counter enables */ 388 uint64_t c9_pmovsr; /* perf monitor overflow status */ 389 uint64_t c9_pmuserenr; /* perf monitor user enable */ 390 uint64_t c9_pmselr; /* perf monitor counter selection register */ 391 uint64_t c9_pminten; /* perf monitor interrupt enables */ 392 union { /* Memory attribute redirection */ 393 struct { 394 #if HOST_BIG_ENDIAN 395 uint64_t _unused_mair_0; 396 uint32_t mair1_ns; 397 uint32_t mair0_ns; 398 uint64_t _unused_mair_1; 399 uint32_t mair1_s; 400 uint32_t mair0_s; 401 #else 402 uint64_t _unused_mair_0; 403 uint32_t mair0_ns; 404 uint32_t mair1_ns; 405 uint64_t _unused_mair_1; 406 uint32_t mair0_s; 407 uint32_t mair1_s; 408 #endif 409 }; 410 uint64_t mair_el[4]; 411 }; 412 union { /* vector base address register */ 413 struct { 414 uint64_t _unused_vbar; 415 uint64_t vbar_ns; 416 uint64_t hvbar; 417 uint64_t vbar_s; 418 }; 419 uint64_t vbar_el[4]; 420 }; 421 uint32_t mvbar; /* (monitor) vector base address register */ 422 uint64_t rvbar; /* rvbar sampled from rvbar property at reset */ 423 struct { /* FCSE PID. */ 424 uint32_t fcseidr_ns; 425 uint32_t fcseidr_s; 426 }; 427 union { /* Context ID. */ 428 struct { 429 uint64_t _unused_contextidr_0; 430 uint64_t contextidr_ns; 431 uint64_t _unused_contextidr_1; 432 uint64_t contextidr_s; 433 }; 434 uint64_t contextidr_el[4]; 435 }; 436 union { /* User RW Thread register. */ 437 struct { 438 uint64_t tpidrurw_ns; 439 uint64_t tpidrprw_ns; 440 uint64_t htpidr; 441 uint64_t _tpidr_el3; 442 }; 443 uint64_t tpidr_el[4]; 444 }; 445 uint64_t tpidr2_el0; 446 /* The secure banks of these registers don't map anywhere */ 447 uint64_t tpidrurw_s; 448 uint64_t tpidrprw_s; 449 uint64_t tpidruro_s; 450 451 union { /* User RO Thread register. */ 452 uint64_t tpidruro_ns; 453 uint64_t tpidrro_el[1]; 454 }; 455 uint64_t c14_cntfrq; /* Counter Frequency register */ 456 uint64_t c14_cntkctl; /* Timer Control register */ 457 uint64_t cnthctl_el2; /* Counter/Timer Hyp Control register */ 458 uint64_t cntvoff_el2; /* Counter Virtual Offset register */ 459 uint64_t cntpoff_el2; /* Counter Physical Offset register */ 460 ARMGenericTimer c14_timer[NUM_GTIMERS]; 461 uint32_t c15_cpar; /* XScale Coprocessor Access Register */ 462 uint32_t c15_ticonfig; /* TI925T configuration byte. */ 463 uint32_t c15_i_max; /* Maximum D-cache dirty line index. */ 464 uint32_t c15_i_min; /* Minimum D-cache dirty line index. */ 465 uint32_t c15_threadid; /* TI debugger thread-ID. */ 466 uint32_t c15_config_base_address; /* SCU base address. */ 467 uint32_t c15_diagnostic; /* diagnostic register */ 468 uint32_t c15_power_diagnostic; 469 uint32_t c15_power_control; /* power control */ 470 uint64_t dbgbvr[16]; /* breakpoint value registers */ 471 uint64_t dbgbcr[16]; /* breakpoint control registers */ 472 uint64_t dbgwvr[16]; /* watchpoint value registers */ 473 uint64_t dbgwcr[16]; /* watchpoint control registers */ 474 uint64_t dbgclaim; /* DBGCLAIM bits */ 475 uint64_t mdscr_el1; 476 uint64_t oslsr_el1; /* OS Lock Status */ 477 uint64_t osdlr_el1; /* OS DoubleLock status */ 478 uint64_t mdcr_el2; 479 uint64_t mdcr_el3; 480 /* Stores the architectural value of the counter *the last time it was 481 * updated* by pmccntr_op_start. Accesses should always be surrounded 482 * by pmccntr_op_start/pmccntr_op_finish to guarantee the latest 483 * architecturally-correct value is being read/set. 484 */ 485 uint64_t c15_ccnt; 486 /* Stores the delta between the architectural value and the underlying 487 * cycle count during normal operation. It is used to update c15_ccnt 488 * to be the correct architectural value before accesses. During 489 * accesses, c15_ccnt_delta contains the underlying count being used 490 * for the access, after which it reverts to the delta value in 491 * pmccntr_op_finish. 492 */ 493 uint64_t c15_ccnt_delta; 494 uint64_t c14_pmevcntr[31]; 495 uint64_t c14_pmevcntr_delta[31]; 496 uint64_t c14_pmevtyper[31]; 497 uint64_t pmccfiltr_el0; /* Performance Monitor Filter Register */ 498 uint64_t vpidr_el2; /* Virtualization Processor ID Register */ 499 uint64_t vmpidr_el2; /* Virtualization Multiprocessor ID Register */ 500 uint64_t tfsr_el[4]; /* tfsre0_el1 is index 0. */ 501 uint64_t gcr_el1; 502 uint64_t rgsr_el1; 503 504 /* Minimal RAS registers */ 505 uint64_t disr_el1; 506 uint64_t vdisr_el2; 507 uint64_t vsesr_el2; 508 509 /* 510 * Fine-Grained Trap registers. We store these as arrays so the 511 * access checking code doesn't have to manually select 512 * HFGRTR_EL2 vs HFDFGRTR_EL2 etc when looking up the bit to test. 513 * FEAT_FGT2 will add more elements to these arrays. 514 */ 515 uint64_t fgt_read[2]; /* HFGRTR, HDFGRTR */ 516 uint64_t fgt_write[2]; /* HFGWTR, HDFGWTR */ 517 uint64_t fgt_exec[1]; /* HFGITR */ 518 519 /* RME registers */ 520 uint64_t gpccr_el3; 521 uint64_t gptbr_el3; 522 uint64_t mfar_el3; 523 524 /* NV2 register */ 525 uint64_t vncr_el2; 526 } cp15; 527 528 struct { 529 /* M profile has up to 4 stack pointers: 530 * a Main Stack Pointer and a Process Stack Pointer for each 531 * of the Secure and Non-Secure states. (If the CPU doesn't support 532 * the security extension then it has only two SPs.) 533 * In QEMU we always store the currently active SP in regs[13], 534 * and the non-active SP for the current security state in 535 * v7m.other_sp. The stack pointers for the inactive security state 536 * are stored in other_ss_msp and other_ss_psp. 537 * switch_v7m_security_state() is responsible for rearranging them 538 * when we change security state. 539 */ 540 uint32_t other_sp; 541 uint32_t other_ss_msp; 542 uint32_t other_ss_psp; 543 uint32_t vecbase[M_REG_NUM_BANKS]; 544 uint32_t basepri[M_REG_NUM_BANKS]; 545 uint32_t control[M_REG_NUM_BANKS]; 546 uint32_t ccr[M_REG_NUM_BANKS]; /* Configuration and Control */ 547 uint32_t cfsr[M_REG_NUM_BANKS]; /* Configurable Fault Status */ 548 uint32_t hfsr; /* HardFault Status */ 549 uint32_t dfsr; /* Debug Fault Status Register */ 550 uint32_t sfsr; /* Secure Fault Status Register */ 551 uint32_t mmfar[M_REG_NUM_BANKS]; /* MemManage Fault Address */ 552 uint32_t bfar; /* BusFault Address */ 553 uint32_t sfar; /* Secure Fault Address Register */ 554 unsigned mpu_ctrl[M_REG_NUM_BANKS]; /* MPU_CTRL */ 555 int exception; 556 uint32_t primask[M_REG_NUM_BANKS]; 557 uint32_t faultmask[M_REG_NUM_BANKS]; 558 uint32_t aircr; /* only holds r/w state if security extn implemented */ 559 uint32_t secure; /* Is CPU in Secure state? (not guest visible) */ 560 uint32_t csselr[M_REG_NUM_BANKS]; 561 uint32_t scr[M_REG_NUM_BANKS]; 562 uint32_t msplim[M_REG_NUM_BANKS]; 563 uint32_t psplim[M_REG_NUM_BANKS]; 564 uint32_t fpcar[M_REG_NUM_BANKS]; 565 uint32_t fpccr[M_REG_NUM_BANKS]; 566 uint32_t fpdscr[M_REG_NUM_BANKS]; 567 uint32_t cpacr[M_REG_NUM_BANKS]; 568 uint32_t nsacr; 569 uint32_t ltpsize; 570 uint32_t vpr; 571 } v7m; 572 573 /* Information associated with an exception about to be taken: 574 * code which raises an exception must set cs->exception_index and 575 * the relevant parts of this structure; the cpu_do_interrupt function 576 * will then set the guest-visible registers as part of the exception 577 * entry process. 578 */ 579 struct { 580 uint32_t syndrome; /* AArch64 format syndrome register */ 581 uint32_t fsr; /* AArch32 format fault status register info */ 582 uint64_t vaddress; /* virtual addr associated with exception, if any */ 583 uint32_t target_el; /* EL the exception should be targeted for */ 584 /* If we implement EL2 we will also need to store information 585 * about the intermediate physical address for stage 2 faults. 586 */ 587 } exception; 588 589 /* Information associated with an SError */ 590 struct { 591 uint8_t pending; 592 uint8_t has_esr; 593 uint64_t esr; 594 } serror; 595 596 uint8_t ext_dabt_raised; /* Tracking/verifying injection of ext DABT */ 597 598 /* State of our input IRQ/FIQ/VIRQ/VFIQ lines */ 599 uint32_t irq_line_state; 600 601 /* Thumb-2 EE state. */ 602 uint32_t teecr; 603 uint32_t teehbr; 604 605 /* VFP coprocessor state. */ 606 struct { 607 ARMVectorReg zregs[32]; 608 609 #ifdef TARGET_AARCH64 610 /* Store FFR as pregs[16] to make it easier to treat as any other. */ 611 #define FFR_PRED_NUM 16 612 ARMPredicateReg pregs[17]; 613 /* Scratch space for aa64 sve predicate temporary. */ 614 ARMPredicateReg preg_tmp; 615 #endif 616 617 /* We store these fpcsr fields separately for convenience. */ 618 uint32_t qc[4] QEMU_ALIGNED(16); 619 int vec_len; 620 int vec_stride; 621 622 uint32_t xregs[16]; 623 624 /* Scratch space for aa32 neon expansion. */ 625 uint32_t scratch[8]; 626 627 /* There are a number of distinct float control structures: 628 * 629 * fp_status: is the "normal" fp status. 630 * fp_status_fp16: used for half-precision calculations 631 * standard_fp_status : the ARM "Standard FPSCR Value" 632 * standard_fp_status_fp16 : used for half-precision 633 * calculations with the ARM "Standard FPSCR Value" 634 * 635 * Half-precision operations are governed by a separate 636 * flush-to-zero control bit in FPSCR:FZ16. We pass a separate 637 * status structure to control this. 638 * 639 * The "Standard FPSCR", ie default-NaN, flush-to-zero, 640 * round-to-nearest and is used by any operations (generally 641 * Neon) which the architecture defines as controlled by the 642 * standard FPSCR value rather than the FPSCR. 643 * 644 * The "standard FPSCR but for fp16 ops" is needed because 645 * the "standard FPSCR" tracks the FPSCR.FZ16 bit rather than 646 * using a fixed value for it. 647 * 648 * To avoid having to transfer exception bits around, we simply 649 * say that the FPSCR cumulative exception flags are the logical 650 * OR of the flags in the four fp statuses. This relies on the 651 * only thing which needs to read the exception flags being 652 * an explicit FPSCR read. 653 */ 654 float_status fp_status; 655 float_status fp_status_f16; 656 float_status standard_fp_status; 657 float_status standard_fp_status_f16; 658 659 uint64_t zcr_el[4]; /* ZCR_EL[1-3] */ 660 uint64_t smcr_el[4]; /* SMCR_EL[1-3] */ 661 } vfp; 662 663 uint64_t exclusive_addr; 664 uint64_t exclusive_val; 665 /* 666 * Contains the 'val' for the second 64-bit register of LDXP, which comes 667 * from the higher address, not the high part of a complete 128-bit value. 668 * In some ways it might be more convenient to record the exclusive value 669 * as the low and high halves of a 128 bit data value, but the current 670 * semantics of these fields are baked into the migration format. 671 */ 672 uint64_t exclusive_high; 673 674 /* iwMMXt coprocessor state. */ 675 struct { 676 uint64_t regs[16]; 677 uint64_t val; 678 679 uint32_t cregs[16]; 680 } iwmmxt; 681 682 #ifdef TARGET_AARCH64 683 struct { 684 ARMPACKey apia; 685 ARMPACKey apib; 686 ARMPACKey apda; 687 ARMPACKey apdb; 688 ARMPACKey apga; 689 } keys; 690 691 uint64_t scxtnum_el[4]; 692 693 /* 694 * SME ZA storage -- 256 x 256 byte array, with bytes in host word order, 695 * as we do with vfp.zregs[]. This corresponds to the architectural ZA 696 * array, where ZA[N] is in the least-significant bytes of env->zarray[N]. 697 * When SVL is less than the architectural maximum, the accessible 698 * storage is restricted, such that if the SVL is X bytes the guest can 699 * see only the bottom X elements of zarray[], and only the least 700 * significant X bytes of each element of the array. (In other words, 701 * the observable part is always square.) 702 * 703 * The ZA storage can also be considered as a set of square tiles of 704 * elements of different sizes. The mapping from tiles to the ZA array 705 * is architecturally defined, such that for tiles of elements of esz 706 * bytes, the Nth row (or "horizontal slice") of tile T is in 707 * ZA[T + N * esz]. Note that this means that each tile is not contiguous 708 * in the ZA storage, because its rows are striped through the ZA array. 709 * 710 * Because this is so large, keep this toward the end of the reset area, 711 * to keep the offsets into the rest of the structure smaller. 712 */ 713 ARMVectorReg zarray[ARM_MAX_VQ * 16]; 714 #endif 715 716 struct CPUBreakpoint *cpu_breakpoint[16]; 717 struct CPUWatchpoint *cpu_watchpoint[16]; 718 719 /* Optional fault info across tlb lookup. */ 720 ARMMMUFaultInfo *tlb_fi; 721 722 /* Fields up to this point are cleared by a CPU reset */ 723 struct {} end_reset_fields; 724 725 /* Fields after this point are preserved across CPU reset. */ 726 727 /* Internal CPU feature flags. */ 728 uint64_t features; 729 730 /* PMSAv7 MPU */ 731 struct { 732 uint32_t *drbar; 733 uint32_t *drsr; 734 uint32_t *dracr; 735 uint32_t rnr[M_REG_NUM_BANKS]; 736 } pmsav7; 737 738 /* PMSAv8 MPU */ 739 struct { 740 /* The PMSAv8 implementation also shares some PMSAv7 config 741 * and state: 742 * pmsav7.rnr (region number register) 743 * pmsav7_dregion (number of configured regions) 744 */ 745 uint32_t *rbar[M_REG_NUM_BANKS]; 746 uint32_t *rlar[M_REG_NUM_BANKS]; 747 uint32_t *hprbar; 748 uint32_t *hprlar; 749 uint32_t mair0[M_REG_NUM_BANKS]; 750 uint32_t mair1[M_REG_NUM_BANKS]; 751 uint32_t hprselr; 752 } pmsav8; 753 754 /* v8M SAU */ 755 struct { 756 uint32_t *rbar; 757 uint32_t *rlar; 758 uint32_t rnr; 759 uint32_t ctrl; 760 } sau; 761 762 #if !defined(CONFIG_USER_ONLY) 763 NVICState *nvic; 764 const struct arm_boot_info *boot_info; 765 /* Store GICv3CPUState to access from this struct */ 766 void *gicv3state; 767 #else /* CONFIG_USER_ONLY */ 768 /* For usermode syscall translation. */ 769 bool eabi; 770 #endif /* CONFIG_USER_ONLY */ 771 772 #ifdef TARGET_TAGGED_ADDRESSES 773 /* Linux syscall tagged address support */ 774 bool tagged_addr_enable; 775 #endif 776 } CPUARMState; 777 778 static inline void set_feature(CPUARMState *env, int feature) 779 { 780 env->features |= 1ULL << feature; 781 } 782 783 static inline void unset_feature(CPUARMState *env, int feature) 784 { 785 env->features &= ~(1ULL << feature); 786 } 787 788 /** 789 * ARMELChangeHookFn: 790 * type of a function which can be registered via arm_register_el_change_hook() 791 * to get callbacks when the CPU changes its exception level or mode. 792 */ 793 typedef void ARMELChangeHookFn(ARMCPU *cpu, void *opaque); 794 typedef struct ARMELChangeHook ARMELChangeHook; 795 struct ARMELChangeHook { 796 ARMELChangeHookFn *hook; 797 void *opaque; 798 QLIST_ENTRY(ARMELChangeHook) node; 799 }; 800 801 /* These values map onto the return values for 802 * QEMU_PSCI_0_2_FN_AFFINITY_INFO */ 803 typedef enum ARMPSCIState { 804 PSCI_ON = 0, 805 PSCI_OFF = 1, 806 PSCI_ON_PENDING = 2 807 } ARMPSCIState; 808 809 typedef struct ARMISARegisters ARMISARegisters; 810 811 /* 812 * In map, each set bit is a supported vector length of (bit-number + 1) * 16 813 * bytes, i.e. each bit number + 1 is the vector length in quadwords. 814 * 815 * While processing properties during initialization, corresponding init bits 816 * are set for bits in sve_vq_map that have been set by properties. 817 * 818 * Bits set in supported represent valid vector lengths for the CPU type. 819 */ 820 typedef struct { 821 uint32_t map, init, supported; 822 } ARMVQMap; 823 824 /** 825 * ARMCPU: 826 * @env: #CPUARMState 827 * 828 * An ARM CPU core. 829 */ 830 struct ArchCPU { 831 CPUState parent_obj; 832 833 CPUARMState env; 834 835 /* Coprocessor information */ 836 GHashTable *cp_regs; 837 /* For marshalling (mostly coprocessor) register state between the 838 * kernel and QEMU (for KVM) and between two QEMUs (for migration), 839 * we use these arrays. 840 */ 841 /* List of register indexes managed via these arrays; (full KVM style 842 * 64 bit indexes, not CPRegInfo 32 bit indexes) 843 */ 844 uint64_t *cpreg_indexes; 845 /* Values of the registers (cpreg_indexes[i]'s value is cpreg_values[i]) */ 846 uint64_t *cpreg_values; 847 /* Length of the indexes, values, reset_values arrays */ 848 int32_t cpreg_array_len; 849 /* These are used only for migration: incoming data arrives in 850 * these fields and is sanity checked in post_load before copying 851 * to the working data structures above. 852 */ 853 uint64_t *cpreg_vmstate_indexes; 854 uint64_t *cpreg_vmstate_values; 855 int32_t cpreg_vmstate_array_len; 856 857 DynamicGDBFeatureInfo dyn_sysreg_feature; 858 DynamicGDBFeatureInfo dyn_svereg_feature; 859 DynamicGDBFeatureInfo dyn_m_systemreg_feature; 860 DynamicGDBFeatureInfo dyn_m_secextreg_feature; 861 862 /* Timers used by the generic (architected) timer */ 863 QEMUTimer *gt_timer[NUM_GTIMERS]; 864 /* 865 * Timer used by the PMU. Its state is restored after migration by 866 * pmu_op_finish() - it does not need other handling during migration 867 */ 868 QEMUTimer *pmu_timer; 869 /* Timer used for WFxT timeouts */ 870 QEMUTimer *wfxt_timer; 871 872 /* GPIO outputs for generic timer */ 873 qemu_irq gt_timer_outputs[NUM_GTIMERS]; 874 /* GPIO output for GICv3 maintenance interrupt signal */ 875 qemu_irq gicv3_maintenance_interrupt; 876 /* GPIO output for the PMU interrupt */ 877 qemu_irq pmu_interrupt; 878 879 /* MemoryRegion to use for secure physical accesses */ 880 MemoryRegion *secure_memory; 881 882 /* MemoryRegion to use for allocation tag accesses */ 883 MemoryRegion *tag_memory; 884 MemoryRegion *secure_tag_memory; 885 886 /* For v8M, pointer to the IDAU interface provided by board/SoC */ 887 Object *idau; 888 889 /* 'compatible' string for this CPU for Linux device trees */ 890 const char *dtb_compatible; 891 892 /* PSCI version for this CPU 893 * Bits[31:16] = Major Version 894 * Bits[15:0] = Minor Version 895 */ 896 uint32_t psci_version; 897 898 /* Current power state, access guarded by BQL */ 899 ARMPSCIState power_state; 900 901 /* CPU has virtualization extension */ 902 bool has_el2; 903 /* CPU has security extension */ 904 bool has_el3; 905 /* CPU has PMU (Performance Monitor Unit) */ 906 bool has_pmu; 907 /* CPU has VFP */ 908 bool has_vfp; 909 /* CPU has 32 VFP registers */ 910 bool has_vfp_d32; 911 /* CPU has Neon */ 912 bool has_neon; 913 /* CPU has M-profile DSP extension */ 914 bool has_dsp; 915 916 /* CPU has memory protection unit */ 917 bool has_mpu; 918 /* PMSAv7 MPU number of supported regions */ 919 uint32_t pmsav7_dregion; 920 /* PMSAv8 MPU number of supported hyp regions */ 921 uint32_t pmsav8r_hdregion; 922 /* v8M SAU number of supported regions */ 923 uint32_t sau_sregion; 924 925 /* PSCI conduit used to invoke PSCI methods 926 * 0 - disabled, 1 - smc, 2 - hvc 927 */ 928 uint32_t psci_conduit; 929 930 /* For v8M, initial value of the Secure VTOR */ 931 uint32_t init_svtor; 932 /* For v8M, initial value of the Non-secure VTOR */ 933 uint32_t init_nsvtor; 934 935 /* [QEMU_]KVM_ARM_TARGET_* constant for this CPU, or 936 * QEMU_KVM_ARM_TARGET_NONE if the kernel doesn't support this CPU type. 937 */ 938 uint32_t kvm_target; 939 940 #ifdef CONFIG_KVM 941 /* KVM init features for this CPU */ 942 uint32_t kvm_init_features[7]; 943 944 /* KVM CPU state */ 945 946 /* KVM virtual time adjustment */ 947 bool kvm_adjvtime; 948 bool kvm_vtime_dirty; 949 uint64_t kvm_vtime; 950 951 /* KVM steal time */ 952 OnOffAuto kvm_steal_time; 953 #endif /* CONFIG_KVM */ 954 955 /* Uniprocessor system with MP extensions */ 956 bool mp_is_up; 957 958 /* True if we tried kvm_arm_host_cpu_features() during CPU instance_init 959 * and the probe failed (so we need to report the error in realize) 960 */ 961 bool host_cpu_probe_failed; 962 963 /* QOM property to indicate we should use the back-compat CNTFRQ default */ 964 bool backcompat_cntfrq; 965 966 /* Specify the number of cores in this CPU cluster. Used for the L2CTLR 967 * register. 968 */ 969 int32_t core_count; 970 971 /* The instance init functions for implementation-specific subclasses 972 * set these fields to specify the implementation-dependent values of 973 * various constant registers and reset values of non-constant 974 * registers. 975 * Some of these might become QOM properties eventually. 976 * Field names match the official register names as defined in the 977 * ARMv7AR ARM Architecture Reference Manual. A reset_ prefix 978 * is used for reset values of non-constant registers; no reset_ 979 * prefix means a constant register. 980 * Some of these registers are split out into a substructure that 981 * is shared with the translators to control the ISA. 982 * 983 * Note that if you add an ID register to the ARMISARegisters struct 984 * you need to also update the 32-bit and 64-bit versions of the 985 * kvm_arm_get_host_cpu_features() function to correctly populate the 986 * field by reading the value from the KVM vCPU. 987 */ 988 struct ARMISARegisters { 989 uint32_t id_isar0; 990 uint32_t id_isar1; 991 uint32_t id_isar2; 992 uint32_t id_isar3; 993 uint32_t id_isar4; 994 uint32_t id_isar5; 995 uint32_t id_isar6; 996 uint32_t id_mmfr0; 997 uint32_t id_mmfr1; 998 uint32_t id_mmfr2; 999 uint32_t id_mmfr3; 1000 uint32_t id_mmfr4; 1001 uint32_t id_mmfr5; 1002 uint32_t id_pfr0; 1003 uint32_t id_pfr1; 1004 uint32_t id_pfr2; 1005 uint32_t mvfr0; 1006 uint32_t mvfr1; 1007 uint32_t mvfr2; 1008 uint32_t id_dfr0; 1009 uint32_t id_dfr1; 1010 uint32_t dbgdidr; 1011 uint32_t dbgdevid; 1012 uint32_t dbgdevid1; 1013 uint64_t id_aa64isar0; 1014 uint64_t id_aa64isar1; 1015 uint64_t id_aa64isar2; 1016 uint64_t id_aa64pfr0; 1017 uint64_t id_aa64pfr1; 1018 uint64_t id_aa64mmfr0; 1019 uint64_t id_aa64mmfr1; 1020 uint64_t id_aa64mmfr2; 1021 uint64_t id_aa64mmfr3; 1022 uint64_t id_aa64dfr0; 1023 uint64_t id_aa64dfr1; 1024 uint64_t id_aa64zfr0; 1025 uint64_t id_aa64smfr0; 1026 uint64_t reset_pmcr_el0; 1027 } isar; 1028 uint64_t midr; 1029 uint32_t revidr; 1030 uint32_t reset_fpsid; 1031 uint64_t ctr; 1032 uint32_t reset_sctlr; 1033 uint64_t pmceid0; 1034 uint64_t pmceid1; 1035 uint32_t id_afr0; 1036 uint64_t id_aa64afr0; 1037 uint64_t id_aa64afr1; 1038 uint64_t clidr; 1039 uint64_t mp_affinity; /* MP ID without feature bits */ 1040 /* The elements of this array are the CCSIDR values for each cache, 1041 * in the order L1DCache, L1ICache, L2DCache, L2ICache, etc. 1042 */ 1043 uint64_t ccsidr[16]; 1044 uint64_t reset_cbar; 1045 uint32_t reset_auxcr; 1046 bool reset_hivecs; 1047 uint8_t reset_l0gptsz; 1048 1049 /* 1050 * Intermediate values used during property parsing. 1051 * Once finalized, the values should be read from ID_AA64*. 1052 */ 1053 bool prop_pauth; 1054 bool prop_pauth_impdef; 1055 bool prop_pauth_qarma3; 1056 bool prop_lpa2; 1057 1058 /* DCZ blocksize, in log_2(words), ie low 4 bits of DCZID_EL0 */ 1059 uint8_t dcz_blocksize; 1060 /* GM blocksize, in log_2(words), ie low 4 bits of GMID_EL0 */ 1061 uint8_t gm_blocksize; 1062 1063 uint64_t rvbar_prop; /* Property/input signals. */ 1064 1065 /* Configurable aspects of GIC cpu interface (which is part of the CPU) */ 1066 int gic_num_lrs; /* number of list registers */ 1067 int gic_vpribits; /* number of virtual priority bits */ 1068 int gic_vprebits; /* number of virtual preemption bits */ 1069 int gic_pribits; /* number of physical priority bits */ 1070 1071 /* Whether the cfgend input is high (i.e. this CPU should reset into 1072 * big-endian mode). This setting isn't used directly: instead it modifies 1073 * the reset_sctlr value to have SCTLR_B or SCTLR_EE set, depending on the 1074 * architecture version. 1075 */ 1076 bool cfgend; 1077 1078 QLIST_HEAD(, ARMELChangeHook) pre_el_change_hooks; 1079 QLIST_HEAD(, ARMELChangeHook) el_change_hooks; 1080 1081 int32_t node_id; /* NUMA node this CPU belongs to */ 1082 1083 /* Used to synchronize KVM and QEMU in-kernel device levels */ 1084 uint8_t device_irq_level; 1085 1086 /* Used to set the maximum vector length the cpu will support. */ 1087 uint32_t sve_max_vq; 1088 1089 #ifdef CONFIG_USER_ONLY 1090 /* Used to set the default vector length at process start. */ 1091 uint32_t sve_default_vq; 1092 uint32_t sme_default_vq; 1093 #endif 1094 1095 ARMVQMap sve_vq; 1096 ARMVQMap sme_vq; 1097 1098 /* Generic timer counter frequency, in Hz */ 1099 uint64_t gt_cntfrq_hz; 1100 }; 1101 1102 typedef struct ARMCPUInfo { 1103 const char *name; 1104 void (*initfn)(Object *obj); 1105 void (*class_init)(ObjectClass *oc, void *data); 1106 } ARMCPUInfo; 1107 1108 /** 1109 * ARMCPUClass: 1110 * @parent_realize: The parent class' realize handler. 1111 * @parent_phases: The parent class' reset phase handlers. 1112 * 1113 * An ARM CPU model. 1114 */ 1115 struct ARMCPUClass { 1116 CPUClass parent_class; 1117 1118 const ARMCPUInfo *info; 1119 DeviceRealize parent_realize; 1120 ResettablePhases parent_phases; 1121 }; 1122 1123 struct AArch64CPUClass { 1124 ARMCPUClass parent_class; 1125 }; 1126 1127 /* Callback functions for the generic timer's timers. */ 1128 void arm_gt_ptimer_cb(void *opaque); 1129 void arm_gt_vtimer_cb(void *opaque); 1130 void arm_gt_htimer_cb(void *opaque); 1131 void arm_gt_stimer_cb(void *opaque); 1132 void arm_gt_hvtimer_cb(void *opaque); 1133 1134 unsigned int gt_cntfrq_period_ns(ARMCPU *cpu); 1135 void gt_rme_post_el_change(ARMCPU *cpu, void *opaque); 1136 1137 void arm_cpu_post_init(Object *obj); 1138 1139 #define ARM_AFF0_SHIFT 0 1140 #define ARM_AFF0_MASK (0xFFULL << ARM_AFF0_SHIFT) 1141 #define ARM_AFF1_SHIFT 8 1142 #define ARM_AFF1_MASK (0xFFULL << ARM_AFF1_SHIFT) 1143 #define ARM_AFF2_SHIFT 16 1144 #define ARM_AFF2_MASK (0xFFULL << ARM_AFF2_SHIFT) 1145 #define ARM_AFF3_SHIFT 32 1146 #define ARM_AFF3_MASK (0xFFULL << ARM_AFF3_SHIFT) 1147 #define ARM_DEFAULT_CPUS_PER_CLUSTER 8 1148 1149 #define ARM32_AFFINITY_MASK (ARM_AFF0_MASK | ARM_AFF1_MASK | ARM_AFF2_MASK) 1150 #define ARM64_AFFINITY_MASK \ 1151 (ARM_AFF0_MASK | ARM_AFF1_MASK | ARM_AFF2_MASK | ARM_AFF3_MASK) 1152 #define ARM64_AFFINITY_INVALID (~ARM64_AFFINITY_MASK) 1153 1154 uint64_t arm_build_mp_affinity(int idx, uint8_t clustersz); 1155 1156 #ifndef CONFIG_USER_ONLY 1157 extern const VMStateDescription vmstate_arm_cpu; 1158 1159 void arm_cpu_do_interrupt(CPUState *cpu); 1160 void arm_v7m_cpu_do_interrupt(CPUState *cpu); 1161 1162 hwaddr arm_cpu_get_phys_page_attrs_debug(CPUState *cpu, vaddr addr, 1163 MemTxAttrs *attrs); 1164 #endif /* !CONFIG_USER_ONLY */ 1165 1166 int arm_cpu_gdb_read_register(CPUState *cpu, GByteArray *buf, int reg); 1167 int arm_cpu_gdb_write_register(CPUState *cpu, uint8_t *buf, int reg); 1168 1169 int arm_cpu_write_elf64_note(WriteCoreDumpFunction f, CPUState *cs, 1170 int cpuid, DumpState *s); 1171 int arm_cpu_write_elf32_note(WriteCoreDumpFunction f, CPUState *cs, 1172 int cpuid, DumpState *s); 1173 1174 /** 1175 * arm_emulate_firmware_reset: Emulate firmware CPU reset handling 1176 * @cpu: CPU (which must have been freshly reset) 1177 * @target_el: exception level to put the CPU into 1178 * @secure: whether to put the CPU in secure state 1179 * 1180 * When QEMU is directly running a guest kernel at a lower level than 1181 * EL3 it implicitly emulates some aspects of the guest firmware. 1182 * This includes that on reset we need to configure the parts of the 1183 * CPU corresponding to EL3 so that the real guest code can run at its 1184 * lower exception level. This function does that post-reset CPU setup, 1185 * for when we do direct boot of a guest kernel, and for when we 1186 * emulate PSCI and similar firmware interfaces starting a CPU at a 1187 * lower exception level. 1188 * 1189 * @target_el must be an EL implemented by the CPU between 1 and 3. 1190 * We do not support dropping into a Secure EL other than 3. 1191 * 1192 * It is the responsibility of the caller to call arm_rebuild_hflags(). 1193 */ 1194 void arm_emulate_firmware_reset(CPUState *cpustate, int target_el); 1195 1196 #ifdef TARGET_AARCH64 1197 int aarch64_cpu_gdb_read_register(CPUState *cpu, GByteArray *buf, int reg); 1198 int aarch64_cpu_gdb_write_register(CPUState *cpu, uint8_t *buf, int reg); 1199 void aarch64_sve_narrow_vq(CPUARMState *env, unsigned vq); 1200 void aarch64_sve_change_el(CPUARMState *env, int old_el, 1201 int new_el, bool el0_a64); 1202 void aarch64_set_svcr(CPUARMState *env, uint64_t new, uint64_t mask); 1203 1204 /* 1205 * SVE registers are encoded in KVM's memory in an endianness-invariant format. 1206 * The byte at offset i from the start of the in-memory representation contains 1207 * the bits [(7 + 8 * i) : (8 * i)] of the register value. As this means the 1208 * lowest offsets are stored in the lowest memory addresses, then that nearly 1209 * matches QEMU's representation, which is to use an array of host-endian 1210 * uint64_t's, where the lower offsets are at the lower indices. To complete 1211 * the translation we just need to byte swap the uint64_t's on big-endian hosts. 1212 */ 1213 static inline uint64_t *sve_bswap64(uint64_t *dst, uint64_t *src, int nr) 1214 { 1215 #if HOST_BIG_ENDIAN 1216 int i; 1217 1218 for (i = 0; i < nr; ++i) { 1219 dst[i] = bswap64(src[i]); 1220 } 1221 1222 return dst; 1223 #else 1224 return src; 1225 #endif 1226 } 1227 1228 #else 1229 static inline void aarch64_sve_narrow_vq(CPUARMState *env, unsigned vq) { } 1230 static inline void aarch64_sve_change_el(CPUARMState *env, int o, 1231 int n, bool a) 1232 { } 1233 #endif 1234 1235 void aarch64_sync_32_to_64(CPUARMState *env); 1236 void aarch64_sync_64_to_32(CPUARMState *env); 1237 1238 int fp_exception_el(CPUARMState *env, int cur_el); 1239 int sve_exception_el(CPUARMState *env, int cur_el); 1240 int sme_exception_el(CPUARMState *env, int cur_el); 1241 1242 /** 1243 * sve_vqm1_for_el_sm: 1244 * @env: CPUARMState 1245 * @el: exception level 1246 * @sm: streaming mode 1247 * 1248 * Compute the current vector length for @el & @sm, in units of 1249 * Quadwords Minus 1 -- the same scale used for ZCR_ELx.LEN. 1250 * If @sm, compute for SVL, otherwise NVL. 1251 */ 1252 uint32_t sve_vqm1_for_el_sm(CPUARMState *env, int el, bool sm); 1253 1254 /* Likewise, but using @sm = PSTATE.SM. */ 1255 uint32_t sve_vqm1_for_el(CPUARMState *env, int el); 1256 1257 static inline bool is_a64(CPUARMState *env) 1258 { 1259 return env->aarch64; 1260 } 1261 1262 /** 1263 * pmu_op_start/finish 1264 * @env: CPUARMState 1265 * 1266 * Convert all PMU counters between their delta form (the typical mode when 1267 * they are enabled) and the guest-visible values. These two calls must 1268 * surround any action which might affect the counters. 1269 */ 1270 void pmu_op_start(CPUARMState *env); 1271 void pmu_op_finish(CPUARMState *env); 1272 1273 /* 1274 * Called when a PMU counter is due to overflow 1275 */ 1276 void arm_pmu_timer_cb(void *opaque); 1277 1278 /** 1279 * Functions to register as EL change hooks for PMU mode filtering 1280 */ 1281 void pmu_pre_el_change(ARMCPU *cpu, void *ignored); 1282 void pmu_post_el_change(ARMCPU *cpu, void *ignored); 1283 1284 /* 1285 * pmu_init 1286 * @cpu: ARMCPU 1287 * 1288 * Initialize the CPU's PMCEID[01]_EL0 registers and associated internal state 1289 * for the current configuration 1290 */ 1291 void pmu_init(ARMCPU *cpu); 1292 1293 /* SCTLR bit meanings. Several bits have been reused in newer 1294 * versions of the architecture; in that case we define constants 1295 * for both old and new bit meanings. Code which tests against those 1296 * bits should probably check or otherwise arrange that the CPU 1297 * is the architectural version it expects. 1298 */ 1299 #define SCTLR_M (1U << 0) 1300 #define SCTLR_A (1U << 1) 1301 #define SCTLR_C (1U << 2) 1302 #define SCTLR_W (1U << 3) /* up to v6; RAO in v7 */ 1303 #define SCTLR_nTLSMD_32 (1U << 3) /* v8.2-LSMAOC, AArch32 only */ 1304 #define SCTLR_SA (1U << 3) /* AArch64 only */ 1305 #define SCTLR_P (1U << 4) /* up to v5; RAO in v6 and v7 */ 1306 #define SCTLR_LSMAOE_32 (1U << 4) /* v8.2-LSMAOC, AArch32 only */ 1307 #define SCTLR_SA0 (1U << 4) /* v8 onward, AArch64 only */ 1308 #define SCTLR_D (1U << 5) /* up to v5; RAO in v6 */ 1309 #define SCTLR_CP15BEN (1U << 5) /* v7 onward */ 1310 #define SCTLR_L (1U << 6) /* up to v5; RAO in v6 and v7; RAZ in v8 */ 1311 #define SCTLR_nAA (1U << 6) /* when FEAT_LSE2 is implemented */ 1312 #define SCTLR_B (1U << 7) /* up to v6; RAZ in v7 */ 1313 #define SCTLR_ITD (1U << 7) /* v8 onward */ 1314 #define SCTLR_S (1U << 8) /* up to v6; RAZ in v7 */ 1315 #define SCTLR_SED (1U << 8) /* v8 onward */ 1316 #define SCTLR_R (1U << 9) /* up to v6; RAZ in v7 */ 1317 #define SCTLR_UMA (1U << 9) /* v8 onward, AArch64 only */ 1318 #define SCTLR_F (1U << 10) /* up to v6 */ 1319 #define SCTLR_SW (1U << 10) /* v7 */ 1320 #define SCTLR_EnRCTX (1U << 10) /* in v8.0-PredInv */ 1321 #define SCTLR_Z (1U << 11) /* in v7, RES1 in v8 */ 1322 #define SCTLR_EOS (1U << 11) /* v8.5-ExS */ 1323 #define SCTLR_I (1U << 12) 1324 #define SCTLR_V (1U << 13) /* AArch32 only */ 1325 #define SCTLR_EnDB (1U << 13) /* v8.3, AArch64 only */ 1326 #define SCTLR_RR (1U << 14) /* up to v7 */ 1327 #define SCTLR_DZE (1U << 14) /* v8 onward, AArch64 only */ 1328 #define SCTLR_L4 (1U << 15) /* up to v6; RAZ in v7 */ 1329 #define SCTLR_UCT (1U << 15) /* v8 onward, AArch64 only */ 1330 #define SCTLR_DT (1U << 16) /* up to ??, RAO in v6 and v7 */ 1331 #define SCTLR_nTWI (1U << 16) /* v8 onward */ 1332 #define SCTLR_HA (1U << 17) /* up to v7, RES0 in v8 */ 1333 #define SCTLR_BR (1U << 17) /* PMSA only */ 1334 #define SCTLR_IT (1U << 18) /* up to ??, RAO in v6 and v7 */ 1335 #define SCTLR_nTWE (1U << 18) /* v8 onward */ 1336 #define SCTLR_WXN (1U << 19) 1337 #define SCTLR_ST (1U << 20) /* up to ??, RAZ in v6 */ 1338 #define SCTLR_UWXN (1U << 20) /* v7 onward, AArch32 only */ 1339 #define SCTLR_TSCXT (1U << 20) /* FEAT_CSV2_1p2, AArch64 only */ 1340 #define SCTLR_FI (1U << 21) /* up to v7, v8 RES0 */ 1341 #define SCTLR_IESB (1U << 21) /* v8.2-IESB, AArch64 only */ 1342 #define SCTLR_U (1U << 22) /* up to v6, RAO in v7 */ 1343 #define SCTLR_EIS (1U << 22) /* v8.5-ExS */ 1344 #define SCTLR_XP (1U << 23) /* up to v6; v7 onward RAO */ 1345 #define SCTLR_SPAN (1U << 23) /* v8.1-PAN */ 1346 #define SCTLR_VE (1U << 24) /* up to v7 */ 1347 #define SCTLR_E0E (1U << 24) /* v8 onward, AArch64 only */ 1348 #define SCTLR_EE (1U << 25) 1349 #define SCTLR_L2 (1U << 26) /* up to v6, RAZ in v7 */ 1350 #define SCTLR_UCI (1U << 26) /* v8 onward, AArch64 only */ 1351 #define SCTLR_NMFI (1U << 27) /* up to v7, RAZ in v7VE and v8 */ 1352 #define SCTLR_EnDA (1U << 27) /* v8.3, AArch64 only */ 1353 #define SCTLR_TRE (1U << 28) /* AArch32 only */ 1354 #define SCTLR_nTLSMD_64 (1U << 28) /* v8.2-LSMAOC, AArch64 only */ 1355 #define SCTLR_AFE (1U << 29) /* AArch32 only */ 1356 #define SCTLR_LSMAOE_64 (1U << 29) /* v8.2-LSMAOC, AArch64 only */ 1357 #define SCTLR_TE (1U << 30) /* AArch32 only */ 1358 #define SCTLR_EnIB (1U << 30) /* v8.3, AArch64 only */ 1359 #define SCTLR_EnIA (1U << 31) /* v8.3, AArch64 only */ 1360 #define SCTLR_DSSBS_32 (1U << 31) /* v8.5, AArch32 only */ 1361 #define SCTLR_MSCEN (1ULL << 33) /* FEAT_MOPS */ 1362 #define SCTLR_BT0 (1ULL << 35) /* v8.5-BTI */ 1363 #define SCTLR_BT1 (1ULL << 36) /* v8.5-BTI */ 1364 #define SCTLR_ITFSB (1ULL << 37) /* v8.5-MemTag */ 1365 #define SCTLR_TCF0 (3ULL << 38) /* v8.5-MemTag */ 1366 #define SCTLR_TCF (3ULL << 40) /* v8.5-MemTag */ 1367 #define SCTLR_ATA0 (1ULL << 42) /* v8.5-MemTag */ 1368 #define SCTLR_ATA (1ULL << 43) /* v8.5-MemTag */ 1369 #define SCTLR_DSSBS_64 (1ULL << 44) /* v8.5, AArch64 only */ 1370 #define SCTLR_TWEDEn (1ULL << 45) /* FEAT_TWED */ 1371 #define SCTLR_TWEDEL MAKE_64_MASK(46, 4) /* FEAT_TWED */ 1372 #define SCTLR_TMT0 (1ULL << 50) /* FEAT_TME */ 1373 #define SCTLR_TMT (1ULL << 51) /* FEAT_TME */ 1374 #define SCTLR_TME0 (1ULL << 52) /* FEAT_TME */ 1375 #define SCTLR_TME (1ULL << 53) /* FEAT_TME */ 1376 #define SCTLR_EnASR (1ULL << 54) /* FEAT_LS64_V */ 1377 #define SCTLR_EnAS0 (1ULL << 55) /* FEAT_LS64_ACCDATA */ 1378 #define SCTLR_EnALS (1ULL << 56) /* FEAT_LS64 */ 1379 #define SCTLR_EPAN (1ULL << 57) /* FEAT_PAN3 */ 1380 #define SCTLR_EnTP2 (1ULL << 60) /* FEAT_SME */ 1381 #define SCTLR_NMI (1ULL << 61) /* FEAT_NMI */ 1382 #define SCTLR_SPINTMASK (1ULL << 62) /* FEAT_NMI */ 1383 #define SCTLR_TIDCP (1ULL << 63) /* FEAT_TIDCP1 */ 1384 1385 #define CPSR_M (0x1fU) 1386 #define CPSR_T (1U << 5) 1387 #define CPSR_F (1U << 6) 1388 #define CPSR_I (1U << 7) 1389 #define CPSR_A (1U << 8) 1390 #define CPSR_E (1U << 9) 1391 #define CPSR_IT_2_7 (0xfc00U) 1392 #define CPSR_GE (0xfU << 16) 1393 #define CPSR_IL (1U << 20) 1394 #define CPSR_DIT (1U << 21) 1395 #define CPSR_PAN (1U << 22) 1396 #define CPSR_SSBS (1U << 23) 1397 #define CPSR_J (1U << 24) 1398 #define CPSR_IT_0_1 (3U << 25) 1399 #define CPSR_Q (1U << 27) 1400 #define CPSR_V (1U << 28) 1401 #define CPSR_C (1U << 29) 1402 #define CPSR_Z (1U << 30) 1403 #define CPSR_N (1U << 31) 1404 #define CPSR_NZCV (CPSR_N | CPSR_Z | CPSR_C | CPSR_V) 1405 #define CPSR_AIF (CPSR_A | CPSR_I | CPSR_F) 1406 #define ISR_FS (1U << 9) 1407 #define ISR_IS (1U << 10) 1408 1409 #define CPSR_IT (CPSR_IT_0_1 | CPSR_IT_2_7) 1410 #define CACHED_CPSR_BITS (CPSR_T | CPSR_AIF | CPSR_GE | CPSR_IT | CPSR_Q \ 1411 | CPSR_NZCV) 1412 /* Bits writable in user mode. */ 1413 #define CPSR_USER (CPSR_NZCV | CPSR_Q | CPSR_GE | CPSR_E) 1414 /* Execution state bits. MRS read as zero, MSR writes ignored. */ 1415 #define CPSR_EXEC (CPSR_T | CPSR_IT | CPSR_J | CPSR_IL) 1416 1417 /* Bit definitions for M profile XPSR. Most are the same as CPSR. */ 1418 #define XPSR_EXCP 0x1ffU 1419 #define XPSR_SPREALIGN (1U << 9) /* Only set in exception stack frames */ 1420 #define XPSR_IT_2_7 CPSR_IT_2_7 1421 #define XPSR_GE CPSR_GE 1422 #define XPSR_SFPA (1U << 20) /* Only set in exception stack frames */ 1423 #define XPSR_T (1U << 24) /* Not the same as CPSR_T ! */ 1424 #define XPSR_IT_0_1 CPSR_IT_0_1 1425 #define XPSR_Q CPSR_Q 1426 #define XPSR_V CPSR_V 1427 #define XPSR_C CPSR_C 1428 #define XPSR_Z CPSR_Z 1429 #define XPSR_N CPSR_N 1430 #define XPSR_NZCV CPSR_NZCV 1431 #define XPSR_IT CPSR_IT 1432 1433 /* Bit definitions for ARMv8 SPSR (PSTATE) format. 1434 * Only these are valid when in AArch64 mode; in 1435 * AArch32 mode SPSRs are basically CPSR-format. 1436 */ 1437 #define PSTATE_SP (1U) 1438 #define PSTATE_M (0xFU) 1439 #define PSTATE_nRW (1U << 4) 1440 #define PSTATE_F (1U << 6) 1441 #define PSTATE_I (1U << 7) 1442 #define PSTATE_A (1U << 8) 1443 #define PSTATE_D (1U << 9) 1444 #define PSTATE_BTYPE (3U << 10) 1445 #define PSTATE_SSBS (1U << 12) 1446 #define PSTATE_ALLINT (1U << 13) 1447 #define PSTATE_IL (1U << 20) 1448 #define PSTATE_SS (1U << 21) 1449 #define PSTATE_PAN (1U << 22) 1450 #define PSTATE_UAO (1U << 23) 1451 #define PSTATE_DIT (1U << 24) 1452 #define PSTATE_TCO (1U << 25) 1453 #define PSTATE_V (1U << 28) 1454 #define PSTATE_C (1U << 29) 1455 #define PSTATE_Z (1U << 30) 1456 #define PSTATE_N (1U << 31) 1457 #define PSTATE_NZCV (PSTATE_N | PSTATE_Z | PSTATE_C | PSTATE_V) 1458 #define PSTATE_DAIF (PSTATE_D | PSTATE_A | PSTATE_I | PSTATE_F) 1459 #define CACHED_PSTATE_BITS (PSTATE_NZCV | PSTATE_DAIF | PSTATE_BTYPE) 1460 /* Mode values for AArch64 */ 1461 #define PSTATE_MODE_EL3h 13 1462 #define PSTATE_MODE_EL3t 12 1463 #define PSTATE_MODE_EL2h 9 1464 #define PSTATE_MODE_EL2t 8 1465 #define PSTATE_MODE_EL1h 5 1466 #define PSTATE_MODE_EL1t 4 1467 #define PSTATE_MODE_EL0t 0 1468 1469 /* PSTATE bits that are accessed via SVCR and not stored in SPSR_ELx. */ 1470 FIELD(SVCR, SM, 0, 1) 1471 FIELD(SVCR, ZA, 1, 1) 1472 1473 /* Fields for SMCR_ELx. */ 1474 FIELD(SMCR, LEN, 0, 4) 1475 FIELD(SMCR, FA64, 31, 1) 1476 1477 /* Write a new value to v7m.exception, thus transitioning into or out 1478 * of Handler mode; this may result in a change of active stack pointer. 1479 */ 1480 void write_v7m_exception(CPUARMState *env, uint32_t new_exc); 1481 1482 /* Map EL and handler into a PSTATE_MODE. */ 1483 static inline unsigned int aarch64_pstate_mode(unsigned int el, bool handler) 1484 { 1485 return (el << 2) | handler; 1486 } 1487 1488 /* Return the current PSTATE value. For the moment we don't support 32<->64 bit 1489 * interprocessing, so we don't attempt to sync with the cpsr state used by 1490 * the 32 bit decoder. 1491 */ 1492 static inline uint32_t pstate_read(CPUARMState *env) 1493 { 1494 int ZF; 1495 1496 ZF = (env->ZF == 0); 1497 return (env->NF & 0x80000000) | (ZF << 30) 1498 | (env->CF << 29) | ((env->VF & 0x80000000) >> 3) 1499 | env->pstate | env->daif | (env->btype << 10); 1500 } 1501 1502 static inline void pstate_write(CPUARMState *env, uint32_t val) 1503 { 1504 env->ZF = (~val) & PSTATE_Z; 1505 env->NF = val; 1506 env->CF = (val >> 29) & 1; 1507 env->VF = (val << 3) & 0x80000000; 1508 env->daif = val & PSTATE_DAIF; 1509 env->btype = (val >> 10) & 3; 1510 env->pstate = val & ~CACHED_PSTATE_BITS; 1511 } 1512 1513 /* Return the current CPSR value. */ 1514 uint32_t cpsr_read(CPUARMState *env); 1515 1516 typedef enum CPSRWriteType { 1517 CPSRWriteByInstr = 0, /* from guest MSR or CPS */ 1518 CPSRWriteExceptionReturn = 1, /* from guest exception return insn */ 1519 CPSRWriteRaw = 2, 1520 /* trust values, no reg bank switch, no hflags rebuild */ 1521 CPSRWriteByGDBStub = 3, /* from the GDB stub */ 1522 } CPSRWriteType; 1523 1524 /* 1525 * Set the CPSR. Note that some bits of mask must be all-set or all-clear. 1526 * This will do an arm_rebuild_hflags() if any of the bits in @mask 1527 * correspond to TB flags bits cached in the hflags, unless @write_type 1528 * is CPSRWriteRaw. 1529 */ 1530 void cpsr_write(CPUARMState *env, uint32_t val, uint32_t mask, 1531 CPSRWriteType write_type); 1532 1533 /* Return the current xPSR value. */ 1534 static inline uint32_t xpsr_read(CPUARMState *env) 1535 { 1536 int ZF; 1537 ZF = (env->ZF == 0); 1538 return (env->NF & 0x80000000) | (ZF << 30) 1539 | (env->CF << 29) | ((env->VF & 0x80000000) >> 3) | (env->QF << 27) 1540 | (env->thumb << 24) | ((env->condexec_bits & 3) << 25) 1541 | ((env->condexec_bits & 0xfc) << 8) 1542 | (env->GE << 16) 1543 | env->v7m.exception; 1544 } 1545 1546 /* Set the xPSR. Note that some bits of mask must be all-set or all-clear. */ 1547 static inline void xpsr_write(CPUARMState *env, uint32_t val, uint32_t mask) 1548 { 1549 if (mask & XPSR_NZCV) { 1550 env->ZF = (~val) & XPSR_Z; 1551 env->NF = val; 1552 env->CF = (val >> 29) & 1; 1553 env->VF = (val << 3) & 0x80000000; 1554 } 1555 if (mask & XPSR_Q) { 1556 env->QF = ((val & XPSR_Q) != 0); 1557 } 1558 if (mask & XPSR_GE) { 1559 env->GE = (val & XPSR_GE) >> 16; 1560 } 1561 #ifndef CONFIG_USER_ONLY 1562 if (mask & XPSR_T) { 1563 env->thumb = ((val & XPSR_T) != 0); 1564 } 1565 if (mask & XPSR_IT_0_1) { 1566 env->condexec_bits &= ~3; 1567 env->condexec_bits |= (val >> 25) & 3; 1568 } 1569 if (mask & XPSR_IT_2_7) { 1570 env->condexec_bits &= 3; 1571 env->condexec_bits |= (val >> 8) & 0xfc; 1572 } 1573 if (mask & XPSR_EXCP) { 1574 /* Note that this only happens on exception exit */ 1575 write_v7m_exception(env, val & XPSR_EXCP); 1576 } 1577 #endif 1578 } 1579 1580 #define HCR_VM (1ULL << 0) 1581 #define HCR_SWIO (1ULL << 1) 1582 #define HCR_PTW (1ULL << 2) 1583 #define HCR_FMO (1ULL << 3) 1584 #define HCR_IMO (1ULL << 4) 1585 #define HCR_AMO (1ULL << 5) 1586 #define HCR_VF (1ULL << 6) 1587 #define HCR_VI (1ULL << 7) 1588 #define HCR_VSE (1ULL << 8) 1589 #define HCR_FB (1ULL << 9) 1590 #define HCR_BSU_MASK (3ULL << 10) 1591 #define HCR_DC (1ULL << 12) 1592 #define HCR_TWI (1ULL << 13) 1593 #define HCR_TWE (1ULL << 14) 1594 #define HCR_TID0 (1ULL << 15) 1595 #define HCR_TID1 (1ULL << 16) 1596 #define HCR_TID2 (1ULL << 17) 1597 #define HCR_TID3 (1ULL << 18) 1598 #define HCR_TSC (1ULL << 19) 1599 #define HCR_TIDCP (1ULL << 20) 1600 #define HCR_TACR (1ULL << 21) 1601 #define HCR_TSW (1ULL << 22) 1602 #define HCR_TPCP (1ULL << 23) 1603 #define HCR_TPU (1ULL << 24) 1604 #define HCR_TTLB (1ULL << 25) 1605 #define HCR_TVM (1ULL << 26) 1606 #define HCR_TGE (1ULL << 27) 1607 #define HCR_TDZ (1ULL << 28) 1608 #define HCR_HCD (1ULL << 29) 1609 #define HCR_TRVM (1ULL << 30) 1610 #define HCR_RW (1ULL << 31) 1611 #define HCR_CD (1ULL << 32) 1612 #define HCR_ID (1ULL << 33) 1613 #define HCR_E2H (1ULL << 34) 1614 #define HCR_TLOR (1ULL << 35) 1615 #define HCR_TERR (1ULL << 36) 1616 #define HCR_TEA (1ULL << 37) 1617 #define HCR_MIOCNCE (1ULL << 38) 1618 #define HCR_TME (1ULL << 39) 1619 #define HCR_APK (1ULL << 40) 1620 #define HCR_API (1ULL << 41) 1621 #define HCR_NV (1ULL << 42) 1622 #define HCR_NV1 (1ULL << 43) 1623 #define HCR_AT (1ULL << 44) 1624 #define HCR_NV2 (1ULL << 45) 1625 #define HCR_FWB (1ULL << 46) 1626 #define HCR_FIEN (1ULL << 47) 1627 #define HCR_GPF (1ULL << 48) 1628 #define HCR_TID4 (1ULL << 49) 1629 #define HCR_TICAB (1ULL << 50) 1630 #define HCR_AMVOFFEN (1ULL << 51) 1631 #define HCR_TOCU (1ULL << 52) 1632 #define HCR_ENSCXT (1ULL << 53) 1633 #define HCR_TTLBIS (1ULL << 54) 1634 #define HCR_TTLBOS (1ULL << 55) 1635 #define HCR_ATA (1ULL << 56) 1636 #define HCR_DCT (1ULL << 57) 1637 #define HCR_TID5 (1ULL << 58) 1638 #define HCR_TWEDEN (1ULL << 59) 1639 #define HCR_TWEDEL MAKE_64BIT_MASK(60, 4) 1640 1641 #define SCR_NS (1ULL << 0) 1642 #define SCR_IRQ (1ULL << 1) 1643 #define SCR_FIQ (1ULL << 2) 1644 #define SCR_EA (1ULL << 3) 1645 #define SCR_FW (1ULL << 4) 1646 #define SCR_AW (1ULL << 5) 1647 #define SCR_NET (1ULL << 6) 1648 #define SCR_SMD (1ULL << 7) 1649 #define SCR_HCE (1ULL << 8) 1650 #define SCR_SIF (1ULL << 9) 1651 #define SCR_RW (1ULL << 10) 1652 #define SCR_ST (1ULL << 11) 1653 #define SCR_TWI (1ULL << 12) 1654 #define SCR_TWE (1ULL << 13) 1655 #define SCR_TLOR (1ULL << 14) 1656 #define SCR_TERR (1ULL << 15) 1657 #define SCR_APK (1ULL << 16) 1658 #define SCR_API (1ULL << 17) 1659 #define SCR_EEL2 (1ULL << 18) 1660 #define SCR_EASE (1ULL << 19) 1661 #define SCR_NMEA (1ULL << 20) 1662 #define SCR_FIEN (1ULL << 21) 1663 #define SCR_ENSCXT (1ULL << 25) 1664 #define SCR_ATA (1ULL << 26) 1665 #define SCR_FGTEN (1ULL << 27) 1666 #define SCR_ECVEN (1ULL << 28) 1667 #define SCR_TWEDEN (1ULL << 29) 1668 #define SCR_TWEDEL MAKE_64BIT_MASK(30, 4) 1669 #define SCR_TME (1ULL << 34) 1670 #define SCR_AMVOFFEN (1ULL << 35) 1671 #define SCR_ENAS0 (1ULL << 36) 1672 #define SCR_ADEN (1ULL << 37) 1673 #define SCR_HXEN (1ULL << 38) 1674 #define SCR_TRNDR (1ULL << 40) 1675 #define SCR_ENTP2 (1ULL << 41) 1676 #define SCR_GPF (1ULL << 48) 1677 #define SCR_NSE (1ULL << 62) 1678 1679 /* Return the current FPSCR value. */ 1680 uint32_t vfp_get_fpscr(CPUARMState *env); 1681 void vfp_set_fpscr(CPUARMState *env, uint32_t val); 1682 1683 /* FPCR, Floating Point Control Register 1684 * FPSR, Floating Poiht Status Register 1685 * 1686 * For A64 the FPSCR is split into two logically distinct registers, 1687 * FPCR and FPSR. However since they still use non-overlapping bits 1688 * we store the underlying state in fpscr and just mask on read/write. 1689 */ 1690 #define FPSR_MASK 0xf800009f 1691 #define FPCR_MASK 0x07ff9f00 1692 1693 #define FPCR_IOE (1 << 8) /* Invalid Operation exception trap enable */ 1694 #define FPCR_DZE (1 << 9) /* Divide by Zero exception trap enable */ 1695 #define FPCR_OFE (1 << 10) /* Overflow exception trap enable */ 1696 #define FPCR_UFE (1 << 11) /* Underflow exception trap enable */ 1697 #define FPCR_IXE (1 << 12) /* Inexact exception trap enable */ 1698 #define FPCR_IDE (1 << 15) /* Input Denormal exception trap enable */ 1699 #define FPCR_FZ16 (1 << 19) /* ARMv8.2+, FP16 flush-to-zero */ 1700 #define FPCR_RMODE_MASK (3 << 22) /* Rounding mode */ 1701 #define FPCR_FZ (1 << 24) /* Flush-to-zero enable bit */ 1702 #define FPCR_DN (1 << 25) /* Default NaN enable bit */ 1703 #define FPCR_AHP (1 << 26) /* Alternative half-precision */ 1704 #define FPCR_QC (1 << 27) /* Cumulative saturation bit */ 1705 #define FPCR_V (1 << 28) /* FP overflow flag */ 1706 #define FPCR_C (1 << 29) /* FP carry flag */ 1707 #define FPCR_Z (1 << 30) /* FP zero flag */ 1708 #define FPCR_N (1 << 31) /* FP negative flag */ 1709 1710 #define FPCR_LTPSIZE_SHIFT 16 /* LTPSIZE, M-profile only */ 1711 #define FPCR_LTPSIZE_MASK (7 << FPCR_LTPSIZE_SHIFT) 1712 #define FPCR_LTPSIZE_LENGTH 3 1713 1714 #define FPCR_NZCV_MASK (FPCR_N | FPCR_Z | FPCR_C | FPCR_V) 1715 #define FPCR_NZCVQC_MASK (FPCR_NZCV_MASK | FPCR_QC) 1716 1717 static inline uint32_t vfp_get_fpsr(CPUARMState *env) 1718 { 1719 return vfp_get_fpscr(env) & FPSR_MASK; 1720 } 1721 1722 static inline void vfp_set_fpsr(CPUARMState *env, uint32_t val) 1723 { 1724 uint32_t new_fpscr = (vfp_get_fpscr(env) & ~FPSR_MASK) | (val & FPSR_MASK); 1725 vfp_set_fpscr(env, new_fpscr); 1726 } 1727 1728 static inline uint32_t vfp_get_fpcr(CPUARMState *env) 1729 { 1730 return vfp_get_fpscr(env) & FPCR_MASK; 1731 } 1732 1733 static inline void vfp_set_fpcr(CPUARMState *env, uint32_t val) 1734 { 1735 uint32_t new_fpscr = (vfp_get_fpscr(env) & ~FPCR_MASK) | (val & FPCR_MASK); 1736 vfp_set_fpscr(env, new_fpscr); 1737 } 1738 1739 enum arm_cpu_mode { 1740 ARM_CPU_MODE_USR = 0x10, 1741 ARM_CPU_MODE_FIQ = 0x11, 1742 ARM_CPU_MODE_IRQ = 0x12, 1743 ARM_CPU_MODE_SVC = 0x13, 1744 ARM_CPU_MODE_MON = 0x16, 1745 ARM_CPU_MODE_ABT = 0x17, 1746 ARM_CPU_MODE_HYP = 0x1a, 1747 ARM_CPU_MODE_UND = 0x1b, 1748 ARM_CPU_MODE_SYS = 0x1f 1749 }; 1750 1751 /* VFP system registers. */ 1752 #define ARM_VFP_FPSID 0 1753 #define ARM_VFP_FPSCR 1 1754 #define ARM_VFP_MVFR2 5 1755 #define ARM_VFP_MVFR1 6 1756 #define ARM_VFP_MVFR0 7 1757 #define ARM_VFP_FPEXC 8 1758 #define ARM_VFP_FPINST 9 1759 #define ARM_VFP_FPINST2 10 1760 /* These ones are M-profile only */ 1761 #define ARM_VFP_FPSCR_NZCVQC 2 1762 #define ARM_VFP_VPR 12 1763 #define ARM_VFP_P0 13 1764 #define ARM_VFP_FPCXT_NS 14 1765 #define ARM_VFP_FPCXT_S 15 1766 1767 /* QEMU-internal value meaning "FPSCR, but we care only about NZCV" */ 1768 #define QEMU_VFP_FPSCR_NZCV 0xffff 1769 1770 /* iwMMXt coprocessor control registers. */ 1771 #define ARM_IWMMXT_wCID 0 1772 #define ARM_IWMMXT_wCon 1 1773 #define ARM_IWMMXT_wCSSF 2 1774 #define ARM_IWMMXT_wCASF 3 1775 #define ARM_IWMMXT_wCGR0 8 1776 #define ARM_IWMMXT_wCGR1 9 1777 #define ARM_IWMMXT_wCGR2 10 1778 #define ARM_IWMMXT_wCGR3 11 1779 1780 /* V7M CCR bits */ 1781 FIELD(V7M_CCR, NONBASETHRDENA, 0, 1) 1782 FIELD(V7M_CCR, USERSETMPEND, 1, 1) 1783 FIELD(V7M_CCR, UNALIGN_TRP, 3, 1) 1784 FIELD(V7M_CCR, DIV_0_TRP, 4, 1) 1785 FIELD(V7M_CCR, BFHFNMIGN, 8, 1) 1786 FIELD(V7M_CCR, STKALIGN, 9, 1) 1787 FIELD(V7M_CCR, STKOFHFNMIGN, 10, 1) 1788 FIELD(V7M_CCR, DC, 16, 1) 1789 FIELD(V7M_CCR, IC, 17, 1) 1790 FIELD(V7M_CCR, BP, 18, 1) 1791 FIELD(V7M_CCR, LOB, 19, 1) 1792 FIELD(V7M_CCR, TRD, 20, 1) 1793 1794 /* V7M SCR bits */ 1795 FIELD(V7M_SCR, SLEEPONEXIT, 1, 1) 1796 FIELD(V7M_SCR, SLEEPDEEP, 2, 1) 1797 FIELD(V7M_SCR, SLEEPDEEPS, 3, 1) 1798 FIELD(V7M_SCR, SEVONPEND, 4, 1) 1799 1800 /* V7M AIRCR bits */ 1801 FIELD(V7M_AIRCR, VECTRESET, 0, 1) 1802 FIELD(V7M_AIRCR, VECTCLRACTIVE, 1, 1) 1803 FIELD(V7M_AIRCR, SYSRESETREQ, 2, 1) 1804 FIELD(V7M_AIRCR, SYSRESETREQS, 3, 1) 1805 FIELD(V7M_AIRCR, PRIGROUP, 8, 3) 1806 FIELD(V7M_AIRCR, BFHFNMINS, 13, 1) 1807 FIELD(V7M_AIRCR, PRIS, 14, 1) 1808 FIELD(V7M_AIRCR, ENDIANNESS, 15, 1) 1809 FIELD(V7M_AIRCR, VECTKEY, 16, 16) 1810 1811 /* V7M CFSR bits for MMFSR */ 1812 FIELD(V7M_CFSR, IACCVIOL, 0, 1) 1813 FIELD(V7M_CFSR, DACCVIOL, 1, 1) 1814 FIELD(V7M_CFSR, MUNSTKERR, 3, 1) 1815 FIELD(V7M_CFSR, MSTKERR, 4, 1) 1816 FIELD(V7M_CFSR, MLSPERR, 5, 1) 1817 FIELD(V7M_CFSR, MMARVALID, 7, 1) 1818 1819 /* V7M CFSR bits for BFSR */ 1820 FIELD(V7M_CFSR, IBUSERR, 8 + 0, 1) 1821 FIELD(V7M_CFSR, PRECISERR, 8 + 1, 1) 1822 FIELD(V7M_CFSR, IMPRECISERR, 8 + 2, 1) 1823 FIELD(V7M_CFSR, UNSTKERR, 8 + 3, 1) 1824 FIELD(V7M_CFSR, STKERR, 8 + 4, 1) 1825 FIELD(V7M_CFSR, LSPERR, 8 + 5, 1) 1826 FIELD(V7M_CFSR, BFARVALID, 8 + 7, 1) 1827 1828 /* V7M CFSR bits for UFSR */ 1829 FIELD(V7M_CFSR, UNDEFINSTR, 16 + 0, 1) 1830 FIELD(V7M_CFSR, INVSTATE, 16 + 1, 1) 1831 FIELD(V7M_CFSR, INVPC, 16 + 2, 1) 1832 FIELD(V7M_CFSR, NOCP, 16 + 3, 1) 1833 FIELD(V7M_CFSR, STKOF, 16 + 4, 1) 1834 FIELD(V7M_CFSR, UNALIGNED, 16 + 8, 1) 1835 FIELD(V7M_CFSR, DIVBYZERO, 16 + 9, 1) 1836 1837 /* V7M CFSR bit masks covering all of the subregister bits */ 1838 FIELD(V7M_CFSR, MMFSR, 0, 8) 1839 FIELD(V7M_CFSR, BFSR, 8, 8) 1840 FIELD(V7M_CFSR, UFSR, 16, 16) 1841 1842 /* V7M HFSR bits */ 1843 FIELD(V7M_HFSR, VECTTBL, 1, 1) 1844 FIELD(V7M_HFSR, FORCED, 30, 1) 1845 FIELD(V7M_HFSR, DEBUGEVT, 31, 1) 1846 1847 /* V7M DFSR bits */ 1848 FIELD(V7M_DFSR, HALTED, 0, 1) 1849 FIELD(V7M_DFSR, BKPT, 1, 1) 1850 FIELD(V7M_DFSR, DWTTRAP, 2, 1) 1851 FIELD(V7M_DFSR, VCATCH, 3, 1) 1852 FIELD(V7M_DFSR, EXTERNAL, 4, 1) 1853 1854 /* V7M SFSR bits */ 1855 FIELD(V7M_SFSR, INVEP, 0, 1) 1856 FIELD(V7M_SFSR, INVIS, 1, 1) 1857 FIELD(V7M_SFSR, INVER, 2, 1) 1858 FIELD(V7M_SFSR, AUVIOL, 3, 1) 1859 FIELD(V7M_SFSR, INVTRAN, 4, 1) 1860 FIELD(V7M_SFSR, LSPERR, 5, 1) 1861 FIELD(V7M_SFSR, SFARVALID, 6, 1) 1862 FIELD(V7M_SFSR, LSERR, 7, 1) 1863 1864 /* v7M MPU_CTRL bits */ 1865 FIELD(V7M_MPU_CTRL, ENABLE, 0, 1) 1866 FIELD(V7M_MPU_CTRL, HFNMIENA, 1, 1) 1867 FIELD(V7M_MPU_CTRL, PRIVDEFENA, 2, 1) 1868 1869 /* v7M CLIDR bits */ 1870 FIELD(V7M_CLIDR, CTYPE_ALL, 0, 21) 1871 FIELD(V7M_CLIDR, LOUIS, 21, 3) 1872 FIELD(V7M_CLIDR, LOC, 24, 3) 1873 FIELD(V7M_CLIDR, LOUU, 27, 3) 1874 FIELD(V7M_CLIDR, ICB, 30, 2) 1875 1876 FIELD(V7M_CSSELR, IND, 0, 1) 1877 FIELD(V7M_CSSELR, LEVEL, 1, 3) 1878 /* We use the combination of InD and Level to index into cpu->ccsidr[]; 1879 * define a mask for this and check that it doesn't permit running off 1880 * the end of the array. 1881 */ 1882 FIELD(V7M_CSSELR, INDEX, 0, 4) 1883 1884 /* v7M FPCCR bits */ 1885 FIELD(V7M_FPCCR, LSPACT, 0, 1) 1886 FIELD(V7M_FPCCR, USER, 1, 1) 1887 FIELD(V7M_FPCCR, S, 2, 1) 1888 FIELD(V7M_FPCCR, THREAD, 3, 1) 1889 FIELD(V7M_FPCCR, HFRDY, 4, 1) 1890 FIELD(V7M_FPCCR, MMRDY, 5, 1) 1891 FIELD(V7M_FPCCR, BFRDY, 6, 1) 1892 FIELD(V7M_FPCCR, SFRDY, 7, 1) 1893 FIELD(V7M_FPCCR, MONRDY, 8, 1) 1894 FIELD(V7M_FPCCR, SPLIMVIOL, 9, 1) 1895 FIELD(V7M_FPCCR, UFRDY, 10, 1) 1896 FIELD(V7M_FPCCR, RES0, 11, 15) 1897 FIELD(V7M_FPCCR, TS, 26, 1) 1898 FIELD(V7M_FPCCR, CLRONRETS, 27, 1) 1899 FIELD(V7M_FPCCR, CLRONRET, 28, 1) 1900 FIELD(V7M_FPCCR, LSPENS, 29, 1) 1901 FIELD(V7M_FPCCR, LSPEN, 30, 1) 1902 FIELD(V7M_FPCCR, ASPEN, 31, 1) 1903 /* These bits are banked. Others are non-banked and live in the M_REG_S bank */ 1904 #define R_V7M_FPCCR_BANKED_MASK \ 1905 (R_V7M_FPCCR_LSPACT_MASK | \ 1906 R_V7M_FPCCR_USER_MASK | \ 1907 R_V7M_FPCCR_THREAD_MASK | \ 1908 R_V7M_FPCCR_MMRDY_MASK | \ 1909 R_V7M_FPCCR_SPLIMVIOL_MASK | \ 1910 R_V7M_FPCCR_UFRDY_MASK | \ 1911 R_V7M_FPCCR_ASPEN_MASK) 1912 1913 /* v7M VPR bits */ 1914 FIELD(V7M_VPR, P0, 0, 16) 1915 FIELD(V7M_VPR, MASK01, 16, 4) 1916 FIELD(V7M_VPR, MASK23, 20, 4) 1917 1918 /* 1919 * System register ID fields. 1920 */ 1921 FIELD(CLIDR_EL1, CTYPE1, 0, 3) 1922 FIELD(CLIDR_EL1, CTYPE2, 3, 3) 1923 FIELD(CLIDR_EL1, CTYPE3, 6, 3) 1924 FIELD(CLIDR_EL1, CTYPE4, 9, 3) 1925 FIELD(CLIDR_EL1, CTYPE5, 12, 3) 1926 FIELD(CLIDR_EL1, CTYPE6, 15, 3) 1927 FIELD(CLIDR_EL1, CTYPE7, 18, 3) 1928 FIELD(CLIDR_EL1, LOUIS, 21, 3) 1929 FIELD(CLIDR_EL1, LOC, 24, 3) 1930 FIELD(CLIDR_EL1, LOUU, 27, 3) 1931 FIELD(CLIDR_EL1, ICB, 30, 3) 1932 1933 /* When FEAT_CCIDX is implemented */ 1934 FIELD(CCSIDR_EL1, CCIDX_LINESIZE, 0, 3) 1935 FIELD(CCSIDR_EL1, CCIDX_ASSOCIATIVITY, 3, 21) 1936 FIELD(CCSIDR_EL1, CCIDX_NUMSETS, 32, 24) 1937 1938 /* When FEAT_CCIDX is not implemented */ 1939 FIELD(CCSIDR_EL1, LINESIZE, 0, 3) 1940 FIELD(CCSIDR_EL1, ASSOCIATIVITY, 3, 10) 1941 FIELD(CCSIDR_EL1, NUMSETS, 13, 15) 1942 1943 FIELD(CTR_EL0, IMINLINE, 0, 4) 1944 FIELD(CTR_EL0, L1IP, 14, 2) 1945 FIELD(CTR_EL0, DMINLINE, 16, 4) 1946 FIELD(CTR_EL0, ERG, 20, 4) 1947 FIELD(CTR_EL0, CWG, 24, 4) 1948 FIELD(CTR_EL0, IDC, 28, 1) 1949 FIELD(CTR_EL0, DIC, 29, 1) 1950 FIELD(CTR_EL0, TMINLINE, 32, 6) 1951 1952 FIELD(MIDR_EL1, REVISION, 0, 4) 1953 FIELD(MIDR_EL1, PARTNUM, 4, 12) 1954 FIELD(MIDR_EL1, ARCHITECTURE, 16, 4) 1955 FIELD(MIDR_EL1, VARIANT, 20, 4) 1956 FIELD(MIDR_EL1, IMPLEMENTER, 24, 8) 1957 1958 FIELD(ID_ISAR0, SWAP, 0, 4) 1959 FIELD(ID_ISAR0, BITCOUNT, 4, 4) 1960 FIELD(ID_ISAR0, BITFIELD, 8, 4) 1961 FIELD(ID_ISAR0, CMPBRANCH, 12, 4) 1962 FIELD(ID_ISAR0, COPROC, 16, 4) 1963 FIELD(ID_ISAR0, DEBUG, 20, 4) 1964 FIELD(ID_ISAR0, DIVIDE, 24, 4) 1965 1966 FIELD(ID_ISAR1, ENDIAN, 0, 4) 1967 FIELD(ID_ISAR1, EXCEPT, 4, 4) 1968 FIELD(ID_ISAR1, EXCEPT_AR, 8, 4) 1969 FIELD(ID_ISAR1, EXTEND, 12, 4) 1970 FIELD(ID_ISAR1, IFTHEN, 16, 4) 1971 FIELD(ID_ISAR1, IMMEDIATE, 20, 4) 1972 FIELD(ID_ISAR1, INTERWORK, 24, 4) 1973 FIELD(ID_ISAR1, JAZELLE, 28, 4) 1974 1975 FIELD(ID_ISAR2, LOADSTORE, 0, 4) 1976 FIELD(ID_ISAR2, MEMHINT, 4, 4) 1977 FIELD(ID_ISAR2, MULTIACCESSINT, 8, 4) 1978 FIELD(ID_ISAR2, MULT, 12, 4) 1979 FIELD(ID_ISAR2, MULTS, 16, 4) 1980 FIELD(ID_ISAR2, MULTU, 20, 4) 1981 FIELD(ID_ISAR2, PSR_AR, 24, 4) 1982 FIELD(ID_ISAR2, REVERSAL, 28, 4) 1983 1984 FIELD(ID_ISAR3, SATURATE, 0, 4) 1985 FIELD(ID_ISAR3, SIMD, 4, 4) 1986 FIELD(ID_ISAR3, SVC, 8, 4) 1987 FIELD(ID_ISAR3, SYNCHPRIM, 12, 4) 1988 FIELD(ID_ISAR3, TABBRANCH, 16, 4) 1989 FIELD(ID_ISAR3, T32COPY, 20, 4) 1990 FIELD(ID_ISAR3, TRUENOP, 24, 4) 1991 FIELD(ID_ISAR3, T32EE, 28, 4) 1992 1993 FIELD(ID_ISAR4, UNPRIV, 0, 4) 1994 FIELD(ID_ISAR4, WITHSHIFTS, 4, 4) 1995 FIELD(ID_ISAR4, WRITEBACK, 8, 4) 1996 FIELD(ID_ISAR4, SMC, 12, 4) 1997 FIELD(ID_ISAR4, BARRIER, 16, 4) 1998 FIELD(ID_ISAR4, SYNCHPRIM_FRAC, 20, 4) 1999 FIELD(ID_ISAR4, PSR_M, 24, 4) 2000 FIELD(ID_ISAR4, SWP_FRAC, 28, 4) 2001 2002 FIELD(ID_ISAR5, SEVL, 0, 4) 2003 FIELD(ID_ISAR5, AES, 4, 4) 2004 FIELD(ID_ISAR5, SHA1, 8, 4) 2005 FIELD(ID_ISAR5, SHA2, 12, 4) 2006 FIELD(ID_ISAR5, CRC32, 16, 4) 2007 FIELD(ID_ISAR5, RDM, 24, 4) 2008 FIELD(ID_ISAR5, VCMA, 28, 4) 2009 2010 FIELD(ID_ISAR6, JSCVT, 0, 4) 2011 FIELD(ID_ISAR6, DP, 4, 4) 2012 FIELD(ID_ISAR6, FHM, 8, 4) 2013 FIELD(ID_ISAR6, SB, 12, 4) 2014 FIELD(ID_ISAR6, SPECRES, 16, 4) 2015 FIELD(ID_ISAR6, BF16, 20, 4) 2016 FIELD(ID_ISAR6, I8MM, 24, 4) 2017 2018 FIELD(ID_MMFR0, VMSA, 0, 4) 2019 FIELD(ID_MMFR0, PMSA, 4, 4) 2020 FIELD(ID_MMFR0, OUTERSHR, 8, 4) 2021 FIELD(ID_MMFR0, SHARELVL, 12, 4) 2022 FIELD(ID_MMFR0, TCM, 16, 4) 2023 FIELD(ID_MMFR0, AUXREG, 20, 4) 2024 FIELD(ID_MMFR0, FCSE, 24, 4) 2025 FIELD(ID_MMFR0, INNERSHR, 28, 4) 2026 2027 FIELD(ID_MMFR1, L1HVDVA, 0, 4) 2028 FIELD(ID_MMFR1, L1UNIVA, 4, 4) 2029 FIELD(ID_MMFR1, L1HVDSW, 8, 4) 2030 FIELD(ID_MMFR1, L1UNISW, 12, 4) 2031 FIELD(ID_MMFR1, L1HVD, 16, 4) 2032 FIELD(ID_MMFR1, L1UNI, 20, 4) 2033 FIELD(ID_MMFR1, L1TSTCLN, 24, 4) 2034 FIELD(ID_MMFR1, BPRED, 28, 4) 2035 2036 FIELD(ID_MMFR2, L1HVDFG, 0, 4) 2037 FIELD(ID_MMFR2, L1HVDBG, 4, 4) 2038 FIELD(ID_MMFR2, L1HVDRNG, 8, 4) 2039 FIELD(ID_MMFR2, HVDTLB, 12, 4) 2040 FIELD(ID_MMFR2, UNITLB, 16, 4) 2041 FIELD(ID_MMFR2, MEMBARR, 20, 4) 2042 FIELD(ID_MMFR2, WFISTALL, 24, 4) 2043 FIELD(ID_MMFR2, HWACCFLG, 28, 4) 2044 2045 FIELD(ID_MMFR3, CMAINTVA, 0, 4) 2046 FIELD(ID_MMFR3, CMAINTSW, 4, 4) 2047 FIELD(ID_MMFR3, BPMAINT, 8, 4) 2048 FIELD(ID_MMFR3, MAINTBCST, 12, 4) 2049 FIELD(ID_MMFR3, PAN, 16, 4) 2050 FIELD(ID_MMFR3, COHWALK, 20, 4) 2051 FIELD(ID_MMFR3, CMEMSZ, 24, 4) 2052 FIELD(ID_MMFR3, SUPERSEC, 28, 4) 2053 2054 FIELD(ID_MMFR4, SPECSEI, 0, 4) 2055 FIELD(ID_MMFR4, AC2, 4, 4) 2056 FIELD(ID_MMFR4, XNX, 8, 4) 2057 FIELD(ID_MMFR4, CNP, 12, 4) 2058 FIELD(ID_MMFR4, HPDS, 16, 4) 2059 FIELD(ID_MMFR4, LSM, 20, 4) 2060 FIELD(ID_MMFR4, CCIDX, 24, 4) 2061 FIELD(ID_MMFR4, EVT, 28, 4) 2062 2063 FIELD(ID_MMFR5, ETS, 0, 4) 2064 FIELD(ID_MMFR5, NTLBPA, 4, 4) 2065 2066 FIELD(ID_PFR0, STATE0, 0, 4) 2067 FIELD(ID_PFR0, STATE1, 4, 4) 2068 FIELD(ID_PFR0, STATE2, 8, 4) 2069 FIELD(ID_PFR0, STATE3, 12, 4) 2070 FIELD(ID_PFR0, CSV2, 16, 4) 2071 FIELD(ID_PFR0, AMU, 20, 4) 2072 FIELD(ID_PFR0, DIT, 24, 4) 2073 FIELD(ID_PFR0, RAS, 28, 4) 2074 2075 FIELD(ID_PFR1, PROGMOD, 0, 4) 2076 FIELD(ID_PFR1, SECURITY, 4, 4) 2077 FIELD(ID_PFR1, MPROGMOD, 8, 4) 2078 FIELD(ID_PFR1, VIRTUALIZATION, 12, 4) 2079 FIELD(ID_PFR1, GENTIMER, 16, 4) 2080 FIELD(ID_PFR1, SEC_FRAC, 20, 4) 2081 FIELD(ID_PFR1, VIRT_FRAC, 24, 4) 2082 FIELD(ID_PFR1, GIC, 28, 4) 2083 2084 FIELD(ID_PFR2, CSV3, 0, 4) 2085 FIELD(ID_PFR2, SSBS, 4, 4) 2086 FIELD(ID_PFR2, RAS_FRAC, 8, 4) 2087 2088 FIELD(ID_AA64ISAR0, AES, 4, 4) 2089 FIELD(ID_AA64ISAR0, SHA1, 8, 4) 2090 FIELD(ID_AA64ISAR0, SHA2, 12, 4) 2091 FIELD(ID_AA64ISAR0, CRC32, 16, 4) 2092 FIELD(ID_AA64ISAR0, ATOMIC, 20, 4) 2093 FIELD(ID_AA64ISAR0, TME, 24, 4) 2094 FIELD(ID_AA64ISAR0, RDM, 28, 4) 2095 FIELD(ID_AA64ISAR0, SHA3, 32, 4) 2096 FIELD(ID_AA64ISAR0, SM3, 36, 4) 2097 FIELD(ID_AA64ISAR0, SM4, 40, 4) 2098 FIELD(ID_AA64ISAR0, DP, 44, 4) 2099 FIELD(ID_AA64ISAR0, FHM, 48, 4) 2100 FIELD(ID_AA64ISAR0, TS, 52, 4) 2101 FIELD(ID_AA64ISAR0, TLB, 56, 4) 2102 FIELD(ID_AA64ISAR0, RNDR, 60, 4) 2103 2104 FIELD(ID_AA64ISAR1, DPB, 0, 4) 2105 FIELD(ID_AA64ISAR1, APA, 4, 4) 2106 FIELD(ID_AA64ISAR1, API, 8, 4) 2107 FIELD(ID_AA64ISAR1, JSCVT, 12, 4) 2108 FIELD(ID_AA64ISAR1, FCMA, 16, 4) 2109 FIELD(ID_AA64ISAR1, LRCPC, 20, 4) 2110 FIELD(ID_AA64ISAR1, GPA, 24, 4) 2111 FIELD(ID_AA64ISAR1, GPI, 28, 4) 2112 FIELD(ID_AA64ISAR1, FRINTTS, 32, 4) 2113 FIELD(ID_AA64ISAR1, SB, 36, 4) 2114 FIELD(ID_AA64ISAR1, SPECRES, 40, 4) 2115 FIELD(ID_AA64ISAR1, BF16, 44, 4) 2116 FIELD(ID_AA64ISAR1, DGH, 48, 4) 2117 FIELD(ID_AA64ISAR1, I8MM, 52, 4) 2118 FIELD(ID_AA64ISAR1, XS, 56, 4) 2119 FIELD(ID_AA64ISAR1, LS64, 60, 4) 2120 2121 FIELD(ID_AA64ISAR2, WFXT, 0, 4) 2122 FIELD(ID_AA64ISAR2, RPRES, 4, 4) 2123 FIELD(ID_AA64ISAR2, GPA3, 8, 4) 2124 FIELD(ID_AA64ISAR2, APA3, 12, 4) 2125 FIELD(ID_AA64ISAR2, MOPS, 16, 4) 2126 FIELD(ID_AA64ISAR2, BC, 20, 4) 2127 FIELD(ID_AA64ISAR2, PAC_FRAC, 24, 4) 2128 FIELD(ID_AA64ISAR2, CLRBHB, 28, 4) 2129 FIELD(ID_AA64ISAR2, SYSREG_128, 32, 4) 2130 FIELD(ID_AA64ISAR2, SYSINSTR_128, 36, 4) 2131 FIELD(ID_AA64ISAR2, PRFMSLC, 40, 4) 2132 FIELD(ID_AA64ISAR2, RPRFM, 48, 4) 2133 FIELD(ID_AA64ISAR2, CSSC, 52, 4) 2134 FIELD(ID_AA64ISAR2, ATS1A, 60, 4) 2135 2136 FIELD(ID_AA64PFR0, EL0, 0, 4) 2137 FIELD(ID_AA64PFR0, EL1, 4, 4) 2138 FIELD(ID_AA64PFR0, EL2, 8, 4) 2139 FIELD(ID_AA64PFR0, EL3, 12, 4) 2140 FIELD(ID_AA64PFR0, FP, 16, 4) 2141 FIELD(ID_AA64PFR0, ADVSIMD, 20, 4) 2142 FIELD(ID_AA64PFR0, GIC, 24, 4) 2143 FIELD(ID_AA64PFR0, RAS, 28, 4) 2144 FIELD(ID_AA64PFR0, SVE, 32, 4) 2145 FIELD(ID_AA64PFR0, SEL2, 36, 4) 2146 FIELD(ID_AA64PFR0, MPAM, 40, 4) 2147 FIELD(ID_AA64PFR0, AMU, 44, 4) 2148 FIELD(ID_AA64PFR0, DIT, 48, 4) 2149 FIELD(ID_AA64PFR0, RME, 52, 4) 2150 FIELD(ID_AA64PFR0, CSV2, 56, 4) 2151 FIELD(ID_AA64PFR0, CSV3, 60, 4) 2152 2153 FIELD(ID_AA64PFR1, BT, 0, 4) 2154 FIELD(ID_AA64PFR1, SSBS, 4, 4) 2155 FIELD(ID_AA64PFR1, MTE, 8, 4) 2156 FIELD(ID_AA64PFR1, RAS_FRAC, 12, 4) 2157 FIELD(ID_AA64PFR1, MPAM_FRAC, 16, 4) 2158 FIELD(ID_AA64PFR1, SME, 24, 4) 2159 FIELD(ID_AA64PFR1, RNDR_TRAP, 28, 4) 2160 FIELD(ID_AA64PFR1, CSV2_FRAC, 32, 4) 2161 FIELD(ID_AA64PFR1, NMI, 36, 4) 2162 FIELD(ID_AA64PFR1, MTE_FRAC, 40, 4) 2163 FIELD(ID_AA64PFR1, GCS, 44, 4) 2164 FIELD(ID_AA64PFR1, THE, 48, 4) 2165 FIELD(ID_AA64PFR1, MTEX, 52, 4) 2166 FIELD(ID_AA64PFR1, DF2, 56, 4) 2167 FIELD(ID_AA64PFR1, PFAR, 60, 4) 2168 2169 FIELD(ID_AA64MMFR0, PARANGE, 0, 4) 2170 FIELD(ID_AA64MMFR0, ASIDBITS, 4, 4) 2171 FIELD(ID_AA64MMFR0, BIGEND, 8, 4) 2172 FIELD(ID_AA64MMFR0, SNSMEM, 12, 4) 2173 FIELD(ID_AA64MMFR0, BIGENDEL0, 16, 4) 2174 FIELD(ID_AA64MMFR0, TGRAN16, 20, 4) 2175 FIELD(ID_AA64MMFR0, TGRAN64, 24, 4) 2176 FIELD(ID_AA64MMFR0, TGRAN4, 28, 4) 2177 FIELD(ID_AA64MMFR0, TGRAN16_2, 32, 4) 2178 FIELD(ID_AA64MMFR0, TGRAN64_2, 36, 4) 2179 FIELD(ID_AA64MMFR0, TGRAN4_2, 40, 4) 2180 FIELD(ID_AA64MMFR0, EXS, 44, 4) 2181 FIELD(ID_AA64MMFR0, FGT, 56, 4) 2182 FIELD(ID_AA64MMFR0, ECV, 60, 4) 2183 2184 FIELD(ID_AA64MMFR1, HAFDBS, 0, 4) 2185 FIELD(ID_AA64MMFR1, VMIDBITS, 4, 4) 2186 FIELD(ID_AA64MMFR1, VH, 8, 4) 2187 FIELD(ID_AA64MMFR1, HPDS, 12, 4) 2188 FIELD(ID_AA64MMFR1, LO, 16, 4) 2189 FIELD(ID_AA64MMFR1, PAN, 20, 4) 2190 FIELD(ID_AA64MMFR1, SPECSEI, 24, 4) 2191 FIELD(ID_AA64MMFR1, XNX, 28, 4) 2192 FIELD(ID_AA64MMFR1, TWED, 32, 4) 2193 FIELD(ID_AA64MMFR1, ETS, 36, 4) 2194 FIELD(ID_AA64MMFR1, HCX, 40, 4) 2195 FIELD(ID_AA64MMFR1, AFP, 44, 4) 2196 FIELD(ID_AA64MMFR1, NTLBPA, 48, 4) 2197 FIELD(ID_AA64MMFR1, TIDCP1, 52, 4) 2198 FIELD(ID_AA64MMFR1, CMOW, 56, 4) 2199 FIELD(ID_AA64MMFR1, ECBHB, 60, 4) 2200 2201 FIELD(ID_AA64MMFR2, CNP, 0, 4) 2202 FIELD(ID_AA64MMFR2, UAO, 4, 4) 2203 FIELD(ID_AA64MMFR2, LSM, 8, 4) 2204 FIELD(ID_AA64MMFR2, IESB, 12, 4) 2205 FIELD(ID_AA64MMFR2, VARANGE, 16, 4) 2206 FIELD(ID_AA64MMFR2, CCIDX, 20, 4) 2207 FIELD(ID_AA64MMFR2, NV, 24, 4) 2208 FIELD(ID_AA64MMFR2, ST, 28, 4) 2209 FIELD(ID_AA64MMFR2, AT, 32, 4) 2210 FIELD(ID_AA64MMFR2, IDS, 36, 4) 2211 FIELD(ID_AA64MMFR2, FWB, 40, 4) 2212 FIELD(ID_AA64MMFR2, TTL, 48, 4) 2213 FIELD(ID_AA64MMFR2, BBM, 52, 4) 2214 FIELD(ID_AA64MMFR2, EVT, 56, 4) 2215 FIELD(ID_AA64MMFR2, E0PD, 60, 4) 2216 2217 FIELD(ID_AA64MMFR3, TCRX, 0, 4) 2218 FIELD(ID_AA64MMFR3, SCTLRX, 4, 4) 2219 FIELD(ID_AA64MMFR3, S1PIE, 8, 4) 2220 FIELD(ID_AA64MMFR3, S2PIE, 12, 4) 2221 FIELD(ID_AA64MMFR3, S1POE, 16, 4) 2222 FIELD(ID_AA64MMFR3, S2POE, 20, 4) 2223 FIELD(ID_AA64MMFR3, AIE, 24, 4) 2224 FIELD(ID_AA64MMFR3, MEC, 28, 4) 2225 FIELD(ID_AA64MMFR3, D128, 32, 4) 2226 FIELD(ID_AA64MMFR3, D128_2, 36, 4) 2227 FIELD(ID_AA64MMFR3, SNERR, 40, 4) 2228 FIELD(ID_AA64MMFR3, ANERR, 44, 4) 2229 FIELD(ID_AA64MMFR3, SDERR, 52, 4) 2230 FIELD(ID_AA64MMFR3, ADERR, 56, 4) 2231 FIELD(ID_AA64MMFR3, SPEC_FPACC, 60, 4) 2232 2233 FIELD(ID_AA64DFR0, DEBUGVER, 0, 4) 2234 FIELD(ID_AA64DFR0, TRACEVER, 4, 4) 2235 FIELD(ID_AA64DFR0, PMUVER, 8, 4) 2236 FIELD(ID_AA64DFR0, BRPS, 12, 4) 2237 FIELD(ID_AA64DFR0, PMSS, 16, 4) 2238 FIELD(ID_AA64DFR0, WRPS, 20, 4) 2239 FIELD(ID_AA64DFR0, SEBEP, 24, 4) 2240 FIELD(ID_AA64DFR0, CTX_CMPS, 28, 4) 2241 FIELD(ID_AA64DFR0, PMSVER, 32, 4) 2242 FIELD(ID_AA64DFR0, DOUBLELOCK, 36, 4) 2243 FIELD(ID_AA64DFR0, TRACEFILT, 40, 4) 2244 FIELD(ID_AA64DFR0, TRACEBUFFER, 44, 4) 2245 FIELD(ID_AA64DFR0, MTPMU, 48, 4) 2246 FIELD(ID_AA64DFR0, BRBE, 52, 4) 2247 FIELD(ID_AA64DFR0, EXTTRCBUFF, 56, 4) 2248 FIELD(ID_AA64DFR0, HPMN0, 60, 4) 2249 2250 FIELD(ID_AA64ZFR0, SVEVER, 0, 4) 2251 FIELD(ID_AA64ZFR0, AES, 4, 4) 2252 FIELD(ID_AA64ZFR0, BITPERM, 16, 4) 2253 FIELD(ID_AA64ZFR0, BFLOAT16, 20, 4) 2254 FIELD(ID_AA64ZFR0, B16B16, 24, 4) 2255 FIELD(ID_AA64ZFR0, SHA3, 32, 4) 2256 FIELD(ID_AA64ZFR0, SM4, 40, 4) 2257 FIELD(ID_AA64ZFR0, I8MM, 44, 4) 2258 FIELD(ID_AA64ZFR0, F32MM, 52, 4) 2259 FIELD(ID_AA64ZFR0, F64MM, 56, 4) 2260 2261 FIELD(ID_AA64SMFR0, F32F32, 32, 1) 2262 FIELD(ID_AA64SMFR0, BI32I32, 33, 1) 2263 FIELD(ID_AA64SMFR0, B16F32, 34, 1) 2264 FIELD(ID_AA64SMFR0, F16F32, 35, 1) 2265 FIELD(ID_AA64SMFR0, I8I32, 36, 4) 2266 FIELD(ID_AA64SMFR0, F16F16, 42, 1) 2267 FIELD(ID_AA64SMFR0, B16B16, 43, 1) 2268 FIELD(ID_AA64SMFR0, I16I32, 44, 4) 2269 FIELD(ID_AA64SMFR0, F64F64, 48, 1) 2270 FIELD(ID_AA64SMFR0, I16I64, 52, 4) 2271 FIELD(ID_AA64SMFR0, SMEVER, 56, 4) 2272 FIELD(ID_AA64SMFR0, FA64, 63, 1) 2273 2274 FIELD(ID_DFR0, COPDBG, 0, 4) 2275 FIELD(ID_DFR0, COPSDBG, 4, 4) 2276 FIELD(ID_DFR0, MMAPDBG, 8, 4) 2277 FIELD(ID_DFR0, COPTRC, 12, 4) 2278 FIELD(ID_DFR0, MMAPTRC, 16, 4) 2279 FIELD(ID_DFR0, MPROFDBG, 20, 4) 2280 FIELD(ID_DFR0, PERFMON, 24, 4) 2281 FIELD(ID_DFR0, TRACEFILT, 28, 4) 2282 2283 FIELD(ID_DFR1, MTPMU, 0, 4) 2284 FIELD(ID_DFR1, HPMN0, 4, 4) 2285 2286 FIELD(DBGDIDR, SE_IMP, 12, 1) 2287 FIELD(DBGDIDR, NSUHD_IMP, 14, 1) 2288 FIELD(DBGDIDR, VERSION, 16, 4) 2289 FIELD(DBGDIDR, CTX_CMPS, 20, 4) 2290 FIELD(DBGDIDR, BRPS, 24, 4) 2291 FIELD(DBGDIDR, WRPS, 28, 4) 2292 2293 FIELD(DBGDEVID, PCSAMPLE, 0, 4) 2294 FIELD(DBGDEVID, WPADDRMASK, 4, 4) 2295 FIELD(DBGDEVID, BPADDRMASK, 8, 4) 2296 FIELD(DBGDEVID, VECTORCATCH, 12, 4) 2297 FIELD(DBGDEVID, VIRTEXTNS, 16, 4) 2298 FIELD(DBGDEVID, DOUBLELOCK, 20, 4) 2299 FIELD(DBGDEVID, AUXREGS, 24, 4) 2300 FIELD(DBGDEVID, CIDMASK, 28, 4) 2301 2302 FIELD(DBGDEVID1, PCSROFFSET, 0, 4) 2303 2304 FIELD(MVFR0, SIMDREG, 0, 4) 2305 FIELD(MVFR0, FPSP, 4, 4) 2306 FIELD(MVFR0, FPDP, 8, 4) 2307 FIELD(MVFR0, FPTRAP, 12, 4) 2308 FIELD(MVFR0, FPDIVIDE, 16, 4) 2309 FIELD(MVFR0, FPSQRT, 20, 4) 2310 FIELD(MVFR0, FPSHVEC, 24, 4) 2311 FIELD(MVFR0, FPROUND, 28, 4) 2312 2313 FIELD(MVFR1, FPFTZ, 0, 4) 2314 FIELD(MVFR1, FPDNAN, 4, 4) 2315 FIELD(MVFR1, SIMDLS, 8, 4) /* A-profile only */ 2316 FIELD(MVFR1, SIMDINT, 12, 4) /* A-profile only */ 2317 FIELD(MVFR1, SIMDSP, 16, 4) /* A-profile only */ 2318 FIELD(MVFR1, SIMDHP, 20, 4) /* A-profile only */ 2319 FIELD(MVFR1, MVE, 8, 4) /* M-profile only */ 2320 FIELD(MVFR1, FP16, 20, 4) /* M-profile only */ 2321 FIELD(MVFR1, FPHP, 24, 4) 2322 FIELD(MVFR1, SIMDFMAC, 28, 4) 2323 2324 FIELD(MVFR2, SIMDMISC, 0, 4) 2325 FIELD(MVFR2, FPMISC, 4, 4) 2326 2327 FIELD(GPCCR, PPS, 0, 3) 2328 FIELD(GPCCR, IRGN, 8, 2) 2329 FIELD(GPCCR, ORGN, 10, 2) 2330 FIELD(GPCCR, SH, 12, 2) 2331 FIELD(GPCCR, PGS, 14, 2) 2332 FIELD(GPCCR, GPC, 16, 1) 2333 FIELD(GPCCR, GPCP, 17, 1) 2334 FIELD(GPCCR, L0GPTSZ, 20, 4) 2335 2336 FIELD(MFAR, FPA, 12, 40) 2337 FIELD(MFAR, NSE, 62, 1) 2338 FIELD(MFAR, NS, 63, 1) 2339 2340 QEMU_BUILD_BUG_ON(ARRAY_SIZE(((ARMCPU *)0)->ccsidr) <= R_V7M_CSSELR_INDEX_MASK); 2341 2342 /* If adding a feature bit which corresponds to a Linux ELF 2343 * HWCAP bit, remember to update the feature-bit-to-hwcap 2344 * mapping in linux-user/elfload.c:get_elf_hwcap(). 2345 */ 2346 enum arm_features { 2347 ARM_FEATURE_AUXCR, /* ARM1026 Auxiliary control register. */ 2348 ARM_FEATURE_XSCALE, /* Intel XScale extensions. */ 2349 ARM_FEATURE_IWMMXT, /* Intel iwMMXt extension. */ 2350 ARM_FEATURE_V6, 2351 ARM_FEATURE_V6K, 2352 ARM_FEATURE_V7, 2353 ARM_FEATURE_THUMB2, 2354 ARM_FEATURE_PMSA, /* no MMU; may have Memory Protection Unit */ 2355 ARM_FEATURE_NEON, 2356 ARM_FEATURE_M, /* Microcontroller profile. */ 2357 ARM_FEATURE_OMAPCP, /* OMAP specific CP15 ops handling. */ 2358 ARM_FEATURE_THUMB2EE, 2359 ARM_FEATURE_V7MP, /* v7 Multiprocessing Extensions */ 2360 ARM_FEATURE_V7VE, /* v7 Virtualization Extensions (non-EL2 parts) */ 2361 ARM_FEATURE_V4T, 2362 ARM_FEATURE_V5, 2363 ARM_FEATURE_STRONGARM, 2364 ARM_FEATURE_VAPA, /* cp15 VA to PA lookups */ 2365 ARM_FEATURE_GENERIC_TIMER, 2366 ARM_FEATURE_MVFR, /* Media and VFP Feature Registers 0 and 1 */ 2367 ARM_FEATURE_DUMMY_C15_REGS, /* RAZ/WI all of cp15 crn=15 */ 2368 ARM_FEATURE_CACHE_TEST_CLEAN, /* 926/1026 style test-and-clean ops */ 2369 ARM_FEATURE_CACHE_DIRTY_REG, /* 1136/1176 cache dirty status register */ 2370 ARM_FEATURE_CACHE_BLOCK_OPS, /* v6 optional cache block operations */ 2371 ARM_FEATURE_MPIDR, /* has cp15 MPIDR */ 2372 ARM_FEATURE_LPAE, /* has Large Physical Address Extension */ 2373 ARM_FEATURE_V8, 2374 ARM_FEATURE_AARCH64, /* supports 64 bit mode */ 2375 ARM_FEATURE_CBAR, /* has cp15 CBAR */ 2376 ARM_FEATURE_CBAR_RO, /* has cp15 CBAR and it is read-only */ 2377 ARM_FEATURE_EL2, /* has EL2 Virtualization support */ 2378 ARM_FEATURE_EL3, /* has EL3 Secure monitor support */ 2379 ARM_FEATURE_THUMB_DSP, /* DSP insns supported in the Thumb encodings */ 2380 ARM_FEATURE_PMU, /* has PMU support */ 2381 ARM_FEATURE_VBAR, /* has cp15 VBAR */ 2382 ARM_FEATURE_M_SECURITY, /* M profile Security Extension */ 2383 ARM_FEATURE_M_MAIN, /* M profile Main Extension */ 2384 ARM_FEATURE_V8_1M, /* M profile extras only in v8.1M and later */ 2385 /* 2386 * ARM_FEATURE_BACKCOMPAT_CNTFRQ makes the CPU default cntfrq be 62.5MHz 2387 * if the board doesn't set a value, instead of 1GHz. It is for backwards 2388 * compatibility and used only with CPU definitions that were already 2389 * in QEMU before we changed the default. It should not be set on any 2390 * CPU types added in future. 2391 */ 2392 ARM_FEATURE_BACKCOMPAT_CNTFRQ, /* 62.5MHz timer default */ 2393 }; 2394 2395 static inline int arm_feature(CPUARMState *env, int feature) 2396 { 2397 return (env->features & (1ULL << feature)) != 0; 2398 } 2399 2400 void arm_cpu_finalize_features(ARMCPU *cpu, Error **errp); 2401 2402 /* 2403 * ARM v9 security states. 2404 * The ordering of the enumeration corresponds to the low 2 bits 2405 * of the GPI value, and (except for Root) the concat of NSE:NS. 2406 */ 2407 2408 typedef enum ARMSecuritySpace { 2409 ARMSS_Secure = 0, 2410 ARMSS_NonSecure = 1, 2411 ARMSS_Root = 2, 2412 ARMSS_Realm = 3, 2413 } ARMSecuritySpace; 2414 2415 /* Return true if @space is secure, in the pre-v9 sense. */ 2416 static inline bool arm_space_is_secure(ARMSecuritySpace space) 2417 { 2418 return space == ARMSS_Secure || space == ARMSS_Root; 2419 } 2420 2421 /* Return the ARMSecuritySpace for @secure, assuming !RME or EL[0-2]. */ 2422 static inline ARMSecuritySpace arm_secure_to_space(bool secure) 2423 { 2424 return secure ? ARMSS_Secure : ARMSS_NonSecure; 2425 } 2426 2427 #if !defined(CONFIG_USER_ONLY) 2428 /** 2429 * arm_security_space_below_el3: 2430 * @env: cpu context 2431 * 2432 * Return the security space of exception levels below EL3, following 2433 * an exception return to those levels. Unlike arm_security_space, 2434 * this doesn't care about the current EL. 2435 */ 2436 ARMSecuritySpace arm_security_space_below_el3(CPUARMState *env); 2437 2438 /** 2439 * arm_is_secure_below_el3: 2440 * @env: cpu context 2441 * 2442 * Return true if exception levels below EL3 are in secure state, 2443 * or would be following an exception return to those levels. 2444 */ 2445 static inline bool arm_is_secure_below_el3(CPUARMState *env) 2446 { 2447 ARMSecuritySpace ss = arm_security_space_below_el3(env); 2448 return ss == ARMSS_Secure; 2449 } 2450 2451 /* Return true if the CPU is AArch64 EL3 or AArch32 Mon */ 2452 static inline bool arm_is_el3_or_mon(CPUARMState *env) 2453 { 2454 assert(!arm_feature(env, ARM_FEATURE_M)); 2455 if (arm_feature(env, ARM_FEATURE_EL3)) { 2456 if (is_a64(env) && extract32(env->pstate, 2, 2) == 3) { 2457 /* CPU currently in AArch64 state and EL3 */ 2458 return true; 2459 } else if (!is_a64(env) && 2460 (env->uncached_cpsr & CPSR_M) == ARM_CPU_MODE_MON) { 2461 /* CPU currently in AArch32 state and monitor mode */ 2462 return true; 2463 } 2464 } 2465 return false; 2466 } 2467 2468 /** 2469 * arm_security_space: 2470 * @env: cpu context 2471 * 2472 * Return the current security space of the cpu. 2473 */ 2474 ARMSecuritySpace arm_security_space(CPUARMState *env); 2475 2476 /** 2477 * arm_is_secure: 2478 * @env: cpu context 2479 * 2480 * Return true if the processor is in secure state. 2481 */ 2482 static inline bool arm_is_secure(CPUARMState *env) 2483 { 2484 return arm_space_is_secure(arm_security_space(env)); 2485 } 2486 2487 /* 2488 * Return true if the current security state has AArch64 EL2 or AArch32 Hyp. 2489 * This corresponds to the pseudocode EL2Enabled(). 2490 */ 2491 static inline bool arm_is_el2_enabled_secstate(CPUARMState *env, 2492 ARMSecuritySpace space) 2493 { 2494 assert(space != ARMSS_Root); 2495 return arm_feature(env, ARM_FEATURE_EL2) 2496 && (space != ARMSS_Secure || (env->cp15.scr_el3 & SCR_EEL2)); 2497 } 2498 2499 static inline bool arm_is_el2_enabled(CPUARMState *env) 2500 { 2501 return arm_is_el2_enabled_secstate(env, arm_security_space_below_el3(env)); 2502 } 2503 2504 #else 2505 static inline ARMSecuritySpace arm_security_space_below_el3(CPUARMState *env) 2506 { 2507 return ARMSS_NonSecure; 2508 } 2509 2510 static inline bool arm_is_secure_below_el3(CPUARMState *env) 2511 { 2512 return false; 2513 } 2514 2515 static inline ARMSecuritySpace arm_security_space(CPUARMState *env) 2516 { 2517 return ARMSS_NonSecure; 2518 } 2519 2520 static inline bool arm_is_secure(CPUARMState *env) 2521 { 2522 return false; 2523 } 2524 2525 static inline bool arm_is_el2_enabled_secstate(CPUARMState *env, 2526 ARMSecuritySpace space) 2527 { 2528 return false; 2529 } 2530 2531 static inline bool arm_is_el2_enabled(CPUARMState *env) 2532 { 2533 return false; 2534 } 2535 #endif 2536 2537 /** 2538 * arm_hcr_el2_eff(): Return the effective value of HCR_EL2. 2539 * E.g. when in secure state, fields in HCR_EL2 are suppressed, 2540 * "for all purposes other than a direct read or write access of HCR_EL2." 2541 * Not included here is HCR_RW. 2542 */ 2543 uint64_t arm_hcr_el2_eff_secstate(CPUARMState *env, ARMSecuritySpace space); 2544 uint64_t arm_hcr_el2_eff(CPUARMState *env); 2545 uint64_t arm_hcrx_el2_eff(CPUARMState *env); 2546 2547 /* Return true if the specified exception level is running in AArch64 state. */ 2548 static inline bool arm_el_is_aa64(CPUARMState *env, int el) 2549 { 2550 /* This isn't valid for EL0 (if we're in EL0, is_a64() is what you want, 2551 * and if we're not in EL0 then the state of EL0 isn't well defined.) 2552 */ 2553 assert(el >= 1 && el <= 3); 2554 bool aa64 = arm_feature(env, ARM_FEATURE_AARCH64); 2555 2556 /* The highest exception level is always at the maximum supported 2557 * register width, and then lower levels have a register width controlled 2558 * by bits in the SCR or HCR registers. 2559 */ 2560 if (el == 3) { 2561 return aa64; 2562 } 2563 2564 if (arm_feature(env, ARM_FEATURE_EL3) && 2565 ((env->cp15.scr_el3 & SCR_NS) || !(env->cp15.scr_el3 & SCR_EEL2))) { 2566 aa64 = aa64 && (env->cp15.scr_el3 & SCR_RW); 2567 } 2568 2569 if (el == 2) { 2570 return aa64; 2571 } 2572 2573 if (arm_is_el2_enabled(env)) { 2574 aa64 = aa64 && (env->cp15.hcr_el2 & HCR_RW); 2575 } 2576 2577 return aa64; 2578 } 2579 2580 /* Function for determining whether guest cp register reads and writes should 2581 * access the secure or non-secure bank of a cp register. When EL3 is 2582 * operating in AArch32 state, the NS-bit determines whether the secure 2583 * instance of a cp register should be used. When EL3 is AArch64 (or if 2584 * it doesn't exist at all) then there is no register banking, and all 2585 * accesses are to the non-secure version. 2586 */ 2587 static inline bool access_secure_reg(CPUARMState *env) 2588 { 2589 bool ret = (arm_feature(env, ARM_FEATURE_EL3) && 2590 !arm_el_is_aa64(env, 3) && 2591 !(env->cp15.scr_el3 & SCR_NS)); 2592 2593 return ret; 2594 } 2595 2596 /* Macros for accessing a specified CP register bank */ 2597 #define A32_BANKED_REG_GET(_env, _regname, _secure) \ 2598 ((_secure) ? (_env)->cp15._regname##_s : (_env)->cp15._regname##_ns) 2599 2600 #define A32_BANKED_REG_SET(_env, _regname, _secure, _val) \ 2601 do { \ 2602 if (_secure) { \ 2603 (_env)->cp15._regname##_s = (_val); \ 2604 } else { \ 2605 (_env)->cp15._regname##_ns = (_val); \ 2606 } \ 2607 } while (0) 2608 2609 /* Macros for automatically accessing a specific CP register bank depending on 2610 * the current secure state of the system. These macros are not intended for 2611 * supporting instruction translation reads/writes as these are dependent 2612 * solely on the SCR.NS bit and not the mode. 2613 */ 2614 #define A32_BANKED_CURRENT_REG_GET(_env, _regname) \ 2615 A32_BANKED_REG_GET((_env), _regname, \ 2616 (arm_is_secure(_env) && !arm_el_is_aa64((_env), 3))) 2617 2618 #define A32_BANKED_CURRENT_REG_SET(_env, _regname, _val) \ 2619 A32_BANKED_REG_SET((_env), _regname, \ 2620 (arm_is_secure(_env) && !arm_el_is_aa64((_env), 3)), \ 2621 (_val)) 2622 2623 uint32_t arm_phys_excp_target_el(CPUState *cs, uint32_t excp_idx, 2624 uint32_t cur_el, bool secure); 2625 2626 /* Return the highest implemented Exception Level */ 2627 static inline int arm_highest_el(CPUARMState *env) 2628 { 2629 if (arm_feature(env, ARM_FEATURE_EL3)) { 2630 return 3; 2631 } 2632 if (arm_feature(env, ARM_FEATURE_EL2)) { 2633 return 2; 2634 } 2635 return 1; 2636 } 2637 2638 /* Return true if a v7M CPU is in Handler mode */ 2639 static inline bool arm_v7m_is_handler_mode(CPUARMState *env) 2640 { 2641 return env->v7m.exception != 0; 2642 } 2643 2644 /* Return the current Exception Level (as per ARMv8; note that this differs 2645 * from the ARMv7 Privilege Level). 2646 */ 2647 static inline int arm_current_el(CPUARMState *env) 2648 { 2649 if (arm_feature(env, ARM_FEATURE_M)) { 2650 return arm_v7m_is_handler_mode(env) || 2651 !(env->v7m.control[env->v7m.secure] & 1); 2652 } 2653 2654 if (is_a64(env)) { 2655 return extract32(env->pstate, 2, 2); 2656 } 2657 2658 switch (env->uncached_cpsr & 0x1f) { 2659 case ARM_CPU_MODE_USR: 2660 return 0; 2661 case ARM_CPU_MODE_HYP: 2662 return 2; 2663 case ARM_CPU_MODE_MON: 2664 return 3; 2665 default: 2666 if (arm_is_secure(env) && !arm_el_is_aa64(env, 3)) { 2667 /* If EL3 is 32-bit then all secure privileged modes run in 2668 * EL3 2669 */ 2670 return 3; 2671 } 2672 2673 return 1; 2674 } 2675 } 2676 2677 /** 2678 * write_list_to_cpustate 2679 * @cpu: ARMCPU 2680 * 2681 * For each register listed in the ARMCPU cpreg_indexes list, write 2682 * its value from the cpreg_values list into the ARMCPUState structure. 2683 * This updates TCG's working data structures from KVM data or 2684 * from incoming migration state. 2685 * 2686 * Returns: true if all register values were updated correctly, 2687 * false if some register was unknown or could not be written. 2688 * Note that we do not stop early on failure -- we will attempt 2689 * writing all registers in the list. 2690 */ 2691 bool write_list_to_cpustate(ARMCPU *cpu); 2692 2693 /** 2694 * write_cpustate_to_list: 2695 * @cpu: ARMCPU 2696 * @kvm_sync: true if this is for syncing back to KVM 2697 * 2698 * For each register listed in the ARMCPU cpreg_indexes list, write 2699 * its value from the ARMCPUState structure into the cpreg_values list. 2700 * This is used to copy info from TCG's working data structures into 2701 * KVM or for outbound migration. 2702 * 2703 * @kvm_sync is true if we are doing this in order to sync the 2704 * register state back to KVM. In this case we will only update 2705 * values in the list if the previous list->cpustate sync actually 2706 * successfully wrote the CPU state. Otherwise we will keep the value 2707 * that is in the list. 2708 * 2709 * Returns: true if all register values were read correctly, 2710 * false if some register was unknown or could not be read. 2711 * Note that we do not stop early on failure -- we will attempt 2712 * reading all registers in the list. 2713 */ 2714 bool write_cpustate_to_list(ARMCPU *cpu, bool kvm_sync); 2715 2716 #define ARM_CPUID_TI915T 0x54029152 2717 #define ARM_CPUID_TI925T 0x54029252 2718 2719 #define CPU_RESOLVING_TYPE TYPE_ARM_CPU 2720 2721 #define TYPE_ARM_HOST_CPU "host-" TYPE_ARM_CPU 2722 2723 /* ARM has the following "translation regimes" (as the ARM ARM calls them): 2724 * 2725 * If EL3 is 64-bit: 2726 * + NonSecure EL1 & 0 stage 1 2727 * + NonSecure EL1 & 0 stage 2 2728 * + NonSecure EL2 2729 * + NonSecure EL2 & 0 (ARMv8.1-VHE) 2730 * + Secure EL1 & 0 2731 * + Secure EL3 2732 * If EL3 is 32-bit: 2733 * + NonSecure PL1 & 0 stage 1 2734 * + NonSecure PL1 & 0 stage 2 2735 * + NonSecure PL2 2736 * + Secure PL0 2737 * + Secure PL1 2738 * (reminder: for 32 bit EL3, Secure PL1 is *EL3*, not EL1.) 2739 * 2740 * For QEMU, an mmu_idx is not quite the same as a translation regime because: 2741 * 1. we need to split the "EL1 & 0" and "EL2 & 0" regimes into two mmu_idxes, 2742 * because they may differ in access permissions even if the VA->PA map is 2743 * the same 2744 * 2. we want to cache in our TLB the full VA->IPA->PA lookup for a stage 1+2 2745 * translation, which means that we have one mmu_idx that deals with two 2746 * concatenated translation regimes [this sort of combined s1+2 TLB is 2747 * architecturally permitted] 2748 * 3. we don't need to allocate an mmu_idx to translations that we won't be 2749 * handling via the TLB. The only way to do a stage 1 translation without 2750 * the immediate stage 2 translation is via the ATS or AT system insns, 2751 * which can be slow-pathed and always do a page table walk. 2752 * The only use of stage 2 translations is either as part of an s1+2 2753 * lookup or when loading the descriptors during a stage 1 page table walk, 2754 * and in both those cases we don't use the TLB. 2755 * 4. we can also safely fold together the "32 bit EL3" and "64 bit EL3" 2756 * translation regimes, because they map reasonably well to each other 2757 * and they can't both be active at the same time. 2758 * 5. we want to be able to use the TLB for accesses done as part of a 2759 * stage1 page table walk, rather than having to walk the stage2 page 2760 * table over and over. 2761 * 6. we need separate EL1/EL2 mmu_idx for handling the Privileged Access 2762 * Never (PAN) bit within PSTATE. 2763 * 7. we fold together the secure and non-secure regimes for A-profile, 2764 * because there are no banked system registers for aarch64, so the 2765 * process of switching between secure and non-secure is 2766 * already heavyweight. 2767 * 2768 * This gives us the following list of cases: 2769 * 2770 * EL0 EL1&0 stage 1+2 (aka NS PL0) 2771 * EL1 EL1&0 stage 1+2 (aka NS PL1) 2772 * EL1 EL1&0 stage 1+2 +PAN 2773 * EL0 EL2&0 2774 * EL2 EL2&0 2775 * EL2 EL2&0 +PAN 2776 * EL2 (aka NS PL2) 2777 * EL3 (aka S PL1) 2778 * Physical (NS & S) 2779 * Stage2 (NS & S) 2780 * 2781 * for a total of 12 different mmu_idx. 2782 * 2783 * R profile CPUs have an MPU, but can use the same set of MMU indexes 2784 * as A profile. They only need to distinguish EL0 and EL1 (and 2785 * EL2 if we ever model a Cortex-R52). 2786 * 2787 * M profile CPUs are rather different as they do not have a true MMU. 2788 * They have the following different MMU indexes: 2789 * User 2790 * Privileged 2791 * User, execution priority negative (ie the MPU HFNMIENA bit may apply) 2792 * Privileged, execution priority negative (ditto) 2793 * If the CPU supports the v8M Security Extension then there are also: 2794 * Secure User 2795 * Secure Privileged 2796 * Secure User, execution priority negative 2797 * Secure Privileged, execution priority negative 2798 * 2799 * The ARMMMUIdx and the mmu index value used by the core QEMU TLB code 2800 * are not quite the same -- different CPU types (most notably M profile 2801 * vs A/R profile) would like to use MMU indexes with different semantics, 2802 * but since we don't ever need to use all of those in a single CPU we 2803 * can avoid having to set NB_MMU_MODES to "total number of A profile MMU 2804 * modes + total number of M profile MMU modes". The lower bits of 2805 * ARMMMUIdx are the core TLB mmu index, and the higher bits are always 2806 * the same for any particular CPU. 2807 * Variables of type ARMMUIdx are always full values, and the core 2808 * index values are in variables of type 'int'. 2809 * 2810 * Our enumeration includes at the end some entries which are not "true" 2811 * mmu_idx values in that they don't have corresponding TLBs and are only 2812 * valid for doing slow path page table walks. 2813 * 2814 * The constant names here are patterned after the general style of the names 2815 * of the AT/ATS operations. 2816 * The values used are carefully arranged to make mmu_idx => EL lookup easy. 2817 * For M profile we arrange them to have a bit for priv, a bit for negpri 2818 * and a bit for secure. 2819 */ 2820 #define ARM_MMU_IDX_A 0x10 /* A profile */ 2821 #define ARM_MMU_IDX_NOTLB 0x20 /* does not have a TLB */ 2822 #define ARM_MMU_IDX_M 0x40 /* M profile */ 2823 2824 /* Meanings of the bits for M profile mmu idx values */ 2825 #define ARM_MMU_IDX_M_PRIV 0x1 2826 #define ARM_MMU_IDX_M_NEGPRI 0x2 2827 #define ARM_MMU_IDX_M_S 0x4 /* Secure */ 2828 2829 #define ARM_MMU_IDX_TYPE_MASK \ 2830 (ARM_MMU_IDX_A | ARM_MMU_IDX_M | ARM_MMU_IDX_NOTLB) 2831 #define ARM_MMU_IDX_COREIDX_MASK 0xf 2832 2833 typedef enum ARMMMUIdx { 2834 /* 2835 * A-profile. 2836 */ 2837 ARMMMUIdx_E10_0 = 0 | ARM_MMU_IDX_A, 2838 ARMMMUIdx_E20_0 = 1 | ARM_MMU_IDX_A, 2839 ARMMMUIdx_E10_1 = 2 | ARM_MMU_IDX_A, 2840 ARMMMUIdx_E20_2 = 3 | ARM_MMU_IDX_A, 2841 ARMMMUIdx_E10_1_PAN = 4 | ARM_MMU_IDX_A, 2842 ARMMMUIdx_E20_2_PAN = 5 | ARM_MMU_IDX_A, 2843 ARMMMUIdx_E2 = 6 | ARM_MMU_IDX_A, 2844 ARMMMUIdx_E3 = 7 | ARM_MMU_IDX_A, 2845 2846 /* 2847 * Used for second stage of an S12 page table walk, or for descriptor 2848 * loads during first stage of an S1 page table walk. Note that both 2849 * are in use simultaneously for SecureEL2: the security state for 2850 * the S2 ptw is selected by the NS bit from the S1 ptw. 2851 */ 2852 ARMMMUIdx_Stage2_S = 8 | ARM_MMU_IDX_A, 2853 ARMMMUIdx_Stage2 = 9 | ARM_MMU_IDX_A, 2854 2855 /* TLBs with 1-1 mapping to the physical address spaces. */ 2856 ARMMMUIdx_Phys_S = 10 | ARM_MMU_IDX_A, 2857 ARMMMUIdx_Phys_NS = 11 | ARM_MMU_IDX_A, 2858 ARMMMUIdx_Phys_Root = 12 | ARM_MMU_IDX_A, 2859 ARMMMUIdx_Phys_Realm = 13 | ARM_MMU_IDX_A, 2860 2861 /* 2862 * These are not allocated TLBs and are used only for AT system 2863 * instructions or for the first stage of an S12 page table walk. 2864 */ 2865 ARMMMUIdx_Stage1_E0 = 0 | ARM_MMU_IDX_NOTLB, 2866 ARMMMUIdx_Stage1_E1 = 1 | ARM_MMU_IDX_NOTLB, 2867 ARMMMUIdx_Stage1_E1_PAN = 2 | ARM_MMU_IDX_NOTLB, 2868 2869 /* 2870 * M-profile. 2871 */ 2872 ARMMMUIdx_MUser = ARM_MMU_IDX_M, 2873 ARMMMUIdx_MPriv = ARM_MMU_IDX_M | ARM_MMU_IDX_M_PRIV, 2874 ARMMMUIdx_MUserNegPri = ARMMMUIdx_MUser | ARM_MMU_IDX_M_NEGPRI, 2875 ARMMMUIdx_MPrivNegPri = ARMMMUIdx_MPriv | ARM_MMU_IDX_M_NEGPRI, 2876 ARMMMUIdx_MSUser = ARMMMUIdx_MUser | ARM_MMU_IDX_M_S, 2877 ARMMMUIdx_MSPriv = ARMMMUIdx_MPriv | ARM_MMU_IDX_M_S, 2878 ARMMMUIdx_MSUserNegPri = ARMMMUIdx_MUserNegPri | ARM_MMU_IDX_M_S, 2879 ARMMMUIdx_MSPrivNegPri = ARMMMUIdx_MPrivNegPri | ARM_MMU_IDX_M_S, 2880 } ARMMMUIdx; 2881 2882 /* 2883 * Bit macros for the core-mmu-index values for each index, 2884 * for use when calling tlb_flush_by_mmuidx() and friends. 2885 */ 2886 #define TO_CORE_BIT(NAME) \ 2887 ARMMMUIdxBit_##NAME = 1 << (ARMMMUIdx_##NAME & ARM_MMU_IDX_COREIDX_MASK) 2888 2889 typedef enum ARMMMUIdxBit { 2890 TO_CORE_BIT(E10_0), 2891 TO_CORE_BIT(E20_0), 2892 TO_CORE_BIT(E10_1), 2893 TO_CORE_BIT(E10_1_PAN), 2894 TO_CORE_BIT(E2), 2895 TO_CORE_BIT(E20_2), 2896 TO_CORE_BIT(E20_2_PAN), 2897 TO_CORE_BIT(E3), 2898 TO_CORE_BIT(Stage2), 2899 TO_CORE_BIT(Stage2_S), 2900 2901 TO_CORE_BIT(MUser), 2902 TO_CORE_BIT(MPriv), 2903 TO_CORE_BIT(MUserNegPri), 2904 TO_CORE_BIT(MPrivNegPri), 2905 TO_CORE_BIT(MSUser), 2906 TO_CORE_BIT(MSPriv), 2907 TO_CORE_BIT(MSUserNegPri), 2908 TO_CORE_BIT(MSPrivNegPri), 2909 } ARMMMUIdxBit; 2910 2911 #undef TO_CORE_BIT 2912 2913 #define MMU_USER_IDX 0 2914 2915 /* Indexes used when registering address spaces with cpu_address_space_init */ 2916 typedef enum ARMASIdx { 2917 ARMASIdx_NS = 0, 2918 ARMASIdx_S = 1, 2919 ARMASIdx_TagNS = 2, 2920 ARMASIdx_TagS = 3, 2921 } ARMASIdx; 2922 2923 static inline ARMMMUIdx arm_space_to_phys(ARMSecuritySpace space) 2924 { 2925 /* Assert the relative order of the physical mmu indexes. */ 2926 QEMU_BUILD_BUG_ON(ARMSS_Secure != 0); 2927 QEMU_BUILD_BUG_ON(ARMMMUIdx_Phys_NS != ARMMMUIdx_Phys_S + ARMSS_NonSecure); 2928 QEMU_BUILD_BUG_ON(ARMMMUIdx_Phys_Root != ARMMMUIdx_Phys_S + ARMSS_Root); 2929 QEMU_BUILD_BUG_ON(ARMMMUIdx_Phys_Realm != ARMMMUIdx_Phys_S + ARMSS_Realm); 2930 2931 return ARMMMUIdx_Phys_S + space; 2932 } 2933 2934 static inline ARMSecuritySpace arm_phys_to_space(ARMMMUIdx idx) 2935 { 2936 assert(idx >= ARMMMUIdx_Phys_S && idx <= ARMMMUIdx_Phys_Realm); 2937 return idx - ARMMMUIdx_Phys_S; 2938 } 2939 2940 static inline bool arm_v7m_csselr_razwi(ARMCPU *cpu) 2941 { 2942 /* If all the CLIDR.Ctypem bits are 0 there are no caches, and 2943 * CSSELR is RAZ/WI. 2944 */ 2945 return (cpu->clidr & R_V7M_CLIDR_CTYPE_ALL_MASK) != 0; 2946 } 2947 2948 static inline bool arm_sctlr_b(CPUARMState *env) 2949 { 2950 return 2951 /* We need not implement SCTLR.ITD in user-mode emulation, so 2952 * let linux-user ignore the fact that it conflicts with SCTLR_B. 2953 * This lets people run BE32 binaries with "-cpu any". 2954 */ 2955 #ifndef CONFIG_USER_ONLY 2956 !arm_feature(env, ARM_FEATURE_V7) && 2957 #endif 2958 (env->cp15.sctlr_el[1] & SCTLR_B) != 0; 2959 } 2960 2961 uint64_t arm_sctlr(CPUARMState *env, int el); 2962 2963 static inline bool arm_cpu_data_is_big_endian_a32(CPUARMState *env, 2964 bool sctlr_b) 2965 { 2966 #ifdef CONFIG_USER_ONLY 2967 /* 2968 * In system mode, BE32 is modelled in line with the 2969 * architecture (as word-invariant big-endianness), where loads 2970 * and stores are done little endian but from addresses which 2971 * are adjusted by XORing with the appropriate constant. So the 2972 * endianness to use for the raw data access is not affected by 2973 * SCTLR.B. 2974 * In user mode, however, we model BE32 as byte-invariant 2975 * big-endianness (because user-only code cannot tell the 2976 * difference), and so we need to use a data access endianness 2977 * that depends on SCTLR.B. 2978 */ 2979 if (sctlr_b) { 2980 return true; 2981 } 2982 #endif 2983 /* In 32bit endianness is determined by looking at CPSR's E bit */ 2984 return env->uncached_cpsr & CPSR_E; 2985 } 2986 2987 static inline bool arm_cpu_data_is_big_endian_a64(int el, uint64_t sctlr) 2988 { 2989 return sctlr & (el ? SCTLR_EE : SCTLR_E0E); 2990 } 2991 2992 /* Return true if the processor is in big-endian mode. */ 2993 static inline bool arm_cpu_data_is_big_endian(CPUARMState *env) 2994 { 2995 if (!is_a64(env)) { 2996 return arm_cpu_data_is_big_endian_a32(env, arm_sctlr_b(env)); 2997 } else { 2998 int cur_el = arm_current_el(env); 2999 uint64_t sctlr = arm_sctlr(env, cur_el); 3000 return arm_cpu_data_is_big_endian_a64(cur_el, sctlr); 3001 } 3002 } 3003 3004 #include "exec/cpu-all.h" 3005 3006 /* 3007 * We have more than 32-bits worth of state per TB, so we split the data 3008 * between tb->flags and tb->cs_base, which is otherwise unused for ARM. 3009 * We collect these two parts in CPUARMTBFlags where they are named 3010 * flags and flags2 respectively. 3011 * 3012 * The flags that are shared between all execution modes, TBFLAG_ANY, 3013 * are stored in flags. The flags that are specific to a given mode 3014 * are stores in flags2. Since cs_base is sized on the configured 3015 * address size, flags2 always has 64-bits for A64, and a minimum of 3016 * 32-bits for A32 and M32. 3017 * 3018 * The bits for 32-bit A-profile and M-profile partially overlap: 3019 * 3020 * 31 23 11 10 0 3021 * +-------------+----------+----------------+ 3022 * | | | TBFLAG_A32 | 3023 * | TBFLAG_AM32 | +-----+----------+ 3024 * | | |TBFLAG_M32| 3025 * +-------------+----------------+----------+ 3026 * 31 23 6 5 0 3027 * 3028 * Unless otherwise noted, these bits are cached in env->hflags. 3029 */ 3030 FIELD(TBFLAG_ANY, AARCH64_STATE, 0, 1) 3031 FIELD(TBFLAG_ANY, SS_ACTIVE, 1, 1) 3032 FIELD(TBFLAG_ANY, PSTATE__SS, 2, 1) /* Not cached. */ 3033 FIELD(TBFLAG_ANY, BE_DATA, 3, 1) 3034 FIELD(TBFLAG_ANY, MMUIDX, 4, 4) 3035 /* Target EL if we take a floating-point-disabled exception */ 3036 FIELD(TBFLAG_ANY, FPEXC_EL, 8, 2) 3037 /* Memory operations require alignment: SCTLR_ELx.A or CCR.UNALIGN_TRP */ 3038 FIELD(TBFLAG_ANY, ALIGN_MEM, 10, 1) 3039 FIELD(TBFLAG_ANY, PSTATE__IL, 11, 1) 3040 FIELD(TBFLAG_ANY, FGT_ACTIVE, 12, 1) 3041 FIELD(TBFLAG_ANY, FGT_SVC, 13, 1) 3042 3043 /* 3044 * Bit usage when in AArch32 state, both A- and M-profile. 3045 */ 3046 FIELD(TBFLAG_AM32, CONDEXEC, 24, 8) /* Not cached. */ 3047 FIELD(TBFLAG_AM32, THUMB, 23, 1) /* Not cached. */ 3048 3049 /* 3050 * Bit usage when in AArch32 state, for A-profile only. 3051 */ 3052 FIELD(TBFLAG_A32, VECLEN, 0, 3) /* Not cached. */ 3053 FIELD(TBFLAG_A32, VECSTRIDE, 3, 2) /* Not cached. */ 3054 /* 3055 * We store the bottom two bits of the CPAR as TB flags and handle 3056 * checks on the other bits at runtime. This shares the same bits as 3057 * VECSTRIDE, which is OK as no XScale CPU has VFP. 3058 * Not cached, because VECLEN+VECSTRIDE are not cached. 3059 */ 3060 FIELD(TBFLAG_A32, XSCALE_CPAR, 5, 2) 3061 FIELD(TBFLAG_A32, VFPEN, 7, 1) /* Partially cached, minus FPEXC. */ 3062 FIELD(TBFLAG_A32, SCTLR__B, 8, 1) /* Cannot overlap with SCTLR_B */ 3063 FIELD(TBFLAG_A32, HSTR_ACTIVE, 9, 1) 3064 /* 3065 * Indicates whether cp register reads and writes by guest code should access 3066 * the secure or nonsecure bank of banked registers; note that this is not 3067 * the same thing as the current security state of the processor! 3068 */ 3069 FIELD(TBFLAG_A32, NS, 10, 1) 3070 /* 3071 * Indicates that SME Streaming mode is active, and SMCR_ELx.FA64 is not. 3072 * This requires an SME trap from AArch32 mode when using NEON. 3073 */ 3074 FIELD(TBFLAG_A32, SME_TRAP_NONSTREAMING, 11, 1) 3075 3076 /* 3077 * Bit usage when in AArch32 state, for M-profile only. 3078 */ 3079 /* Handler (ie not Thread) mode */ 3080 FIELD(TBFLAG_M32, HANDLER, 0, 1) 3081 /* Whether we should generate stack-limit checks */ 3082 FIELD(TBFLAG_M32, STACKCHECK, 1, 1) 3083 /* Set if FPCCR.LSPACT is set */ 3084 FIELD(TBFLAG_M32, LSPACT, 2, 1) /* Not cached. */ 3085 /* Set if we must create a new FP context */ 3086 FIELD(TBFLAG_M32, NEW_FP_CTXT_NEEDED, 3, 1) /* Not cached. */ 3087 /* Set if FPCCR.S does not match current security state */ 3088 FIELD(TBFLAG_M32, FPCCR_S_WRONG, 4, 1) /* Not cached. */ 3089 /* Set if MVE insns are definitely not predicated by VPR or LTPSIZE */ 3090 FIELD(TBFLAG_M32, MVE_NO_PRED, 5, 1) /* Not cached. */ 3091 /* Set if in secure mode */ 3092 FIELD(TBFLAG_M32, SECURE, 6, 1) 3093 3094 /* 3095 * Bit usage when in AArch64 state 3096 */ 3097 FIELD(TBFLAG_A64, TBII, 0, 2) 3098 FIELD(TBFLAG_A64, SVEEXC_EL, 2, 2) 3099 /* The current vector length, either NVL or SVL. */ 3100 FIELD(TBFLAG_A64, VL, 4, 4) 3101 FIELD(TBFLAG_A64, PAUTH_ACTIVE, 8, 1) 3102 FIELD(TBFLAG_A64, BT, 9, 1) 3103 FIELD(TBFLAG_A64, BTYPE, 10, 2) /* Not cached. */ 3104 FIELD(TBFLAG_A64, TBID, 12, 2) 3105 FIELD(TBFLAG_A64, UNPRIV, 14, 1) 3106 FIELD(TBFLAG_A64, ATA, 15, 1) 3107 FIELD(TBFLAG_A64, TCMA, 16, 2) 3108 FIELD(TBFLAG_A64, MTE_ACTIVE, 18, 1) 3109 FIELD(TBFLAG_A64, MTE0_ACTIVE, 19, 1) 3110 FIELD(TBFLAG_A64, SMEEXC_EL, 20, 2) 3111 FIELD(TBFLAG_A64, PSTATE_SM, 22, 1) 3112 FIELD(TBFLAG_A64, PSTATE_ZA, 23, 1) 3113 FIELD(TBFLAG_A64, SVL, 24, 4) 3114 /* Indicates that SME Streaming mode is active, and SMCR_ELx.FA64 is not. */ 3115 FIELD(TBFLAG_A64, SME_TRAP_NONSTREAMING, 28, 1) 3116 FIELD(TBFLAG_A64, TRAP_ERET, 29, 1) 3117 FIELD(TBFLAG_A64, NAA, 30, 1) 3118 FIELD(TBFLAG_A64, ATA0, 31, 1) 3119 FIELD(TBFLAG_A64, NV, 32, 1) 3120 FIELD(TBFLAG_A64, NV1, 33, 1) 3121 FIELD(TBFLAG_A64, NV2, 34, 1) 3122 /* Set if FEAT_NV2 RAM accesses use the EL2&0 translation regime */ 3123 FIELD(TBFLAG_A64, NV2_MEM_E20, 35, 1) 3124 /* Set if FEAT_NV2 RAM accesses are big-endian */ 3125 FIELD(TBFLAG_A64, NV2_MEM_BE, 36, 1) 3126 3127 /* 3128 * Helpers for using the above. Note that only the A64 accessors use 3129 * FIELD_DP64() and FIELD_EX64(), because in the other cases the flags 3130 * word either is or might be 32 bits only. 3131 */ 3132 #define DP_TBFLAG_ANY(DST, WHICH, VAL) \ 3133 (DST.flags = FIELD_DP32(DST.flags, TBFLAG_ANY, WHICH, VAL)) 3134 #define DP_TBFLAG_A64(DST, WHICH, VAL) \ 3135 (DST.flags2 = FIELD_DP64(DST.flags2, TBFLAG_A64, WHICH, VAL)) 3136 #define DP_TBFLAG_A32(DST, WHICH, VAL) \ 3137 (DST.flags2 = FIELD_DP32(DST.flags2, TBFLAG_A32, WHICH, VAL)) 3138 #define DP_TBFLAG_M32(DST, WHICH, VAL) \ 3139 (DST.flags2 = FIELD_DP32(DST.flags2, TBFLAG_M32, WHICH, VAL)) 3140 #define DP_TBFLAG_AM32(DST, WHICH, VAL) \ 3141 (DST.flags2 = FIELD_DP32(DST.flags2, TBFLAG_AM32, WHICH, VAL)) 3142 3143 #define EX_TBFLAG_ANY(IN, WHICH) FIELD_EX32(IN.flags, TBFLAG_ANY, WHICH) 3144 #define EX_TBFLAG_A64(IN, WHICH) FIELD_EX64(IN.flags2, TBFLAG_A64, WHICH) 3145 #define EX_TBFLAG_A32(IN, WHICH) FIELD_EX32(IN.flags2, TBFLAG_A32, WHICH) 3146 #define EX_TBFLAG_M32(IN, WHICH) FIELD_EX32(IN.flags2, TBFLAG_M32, WHICH) 3147 #define EX_TBFLAG_AM32(IN, WHICH) FIELD_EX32(IN.flags2, TBFLAG_AM32, WHICH) 3148 3149 /** 3150 * sve_vq 3151 * @env: the cpu context 3152 * 3153 * Return the VL cached within env->hflags, in units of quadwords. 3154 */ 3155 static inline int sve_vq(CPUARMState *env) 3156 { 3157 return EX_TBFLAG_A64(env->hflags, VL) + 1; 3158 } 3159 3160 /** 3161 * sme_vq 3162 * @env: the cpu context 3163 * 3164 * Return the SVL cached within env->hflags, in units of quadwords. 3165 */ 3166 static inline int sme_vq(CPUARMState *env) 3167 { 3168 return EX_TBFLAG_A64(env->hflags, SVL) + 1; 3169 } 3170 3171 static inline bool bswap_code(bool sctlr_b) 3172 { 3173 #ifdef CONFIG_USER_ONLY 3174 /* BE8 (SCTLR.B = 0, TARGET_BIG_ENDIAN = 1) is mixed endian. 3175 * The invalid combination SCTLR.B=1/CPSR.E=1/TARGET_BIG_ENDIAN=0 3176 * would also end up as a mixed-endian mode with BE code, LE data. 3177 */ 3178 return TARGET_BIG_ENDIAN ^ sctlr_b; 3179 #else 3180 /* All code access in ARM is little endian, and there are no loaders 3181 * doing swaps that need to be reversed 3182 */ 3183 return 0; 3184 #endif 3185 } 3186 3187 #ifdef CONFIG_USER_ONLY 3188 static inline bool arm_cpu_bswap_data(CPUARMState *env) 3189 { 3190 return TARGET_BIG_ENDIAN ^ arm_cpu_data_is_big_endian(env); 3191 } 3192 #endif 3193 3194 void cpu_get_tb_cpu_state(CPUARMState *env, vaddr *pc, 3195 uint64_t *cs_base, uint32_t *flags); 3196 3197 enum { 3198 QEMU_PSCI_CONDUIT_DISABLED = 0, 3199 QEMU_PSCI_CONDUIT_SMC = 1, 3200 QEMU_PSCI_CONDUIT_HVC = 2, 3201 }; 3202 3203 #ifndef CONFIG_USER_ONLY 3204 /* Return the address space index to use for a memory access */ 3205 static inline int arm_asidx_from_attrs(CPUState *cs, MemTxAttrs attrs) 3206 { 3207 return attrs.secure ? ARMASIdx_S : ARMASIdx_NS; 3208 } 3209 3210 /* Return the AddressSpace to use for a memory access 3211 * (which depends on whether the access is S or NS, and whether 3212 * the board gave us a separate AddressSpace for S accesses). 3213 */ 3214 static inline AddressSpace *arm_addressspace(CPUState *cs, MemTxAttrs attrs) 3215 { 3216 return cpu_get_address_space(cs, arm_asidx_from_attrs(cs, attrs)); 3217 } 3218 #endif 3219 3220 /** 3221 * arm_register_pre_el_change_hook: 3222 * Register a hook function which will be called immediately before this 3223 * CPU changes exception level or mode. The hook function will be 3224 * passed a pointer to the ARMCPU and the opaque data pointer passed 3225 * to this function when the hook was registered. 3226 * 3227 * Note that if a pre-change hook is called, any registered post-change hooks 3228 * are guaranteed to subsequently be called. 3229 */ 3230 void arm_register_pre_el_change_hook(ARMCPU *cpu, ARMELChangeHookFn *hook, 3231 void *opaque); 3232 /** 3233 * arm_register_el_change_hook: 3234 * Register a hook function which will be called immediately after this 3235 * CPU changes exception level or mode. The hook function will be 3236 * passed a pointer to the ARMCPU and the opaque data pointer passed 3237 * to this function when the hook was registered. 3238 * 3239 * Note that any registered hooks registered here are guaranteed to be called 3240 * if pre-change hooks have been. 3241 */ 3242 void arm_register_el_change_hook(ARMCPU *cpu, ARMELChangeHookFn *hook, void 3243 *opaque); 3244 3245 /** 3246 * arm_rebuild_hflags: 3247 * Rebuild the cached TBFLAGS for arbitrary changed processor state. 3248 */ 3249 void arm_rebuild_hflags(CPUARMState *env); 3250 3251 /** 3252 * aa32_vfp_dreg: 3253 * Return a pointer to the Dn register within env in 32-bit mode. 3254 */ 3255 static inline uint64_t *aa32_vfp_dreg(CPUARMState *env, unsigned regno) 3256 { 3257 return &env->vfp.zregs[regno >> 1].d[regno & 1]; 3258 } 3259 3260 /** 3261 * aa32_vfp_qreg: 3262 * Return a pointer to the Qn register within env in 32-bit mode. 3263 */ 3264 static inline uint64_t *aa32_vfp_qreg(CPUARMState *env, unsigned regno) 3265 { 3266 return &env->vfp.zregs[regno].d[0]; 3267 } 3268 3269 /** 3270 * aa64_vfp_qreg: 3271 * Return a pointer to the Qn register within env in 64-bit mode. 3272 */ 3273 static inline uint64_t *aa64_vfp_qreg(CPUARMState *env, unsigned regno) 3274 { 3275 return &env->vfp.zregs[regno].d[0]; 3276 } 3277 3278 /* Shared between translate-sve.c and sve_helper.c. */ 3279 extern const uint64_t pred_esz_masks[5]; 3280 3281 /* 3282 * AArch64 usage of the PAGE_TARGET_* bits for linux-user. 3283 * Note that with the Linux kernel, PROT_MTE may not be cleared by mprotect 3284 * mprotect but PROT_BTI may be cleared. C.f. the kernel's VM_ARCH_CLEAR. 3285 */ 3286 #define PAGE_BTI PAGE_TARGET_1 3287 #define PAGE_MTE PAGE_TARGET_2 3288 #define PAGE_TARGET_STICKY PAGE_MTE 3289 3290 /* We associate one allocation tag per 16 bytes, the minimum. */ 3291 #define LOG2_TAG_GRANULE 4 3292 #define TAG_GRANULE (1 << LOG2_TAG_GRANULE) 3293 3294 #ifdef CONFIG_USER_ONLY 3295 #define TARGET_PAGE_DATA_SIZE (TARGET_PAGE_SIZE >> (LOG2_TAG_GRANULE + 1)) 3296 #endif 3297 3298 #ifdef TARGET_TAGGED_ADDRESSES 3299 /** 3300 * cpu_untagged_addr: 3301 * @cs: CPU context 3302 * @x: tagged address 3303 * 3304 * Remove any address tag from @x. This is explicitly related to the 3305 * linux syscall TIF_TAGGED_ADDR setting, not TBI in general. 3306 * 3307 * There should be a better place to put this, but we need this in 3308 * include/exec/cpu_ldst.h, and not some place linux-user specific. 3309 */ 3310 static inline target_ulong cpu_untagged_addr(CPUState *cs, target_ulong x) 3311 { 3312 ARMCPU *cpu = ARM_CPU(cs); 3313 if (cpu->env.tagged_addr_enable) { 3314 /* 3315 * TBI is enabled for userspace but not kernelspace addresses. 3316 * Only clear the tag if bit 55 is clear. 3317 */ 3318 x &= sextract64(x, 0, 56); 3319 } 3320 return x; 3321 } 3322 #endif 3323 3324 #endif 3325