1 /* 2 * ARM virtual CPU header 3 * 4 * Copyright (c) 2003 Fabrice Bellard 5 * 6 * This library is free software; you can redistribute it and/or 7 * modify it under the terms of the GNU Lesser General Public 8 * License as published by the Free Software Foundation; either 9 * version 2 of the License, or (at your option) any later version. 10 * 11 * This library is distributed in the hope that it will be useful, 12 * but WITHOUT ANY WARRANTY; without even the implied warranty of 13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU 14 * Lesser General Public License for more details. 15 * 16 * You should have received a copy of the GNU Lesser General Public 17 * License along with this library; if not, see <http://www.gnu.org/licenses/>. 18 */ 19 20 #ifndef ARM_CPU_H 21 #define ARM_CPU_H 22 23 #include "kvm-consts.h" 24 #include "hw/registerfields.h" 25 26 #if defined(TARGET_AARCH64) 27 /* AArch64 definitions */ 28 # define TARGET_LONG_BITS 64 29 #else 30 # define TARGET_LONG_BITS 32 31 #endif 32 33 /* ARM processors have a weak memory model */ 34 #define TCG_GUEST_DEFAULT_MO (0) 35 36 #define CPUArchState struct CPUARMState 37 38 #include "qemu-common.h" 39 #include "cpu-qom.h" 40 #include "exec/cpu-defs.h" 41 42 #define EXCP_UDEF 1 /* undefined instruction */ 43 #define EXCP_SWI 2 /* software interrupt */ 44 #define EXCP_PREFETCH_ABORT 3 45 #define EXCP_DATA_ABORT 4 46 #define EXCP_IRQ 5 47 #define EXCP_FIQ 6 48 #define EXCP_BKPT 7 49 #define EXCP_EXCEPTION_EXIT 8 /* Return from v7M exception. */ 50 #define EXCP_KERNEL_TRAP 9 /* Jumped to kernel code page. */ 51 #define EXCP_HVC 11 /* HyperVisor Call */ 52 #define EXCP_HYP_TRAP 12 53 #define EXCP_SMC 13 /* Secure Monitor Call */ 54 #define EXCP_VIRQ 14 55 #define EXCP_VFIQ 15 56 #define EXCP_SEMIHOST 16 /* semihosting call */ 57 #define EXCP_NOCP 17 /* v7M NOCP UsageFault */ 58 #define EXCP_INVSTATE 18 /* v7M INVSTATE UsageFault */ 59 #define EXCP_STKOF 19 /* v8M STKOF UsageFault */ 60 #define EXCP_LAZYFP 20 /* v7M fault during lazy FP stacking */ 61 #define EXCP_LSERR 21 /* v8M LSERR SecureFault */ 62 #define EXCP_UNALIGNED 22 /* v7M UNALIGNED UsageFault */ 63 /* NB: add new EXCP_ defines to the array in arm_log_exception() too */ 64 65 #define ARMV7M_EXCP_RESET 1 66 #define ARMV7M_EXCP_NMI 2 67 #define ARMV7M_EXCP_HARD 3 68 #define ARMV7M_EXCP_MEM 4 69 #define ARMV7M_EXCP_BUS 5 70 #define ARMV7M_EXCP_USAGE 6 71 #define ARMV7M_EXCP_SECURE 7 72 #define ARMV7M_EXCP_SVC 11 73 #define ARMV7M_EXCP_DEBUG 12 74 #define ARMV7M_EXCP_PENDSV 14 75 #define ARMV7M_EXCP_SYSTICK 15 76 77 /* For M profile, some registers are banked secure vs non-secure; 78 * these are represented as a 2-element array where the first element 79 * is the non-secure copy and the second is the secure copy. 80 * When the CPU does not have implement the security extension then 81 * only the first element is used. 82 * This means that the copy for the current security state can be 83 * accessed via env->registerfield[env->v7m.secure] (whether the security 84 * extension is implemented or not). 85 */ 86 enum { 87 M_REG_NS = 0, 88 M_REG_S = 1, 89 M_REG_NUM_BANKS = 2, 90 }; 91 92 /* ARM-specific interrupt pending bits. */ 93 #define CPU_INTERRUPT_FIQ CPU_INTERRUPT_TGT_EXT_1 94 #define CPU_INTERRUPT_VIRQ CPU_INTERRUPT_TGT_EXT_2 95 #define CPU_INTERRUPT_VFIQ CPU_INTERRUPT_TGT_EXT_3 96 97 /* The usual mapping for an AArch64 system register to its AArch32 98 * counterpart is for the 32 bit world to have access to the lower 99 * half only (with writes leaving the upper half untouched). It's 100 * therefore useful to be able to pass TCG the offset of the least 101 * significant half of a uint64_t struct member. 102 */ 103 #ifdef HOST_WORDS_BIGENDIAN 104 #define offsetoflow32(S, M) (offsetof(S, M) + sizeof(uint32_t)) 105 #define offsetofhigh32(S, M) offsetof(S, M) 106 #else 107 #define offsetoflow32(S, M) offsetof(S, M) 108 #define offsetofhigh32(S, M) (offsetof(S, M) + sizeof(uint32_t)) 109 #endif 110 111 /* Meanings of the ARMCPU object's four inbound GPIO lines */ 112 #define ARM_CPU_IRQ 0 113 #define ARM_CPU_FIQ 1 114 #define ARM_CPU_VIRQ 2 115 #define ARM_CPU_VFIQ 3 116 117 #define NB_MMU_MODES 8 118 /* ARM-specific extra insn start words: 119 * 1: Conditional execution bits 120 * 2: Partial exception syndrome for data aborts 121 */ 122 #define TARGET_INSN_START_EXTRA_WORDS 2 123 124 /* The 2nd extra word holding syndrome info for data aborts does not use 125 * the upper 6 bits nor the lower 14 bits. We mask and shift it down to 126 * help the sleb128 encoder do a better job. 127 * When restoring the CPU state, we shift it back up. 128 */ 129 #define ARM_INSN_START_WORD2_MASK ((1 << 26) - 1) 130 #define ARM_INSN_START_WORD2_SHIFT 14 131 132 /* We currently assume float and double are IEEE single and double 133 precision respectively. 134 Doing runtime conversions is tricky because VFP registers may contain 135 integer values (eg. as the result of a FTOSI instruction). 136 s<2n> maps to the least significant half of d<n> 137 s<2n+1> maps to the most significant half of d<n> 138 */ 139 140 /** 141 * DynamicGDBXMLInfo: 142 * @desc: Contains the XML descriptions. 143 * @num_cpregs: Number of the Coprocessor registers seen by GDB. 144 * @cpregs_keys: Array that contains the corresponding Key of 145 * a given cpreg with the same order of the cpreg in the XML description. 146 */ 147 typedef struct DynamicGDBXMLInfo { 148 char *desc; 149 int num_cpregs; 150 uint32_t *cpregs_keys; 151 } DynamicGDBXMLInfo; 152 153 /* CPU state for each instance of a generic timer (in cp15 c14) */ 154 typedef struct ARMGenericTimer { 155 uint64_t cval; /* Timer CompareValue register */ 156 uint64_t ctl; /* Timer Control register */ 157 } ARMGenericTimer; 158 159 #define GTIMER_PHYS 0 160 #define GTIMER_VIRT 1 161 #define GTIMER_HYP 2 162 #define GTIMER_SEC 3 163 #define NUM_GTIMERS 4 164 165 typedef struct { 166 uint64_t raw_tcr; 167 uint32_t mask; 168 uint32_t base_mask; 169 } TCR; 170 171 /* Define a maximum sized vector register. 172 * For 32-bit, this is a 128-bit NEON/AdvSIMD register. 173 * For 64-bit, this is a 2048-bit SVE register. 174 * 175 * Note that the mapping between S, D, and Q views of the register bank 176 * differs between AArch64 and AArch32. 177 * In AArch32: 178 * Qn = regs[n].d[1]:regs[n].d[0] 179 * Dn = regs[n / 2].d[n & 1] 180 * Sn = regs[n / 4].d[n % 4 / 2], 181 * bits 31..0 for even n, and bits 63..32 for odd n 182 * (and regs[16] to regs[31] are inaccessible) 183 * In AArch64: 184 * Zn = regs[n].d[*] 185 * Qn = regs[n].d[1]:regs[n].d[0] 186 * Dn = regs[n].d[0] 187 * Sn = regs[n].d[0] bits 31..0 188 * Hn = regs[n].d[0] bits 15..0 189 * 190 * This corresponds to the architecturally defined mapping between 191 * the two execution states, and means we do not need to explicitly 192 * map these registers when changing states. 193 * 194 * Align the data for use with TCG host vector operations. 195 */ 196 197 #ifdef TARGET_AARCH64 198 # define ARM_MAX_VQ 16 199 #else 200 # define ARM_MAX_VQ 1 201 #endif 202 203 typedef struct ARMVectorReg { 204 uint64_t d[2 * ARM_MAX_VQ] QEMU_ALIGNED(16); 205 } ARMVectorReg; 206 207 #ifdef TARGET_AARCH64 208 /* In AArch32 mode, predicate registers do not exist at all. */ 209 typedef struct ARMPredicateReg { 210 uint64_t p[2 * ARM_MAX_VQ / 8] QEMU_ALIGNED(16); 211 } ARMPredicateReg; 212 213 /* In AArch32 mode, PAC keys do not exist at all. */ 214 typedef struct ARMPACKey { 215 uint64_t lo, hi; 216 } ARMPACKey; 217 #endif 218 219 220 typedef struct CPUARMState { 221 /* Regs for current mode. */ 222 uint32_t regs[16]; 223 224 /* 32/64 switch only happens when taking and returning from 225 * exceptions so the overlap semantics are taken care of then 226 * instead of having a complicated union. 227 */ 228 /* Regs for A64 mode. */ 229 uint64_t xregs[32]; 230 uint64_t pc; 231 /* PSTATE isn't an architectural register for ARMv8. However, it is 232 * convenient for us to assemble the underlying state into a 32 bit format 233 * identical to the architectural format used for the SPSR. (This is also 234 * what the Linux kernel's 'pstate' field in signal handlers and KVM's 235 * 'pstate' register are.) Of the PSTATE bits: 236 * NZCV are kept in the split out env->CF/VF/NF/ZF, (which have the same 237 * semantics as for AArch32, as described in the comments on each field) 238 * nRW (also known as M[4]) is kept, inverted, in env->aarch64 239 * DAIF (exception masks) are kept in env->daif 240 * BTYPE is kept in env->btype 241 * all other bits are stored in their correct places in env->pstate 242 */ 243 uint32_t pstate; 244 uint32_t aarch64; /* 1 if CPU is in aarch64 state; inverse of PSTATE.nRW */ 245 246 /* Frequently accessed CPSR bits are stored separately for efficiency. 247 This contains all the other bits. Use cpsr_{read,write} to access 248 the whole CPSR. */ 249 uint32_t uncached_cpsr; 250 uint32_t spsr; 251 252 /* Banked registers. */ 253 uint64_t banked_spsr[8]; 254 uint32_t banked_r13[8]; 255 uint32_t banked_r14[8]; 256 257 /* These hold r8-r12. */ 258 uint32_t usr_regs[5]; 259 uint32_t fiq_regs[5]; 260 261 /* cpsr flag cache for faster execution */ 262 uint32_t CF; /* 0 or 1 */ 263 uint32_t VF; /* V is the bit 31. All other bits are undefined */ 264 uint32_t NF; /* N is bit 31. All other bits are undefined. */ 265 uint32_t ZF; /* Z set if zero. */ 266 uint32_t QF; /* 0 or 1 */ 267 uint32_t GE; /* cpsr[19:16] */ 268 uint32_t thumb; /* cpsr[5]. 0 = arm mode, 1 = thumb mode. */ 269 uint32_t condexec_bits; /* IT bits. cpsr[15:10,26:25]. */ 270 uint32_t btype; /* BTI branch type. spsr[11:10]. */ 271 uint64_t daif; /* exception masks, in the bits they are in PSTATE */ 272 273 uint64_t elr_el[4]; /* AArch64 exception link regs */ 274 uint64_t sp_el[4]; /* AArch64 banked stack pointers */ 275 276 /* System control coprocessor (cp15) */ 277 struct { 278 uint32_t c0_cpuid; 279 union { /* Cache size selection */ 280 struct { 281 uint64_t _unused_csselr0; 282 uint64_t csselr_ns; 283 uint64_t _unused_csselr1; 284 uint64_t csselr_s; 285 }; 286 uint64_t csselr_el[4]; 287 }; 288 union { /* System control register. */ 289 struct { 290 uint64_t _unused_sctlr; 291 uint64_t sctlr_ns; 292 uint64_t hsctlr; 293 uint64_t sctlr_s; 294 }; 295 uint64_t sctlr_el[4]; 296 }; 297 uint64_t cpacr_el1; /* Architectural feature access control register */ 298 uint64_t cptr_el[4]; /* ARMv8 feature trap registers */ 299 uint32_t c1_xscaleauxcr; /* XScale auxiliary control register. */ 300 uint64_t sder; /* Secure debug enable register. */ 301 uint32_t nsacr; /* Non-secure access control register. */ 302 union { /* MMU translation table base 0. */ 303 struct { 304 uint64_t _unused_ttbr0_0; 305 uint64_t ttbr0_ns; 306 uint64_t _unused_ttbr0_1; 307 uint64_t ttbr0_s; 308 }; 309 uint64_t ttbr0_el[4]; 310 }; 311 union { /* MMU translation table base 1. */ 312 struct { 313 uint64_t _unused_ttbr1_0; 314 uint64_t ttbr1_ns; 315 uint64_t _unused_ttbr1_1; 316 uint64_t ttbr1_s; 317 }; 318 uint64_t ttbr1_el[4]; 319 }; 320 uint64_t vttbr_el2; /* Virtualization Translation Table Base. */ 321 /* MMU translation table base control. */ 322 TCR tcr_el[4]; 323 TCR vtcr_el2; /* Virtualization Translation Control. */ 324 uint32_t c2_data; /* MPU data cacheable bits. */ 325 uint32_t c2_insn; /* MPU instruction cacheable bits. */ 326 union { /* MMU domain access control register 327 * MPU write buffer control. 328 */ 329 struct { 330 uint64_t dacr_ns; 331 uint64_t dacr_s; 332 }; 333 struct { 334 uint64_t dacr32_el2; 335 }; 336 }; 337 uint32_t pmsav5_data_ap; /* PMSAv5 MPU data access permissions */ 338 uint32_t pmsav5_insn_ap; /* PMSAv5 MPU insn access permissions */ 339 uint64_t hcr_el2; /* Hypervisor configuration register */ 340 uint64_t scr_el3; /* Secure configuration register. */ 341 union { /* Fault status registers. */ 342 struct { 343 uint64_t ifsr_ns; 344 uint64_t ifsr_s; 345 }; 346 struct { 347 uint64_t ifsr32_el2; 348 }; 349 }; 350 union { 351 struct { 352 uint64_t _unused_dfsr; 353 uint64_t dfsr_ns; 354 uint64_t hsr; 355 uint64_t dfsr_s; 356 }; 357 uint64_t esr_el[4]; 358 }; 359 uint32_t c6_region[8]; /* MPU base/size registers. */ 360 union { /* Fault address registers. */ 361 struct { 362 uint64_t _unused_far0; 363 #ifdef HOST_WORDS_BIGENDIAN 364 uint32_t ifar_ns; 365 uint32_t dfar_ns; 366 uint32_t ifar_s; 367 uint32_t dfar_s; 368 #else 369 uint32_t dfar_ns; 370 uint32_t ifar_ns; 371 uint32_t dfar_s; 372 uint32_t ifar_s; 373 #endif 374 uint64_t _unused_far3; 375 }; 376 uint64_t far_el[4]; 377 }; 378 uint64_t hpfar_el2; 379 uint64_t hstr_el2; 380 union { /* Translation result. */ 381 struct { 382 uint64_t _unused_par_0; 383 uint64_t par_ns; 384 uint64_t _unused_par_1; 385 uint64_t par_s; 386 }; 387 uint64_t par_el[4]; 388 }; 389 390 uint32_t c9_insn; /* Cache lockdown registers. */ 391 uint32_t c9_data; 392 uint64_t c9_pmcr; /* performance monitor control register */ 393 uint64_t c9_pmcnten; /* perf monitor counter enables */ 394 uint64_t c9_pmovsr; /* perf monitor overflow status */ 395 uint64_t c9_pmuserenr; /* perf monitor user enable */ 396 uint64_t c9_pmselr; /* perf monitor counter selection register */ 397 uint64_t c9_pminten; /* perf monitor interrupt enables */ 398 union { /* Memory attribute redirection */ 399 struct { 400 #ifdef HOST_WORDS_BIGENDIAN 401 uint64_t _unused_mair_0; 402 uint32_t mair1_ns; 403 uint32_t mair0_ns; 404 uint64_t _unused_mair_1; 405 uint32_t mair1_s; 406 uint32_t mair0_s; 407 #else 408 uint64_t _unused_mair_0; 409 uint32_t mair0_ns; 410 uint32_t mair1_ns; 411 uint64_t _unused_mair_1; 412 uint32_t mair0_s; 413 uint32_t mair1_s; 414 #endif 415 }; 416 uint64_t mair_el[4]; 417 }; 418 union { /* vector base address register */ 419 struct { 420 uint64_t _unused_vbar; 421 uint64_t vbar_ns; 422 uint64_t hvbar; 423 uint64_t vbar_s; 424 }; 425 uint64_t vbar_el[4]; 426 }; 427 uint32_t mvbar; /* (monitor) vector base address register */ 428 struct { /* FCSE PID. */ 429 uint32_t fcseidr_ns; 430 uint32_t fcseidr_s; 431 }; 432 union { /* Context ID. */ 433 struct { 434 uint64_t _unused_contextidr_0; 435 uint64_t contextidr_ns; 436 uint64_t _unused_contextidr_1; 437 uint64_t contextidr_s; 438 }; 439 uint64_t contextidr_el[4]; 440 }; 441 union { /* User RW Thread register. */ 442 struct { 443 uint64_t tpidrurw_ns; 444 uint64_t tpidrprw_ns; 445 uint64_t htpidr; 446 uint64_t _tpidr_el3; 447 }; 448 uint64_t tpidr_el[4]; 449 }; 450 /* The secure banks of these registers don't map anywhere */ 451 uint64_t tpidrurw_s; 452 uint64_t tpidrprw_s; 453 uint64_t tpidruro_s; 454 455 union { /* User RO Thread register. */ 456 uint64_t tpidruro_ns; 457 uint64_t tpidrro_el[1]; 458 }; 459 uint64_t c14_cntfrq; /* Counter Frequency register */ 460 uint64_t c14_cntkctl; /* Timer Control register */ 461 uint32_t cnthctl_el2; /* Counter/Timer Hyp Control register */ 462 uint64_t cntvoff_el2; /* Counter Virtual Offset register */ 463 ARMGenericTimer c14_timer[NUM_GTIMERS]; 464 uint32_t c15_cpar; /* XScale Coprocessor Access Register */ 465 uint32_t c15_ticonfig; /* TI925T configuration byte. */ 466 uint32_t c15_i_max; /* Maximum D-cache dirty line index. */ 467 uint32_t c15_i_min; /* Minimum D-cache dirty line index. */ 468 uint32_t c15_threadid; /* TI debugger thread-ID. */ 469 uint32_t c15_config_base_address; /* SCU base address. */ 470 uint32_t c15_diagnostic; /* diagnostic register */ 471 uint32_t c15_power_diagnostic; 472 uint32_t c15_power_control; /* power control */ 473 uint64_t dbgbvr[16]; /* breakpoint value registers */ 474 uint64_t dbgbcr[16]; /* breakpoint control registers */ 475 uint64_t dbgwvr[16]; /* watchpoint value registers */ 476 uint64_t dbgwcr[16]; /* watchpoint control registers */ 477 uint64_t mdscr_el1; 478 uint64_t oslsr_el1; /* OS Lock Status */ 479 uint64_t mdcr_el2; 480 uint64_t mdcr_el3; 481 /* Stores the architectural value of the counter *the last time it was 482 * updated* by pmccntr_op_start. Accesses should always be surrounded 483 * by pmccntr_op_start/pmccntr_op_finish to guarantee the latest 484 * architecturally-correct value is being read/set. 485 */ 486 uint64_t c15_ccnt; 487 /* Stores the delta between the architectural value and the underlying 488 * cycle count during normal operation. It is used to update c15_ccnt 489 * to be the correct architectural value before accesses. During 490 * accesses, c15_ccnt_delta contains the underlying count being used 491 * for the access, after which it reverts to the delta value in 492 * pmccntr_op_finish. 493 */ 494 uint64_t c15_ccnt_delta; 495 uint64_t c14_pmevcntr[31]; 496 uint64_t c14_pmevcntr_delta[31]; 497 uint64_t c14_pmevtyper[31]; 498 uint64_t pmccfiltr_el0; /* Performance Monitor Filter Register */ 499 uint64_t vpidr_el2; /* Virtualization Processor ID Register */ 500 uint64_t vmpidr_el2; /* Virtualization Multiprocessor ID Register */ 501 } cp15; 502 503 struct { 504 /* M profile has up to 4 stack pointers: 505 * a Main Stack Pointer and a Process Stack Pointer for each 506 * of the Secure and Non-Secure states. (If the CPU doesn't support 507 * the security extension then it has only two SPs.) 508 * In QEMU we always store the currently active SP in regs[13], 509 * and the non-active SP for the current security state in 510 * v7m.other_sp. The stack pointers for the inactive security state 511 * are stored in other_ss_msp and other_ss_psp. 512 * switch_v7m_security_state() is responsible for rearranging them 513 * when we change security state. 514 */ 515 uint32_t other_sp; 516 uint32_t other_ss_msp; 517 uint32_t other_ss_psp; 518 uint32_t vecbase[M_REG_NUM_BANKS]; 519 uint32_t basepri[M_REG_NUM_BANKS]; 520 uint32_t control[M_REG_NUM_BANKS]; 521 uint32_t ccr[M_REG_NUM_BANKS]; /* Configuration and Control */ 522 uint32_t cfsr[M_REG_NUM_BANKS]; /* Configurable Fault Status */ 523 uint32_t hfsr; /* HardFault Status */ 524 uint32_t dfsr; /* Debug Fault Status Register */ 525 uint32_t sfsr; /* Secure Fault Status Register */ 526 uint32_t mmfar[M_REG_NUM_BANKS]; /* MemManage Fault Address */ 527 uint32_t bfar; /* BusFault Address */ 528 uint32_t sfar; /* Secure Fault Address Register */ 529 unsigned mpu_ctrl[M_REG_NUM_BANKS]; /* MPU_CTRL */ 530 int exception; 531 uint32_t primask[M_REG_NUM_BANKS]; 532 uint32_t faultmask[M_REG_NUM_BANKS]; 533 uint32_t aircr; /* only holds r/w state if security extn implemented */ 534 uint32_t secure; /* Is CPU in Secure state? (not guest visible) */ 535 uint32_t csselr[M_REG_NUM_BANKS]; 536 uint32_t scr[M_REG_NUM_BANKS]; 537 uint32_t msplim[M_REG_NUM_BANKS]; 538 uint32_t psplim[M_REG_NUM_BANKS]; 539 uint32_t fpcar[M_REG_NUM_BANKS]; 540 uint32_t fpccr[M_REG_NUM_BANKS]; 541 uint32_t fpdscr[M_REG_NUM_BANKS]; 542 uint32_t cpacr[M_REG_NUM_BANKS]; 543 uint32_t nsacr; 544 } v7m; 545 546 /* Information associated with an exception about to be taken: 547 * code which raises an exception must set cs->exception_index and 548 * the relevant parts of this structure; the cpu_do_interrupt function 549 * will then set the guest-visible registers as part of the exception 550 * entry process. 551 */ 552 struct { 553 uint32_t syndrome; /* AArch64 format syndrome register */ 554 uint32_t fsr; /* AArch32 format fault status register info */ 555 uint64_t vaddress; /* virtual addr associated with exception, if any */ 556 uint32_t target_el; /* EL the exception should be targeted for */ 557 /* If we implement EL2 we will also need to store information 558 * about the intermediate physical address for stage 2 faults. 559 */ 560 } exception; 561 562 /* Information associated with an SError */ 563 struct { 564 uint8_t pending; 565 uint8_t has_esr; 566 uint64_t esr; 567 } serror; 568 569 /* State of our input IRQ/FIQ/VIRQ/VFIQ lines */ 570 uint32_t irq_line_state; 571 572 /* Thumb-2 EE state. */ 573 uint32_t teecr; 574 uint32_t teehbr; 575 576 /* VFP coprocessor state. */ 577 struct { 578 ARMVectorReg zregs[32]; 579 580 #ifdef TARGET_AARCH64 581 /* Store FFR as pregs[16] to make it easier to treat as any other. */ 582 #define FFR_PRED_NUM 16 583 ARMPredicateReg pregs[17]; 584 /* Scratch space for aa64 sve predicate temporary. */ 585 ARMPredicateReg preg_tmp; 586 #endif 587 588 /* We store these fpcsr fields separately for convenience. */ 589 uint32_t qc[4] QEMU_ALIGNED(16); 590 int vec_len; 591 int vec_stride; 592 593 uint32_t xregs[16]; 594 595 /* Scratch space for aa32 neon expansion. */ 596 uint32_t scratch[8]; 597 598 /* There are a number of distinct float control structures: 599 * 600 * fp_status: is the "normal" fp status. 601 * fp_status_fp16: used for half-precision calculations 602 * standard_fp_status : the ARM "Standard FPSCR Value" 603 * 604 * Half-precision operations are governed by a separate 605 * flush-to-zero control bit in FPSCR:FZ16. We pass a separate 606 * status structure to control this. 607 * 608 * The "Standard FPSCR", ie default-NaN, flush-to-zero, 609 * round-to-nearest and is used by any operations (generally 610 * Neon) which the architecture defines as controlled by the 611 * standard FPSCR value rather than the FPSCR. 612 * 613 * To avoid having to transfer exception bits around, we simply 614 * say that the FPSCR cumulative exception flags are the logical 615 * OR of the flags in the three fp statuses. This relies on the 616 * only thing which needs to read the exception flags being 617 * an explicit FPSCR read. 618 */ 619 float_status fp_status; 620 float_status fp_status_f16; 621 float_status standard_fp_status; 622 623 /* ZCR_EL[1-3] */ 624 uint64_t zcr_el[4]; 625 } vfp; 626 uint64_t exclusive_addr; 627 uint64_t exclusive_val; 628 uint64_t exclusive_high; 629 630 /* iwMMXt coprocessor state. */ 631 struct { 632 uint64_t regs[16]; 633 uint64_t val; 634 635 uint32_t cregs[16]; 636 } iwmmxt; 637 638 #ifdef TARGET_AARCH64 639 struct { 640 ARMPACKey apia; 641 ARMPACKey apib; 642 ARMPACKey apda; 643 ARMPACKey apdb; 644 ARMPACKey apga; 645 } keys; 646 #endif 647 648 #if defined(CONFIG_USER_ONLY) 649 /* For usermode syscall translation. */ 650 int eabi; 651 #endif 652 653 struct CPUBreakpoint *cpu_breakpoint[16]; 654 struct CPUWatchpoint *cpu_watchpoint[16]; 655 656 /* Fields up to this point are cleared by a CPU reset */ 657 struct {} end_reset_fields; 658 659 CPU_COMMON 660 661 /* Fields after CPU_COMMON are preserved across CPU reset. */ 662 663 /* Internal CPU feature flags. */ 664 uint64_t features; 665 666 /* PMSAv7 MPU */ 667 struct { 668 uint32_t *drbar; 669 uint32_t *drsr; 670 uint32_t *dracr; 671 uint32_t rnr[M_REG_NUM_BANKS]; 672 } pmsav7; 673 674 /* PMSAv8 MPU */ 675 struct { 676 /* The PMSAv8 implementation also shares some PMSAv7 config 677 * and state: 678 * pmsav7.rnr (region number register) 679 * pmsav7_dregion (number of configured regions) 680 */ 681 uint32_t *rbar[M_REG_NUM_BANKS]; 682 uint32_t *rlar[M_REG_NUM_BANKS]; 683 uint32_t mair0[M_REG_NUM_BANKS]; 684 uint32_t mair1[M_REG_NUM_BANKS]; 685 } pmsav8; 686 687 /* v8M SAU */ 688 struct { 689 uint32_t *rbar; 690 uint32_t *rlar; 691 uint32_t rnr; 692 uint32_t ctrl; 693 } sau; 694 695 void *nvic; 696 const struct arm_boot_info *boot_info; 697 /* Store GICv3CPUState to access from this struct */ 698 void *gicv3state; 699 } CPUARMState; 700 701 /** 702 * ARMELChangeHookFn: 703 * type of a function which can be registered via arm_register_el_change_hook() 704 * to get callbacks when the CPU changes its exception level or mode. 705 */ 706 typedef void ARMELChangeHookFn(ARMCPU *cpu, void *opaque); 707 typedef struct ARMELChangeHook ARMELChangeHook; 708 struct ARMELChangeHook { 709 ARMELChangeHookFn *hook; 710 void *opaque; 711 QLIST_ENTRY(ARMELChangeHook) node; 712 }; 713 714 /* These values map onto the return values for 715 * QEMU_PSCI_0_2_FN_AFFINITY_INFO */ 716 typedef enum ARMPSCIState { 717 PSCI_ON = 0, 718 PSCI_OFF = 1, 719 PSCI_ON_PENDING = 2 720 } ARMPSCIState; 721 722 typedef struct ARMISARegisters ARMISARegisters; 723 724 /** 725 * ARMCPU: 726 * @env: #CPUARMState 727 * 728 * An ARM CPU core. 729 */ 730 struct ARMCPU { 731 /*< private >*/ 732 CPUState parent_obj; 733 /*< public >*/ 734 735 CPUARMState env; 736 737 /* Coprocessor information */ 738 GHashTable *cp_regs; 739 /* For marshalling (mostly coprocessor) register state between the 740 * kernel and QEMU (for KVM) and between two QEMUs (for migration), 741 * we use these arrays. 742 */ 743 /* List of register indexes managed via these arrays; (full KVM style 744 * 64 bit indexes, not CPRegInfo 32 bit indexes) 745 */ 746 uint64_t *cpreg_indexes; 747 /* Values of the registers (cpreg_indexes[i]'s value is cpreg_values[i]) */ 748 uint64_t *cpreg_values; 749 /* Length of the indexes, values, reset_values arrays */ 750 int32_t cpreg_array_len; 751 /* These are used only for migration: incoming data arrives in 752 * these fields and is sanity checked in post_load before copying 753 * to the working data structures above. 754 */ 755 uint64_t *cpreg_vmstate_indexes; 756 uint64_t *cpreg_vmstate_values; 757 int32_t cpreg_vmstate_array_len; 758 759 DynamicGDBXMLInfo dyn_xml; 760 761 /* Timers used by the generic (architected) timer */ 762 QEMUTimer *gt_timer[NUM_GTIMERS]; 763 /* 764 * Timer used by the PMU. Its state is restored after migration by 765 * pmu_op_finish() - it does not need other handling during migration 766 */ 767 QEMUTimer *pmu_timer; 768 /* GPIO outputs for generic timer */ 769 qemu_irq gt_timer_outputs[NUM_GTIMERS]; 770 /* GPIO output for GICv3 maintenance interrupt signal */ 771 qemu_irq gicv3_maintenance_interrupt; 772 /* GPIO output for the PMU interrupt */ 773 qemu_irq pmu_interrupt; 774 775 /* MemoryRegion to use for secure physical accesses */ 776 MemoryRegion *secure_memory; 777 778 /* For v8M, pointer to the IDAU interface provided by board/SoC */ 779 Object *idau; 780 781 /* 'compatible' string for this CPU for Linux device trees */ 782 const char *dtb_compatible; 783 784 /* PSCI version for this CPU 785 * Bits[31:16] = Major Version 786 * Bits[15:0] = Minor Version 787 */ 788 uint32_t psci_version; 789 790 /* Should CPU start in PSCI powered-off state? */ 791 bool start_powered_off; 792 793 /* Current power state, access guarded by BQL */ 794 ARMPSCIState power_state; 795 796 /* CPU has virtualization extension */ 797 bool has_el2; 798 /* CPU has security extension */ 799 bool has_el3; 800 /* CPU has PMU (Performance Monitor Unit) */ 801 bool has_pmu; 802 803 /* CPU has memory protection unit */ 804 bool has_mpu; 805 /* PMSAv7 MPU number of supported regions */ 806 uint32_t pmsav7_dregion; 807 /* v8M SAU number of supported regions */ 808 uint32_t sau_sregion; 809 810 /* PSCI conduit used to invoke PSCI methods 811 * 0 - disabled, 1 - smc, 2 - hvc 812 */ 813 uint32_t psci_conduit; 814 815 /* For v8M, initial value of the Secure VTOR */ 816 uint32_t init_svtor; 817 818 /* [QEMU_]KVM_ARM_TARGET_* constant for this CPU, or 819 * QEMU_KVM_ARM_TARGET_NONE if the kernel doesn't support this CPU type. 820 */ 821 uint32_t kvm_target; 822 823 /* KVM init features for this CPU */ 824 uint32_t kvm_init_features[7]; 825 826 /* Uniprocessor system with MP extensions */ 827 bool mp_is_up; 828 829 /* True if we tried kvm_arm_host_cpu_features() during CPU instance_init 830 * and the probe failed (so we need to report the error in realize) 831 */ 832 bool host_cpu_probe_failed; 833 834 /* Specify the number of cores in this CPU cluster. Used for the L2CTLR 835 * register. 836 */ 837 int32_t core_count; 838 839 /* The instance init functions for implementation-specific subclasses 840 * set these fields to specify the implementation-dependent values of 841 * various constant registers and reset values of non-constant 842 * registers. 843 * Some of these might become QOM properties eventually. 844 * Field names match the official register names as defined in the 845 * ARMv7AR ARM Architecture Reference Manual. A reset_ prefix 846 * is used for reset values of non-constant registers; no reset_ 847 * prefix means a constant register. 848 * Some of these registers are split out into a substructure that 849 * is shared with the translators to control the ISA. 850 */ 851 struct ARMISARegisters { 852 uint32_t id_isar0; 853 uint32_t id_isar1; 854 uint32_t id_isar2; 855 uint32_t id_isar3; 856 uint32_t id_isar4; 857 uint32_t id_isar5; 858 uint32_t id_isar6; 859 uint32_t mvfr0; 860 uint32_t mvfr1; 861 uint32_t mvfr2; 862 uint64_t id_aa64isar0; 863 uint64_t id_aa64isar1; 864 uint64_t id_aa64pfr0; 865 uint64_t id_aa64pfr1; 866 uint64_t id_aa64mmfr0; 867 uint64_t id_aa64mmfr1; 868 } isar; 869 uint32_t midr; 870 uint32_t revidr; 871 uint32_t reset_fpsid; 872 uint32_t ctr; 873 uint32_t reset_sctlr; 874 uint32_t id_pfr0; 875 uint32_t id_pfr1; 876 uint32_t id_dfr0; 877 uint64_t pmceid0; 878 uint64_t pmceid1; 879 uint32_t id_afr0; 880 uint32_t id_mmfr0; 881 uint32_t id_mmfr1; 882 uint32_t id_mmfr2; 883 uint32_t id_mmfr3; 884 uint32_t id_mmfr4; 885 uint64_t id_aa64dfr0; 886 uint64_t id_aa64dfr1; 887 uint64_t id_aa64afr0; 888 uint64_t id_aa64afr1; 889 uint32_t dbgdidr; 890 uint32_t clidr; 891 uint64_t mp_affinity; /* MP ID without feature bits */ 892 /* The elements of this array are the CCSIDR values for each cache, 893 * in the order L1DCache, L1ICache, L2DCache, L2ICache, etc. 894 */ 895 uint32_t ccsidr[16]; 896 uint64_t reset_cbar; 897 uint32_t reset_auxcr; 898 bool reset_hivecs; 899 /* DCZ blocksize, in log_2(words), ie low 4 bits of DCZID_EL0 */ 900 uint32_t dcz_blocksize; 901 uint64_t rvbar; 902 903 /* Configurable aspects of GIC cpu interface (which is part of the CPU) */ 904 int gic_num_lrs; /* number of list registers */ 905 int gic_vpribits; /* number of virtual priority bits */ 906 int gic_vprebits; /* number of virtual preemption bits */ 907 908 /* Whether the cfgend input is high (i.e. this CPU should reset into 909 * big-endian mode). This setting isn't used directly: instead it modifies 910 * the reset_sctlr value to have SCTLR_B or SCTLR_EE set, depending on the 911 * architecture version. 912 */ 913 bool cfgend; 914 915 QLIST_HEAD(, ARMELChangeHook) pre_el_change_hooks; 916 QLIST_HEAD(, ARMELChangeHook) el_change_hooks; 917 918 int32_t node_id; /* NUMA node this CPU belongs to */ 919 920 /* Used to synchronize KVM and QEMU in-kernel device levels */ 921 uint8_t device_irq_level; 922 923 /* Used to set the maximum vector length the cpu will support. */ 924 uint32_t sve_max_vq; 925 }; 926 927 static inline ARMCPU *arm_env_get_cpu(CPUARMState *env) 928 { 929 return container_of(env, ARMCPU, env); 930 } 931 932 void arm_cpu_post_init(Object *obj); 933 934 uint64_t arm_cpu_mp_affinity(int idx, uint8_t clustersz); 935 936 #define ENV_GET_CPU(e) CPU(arm_env_get_cpu(e)) 937 938 #define ENV_OFFSET offsetof(ARMCPU, env) 939 940 #ifndef CONFIG_USER_ONLY 941 extern const struct VMStateDescription vmstate_arm_cpu; 942 #endif 943 944 void arm_cpu_do_interrupt(CPUState *cpu); 945 void arm_v7m_cpu_do_interrupt(CPUState *cpu); 946 bool arm_cpu_exec_interrupt(CPUState *cpu, int int_req); 947 948 void arm_cpu_dump_state(CPUState *cs, FILE *f, int flags); 949 950 hwaddr arm_cpu_get_phys_page_attrs_debug(CPUState *cpu, vaddr addr, 951 MemTxAttrs *attrs); 952 953 int arm_cpu_gdb_read_register(CPUState *cpu, uint8_t *buf, int reg); 954 int arm_cpu_gdb_write_register(CPUState *cpu, uint8_t *buf, int reg); 955 956 /* Dynamically generates for gdb stub an XML description of the sysregs from 957 * the cp_regs hashtable. Returns the registered sysregs number. 958 */ 959 int arm_gen_dynamic_xml(CPUState *cpu); 960 961 /* Returns the dynamically generated XML for the gdb stub. 962 * Returns a pointer to the XML contents for the specified XML file or NULL 963 * if the XML name doesn't match the predefined one. 964 */ 965 const char *arm_gdb_get_dynamic_xml(CPUState *cpu, const char *xmlname); 966 967 int arm_cpu_write_elf64_note(WriteCoreDumpFunction f, CPUState *cs, 968 int cpuid, void *opaque); 969 int arm_cpu_write_elf32_note(WriteCoreDumpFunction f, CPUState *cs, 970 int cpuid, void *opaque); 971 972 #ifdef TARGET_AARCH64 973 int aarch64_cpu_gdb_read_register(CPUState *cpu, uint8_t *buf, int reg); 974 int aarch64_cpu_gdb_write_register(CPUState *cpu, uint8_t *buf, int reg); 975 void aarch64_sve_narrow_vq(CPUARMState *env, unsigned vq); 976 void aarch64_sve_change_el(CPUARMState *env, int old_el, 977 int new_el, bool el0_a64); 978 #else 979 static inline void aarch64_sve_narrow_vq(CPUARMState *env, unsigned vq) { } 980 static inline void aarch64_sve_change_el(CPUARMState *env, int o, 981 int n, bool a) 982 { } 983 #endif 984 985 target_ulong do_arm_semihosting(CPUARMState *env); 986 void aarch64_sync_32_to_64(CPUARMState *env); 987 void aarch64_sync_64_to_32(CPUARMState *env); 988 989 int fp_exception_el(CPUARMState *env, int cur_el); 990 int sve_exception_el(CPUARMState *env, int cur_el); 991 uint32_t sve_zcr_len_for_el(CPUARMState *env, int el); 992 993 static inline bool is_a64(CPUARMState *env) 994 { 995 return env->aarch64; 996 } 997 998 /* you can call this signal handler from your SIGBUS and SIGSEGV 999 signal handlers to inform the virtual CPU of exceptions. non zero 1000 is returned if the signal was handled by the virtual CPU. */ 1001 int cpu_arm_signal_handler(int host_signum, void *pinfo, 1002 void *puc); 1003 1004 /** 1005 * pmu_op_start/finish 1006 * @env: CPUARMState 1007 * 1008 * Convert all PMU counters between their delta form (the typical mode when 1009 * they are enabled) and the guest-visible values. These two calls must 1010 * surround any action which might affect the counters. 1011 */ 1012 void pmu_op_start(CPUARMState *env); 1013 void pmu_op_finish(CPUARMState *env); 1014 1015 /* 1016 * Called when a PMU counter is due to overflow 1017 */ 1018 void arm_pmu_timer_cb(void *opaque); 1019 1020 /** 1021 * Functions to register as EL change hooks for PMU mode filtering 1022 */ 1023 void pmu_pre_el_change(ARMCPU *cpu, void *ignored); 1024 void pmu_post_el_change(ARMCPU *cpu, void *ignored); 1025 1026 /* 1027 * pmu_init 1028 * @cpu: ARMCPU 1029 * 1030 * Initialize the CPU's PMCEID[01]_EL0 registers and associated internal state 1031 * for the current configuration 1032 */ 1033 void pmu_init(ARMCPU *cpu); 1034 1035 /* SCTLR bit meanings. Several bits have been reused in newer 1036 * versions of the architecture; in that case we define constants 1037 * for both old and new bit meanings. Code which tests against those 1038 * bits should probably check or otherwise arrange that the CPU 1039 * is the architectural version it expects. 1040 */ 1041 #define SCTLR_M (1U << 0) 1042 #define SCTLR_A (1U << 1) 1043 #define SCTLR_C (1U << 2) 1044 #define SCTLR_W (1U << 3) /* up to v6; RAO in v7 */ 1045 #define SCTLR_nTLSMD_32 (1U << 3) /* v8.2-LSMAOC, AArch32 only */ 1046 #define SCTLR_SA (1U << 3) /* AArch64 only */ 1047 #define SCTLR_P (1U << 4) /* up to v5; RAO in v6 and v7 */ 1048 #define SCTLR_LSMAOE_32 (1U << 4) /* v8.2-LSMAOC, AArch32 only */ 1049 #define SCTLR_SA0 (1U << 4) /* v8 onward, AArch64 only */ 1050 #define SCTLR_D (1U << 5) /* up to v5; RAO in v6 */ 1051 #define SCTLR_CP15BEN (1U << 5) /* v7 onward */ 1052 #define SCTLR_L (1U << 6) /* up to v5; RAO in v6 and v7; RAZ in v8 */ 1053 #define SCTLR_nAA (1U << 6) /* when v8.4-LSE is implemented */ 1054 #define SCTLR_B (1U << 7) /* up to v6; RAZ in v7 */ 1055 #define SCTLR_ITD (1U << 7) /* v8 onward */ 1056 #define SCTLR_S (1U << 8) /* up to v6; RAZ in v7 */ 1057 #define SCTLR_SED (1U << 8) /* v8 onward */ 1058 #define SCTLR_R (1U << 9) /* up to v6; RAZ in v7 */ 1059 #define SCTLR_UMA (1U << 9) /* v8 onward, AArch64 only */ 1060 #define SCTLR_F (1U << 10) /* up to v6 */ 1061 #define SCTLR_SW (1U << 10) /* v7 */ 1062 #define SCTLR_EnRCTX (1U << 10) /* in v8.0-PredInv */ 1063 #define SCTLR_Z (1U << 11) /* in v7, RES1 in v8 */ 1064 #define SCTLR_EOS (1U << 11) /* v8.5-ExS */ 1065 #define SCTLR_I (1U << 12) 1066 #define SCTLR_V (1U << 13) /* AArch32 only */ 1067 #define SCTLR_EnDB (1U << 13) /* v8.3, AArch64 only */ 1068 #define SCTLR_RR (1U << 14) /* up to v7 */ 1069 #define SCTLR_DZE (1U << 14) /* v8 onward, AArch64 only */ 1070 #define SCTLR_L4 (1U << 15) /* up to v6; RAZ in v7 */ 1071 #define SCTLR_UCT (1U << 15) /* v8 onward, AArch64 only */ 1072 #define SCTLR_DT (1U << 16) /* up to ??, RAO in v6 and v7 */ 1073 #define SCTLR_nTWI (1U << 16) /* v8 onward */ 1074 #define SCTLR_HA (1U << 17) /* up to v7, RES0 in v8 */ 1075 #define SCTLR_BR (1U << 17) /* PMSA only */ 1076 #define SCTLR_IT (1U << 18) /* up to ??, RAO in v6 and v7 */ 1077 #define SCTLR_nTWE (1U << 18) /* v8 onward */ 1078 #define SCTLR_WXN (1U << 19) 1079 #define SCTLR_ST (1U << 20) /* up to ??, RAZ in v6 */ 1080 #define SCTLR_UWXN (1U << 20) /* v7 onward, AArch32 only */ 1081 #define SCTLR_FI (1U << 21) /* up to v7, v8 RES0 */ 1082 #define SCTLR_IESB (1U << 21) /* v8.2-IESB, AArch64 only */ 1083 #define SCTLR_U (1U << 22) /* up to v6, RAO in v7 */ 1084 #define SCTLR_EIS (1U << 22) /* v8.5-ExS */ 1085 #define SCTLR_XP (1U << 23) /* up to v6; v7 onward RAO */ 1086 #define SCTLR_SPAN (1U << 23) /* v8.1-PAN */ 1087 #define SCTLR_VE (1U << 24) /* up to v7 */ 1088 #define SCTLR_E0E (1U << 24) /* v8 onward, AArch64 only */ 1089 #define SCTLR_EE (1U << 25) 1090 #define SCTLR_L2 (1U << 26) /* up to v6, RAZ in v7 */ 1091 #define SCTLR_UCI (1U << 26) /* v8 onward, AArch64 only */ 1092 #define SCTLR_NMFI (1U << 27) /* up to v7, RAZ in v7VE and v8 */ 1093 #define SCTLR_EnDA (1U << 27) /* v8.3, AArch64 only */ 1094 #define SCTLR_TRE (1U << 28) /* AArch32 only */ 1095 #define SCTLR_nTLSMD_64 (1U << 28) /* v8.2-LSMAOC, AArch64 only */ 1096 #define SCTLR_AFE (1U << 29) /* AArch32 only */ 1097 #define SCTLR_LSMAOE_64 (1U << 29) /* v8.2-LSMAOC, AArch64 only */ 1098 #define SCTLR_TE (1U << 30) /* AArch32 only */ 1099 #define SCTLR_EnIB (1U << 30) /* v8.3, AArch64 only */ 1100 #define SCTLR_EnIA (1U << 31) /* v8.3, AArch64 only */ 1101 #define SCTLR_BT0 (1ULL << 35) /* v8.5-BTI */ 1102 #define SCTLR_BT1 (1ULL << 36) /* v8.5-BTI */ 1103 #define SCTLR_ITFSB (1ULL << 37) /* v8.5-MemTag */ 1104 #define SCTLR_TCF0 (3ULL << 38) /* v8.5-MemTag */ 1105 #define SCTLR_TCF (3ULL << 40) /* v8.5-MemTag */ 1106 #define SCTLR_ATA0 (1ULL << 42) /* v8.5-MemTag */ 1107 #define SCTLR_ATA (1ULL << 43) /* v8.5-MemTag */ 1108 #define SCTLR_DSSBS (1ULL << 44) /* v8.5 */ 1109 1110 #define CPTR_TCPAC (1U << 31) 1111 #define CPTR_TTA (1U << 20) 1112 #define CPTR_TFP (1U << 10) 1113 #define CPTR_TZ (1U << 8) /* CPTR_EL2 */ 1114 #define CPTR_EZ (1U << 8) /* CPTR_EL3 */ 1115 1116 #define MDCR_EPMAD (1U << 21) 1117 #define MDCR_EDAD (1U << 20) 1118 #define MDCR_SPME (1U << 17) /* MDCR_EL3 */ 1119 #define MDCR_HPMD (1U << 17) /* MDCR_EL2 */ 1120 #define MDCR_SDD (1U << 16) 1121 #define MDCR_SPD (3U << 14) 1122 #define MDCR_TDRA (1U << 11) 1123 #define MDCR_TDOSA (1U << 10) 1124 #define MDCR_TDA (1U << 9) 1125 #define MDCR_TDE (1U << 8) 1126 #define MDCR_HPME (1U << 7) 1127 #define MDCR_TPM (1U << 6) 1128 #define MDCR_TPMCR (1U << 5) 1129 #define MDCR_HPMN (0x1fU) 1130 1131 /* Not all of the MDCR_EL3 bits are present in the 32-bit SDCR */ 1132 #define SDCR_VALID_MASK (MDCR_EPMAD | MDCR_EDAD | MDCR_SPME | MDCR_SPD) 1133 1134 #define CPSR_M (0x1fU) 1135 #define CPSR_T (1U << 5) 1136 #define CPSR_F (1U << 6) 1137 #define CPSR_I (1U << 7) 1138 #define CPSR_A (1U << 8) 1139 #define CPSR_E (1U << 9) 1140 #define CPSR_IT_2_7 (0xfc00U) 1141 #define CPSR_GE (0xfU << 16) 1142 #define CPSR_IL (1U << 20) 1143 /* Note that the RESERVED bits include bit 21, which is PSTATE_SS in 1144 * an AArch64 SPSR but RES0 in AArch32 SPSR and CPSR. In QEMU we use 1145 * env->uncached_cpsr bit 21 to store PSTATE.SS when executing in AArch32, 1146 * where it is live state but not accessible to the AArch32 code. 1147 */ 1148 #define CPSR_RESERVED (0x7U << 21) 1149 #define CPSR_J (1U << 24) 1150 #define CPSR_IT_0_1 (3U << 25) 1151 #define CPSR_Q (1U << 27) 1152 #define CPSR_V (1U << 28) 1153 #define CPSR_C (1U << 29) 1154 #define CPSR_Z (1U << 30) 1155 #define CPSR_N (1U << 31) 1156 #define CPSR_NZCV (CPSR_N | CPSR_Z | CPSR_C | CPSR_V) 1157 #define CPSR_AIF (CPSR_A | CPSR_I | CPSR_F) 1158 1159 #define CPSR_IT (CPSR_IT_0_1 | CPSR_IT_2_7) 1160 #define CACHED_CPSR_BITS (CPSR_T | CPSR_AIF | CPSR_GE | CPSR_IT | CPSR_Q \ 1161 | CPSR_NZCV) 1162 /* Bits writable in user mode. */ 1163 #define CPSR_USER (CPSR_NZCV | CPSR_Q | CPSR_GE) 1164 /* Execution state bits. MRS read as zero, MSR writes ignored. */ 1165 #define CPSR_EXEC (CPSR_T | CPSR_IT | CPSR_J | CPSR_IL) 1166 /* Mask of bits which may be set by exception return copying them from SPSR */ 1167 #define CPSR_ERET_MASK (~CPSR_RESERVED) 1168 1169 /* Bit definitions for M profile XPSR. Most are the same as CPSR. */ 1170 #define XPSR_EXCP 0x1ffU 1171 #define XPSR_SPREALIGN (1U << 9) /* Only set in exception stack frames */ 1172 #define XPSR_IT_2_7 CPSR_IT_2_7 1173 #define XPSR_GE CPSR_GE 1174 #define XPSR_SFPA (1U << 20) /* Only set in exception stack frames */ 1175 #define XPSR_T (1U << 24) /* Not the same as CPSR_T ! */ 1176 #define XPSR_IT_0_1 CPSR_IT_0_1 1177 #define XPSR_Q CPSR_Q 1178 #define XPSR_V CPSR_V 1179 #define XPSR_C CPSR_C 1180 #define XPSR_Z CPSR_Z 1181 #define XPSR_N CPSR_N 1182 #define XPSR_NZCV CPSR_NZCV 1183 #define XPSR_IT CPSR_IT 1184 1185 #define TTBCR_N (7U << 0) /* TTBCR.EAE==0 */ 1186 #define TTBCR_T0SZ (7U << 0) /* TTBCR.EAE==1 */ 1187 #define TTBCR_PD0 (1U << 4) 1188 #define TTBCR_PD1 (1U << 5) 1189 #define TTBCR_EPD0 (1U << 7) 1190 #define TTBCR_IRGN0 (3U << 8) 1191 #define TTBCR_ORGN0 (3U << 10) 1192 #define TTBCR_SH0 (3U << 12) 1193 #define TTBCR_T1SZ (3U << 16) 1194 #define TTBCR_A1 (1U << 22) 1195 #define TTBCR_EPD1 (1U << 23) 1196 #define TTBCR_IRGN1 (3U << 24) 1197 #define TTBCR_ORGN1 (3U << 26) 1198 #define TTBCR_SH1 (1U << 28) 1199 #define TTBCR_EAE (1U << 31) 1200 1201 /* Bit definitions for ARMv8 SPSR (PSTATE) format. 1202 * Only these are valid when in AArch64 mode; in 1203 * AArch32 mode SPSRs are basically CPSR-format. 1204 */ 1205 #define PSTATE_SP (1U) 1206 #define PSTATE_M (0xFU) 1207 #define PSTATE_nRW (1U << 4) 1208 #define PSTATE_F (1U << 6) 1209 #define PSTATE_I (1U << 7) 1210 #define PSTATE_A (1U << 8) 1211 #define PSTATE_D (1U << 9) 1212 #define PSTATE_BTYPE (3U << 10) 1213 #define PSTATE_IL (1U << 20) 1214 #define PSTATE_SS (1U << 21) 1215 #define PSTATE_V (1U << 28) 1216 #define PSTATE_C (1U << 29) 1217 #define PSTATE_Z (1U << 30) 1218 #define PSTATE_N (1U << 31) 1219 #define PSTATE_NZCV (PSTATE_N | PSTATE_Z | PSTATE_C | PSTATE_V) 1220 #define PSTATE_DAIF (PSTATE_D | PSTATE_A | PSTATE_I | PSTATE_F) 1221 #define CACHED_PSTATE_BITS (PSTATE_NZCV | PSTATE_DAIF | PSTATE_BTYPE) 1222 /* Mode values for AArch64 */ 1223 #define PSTATE_MODE_EL3h 13 1224 #define PSTATE_MODE_EL3t 12 1225 #define PSTATE_MODE_EL2h 9 1226 #define PSTATE_MODE_EL2t 8 1227 #define PSTATE_MODE_EL1h 5 1228 #define PSTATE_MODE_EL1t 4 1229 #define PSTATE_MODE_EL0t 0 1230 1231 /* Write a new value to v7m.exception, thus transitioning into or out 1232 * of Handler mode; this may result in a change of active stack pointer. 1233 */ 1234 void write_v7m_exception(CPUARMState *env, uint32_t new_exc); 1235 1236 /* Map EL and handler into a PSTATE_MODE. */ 1237 static inline unsigned int aarch64_pstate_mode(unsigned int el, bool handler) 1238 { 1239 return (el << 2) | handler; 1240 } 1241 1242 /* Return the current PSTATE value. For the moment we don't support 32<->64 bit 1243 * interprocessing, so we don't attempt to sync with the cpsr state used by 1244 * the 32 bit decoder. 1245 */ 1246 static inline uint32_t pstate_read(CPUARMState *env) 1247 { 1248 int ZF; 1249 1250 ZF = (env->ZF == 0); 1251 return (env->NF & 0x80000000) | (ZF << 30) 1252 | (env->CF << 29) | ((env->VF & 0x80000000) >> 3) 1253 | env->pstate | env->daif | (env->btype << 10); 1254 } 1255 1256 static inline void pstate_write(CPUARMState *env, uint32_t val) 1257 { 1258 env->ZF = (~val) & PSTATE_Z; 1259 env->NF = val; 1260 env->CF = (val >> 29) & 1; 1261 env->VF = (val << 3) & 0x80000000; 1262 env->daif = val & PSTATE_DAIF; 1263 env->btype = (val >> 10) & 3; 1264 env->pstate = val & ~CACHED_PSTATE_BITS; 1265 } 1266 1267 /* Return the current CPSR value. */ 1268 uint32_t cpsr_read(CPUARMState *env); 1269 1270 typedef enum CPSRWriteType { 1271 CPSRWriteByInstr = 0, /* from guest MSR or CPS */ 1272 CPSRWriteExceptionReturn = 1, /* from guest exception return insn */ 1273 CPSRWriteRaw = 2, /* trust values, do not switch reg banks */ 1274 CPSRWriteByGDBStub = 3, /* from the GDB stub */ 1275 } CPSRWriteType; 1276 1277 /* Set the CPSR. Note that some bits of mask must be all-set or all-clear.*/ 1278 void cpsr_write(CPUARMState *env, uint32_t val, uint32_t mask, 1279 CPSRWriteType write_type); 1280 1281 /* Return the current xPSR value. */ 1282 static inline uint32_t xpsr_read(CPUARMState *env) 1283 { 1284 int ZF; 1285 ZF = (env->ZF == 0); 1286 return (env->NF & 0x80000000) | (ZF << 30) 1287 | (env->CF << 29) | ((env->VF & 0x80000000) >> 3) | (env->QF << 27) 1288 | (env->thumb << 24) | ((env->condexec_bits & 3) << 25) 1289 | ((env->condexec_bits & 0xfc) << 8) 1290 | (env->GE << 16) 1291 | env->v7m.exception; 1292 } 1293 1294 /* Set the xPSR. Note that some bits of mask must be all-set or all-clear. */ 1295 static inline void xpsr_write(CPUARMState *env, uint32_t val, uint32_t mask) 1296 { 1297 if (mask & XPSR_NZCV) { 1298 env->ZF = (~val) & XPSR_Z; 1299 env->NF = val; 1300 env->CF = (val >> 29) & 1; 1301 env->VF = (val << 3) & 0x80000000; 1302 } 1303 if (mask & XPSR_Q) { 1304 env->QF = ((val & XPSR_Q) != 0); 1305 } 1306 if (mask & XPSR_GE) { 1307 env->GE = (val & XPSR_GE) >> 16; 1308 } 1309 if (mask & XPSR_T) { 1310 env->thumb = ((val & XPSR_T) != 0); 1311 } 1312 if (mask & XPSR_IT_0_1) { 1313 env->condexec_bits &= ~3; 1314 env->condexec_bits |= (val >> 25) & 3; 1315 } 1316 if (mask & XPSR_IT_2_7) { 1317 env->condexec_bits &= 3; 1318 env->condexec_bits |= (val >> 8) & 0xfc; 1319 } 1320 if (mask & XPSR_EXCP) { 1321 /* Note that this only happens on exception exit */ 1322 write_v7m_exception(env, val & XPSR_EXCP); 1323 } 1324 } 1325 1326 #define HCR_VM (1ULL << 0) 1327 #define HCR_SWIO (1ULL << 1) 1328 #define HCR_PTW (1ULL << 2) 1329 #define HCR_FMO (1ULL << 3) 1330 #define HCR_IMO (1ULL << 4) 1331 #define HCR_AMO (1ULL << 5) 1332 #define HCR_VF (1ULL << 6) 1333 #define HCR_VI (1ULL << 7) 1334 #define HCR_VSE (1ULL << 8) 1335 #define HCR_FB (1ULL << 9) 1336 #define HCR_BSU_MASK (3ULL << 10) 1337 #define HCR_DC (1ULL << 12) 1338 #define HCR_TWI (1ULL << 13) 1339 #define HCR_TWE (1ULL << 14) 1340 #define HCR_TID0 (1ULL << 15) 1341 #define HCR_TID1 (1ULL << 16) 1342 #define HCR_TID2 (1ULL << 17) 1343 #define HCR_TID3 (1ULL << 18) 1344 #define HCR_TSC (1ULL << 19) 1345 #define HCR_TIDCP (1ULL << 20) 1346 #define HCR_TACR (1ULL << 21) 1347 #define HCR_TSW (1ULL << 22) 1348 #define HCR_TPCP (1ULL << 23) 1349 #define HCR_TPU (1ULL << 24) 1350 #define HCR_TTLB (1ULL << 25) 1351 #define HCR_TVM (1ULL << 26) 1352 #define HCR_TGE (1ULL << 27) 1353 #define HCR_TDZ (1ULL << 28) 1354 #define HCR_HCD (1ULL << 29) 1355 #define HCR_TRVM (1ULL << 30) 1356 #define HCR_RW (1ULL << 31) 1357 #define HCR_CD (1ULL << 32) 1358 #define HCR_ID (1ULL << 33) 1359 #define HCR_E2H (1ULL << 34) 1360 #define HCR_TLOR (1ULL << 35) 1361 #define HCR_TERR (1ULL << 36) 1362 #define HCR_TEA (1ULL << 37) 1363 #define HCR_MIOCNCE (1ULL << 38) 1364 #define HCR_APK (1ULL << 40) 1365 #define HCR_API (1ULL << 41) 1366 #define HCR_NV (1ULL << 42) 1367 #define HCR_NV1 (1ULL << 43) 1368 #define HCR_AT (1ULL << 44) 1369 #define HCR_NV2 (1ULL << 45) 1370 #define HCR_FWB (1ULL << 46) 1371 #define HCR_FIEN (1ULL << 47) 1372 #define HCR_TID4 (1ULL << 49) 1373 #define HCR_TICAB (1ULL << 50) 1374 #define HCR_TOCU (1ULL << 52) 1375 #define HCR_TTLBIS (1ULL << 54) 1376 #define HCR_TTLBOS (1ULL << 55) 1377 #define HCR_ATA (1ULL << 56) 1378 #define HCR_DCT (1ULL << 57) 1379 1380 /* 1381 * When we actually implement ARMv8.1-VHE we should add HCR_E2H to 1382 * HCR_MASK and then clear it again if the feature bit is not set in 1383 * hcr_write(). 1384 */ 1385 #define HCR_MASK ((1ULL << 34) - 1) 1386 1387 #define SCR_NS (1U << 0) 1388 #define SCR_IRQ (1U << 1) 1389 #define SCR_FIQ (1U << 2) 1390 #define SCR_EA (1U << 3) 1391 #define SCR_FW (1U << 4) 1392 #define SCR_AW (1U << 5) 1393 #define SCR_NET (1U << 6) 1394 #define SCR_SMD (1U << 7) 1395 #define SCR_HCE (1U << 8) 1396 #define SCR_SIF (1U << 9) 1397 #define SCR_RW (1U << 10) 1398 #define SCR_ST (1U << 11) 1399 #define SCR_TWI (1U << 12) 1400 #define SCR_TWE (1U << 13) 1401 #define SCR_TLOR (1U << 14) 1402 #define SCR_TERR (1U << 15) 1403 #define SCR_APK (1U << 16) 1404 #define SCR_API (1U << 17) 1405 #define SCR_EEL2 (1U << 18) 1406 #define SCR_EASE (1U << 19) 1407 #define SCR_NMEA (1U << 20) 1408 #define SCR_FIEN (1U << 21) 1409 #define SCR_ENSCXT (1U << 25) 1410 #define SCR_ATA (1U << 26) 1411 1412 /* Return the current FPSCR value. */ 1413 uint32_t vfp_get_fpscr(CPUARMState *env); 1414 void vfp_set_fpscr(CPUARMState *env, uint32_t val); 1415 1416 /* FPCR, Floating Point Control Register 1417 * FPSR, Floating Poiht Status Register 1418 * 1419 * For A64 the FPSCR is split into two logically distinct registers, 1420 * FPCR and FPSR. However since they still use non-overlapping bits 1421 * we store the underlying state in fpscr and just mask on read/write. 1422 */ 1423 #define FPSR_MASK 0xf800009f 1424 #define FPCR_MASK 0x07ff9f00 1425 1426 #define FPCR_IOE (1 << 8) /* Invalid Operation exception trap enable */ 1427 #define FPCR_DZE (1 << 9) /* Divide by Zero exception trap enable */ 1428 #define FPCR_OFE (1 << 10) /* Overflow exception trap enable */ 1429 #define FPCR_UFE (1 << 11) /* Underflow exception trap enable */ 1430 #define FPCR_IXE (1 << 12) /* Inexact exception trap enable */ 1431 #define FPCR_IDE (1 << 15) /* Input Denormal exception trap enable */ 1432 #define FPCR_FZ16 (1 << 19) /* ARMv8.2+, FP16 flush-to-zero */ 1433 #define FPCR_FZ (1 << 24) /* Flush-to-zero enable bit */ 1434 #define FPCR_DN (1 << 25) /* Default NaN enable bit */ 1435 #define FPCR_QC (1 << 27) /* Cumulative saturation bit */ 1436 1437 static inline uint32_t vfp_get_fpsr(CPUARMState *env) 1438 { 1439 return vfp_get_fpscr(env) & FPSR_MASK; 1440 } 1441 1442 static inline void vfp_set_fpsr(CPUARMState *env, uint32_t val) 1443 { 1444 uint32_t new_fpscr = (vfp_get_fpscr(env) & ~FPSR_MASK) | (val & FPSR_MASK); 1445 vfp_set_fpscr(env, new_fpscr); 1446 } 1447 1448 static inline uint32_t vfp_get_fpcr(CPUARMState *env) 1449 { 1450 return vfp_get_fpscr(env) & FPCR_MASK; 1451 } 1452 1453 static inline void vfp_set_fpcr(CPUARMState *env, uint32_t val) 1454 { 1455 uint32_t new_fpscr = (vfp_get_fpscr(env) & ~FPCR_MASK) | (val & FPCR_MASK); 1456 vfp_set_fpscr(env, new_fpscr); 1457 } 1458 1459 enum arm_cpu_mode { 1460 ARM_CPU_MODE_USR = 0x10, 1461 ARM_CPU_MODE_FIQ = 0x11, 1462 ARM_CPU_MODE_IRQ = 0x12, 1463 ARM_CPU_MODE_SVC = 0x13, 1464 ARM_CPU_MODE_MON = 0x16, 1465 ARM_CPU_MODE_ABT = 0x17, 1466 ARM_CPU_MODE_HYP = 0x1a, 1467 ARM_CPU_MODE_UND = 0x1b, 1468 ARM_CPU_MODE_SYS = 0x1f 1469 }; 1470 1471 /* VFP system registers. */ 1472 #define ARM_VFP_FPSID 0 1473 #define ARM_VFP_FPSCR 1 1474 #define ARM_VFP_MVFR2 5 1475 #define ARM_VFP_MVFR1 6 1476 #define ARM_VFP_MVFR0 7 1477 #define ARM_VFP_FPEXC 8 1478 #define ARM_VFP_FPINST 9 1479 #define ARM_VFP_FPINST2 10 1480 1481 /* iwMMXt coprocessor control registers. */ 1482 #define ARM_IWMMXT_wCID 0 1483 #define ARM_IWMMXT_wCon 1 1484 #define ARM_IWMMXT_wCSSF 2 1485 #define ARM_IWMMXT_wCASF 3 1486 #define ARM_IWMMXT_wCGR0 8 1487 #define ARM_IWMMXT_wCGR1 9 1488 #define ARM_IWMMXT_wCGR2 10 1489 #define ARM_IWMMXT_wCGR3 11 1490 1491 /* V7M CCR bits */ 1492 FIELD(V7M_CCR, NONBASETHRDENA, 0, 1) 1493 FIELD(V7M_CCR, USERSETMPEND, 1, 1) 1494 FIELD(V7M_CCR, UNALIGN_TRP, 3, 1) 1495 FIELD(V7M_CCR, DIV_0_TRP, 4, 1) 1496 FIELD(V7M_CCR, BFHFNMIGN, 8, 1) 1497 FIELD(V7M_CCR, STKALIGN, 9, 1) 1498 FIELD(V7M_CCR, STKOFHFNMIGN, 10, 1) 1499 FIELD(V7M_CCR, DC, 16, 1) 1500 FIELD(V7M_CCR, IC, 17, 1) 1501 FIELD(V7M_CCR, BP, 18, 1) 1502 1503 /* V7M SCR bits */ 1504 FIELD(V7M_SCR, SLEEPONEXIT, 1, 1) 1505 FIELD(V7M_SCR, SLEEPDEEP, 2, 1) 1506 FIELD(V7M_SCR, SLEEPDEEPS, 3, 1) 1507 FIELD(V7M_SCR, SEVONPEND, 4, 1) 1508 1509 /* V7M AIRCR bits */ 1510 FIELD(V7M_AIRCR, VECTRESET, 0, 1) 1511 FIELD(V7M_AIRCR, VECTCLRACTIVE, 1, 1) 1512 FIELD(V7M_AIRCR, SYSRESETREQ, 2, 1) 1513 FIELD(V7M_AIRCR, SYSRESETREQS, 3, 1) 1514 FIELD(V7M_AIRCR, PRIGROUP, 8, 3) 1515 FIELD(V7M_AIRCR, BFHFNMINS, 13, 1) 1516 FIELD(V7M_AIRCR, PRIS, 14, 1) 1517 FIELD(V7M_AIRCR, ENDIANNESS, 15, 1) 1518 FIELD(V7M_AIRCR, VECTKEY, 16, 16) 1519 1520 /* V7M CFSR bits for MMFSR */ 1521 FIELD(V7M_CFSR, IACCVIOL, 0, 1) 1522 FIELD(V7M_CFSR, DACCVIOL, 1, 1) 1523 FIELD(V7M_CFSR, MUNSTKERR, 3, 1) 1524 FIELD(V7M_CFSR, MSTKERR, 4, 1) 1525 FIELD(V7M_CFSR, MLSPERR, 5, 1) 1526 FIELD(V7M_CFSR, MMARVALID, 7, 1) 1527 1528 /* V7M CFSR bits for BFSR */ 1529 FIELD(V7M_CFSR, IBUSERR, 8 + 0, 1) 1530 FIELD(V7M_CFSR, PRECISERR, 8 + 1, 1) 1531 FIELD(V7M_CFSR, IMPRECISERR, 8 + 2, 1) 1532 FIELD(V7M_CFSR, UNSTKERR, 8 + 3, 1) 1533 FIELD(V7M_CFSR, STKERR, 8 + 4, 1) 1534 FIELD(V7M_CFSR, LSPERR, 8 + 5, 1) 1535 FIELD(V7M_CFSR, BFARVALID, 8 + 7, 1) 1536 1537 /* V7M CFSR bits for UFSR */ 1538 FIELD(V7M_CFSR, UNDEFINSTR, 16 + 0, 1) 1539 FIELD(V7M_CFSR, INVSTATE, 16 + 1, 1) 1540 FIELD(V7M_CFSR, INVPC, 16 + 2, 1) 1541 FIELD(V7M_CFSR, NOCP, 16 + 3, 1) 1542 FIELD(V7M_CFSR, STKOF, 16 + 4, 1) 1543 FIELD(V7M_CFSR, UNALIGNED, 16 + 8, 1) 1544 FIELD(V7M_CFSR, DIVBYZERO, 16 + 9, 1) 1545 1546 /* V7M CFSR bit masks covering all of the subregister bits */ 1547 FIELD(V7M_CFSR, MMFSR, 0, 8) 1548 FIELD(V7M_CFSR, BFSR, 8, 8) 1549 FIELD(V7M_CFSR, UFSR, 16, 16) 1550 1551 /* V7M HFSR bits */ 1552 FIELD(V7M_HFSR, VECTTBL, 1, 1) 1553 FIELD(V7M_HFSR, FORCED, 30, 1) 1554 FIELD(V7M_HFSR, DEBUGEVT, 31, 1) 1555 1556 /* V7M DFSR bits */ 1557 FIELD(V7M_DFSR, HALTED, 0, 1) 1558 FIELD(V7M_DFSR, BKPT, 1, 1) 1559 FIELD(V7M_DFSR, DWTTRAP, 2, 1) 1560 FIELD(V7M_DFSR, VCATCH, 3, 1) 1561 FIELD(V7M_DFSR, EXTERNAL, 4, 1) 1562 1563 /* V7M SFSR bits */ 1564 FIELD(V7M_SFSR, INVEP, 0, 1) 1565 FIELD(V7M_SFSR, INVIS, 1, 1) 1566 FIELD(V7M_SFSR, INVER, 2, 1) 1567 FIELD(V7M_SFSR, AUVIOL, 3, 1) 1568 FIELD(V7M_SFSR, INVTRAN, 4, 1) 1569 FIELD(V7M_SFSR, LSPERR, 5, 1) 1570 FIELD(V7M_SFSR, SFARVALID, 6, 1) 1571 FIELD(V7M_SFSR, LSERR, 7, 1) 1572 1573 /* v7M MPU_CTRL bits */ 1574 FIELD(V7M_MPU_CTRL, ENABLE, 0, 1) 1575 FIELD(V7M_MPU_CTRL, HFNMIENA, 1, 1) 1576 FIELD(V7M_MPU_CTRL, PRIVDEFENA, 2, 1) 1577 1578 /* v7M CLIDR bits */ 1579 FIELD(V7M_CLIDR, CTYPE_ALL, 0, 21) 1580 FIELD(V7M_CLIDR, LOUIS, 21, 3) 1581 FIELD(V7M_CLIDR, LOC, 24, 3) 1582 FIELD(V7M_CLIDR, LOUU, 27, 3) 1583 FIELD(V7M_CLIDR, ICB, 30, 2) 1584 1585 FIELD(V7M_CSSELR, IND, 0, 1) 1586 FIELD(V7M_CSSELR, LEVEL, 1, 3) 1587 /* We use the combination of InD and Level to index into cpu->ccsidr[]; 1588 * define a mask for this and check that it doesn't permit running off 1589 * the end of the array. 1590 */ 1591 FIELD(V7M_CSSELR, INDEX, 0, 4) 1592 1593 /* v7M FPCCR bits */ 1594 FIELD(V7M_FPCCR, LSPACT, 0, 1) 1595 FIELD(V7M_FPCCR, USER, 1, 1) 1596 FIELD(V7M_FPCCR, S, 2, 1) 1597 FIELD(V7M_FPCCR, THREAD, 3, 1) 1598 FIELD(V7M_FPCCR, HFRDY, 4, 1) 1599 FIELD(V7M_FPCCR, MMRDY, 5, 1) 1600 FIELD(V7M_FPCCR, BFRDY, 6, 1) 1601 FIELD(V7M_FPCCR, SFRDY, 7, 1) 1602 FIELD(V7M_FPCCR, MONRDY, 8, 1) 1603 FIELD(V7M_FPCCR, SPLIMVIOL, 9, 1) 1604 FIELD(V7M_FPCCR, UFRDY, 10, 1) 1605 FIELD(V7M_FPCCR, RES0, 11, 15) 1606 FIELD(V7M_FPCCR, TS, 26, 1) 1607 FIELD(V7M_FPCCR, CLRONRETS, 27, 1) 1608 FIELD(V7M_FPCCR, CLRONRET, 28, 1) 1609 FIELD(V7M_FPCCR, LSPENS, 29, 1) 1610 FIELD(V7M_FPCCR, LSPEN, 30, 1) 1611 FIELD(V7M_FPCCR, ASPEN, 31, 1) 1612 /* These bits are banked. Others are non-banked and live in the M_REG_S bank */ 1613 #define R_V7M_FPCCR_BANKED_MASK \ 1614 (R_V7M_FPCCR_LSPACT_MASK | \ 1615 R_V7M_FPCCR_USER_MASK | \ 1616 R_V7M_FPCCR_THREAD_MASK | \ 1617 R_V7M_FPCCR_MMRDY_MASK | \ 1618 R_V7M_FPCCR_SPLIMVIOL_MASK | \ 1619 R_V7M_FPCCR_UFRDY_MASK | \ 1620 R_V7M_FPCCR_ASPEN_MASK) 1621 1622 /* 1623 * System register ID fields. 1624 */ 1625 FIELD(ID_ISAR0, SWAP, 0, 4) 1626 FIELD(ID_ISAR0, BITCOUNT, 4, 4) 1627 FIELD(ID_ISAR0, BITFIELD, 8, 4) 1628 FIELD(ID_ISAR0, CMPBRANCH, 12, 4) 1629 FIELD(ID_ISAR0, COPROC, 16, 4) 1630 FIELD(ID_ISAR0, DEBUG, 20, 4) 1631 FIELD(ID_ISAR0, DIVIDE, 24, 4) 1632 1633 FIELD(ID_ISAR1, ENDIAN, 0, 4) 1634 FIELD(ID_ISAR1, EXCEPT, 4, 4) 1635 FIELD(ID_ISAR1, EXCEPT_AR, 8, 4) 1636 FIELD(ID_ISAR1, EXTEND, 12, 4) 1637 FIELD(ID_ISAR1, IFTHEN, 16, 4) 1638 FIELD(ID_ISAR1, IMMEDIATE, 20, 4) 1639 FIELD(ID_ISAR1, INTERWORK, 24, 4) 1640 FIELD(ID_ISAR1, JAZELLE, 28, 4) 1641 1642 FIELD(ID_ISAR2, LOADSTORE, 0, 4) 1643 FIELD(ID_ISAR2, MEMHINT, 4, 4) 1644 FIELD(ID_ISAR2, MULTIACCESSINT, 8, 4) 1645 FIELD(ID_ISAR2, MULT, 12, 4) 1646 FIELD(ID_ISAR2, MULTS, 16, 4) 1647 FIELD(ID_ISAR2, MULTU, 20, 4) 1648 FIELD(ID_ISAR2, PSR_AR, 24, 4) 1649 FIELD(ID_ISAR2, REVERSAL, 28, 4) 1650 1651 FIELD(ID_ISAR3, SATURATE, 0, 4) 1652 FIELD(ID_ISAR3, SIMD, 4, 4) 1653 FIELD(ID_ISAR3, SVC, 8, 4) 1654 FIELD(ID_ISAR3, SYNCHPRIM, 12, 4) 1655 FIELD(ID_ISAR3, TABBRANCH, 16, 4) 1656 FIELD(ID_ISAR3, T32COPY, 20, 4) 1657 FIELD(ID_ISAR3, TRUENOP, 24, 4) 1658 FIELD(ID_ISAR3, T32EE, 28, 4) 1659 1660 FIELD(ID_ISAR4, UNPRIV, 0, 4) 1661 FIELD(ID_ISAR4, WITHSHIFTS, 4, 4) 1662 FIELD(ID_ISAR4, WRITEBACK, 8, 4) 1663 FIELD(ID_ISAR4, SMC, 12, 4) 1664 FIELD(ID_ISAR4, BARRIER, 16, 4) 1665 FIELD(ID_ISAR4, SYNCHPRIM_FRAC, 20, 4) 1666 FIELD(ID_ISAR4, PSR_M, 24, 4) 1667 FIELD(ID_ISAR4, SWP_FRAC, 28, 4) 1668 1669 FIELD(ID_ISAR5, SEVL, 0, 4) 1670 FIELD(ID_ISAR5, AES, 4, 4) 1671 FIELD(ID_ISAR5, SHA1, 8, 4) 1672 FIELD(ID_ISAR5, SHA2, 12, 4) 1673 FIELD(ID_ISAR5, CRC32, 16, 4) 1674 FIELD(ID_ISAR5, RDM, 24, 4) 1675 FIELD(ID_ISAR5, VCMA, 28, 4) 1676 1677 FIELD(ID_ISAR6, JSCVT, 0, 4) 1678 FIELD(ID_ISAR6, DP, 4, 4) 1679 FIELD(ID_ISAR6, FHM, 8, 4) 1680 FIELD(ID_ISAR6, SB, 12, 4) 1681 FIELD(ID_ISAR6, SPECRES, 16, 4) 1682 1683 FIELD(ID_MMFR4, SPECSEI, 0, 4) 1684 FIELD(ID_MMFR4, AC2, 4, 4) 1685 FIELD(ID_MMFR4, XNX, 8, 4) 1686 FIELD(ID_MMFR4, CNP, 12, 4) 1687 FIELD(ID_MMFR4, HPDS, 16, 4) 1688 FIELD(ID_MMFR4, LSM, 20, 4) 1689 FIELD(ID_MMFR4, CCIDX, 24, 4) 1690 FIELD(ID_MMFR4, EVT, 28, 4) 1691 1692 FIELD(ID_AA64ISAR0, AES, 4, 4) 1693 FIELD(ID_AA64ISAR0, SHA1, 8, 4) 1694 FIELD(ID_AA64ISAR0, SHA2, 12, 4) 1695 FIELD(ID_AA64ISAR0, CRC32, 16, 4) 1696 FIELD(ID_AA64ISAR0, ATOMIC, 20, 4) 1697 FIELD(ID_AA64ISAR0, RDM, 28, 4) 1698 FIELD(ID_AA64ISAR0, SHA3, 32, 4) 1699 FIELD(ID_AA64ISAR0, SM3, 36, 4) 1700 FIELD(ID_AA64ISAR0, SM4, 40, 4) 1701 FIELD(ID_AA64ISAR0, DP, 44, 4) 1702 FIELD(ID_AA64ISAR0, FHM, 48, 4) 1703 FIELD(ID_AA64ISAR0, TS, 52, 4) 1704 FIELD(ID_AA64ISAR0, TLB, 56, 4) 1705 FIELD(ID_AA64ISAR0, RNDR, 60, 4) 1706 1707 FIELD(ID_AA64ISAR1, DPB, 0, 4) 1708 FIELD(ID_AA64ISAR1, APA, 4, 4) 1709 FIELD(ID_AA64ISAR1, API, 8, 4) 1710 FIELD(ID_AA64ISAR1, JSCVT, 12, 4) 1711 FIELD(ID_AA64ISAR1, FCMA, 16, 4) 1712 FIELD(ID_AA64ISAR1, LRCPC, 20, 4) 1713 FIELD(ID_AA64ISAR1, GPA, 24, 4) 1714 FIELD(ID_AA64ISAR1, GPI, 28, 4) 1715 FIELD(ID_AA64ISAR1, FRINTTS, 32, 4) 1716 FIELD(ID_AA64ISAR1, SB, 36, 4) 1717 FIELD(ID_AA64ISAR1, SPECRES, 40, 4) 1718 1719 FIELD(ID_AA64PFR0, EL0, 0, 4) 1720 FIELD(ID_AA64PFR0, EL1, 4, 4) 1721 FIELD(ID_AA64PFR0, EL2, 8, 4) 1722 FIELD(ID_AA64PFR0, EL3, 12, 4) 1723 FIELD(ID_AA64PFR0, FP, 16, 4) 1724 FIELD(ID_AA64PFR0, ADVSIMD, 20, 4) 1725 FIELD(ID_AA64PFR0, GIC, 24, 4) 1726 FIELD(ID_AA64PFR0, RAS, 28, 4) 1727 FIELD(ID_AA64PFR0, SVE, 32, 4) 1728 1729 FIELD(ID_AA64PFR1, BT, 0, 4) 1730 FIELD(ID_AA64PFR1, SBSS, 4, 4) 1731 FIELD(ID_AA64PFR1, MTE, 8, 4) 1732 FIELD(ID_AA64PFR1, RAS_FRAC, 12, 4) 1733 1734 FIELD(ID_AA64MMFR0, PARANGE, 0, 4) 1735 FIELD(ID_AA64MMFR0, ASIDBITS, 4, 4) 1736 FIELD(ID_AA64MMFR0, BIGEND, 8, 4) 1737 FIELD(ID_AA64MMFR0, SNSMEM, 12, 4) 1738 FIELD(ID_AA64MMFR0, BIGENDEL0, 16, 4) 1739 FIELD(ID_AA64MMFR0, TGRAN16, 20, 4) 1740 FIELD(ID_AA64MMFR0, TGRAN64, 24, 4) 1741 FIELD(ID_AA64MMFR0, TGRAN4, 28, 4) 1742 FIELD(ID_AA64MMFR0, TGRAN16_2, 32, 4) 1743 FIELD(ID_AA64MMFR0, TGRAN64_2, 36, 4) 1744 FIELD(ID_AA64MMFR0, TGRAN4_2, 40, 4) 1745 FIELD(ID_AA64MMFR0, EXS, 44, 4) 1746 1747 FIELD(ID_AA64MMFR1, HAFDBS, 0, 4) 1748 FIELD(ID_AA64MMFR1, VMIDBITS, 4, 4) 1749 FIELD(ID_AA64MMFR1, VH, 8, 4) 1750 FIELD(ID_AA64MMFR1, HPDS, 12, 4) 1751 FIELD(ID_AA64MMFR1, LO, 16, 4) 1752 FIELD(ID_AA64MMFR1, PAN, 20, 4) 1753 FIELD(ID_AA64MMFR1, SPECSEI, 24, 4) 1754 FIELD(ID_AA64MMFR1, XNX, 28, 4) 1755 1756 FIELD(ID_DFR0, COPDBG, 0, 4) 1757 FIELD(ID_DFR0, COPSDBG, 4, 4) 1758 FIELD(ID_DFR0, MMAPDBG, 8, 4) 1759 FIELD(ID_DFR0, COPTRC, 12, 4) 1760 FIELD(ID_DFR0, MMAPTRC, 16, 4) 1761 FIELD(ID_DFR0, MPROFDBG, 20, 4) 1762 FIELD(ID_DFR0, PERFMON, 24, 4) 1763 FIELD(ID_DFR0, TRACEFILT, 28, 4) 1764 1765 FIELD(MVFR0, SIMDREG, 0, 4) 1766 FIELD(MVFR0, FPSP, 4, 4) 1767 FIELD(MVFR0, FPDP, 8, 4) 1768 FIELD(MVFR0, FPTRAP, 12, 4) 1769 FIELD(MVFR0, FPDIVIDE, 16, 4) 1770 FIELD(MVFR0, FPSQRT, 20, 4) 1771 FIELD(MVFR0, FPSHVEC, 24, 4) 1772 FIELD(MVFR0, FPROUND, 28, 4) 1773 1774 FIELD(MVFR1, FPFTZ, 0, 4) 1775 FIELD(MVFR1, FPDNAN, 4, 4) 1776 FIELD(MVFR1, SIMDLS, 8, 4) 1777 FIELD(MVFR1, SIMDINT, 12, 4) 1778 FIELD(MVFR1, SIMDSP, 16, 4) 1779 FIELD(MVFR1, SIMDHP, 20, 4) 1780 FIELD(MVFR1, FPHP, 24, 4) 1781 FIELD(MVFR1, SIMDFMAC, 28, 4) 1782 1783 FIELD(MVFR2, SIMDMISC, 0, 4) 1784 FIELD(MVFR2, FPMISC, 4, 4) 1785 1786 QEMU_BUILD_BUG_ON(ARRAY_SIZE(((ARMCPU *)0)->ccsidr) <= R_V7M_CSSELR_INDEX_MASK); 1787 1788 /* If adding a feature bit which corresponds to a Linux ELF 1789 * HWCAP bit, remember to update the feature-bit-to-hwcap 1790 * mapping in linux-user/elfload.c:get_elf_hwcap(). 1791 */ 1792 enum arm_features { 1793 ARM_FEATURE_VFP, 1794 ARM_FEATURE_AUXCR, /* ARM1026 Auxiliary control register. */ 1795 ARM_FEATURE_XSCALE, /* Intel XScale extensions. */ 1796 ARM_FEATURE_IWMMXT, /* Intel iwMMXt extension. */ 1797 ARM_FEATURE_V6, 1798 ARM_FEATURE_V6K, 1799 ARM_FEATURE_V7, 1800 ARM_FEATURE_THUMB2, 1801 ARM_FEATURE_PMSA, /* no MMU; may have Memory Protection Unit */ 1802 ARM_FEATURE_VFP3, 1803 ARM_FEATURE_NEON, 1804 ARM_FEATURE_M, /* Microcontroller profile. */ 1805 ARM_FEATURE_OMAPCP, /* OMAP specific CP15 ops handling. */ 1806 ARM_FEATURE_THUMB2EE, 1807 ARM_FEATURE_V7MP, /* v7 Multiprocessing Extensions */ 1808 ARM_FEATURE_V7VE, /* v7 Virtualization Extensions (non-EL2 parts) */ 1809 ARM_FEATURE_V4T, 1810 ARM_FEATURE_V5, 1811 ARM_FEATURE_STRONGARM, 1812 ARM_FEATURE_VAPA, /* cp15 VA to PA lookups */ 1813 ARM_FEATURE_VFP4, /* VFPv4 (implies that NEON is v2) */ 1814 ARM_FEATURE_GENERIC_TIMER, 1815 ARM_FEATURE_MVFR, /* Media and VFP Feature Registers 0 and 1 */ 1816 ARM_FEATURE_DUMMY_C15_REGS, /* RAZ/WI all of cp15 crn=15 */ 1817 ARM_FEATURE_CACHE_TEST_CLEAN, /* 926/1026 style test-and-clean ops */ 1818 ARM_FEATURE_CACHE_DIRTY_REG, /* 1136/1176 cache dirty status register */ 1819 ARM_FEATURE_CACHE_BLOCK_OPS, /* v6 optional cache block operations */ 1820 ARM_FEATURE_MPIDR, /* has cp15 MPIDR */ 1821 ARM_FEATURE_PXN, /* has Privileged Execute Never bit */ 1822 ARM_FEATURE_LPAE, /* has Large Physical Address Extension */ 1823 ARM_FEATURE_V8, 1824 ARM_FEATURE_AARCH64, /* supports 64 bit mode */ 1825 ARM_FEATURE_CBAR, /* has cp15 CBAR */ 1826 ARM_FEATURE_CRC, /* ARMv8 CRC instructions */ 1827 ARM_FEATURE_CBAR_RO, /* has cp15 CBAR and it is read-only */ 1828 ARM_FEATURE_EL2, /* has EL2 Virtualization support */ 1829 ARM_FEATURE_EL3, /* has EL3 Secure monitor support */ 1830 ARM_FEATURE_THUMB_DSP, /* DSP insns supported in the Thumb encodings */ 1831 ARM_FEATURE_PMU, /* has PMU support */ 1832 ARM_FEATURE_VBAR, /* has cp15 VBAR */ 1833 ARM_FEATURE_M_SECURITY, /* M profile Security Extension */ 1834 ARM_FEATURE_M_MAIN, /* M profile Main Extension */ 1835 }; 1836 1837 static inline int arm_feature(CPUARMState *env, int feature) 1838 { 1839 return (env->features & (1ULL << feature)) != 0; 1840 } 1841 1842 #if !defined(CONFIG_USER_ONLY) 1843 /* Return true if exception levels below EL3 are in secure state, 1844 * or would be following an exception return to that level. 1845 * Unlike arm_is_secure() (which is always a question about the 1846 * _current_ state of the CPU) this doesn't care about the current 1847 * EL or mode. 1848 */ 1849 static inline bool arm_is_secure_below_el3(CPUARMState *env) 1850 { 1851 if (arm_feature(env, ARM_FEATURE_EL3)) { 1852 return !(env->cp15.scr_el3 & SCR_NS); 1853 } else { 1854 /* If EL3 is not supported then the secure state is implementation 1855 * defined, in which case QEMU defaults to non-secure. 1856 */ 1857 return false; 1858 } 1859 } 1860 1861 /* Return true if the CPU is AArch64 EL3 or AArch32 Mon */ 1862 static inline bool arm_is_el3_or_mon(CPUARMState *env) 1863 { 1864 if (arm_feature(env, ARM_FEATURE_EL3)) { 1865 if (is_a64(env) && extract32(env->pstate, 2, 2) == 3) { 1866 /* CPU currently in AArch64 state and EL3 */ 1867 return true; 1868 } else if (!is_a64(env) && 1869 (env->uncached_cpsr & CPSR_M) == ARM_CPU_MODE_MON) { 1870 /* CPU currently in AArch32 state and monitor mode */ 1871 return true; 1872 } 1873 } 1874 return false; 1875 } 1876 1877 /* Return true if the processor is in secure state */ 1878 static inline bool arm_is_secure(CPUARMState *env) 1879 { 1880 if (arm_is_el3_or_mon(env)) { 1881 return true; 1882 } 1883 return arm_is_secure_below_el3(env); 1884 } 1885 1886 #else 1887 static inline bool arm_is_secure_below_el3(CPUARMState *env) 1888 { 1889 return false; 1890 } 1891 1892 static inline bool arm_is_secure(CPUARMState *env) 1893 { 1894 return false; 1895 } 1896 #endif 1897 1898 /** 1899 * arm_hcr_el2_eff(): Return the effective value of HCR_EL2. 1900 * E.g. when in secure state, fields in HCR_EL2 are suppressed, 1901 * "for all purposes other than a direct read or write access of HCR_EL2." 1902 * Not included here is HCR_RW. 1903 */ 1904 uint64_t arm_hcr_el2_eff(CPUARMState *env); 1905 1906 /* Return true if the specified exception level is running in AArch64 state. */ 1907 static inline bool arm_el_is_aa64(CPUARMState *env, int el) 1908 { 1909 /* This isn't valid for EL0 (if we're in EL0, is_a64() is what you want, 1910 * and if we're not in EL0 then the state of EL0 isn't well defined.) 1911 */ 1912 assert(el >= 1 && el <= 3); 1913 bool aa64 = arm_feature(env, ARM_FEATURE_AARCH64); 1914 1915 /* The highest exception level is always at the maximum supported 1916 * register width, and then lower levels have a register width controlled 1917 * by bits in the SCR or HCR registers. 1918 */ 1919 if (el == 3) { 1920 return aa64; 1921 } 1922 1923 if (arm_feature(env, ARM_FEATURE_EL3)) { 1924 aa64 = aa64 && (env->cp15.scr_el3 & SCR_RW); 1925 } 1926 1927 if (el == 2) { 1928 return aa64; 1929 } 1930 1931 if (arm_feature(env, ARM_FEATURE_EL2) && !arm_is_secure_below_el3(env)) { 1932 aa64 = aa64 && (env->cp15.hcr_el2 & HCR_RW); 1933 } 1934 1935 return aa64; 1936 } 1937 1938 /* Function for determing whether guest cp register reads and writes should 1939 * access the secure or non-secure bank of a cp register. When EL3 is 1940 * operating in AArch32 state, the NS-bit determines whether the secure 1941 * instance of a cp register should be used. When EL3 is AArch64 (or if 1942 * it doesn't exist at all) then there is no register banking, and all 1943 * accesses are to the non-secure version. 1944 */ 1945 static inline bool access_secure_reg(CPUARMState *env) 1946 { 1947 bool ret = (arm_feature(env, ARM_FEATURE_EL3) && 1948 !arm_el_is_aa64(env, 3) && 1949 !(env->cp15.scr_el3 & SCR_NS)); 1950 1951 return ret; 1952 } 1953 1954 /* Macros for accessing a specified CP register bank */ 1955 #define A32_BANKED_REG_GET(_env, _regname, _secure) \ 1956 ((_secure) ? (_env)->cp15._regname##_s : (_env)->cp15._regname##_ns) 1957 1958 #define A32_BANKED_REG_SET(_env, _regname, _secure, _val) \ 1959 do { \ 1960 if (_secure) { \ 1961 (_env)->cp15._regname##_s = (_val); \ 1962 } else { \ 1963 (_env)->cp15._regname##_ns = (_val); \ 1964 } \ 1965 } while (0) 1966 1967 /* Macros for automatically accessing a specific CP register bank depending on 1968 * the current secure state of the system. These macros are not intended for 1969 * supporting instruction translation reads/writes as these are dependent 1970 * solely on the SCR.NS bit and not the mode. 1971 */ 1972 #define A32_BANKED_CURRENT_REG_GET(_env, _regname) \ 1973 A32_BANKED_REG_GET((_env), _regname, \ 1974 (arm_is_secure(_env) && !arm_el_is_aa64((_env), 3))) 1975 1976 #define A32_BANKED_CURRENT_REG_SET(_env, _regname, _val) \ 1977 A32_BANKED_REG_SET((_env), _regname, \ 1978 (arm_is_secure(_env) && !arm_el_is_aa64((_env), 3)), \ 1979 (_val)) 1980 1981 void arm_cpu_list(void); 1982 uint32_t arm_phys_excp_target_el(CPUState *cs, uint32_t excp_idx, 1983 uint32_t cur_el, bool secure); 1984 1985 /* Interface between CPU and Interrupt controller. */ 1986 #ifndef CONFIG_USER_ONLY 1987 bool armv7m_nvic_can_take_pending_exception(void *opaque); 1988 #else 1989 static inline bool armv7m_nvic_can_take_pending_exception(void *opaque) 1990 { 1991 return true; 1992 } 1993 #endif 1994 /** 1995 * armv7m_nvic_set_pending: mark the specified exception as pending 1996 * @opaque: the NVIC 1997 * @irq: the exception number to mark pending 1998 * @secure: false for non-banked exceptions or for the nonsecure 1999 * version of a banked exception, true for the secure version of a banked 2000 * exception. 2001 * 2002 * Marks the specified exception as pending. Note that we will assert() 2003 * if @secure is true and @irq does not specify one of the fixed set 2004 * of architecturally banked exceptions. 2005 */ 2006 void armv7m_nvic_set_pending(void *opaque, int irq, bool secure); 2007 /** 2008 * armv7m_nvic_set_pending_derived: mark this derived exception as pending 2009 * @opaque: the NVIC 2010 * @irq: the exception number to mark pending 2011 * @secure: false for non-banked exceptions or for the nonsecure 2012 * version of a banked exception, true for the secure version of a banked 2013 * exception. 2014 * 2015 * Similar to armv7m_nvic_set_pending(), but specifically for derived 2016 * exceptions (exceptions generated in the course of trying to take 2017 * a different exception). 2018 */ 2019 void armv7m_nvic_set_pending_derived(void *opaque, int irq, bool secure); 2020 /** 2021 * armv7m_nvic_set_pending_lazyfp: mark this lazy FP exception as pending 2022 * @opaque: the NVIC 2023 * @irq: the exception number to mark pending 2024 * @secure: false for non-banked exceptions or for the nonsecure 2025 * version of a banked exception, true for the secure version of a banked 2026 * exception. 2027 * 2028 * Similar to armv7m_nvic_set_pending(), but specifically for exceptions 2029 * generated in the course of lazy stacking of FP registers. 2030 */ 2031 void armv7m_nvic_set_pending_lazyfp(void *opaque, int irq, bool secure); 2032 /** 2033 * armv7m_nvic_get_pending_irq_info: return highest priority pending 2034 * exception, and whether it targets Secure state 2035 * @opaque: the NVIC 2036 * @pirq: set to pending exception number 2037 * @ptargets_secure: set to whether pending exception targets Secure 2038 * 2039 * This function writes the number of the highest priority pending 2040 * exception (the one which would be made active by 2041 * armv7m_nvic_acknowledge_irq()) to @pirq, and sets @ptargets_secure 2042 * to true if the current highest priority pending exception should 2043 * be taken to Secure state, false for NS. 2044 */ 2045 void armv7m_nvic_get_pending_irq_info(void *opaque, int *pirq, 2046 bool *ptargets_secure); 2047 /** 2048 * armv7m_nvic_acknowledge_irq: make highest priority pending exception active 2049 * @opaque: the NVIC 2050 * 2051 * Move the current highest priority pending exception from the pending 2052 * state to the active state, and update v7m.exception to indicate that 2053 * it is the exception currently being handled. 2054 */ 2055 void armv7m_nvic_acknowledge_irq(void *opaque); 2056 /** 2057 * armv7m_nvic_complete_irq: complete specified interrupt or exception 2058 * @opaque: the NVIC 2059 * @irq: the exception number to complete 2060 * @secure: true if this exception was secure 2061 * 2062 * Returns: -1 if the irq was not active 2063 * 1 if completing this irq brought us back to base (no active irqs) 2064 * 0 if there is still an irq active after this one was completed 2065 * (Ignoring -1, this is the same as the RETTOBASE value before completion.) 2066 */ 2067 int armv7m_nvic_complete_irq(void *opaque, int irq, bool secure); 2068 /** 2069 * armv7m_nvic_get_ready_status(void *opaque, int irq, bool secure) 2070 * @opaque: the NVIC 2071 * @irq: the exception number to mark pending 2072 * @secure: false for non-banked exceptions or for the nonsecure 2073 * version of a banked exception, true for the secure version of a banked 2074 * exception. 2075 * 2076 * Return whether an exception is "ready", i.e. whether the exception is 2077 * enabled and is configured at a priority which would allow it to 2078 * interrupt the current execution priority. This controls whether the 2079 * RDY bit for it in the FPCCR is set. 2080 */ 2081 bool armv7m_nvic_get_ready_status(void *opaque, int irq, bool secure); 2082 /** 2083 * armv7m_nvic_raw_execution_priority: return the raw execution priority 2084 * @opaque: the NVIC 2085 * 2086 * Returns: the raw execution priority as defined by the v8M architecture. 2087 * This is the execution priority minus the effects of AIRCR.PRIS, 2088 * and minus any PRIMASK/FAULTMASK/BASEPRI priority boosting. 2089 * (v8M ARM ARM I_PKLD.) 2090 */ 2091 int armv7m_nvic_raw_execution_priority(void *opaque); 2092 /** 2093 * armv7m_nvic_neg_prio_requested: return true if the requested execution 2094 * priority is negative for the specified security state. 2095 * @opaque: the NVIC 2096 * @secure: the security state to test 2097 * This corresponds to the pseudocode IsReqExecPriNeg(). 2098 */ 2099 #ifndef CONFIG_USER_ONLY 2100 bool armv7m_nvic_neg_prio_requested(void *opaque, bool secure); 2101 #else 2102 static inline bool armv7m_nvic_neg_prio_requested(void *opaque, bool secure) 2103 { 2104 return false; 2105 } 2106 #endif 2107 2108 /* Interface for defining coprocessor registers. 2109 * Registers are defined in tables of arm_cp_reginfo structs 2110 * which are passed to define_arm_cp_regs(). 2111 */ 2112 2113 /* When looking up a coprocessor register we look for it 2114 * via an integer which encodes all of: 2115 * coprocessor number 2116 * Crn, Crm, opc1, opc2 fields 2117 * 32 or 64 bit register (ie is it accessed via MRC/MCR 2118 * or via MRRC/MCRR?) 2119 * non-secure/secure bank (AArch32 only) 2120 * We allow 4 bits for opc1 because MRRC/MCRR have a 4 bit field. 2121 * (In this case crn and opc2 should be zero.) 2122 * For AArch64, there is no 32/64 bit size distinction; 2123 * instead all registers have a 2 bit op0, 3 bit op1 and op2, 2124 * and 4 bit CRn and CRm. The encoding patterns are chosen 2125 * to be easy to convert to and from the KVM encodings, and also 2126 * so that the hashtable can contain both AArch32 and AArch64 2127 * registers (to allow for interprocessing where we might run 2128 * 32 bit code on a 64 bit core). 2129 */ 2130 /* This bit is private to our hashtable cpreg; in KVM register 2131 * IDs the AArch64/32 distinction is the KVM_REG_ARM/ARM64 2132 * in the upper bits of the 64 bit ID. 2133 */ 2134 #define CP_REG_AA64_SHIFT 28 2135 #define CP_REG_AA64_MASK (1 << CP_REG_AA64_SHIFT) 2136 2137 /* To enable banking of coprocessor registers depending on ns-bit we 2138 * add a bit to distinguish between secure and non-secure cpregs in the 2139 * hashtable. 2140 */ 2141 #define CP_REG_NS_SHIFT 29 2142 #define CP_REG_NS_MASK (1 << CP_REG_NS_SHIFT) 2143 2144 #define ENCODE_CP_REG(cp, is64, ns, crn, crm, opc1, opc2) \ 2145 ((ns) << CP_REG_NS_SHIFT | ((cp) << 16) | ((is64) << 15) | \ 2146 ((crn) << 11) | ((crm) << 7) | ((opc1) << 3) | (opc2)) 2147 2148 #define ENCODE_AA64_CP_REG(cp, crn, crm, op0, op1, op2) \ 2149 (CP_REG_AA64_MASK | \ 2150 ((cp) << CP_REG_ARM_COPROC_SHIFT) | \ 2151 ((op0) << CP_REG_ARM64_SYSREG_OP0_SHIFT) | \ 2152 ((op1) << CP_REG_ARM64_SYSREG_OP1_SHIFT) | \ 2153 ((crn) << CP_REG_ARM64_SYSREG_CRN_SHIFT) | \ 2154 ((crm) << CP_REG_ARM64_SYSREG_CRM_SHIFT) | \ 2155 ((op2) << CP_REG_ARM64_SYSREG_OP2_SHIFT)) 2156 2157 /* Convert a full 64 bit KVM register ID to the truncated 32 bit 2158 * version used as a key for the coprocessor register hashtable 2159 */ 2160 static inline uint32_t kvm_to_cpreg_id(uint64_t kvmid) 2161 { 2162 uint32_t cpregid = kvmid; 2163 if ((kvmid & CP_REG_ARCH_MASK) == CP_REG_ARM64) { 2164 cpregid |= CP_REG_AA64_MASK; 2165 } else { 2166 if ((kvmid & CP_REG_SIZE_MASK) == CP_REG_SIZE_U64) { 2167 cpregid |= (1 << 15); 2168 } 2169 2170 /* KVM is always non-secure so add the NS flag on AArch32 register 2171 * entries. 2172 */ 2173 cpregid |= 1 << CP_REG_NS_SHIFT; 2174 } 2175 return cpregid; 2176 } 2177 2178 /* Convert a truncated 32 bit hashtable key into the full 2179 * 64 bit KVM register ID. 2180 */ 2181 static inline uint64_t cpreg_to_kvm_id(uint32_t cpregid) 2182 { 2183 uint64_t kvmid; 2184 2185 if (cpregid & CP_REG_AA64_MASK) { 2186 kvmid = cpregid & ~CP_REG_AA64_MASK; 2187 kvmid |= CP_REG_SIZE_U64 | CP_REG_ARM64; 2188 } else { 2189 kvmid = cpregid & ~(1 << 15); 2190 if (cpregid & (1 << 15)) { 2191 kvmid |= CP_REG_SIZE_U64 | CP_REG_ARM; 2192 } else { 2193 kvmid |= CP_REG_SIZE_U32 | CP_REG_ARM; 2194 } 2195 } 2196 return kvmid; 2197 } 2198 2199 /* ARMCPRegInfo type field bits. If the SPECIAL bit is set this is a 2200 * special-behaviour cp reg and bits [11..8] indicate what behaviour 2201 * it has. Otherwise it is a simple cp reg, where CONST indicates that 2202 * TCG can assume the value to be constant (ie load at translate time) 2203 * and 64BIT indicates a 64 bit wide coprocessor register. SUPPRESS_TB_END 2204 * indicates that the TB should not be ended after a write to this register 2205 * (the default is that the TB ends after cp writes). OVERRIDE permits 2206 * a register definition to override a previous definition for the 2207 * same (cp, is64, crn, crm, opc1, opc2) tuple: either the new or the 2208 * old must have the OVERRIDE bit set. 2209 * ALIAS indicates that this register is an alias view of some underlying 2210 * state which is also visible via another register, and that the other 2211 * register is handling migration and reset; registers marked ALIAS will not be 2212 * migrated but may have their state set by syncing of register state from KVM. 2213 * NO_RAW indicates that this register has no underlying state and does not 2214 * support raw access for state saving/loading; it will not be used for either 2215 * migration or KVM state synchronization. (Typically this is for "registers" 2216 * which are actually used as instructions for cache maintenance and so on.) 2217 * IO indicates that this register does I/O and therefore its accesses 2218 * need to be surrounded by gen_io_start()/gen_io_end(). In particular, 2219 * registers which implement clocks or timers require this. 2220 */ 2221 #define ARM_CP_SPECIAL 0x0001 2222 #define ARM_CP_CONST 0x0002 2223 #define ARM_CP_64BIT 0x0004 2224 #define ARM_CP_SUPPRESS_TB_END 0x0008 2225 #define ARM_CP_OVERRIDE 0x0010 2226 #define ARM_CP_ALIAS 0x0020 2227 #define ARM_CP_IO 0x0040 2228 #define ARM_CP_NO_RAW 0x0080 2229 #define ARM_CP_NOP (ARM_CP_SPECIAL | 0x0100) 2230 #define ARM_CP_WFI (ARM_CP_SPECIAL | 0x0200) 2231 #define ARM_CP_NZCV (ARM_CP_SPECIAL | 0x0300) 2232 #define ARM_CP_CURRENTEL (ARM_CP_SPECIAL | 0x0400) 2233 #define ARM_CP_DC_ZVA (ARM_CP_SPECIAL | 0x0500) 2234 #define ARM_LAST_SPECIAL ARM_CP_DC_ZVA 2235 #define ARM_CP_FPU 0x1000 2236 #define ARM_CP_SVE 0x2000 2237 #define ARM_CP_NO_GDB 0x4000 2238 /* Used only as a terminator for ARMCPRegInfo lists */ 2239 #define ARM_CP_SENTINEL 0xffff 2240 /* Mask of only the flag bits in a type field */ 2241 #define ARM_CP_FLAG_MASK 0x70ff 2242 2243 /* Valid values for ARMCPRegInfo state field, indicating which of 2244 * the AArch32 and AArch64 execution states this register is visible in. 2245 * If the reginfo doesn't explicitly specify then it is AArch32 only. 2246 * If the reginfo is declared to be visible in both states then a second 2247 * reginfo is synthesised for the AArch32 view of the AArch64 register, 2248 * such that the AArch32 view is the lower 32 bits of the AArch64 one. 2249 * Note that we rely on the values of these enums as we iterate through 2250 * the various states in some places. 2251 */ 2252 enum { 2253 ARM_CP_STATE_AA32 = 0, 2254 ARM_CP_STATE_AA64 = 1, 2255 ARM_CP_STATE_BOTH = 2, 2256 }; 2257 2258 /* ARM CP register secure state flags. These flags identify security state 2259 * attributes for a given CP register entry. 2260 * The existence of both or neither secure and non-secure flags indicates that 2261 * the register has both a secure and non-secure hash entry. A single one of 2262 * these flags causes the register to only be hashed for the specified 2263 * security state. 2264 * Although definitions may have any combination of the S/NS bits, each 2265 * registered entry will only have one to identify whether the entry is secure 2266 * or non-secure. 2267 */ 2268 enum { 2269 ARM_CP_SECSTATE_S = (1 << 0), /* bit[0]: Secure state register */ 2270 ARM_CP_SECSTATE_NS = (1 << 1), /* bit[1]: Non-secure state register */ 2271 }; 2272 2273 /* Return true if cptype is a valid type field. This is used to try to 2274 * catch errors where the sentinel has been accidentally left off the end 2275 * of a list of registers. 2276 */ 2277 static inline bool cptype_valid(int cptype) 2278 { 2279 return ((cptype & ~ARM_CP_FLAG_MASK) == 0) 2280 || ((cptype & ARM_CP_SPECIAL) && 2281 ((cptype & ~ARM_CP_FLAG_MASK) <= ARM_LAST_SPECIAL)); 2282 } 2283 2284 /* Access rights: 2285 * We define bits for Read and Write access for what rev C of the v7-AR ARM ARM 2286 * defines as PL0 (user), PL1 (fiq/irq/svc/abt/und/sys, ie privileged), and 2287 * PL2 (hyp). The other level which has Read and Write bits is Secure PL1 2288 * (ie any of the privileged modes in Secure state, or Monitor mode). 2289 * If a register is accessible in one privilege level it's always accessible 2290 * in higher privilege levels too. Since "Secure PL1" also follows this rule 2291 * (ie anything visible in PL2 is visible in S-PL1, some things are only 2292 * visible in S-PL1) but "Secure PL1" is a bit of a mouthful, we bend the 2293 * terminology a little and call this PL3. 2294 * In AArch64 things are somewhat simpler as the PLx bits line up exactly 2295 * with the ELx exception levels. 2296 * 2297 * If access permissions for a register are more complex than can be 2298 * described with these bits, then use a laxer set of restrictions, and 2299 * do the more restrictive/complex check inside a helper function. 2300 */ 2301 #define PL3_R 0x80 2302 #define PL3_W 0x40 2303 #define PL2_R (0x20 | PL3_R) 2304 #define PL2_W (0x10 | PL3_W) 2305 #define PL1_R (0x08 | PL2_R) 2306 #define PL1_W (0x04 | PL2_W) 2307 #define PL0_R (0x02 | PL1_R) 2308 #define PL0_W (0x01 | PL1_W) 2309 2310 /* 2311 * For user-mode some registers are accessible to EL0 via a kernel 2312 * trap-and-emulate ABI. In this case we define the read permissions 2313 * as actually being PL0_R. However some bits of any given register 2314 * may still be masked. 2315 */ 2316 #ifdef CONFIG_USER_ONLY 2317 #define PL0U_R PL0_R 2318 #else 2319 #define PL0U_R PL1_R 2320 #endif 2321 2322 #define PL3_RW (PL3_R | PL3_W) 2323 #define PL2_RW (PL2_R | PL2_W) 2324 #define PL1_RW (PL1_R | PL1_W) 2325 #define PL0_RW (PL0_R | PL0_W) 2326 2327 /* Return the highest implemented Exception Level */ 2328 static inline int arm_highest_el(CPUARMState *env) 2329 { 2330 if (arm_feature(env, ARM_FEATURE_EL3)) { 2331 return 3; 2332 } 2333 if (arm_feature(env, ARM_FEATURE_EL2)) { 2334 return 2; 2335 } 2336 return 1; 2337 } 2338 2339 /* Return true if a v7M CPU is in Handler mode */ 2340 static inline bool arm_v7m_is_handler_mode(CPUARMState *env) 2341 { 2342 return env->v7m.exception != 0; 2343 } 2344 2345 /* Return the current Exception Level (as per ARMv8; note that this differs 2346 * from the ARMv7 Privilege Level). 2347 */ 2348 static inline int arm_current_el(CPUARMState *env) 2349 { 2350 if (arm_feature(env, ARM_FEATURE_M)) { 2351 return arm_v7m_is_handler_mode(env) || 2352 !(env->v7m.control[env->v7m.secure] & 1); 2353 } 2354 2355 if (is_a64(env)) { 2356 return extract32(env->pstate, 2, 2); 2357 } 2358 2359 switch (env->uncached_cpsr & 0x1f) { 2360 case ARM_CPU_MODE_USR: 2361 return 0; 2362 case ARM_CPU_MODE_HYP: 2363 return 2; 2364 case ARM_CPU_MODE_MON: 2365 return 3; 2366 default: 2367 if (arm_is_secure(env) && !arm_el_is_aa64(env, 3)) { 2368 /* If EL3 is 32-bit then all secure privileged modes run in 2369 * EL3 2370 */ 2371 return 3; 2372 } 2373 2374 return 1; 2375 } 2376 } 2377 2378 typedef struct ARMCPRegInfo ARMCPRegInfo; 2379 2380 typedef enum CPAccessResult { 2381 /* Access is permitted */ 2382 CP_ACCESS_OK = 0, 2383 /* Access fails due to a configurable trap or enable which would 2384 * result in a categorized exception syndrome giving information about 2385 * the failing instruction (ie syndrome category 0x3, 0x4, 0x5, 0x6, 2386 * 0xc or 0x18). The exception is taken to the usual target EL (EL1 or 2387 * PL1 if in EL0, otherwise to the current EL). 2388 */ 2389 CP_ACCESS_TRAP = 1, 2390 /* Access fails and results in an exception syndrome 0x0 ("uncategorized"). 2391 * Note that this is not a catch-all case -- the set of cases which may 2392 * result in this failure is specifically defined by the architecture. 2393 */ 2394 CP_ACCESS_TRAP_UNCATEGORIZED = 2, 2395 /* As CP_ACCESS_TRAP, but for traps directly to EL2 or EL3 */ 2396 CP_ACCESS_TRAP_EL2 = 3, 2397 CP_ACCESS_TRAP_EL3 = 4, 2398 /* As CP_ACCESS_UNCATEGORIZED, but for traps directly to EL2 or EL3 */ 2399 CP_ACCESS_TRAP_UNCATEGORIZED_EL2 = 5, 2400 CP_ACCESS_TRAP_UNCATEGORIZED_EL3 = 6, 2401 /* Access fails and results in an exception syndrome for an FP access, 2402 * trapped directly to EL2 or EL3 2403 */ 2404 CP_ACCESS_TRAP_FP_EL2 = 7, 2405 CP_ACCESS_TRAP_FP_EL3 = 8, 2406 } CPAccessResult; 2407 2408 /* Access functions for coprocessor registers. These cannot fail and 2409 * may not raise exceptions. 2410 */ 2411 typedef uint64_t CPReadFn(CPUARMState *env, const ARMCPRegInfo *opaque); 2412 typedef void CPWriteFn(CPUARMState *env, const ARMCPRegInfo *opaque, 2413 uint64_t value); 2414 /* Access permission check functions for coprocessor registers. */ 2415 typedef CPAccessResult CPAccessFn(CPUARMState *env, 2416 const ARMCPRegInfo *opaque, 2417 bool isread); 2418 /* Hook function for register reset */ 2419 typedef void CPResetFn(CPUARMState *env, const ARMCPRegInfo *opaque); 2420 2421 #define CP_ANY 0xff 2422 2423 /* Definition of an ARM coprocessor register */ 2424 struct ARMCPRegInfo { 2425 /* Name of register (useful mainly for debugging, need not be unique) */ 2426 const char *name; 2427 /* Location of register: coprocessor number and (crn,crm,opc1,opc2) 2428 * tuple. Any of crm, opc1 and opc2 may be CP_ANY to indicate a 2429 * 'wildcard' field -- any value of that field in the MRC/MCR insn 2430 * will be decoded to this register. The register read and write 2431 * callbacks will be passed an ARMCPRegInfo with the crn/crm/opc1/opc2 2432 * used by the program, so it is possible to register a wildcard and 2433 * then behave differently on read/write if necessary. 2434 * For 64 bit registers, only crm and opc1 are relevant; crn and opc2 2435 * must both be zero. 2436 * For AArch64-visible registers, opc0 is also used. 2437 * Since there are no "coprocessors" in AArch64, cp is purely used as a 2438 * way to distinguish (for KVM's benefit) guest-visible system registers 2439 * from demuxed ones provided to preserve the "no side effects on 2440 * KVM register read/write from QEMU" semantics. cp==0x13 is guest 2441 * visible (to match KVM's encoding); cp==0 will be converted to 2442 * cp==0x13 when the ARMCPRegInfo is registered, for convenience. 2443 */ 2444 uint8_t cp; 2445 uint8_t crn; 2446 uint8_t crm; 2447 uint8_t opc0; 2448 uint8_t opc1; 2449 uint8_t opc2; 2450 /* Execution state in which this register is visible: ARM_CP_STATE_* */ 2451 int state; 2452 /* Register type: ARM_CP_* bits/values */ 2453 int type; 2454 /* Access rights: PL*_[RW] */ 2455 int access; 2456 /* Security state: ARM_CP_SECSTATE_* bits/values */ 2457 int secure; 2458 /* The opaque pointer passed to define_arm_cp_regs_with_opaque() when 2459 * this register was defined: can be used to hand data through to the 2460 * register read/write functions, since they are passed the ARMCPRegInfo*. 2461 */ 2462 void *opaque; 2463 /* Value of this register, if it is ARM_CP_CONST. Otherwise, if 2464 * fieldoffset is non-zero, the reset value of the register. 2465 */ 2466 uint64_t resetvalue; 2467 /* Offset of the field in CPUARMState for this register. 2468 * 2469 * This is not needed if either: 2470 * 1. type is ARM_CP_CONST or one of the ARM_CP_SPECIALs 2471 * 2. both readfn and writefn are specified 2472 */ 2473 ptrdiff_t fieldoffset; /* offsetof(CPUARMState, field) */ 2474 2475 /* Offsets of the secure and non-secure fields in CPUARMState for the 2476 * register if it is banked. These fields are only used during the static 2477 * registration of a register. During hashing the bank associated 2478 * with a given security state is copied to fieldoffset which is used from 2479 * there on out. 2480 * 2481 * It is expected that register definitions use either fieldoffset or 2482 * bank_fieldoffsets in the definition but not both. It is also expected 2483 * that both bank offsets are set when defining a banked register. This 2484 * use indicates that a register is banked. 2485 */ 2486 ptrdiff_t bank_fieldoffsets[2]; 2487 2488 /* Function for making any access checks for this register in addition to 2489 * those specified by the 'access' permissions bits. If NULL, no extra 2490 * checks required. The access check is performed at runtime, not at 2491 * translate time. 2492 */ 2493 CPAccessFn *accessfn; 2494 /* Function for handling reads of this register. If NULL, then reads 2495 * will be done by loading from the offset into CPUARMState specified 2496 * by fieldoffset. 2497 */ 2498 CPReadFn *readfn; 2499 /* Function for handling writes of this register. If NULL, then writes 2500 * will be done by writing to the offset into CPUARMState specified 2501 * by fieldoffset. 2502 */ 2503 CPWriteFn *writefn; 2504 /* Function for doing a "raw" read; used when we need to copy 2505 * coprocessor state to the kernel for KVM or out for 2506 * migration. This only needs to be provided if there is also a 2507 * readfn and it has side effects (for instance clear-on-read bits). 2508 */ 2509 CPReadFn *raw_readfn; 2510 /* Function for doing a "raw" write; used when we need to copy KVM 2511 * kernel coprocessor state into userspace, or for inbound 2512 * migration. This only needs to be provided if there is also a 2513 * writefn and it masks out "unwritable" bits or has write-one-to-clear 2514 * or similar behaviour. 2515 */ 2516 CPWriteFn *raw_writefn; 2517 /* Function for resetting the register. If NULL, then reset will be done 2518 * by writing resetvalue to the field specified in fieldoffset. If 2519 * fieldoffset is 0 then no reset will be done. 2520 */ 2521 CPResetFn *resetfn; 2522 }; 2523 2524 /* Macros which are lvalues for the field in CPUARMState for the 2525 * ARMCPRegInfo *ri. 2526 */ 2527 #define CPREG_FIELD32(env, ri) \ 2528 (*(uint32_t *)((char *)(env) + (ri)->fieldoffset)) 2529 #define CPREG_FIELD64(env, ri) \ 2530 (*(uint64_t *)((char *)(env) + (ri)->fieldoffset)) 2531 2532 #define REGINFO_SENTINEL { .type = ARM_CP_SENTINEL } 2533 2534 void define_arm_cp_regs_with_opaque(ARMCPU *cpu, 2535 const ARMCPRegInfo *regs, void *opaque); 2536 void define_one_arm_cp_reg_with_opaque(ARMCPU *cpu, 2537 const ARMCPRegInfo *regs, void *opaque); 2538 static inline void define_arm_cp_regs(ARMCPU *cpu, const ARMCPRegInfo *regs) 2539 { 2540 define_arm_cp_regs_with_opaque(cpu, regs, 0); 2541 } 2542 static inline void define_one_arm_cp_reg(ARMCPU *cpu, const ARMCPRegInfo *regs) 2543 { 2544 define_one_arm_cp_reg_with_opaque(cpu, regs, 0); 2545 } 2546 const ARMCPRegInfo *get_arm_cp_reginfo(GHashTable *cpregs, uint32_t encoded_cp); 2547 2548 /* 2549 * Definition of an ARM co-processor register as viewed from 2550 * userspace. This is used for presenting sanitised versions of 2551 * registers to userspace when emulating the Linux AArch64 CPU 2552 * ID/feature ABI (advertised as HWCAP_CPUID). 2553 */ 2554 typedef struct ARMCPRegUserSpaceInfo { 2555 /* Name of register */ 2556 const char *name; 2557 2558 /* Is the name actually a glob pattern */ 2559 bool is_glob; 2560 2561 /* Only some bits are exported to user space */ 2562 uint64_t exported_bits; 2563 2564 /* Fixed bits are applied after the mask */ 2565 uint64_t fixed_bits; 2566 } ARMCPRegUserSpaceInfo; 2567 2568 #define REGUSERINFO_SENTINEL { .name = NULL } 2569 2570 void modify_arm_cp_regs(ARMCPRegInfo *regs, const ARMCPRegUserSpaceInfo *mods); 2571 2572 /* CPWriteFn that can be used to implement writes-ignored behaviour */ 2573 void arm_cp_write_ignore(CPUARMState *env, const ARMCPRegInfo *ri, 2574 uint64_t value); 2575 /* CPReadFn that can be used for read-as-zero behaviour */ 2576 uint64_t arm_cp_read_zero(CPUARMState *env, const ARMCPRegInfo *ri); 2577 2578 /* CPResetFn that does nothing, for use if no reset is required even 2579 * if fieldoffset is non zero. 2580 */ 2581 void arm_cp_reset_ignore(CPUARMState *env, const ARMCPRegInfo *opaque); 2582 2583 /* Return true if this reginfo struct's field in the cpu state struct 2584 * is 64 bits wide. 2585 */ 2586 static inline bool cpreg_field_is_64bit(const ARMCPRegInfo *ri) 2587 { 2588 return (ri->state == ARM_CP_STATE_AA64) || (ri->type & ARM_CP_64BIT); 2589 } 2590 2591 static inline bool cp_access_ok(int current_el, 2592 const ARMCPRegInfo *ri, int isread) 2593 { 2594 return (ri->access >> ((current_el * 2) + isread)) & 1; 2595 } 2596 2597 /* Raw read of a coprocessor register (as needed for migration, etc) */ 2598 uint64_t read_raw_cp_reg(CPUARMState *env, const ARMCPRegInfo *ri); 2599 2600 /** 2601 * write_list_to_cpustate 2602 * @cpu: ARMCPU 2603 * 2604 * For each register listed in the ARMCPU cpreg_indexes list, write 2605 * its value from the cpreg_values list into the ARMCPUState structure. 2606 * This updates TCG's working data structures from KVM data or 2607 * from incoming migration state. 2608 * 2609 * Returns: true if all register values were updated correctly, 2610 * false if some register was unknown or could not be written. 2611 * Note that we do not stop early on failure -- we will attempt 2612 * writing all registers in the list. 2613 */ 2614 bool write_list_to_cpustate(ARMCPU *cpu); 2615 2616 /** 2617 * write_cpustate_to_list: 2618 * @cpu: ARMCPU 2619 * @kvm_sync: true if this is for syncing back to KVM 2620 * 2621 * For each register listed in the ARMCPU cpreg_indexes list, write 2622 * its value from the ARMCPUState structure into the cpreg_values list. 2623 * This is used to copy info from TCG's working data structures into 2624 * KVM or for outbound migration. 2625 * 2626 * @kvm_sync is true if we are doing this in order to sync the 2627 * register state back to KVM. In this case we will only update 2628 * values in the list if the previous list->cpustate sync actually 2629 * successfully wrote the CPU state. Otherwise we will keep the value 2630 * that is in the list. 2631 * 2632 * Returns: true if all register values were read correctly, 2633 * false if some register was unknown or could not be read. 2634 * Note that we do not stop early on failure -- we will attempt 2635 * reading all registers in the list. 2636 */ 2637 bool write_cpustate_to_list(ARMCPU *cpu, bool kvm_sync); 2638 2639 #define ARM_CPUID_TI915T 0x54029152 2640 #define ARM_CPUID_TI925T 0x54029252 2641 2642 #if defined(CONFIG_USER_ONLY) 2643 #define TARGET_PAGE_BITS 12 2644 #else 2645 /* ARMv7 and later CPUs have 4K pages minimum, but ARMv5 and v6 2646 * have to support 1K tiny pages. 2647 */ 2648 #define TARGET_PAGE_BITS_VARY 2649 #define TARGET_PAGE_BITS_MIN 10 2650 #endif 2651 2652 #if defined(TARGET_AARCH64) 2653 # define TARGET_PHYS_ADDR_SPACE_BITS 48 2654 # define TARGET_VIRT_ADDR_SPACE_BITS 48 2655 #else 2656 # define TARGET_PHYS_ADDR_SPACE_BITS 40 2657 # define TARGET_VIRT_ADDR_SPACE_BITS 32 2658 #endif 2659 2660 static inline bool arm_excp_unmasked(CPUState *cs, unsigned int excp_idx, 2661 unsigned int target_el) 2662 { 2663 CPUARMState *env = cs->env_ptr; 2664 unsigned int cur_el = arm_current_el(env); 2665 bool secure = arm_is_secure(env); 2666 bool pstate_unmasked; 2667 int8_t unmasked = 0; 2668 uint64_t hcr_el2; 2669 2670 /* Don't take exceptions if they target a lower EL. 2671 * This check should catch any exceptions that would not be taken but left 2672 * pending. 2673 */ 2674 if (cur_el > target_el) { 2675 return false; 2676 } 2677 2678 hcr_el2 = arm_hcr_el2_eff(env); 2679 2680 switch (excp_idx) { 2681 case EXCP_FIQ: 2682 pstate_unmasked = !(env->daif & PSTATE_F); 2683 break; 2684 2685 case EXCP_IRQ: 2686 pstate_unmasked = !(env->daif & PSTATE_I); 2687 break; 2688 2689 case EXCP_VFIQ: 2690 if (secure || !(hcr_el2 & HCR_FMO) || (hcr_el2 & HCR_TGE)) { 2691 /* VFIQs are only taken when hypervized and non-secure. */ 2692 return false; 2693 } 2694 return !(env->daif & PSTATE_F); 2695 case EXCP_VIRQ: 2696 if (secure || !(hcr_el2 & HCR_IMO) || (hcr_el2 & HCR_TGE)) { 2697 /* VIRQs are only taken when hypervized and non-secure. */ 2698 return false; 2699 } 2700 return !(env->daif & PSTATE_I); 2701 default: 2702 g_assert_not_reached(); 2703 } 2704 2705 /* Use the target EL, current execution state and SCR/HCR settings to 2706 * determine whether the corresponding CPSR bit is used to mask the 2707 * interrupt. 2708 */ 2709 if ((target_el > cur_el) && (target_el != 1)) { 2710 /* Exceptions targeting a higher EL may not be maskable */ 2711 if (arm_feature(env, ARM_FEATURE_AARCH64)) { 2712 /* 64-bit masking rules are simple: exceptions to EL3 2713 * can't be masked, and exceptions to EL2 can only be 2714 * masked from Secure state. The HCR and SCR settings 2715 * don't affect the masking logic, only the interrupt routing. 2716 */ 2717 if (target_el == 3 || !secure) { 2718 unmasked = 1; 2719 } 2720 } else { 2721 /* The old 32-bit-only environment has a more complicated 2722 * masking setup. HCR and SCR bits not only affect interrupt 2723 * routing but also change the behaviour of masking. 2724 */ 2725 bool hcr, scr; 2726 2727 switch (excp_idx) { 2728 case EXCP_FIQ: 2729 /* If FIQs are routed to EL3 or EL2 then there are cases where 2730 * we override the CPSR.F in determining if the exception is 2731 * masked or not. If neither of these are set then we fall back 2732 * to the CPSR.F setting otherwise we further assess the state 2733 * below. 2734 */ 2735 hcr = hcr_el2 & HCR_FMO; 2736 scr = (env->cp15.scr_el3 & SCR_FIQ); 2737 2738 /* When EL3 is 32-bit, the SCR.FW bit controls whether the 2739 * CPSR.F bit masks FIQ interrupts when taken in non-secure 2740 * state. If SCR.FW is set then FIQs can be masked by CPSR.F 2741 * when non-secure but only when FIQs are only routed to EL3. 2742 */ 2743 scr = scr && !((env->cp15.scr_el3 & SCR_FW) && !hcr); 2744 break; 2745 case EXCP_IRQ: 2746 /* When EL3 execution state is 32-bit, if HCR.IMO is set then 2747 * we may override the CPSR.I masking when in non-secure state. 2748 * The SCR.IRQ setting has already been taken into consideration 2749 * when setting the target EL, so it does not have a further 2750 * affect here. 2751 */ 2752 hcr = hcr_el2 & HCR_IMO; 2753 scr = false; 2754 break; 2755 default: 2756 g_assert_not_reached(); 2757 } 2758 2759 if ((scr || hcr) && !secure) { 2760 unmasked = 1; 2761 } 2762 } 2763 } 2764 2765 /* The PSTATE bits only mask the interrupt if we have not overriden the 2766 * ability above. 2767 */ 2768 return unmasked || pstate_unmasked; 2769 } 2770 2771 #define ARM_CPU_TYPE_SUFFIX "-" TYPE_ARM_CPU 2772 #define ARM_CPU_TYPE_NAME(name) (name ARM_CPU_TYPE_SUFFIX) 2773 #define CPU_RESOLVING_TYPE TYPE_ARM_CPU 2774 2775 #define cpu_signal_handler cpu_arm_signal_handler 2776 #define cpu_list arm_cpu_list 2777 2778 /* ARM has the following "translation regimes" (as the ARM ARM calls them): 2779 * 2780 * If EL3 is 64-bit: 2781 * + NonSecure EL1 & 0 stage 1 2782 * + NonSecure EL1 & 0 stage 2 2783 * + NonSecure EL2 2784 * + Secure EL1 & EL0 2785 * + Secure EL3 2786 * If EL3 is 32-bit: 2787 * + NonSecure PL1 & 0 stage 1 2788 * + NonSecure PL1 & 0 stage 2 2789 * + NonSecure PL2 2790 * + Secure PL0 & PL1 2791 * (reminder: for 32 bit EL3, Secure PL1 is *EL3*, not EL1.) 2792 * 2793 * For QEMU, an mmu_idx is not quite the same as a translation regime because: 2794 * 1. we need to split the "EL1 & 0" regimes into two mmu_idxes, because they 2795 * may differ in access permissions even if the VA->PA map is the same 2796 * 2. we want to cache in our TLB the full VA->IPA->PA lookup for a stage 1+2 2797 * translation, which means that we have one mmu_idx that deals with two 2798 * concatenated translation regimes [this sort of combined s1+2 TLB is 2799 * architecturally permitted] 2800 * 3. we don't need to allocate an mmu_idx to translations that we won't be 2801 * handling via the TLB. The only way to do a stage 1 translation without 2802 * the immediate stage 2 translation is via the ATS or AT system insns, 2803 * which can be slow-pathed and always do a page table walk. 2804 * 4. we can also safely fold together the "32 bit EL3" and "64 bit EL3" 2805 * translation regimes, because they map reasonably well to each other 2806 * and they can't both be active at the same time. 2807 * This gives us the following list of mmu_idx values: 2808 * 2809 * NS EL0 (aka NS PL0) stage 1+2 2810 * NS EL1 (aka NS PL1) stage 1+2 2811 * NS EL2 (aka NS PL2) 2812 * S EL3 (aka S PL1) 2813 * S EL0 (aka S PL0) 2814 * S EL1 (not used if EL3 is 32 bit) 2815 * NS EL0+1 stage 2 2816 * 2817 * (The last of these is an mmu_idx because we want to be able to use the TLB 2818 * for the accesses done as part of a stage 1 page table walk, rather than 2819 * having to walk the stage 2 page table over and over.) 2820 * 2821 * R profile CPUs have an MPU, but can use the same set of MMU indexes 2822 * as A profile. They only need to distinguish NS EL0 and NS EL1 (and 2823 * NS EL2 if we ever model a Cortex-R52). 2824 * 2825 * M profile CPUs are rather different as they do not have a true MMU. 2826 * They have the following different MMU indexes: 2827 * User 2828 * Privileged 2829 * User, execution priority negative (ie the MPU HFNMIENA bit may apply) 2830 * Privileged, execution priority negative (ditto) 2831 * If the CPU supports the v8M Security Extension then there are also: 2832 * Secure User 2833 * Secure Privileged 2834 * Secure User, execution priority negative 2835 * Secure Privileged, execution priority negative 2836 * 2837 * The ARMMMUIdx and the mmu index value used by the core QEMU TLB code 2838 * are not quite the same -- different CPU types (most notably M profile 2839 * vs A/R profile) would like to use MMU indexes with different semantics, 2840 * but since we don't ever need to use all of those in a single CPU we 2841 * can avoid setting NB_MMU_MODES to more than 8. The lower bits of 2842 * ARMMMUIdx are the core TLB mmu index, and the higher bits are always 2843 * the same for any particular CPU. 2844 * Variables of type ARMMUIdx are always full values, and the core 2845 * index values are in variables of type 'int'. 2846 * 2847 * Our enumeration includes at the end some entries which are not "true" 2848 * mmu_idx values in that they don't have corresponding TLBs and are only 2849 * valid for doing slow path page table walks. 2850 * 2851 * The constant names here are patterned after the general style of the names 2852 * of the AT/ATS operations. 2853 * The values used are carefully arranged to make mmu_idx => EL lookup easy. 2854 * For M profile we arrange them to have a bit for priv, a bit for negpri 2855 * and a bit for secure. 2856 */ 2857 #define ARM_MMU_IDX_A 0x10 /* A profile */ 2858 #define ARM_MMU_IDX_NOTLB 0x20 /* does not have a TLB */ 2859 #define ARM_MMU_IDX_M 0x40 /* M profile */ 2860 2861 /* meanings of the bits for M profile mmu idx values */ 2862 #define ARM_MMU_IDX_M_PRIV 0x1 2863 #define ARM_MMU_IDX_M_NEGPRI 0x2 2864 #define ARM_MMU_IDX_M_S 0x4 2865 2866 #define ARM_MMU_IDX_TYPE_MASK (~0x7) 2867 #define ARM_MMU_IDX_COREIDX_MASK 0x7 2868 2869 typedef enum ARMMMUIdx { 2870 ARMMMUIdx_S12NSE0 = 0 | ARM_MMU_IDX_A, 2871 ARMMMUIdx_S12NSE1 = 1 | ARM_MMU_IDX_A, 2872 ARMMMUIdx_S1E2 = 2 | ARM_MMU_IDX_A, 2873 ARMMMUIdx_S1E3 = 3 | ARM_MMU_IDX_A, 2874 ARMMMUIdx_S1SE0 = 4 | ARM_MMU_IDX_A, 2875 ARMMMUIdx_S1SE1 = 5 | ARM_MMU_IDX_A, 2876 ARMMMUIdx_S2NS = 6 | ARM_MMU_IDX_A, 2877 ARMMMUIdx_MUser = 0 | ARM_MMU_IDX_M, 2878 ARMMMUIdx_MPriv = 1 | ARM_MMU_IDX_M, 2879 ARMMMUIdx_MUserNegPri = 2 | ARM_MMU_IDX_M, 2880 ARMMMUIdx_MPrivNegPri = 3 | ARM_MMU_IDX_M, 2881 ARMMMUIdx_MSUser = 4 | ARM_MMU_IDX_M, 2882 ARMMMUIdx_MSPriv = 5 | ARM_MMU_IDX_M, 2883 ARMMMUIdx_MSUserNegPri = 6 | ARM_MMU_IDX_M, 2884 ARMMMUIdx_MSPrivNegPri = 7 | ARM_MMU_IDX_M, 2885 /* Indexes below here don't have TLBs and are used only for AT system 2886 * instructions or for the first stage of an S12 page table walk. 2887 */ 2888 ARMMMUIdx_S1NSE0 = 0 | ARM_MMU_IDX_NOTLB, 2889 ARMMMUIdx_S1NSE1 = 1 | ARM_MMU_IDX_NOTLB, 2890 } ARMMMUIdx; 2891 2892 /* Bit macros for the core-mmu-index values for each index, 2893 * for use when calling tlb_flush_by_mmuidx() and friends. 2894 */ 2895 typedef enum ARMMMUIdxBit { 2896 ARMMMUIdxBit_S12NSE0 = 1 << 0, 2897 ARMMMUIdxBit_S12NSE1 = 1 << 1, 2898 ARMMMUIdxBit_S1E2 = 1 << 2, 2899 ARMMMUIdxBit_S1E3 = 1 << 3, 2900 ARMMMUIdxBit_S1SE0 = 1 << 4, 2901 ARMMMUIdxBit_S1SE1 = 1 << 5, 2902 ARMMMUIdxBit_S2NS = 1 << 6, 2903 ARMMMUIdxBit_MUser = 1 << 0, 2904 ARMMMUIdxBit_MPriv = 1 << 1, 2905 ARMMMUIdxBit_MUserNegPri = 1 << 2, 2906 ARMMMUIdxBit_MPrivNegPri = 1 << 3, 2907 ARMMMUIdxBit_MSUser = 1 << 4, 2908 ARMMMUIdxBit_MSPriv = 1 << 5, 2909 ARMMMUIdxBit_MSUserNegPri = 1 << 6, 2910 ARMMMUIdxBit_MSPrivNegPri = 1 << 7, 2911 } ARMMMUIdxBit; 2912 2913 #define MMU_USER_IDX 0 2914 2915 static inline int arm_to_core_mmu_idx(ARMMMUIdx mmu_idx) 2916 { 2917 return mmu_idx & ARM_MMU_IDX_COREIDX_MASK; 2918 } 2919 2920 static inline ARMMMUIdx core_to_arm_mmu_idx(CPUARMState *env, int mmu_idx) 2921 { 2922 if (arm_feature(env, ARM_FEATURE_M)) { 2923 return mmu_idx | ARM_MMU_IDX_M; 2924 } else { 2925 return mmu_idx | ARM_MMU_IDX_A; 2926 } 2927 } 2928 2929 /* Return the exception level we're running at if this is our mmu_idx */ 2930 static inline int arm_mmu_idx_to_el(ARMMMUIdx mmu_idx) 2931 { 2932 switch (mmu_idx & ARM_MMU_IDX_TYPE_MASK) { 2933 case ARM_MMU_IDX_A: 2934 return mmu_idx & 3; 2935 case ARM_MMU_IDX_M: 2936 return mmu_idx & ARM_MMU_IDX_M_PRIV; 2937 default: 2938 g_assert_not_reached(); 2939 } 2940 } 2941 2942 /* 2943 * Return the MMU index for a v7M CPU with all relevant information 2944 * manually specified. 2945 */ 2946 ARMMMUIdx arm_v7m_mmu_idx_all(CPUARMState *env, 2947 bool secstate, bool priv, bool negpri); 2948 2949 /* Return the MMU index for a v7M CPU in the specified security and 2950 * privilege state. 2951 */ 2952 ARMMMUIdx arm_v7m_mmu_idx_for_secstate_and_priv(CPUARMState *env, 2953 bool secstate, bool priv); 2954 2955 /* Return the MMU index for a v7M CPU in the specified security state */ 2956 ARMMMUIdx arm_v7m_mmu_idx_for_secstate(CPUARMState *env, bool secstate); 2957 2958 /** 2959 * cpu_mmu_index: 2960 * @env: The cpu environment 2961 * @ifetch: True for code access, false for data access. 2962 * 2963 * Return the core mmu index for the current translation regime. 2964 * This function is used by generic TCG code paths. 2965 */ 2966 int cpu_mmu_index(CPUARMState *env, bool ifetch); 2967 2968 /* Indexes used when registering address spaces with cpu_address_space_init */ 2969 typedef enum ARMASIdx { 2970 ARMASIdx_NS = 0, 2971 ARMASIdx_S = 1, 2972 } ARMASIdx; 2973 2974 /* Return the Exception Level targeted by debug exceptions. */ 2975 static inline int arm_debug_target_el(CPUARMState *env) 2976 { 2977 bool secure = arm_is_secure(env); 2978 bool route_to_el2 = false; 2979 2980 if (arm_feature(env, ARM_FEATURE_EL2) && !secure) { 2981 route_to_el2 = env->cp15.hcr_el2 & HCR_TGE || 2982 env->cp15.mdcr_el2 & MDCR_TDE; 2983 } 2984 2985 if (route_to_el2) { 2986 return 2; 2987 } else if (arm_feature(env, ARM_FEATURE_EL3) && 2988 !arm_el_is_aa64(env, 3) && secure) { 2989 return 3; 2990 } else { 2991 return 1; 2992 } 2993 } 2994 2995 static inline bool arm_v7m_csselr_razwi(ARMCPU *cpu) 2996 { 2997 /* If all the CLIDR.Ctypem bits are 0 there are no caches, and 2998 * CSSELR is RAZ/WI. 2999 */ 3000 return (cpu->clidr & R_V7M_CLIDR_CTYPE_ALL_MASK) != 0; 3001 } 3002 3003 /* See AArch64.GenerateDebugExceptionsFrom() in ARM ARM pseudocode */ 3004 static inline bool aa64_generate_debug_exceptions(CPUARMState *env) 3005 { 3006 int cur_el = arm_current_el(env); 3007 int debug_el; 3008 3009 if (cur_el == 3) { 3010 return false; 3011 } 3012 3013 /* MDCR_EL3.SDD disables debug events from Secure state */ 3014 if (arm_is_secure_below_el3(env) 3015 && extract32(env->cp15.mdcr_el3, 16, 1)) { 3016 return false; 3017 } 3018 3019 /* 3020 * Same EL to same EL debug exceptions need MDSCR_KDE enabled 3021 * while not masking the (D)ebug bit in DAIF. 3022 */ 3023 debug_el = arm_debug_target_el(env); 3024 3025 if (cur_el == debug_el) { 3026 return extract32(env->cp15.mdscr_el1, 13, 1) 3027 && !(env->daif & PSTATE_D); 3028 } 3029 3030 /* Otherwise the debug target needs to be a higher EL */ 3031 return debug_el > cur_el; 3032 } 3033 3034 static inline bool aa32_generate_debug_exceptions(CPUARMState *env) 3035 { 3036 int el = arm_current_el(env); 3037 3038 if (el == 0 && arm_el_is_aa64(env, 1)) { 3039 return aa64_generate_debug_exceptions(env); 3040 } 3041 3042 if (arm_is_secure(env)) { 3043 int spd; 3044 3045 if (el == 0 && (env->cp15.sder & 1)) { 3046 /* SDER.SUIDEN means debug exceptions from Secure EL0 3047 * are always enabled. Otherwise they are controlled by 3048 * SDCR.SPD like those from other Secure ELs. 3049 */ 3050 return true; 3051 } 3052 3053 spd = extract32(env->cp15.mdcr_el3, 14, 2); 3054 switch (spd) { 3055 case 1: 3056 /* SPD == 0b01 is reserved, but behaves as 0b00. */ 3057 case 0: 3058 /* For 0b00 we return true if external secure invasive debug 3059 * is enabled. On real hardware this is controlled by external 3060 * signals to the core. QEMU always permits debug, and behaves 3061 * as if DBGEN, SPIDEN, NIDEN and SPNIDEN are all tied high. 3062 */ 3063 return true; 3064 case 2: 3065 return false; 3066 case 3: 3067 return true; 3068 } 3069 } 3070 3071 return el != 2; 3072 } 3073 3074 /* Return true if debugging exceptions are currently enabled. 3075 * This corresponds to what in ARM ARM pseudocode would be 3076 * if UsingAArch32() then 3077 * return AArch32.GenerateDebugExceptions() 3078 * else 3079 * return AArch64.GenerateDebugExceptions() 3080 * We choose to push the if() down into this function for clarity, 3081 * since the pseudocode has it at all callsites except for the one in 3082 * CheckSoftwareStep(), where it is elided because both branches would 3083 * always return the same value. 3084 */ 3085 static inline bool arm_generate_debug_exceptions(CPUARMState *env) 3086 { 3087 if (env->aarch64) { 3088 return aa64_generate_debug_exceptions(env); 3089 } else { 3090 return aa32_generate_debug_exceptions(env); 3091 } 3092 } 3093 3094 /* Is single-stepping active? (Note that the "is EL_D AArch64?" check 3095 * implicitly means this always returns false in pre-v8 CPUs.) 3096 */ 3097 static inline bool arm_singlestep_active(CPUARMState *env) 3098 { 3099 return extract32(env->cp15.mdscr_el1, 0, 1) 3100 && arm_el_is_aa64(env, arm_debug_target_el(env)) 3101 && arm_generate_debug_exceptions(env); 3102 } 3103 3104 static inline bool arm_sctlr_b(CPUARMState *env) 3105 { 3106 return 3107 /* We need not implement SCTLR.ITD in user-mode emulation, so 3108 * let linux-user ignore the fact that it conflicts with SCTLR_B. 3109 * This lets people run BE32 binaries with "-cpu any". 3110 */ 3111 #ifndef CONFIG_USER_ONLY 3112 !arm_feature(env, ARM_FEATURE_V7) && 3113 #endif 3114 (env->cp15.sctlr_el[1] & SCTLR_B) != 0; 3115 } 3116 3117 static inline uint64_t arm_sctlr(CPUARMState *env, int el) 3118 { 3119 if (el == 0) { 3120 /* FIXME: ARMv8.1-VHE S2 translation regime. */ 3121 return env->cp15.sctlr_el[1]; 3122 } else { 3123 return env->cp15.sctlr_el[el]; 3124 } 3125 } 3126 3127 3128 /* Return true if the processor is in big-endian mode. */ 3129 static inline bool arm_cpu_data_is_big_endian(CPUARMState *env) 3130 { 3131 /* In 32bit endianness is determined by looking at CPSR's E bit */ 3132 if (!is_a64(env)) { 3133 return 3134 #ifdef CONFIG_USER_ONLY 3135 /* In system mode, BE32 is modelled in line with the 3136 * architecture (as word-invariant big-endianness), where loads 3137 * and stores are done little endian but from addresses which 3138 * are adjusted by XORing with the appropriate constant. So the 3139 * endianness to use for the raw data access is not affected by 3140 * SCTLR.B. 3141 * In user mode, however, we model BE32 as byte-invariant 3142 * big-endianness (because user-only code cannot tell the 3143 * difference), and so we need to use a data access endianness 3144 * that depends on SCTLR.B. 3145 */ 3146 arm_sctlr_b(env) || 3147 #endif 3148 ((env->uncached_cpsr & CPSR_E) ? 1 : 0); 3149 } else { 3150 int cur_el = arm_current_el(env); 3151 uint64_t sctlr = arm_sctlr(env, cur_el); 3152 3153 return (sctlr & (cur_el ? SCTLR_EE : SCTLR_E0E)) != 0; 3154 } 3155 } 3156 3157 #include "exec/cpu-all.h" 3158 3159 /* Bit usage in the TB flags field: bit 31 indicates whether we are 3160 * in 32 or 64 bit mode. The meaning of the other bits depends on that. 3161 * We put flags which are shared between 32 and 64 bit mode at the top 3162 * of the word, and flags which apply to only one mode at the bottom. 3163 */ 3164 FIELD(TBFLAG_ANY, AARCH64_STATE, 31, 1) 3165 FIELD(TBFLAG_ANY, MMUIDX, 28, 3) 3166 FIELD(TBFLAG_ANY, SS_ACTIVE, 27, 1) 3167 FIELD(TBFLAG_ANY, PSTATE_SS, 26, 1) 3168 /* Target EL if we take a floating-point-disabled exception */ 3169 FIELD(TBFLAG_ANY, FPEXC_EL, 24, 2) 3170 FIELD(TBFLAG_ANY, BE_DATA, 23, 1) 3171 3172 /* Bit usage when in AArch32 state: */ 3173 FIELD(TBFLAG_A32, THUMB, 0, 1) 3174 FIELD(TBFLAG_A32, VECLEN, 1, 3) 3175 FIELD(TBFLAG_A32, VECSTRIDE, 4, 2) 3176 /* 3177 * We store the bottom two bits of the CPAR as TB flags and handle 3178 * checks on the other bits at runtime. This shares the same bits as 3179 * VECSTRIDE, which is OK as no XScale CPU has VFP. 3180 */ 3181 FIELD(TBFLAG_A32, XSCALE_CPAR, 4, 2) 3182 /* 3183 * Indicates whether cp register reads and writes by guest code should access 3184 * the secure or nonsecure bank of banked registers; note that this is not 3185 * the same thing as the current security state of the processor! 3186 */ 3187 FIELD(TBFLAG_A32, NS, 6, 1) 3188 FIELD(TBFLAG_A32, VFPEN, 7, 1) 3189 FIELD(TBFLAG_A32, CONDEXEC, 8, 8) 3190 FIELD(TBFLAG_A32, SCTLR_B, 16, 1) 3191 /* For M profile only, set if FPCCR.LSPACT is set */ 3192 FIELD(TBFLAG_A32, LSPACT, 18, 1) 3193 /* For M profile only, set if we must create a new FP context */ 3194 FIELD(TBFLAG_A32, NEW_FP_CTXT_NEEDED, 19, 1) 3195 /* For M profile only, set if FPCCR.S does not match current security state */ 3196 FIELD(TBFLAG_A32, FPCCR_S_WRONG, 20, 1) 3197 /* For M profile only, Handler (ie not Thread) mode */ 3198 FIELD(TBFLAG_A32, HANDLER, 21, 1) 3199 /* For M profile only, whether we should generate stack-limit checks */ 3200 FIELD(TBFLAG_A32, STACKCHECK, 22, 1) 3201 3202 /* Bit usage when in AArch64 state */ 3203 FIELD(TBFLAG_A64, TBII, 0, 2) 3204 FIELD(TBFLAG_A64, SVEEXC_EL, 2, 2) 3205 FIELD(TBFLAG_A64, ZCR_LEN, 4, 4) 3206 FIELD(TBFLAG_A64, PAUTH_ACTIVE, 8, 1) 3207 FIELD(TBFLAG_A64, BT, 9, 1) 3208 FIELD(TBFLAG_A64, BTYPE, 10, 2) 3209 FIELD(TBFLAG_A64, TBID, 12, 2) 3210 3211 static inline bool bswap_code(bool sctlr_b) 3212 { 3213 #ifdef CONFIG_USER_ONLY 3214 /* BE8 (SCTLR.B = 0, TARGET_WORDS_BIGENDIAN = 1) is mixed endian. 3215 * The invalid combination SCTLR.B=1/CPSR.E=1/TARGET_WORDS_BIGENDIAN=0 3216 * would also end up as a mixed-endian mode with BE code, LE data. 3217 */ 3218 return 3219 #ifdef TARGET_WORDS_BIGENDIAN 3220 1 ^ 3221 #endif 3222 sctlr_b; 3223 #else 3224 /* All code access in ARM is little endian, and there are no loaders 3225 * doing swaps that need to be reversed 3226 */ 3227 return 0; 3228 #endif 3229 } 3230 3231 #ifdef CONFIG_USER_ONLY 3232 static inline bool arm_cpu_bswap_data(CPUARMState *env) 3233 { 3234 return 3235 #ifdef TARGET_WORDS_BIGENDIAN 3236 1 ^ 3237 #endif 3238 arm_cpu_data_is_big_endian(env); 3239 } 3240 #endif 3241 3242 void cpu_get_tb_cpu_state(CPUARMState *env, target_ulong *pc, 3243 target_ulong *cs_base, uint32_t *flags); 3244 3245 enum { 3246 QEMU_PSCI_CONDUIT_DISABLED = 0, 3247 QEMU_PSCI_CONDUIT_SMC = 1, 3248 QEMU_PSCI_CONDUIT_HVC = 2, 3249 }; 3250 3251 #ifndef CONFIG_USER_ONLY 3252 /* Return the address space index to use for a memory access */ 3253 static inline int arm_asidx_from_attrs(CPUState *cs, MemTxAttrs attrs) 3254 { 3255 return attrs.secure ? ARMASIdx_S : ARMASIdx_NS; 3256 } 3257 3258 /* Return the AddressSpace to use for a memory access 3259 * (which depends on whether the access is S or NS, and whether 3260 * the board gave us a separate AddressSpace for S accesses). 3261 */ 3262 static inline AddressSpace *arm_addressspace(CPUState *cs, MemTxAttrs attrs) 3263 { 3264 return cpu_get_address_space(cs, arm_asidx_from_attrs(cs, attrs)); 3265 } 3266 #endif 3267 3268 /** 3269 * arm_register_pre_el_change_hook: 3270 * Register a hook function which will be called immediately before this 3271 * CPU changes exception level or mode. The hook function will be 3272 * passed a pointer to the ARMCPU and the opaque data pointer passed 3273 * to this function when the hook was registered. 3274 * 3275 * Note that if a pre-change hook is called, any registered post-change hooks 3276 * are guaranteed to subsequently be called. 3277 */ 3278 void arm_register_pre_el_change_hook(ARMCPU *cpu, ARMELChangeHookFn *hook, 3279 void *opaque); 3280 /** 3281 * arm_register_el_change_hook: 3282 * Register a hook function which will be called immediately after this 3283 * CPU changes exception level or mode. The hook function will be 3284 * passed a pointer to the ARMCPU and the opaque data pointer passed 3285 * to this function when the hook was registered. 3286 * 3287 * Note that any registered hooks registered here are guaranteed to be called 3288 * if pre-change hooks have been. 3289 */ 3290 void arm_register_el_change_hook(ARMCPU *cpu, ARMELChangeHookFn *hook, void 3291 *opaque); 3292 3293 /** 3294 * aa32_vfp_dreg: 3295 * Return a pointer to the Dn register within env in 32-bit mode. 3296 */ 3297 static inline uint64_t *aa32_vfp_dreg(CPUARMState *env, unsigned regno) 3298 { 3299 return &env->vfp.zregs[regno >> 1].d[regno & 1]; 3300 } 3301 3302 /** 3303 * aa32_vfp_qreg: 3304 * Return a pointer to the Qn register within env in 32-bit mode. 3305 */ 3306 static inline uint64_t *aa32_vfp_qreg(CPUARMState *env, unsigned regno) 3307 { 3308 return &env->vfp.zregs[regno].d[0]; 3309 } 3310 3311 /** 3312 * aa64_vfp_qreg: 3313 * Return a pointer to the Qn register within env in 64-bit mode. 3314 */ 3315 static inline uint64_t *aa64_vfp_qreg(CPUARMState *env, unsigned regno) 3316 { 3317 return &env->vfp.zregs[regno].d[0]; 3318 } 3319 3320 /* Shared between translate-sve.c and sve_helper.c. */ 3321 extern const uint64_t pred_esz_masks[4]; 3322 3323 /* 3324 * 32-bit feature tests via id registers. 3325 */ 3326 static inline bool isar_feature_thumb_div(const ARMISARegisters *id) 3327 { 3328 return FIELD_EX32(id->id_isar0, ID_ISAR0, DIVIDE) != 0; 3329 } 3330 3331 static inline bool isar_feature_arm_div(const ARMISARegisters *id) 3332 { 3333 return FIELD_EX32(id->id_isar0, ID_ISAR0, DIVIDE) > 1; 3334 } 3335 3336 static inline bool isar_feature_jazelle(const ARMISARegisters *id) 3337 { 3338 return FIELD_EX32(id->id_isar1, ID_ISAR1, JAZELLE) != 0; 3339 } 3340 3341 static inline bool isar_feature_aa32_aes(const ARMISARegisters *id) 3342 { 3343 return FIELD_EX32(id->id_isar5, ID_ISAR5, AES) != 0; 3344 } 3345 3346 static inline bool isar_feature_aa32_pmull(const ARMISARegisters *id) 3347 { 3348 return FIELD_EX32(id->id_isar5, ID_ISAR5, AES) > 1; 3349 } 3350 3351 static inline bool isar_feature_aa32_sha1(const ARMISARegisters *id) 3352 { 3353 return FIELD_EX32(id->id_isar5, ID_ISAR5, SHA1) != 0; 3354 } 3355 3356 static inline bool isar_feature_aa32_sha2(const ARMISARegisters *id) 3357 { 3358 return FIELD_EX32(id->id_isar5, ID_ISAR5, SHA2) != 0; 3359 } 3360 3361 static inline bool isar_feature_aa32_crc32(const ARMISARegisters *id) 3362 { 3363 return FIELD_EX32(id->id_isar5, ID_ISAR5, CRC32) != 0; 3364 } 3365 3366 static inline bool isar_feature_aa32_rdm(const ARMISARegisters *id) 3367 { 3368 return FIELD_EX32(id->id_isar5, ID_ISAR5, RDM) != 0; 3369 } 3370 3371 static inline bool isar_feature_aa32_vcma(const ARMISARegisters *id) 3372 { 3373 return FIELD_EX32(id->id_isar5, ID_ISAR5, VCMA) != 0; 3374 } 3375 3376 static inline bool isar_feature_aa32_jscvt(const ARMISARegisters *id) 3377 { 3378 return FIELD_EX32(id->id_isar6, ID_ISAR6, JSCVT) != 0; 3379 } 3380 3381 static inline bool isar_feature_aa32_dp(const ARMISARegisters *id) 3382 { 3383 return FIELD_EX32(id->id_isar6, ID_ISAR6, DP) != 0; 3384 } 3385 3386 static inline bool isar_feature_aa32_fhm(const ARMISARegisters *id) 3387 { 3388 return FIELD_EX32(id->id_isar6, ID_ISAR6, FHM) != 0; 3389 } 3390 3391 static inline bool isar_feature_aa32_sb(const ARMISARegisters *id) 3392 { 3393 return FIELD_EX32(id->id_isar6, ID_ISAR6, SB) != 0; 3394 } 3395 3396 static inline bool isar_feature_aa32_predinv(const ARMISARegisters *id) 3397 { 3398 return FIELD_EX32(id->id_isar6, ID_ISAR6, SPECRES) != 0; 3399 } 3400 3401 static inline bool isar_feature_aa32_fp16_arith(const ARMISARegisters *id) 3402 { 3403 /* 3404 * This is a placeholder for use by VCMA until the rest of 3405 * the ARMv8.2-FP16 extension is implemented for aa32 mode. 3406 * At which point we can properly set and check MVFR1.FPHP. 3407 */ 3408 return FIELD_EX64(id->id_aa64pfr0, ID_AA64PFR0, FP) == 1; 3409 } 3410 3411 /* 3412 * We always set the FP and SIMD FP16 fields to indicate identical 3413 * levels of support (assuming SIMD is implemented at all), so 3414 * we only need one set of accessors. 3415 */ 3416 static inline bool isar_feature_aa32_fp16_spconv(const ARMISARegisters *id) 3417 { 3418 return FIELD_EX64(id->mvfr1, MVFR1, FPHP) > 0; 3419 } 3420 3421 static inline bool isar_feature_aa32_fp16_dpconv(const ARMISARegisters *id) 3422 { 3423 return FIELD_EX64(id->mvfr1, MVFR1, FPHP) > 1; 3424 } 3425 3426 static inline bool isar_feature_aa32_vsel(const ARMISARegisters *id) 3427 { 3428 return FIELD_EX64(id->mvfr2, MVFR2, FPMISC) >= 1; 3429 } 3430 3431 static inline bool isar_feature_aa32_vcvt_dr(const ARMISARegisters *id) 3432 { 3433 return FIELD_EX64(id->mvfr2, MVFR2, FPMISC) >= 2; 3434 } 3435 3436 static inline bool isar_feature_aa32_vrint(const ARMISARegisters *id) 3437 { 3438 return FIELD_EX64(id->mvfr2, MVFR2, FPMISC) >= 3; 3439 } 3440 3441 static inline bool isar_feature_aa32_vminmaxnm(const ARMISARegisters *id) 3442 { 3443 return FIELD_EX64(id->mvfr2, MVFR2, FPMISC) >= 4; 3444 } 3445 3446 /* 3447 * 64-bit feature tests via id registers. 3448 */ 3449 static inline bool isar_feature_aa64_aes(const ARMISARegisters *id) 3450 { 3451 return FIELD_EX64(id->id_aa64isar0, ID_AA64ISAR0, AES) != 0; 3452 } 3453 3454 static inline bool isar_feature_aa64_pmull(const ARMISARegisters *id) 3455 { 3456 return FIELD_EX64(id->id_aa64isar0, ID_AA64ISAR0, AES) > 1; 3457 } 3458 3459 static inline bool isar_feature_aa64_sha1(const ARMISARegisters *id) 3460 { 3461 return FIELD_EX64(id->id_aa64isar0, ID_AA64ISAR0, SHA1) != 0; 3462 } 3463 3464 static inline bool isar_feature_aa64_sha256(const ARMISARegisters *id) 3465 { 3466 return FIELD_EX64(id->id_aa64isar0, ID_AA64ISAR0, SHA2) != 0; 3467 } 3468 3469 static inline bool isar_feature_aa64_sha512(const ARMISARegisters *id) 3470 { 3471 return FIELD_EX64(id->id_aa64isar0, ID_AA64ISAR0, SHA2) > 1; 3472 } 3473 3474 static inline bool isar_feature_aa64_crc32(const ARMISARegisters *id) 3475 { 3476 return FIELD_EX64(id->id_aa64isar0, ID_AA64ISAR0, CRC32) != 0; 3477 } 3478 3479 static inline bool isar_feature_aa64_atomics(const ARMISARegisters *id) 3480 { 3481 return FIELD_EX64(id->id_aa64isar0, ID_AA64ISAR0, ATOMIC) != 0; 3482 } 3483 3484 static inline bool isar_feature_aa64_rdm(const ARMISARegisters *id) 3485 { 3486 return FIELD_EX64(id->id_aa64isar0, ID_AA64ISAR0, RDM) != 0; 3487 } 3488 3489 static inline bool isar_feature_aa64_sha3(const ARMISARegisters *id) 3490 { 3491 return FIELD_EX64(id->id_aa64isar0, ID_AA64ISAR0, SHA3) != 0; 3492 } 3493 3494 static inline bool isar_feature_aa64_sm3(const ARMISARegisters *id) 3495 { 3496 return FIELD_EX64(id->id_aa64isar0, ID_AA64ISAR0, SM3) != 0; 3497 } 3498 3499 static inline bool isar_feature_aa64_sm4(const ARMISARegisters *id) 3500 { 3501 return FIELD_EX64(id->id_aa64isar0, ID_AA64ISAR0, SM4) != 0; 3502 } 3503 3504 static inline bool isar_feature_aa64_dp(const ARMISARegisters *id) 3505 { 3506 return FIELD_EX64(id->id_aa64isar0, ID_AA64ISAR0, DP) != 0; 3507 } 3508 3509 static inline bool isar_feature_aa64_fhm(const ARMISARegisters *id) 3510 { 3511 return FIELD_EX64(id->id_aa64isar0, ID_AA64ISAR0, FHM) != 0; 3512 } 3513 3514 static inline bool isar_feature_aa64_condm_4(const ARMISARegisters *id) 3515 { 3516 return FIELD_EX64(id->id_aa64isar0, ID_AA64ISAR0, TS) != 0; 3517 } 3518 3519 static inline bool isar_feature_aa64_condm_5(const ARMISARegisters *id) 3520 { 3521 return FIELD_EX64(id->id_aa64isar0, ID_AA64ISAR0, TS) >= 2; 3522 } 3523 3524 static inline bool isar_feature_aa64_rndr(const ARMISARegisters *id) 3525 { 3526 return FIELD_EX64(id->id_aa64isar0, ID_AA64ISAR0, RNDR) != 0; 3527 } 3528 3529 static inline bool isar_feature_aa64_jscvt(const ARMISARegisters *id) 3530 { 3531 return FIELD_EX64(id->id_aa64isar1, ID_AA64ISAR1, JSCVT) != 0; 3532 } 3533 3534 static inline bool isar_feature_aa64_fcma(const ARMISARegisters *id) 3535 { 3536 return FIELD_EX64(id->id_aa64isar1, ID_AA64ISAR1, FCMA) != 0; 3537 } 3538 3539 static inline bool isar_feature_aa64_pauth(const ARMISARegisters *id) 3540 { 3541 /* 3542 * Note that while QEMU will only implement the architected algorithm 3543 * QARMA, and thus APA+GPA, the host cpu for kvm may use implementation 3544 * defined algorithms, and thus API+GPI, and this predicate controls 3545 * migration of the 128-bit keys. 3546 */ 3547 return (id->id_aa64isar1 & 3548 (FIELD_DP64(0, ID_AA64ISAR1, APA, 0xf) | 3549 FIELD_DP64(0, ID_AA64ISAR1, API, 0xf) | 3550 FIELD_DP64(0, ID_AA64ISAR1, GPA, 0xf) | 3551 FIELD_DP64(0, ID_AA64ISAR1, GPI, 0xf))) != 0; 3552 } 3553 3554 static inline bool isar_feature_aa64_sb(const ARMISARegisters *id) 3555 { 3556 return FIELD_EX64(id->id_aa64isar1, ID_AA64ISAR1, SB) != 0; 3557 } 3558 3559 static inline bool isar_feature_aa64_predinv(const ARMISARegisters *id) 3560 { 3561 return FIELD_EX64(id->id_aa64isar1, ID_AA64ISAR1, SPECRES) != 0; 3562 } 3563 3564 static inline bool isar_feature_aa64_frint(const ARMISARegisters *id) 3565 { 3566 return FIELD_EX64(id->id_aa64isar1, ID_AA64ISAR1, FRINTTS) != 0; 3567 } 3568 3569 static inline bool isar_feature_aa64_fp16(const ARMISARegisters *id) 3570 { 3571 /* We always set the AdvSIMD and FP fields identically wrt FP16. */ 3572 return FIELD_EX64(id->id_aa64pfr0, ID_AA64PFR0, FP) == 1; 3573 } 3574 3575 static inline bool isar_feature_aa64_aa32(const ARMISARegisters *id) 3576 { 3577 return FIELD_EX64(id->id_aa64pfr0, ID_AA64PFR0, EL0) >= 2; 3578 } 3579 3580 static inline bool isar_feature_aa64_sve(const ARMISARegisters *id) 3581 { 3582 return FIELD_EX64(id->id_aa64pfr0, ID_AA64PFR0, SVE) != 0; 3583 } 3584 3585 static inline bool isar_feature_aa64_lor(const ARMISARegisters *id) 3586 { 3587 return FIELD_EX64(id->id_aa64mmfr1, ID_AA64MMFR1, LO) != 0; 3588 } 3589 3590 static inline bool isar_feature_aa64_bti(const ARMISARegisters *id) 3591 { 3592 return FIELD_EX64(id->id_aa64pfr1, ID_AA64PFR1, BT) != 0; 3593 } 3594 3595 /* 3596 * Forward to the above feature tests given an ARMCPU pointer. 3597 */ 3598 #define cpu_isar_feature(name, cpu) \ 3599 ({ ARMCPU *cpu_ = (cpu); isar_feature_##name(&cpu_->isar); }) 3600 3601 #endif 3602