1 /* 2 * ARM virtual CPU header 3 * 4 * Copyright (c) 2003 Fabrice Bellard 5 * 6 * This library is free software; you can redistribute it and/or 7 * modify it under the terms of the GNU Lesser General Public 8 * License as published by the Free Software Foundation; either 9 * version 2.1 of the License, or (at your option) any later version. 10 * 11 * This library is distributed in the hope that it will be useful, 12 * but WITHOUT ANY WARRANTY; without even the implied warranty of 13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU 14 * Lesser General Public License for more details. 15 * 16 * You should have received a copy of the GNU Lesser General Public 17 * License along with this library; if not, see <http://www.gnu.org/licenses/>. 18 */ 19 20 #ifndef ARM_CPU_H 21 #define ARM_CPU_H 22 23 #include "kvm-consts.h" 24 #include "qemu/cpu-float.h" 25 #include "hw/registerfields.h" 26 #include "cpu-qom.h" 27 #include "exec/cpu-defs.h" 28 #include "exec/gdbstub.h" 29 #include "qapi/qapi-types-common.h" 30 #include "target/arm/multiprocessing.h" 31 #include "target/arm/gtimer.h" 32 33 /* ARM processors have a weak memory model */ 34 #define TCG_GUEST_DEFAULT_MO (0) 35 36 #ifdef TARGET_AARCH64 37 #define KVM_HAVE_MCE_INJECTION 1 38 #endif 39 40 #define EXCP_UDEF 1 /* undefined instruction */ 41 #define EXCP_SWI 2 /* software interrupt */ 42 #define EXCP_PREFETCH_ABORT 3 43 #define EXCP_DATA_ABORT 4 44 #define EXCP_IRQ 5 45 #define EXCP_FIQ 6 46 #define EXCP_BKPT 7 47 #define EXCP_EXCEPTION_EXIT 8 /* Return from v7M exception. */ 48 #define EXCP_KERNEL_TRAP 9 /* Jumped to kernel code page. */ 49 #define EXCP_HVC 11 /* HyperVisor Call */ 50 #define EXCP_HYP_TRAP 12 51 #define EXCP_SMC 13 /* Secure Monitor Call */ 52 #define EXCP_VIRQ 14 53 #define EXCP_VFIQ 15 54 #define EXCP_SEMIHOST 16 /* semihosting call */ 55 #define EXCP_NOCP 17 /* v7M NOCP UsageFault */ 56 #define EXCP_INVSTATE 18 /* v7M INVSTATE UsageFault */ 57 #define EXCP_STKOF 19 /* v8M STKOF UsageFault */ 58 #define EXCP_LAZYFP 20 /* v7M fault during lazy FP stacking */ 59 #define EXCP_LSERR 21 /* v8M LSERR SecureFault */ 60 #define EXCP_UNALIGNED 22 /* v7M UNALIGNED UsageFault */ 61 #define EXCP_DIVBYZERO 23 /* v7M DIVBYZERO UsageFault */ 62 #define EXCP_VSERR 24 63 #define EXCP_GPC 25 /* v9 Granule Protection Check Fault */ 64 /* NB: add new EXCP_ defines to the array in arm_log_exception() too */ 65 66 #define ARMV7M_EXCP_RESET 1 67 #define ARMV7M_EXCP_NMI 2 68 #define ARMV7M_EXCP_HARD 3 69 #define ARMV7M_EXCP_MEM 4 70 #define ARMV7M_EXCP_BUS 5 71 #define ARMV7M_EXCP_USAGE 6 72 #define ARMV7M_EXCP_SECURE 7 73 #define ARMV7M_EXCP_SVC 11 74 #define ARMV7M_EXCP_DEBUG 12 75 #define ARMV7M_EXCP_PENDSV 14 76 #define ARMV7M_EXCP_SYSTICK 15 77 78 /* ARM-specific interrupt pending bits. */ 79 #define CPU_INTERRUPT_FIQ CPU_INTERRUPT_TGT_EXT_1 80 #define CPU_INTERRUPT_VIRQ CPU_INTERRUPT_TGT_EXT_2 81 #define CPU_INTERRUPT_VFIQ CPU_INTERRUPT_TGT_EXT_3 82 #define CPU_INTERRUPT_VSERR CPU_INTERRUPT_TGT_INT_0 83 84 /* The usual mapping for an AArch64 system register to its AArch32 85 * counterpart is for the 32 bit world to have access to the lower 86 * half only (with writes leaving the upper half untouched). It's 87 * therefore useful to be able to pass TCG the offset of the least 88 * significant half of a uint64_t struct member. 89 */ 90 #if HOST_BIG_ENDIAN 91 #define offsetoflow32(S, M) (offsetof(S, M) + sizeof(uint32_t)) 92 #define offsetofhigh32(S, M) offsetof(S, M) 93 #else 94 #define offsetoflow32(S, M) offsetof(S, M) 95 #define offsetofhigh32(S, M) (offsetof(S, M) + sizeof(uint32_t)) 96 #endif 97 98 /* ARM-specific extra insn start words: 99 * 1: Conditional execution bits 100 * 2: Partial exception syndrome for data aborts 101 */ 102 #define TARGET_INSN_START_EXTRA_WORDS 2 103 104 /* The 2nd extra word holding syndrome info for data aborts does not use 105 * the upper 6 bits nor the lower 13 bits. We mask and shift it down to 106 * help the sleb128 encoder do a better job. 107 * When restoring the CPU state, we shift it back up. 108 */ 109 #define ARM_INSN_START_WORD2_MASK ((1 << 26) - 1) 110 #define ARM_INSN_START_WORD2_SHIFT 13 111 112 /* We currently assume float and double are IEEE single and double 113 precision respectively. 114 Doing runtime conversions is tricky because VFP registers may contain 115 integer values (eg. as the result of a FTOSI instruction). 116 s<2n> maps to the least significant half of d<n> 117 s<2n+1> maps to the most significant half of d<n> 118 */ 119 120 /** 121 * DynamicGDBFeatureInfo: 122 * @desc: Contains the feature descriptions. 123 * @data: A union with data specific to the set of registers 124 * @cpregs_keys: Array that contains the corresponding Key of 125 * a given cpreg with the same order of the cpreg 126 * in the XML description. 127 */ 128 typedef struct DynamicGDBFeatureInfo { 129 GDBFeature desc; 130 union { 131 struct { 132 uint32_t *keys; 133 } cpregs; 134 } data; 135 } DynamicGDBFeatureInfo; 136 137 /* CPU state for each instance of a generic timer (in cp15 c14) */ 138 typedef struct ARMGenericTimer { 139 uint64_t cval; /* Timer CompareValue register */ 140 uint64_t ctl; /* Timer Control register */ 141 } ARMGenericTimer; 142 143 #define VTCR_NSW (1u << 29) 144 #define VTCR_NSA (1u << 30) 145 #define VSTCR_SW VTCR_NSW 146 #define VSTCR_SA VTCR_NSA 147 148 /* Define a maximum sized vector register. 149 * For 32-bit, this is a 128-bit NEON/AdvSIMD register. 150 * For 64-bit, this is a 2048-bit SVE register. 151 * 152 * Note that the mapping between S, D, and Q views of the register bank 153 * differs between AArch64 and AArch32. 154 * In AArch32: 155 * Qn = regs[n].d[1]:regs[n].d[0] 156 * Dn = regs[n / 2].d[n & 1] 157 * Sn = regs[n / 4].d[n % 4 / 2], 158 * bits 31..0 for even n, and bits 63..32 for odd n 159 * (and regs[16] to regs[31] are inaccessible) 160 * In AArch64: 161 * Zn = regs[n].d[*] 162 * Qn = regs[n].d[1]:regs[n].d[0] 163 * Dn = regs[n].d[0] 164 * Sn = regs[n].d[0] bits 31..0 165 * Hn = regs[n].d[0] bits 15..0 166 * 167 * This corresponds to the architecturally defined mapping between 168 * the two execution states, and means we do not need to explicitly 169 * map these registers when changing states. 170 * 171 * Align the data for use with TCG host vector operations. 172 */ 173 174 #ifdef TARGET_AARCH64 175 # define ARM_MAX_VQ 16 176 #else 177 # define ARM_MAX_VQ 1 178 #endif 179 180 typedef struct ARMVectorReg { 181 uint64_t d[2 * ARM_MAX_VQ] QEMU_ALIGNED(16); 182 } ARMVectorReg; 183 184 #ifdef TARGET_AARCH64 185 /* In AArch32 mode, predicate registers do not exist at all. */ 186 typedef struct ARMPredicateReg { 187 uint64_t p[DIV_ROUND_UP(2 * ARM_MAX_VQ, 8)] QEMU_ALIGNED(16); 188 } ARMPredicateReg; 189 190 /* In AArch32 mode, PAC keys do not exist at all. */ 191 typedef struct ARMPACKey { 192 uint64_t lo, hi; 193 } ARMPACKey; 194 #endif 195 196 /* See the commentary above the TBFLAG field definitions. */ 197 typedef struct CPUARMTBFlags { 198 uint32_t flags; 199 target_ulong flags2; 200 } CPUARMTBFlags; 201 202 typedef struct ARMMMUFaultInfo ARMMMUFaultInfo; 203 204 typedef struct NVICState NVICState; 205 206 typedef struct CPUArchState { 207 /* Regs for current mode. */ 208 uint32_t regs[16]; 209 210 /* 32/64 switch only happens when taking and returning from 211 * exceptions so the overlap semantics are taken care of then 212 * instead of having a complicated union. 213 */ 214 /* Regs for A64 mode. */ 215 uint64_t xregs[32]; 216 uint64_t pc; 217 /* PSTATE isn't an architectural register for ARMv8. However, it is 218 * convenient for us to assemble the underlying state into a 32 bit format 219 * identical to the architectural format used for the SPSR. (This is also 220 * what the Linux kernel's 'pstate' field in signal handlers and KVM's 221 * 'pstate' register are.) Of the PSTATE bits: 222 * NZCV are kept in the split out env->CF/VF/NF/ZF, (which have the same 223 * semantics as for AArch32, as described in the comments on each field) 224 * nRW (also known as M[4]) is kept, inverted, in env->aarch64 225 * DAIF (exception masks) are kept in env->daif 226 * BTYPE is kept in env->btype 227 * SM and ZA are kept in env->svcr 228 * all other bits are stored in their correct places in env->pstate 229 */ 230 uint32_t pstate; 231 bool aarch64; /* True if CPU is in aarch64 state; inverse of PSTATE.nRW */ 232 bool thumb; /* True if CPU is in thumb mode; cpsr[5] */ 233 234 /* Cached TBFLAGS state. See below for which bits are included. */ 235 CPUARMTBFlags hflags; 236 237 /* Frequently accessed CPSR bits are stored separately for efficiency. 238 This contains all the other bits. Use cpsr_{read,write} to access 239 the whole CPSR. */ 240 uint32_t uncached_cpsr; 241 uint32_t spsr; 242 243 /* Banked registers. */ 244 uint64_t banked_spsr[8]; 245 uint32_t banked_r13[8]; 246 uint32_t banked_r14[8]; 247 248 /* These hold r8-r12. */ 249 uint32_t usr_regs[5]; 250 uint32_t fiq_regs[5]; 251 252 /* cpsr flag cache for faster execution */ 253 uint32_t CF; /* 0 or 1 */ 254 uint32_t VF; /* V is the bit 31. All other bits are undefined */ 255 uint32_t NF; /* N is bit 31. All other bits are undefined. */ 256 uint32_t ZF; /* Z set if zero. */ 257 uint32_t QF; /* 0 or 1 */ 258 uint32_t GE; /* cpsr[19:16] */ 259 uint32_t condexec_bits; /* IT bits. cpsr[15:10,26:25]. */ 260 uint32_t btype; /* BTI branch type. spsr[11:10]. */ 261 uint64_t daif; /* exception masks, in the bits they are in PSTATE */ 262 uint64_t svcr; /* PSTATE.{SM,ZA} in the bits they are in SVCR */ 263 264 uint64_t elr_el[4]; /* AArch64 exception link regs */ 265 uint64_t sp_el[4]; /* AArch64 banked stack pointers */ 266 267 /* System control coprocessor (cp15) */ 268 struct { 269 uint32_t c0_cpuid; 270 union { /* Cache size selection */ 271 struct { 272 uint64_t _unused_csselr0; 273 uint64_t csselr_ns; 274 uint64_t _unused_csselr1; 275 uint64_t csselr_s; 276 }; 277 uint64_t csselr_el[4]; 278 }; 279 union { /* System control register. */ 280 struct { 281 uint64_t _unused_sctlr; 282 uint64_t sctlr_ns; 283 uint64_t hsctlr; 284 uint64_t sctlr_s; 285 }; 286 uint64_t sctlr_el[4]; 287 }; 288 uint64_t vsctlr; /* Virtualization System control register. */ 289 uint64_t cpacr_el1; /* Architectural feature access control register */ 290 uint64_t cptr_el[4]; /* ARMv8 feature trap registers */ 291 uint32_t c1_xscaleauxcr; /* XScale auxiliary control register. */ 292 uint64_t sder; /* Secure debug enable register. */ 293 uint32_t nsacr; /* Non-secure access control register. */ 294 union { /* MMU translation table base 0. */ 295 struct { 296 uint64_t _unused_ttbr0_0; 297 uint64_t ttbr0_ns; 298 uint64_t _unused_ttbr0_1; 299 uint64_t ttbr0_s; 300 }; 301 uint64_t ttbr0_el[4]; 302 }; 303 union { /* MMU translation table base 1. */ 304 struct { 305 uint64_t _unused_ttbr1_0; 306 uint64_t ttbr1_ns; 307 uint64_t _unused_ttbr1_1; 308 uint64_t ttbr1_s; 309 }; 310 uint64_t ttbr1_el[4]; 311 }; 312 uint64_t vttbr_el2; /* Virtualization Translation Table Base. */ 313 uint64_t vsttbr_el2; /* Secure Virtualization Translation Table. */ 314 /* MMU translation table base control. */ 315 uint64_t tcr_el[4]; 316 uint64_t vtcr_el2; /* Virtualization Translation Control. */ 317 uint64_t vstcr_el2; /* Secure Virtualization Translation Control. */ 318 uint32_t c2_data; /* MPU data cacheable bits. */ 319 uint32_t c2_insn; /* MPU instruction cacheable bits. */ 320 union { /* MMU domain access control register 321 * MPU write buffer control. 322 */ 323 struct { 324 uint64_t dacr_ns; 325 uint64_t dacr_s; 326 }; 327 struct { 328 uint64_t dacr32_el2; 329 }; 330 }; 331 uint32_t pmsav5_data_ap; /* PMSAv5 MPU data access permissions */ 332 uint32_t pmsav5_insn_ap; /* PMSAv5 MPU insn access permissions */ 333 uint64_t hcr_el2; /* Hypervisor configuration register */ 334 uint64_t hcrx_el2; /* Extended Hypervisor configuration register */ 335 uint64_t scr_el3; /* Secure configuration register. */ 336 union { /* Fault status registers. */ 337 struct { 338 uint64_t ifsr_ns; 339 uint64_t ifsr_s; 340 }; 341 struct { 342 uint64_t ifsr32_el2; 343 }; 344 }; 345 union { 346 struct { 347 uint64_t _unused_dfsr; 348 uint64_t dfsr_ns; 349 uint64_t hsr; 350 uint64_t dfsr_s; 351 }; 352 uint64_t esr_el[4]; 353 }; 354 uint32_t c6_region[8]; /* MPU base/size registers. */ 355 union { /* Fault address registers. */ 356 struct { 357 uint64_t _unused_far0; 358 #if HOST_BIG_ENDIAN 359 uint32_t ifar_ns; 360 uint32_t dfar_ns; 361 uint32_t ifar_s; 362 uint32_t dfar_s; 363 #else 364 uint32_t dfar_ns; 365 uint32_t ifar_ns; 366 uint32_t dfar_s; 367 uint32_t ifar_s; 368 #endif 369 uint64_t _unused_far3; 370 }; 371 uint64_t far_el[4]; 372 }; 373 uint64_t hpfar_el2; 374 uint64_t hstr_el2; 375 union { /* Translation result. */ 376 struct { 377 uint64_t _unused_par_0; 378 uint64_t par_ns; 379 uint64_t _unused_par_1; 380 uint64_t par_s; 381 }; 382 uint64_t par_el[4]; 383 }; 384 385 uint32_t c9_insn; /* Cache lockdown registers. */ 386 uint32_t c9_data; 387 uint64_t c9_pmcr; /* performance monitor control register */ 388 uint64_t c9_pmcnten; /* perf monitor counter enables */ 389 uint64_t c9_pmovsr; /* perf monitor overflow status */ 390 uint64_t c9_pmuserenr; /* perf monitor user enable */ 391 uint64_t c9_pmselr; /* perf monitor counter selection register */ 392 uint64_t c9_pminten; /* perf monitor interrupt enables */ 393 union { /* Memory attribute redirection */ 394 struct { 395 #if HOST_BIG_ENDIAN 396 uint64_t _unused_mair_0; 397 uint32_t mair1_ns; 398 uint32_t mair0_ns; 399 uint64_t _unused_mair_1; 400 uint32_t mair1_s; 401 uint32_t mair0_s; 402 #else 403 uint64_t _unused_mair_0; 404 uint32_t mair0_ns; 405 uint32_t mair1_ns; 406 uint64_t _unused_mair_1; 407 uint32_t mair0_s; 408 uint32_t mair1_s; 409 #endif 410 }; 411 uint64_t mair_el[4]; 412 }; 413 union { /* vector base address register */ 414 struct { 415 uint64_t _unused_vbar; 416 uint64_t vbar_ns; 417 uint64_t hvbar; 418 uint64_t vbar_s; 419 }; 420 uint64_t vbar_el[4]; 421 }; 422 uint32_t mvbar; /* (monitor) vector base address register */ 423 uint64_t rvbar; /* rvbar sampled from rvbar property at reset */ 424 struct { /* FCSE PID. */ 425 uint32_t fcseidr_ns; 426 uint32_t fcseidr_s; 427 }; 428 union { /* Context ID. */ 429 struct { 430 uint64_t _unused_contextidr_0; 431 uint64_t contextidr_ns; 432 uint64_t _unused_contextidr_1; 433 uint64_t contextidr_s; 434 }; 435 uint64_t contextidr_el[4]; 436 }; 437 union { /* User RW Thread register. */ 438 struct { 439 uint64_t tpidrurw_ns; 440 uint64_t tpidrprw_ns; 441 uint64_t htpidr; 442 uint64_t _tpidr_el3; 443 }; 444 uint64_t tpidr_el[4]; 445 }; 446 uint64_t tpidr2_el0; 447 /* The secure banks of these registers don't map anywhere */ 448 uint64_t tpidrurw_s; 449 uint64_t tpidrprw_s; 450 uint64_t tpidruro_s; 451 452 union { /* User RO Thread register. */ 453 uint64_t tpidruro_ns; 454 uint64_t tpidrro_el[1]; 455 }; 456 uint64_t c14_cntfrq; /* Counter Frequency register */ 457 uint64_t c14_cntkctl; /* Timer Control register */ 458 uint64_t cnthctl_el2; /* Counter/Timer Hyp Control register */ 459 uint64_t cntvoff_el2; /* Counter Virtual Offset register */ 460 ARMGenericTimer c14_timer[NUM_GTIMERS]; 461 uint32_t c15_cpar; /* XScale Coprocessor Access Register */ 462 uint32_t c15_ticonfig; /* TI925T configuration byte. */ 463 uint32_t c15_i_max; /* Maximum D-cache dirty line index. */ 464 uint32_t c15_i_min; /* Minimum D-cache dirty line index. */ 465 uint32_t c15_threadid; /* TI debugger thread-ID. */ 466 uint32_t c15_config_base_address; /* SCU base address. */ 467 uint32_t c15_diagnostic; /* diagnostic register */ 468 uint32_t c15_power_diagnostic; 469 uint32_t c15_power_control; /* power control */ 470 uint64_t dbgbvr[16]; /* breakpoint value registers */ 471 uint64_t dbgbcr[16]; /* breakpoint control registers */ 472 uint64_t dbgwvr[16]; /* watchpoint value registers */ 473 uint64_t dbgwcr[16]; /* watchpoint control registers */ 474 uint64_t dbgclaim; /* DBGCLAIM bits */ 475 uint64_t mdscr_el1; 476 uint64_t oslsr_el1; /* OS Lock Status */ 477 uint64_t osdlr_el1; /* OS DoubleLock status */ 478 uint64_t mdcr_el2; 479 uint64_t mdcr_el3; 480 /* Stores the architectural value of the counter *the last time it was 481 * updated* by pmccntr_op_start. Accesses should always be surrounded 482 * by pmccntr_op_start/pmccntr_op_finish to guarantee the latest 483 * architecturally-correct value is being read/set. 484 */ 485 uint64_t c15_ccnt; 486 /* Stores the delta between the architectural value and the underlying 487 * cycle count during normal operation. It is used to update c15_ccnt 488 * to be the correct architectural value before accesses. During 489 * accesses, c15_ccnt_delta contains the underlying count being used 490 * for the access, after which it reverts to the delta value in 491 * pmccntr_op_finish. 492 */ 493 uint64_t c15_ccnt_delta; 494 uint64_t c14_pmevcntr[31]; 495 uint64_t c14_pmevcntr_delta[31]; 496 uint64_t c14_pmevtyper[31]; 497 uint64_t pmccfiltr_el0; /* Performance Monitor Filter Register */ 498 uint64_t vpidr_el2; /* Virtualization Processor ID Register */ 499 uint64_t vmpidr_el2; /* Virtualization Multiprocessor ID Register */ 500 uint64_t tfsr_el[4]; /* tfsre0_el1 is index 0. */ 501 uint64_t gcr_el1; 502 uint64_t rgsr_el1; 503 504 /* Minimal RAS registers */ 505 uint64_t disr_el1; 506 uint64_t vdisr_el2; 507 uint64_t vsesr_el2; 508 509 /* 510 * Fine-Grained Trap registers. We store these as arrays so the 511 * access checking code doesn't have to manually select 512 * HFGRTR_EL2 vs HFDFGRTR_EL2 etc when looking up the bit to test. 513 * FEAT_FGT2 will add more elements to these arrays. 514 */ 515 uint64_t fgt_read[2]; /* HFGRTR, HDFGRTR */ 516 uint64_t fgt_write[2]; /* HFGWTR, HDFGWTR */ 517 uint64_t fgt_exec[1]; /* HFGITR */ 518 519 /* RME registers */ 520 uint64_t gpccr_el3; 521 uint64_t gptbr_el3; 522 uint64_t mfar_el3; 523 524 /* NV2 register */ 525 uint64_t vncr_el2; 526 } cp15; 527 528 struct { 529 /* M profile has up to 4 stack pointers: 530 * a Main Stack Pointer and a Process Stack Pointer for each 531 * of the Secure and Non-Secure states. (If the CPU doesn't support 532 * the security extension then it has only two SPs.) 533 * In QEMU we always store the currently active SP in regs[13], 534 * and the non-active SP for the current security state in 535 * v7m.other_sp. The stack pointers for the inactive security state 536 * are stored in other_ss_msp and other_ss_psp. 537 * switch_v7m_security_state() is responsible for rearranging them 538 * when we change security state. 539 */ 540 uint32_t other_sp; 541 uint32_t other_ss_msp; 542 uint32_t other_ss_psp; 543 uint32_t vecbase[M_REG_NUM_BANKS]; 544 uint32_t basepri[M_REG_NUM_BANKS]; 545 uint32_t control[M_REG_NUM_BANKS]; 546 uint32_t ccr[M_REG_NUM_BANKS]; /* Configuration and Control */ 547 uint32_t cfsr[M_REG_NUM_BANKS]; /* Configurable Fault Status */ 548 uint32_t hfsr; /* HardFault Status */ 549 uint32_t dfsr; /* Debug Fault Status Register */ 550 uint32_t sfsr; /* Secure Fault Status Register */ 551 uint32_t mmfar[M_REG_NUM_BANKS]; /* MemManage Fault Address */ 552 uint32_t bfar; /* BusFault Address */ 553 uint32_t sfar; /* Secure Fault Address Register */ 554 unsigned mpu_ctrl[M_REG_NUM_BANKS]; /* MPU_CTRL */ 555 int exception; 556 uint32_t primask[M_REG_NUM_BANKS]; 557 uint32_t faultmask[M_REG_NUM_BANKS]; 558 uint32_t aircr; /* only holds r/w state if security extn implemented */ 559 uint32_t secure; /* Is CPU in Secure state? (not guest visible) */ 560 uint32_t csselr[M_REG_NUM_BANKS]; 561 uint32_t scr[M_REG_NUM_BANKS]; 562 uint32_t msplim[M_REG_NUM_BANKS]; 563 uint32_t psplim[M_REG_NUM_BANKS]; 564 uint32_t fpcar[M_REG_NUM_BANKS]; 565 uint32_t fpccr[M_REG_NUM_BANKS]; 566 uint32_t fpdscr[M_REG_NUM_BANKS]; 567 uint32_t cpacr[M_REG_NUM_BANKS]; 568 uint32_t nsacr; 569 uint32_t ltpsize; 570 uint32_t vpr; 571 } v7m; 572 573 /* Information associated with an exception about to be taken: 574 * code which raises an exception must set cs->exception_index and 575 * the relevant parts of this structure; the cpu_do_interrupt function 576 * will then set the guest-visible registers as part of the exception 577 * entry process. 578 */ 579 struct { 580 uint32_t syndrome; /* AArch64 format syndrome register */ 581 uint32_t fsr; /* AArch32 format fault status register info */ 582 uint64_t vaddress; /* virtual addr associated with exception, if any */ 583 uint32_t target_el; /* EL the exception should be targeted for */ 584 /* If we implement EL2 we will also need to store information 585 * about the intermediate physical address for stage 2 faults. 586 */ 587 } exception; 588 589 /* Information associated with an SError */ 590 struct { 591 uint8_t pending; 592 uint8_t has_esr; 593 uint64_t esr; 594 } serror; 595 596 uint8_t ext_dabt_raised; /* Tracking/verifying injection of ext DABT */ 597 598 /* State of our input IRQ/FIQ/VIRQ/VFIQ lines */ 599 uint32_t irq_line_state; 600 601 /* Thumb-2 EE state. */ 602 uint32_t teecr; 603 uint32_t teehbr; 604 605 /* VFP coprocessor state. */ 606 struct { 607 ARMVectorReg zregs[32]; 608 609 #ifdef TARGET_AARCH64 610 /* Store FFR as pregs[16] to make it easier to treat as any other. */ 611 #define FFR_PRED_NUM 16 612 ARMPredicateReg pregs[17]; 613 /* Scratch space for aa64 sve predicate temporary. */ 614 ARMPredicateReg preg_tmp; 615 #endif 616 617 /* We store these fpcsr fields separately for convenience. */ 618 uint32_t qc[4] QEMU_ALIGNED(16); 619 int vec_len; 620 int vec_stride; 621 622 uint32_t xregs[16]; 623 624 /* Scratch space for aa32 neon expansion. */ 625 uint32_t scratch[8]; 626 627 /* There are a number of distinct float control structures: 628 * 629 * fp_status: is the "normal" fp status. 630 * fp_status_fp16: used for half-precision calculations 631 * standard_fp_status : the ARM "Standard FPSCR Value" 632 * standard_fp_status_fp16 : used for half-precision 633 * calculations with the ARM "Standard FPSCR Value" 634 * 635 * Half-precision operations are governed by a separate 636 * flush-to-zero control bit in FPSCR:FZ16. We pass a separate 637 * status structure to control this. 638 * 639 * The "Standard FPSCR", ie default-NaN, flush-to-zero, 640 * round-to-nearest and is used by any operations (generally 641 * Neon) which the architecture defines as controlled by the 642 * standard FPSCR value rather than the FPSCR. 643 * 644 * The "standard FPSCR but for fp16 ops" is needed because 645 * the "standard FPSCR" tracks the FPSCR.FZ16 bit rather than 646 * using a fixed value for it. 647 * 648 * To avoid having to transfer exception bits around, we simply 649 * say that the FPSCR cumulative exception flags are the logical 650 * OR of the flags in the four fp statuses. This relies on the 651 * only thing which needs to read the exception flags being 652 * an explicit FPSCR read. 653 */ 654 float_status fp_status; 655 float_status fp_status_f16; 656 float_status standard_fp_status; 657 float_status standard_fp_status_f16; 658 659 uint64_t zcr_el[4]; /* ZCR_EL[1-3] */ 660 uint64_t smcr_el[4]; /* SMCR_EL[1-3] */ 661 } vfp; 662 663 uint64_t exclusive_addr; 664 uint64_t exclusive_val; 665 /* 666 * Contains the 'val' for the second 64-bit register of LDXP, which comes 667 * from the higher address, not the high part of a complete 128-bit value. 668 * In some ways it might be more convenient to record the exclusive value 669 * as the low and high halves of a 128 bit data value, but the current 670 * semantics of these fields are baked into the migration format. 671 */ 672 uint64_t exclusive_high; 673 674 /* iwMMXt coprocessor state. */ 675 struct { 676 uint64_t regs[16]; 677 uint64_t val; 678 679 uint32_t cregs[16]; 680 } iwmmxt; 681 682 #ifdef TARGET_AARCH64 683 struct { 684 ARMPACKey apia; 685 ARMPACKey apib; 686 ARMPACKey apda; 687 ARMPACKey apdb; 688 ARMPACKey apga; 689 } keys; 690 691 uint64_t scxtnum_el[4]; 692 693 /* 694 * SME ZA storage -- 256 x 256 byte array, with bytes in host word order, 695 * as we do with vfp.zregs[]. This corresponds to the architectural ZA 696 * array, where ZA[N] is in the least-significant bytes of env->zarray[N]. 697 * When SVL is less than the architectural maximum, the accessible 698 * storage is restricted, such that if the SVL is X bytes the guest can 699 * see only the bottom X elements of zarray[], and only the least 700 * significant X bytes of each element of the array. (In other words, 701 * the observable part is always square.) 702 * 703 * The ZA storage can also be considered as a set of square tiles of 704 * elements of different sizes. The mapping from tiles to the ZA array 705 * is architecturally defined, such that for tiles of elements of esz 706 * bytes, the Nth row (or "horizontal slice") of tile T is in 707 * ZA[T + N * esz]. Note that this means that each tile is not contiguous 708 * in the ZA storage, because its rows are striped through the ZA array. 709 * 710 * Because this is so large, keep this toward the end of the reset area, 711 * to keep the offsets into the rest of the structure smaller. 712 */ 713 ARMVectorReg zarray[ARM_MAX_VQ * 16]; 714 #endif 715 716 struct CPUBreakpoint *cpu_breakpoint[16]; 717 struct CPUWatchpoint *cpu_watchpoint[16]; 718 719 /* Optional fault info across tlb lookup. */ 720 ARMMMUFaultInfo *tlb_fi; 721 722 /* Fields up to this point are cleared by a CPU reset */ 723 struct {} end_reset_fields; 724 725 /* Fields after this point are preserved across CPU reset. */ 726 727 /* Internal CPU feature flags. */ 728 uint64_t features; 729 730 /* PMSAv7 MPU */ 731 struct { 732 uint32_t *drbar; 733 uint32_t *drsr; 734 uint32_t *dracr; 735 uint32_t rnr[M_REG_NUM_BANKS]; 736 } pmsav7; 737 738 /* PMSAv8 MPU */ 739 struct { 740 /* The PMSAv8 implementation also shares some PMSAv7 config 741 * and state: 742 * pmsav7.rnr (region number register) 743 * pmsav7_dregion (number of configured regions) 744 */ 745 uint32_t *rbar[M_REG_NUM_BANKS]; 746 uint32_t *rlar[M_REG_NUM_BANKS]; 747 uint32_t *hprbar; 748 uint32_t *hprlar; 749 uint32_t mair0[M_REG_NUM_BANKS]; 750 uint32_t mair1[M_REG_NUM_BANKS]; 751 uint32_t hprselr; 752 } pmsav8; 753 754 /* v8M SAU */ 755 struct { 756 uint32_t *rbar; 757 uint32_t *rlar; 758 uint32_t rnr; 759 uint32_t ctrl; 760 } sau; 761 762 #if !defined(CONFIG_USER_ONLY) 763 NVICState *nvic; 764 const struct arm_boot_info *boot_info; 765 /* Store GICv3CPUState to access from this struct */ 766 void *gicv3state; 767 #else /* CONFIG_USER_ONLY */ 768 /* For usermode syscall translation. */ 769 bool eabi; 770 #endif /* CONFIG_USER_ONLY */ 771 772 #ifdef TARGET_TAGGED_ADDRESSES 773 /* Linux syscall tagged address support */ 774 bool tagged_addr_enable; 775 #endif 776 } CPUARMState; 777 778 static inline void set_feature(CPUARMState *env, int feature) 779 { 780 env->features |= 1ULL << feature; 781 } 782 783 static inline void unset_feature(CPUARMState *env, int feature) 784 { 785 env->features &= ~(1ULL << feature); 786 } 787 788 /** 789 * ARMELChangeHookFn: 790 * type of a function which can be registered via arm_register_el_change_hook() 791 * to get callbacks when the CPU changes its exception level or mode. 792 */ 793 typedef void ARMELChangeHookFn(ARMCPU *cpu, void *opaque); 794 typedef struct ARMELChangeHook ARMELChangeHook; 795 struct ARMELChangeHook { 796 ARMELChangeHookFn *hook; 797 void *opaque; 798 QLIST_ENTRY(ARMELChangeHook) node; 799 }; 800 801 /* These values map onto the return values for 802 * QEMU_PSCI_0_2_FN_AFFINITY_INFO */ 803 typedef enum ARMPSCIState { 804 PSCI_ON = 0, 805 PSCI_OFF = 1, 806 PSCI_ON_PENDING = 2 807 } ARMPSCIState; 808 809 typedef struct ARMISARegisters ARMISARegisters; 810 811 /* 812 * In map, each set bit is a supported vector length of (bit-number + 1) * 16 813 * bytes, i.e. each bit number + 1 is the vector length in quadwords. 814 * 815 * While processing properties during initialization, corresponding init bits 816 * are set for bits in sve_vq_map that have been set by properties. 817 * 818 * Bits set in supported represent valid vector lengths for the CPU type. 819 */ 820 typedef struct { 821 uint32_t map, init, supported; 822 } ARMVQMap; 823 824 /** 825 * ARMCPU: 826 * @env: #CPUARMState 827 * 828 * An ARM CPU core. 829 */ 830 struct ArchCPU { 831 CPUState parent_obj; 832 833 CPUARMState env; 834 835 /* Coprocessor information */ 836 GHashTable *cp_regs; 837 /* For marshalling (mostly coprocessor) register state between the 838 * kernel and QEMU (for KVM) and between two QEMUs (for migration), 839 * we use these arrays. 840 */ 841 /* List of register indexes managed via these arrays; (full KVM style 842 * 64 bit indexes, not CPRegInfo 32 bit indexes) 843 */ 844 uint64_t *cpreg_indexes; 845 /* Values of the registers (cpreg_indexes[i]'s value is cpreg_values[i]) */ 846 uint64_t *cpreg_values; 847 /* Length of the indexes, values, reset_values arrays */ 848 int32_t cpreg_array_len; 849 /* These are used only for migration: incoming data arrives in 850 * these fields and is sanity checked in post_load before copying 851 * to the working data structures above. 852 */ 853 uint64_t *cpreg_vmstate_indexes; 854 uint64_t *cpreg_vmstate_values; 855 int32_t cpreg_vmstate_array_len; 856 857 DynamicGDBFeatureInfo dyn_sysreg_feature; 858 DynamicGDBFeatureInfo dyn_svereg_feature; 859 DynamicGDBFeatureInfo dyn_m_systemreg_feature; 860 DynamicGDBFeatureInfo dyn_m_secextreg_feature; 861 862 /* Timers used by the generic (architected) timer */ 863 QEMUTimer *gt_timer[NUM_GTIMERS]; 864 /* 865 * Timer used by the PMU. Its state is restored after migration by 866 * pmu_op_finish() - it does not need other handling during migration 867 */ 868 QEMUTimer *pmu_timer; 869 /* GPIO outputs for generic timer */ 870 qemu_irq gt_timer_outputs[NUM_GTIMERS]; 871 /* GPIO output for GICv3 maintenance interrupt signal */ 872 qemu_irq gicv3_maintenance_interrupt; 873 /* GPIO output for the PMU interrupt */ 874 qemu_irq pmu_interrupt; 875 876 /* MemoryRegion to use for secure physical accesses */ 877 MemoryRegion *secure_memory; 878 879 /* MemoryRegion to use for allocation tag accesses */ 880 MemoryRegion *tag_memory; 881 MemoryRegion *secure_tag_memory; 882 883 /* For v8M, pointer to the IDAU interface provided by board/SoC */ 884 Object *idau; 885 886 /* 'compatible' string for this CPU for Linux device trees */ 887 const char *dtb_compatible; 888 889 /* PSCI version for this CPU 890 * Bits[31:16] = Major Version 891 * Bits[15:0] = Minor Version 892 */ 893 uint32_t psci_version; 894 895 /* Current power state, access guarded by BQL */ 896 ARMPSCIState power_state; 897 898 /* CPU has virtualization extension */ 899 bool has_el2; 900 /* CPU has security extension */ 901 bool has_el3; 902 /* CPU has PMU (Performance Monitor Unit) */ 903 bool has_pmu; 904 /* CPU has VFP */ 905 bool has_vfp; 906 /* CPU has 32 VFP registers */ 907 bool has_vfp_d32; 908 /* CPU has Neon */ 909 bool has_neon; 910 /* CPU has M-profile DSP extension */ 911 bool has_dsp; 912 913 /* CPU has memory protection unit */ 914 bool has_mpu; 915 /* PMSAv7 MPU number of supported regions */ 916 uint32_t pmsav7_dregion; 917 /* PMSAv8 MPU number of supported hyp regions */ 918 uint32_t pmsav8r_hdregion; 919 /* v8M SAU number of supported regions */ 920 uint32_t sau_sregion; 921 922 /* PSCI conduit used to invoke PSCI methods 923 * 0 - disabled, 1 - smc, 2 - hvc 924 */ 925 uint32_t psci_conduit; 926 927 /* For v8M, initial value of the Secure VTOR */ 928 uint32_t init_svtor; 929 /* For v8M, initial value of the Non-secure VTOR */ 930 uint32_t init_nsvtor; 931 932 /* [QEMU_]KVM_ARM_TARGET_* constant for this CPU, or 933 * QEMU_KVM_ARM_TARGET_NONE if the kernel doesn't support this CPU type. 934 */ 935 uint32_t kvm_target; 936 937 #ifdef CONFIG_KVM 938 /* KVM init features for this CPU */ 939 uint32_t kvm_init_features[7]; 940 941 /* KVM CPU state */ 942 943 /* KVM virtual time adjustment */ 944 bool kvm_adjvtime; 945 bool kvm_vtime_dirty; 946 uint64_t kvm_vtime; 947 948 /* KVM steal time */ 949 OnOffAuto kvm_steal_time; 950 #endif /* CONFIG_KVM */ 951 952 /* Uniprocessor system with MP extensions */ 953 bool mp_is_up; 954 955 /* True if we tried kvm_arm_host_cpu_features() during CPU instance_init 956 * and the probe failed (so we need to report the error in realize) 957 */ 958 bool host_cpu_probe_failed; 959 960 /* Specify the number of cores in this CPU cluster. Used for the L2CTLR 961 * register. 962 */ 963 int32_t core_count; 964 965 /* The instance init functions for implementation-specific subclasses 966 * set these fields to specify the implementation-dependent values of 967 * various constant registers and reset values of non-constant 968 * registers. 969 * Some of these might become QOM properties eventually. 970 * Field names match the official register names as defined in the 971 * ARMv7AR ARM Architecture Reference Manual. A reset_ prefix 972 * is used for reset values of non-constant registers; no reset_ 973 * prefix means a constant register. 974 * Some of these registers are split out into a substructure that 975 * is shared with the translators to control the ISA. 976 * 977 * Note that if you add an ID register to the ARMISARegisters struct 978 * you need to also update the 32-bit and 64-bit versions of the 979 * kvm_arm_get_host_cpu_features() function to correctly populate the 980 * field by reading the value from the KVM vCPU. 981 */ 982 struct ARMISARegisters { 983 uint32_t id_isar0; 984 uint32_t id_isar1; 985 uint32_t id_isar2; 986 uint32_t id_isar3; 987 uint32_t id_isar4; 988 uint32_t id_isar5; 989 uint32_t id_isar6; 990 uint32_t id_mmfr0; 991 uint32_t id_mmfr1; 992 uint32_t id_mmfr2; 993 uint32_t id_mmfr3; 994 uint32_t id_mmfr4; 995 uint32_t id_mmfr5; 996 uint32_t id_pfr0; 997 uint32_t id_pfr1; 998 uint32_t id_pfr2; 999 uint32_t mvfr0; 1000 uint32_t mvfr1; 1001 uint32_t mvfr2; 1002 uint32_t id_dfr0; 1003 uint32_t id_dfr1; 1004 uint32_t dbgdidr; 1005 uint32_t dbgdevid; 1006 uint32_t dbgdevid1; 1007 uint64_t id_aa64isar0; 1008 uint64_t id_aa64isar1; 1009 uint64_t id_aa64isar2; 1010 uint64_t id_aa64pfr0; 1011 uint64_t id_aa64pfr1; 1012 uint64_t id_aa64mmfr0; 1013 uint64_t id_aa64mmfr1; 1014 uint64_t id_aa64mmfr2; 1015 uint64_t id_aa64dfr0; 1016 uint64_t id_aa64dfr1; 1017 uint64_t id_aa64zfr0; 1018 uint64_t id_aa64smfr0; 1019 uint64_t reset_pmcr_el0; 1020 } isar; 1021 uint64_t midr; 1022 uint32_t revidr; 1023 uint32_t reset_fpsid; 1024 uint64_t ctr; 1025 uint32_t reset_sctlr; 1026 uint64_t pmceid0; 1027 uint64_t pmceid1; 1028 uint32_t id_afr0; 1029 uint64_t id_aa64afr0; 1030 uint64_t id_aa64afr1; 1031 uint64_t clidr; 1032 uint64_t mp_affinity; /* MP ID without feature bits */ 1033 /* The elements of this array are the CCSIDR values for each cache, 1034 * in the order L1DCache, L1ICache, L2DCache, L2ICache, etc. 1035 */ 1036 uint64_t ccsidr[16]; 1037 uint64_t reset_cbar; 1038 uint32_t reset_auxcr; 1039 bool reset_hivecs; 1040 uint8_t reset_l0gptsz; 1041 1042 /* 1043 * Intermediate values used during property parsing. 1044 * Once finalized, the values should be read from ID_AA64*. 1045 */ 1046 bool prop_pauth; 1047 bool prop_pauth_impdef; 1048 bool prop_pauth_qarma3; 1049 bool prop_lpa2; 1050 1051 /* DCZ blocksize, in log_2(words), ie low 4 bits of DCZID_EL0 */ 1052 uint8_t dcz_blocksize; 1053 /* GM blocksize, in log_2(words), ie low 4 bits of GMID_EL0 */ 1054 uint8_t gm_blocksize; 1055 1056 uint64_t rvbar_prop; /* Property/input signals. */ 1057 1058 /* Configurable aspects of GIC cpu interface (which is part of the CPU) */ 1059 int gic_num_lrs; /* number of list registers */ 1060 int gic_vpribits; /* number of virtual priority bits */ 1061 int gic_vprebits; /* number of virtual preemption bits */ 1062 int gic_pribits; /* number of physical priority bits */ 1063 1064 /* Whether the cfgend input is high (i.e. this CPU should reset into 1065 * big-endian mode). This setting isn't used directly: instead it modifies 1066 * the reset_sctlr value to have SCTLR_B or SCTLR_EE set, depending on the 1067 * architecture version. 1068 */ 1069 bool cfgend; 1070 1071 QLIST_HEAD(, ARMELChangeHook) pre_el_change_hooks; 1072 QLIST_HEAD(, ARMELChangeHook) el_change_hooks; 1073 1074 int32_t node_id; /* NUMA node this CPU belongs to */ 1075 1076 /* Used to synchronize KVM and QEMU in-kernel device levels */ 1077 uint8_t device_irq_level; 1078 1079 /* Used to set the maximum vector length the cpu will support. */ 1080 uint32_t sve_max_vq; 1081 1082 #ifdef CONFIG_USER_ONLY 1083 /* Used to set the default vector length at process start. */ 1084 uint32_t sve_default_vq; 1085 uint32_t sme_default_vq; 1086 #endif 1087 1088 ARMVQMap sve_vq; 1089 ARMVQMap sme_vq; 1090 1091 /* Generic timer counter frequency, in Hz */ 1092 uint64_t gt_cntfrq_hz; 1093 }; 1094 1095 typedef struct ARMCPUInfo { 1096 const char *name; 1097 void (*initfn)(Object *obj); 1098 void (*class_init)(ObjectClass *oc, void *data); 1099 } ARMCPUInfo; 1100 1101 /** 1102 * ARMCPUClass: 1103 * @parent_realize: The parent class' realize handler. 1104 * @parent_phases: The parent class' reset phase handlers. 1105 * 1106 * An ARM CPU model. 1107 */ 1108 struct ARMCPUClass { 1109 CPUClass parent_class; 1110 1111 const ARMCPUInfo *info; 1112 DeviceRealize parent_realize; 1113 ResettablePhases parent_phases; 1114 }; 1115 1116 struct AArch64CPUClass { 1117 ARMCPUClass parent_class; 1118 }; 1119 1120 /* Callback functions for the generic timer's timers. */ 1121 void arm_gt_ptimer_cb(void *opaque); 1122 void arm_gt_vtimer_cb(void *opaque); 1123 void arm_gt_htimer_cb(void *opaque); 1124 void arm_gt_stimer_cb(void *opaque); 1125 void arm_gt_hvtimer_cb(void *opaque); 1126 1127 unsigned int gt_cntfrq_period_ns(ARMCPU *cpu); 1128 void gt_rme_post_el_change(ARMCPU *cpu, void *opaque); 1129 1130 void arm_cpu_post_init(Object *obj); 1131 1132 #define ARM_AFF0_SHIFT 0 1133 #define ARM_AFF0_MASK (0xFFULL << ARM_AFF0_SHIFT) 1134 #define ARM_AFF1_SHIFT 8 1135 #define ARM_AFF1_MASK (0xFFULL << ARM_AFF1_SHIFT) 1136 #define ARM_AFF2_SHIFT 16 1137 #define ARM_AFF2_MASK (0xFFULL << ARM_AFF2_SHIFT) 1138 #define ARM_AFF3_SHIFT 32 1139 #define ARM_AFF3_MASK (0xFFULL << ARM_AFF3_SHIFT) 1140 #define ARM_DEFAULT_CPUS_PER_CLUSTER 8 1141 1142 #define ARM32_AFFINITY_MASK (ARM_AFF0_MASK | ARM_AFF1_MASK | ARM_AFF2_MASK) 1143 #define ARM64_AFFINITY_MASK \ 1144 (ARM_AFF0_MASK | ARM_AFF1_MASK | ARM_AFF2_MASK | ARM_AFF3_MASK) 1145 #define ARM64_AFFINITY_INVALID (~ARM64_AFFINITY_MASK) 1146 1147 uint64_t arm_build_mp_affinity(int idx, uint8_t clustersz); 1148 1149 #ifndef CONFIG_USER_ONLY 1150 extern const VMStateDescription vmstate_arm_cpu; 1151 1152 void arm_cpu_do_interrupt(CPUState *cpu); 1153 void arm_v7m_cpu_do_interrupt(CPUState *cpu); 1154 1155 hwaddr arm_cpu_get_phys_page_attrs_debug(CPUState *cpu, vaddr addr, 1156 MemTxAttrs *attrs); 1157 #endif /* !CONFIG_USER_ONLY */ 1158 1159 int arm_cpu_gdb_read_register(CPUState *cpu, GByteArray *buf, int reg); 1160 int arm_cpu_gdb_write_register(CPUState *cpu, uint8_t *buf, int reg); 1161 1162 int arm_cpu_write_elf64_note(WriteCoreDumpFunction f, CPUState *cs, 1163 int cpuid, DumpState *s); 1164 int arm_cpu_write_elf32_note(WriteCoreDumpFunction f, CPUState *cs, 1165 int cpuid, DumpState *s); 1166 1167 /** 1168 * arm_emulate_firmware_reset: Emulate firmware CPU reset handling 1169 * @cpu: CPU (which must have been freshly reset) 1170 * @target_el: exception level to put the CPU into 1171 * @secure: whether to put the CPU in secure state 1172 * 1173 * When QEMU is directly running a guest kernel at a lower level than 1174 * EL3 it implicitly emulates some aspects of the guest firmware. 1175 * This includes that on reset we need to configure the parts of the 1176 * CPU corresponding to EL3 so that the real guest code can run at its 1177 * lower exception level. This function does that post-reset CPU setup, 1178 * for when we do direct boot of a guest kernel, and for when we 1179 * emulate PSCI and similar firmware interfaces starting a CPU at a 1180 * lower exception level. 1181 * 1182 * @target_el must be an EL implemented by the CPU between 1 and 3. 1183 * We do not support dropping into a Secure EL other than 3. 1184 * 1185 * It is the responsibility of the caller to call arm_rebuild_hflags(). 1186 */ 1187 void arm_emulate_firmware_reset(CPUState *cpustate, int target_el); 1188 1189 #ifdef TARGET_AARCH64 1190 int aarch64_cpu_gdb_read_register(CPUState *cpu, GByteArray *buf, int reg); 1191 int aarch64_cpu_gdb_write_register(CPUState *cpu, uint8_t *buf, int reg); 1192 void aarch64_sve_narrow_vq(CPUARMState *env, unsigned vq); 1193 void aarch64_sve_change_el(CPUARMState *env, int old_el, 1194 int new_el, bool el0_a64); 1195 void aarch64_set_svcr(CPUARMState *env, uint64_t new, uint64_t mask); 1196 1197 /* 1198 * SVE registers are encoded in KVM's memory in an endianness-invariant format. 1199 * The byte at offset i from the start of the in-memory representation contains 1200 * the bits [(7 + 8 * i) : (8 * i)] of the register value. As this means the 1201 * lowest offsets are stored in the lowest memory addresses, then that nearly 1202 * matches QEMU's representation, which is to use an array of host-endian 1203 * uint64_t's, where the lower offsets are at the lower indices. To complete 1204 * the translation we just need to byte swap the uint64_t's on big-endian hosts. 1205 */ 1206 static inline uint64_t *sve_bswap64(uint64_t *dst, uint64_t *src, int nr) 1207 { 1208 #if HOST_BIG_ENDIAN 1209 int i; 1210 1211 for (i = 0; i < nr; ++i) { 1212 dst[i] = bswap64(src[i]); 1213 } 1214 1215 return dst; 1216 #else 1217 return src; 1218 #endif 1219 } 1220 1221 #else 1222 static inline void aarch64_sve_narrow_vq(CPUARMState *env, unsigned vq) { } 1223 static inline void aarch64_sve_change_el(CPUARMState *env, int o, 1224 int n, bool a) 1225 { } 1226 #endif 1227 1228 void aarch64_sync_32_to_64(CPUARMState *env); 1229 void aarch64_sync_64_to_32(CPUARMState *env); 1230 1231 int fp_exception_el(CPUARMState *env, int cur_el); 1232 int sve_exception_el(CPUARMState *env, int cur_el); 1233 int sme_exception_el(CPUARMState *env, int cur_el); 1234 1235 /** 1236 * sve_vqm1_for_el_sm: 1237 * @env: CPUARMState 1238 * @el: exception level 1239 * @sm: streaming mode 1240 * 1241 * Compute the current vector length for @el & @sm, in units of 1242 * Quadwords Minus 1 -- the same scale used for ZCR_ELx.LEN. 1243 * If @sm, compute for SVL, otherwise NVL. 1244 */ 1245 uint32_t sve_vqm1_for_el_sm(CPUARMState *env, int el, bool sm); 1246 1247 /* Likewise, but using @sm = PSTATE.SM. */ 1248 uint32_t sve_vqm1_for_el(CPUARMState *env, int el); 1249 1250 static inline bool is_a64(CPUARMState *env) 1251 { 1252 return env->aarch64; 1253 } 1254 1255 /** 1256 * pmu_op_start/finish 1257 * @env: CPUARMState 1258 * 1259 * Convert all PMU counters between their delta form (the typical mode when 1260 * they are enabled) and the guest-visible values. These two calls must 1261 * surround any action which might affect the counters. 1262 */ 1263 void pmu_op_start(CPUARMState *env); 1264 void pmu_op_finish(CPUARMState *env); 1265 1266 /* 1267 * Called when a PMU counter is due to overflow 1268 */ 1269 void arm_pmu_timer_cb(void *opaque); 1270 1271 /** 1272 * Functions to register as EL change hooks for PMU mode filtering 1273 */ 1274 void pmu_pre_el_change(ARMCPU *cpu, void *ignored); 1275 void pmu_post_el_change(ARMCPU *cpu, void *ignored); 1276 1277 /* 1278 * pmu_init 1279 * @cpu: ARMCPU 1280 * 1281 * Initialize the CPU's PMCEID[01]_EL0 registers and associated internal state 1282 * for the current configuration 1283 */ 1284 void pmu_init(ARMCPU *cpu); 1285 1286 /* SCTLR bit meanings. Several bits have been reused in newer 1287 * versions of the architecture; in that case we define constants 1288 * for both old and new bit meanings. Code which tests against those 1289 * bits should probably check or otherwise arrange that the CPU 1290 * is the architectural version it expects. 1291 */ 1292 #define SCTLR_M (1U << 0) 1293 #define SCTLR_A (1U << 1) 1294 #define SCTLR_C (1U << 2) 1295 #define SCTLR_W (1U << 3) /* up to v6; RAO in v7 */ 1296 #define SCTLR_nTLSMD_32 (1U << 3) /* v8.2-LSMAOC, AArch32 only */ 1297 #define SCTLR_SA (1U << 3) /* AArch64 only */ 1298 #define SCTLR_P (1U << 4) /* up to v5; RAO in v6 and v7 */ 1299 #define SCTLR_LSMAOE_32 (1U << 4) /* v8.2-LSMAOC, AArch32 only */ 1300 #define SCTLR_SA0 (1U << 4) /* v8 onward, AArch64 only */ 1301 #define SCTLR_D (1U << 5) /* up to v5; RAO in v6 */ 1302 #define SCTLR_CP15BEN (1U << 5) /* v7 onward */ 1303 #define SCTLR_L (1U << 6) /* up to v5; RAO in v6 and v7; RAZ in v8 */ 1304 #define SCTLR_nAA (1U << 6) /* when FEAT_LSE2 is implemented */ 1305 #define SCTLR_B (1U << 7) /* up to v6; RAZ in v7 */ 1306 #define SCTLR_ITD (1U << 7) /* v8 onward */ 1307 #define SCTLR_S (1U << 8) /* up to v6; RAZ in v7 */ 1308 #define SCTLR_SED (1U << 8) /* v8 onward */ 1309 #define SCTLR_R (1U << 9) /* up to v6; RAZ in v7 */ 1310 #define SCTLR_UMA (1U << 9) /* v8 onward, AArch64 only */ 1311 #define SCTLR_F (1U << 10) /* up to v6 */ 1312 #define SCTLR_SW (1U << 10) /* v7 */ 1313 #define SCTLR_EnRCTX (1U << 10) /* in v8.0-PredInv */ 1314 #define SCTLR_Z (1U << 11) /* in v7, RES1 in v8 */ 1315 #define SCTLR_EOS (1U << 11) /* v8.5-ExS */ 1316 #define SCTLR_I (1U << 12) 1317 #define SCTLR_V (1U << 13) /* AArch32 only */ 1318 #define SCTLR_EnDB (1U << 13) /* v8.3, AArch64 only */ 1319 #define SCTLR_RR (1U << 14) /* up to v7 */ 1320 #define SCTLR_DZE (1U << 14) /* v8 onward, AArch64 only */ 1321 #define SCTLR_L4 (1U << 15) /* up to v6; RAZ in v7 */ 1322 #define SCTLR_UCT (1U << 15) /* v8 onward, AArch64 only */ 1323 #define SCTLR_DT (1U << 16) /* up to ??, RAO in v6 and v7 */ 1324 #define SCTLR_nTWI (1U << 16) /* v8 onward */ 1325 #define SCTLR_HA (1U << 17) /* up to v7, RES0 in v8 */ 1326 #define SCTLR_BR (1U << 17) /* PMSA only */ 1327 #define SCTLR_IT (1U << 18) /* up to ??, RAO in v6 and v7 */ 1328 #define SCTLR_nTWE (1U << 18) /* v8 onward */ 1329 #define SCTLR_WXN (1U << 19) 1330 #define SCTLR_ST (1U << 20) /* up to ??, RAZ in v6 */ 1331 #define SCTLR_UWXN (1U << 20) /* v7 onward, AArch32 only */ 1332 #define SCTLR_TSCXT (1U << 20) /* FEAT_CSV2_1p2, AArch64 only */ 1333 #define SCTLR_FI (1U << 21) /* up to v7, v8 RES0 */ 1334 #define SCTLR_IESB (1U << 21) /* v8.2-IESB, AArch64 only */ 1335 #define SCTLR_U (1U << 22) /* up to v6, RAO in v7 */ 1336 #define SCTLR_EIS (1U << 22) /* v8.5-ExS */ 1337 #define SCTLR_XP (1U << 23) /* up to v6; v7 onward RAO */ 1338 #define SCTLR_SPAN (1U << 23) /* v8.1-PAN */ 1339 #define SCTLR_VE (1U << 24) /* up to v7 */ 1340 #define SCTLR_E0E (1U << 24) /* v8 onward, AArch64 only */ 1341 #define SCTLR_EE (1U << 25) 1342 #define SCTLR_L2 (1U << 26) /* up to v6, RAZ in v7 */ 1343 #define SCTLR_UCI (1U << 26) /* v8 onward, AArch64 only */ 1344 #define SCTLR_NMFI (1U << 27) /* up to v7, RAZ in v7VE and v8 */ 1345 #define SCTLR_EnDA (1U << 27) /* v8.3, AArch64 only */ 1346 #define SCTLR_TRE (1U << 28) /* AArch32 only */ 1347 #define SCTLR_nTLSMD_64 (1U << 28) /* v8.2-LSMAOC, AArch64 only */ 1348 #define SCTLR_AFE (1U << 29) /* AArch32 only */ 1349 #define SCTLR_LSMAOE_64 (1U << 29) /* v8.2-LSMAOC, AArch64 only */ 1350 #define SCTLR_TE (1U << 30) /* AArch32 only */ 1351 #define SCTLR_EnIB (1U << 30) /* v8.3, AArch64 only */ 1352 #define SCTLR_EnIA (1U << 31) /* v8.3, AArch64 only */ 1353 #define SCTLR_DSSBS_32 (1U << 31) /* v8.5, AArch32 only */ 1354 #define SCTLR_MSCEN (1ULL << 33) /* FEAT_MOPS */ 1355 #define SCTLR_BT0 (1ULL << 35) /* v8.5-BTI */ 1356 #define SCTLR_BT1 (1ULL << 36) /* v8.5-BTI */ 1357 #define SCTLR_ITFSB (1ULL << 37) /* v8.5-MemTag */ 1358 #define SCTLR_TCF0 (3ULL << 38) /* v8.5-MemTag */ 1359 #define SCTLR_TCF (3ULL << 40) /* v8.5-MemTag */ 1360 #define SCTLR_ATA0 (1ULL << 42) /* v8.5-MemTag */ 1361 #define SCTLR_ATA (1ULL << 43) /* v8.5-MemTag */ 1362 #define SCTLR_DSSBS_64 (1ULL << 44) /* v8.5, AArch64 only */ 1363 #define SCTLR_TWEDEn (1ULL << 45) /* FEAT_TWED */ 1364 #define SCTLR_TWEDEL MAKE_64_MASK(46, 4) /* FEAT_TWED */ 1365 #define SCTLR_TMT0 (1ULL << 50) /* FEAT_TME */ 1366 #define SCTLR_TMT (1ULL << 51) /* FEAT_TME */ 1367 #define SCTLR_TME0 (1ULL << 52) /* FEAT_TME */ 1368 #define SCTLR_TME (1ULL << 53) /* FEAT_TME */ 1369 #define SCTLR_EnASR (1ULL << 54) /* FEAT_LS64_V */ 1370 #define SCTLR_EnAS0 (1ULL << 55) /* FEAT_LS64_ACCDATA */ 1371 #define SCTLR_EnALS (1ULL << 56) /* FEAT_LS64 */ 1372 #define SCTLR_EPAN (1ULL << 57) /* FEAT_PAN3 */ 1373 #define SCTLR_EnTP2 (1ULL << 60) /* FEAT_SME */ 1374 #define SCTLR_NMI (1ULL << 61) /* FEAT_NMI */ 1375 #define SCTLR_SPINTMASK (1ULL << 62) /* FEAT_NMI */ 1376 #define SCTLR_TIDCP (1ULL << 63) /* FEAT_TIDCP1 */ 1377 1378 /* Bit definitions for CPACR (AArch32 only) */ 1379 FIELD(CPACR, CP10, 20, 2) 1380 FIELD(CPACR, CP11, 22, 2) 1381 FIELD(CPACR, TRCDIS, 28, 1) /* matches CPACR_EL1.TTA */ 1382 FIELD(CPACR, D32DIS, 30, 1) /* up to v7; RAZ in v8 */ 1383 FIELD(CPACR, ASEDIS, 31, 1) 1384 1385 /* Bit definitions for CPACR_EL1 (AArch64 only) */ 1386 FIELD(CPACR_EL1, ZEN, 16, 2) 1387 FIELD(CPACR_EL1, FPEN, 20, 2) 1388 FIELD(CPACR_EL1, SMEN, 24, 2) 1389 FIELD(CPACR_EL1, TTA, 28, 1) /* matches CPACR.TRCDIS */ 1390 1391 /* Bit definitions for HCPTR (AArch32 only) */ 1392 FIELD(HCPTR, TCP10, 10, 1) 1393 FIELD(HCPTR, TCP11, 11, 1) 1394 FIELD(HCPTR, TASE, 15, 1) 1395 FIELD(HCPTR, TTA, 20, 1) 1396 FIELD(HCPTR, TAM, 30, 1) /* matches CPTR_EL2.TAM */ 1397 FIELD(HCPTR, TCPAC, 31, 1) /* matches CPTR_EL2.TCPAC */ 1398 1399 /* Bit definitions for CPTR_EL2 (AArch64 only) */ 1400 FIELD(CPTR_EL2, TZ, 8, 1) /* !E2H */ 1401 FIELD(CPTR_EL2, TFP, 10, 1) /* !E2H, matches HCPTR.TCP10 */ 1402 FIELD(CPTR_EL2, TSM, 12, 1) /* !E2H */ 1403 FIELD(CPTR_EL2, ZEN, 16, 2) /* E2H */ 1404 FIELD(CPTR_EL2, FPEN, 20, 2) /* E2H */ 1405 FIELD(CPTR_EL2, SMEN, 24, 2) /* E2H */ 1406 FIELD(CPTR_EL2, TTA, 28, 1) 1407 FIELD(CPTR_EL2, TAM, 30, 1) /* matches HCPTR.TAM */ 1408 FIELD(CPTR_EL2, TCPAC, 31, 1) /* matches HCPTR.TCPAC */ 1409 1410 /* Bit definitions for CPTR_EL3 (AArch64 only) */ 1411 FIELD(CPTR_EL3, EZ, 8, 1) 1412 FIELD(CPTR_EL3, TFP, 10, 1) 1413 FIELD(CPTR_EL3, ESM, 12, 1) 1414 FIELD(CPTR_EL3, TTA, 20, 1) 1415 FIELD(CPTR_EL3, TAM, 30, 1) 1416 FIELD(CPTR_EL3, TCPAC, 31, 1) 1417 1418 #define MDCR_MTPME (1U << 28) 1419 #define MDCR_TDCC (1U << 27) 1420 #define MDCR_HLP (1U << 26) /* MDCR_EL2 */ 1421 #define MDCR_SCCD (1U << 23) /* MDCR_EL3 */ 1422 #define MDCR_HCCD (1U << 23) /* MDCR_EL2 */ 1423 #define MDCR_EPMAD (1U << 21) 1424 #define MDCR_EDAD (1U << 20) 1425 #define MDCR_TTRF (1U << 19) 1426 #define MDCR_STE (1U << 18) /* MDCR_EL3 */ 1427 #define MDCR_SPME (1U << 17) /* MDCR_EL3 */ 1428 #define MDCR_HPMD (1U << 17) /* MDCR_EL2 */ 1429 #define MDCR_SDD (1U << 16) 1430 #define MDCR_SPD (3U << 14) 1431 #define MDCR_TDRA (1U << 11) 1432 #define MDCR_TDOSA (1U << 10) 1433 #define MDCR_TDA (1U << 9) 1434 #define MDCR_TDE (1U << 8) 1435 #define MDCR_HPME (1U << 7) 1436 #define MDCR_TPM (1U << 6) 1437 #define MDCR_TPMCR (1U << 5) 1438 #define MDCR_HPMN (0x1fU) 1439 1440 /* Not all of the MDCR_EL3 bits are present in the 32-bit SDCR */ 1441 #define SDCR_VALID_MASK (MDCR_MTPME | MDCR_TDCC | MDCR_SCCD | \ 1442 MDCR_EPMAD | MDCR_EDAD | MDCR_TTRF | \ 1443 MDCR_STE | MDCR_SPME | MDCR_SPD) 1444 1445 #define CPSR_M (0x1fU) 1446 #define CPSR_T (1U << 5) 1447 #define CPSR_F (1U << 6) 1448 #define CPSR_I (1U << 7) 1449 #define CPSR_A (1U << 8) 1450 #define CPSR_E (1U << 9) 1451 #define CPSR_IT_2_7 (0xfc00U) 1452 #define CPSR_GE (0xfU << 16) 1453 #define CPSR_IL (1U << 20) 1454 #define CPSR_DIT (1U << 21) 1455 #define CPSR_PAN (1U << 22) 1456 #define CPSR_SSBS (1U << 23) 1457 #define CPSR_J (1U << 24) 1458 #define CPSR_IT_0_1 (3U << 25) 1459 #define CPSR_Q (1U << 27) 1460 #define CPSR_V (1U << 28) 1461 #define CPSR_C (1U << 29) 1462 #define CPSR_Z (1U << 30) 1463 #define CPSR_N (1U << 31) 1464 #define CPSR_NZCV (CPSR_N | CPSR_Z | CPSR_C | CPSR_V) 1465 #define CPSR_AIF (CPSR_A | CPSR_I | CPSR_F) 1466 1467 #define CPSR_IT (CPSR_IT_0_1 | CPSR_IT_2_7) 1468 #define CACHED_CPSR_BITS (CPSR_T | CPSR_AIF | CPSR_GE | CPSR_IT | CPSR_Q \ 1469 | CPSR_NZCV) 1470 /* Bits writable in user mode. */ 1471 #define CPSR_USER (CPSR_NZCV | CPSR_Q | CPSR_GE | CPSR_E) 1472 /* Execution state bits. MRS read as zero, MSR writes ignored. */ 1473 #define CPSR_EXEC (CPSR_T | CPSR_IT | CPSR_J | CPSR_IL) 1474 1475 /* Bit definitions for M profile XPSR. Most are the same as CPSR. */ 1476 #define XPSR_EXCP 0x1ffU 1477 #define XPSR_SPREALIGN (1U << 9) /* Only set in exception stack frames */ 1478 #define XPSR_IT_2_7 CPSR_IT_2_7 1479 #define XPSR_GE CPSR_GE 1480 #define XPSR_SFPA (1U << 20) /* Only set in exception stack frames */ 1481 #define XPSR_T (1U << 24) /* Not the same as CPSR_T ! */ 1482 #define XPSR_IT_0_1 CPSR_IT_0_1 1483 #define XPSR_Q CPSR_Q 1484 #define XPSR_V CPSR_V 1485 #define XPSR_C CPSR_C 1486 #define XPSR_Z CPSR_Z 1487 #define XPSR_N CPSR_N 1488 #define XPSR_NZCV CPSR_NZCV 1489 #define XPSR_IT CPSR_IT 1490 1491 #define TTBCR_N (7U << 0) /* TTBCR.EAE==0 */ 1492 #define TTBCR_T0SZ (7U << 0) /* TTBCR.EAE==1 */ 1493 #define TTBCR_PD0 (1U << 4) 1494 #define TTBCR_PD1 (1U << 5) 1495 #define TTBCR_EPD0 (1U << 7) 1496 #define TTBCR_IRGN0 (3U << 8) 1497 #define TTBCR_ORGN0 (3U << 10) 1498 #define TTBCR_SH0 (3U << 12) 1499 #define TTBCR_T1SZ (3U << 16) 1500 #define TTBCR_A1 (1U << 22) 1501 #define TTBCR_EPD1 (1U << 23) 1502 #define TTBCR_IRGN1 (3U << 24) 1503 #define TTBCR_ORGN1 (3U << 26) 1504 #define TTBCR_SH1 (1U << 28) 1505 #define TTBCR_EAE (1U << 31) 1506 1507 FIELD(VTCR, T0SZ, 0, 6) 1508 FIELD(VTCR, SL0, 6, 2) 1509 FIELD(VTCR, IRGN0, 8, 2) 1510 FIELD(VTCR, ORGN0, 10, 2) 1511 FIELD(VTCR, SH0, 12, 2) 1512 FIELD(VTCR, TG0, 14, 2) 1513 FIELD(VTCR, PS, 16, 3) 1514 FIELD(VTCR, VS, 19, 1) 1515 FIELD(VTCR, HA, 21, 1) 1516 FIELD(VTCR, HD, 22, 1) 1517 FIELD(VTCR, HWU59, 25, 1) 1518 FIELD(VTCR, HWU60, 26, 1) 1519 FIELD(VTCR, HWU61, 27, 1) 1520 FIELD(VTCR, HWU62, 28, 1) 1521 FIELD(VTCR, NSW, 29, 1) 1522 FIELD(VTCR, NSA, 30, 1) 1523 FIELD(VTCR, DS, 32, 1) 1524 FIELD(VTCR, SL2, 33, 1) 1525 1526 /* Bit definitions for ARMv8 SPSR (PSTATE) format. 1527 * Only these are valid when in AArch64 mode; in 1528 * AArch32 mode SPSRs are basically CPSR-format. 1529 */ 1530 #define PSTATE_SP (1U) 1531 #define PSTATE_M (0xFU) 1532 #define PSTATE_nRW (1U << 4) 1533 #define PSTATE_F (1U << 6) 1534 #define PSTATE_I (1U << 7) 1535 #define PSTATE_A (1U << 8) 1536 #define PSTATE_D (1U << 9) 1537 #define PSTATE_BTYPE (3U << 10) 1538 #define PSTATE_SSBS (1U << 12) 1539 #define PSTATE_IL (1U << 20) 1540 #define PSTATE_SS (1U << 21) 1541 #define PSTATE_PAN (1U << 22) 1542 #define PSTATE_UAO (1U << 23) 1543 #define PSTATE_DIT (1U << 24) 1544 #define PSTATE_TCO (1U << 25) 1545 #define PSTATE_V (1U << 28) 1546 #define PSTATE_C (1U << 29) 1547 #define PSTATE_Z (1U << 30) 1548 #define PSTATE_N (1U << 31) 1549 #define PSTATE_NZCV (PSTATE_N | PSTATE_Z | PSTATE_C | PSTATE_V) 1550 #define PSTATE_DAIF (PSTATE_D | PSTATE_A | PSTATE_I | PSTATE_F) 1551 #define CACHED_PSTATE_BITS (PSTATE_NZCV | PSTATE_DAIF | PSTATE_BTYPE) 1552 /* Mode values for AArch64 */ 1553 #define PSTATE_MODE_EL3h 13 1554 #define PSTATE_MODE_EL3t 12 1555 #define PSTATE_MODE_EL2h 9 1556 #define PSTATE_MODE_EL2t 8 1557 #define PSTATE_MODE_EL1h 5 1558 #define PSTATE_MODE_EL1t 4 1559 #define PSTATE_MODE_EL0t 0 1560 1561 /* PSTATE bits that are accessed via SVCR and not stored in SPSR_ELx. */ 1562 FIELD(SVCR, SM, 0, 1) 1563 FIELD(SVCR, ZA, 1, 1) 1564 1565 /* Fields for SMCR_ELx. */ 1566 FIELD(SMCR, LEN, 0, 4) 1567 FIELD(SMCR, FA64, 31, 1) 1568 1569 /* Write a new value to v7m.exception, thus transitioning into or out 1570 * of Handler mode; this may result in a change of active stack pointer. 1571 */ 1572 void write_v7m_exception(CPUARMState *env, uint32_t new_exc); 1573 1574 /* Map EL and handler into a PSTATE_MODE. */ 1575 static inline unsigned int aarch64_pstate_mode(unsigned int el, bool handler) 1576 { 1577 return (el << 2) | handler; 1578 } 1579 1580 /* Return the current PSTATE value. For the moment we don't support 32<->64 bit 1581 * interprocessing, so we don't attempt to sync with the cpsr state used by 1582 * the 32 bit decoder. 1583 */ 1584 static inline uint32_t pstate_read(CPUARMState *env) 1585 { 1586 int ZF; 1587 1588 ZF = (env->ZF == 0); 1589 return (env->NF & 0x80000000) | (ZF << 30) 1590 | (env->CF << 29) | ((env->VF & 0x80000000) >> 3) 1591 | env->pstate | env->daif | (env->btype << 10); 1592 } 1593 1594 static inline void pstate_write(CPUARMState *env, uint32_t val) 1595 { 1596 env->ZF = (~val) & PSTATE_Z; 1597 env->NF = val; 1598 env->CF = (val >> 29) & 1; 1599 env->VF = (val << 3) & 0x80000000; 1600 env->daif = val & PSTATE_DAIF; 1601 env->btype = (val >> 10) & 3; 1602 env->pstate = val & ~CACHED_PSTATE_BITS; 1603 } 1604 1605 /* Return the current CPSR value. */ 1606 uint32_t cpsr_read(CPUARMState *env); 1607 1608 typedef enum CPSRWriteType { 1609 CPSRWriteByInstr = 0, /* from guest MSR or CPS */ 1610 CPSRWriteExceptionReturn = 1, /* from guest exception return insn */ 1611 CPSRWriteRaw = 2, 1612 /* trust values, no reg bank switch, no hflags rebuild */ 1613 CPSRWriteByGDBStub = 3, /* from the GDB stub */ 1614 } CPSRWriteType; 1615 1616 /* 1617 * Set the CPSR. Note that some bits of mask must be all-set or all-clear. 1618 * This will do an arm_rebuild_hflags() if any of the bits in @mask 1619 * correspond to TB flags bits cached in the hflags, unless @write_type 1620 * is CPSRWriteRaw. 1621 */ 1622 void cpsr_write(CPUARMState *env, uint32_t val, uint32_t mask, 1623 CPSRWriteType write_type); 1624 1625 /* Return the current xPSR value. */ 1626 static inline uint32_t xpsr_read(CPUARMState *env) 1627 { 1628 int ZF; 1629 ZF = (env->ZF == 0); 1630 return (env->NF & 0x80000000) | (ZF << 30) 1631 | (env->CF << 29) | ((env->VF & 0x80000000) >> 3) | (env->QF << 27) 1632 | (env->thumb << 24) | ((env->condexec_bits & 3) << 25) 1633 | ((env->condexec_bits & 0xfc) << 8) 1634 | (env->GE << 16) 1635 | env->v7m.exception; 1636 } 1637 1638 /* Set the xPSR. Note that some bits of mask must be all-set or all-clear. */ 1639 static inline void xpsr_write(CPUARMState *env, uint32_t val, uint32_t mask) 1640 { 1641 if (mask & XPSR_NZCV) { 1642 env->ZF = (~val) & XPSR_Z; 1643 env->NF = val; 1644 env->CF = (val >> 29) & 1; 1645 env->VF = (val << 3) & 0x80000000; 1646 } 1647 if (mask & XPSR_Q) { 1648 env->QF = ((val & XPSR_Q) != 0); 1649 } 1650 if (mask & XPSR_GE) { 1651 env->GE = (val & XPSR_GE) >> 16; 1652 } 1653 #ifndef CONFIG_USER_ONLY 1654 if (mask & XPSR_T) { 1655 env->thumb = ((val & XPSR_T) != 0); 1656 } 1657 if (mask & XPSR_IT_0_1) { 1658 env->condexec_bits &= ~3; 1659 env->condexec_bits |= (val >> 25) & 3; 1660 } 1661 if (mask & XPSR_IT_2_7) { 1662 env->condexec_bits &= 3; 1663 env->condexec_bits |= (val >> 8) & 0xfc; 1664 } 1665 if (mask & XPSR_EXCP) { 1666 /* Note that this only happens on exception exit */ 1667 write_v7m_exception(env, val & XPSR_EXCP); 1668 } 1669 #endif 1670 } 1671 1672 #define HCR_VM (1ULL << 0) 1673 #define HCR_SWIO (1ULL << 1) 1674 #define HCR_PTW (1ULL << 2) 1675 #define HCR_FMO (1ULL << 3) 1676 #define HCR_IMO (1ULL << 4) 1677 #define HCR_AMO (1ULL << 5) 1678 #define HCR_VF (1ULL << 6) 1679 #define HCR_VI (1ULL << 7) 1680 #define HCR_VSE (1ULL << 8) 1681 #define HCR_FB (1ULL << 9) 1682 #define HCR_BSU_MASK (3ULL << 10) 1683 #define HCR_DC (1ULL << 12) 1684 #define HCR_TWI (1ULL << 13) 1685 #define HCR_TWE (1ULL << 14) 1686 #define HCR_TID0 (1ULL << 15) 1687 #define HCR_TID1 (1ULL << 16) 1688 #define HCR_TID2 (1ULL << 17) 1689 #define HCR_TID3 (1ULL << 18) 1690 #define HCR_TSC (1ULL << 19) 1691 #define HCR_TIDCP (1ULL << 20) 1692 #define HCR_TACR (1ULL << 21) 1693 #define HCR_TSW (1ULL << 22) 1694 #define HCR_TPCP (1ULL << 23) 1695 #define HCR_TPU (1ULL << 24) 1696 #define HCR_TTLB (1ULL << 25) 1697 #define HCR_TVM (1ULL << 26) 1698 #define HCR_TGE (1ULL << 27) 1699 #define HCR_TDZ (1ULL << 28) 1700 #define HCR_HCD (1ULL << 29) 1701 #define HCR_TRVM (1ULL << 30) 1702 #define HCR_RW (1ULL << 31) 1703 #define HCR_CD (1ULL << 32) 1704 #define HCR_ID (1ULL << 33) 1705 #define HCR_E2H (1ULL << 34) 1706 #define HCR_TLOR (1ULL << 35) 1707 #define HCR_TERR (1ULL << 36) 1708 #define HCR_TEA (1ULL << 37) 1709 #define HCR_MIOCNCE (1ULL << 38) 1710 #define HCR_TME (1ULL << 39) 1711 #define HCR_APK (1ULL << 40) 1712 #define HCR_API (1ULL << 41) 1713 #define HCR_NV (1ULL << 42) 1714 #define HCR_NV1 (1ULL << 43) 1715 #define HCR_AT (1ULL << 44) 1716 #define HCR_NV2 (1ULL << 45) 1717 #define HCR_FWB (1ULL << 46) 1718 #define HCR_FIEN (1ULL << 47) 1719 #define HCR_GPF (1ULL << 48) 1720 #define HCR_TID4 (1ULL << 49) 1721 #define HCR_TICAB (1ULL << 50) 1722 #define HCR_AMVOFFEN (1ULL << 51) 1723 #define HCR_TOCU (1ULL << 52) 1724 #define HCR_ENSCXT (1ULL << 53) 1725 #define HCR_TTLBIS (1ULL << 54) 1726 #define HCR_TTLBOS (1ULL << 55) 1727 #define HCR_ATA (1ULL << 56) 1728 #define HCR_DCT (1ULL << 57) 1729 #define HCR_TID5 (1ULL << 58) 1730 #define HCR_TWEDEN (1ULL << 59) 1731 #define HCR_TWEDEL MAKE_64BIT_MASK(60, 4) 1732 1733 #define HCRX_ENAS0 (1ULL << 0) 1734 #define HCRX_ENALS (1ULL << 1) 1735 #define HCRX_ENASR (1ULL << 2) 1736 #define HCRX_FNXS (1ULL << 3) 1737 #define HCRX_FGTNXS (1ULL << 4) 1738 #define HCRX_SMPME (1ULL << 5) 1739 #define HCRX_TALLINT (1ULL << 6) 1740 #define HCRX_VINMI (1ULL << 7) 1741 #define HCRX_VFNMI (1ULL << 8) 1742 #define HCRX_CMOW (1ULL << 9) 1743 #define HCRX_MCE2 (1ULL << 10) 1744 #define HCRX_MSCEN (1ULL << 11) 1745 1746 #define HPFAR_NS (1ULL << 63) 1747 1748 #define SCR_NS (1ULL << 0) 1749 #define SCR_IRQ (1ULL << 1) 1750 #define SCR_FIQ (1ULL << 2) 1751 #define SCR_EA (1ULL << 3) 1752 #define SCR_FW (1ULL << 4) 1753 #define SCR_AW (1ULL << 5) 1754 #define SCR_NET (1ULL << 6) 1755 #define SCR_SMD (1ULL << 7) 1756 #define SCR_HCE (1ULL << 8) 1757 #define SCR_SIF (1ULL << 9) 1758 #define SCR_RW (1ULL << 10) 1759 #define SCR_ST (1ULL << 11) 1760 #define SCR_TWI (1ULL << 12) 1761 #define SCR_TWE (1ULL << 13) 1762 #define SCR_TLOR (1ULL << 14) 1763 #define SCR_TERR (1ULL << 15) 1764 #define SCR_APK (1ULL << 16) 1765 #define SCR_API (1ULL << 17) 1766 #define SCR_EEL2 (1ULL << 18) 1767 #define SCR_EASE (1ULL << 19) 1768 #define SCR_NMEA (1ULL << 20) 1769 #define SCR_FIEN (1ULL << 21) 1770 #define SCR_ENSCXT (1ULL << 25) 1771 #define SCR_ATA (1ULL << 26) 1772 #define SCR_FGTEN (1ULL << 27) 1773 #define SCR_ECVEN (1ULL << 28) 1774 #define SCR_TWEDEN (1ULL << 29) 1775 #define SCR_TWEDEL MAKE_64BIT_MASK(30, 4) 1776 #define SCR_TME (1ULL << 34) 1777 #define SCR_AMVOFFEN (1ULL << 35) 1778 #define SCR_ENAS0 (1ULL << 36) 1779 #define SCR_ADEN (1ULL << 37) 1780 #define SCR_HXEN (1ULL << 38) 1781 #define SCR_TRNDR (1ULL << 40) 1782 #define SCR_ENTP2 (1ULL << 41) 1783 #define SCR_GPF (1ULL << 48) 1784 #define SCR_NSE (1ULL << 62) 1785 1786 #define HSTR_TTEE (1 << 16) 1787 #define HSTR_TJDBX (1 << 17) 1788 1789 #define CNTHCTL_CNTVMASK (1 << 18) 1790 #define CNTHCTL_CNTPMASK (1 << 19) 1791 1792 /* Return the current FPSCR value. */ 1793 uint32_t vfp_get_fpscr(CPUARMState *env); 1794 void vfp_set_fpscr(CPUARMState *env, uint32_t val); 1795 1796 /* FPCR, Floating Point Control Register 1797 * FPSR, Floating Poiht Status Register 1798 * 1799 * For A64 the FPSCR is split into two logically distinct registers, 1800 * FPCR and FPSR. However since they still use non-overlapping bits 1801 * we store the underlying state in fpscr and just mask on read/write. 1802 */ 1803 #define FPSR_MASK 0xf800009f 1804 #define FPCR_MASK 0x07ff9f00 1805 1806 #define FPCR_IOE (1 << 8) /* Invalid Operation exception trap enable */ 1807 #define FPCR_DZE (1 << 9) /* Divide by Zero exception trap enable */ 1808 #define FPCR_OFE (1 << 10) /* Overflow exception trap enable */ 1809 #define FPCR_UFE (1 << 11) /* Underflow exception trap enable */ 1810 #define FPCR_IXE (1 << 12) /* Inexact exception trap enable */ 1811 #define FPCR_IDE (1 << 15) /* Input Denormal exception trap enable */ 1812 #define FPCR_FZ16 (1 << 19) /* ARMv8.2+, FP16 flush-to-zero */ 1813 #define FPCR_RMODE_MASK (3 << 22) /* Rounding mode */ 1814 #define FPCR_FZ (1 << 24) /* Flush-to-zero enable bit */ 1815 #define FPCR_DN (1 << 25) /* Default NaN enable bit */ 1816 #define FPCR_AHP (1 << 26) /* Alternative half-precision */ 1817 #define FPCR_QC (1 << 27) /* Cumulative saturation bit */ 1818 #define FPCR_V (1 << 28) /* FP overflow flag */ 1819 #define FPCR_C (1 << 29) /* FP carry flag */ 1820 #define FPCR_Z (1 << 30) /* FP zero flag */ 1821 #define FPCR_N (1 << 31) /* FP negative flag */ 1822 1823 #define FPCR_LTPSIZE_SHIFT 16 /* LTPSIZE, M-profile only */ 1824 #define FPCR_LTPSIZE_MASK (7 << FPCR_LTPSIZE_SHIFT) 1825 #define FPCR_LTPSIZE_LENGTH 3 1826 1827 #define FPCR_NZCV_MASK (FPCR_N | FPCR_Z | FPCR_C | FPCR_V) 1828 #define FPCR_NZCVQC_MASK (FPCR_NZCV_MASK | FPCR_QC) 1829 1830 static inline uint32_t vfp_get_fpsr(CPUARMState *env) 1831 { 1832 return vfp_get_fpscr(env) & FPSR_MASK; 1833 } 1834 1835 static inline void vfp_set_fpsr(CPUARMState *env, uint32_t val) 1836 { 1837 uint32_t new_fpscr = (vfp_get_fpscr(env) & ~FPSR_MASK) | (val & FPSR_MASK); 1838 vfp_set_fpscr(env, new_fpscr); 1839 } 1840 1841 static inline uint32_t vfp_get_fpcr(CPUARMState *env) 1842 { 1843 return vfp_get_fpscr(env) & FPCR_MASK; 1844 } 1845 1846 static inline void vfp_set_fpcr(CPUARMState *env, uint32_t val) 1847 { 1848 uint32_t new_fpscr = (vfp_get_fpscr(env) & ~FPCR_MASK) | (val & FPCR_MASK); 1849 vfp_set_fpscr(env, new_fpscr); 1850 } 1851 1852 enum arm_cpu_mode { 1853 ARM_CPU_MODE_USR = 0x10, 1854 ARM_CPU_MODE_FIQ = 0x11, 1855 ARM_CPU_MODE_IRQ = 0x12, 1856 ARM_CPU_MODE_SVC = 0x13, 1857 ARM_CPU_MODE_MON = 0x16, 1858 ARM_CPU_MODE_ABT = 0x17, 1859 ARM_CPU_MODE_HYP = 0x1a, 1860 ARM_CPU_MODE_UND = 0x1b, 1861 ARM_CPU_MODE_SYS = 0x1f 1862 }; 1863 1864 /* VFP system registers. */ 1865 #define ARM_VFP_FPSID 0 1866 #define ARM_VFP_FPSCR 1 1867 #define ARM_VFP_MVFR2 5 1868 #define ARM_VFP_MVFR1 6 1869 #define ARM_VFP_MVFR0 7 1870 #define ARM_VFP_FPEXC 8 1871 #define ARM_VFP_FPINST 9 1872 #define ARM_VFP_FPINST2 10 1873 /* These ones are M-profile only */ 1874 #define ARM_VFP_FPSCR_NZCVQC 2 1875 #define ARM_VFP_VPR 12 1876 #define ARM_VFP_P0 13 1877 #define ARM_VFP_FPCXT_NS 14 1878 #define ARM_VFP_FPCXT_S 15 1879 1880 /* QEMU-internal value meaning "FPSCR, but we care only about NZCV" */ 1881 #define QEMU_VFP_FPSCR_NZCV 0xffff 1882 1883 /* iwMMXt coprocessor control registers. */ 1884 #define ARM_IWMMXT_wCID 0 1885 #define ARM_IWMMXT_wCon 1 1886 #define ARM_IWMMXT_wCSSF 2 1887 #define ARM_IWMMXT_wCASF 3 1888 #define ARM_IWMMXT_wCGR0 8 1889 #define ARM_IWMMXT_wCGR1 9 1890 #define ARM_IWMMXT_wCGR2 10 1891 #define ARM_IWMMXT_wCGR3 11 1892 1893 /* V7M CCR bits */ 1894 FIELD(V7M_CCR, NONBASETHRDENA, 0, 1) 1895 FIELD(V7M_CCR, USERSETMPEND, 1, 1) 1896 FIELD(V7M_CCR, UNALIGN_TRP, 3, 1) 1897 FIELD(V7M_CCR, DIV_0_TRP, 4, 1) 1898 FIELD(V7M_CCR, BFHFNMIGN, 8, 1) 1899 FIELD(V7M_CCR, STKALIGN, 9, 1) 1900 FIELD(V7M_CCR, STKOFHFNMIGN, 10, 1) 1901 FIELD(V7M_CCR, DC, 16, 1) 1902 FIELD(V7M_CCR, IC, 17, 1) 1903 FIELD(V7M_CCR, BP, 18, 1) 1904 FIELD(V7M_CCR, LOB, 19, 1) 1905 FIELD(V7M_CCR, TRD, 20, 1) 1906 1907 /* V7M SCR bits */ 1908 FIELD(V7M_SCR, SLEEPONEXIT, 1, 1) 1909 FIELD(V7M_SCR, SLEEPDEEP, 2, 1) 1910 FIELD(V7M_SCR, SLEEPDEEPS, 3, 1) 1911 FIELD(V7M_SCR, SEVONPEND, 4, 1) 1912 1913 /* V7M AIRCR bits */ 1914 FIELD(V7M_AIRCR, VECTRESET, 0, 1) 1915 FIELD(V7M_AIRCR, VECTCLRACTIVE, 1, 1) 1916 FIELD(V7M_AIRCR, SYSRESETREQ, 2, 1) 1917 FIELD(V7M_AIRCR, SYSRESETREQS, 3, 1) 1918 FIELD(V7M_AIRCR, PRIGROUP, 8, 3) 1919 FIELD(V7M_AIRCR, BFHFNMINS, 13, 1) 1920 FIELD(V7M_AIRCR, PRIS, 14, 1) 1921 FIELD(V7M_AIRCR, ENDIANNESS, 15, 1) 1922 FIELD(V7M_AIRCR, VECTKEY, 16, 16) 1923 1924 /* V7M CFSR bits for MMFSR */ 1925 FIELD(V7M_CFSR, IACCVIOL, 0, 1) 1926 FIELD(V7M_CFSR, DACCVIOL, 1, 1) 1927 FIELD(V7M_CFSR, MUNSTKERR, 3, 1) 1928 FIELD(V7M_CFSR, MSTKERR, 4, 1) 1929 FIELD(V7M_CFSR, MLSPERR, 5, 1) 1930 FIELD(V7M_CFSR, MMARVALID, 7, 1) 1931 1932 /* V7M CFSR bits for BFSR */ 1933 FIELD(V7M_CFSR, IBUSERR, 8 + 0, 1) 1934 FIELD(V7M_CFSR, PRECISERR, 8 + 1, 1) 1935 FIELD(V7M_CFSR, IMPRECISERR, 8 + 2, 1) 1936 FIELD(V7M_CFSR, UNSTKERR, 8 + 3, 1) 1937 FIELD(V7M_CFSR, STKERR, 8 + 4, 1) 1938 FIELD(V7M_CFSR, LSPERR, 8 + 5, 1) 1939 FIELD(V7M_CFSR, BFARVALID, 8 + 7, 1) 1940 1941 /* V7M CFSR bits for UFSR */ 1942 FIELD(V7M_CFSR, UNDEFINSTR, 16 + 0, 1) 1943 FIELD(V7M_CFSR, INVSTATE, 16 + 1, 1) 1944 FIELD(V7M_CFSR, INVPC, 16 + 2, 1) 1945 FIELD(V7M_CFSR, NOCP, 16 + 3, 1) 1946 FIELD(V7M_CFSR, STKOF, 16 + 4, 1) 1947 FIELD(V7M_CFSR, UNALIGNED, 16 + 8, 1) 1948 FIELD(V7M_CFSR, DIVBYZERO, 16 + 9, 1) 1949 1950 /* V7M CFSR bit masks covering all of the subregister bits */ 1951 FIELD(V7M_CFSR, MMFSR, 0, 8) 1952 FIELD(V7M_CFSR, BFSR, 8, 8) 1953 FIELD(V7M_CFSR, UFSR, 16, 16) 1954 1955 /* V7M HFSR bits */ 1956 FIELD(V7M_HFSR, VECTTBL, 1, 1) 1957 FIELD(V7M_HFSR, FORCED, 30, 1) 1958 FIELD(V7M_HFSR, DEBUGEVT, 31, 1) 1959 1960 /* V7M DFSR bits */ 1961 FIELD(V7M_DFSR, HALTED, 0, 1) 1962 FIELD(V7M_DFSR, BKPT, 1, 1) 1963 FIELD(V7M_DFSR, DWTTRAP, 2, 1) 1964 FIELD(V7M_DFSR, VCATCH, 3, 1) 1965 FIELD(V7M_DFSR, EXTERNAL, 4, 1) 1966 1967 /* V7M SFSR bits */ 1968 FIELD(V7M_SFSR, INVEP, 0, 1) 1969 FIELD(V7M_SFSR, INVIS, 1, 1) 1970 FIELD(V7M_SFSR, INVER, 2, 1) 1971 FIELD(V7M_SFSR, AUVIOL, 3, 1) 1972 FIELD(V7M_SFSR, INVTRAN, 4, 1) 1973 FIELD(V7M_SFSR, LSPERR, 5, 1) 1974 FIELD(V7M_SFSR, SFARVALID, 6, 1) 1975 FIELD(V7M_SFSR, LSERR, 7, 1) 1976 1977 /* v7M MPU_CTRL bits */ 1978 FIELD(V7M_MPU_CTRL, ENABLE, 0, 1) 1979 FIELD(V7M_MPU_CTRL, HFNMIENA, 1, 1) 1980 FIELD(V7M_MPU_CTRL, PRIVDEFENA, 2, 1) 1981 1982 /* v7M CLIDR bits */ 1983 FIELD(V7M_CLIDR, CTYPE_ALL, 0, 21) 1984 FIELD(V7M_CLIDR, LOUIS, 21, 3) 1985 FIELD(V7M_CLIDR, LOC, 24, 3) 1986 FIELD(V7M_CLIDR, LOUU, 27, 3) 1987 FIELD(V7M_CLIDR, ICB, 30, 2) 1988 1989 FIELD(V7M_CSSELR, IND, 0, 1) 1990 FIELD(V7M_CSSELR, LEVEL, 1, 3) 1991 /* We use the combination of InD and Level to index into cpu->ccsidr[]; 1992 * define a mask for this and check that it doesn't permit running off 1993 * the end of the array. 1994 */ 1995 FIELD(V7M_CSSELR, INDEX, 0, 4) 1996 1997 /* v7M FPCCR bits */ 1998 FIELD(V7M_FPCCR, LSPACT, 0, 1) 1999 FIELD(V7M_FPCCR, USER, 1, 1) 2000 FIELD(V7M_FPCCR, S, 2, 1) 2001 FIELD(V7M_FPCCR, THREAD, 3, 1) 2002 FIELD(V7M_FPCCR, HFRDY, 4, 1) 2003 FIELD(V7M_FPCCR, MMRDY, 5, 1) 2004 FIELD(V7M_FPCCR, BFRDY, 6, 1) 2005 FIELD(V7M_FPCCR, SFRDY, 7, 1) 2006 FIELD(V7M_FPCCR, MONRDY, 8, 1) 2007 FIELD(V7M_FPCCR, SPLIMVIOL, 9, 1) 2008 FIELD(V7M_FPCCR, UFRDY, 10, 1) 2009 FIELD(V7M_FPCCR, RES0, 11, 15) 2010 FIELD(V7M_FPCCR, TS, 26, 1) 2011 FIELD(V7M_FPCCR, CLRONRETS, 27, 1) 2012 FIELD(V7M_FPCCR, CLRONRET, 28, 1) 2013 FIELD(V7M_FPCCR, LSPENS, 29, 1) 2014 FIELD(V7M_FPCCR, LSPEN, 30, 1) 2015 FIELD(V7M_FPCCR, ASPEN, 31, 1) 2016 /* These bits are banked. Others are non-banked and live in the M_REG_S bank */ 2017 #define R_V7M_FPCCR_BANKED_MASK \ 2018 (R_V7M_FPCCR_LSPACT_MASK | \ 2019 R_V7M_FPCCR_USER_MASK | \ 2020 R_V7M_FPCCR_THREAD_MASK | \ 2021 R_V7M_FPCCR_MMRDY_MASK | \ 2022 R_V7M_FPCCR_SPLIMVIOL_MASK | \ 2023 R_V7M_FPCCR_UFRDY_MASK | \ 2024 R_V7M_FPCCR_ASPEN_MASK) 2025 2026 /* v7M VPR bits */ 2027 FIELD(V7M_VPR, P0, 0, 16) 2028 FIELD(V7M_VPR, MASK01, 16, 4) 2029 FIELD(V7M_VPR, MASK23, 20, 4) 2030 2031 /* 2032 * System register ID fields. 2033 */ 2034 FIELD(CLIDR_EL1, CTYPE1, 0, 3) 2035 FIELD(CLIDR_EL1, CTYPE2, 3, 3) 2036 FIELD(CLIDR_EL1, CTYPE3, 6, 3) 2037 FIELD(CLIDR_EL1, CTYPE4, 9, 3) 2038 FIELD(CLIDR_EL1, CTYPE5, 12, 3) 2039 FIELD(CLIDR_EL1, CTYPE6, 15, 3) 2040 FIELD(CLIDR_EL1, CTYPE7, 18, 3) 2041 FIELD(CLIDR_EL1, LOUIS, 21, 3) 2042 FIELD(CLIDR_EL1, LOC, 24, 3) 2043 FIELD(CLIDR_EL1, LOUU, 27, 3) 2044 FIELD(CLIDR_EL1, ICB, 30, 3) 2045 2046 /* When FEAT_CCIDX is implemented */ 2047 FIELD(CCSIDR_EL1, CCIDX_LINESIZE, 0, 3) 2048 FIELD(CCSIDR_EL1, CCIDX_ASSOCIATIVITY, 3, 21) 2049 FIELD(CCSIDR_EL1, CCIDX_NUMSETS, 32, 24) 2050 2051 /* When FEAT_CCIDX is not implemented */ 2052 FIELD(CCSIDR_EL1, LINESIZE, 0, 3) 2053 FIELD(CCSIDR_EL1, ASSOCIATIVITY, 3, 10) 2054 FIELD(CCSIDR_EL1, NUMSETS, 13, 15) 2055 2056 FIELD(CTR_EL0, IMINLINE, 0, 4) 2057 FIELD(CTR_EL0, L1IP, 14, 2) 2058 FIELD(CTR_EL0, DMINLINE, 16, 4) 2059 FIELD(CTR_EL0, ERG, 20, 4) 2060 FIELD(CTR_EL0, CWG, 24, 4) 2061 FIELD(CTR_EL0, IDC, 28, 1) 2062 FIELD(CTR_EL0, DIC, 29, 1) 2063 FIELD(CTR_EL0, TMINLINE, 32, 6) 2064 2065 FIELD(MIDR_EL1, REVISION, 0, 4) 2066 FIELD(MIDR_EL1, PARTNUM, 4, 12) 2067 FIELD(MIDR_EL1, ARCHITECTURE, 16, 4) 2068 FIELD(MIDR_EL1, VARIANT, 20, 4) 2069 FIELD(MIDR_EL1, IMPLEMENTER, 24, 8) 2070 2071 FIELD(ID_ISAR0, SWAP, 0, 4) 2072 FIELD(ID_ISAR0, BITCOUNT, 4, 4) 2073 FIELD(ID_ISAR0, BITFIELD, 8, 4) 2074 FIELD(ID_ISAR0, CMPBRANCH, 12, 4) 2075 FIELD(ID_ISAR0, COPROC, 16, 4) 2076 FIELD(ID_ISAR0, DEBUG, 20, 4) 2077 FIELD(ID_ISAR0, DIVIDE, 24, 4) 2078 2079 FIELD(ID_ISAR1, ENDIAN, 0, 4) 2080 FIELD(ID_ISAR1, EXCEPT, 4, 4) 2081 FIELD(ID_ISAR1, EXCEPT_AR, 8, 4) 2082 FIELD(ID_ISAR1, EXTEND, 12, 4) 2083 FIELD(ID_ISAR1, IFTHEN, 16, 4) 2084 FIELD(ID_ISAR1, IMMEDIATE, 20, 4) 2085 FIELD(ID_ISAR1, INTERWORK, 24, 4) 2086 FIELD(ID_ISAR1, JAZELLE, 28, 4) 2087 2088 FIELD(ID_ISAR2, LOADSTORE, 0, 4) 2089 FIELD(ID_ISAR2, MEMHINT, 4, 4) 2090 FIELD(ID_ISAR2, MULTIACCESSINT, 8, 4) 2091 FIELD(ID_ISAR2, MULT, 12, 4) 2092 FIELD(ID_ISAR2, MULTS, 16, 4) 2093 FIELD(ID_ISAR2, MULTU, 20, 4) 2094 FIELD(ID_ISAR2, PSR_AR, 24, 4) 2095 FIELD(ID_ISAR2, REVERSAL, 28, 4) 2096 2097 FIELD(ID_ISAR3, SATURATE, 0, 4) 2098 FIELD(ID_ISAR3, SIMD, 4, 4) 2099 FIELD(ID_ISAR3, SVC, 8, 4) 2100 FIELD(ID_ISAR3, SYNCHPRIM, 12, 4) 2101 FIELD(ID_ISAR3, TABBRANCH, 16, 4) 2102 FIELD(ID_ISAR3, T32COPY, 20, 4) 2103 FIELD(ID_ISAR3, TRUENOP, 24, 4) 2104 FIELD(ID_ISAR3, T32EE, 28, 4) 2105 2106 FIELD(ID_ISAR4, UNPRIV, 0, 4) 2107 FIELD(ID_ISAR4, WITHSHIFTS, 4, 4) 2108 FIELD(ID_ISAR4, WRITEBACK, 8, 4) 2109 FIELD(ID_ISAR4, SMC, 12, 4) 2110 FIELD(ID_ISAR4, BARRIER, 16, 4) 2111 FIELD(ID_ISAR4, SYNCHPRIM_FRAC, 20, 4) 2112 FIELD(ID_ISAR4, PSR_M, 24, 4) 2113 FIELD(ID_ISAR4, SWP_FRAC, 28, 4) 2114 2115 FIELD(ID_ISAR5, SEVL, 0, 4) 2116 FIELD(ID_ISAR5, AES, 4, 4) 2117 FIELD(ID_ISAR5, SHA1, 8, 4) 2118 FIELD(ID_ISAR5, SHA2, 12, 4) 2119 FIELD(ID_ISAR5, CRC32, 16, 4) 2120 FIELD(ID_ISAR5, RDM, 24, 4) 2121 FIELD(ID_ISAR5, VCMA, 28, 4) 2122 2123 FIELD(ID_ISAR6, JSCVT, 0, 4) 2124 FIELD(ID_ISAR6, DP, 4, 4) 2125 FIELD(ID_ISAR6, FHM, 8, 4) 2126 FIELD(ID_ISAR6, SB, 12, 4) 2127 FIELD(ID_ISAR6, SPECRES, 16, 4) 2128 FIELD(ID_ISAR6, BF16, 20, 4) 2129 FIELD(ID_ISAR6, I8MM, 24, 4) 2130 2131 FIELD(ID_MMFR0, VMSA, 0, 4) 2132 FIELD(ID_MMFR0, PMSA, 4, 4) 2133 FIELD(ID_MMFR0, OUTERSHR, 8, 4) 2134 FIELD(ID_MMFR0, SHARELVL, 12, 4) 2135 FIELD(ID_MMFR0, TCM, 16, 4) 2136 FIELD(ID_MMFR0, AUXREG, 20, 4) 2137 FIELD(ID_MMFR0, FCSE, 24, 4) 2138 FIELD(ID_MMFR0, INNERSHR, 28, 4) 2139 2140 FIELD(ID_MMFR1, L1HVDVA, 0, 4) 2141 FIELD(ID_MMFR1, L1UNIVA, 4, 4) 2142 FIELD(ID_MMFR1, L1HVDSW, 8, 4) 2143 FIELD(ID_MMFR1, L1UNISW, 12, 4) 2144 FIELD(ID_MMFR1, L1HVD, 16, 4) 2145 FIELD(ID_MMFR1, L1UNI, 20, 4) 2146 FIELD(ID_MMFR1, L1TSTCLN, 24, 4) 2147 FIELD(ID_MMFR1, BPRED, 28, 4) 2148 2149 FIELD(ID_MMFR2, L1HVDFG, 0, 4) 2150 FIELD(ID_MMFR2, L1HVDBG, 4, 4) 2151 FIELD(ID_MMFR2, L1HVDRNG, 8, 4) 2152 FIELD(ID_MMFR2, HVDTLB, 12, 4) 2153 FIELD(ID_MMFR2, UNITLB, 16, 4) 2154 FIELD(ID_MMFR2, MEMBARR, 20, 4) 2155 FIELD(ID_MMFR2, WFISTALL, 24, 4) 2156 FIELD(ID_MMFR2, HWACCFLG, 28, 4) 2157 2158 FIELD(ID_MMFR3, CMAINTVA, 0, 4) 2159 FIELD(ID_MMFR3, CMAINTSW, 4, 4) 2160 FIELD(ID_MMFR3, BPMAINT, 8, 4) 2161 FIELD(ID_MMFR3, MAINTBCST, 12, 4) 2162 FIELD(ID_MMFR3, PAN, 16, 4) 2163 FIELD(ID_MMFR3, COHWALK, 20, 4) 2164 FIELD(ID_MMFR3, CMEMSZ, 24, 4) 2165 FIELD(ID_MMFR3, SUPERSEC, 28, 4) 2166 2167 FIELD(ID_MMFR4, SPECSEI, 0, 4) 2168 FIELD(ID_MMFR4, AC2, 4, 4) 2169 FIELD(ID_MMFR4, XNX, 8, 4) 2170 FIELD(ID_MMFR4, CNP, 12, 4) 2171 FIELD(ID_MMFR4, HPDS, 16, 4) 2172 FIELD(ID_MMFR4, LSM, 20, 4) 2173 FIELD(ID_MMFR4, CCIDX, 24, 4) 2174 FIELD(ID_MMFR4, EVT, 28, 4) 2175 2176 FIELD(ID_MMFR5, ETS, 0, 4) 2177 FIELD(ID_MMFR5, NTLBPA, 4, 4) 2178 2179 FIELD(ID_PFR0, STATE0, 0, 4) 2180 FIELD(ID_PFR0, STATE1, 4, 4) 2181 FIELD(ID_PFR0, STATE2, 8, 4) 2182 FIELD(ID_PFR0, STATE3, 12, 4) 2183 FIELD(ID_PFR0, CSV2, 16, 4) 2184 FIELD(ID_PFR0, AMU, 20, 4) 2185 FIELD(ID_PFR0, DIT, 24, 4) 2186 FIELD(ID_PFR0, RAS, 28, 4) 2187 2188 FIELD(ID_PFR1, PROGMOD, 0, 4) 2189 FIELD(ID_PFR1, SECURITY, 4, 4) 2190 FIELD(ID_PFR1, MPROGMOD, 8, 4) 2191 FIELD(ID_PFR1, VIRTUALIZATION, 12, 4) 2192 FIELD(ID_PFR1, GENTIMER, 16, 4) 2193 FIELD(ID_PFR1, SEC_FRAC, 20, 4) 2194 FIELD(ID_PFR1, VIRT_FRAC, 24, 4) 2195 FIELD(ID_PFR1, GIC, 28, 4) 2196 2197 FIELD(ID_PFR2, CSV3, 0, 4) 2198 FIELD(ID_PFR2, SSBS, 4, 4) 2199 FIELD(ID_PFR2, RAS_FRAC, 8, 4) 2200 2201 FIELD(ID_AA64ISAR0, AES, 4, 4) 2202 FIELD(ID_AA64ISAR0, SHA1, 8, 4) 2203 FIELD(ID_AA64ISAR0, SHA2, 12, 4) 2204 FIELD(ID_AA64ISAR0, CRC32, 16, 4) 2205 FIELD(ID_AA64ISAR0, ATOMIC, 20, 4) 2206 FIELD(ID_AA64ISAR0, TME, 24, 4) 2207 FIELD(ID_AA64ISAR0, RDM, 28, 4) 2208 FIELD(ID_AA64ISAR0, SHA3, 32, 4) 2209 FIELD(ID_AA64ISAR0, SM3, 36, 4) 2210 FIELD(ID_AA64ISAR0, SM4, 40, 4) 2211 FIELD(ID_AA64ISAR0, DP, 44, 4) 2212 FIELD(ID_AA64ISAR0, FHM, 48, 4) 2213 FIELD(ID_AA64ISAR0, TS, 52, 4) 2214 FIELD(ID_AA64ISAR0, TLB, 56, 4) 2215 FIELD(ID_AA64ISAR0, RNDR, 60, 4) 2216 2217 FIELD(ID_AA64ISAR1, DPB, 0, 4) 2218 FIELD(ID_AA64ISAR1, APA, 4, 4) 2219 FIELD(ID_AA64ISAR1, API, 8, 4) 2220 FIELD(ID_AA64ISAR1, JSCVT, 12, 4) 2221 FIELD(ID_AA64ISAR1, FCMA, 16, 4) 2222 FIELD(ID_AA64ISAR1, LRCPC, 20, 4) 2223 FIELD(ID_AA64ISAR1, GPA, 24, 4) 2224 FIELD(ID_AA64ISAR1, GPI, 28, 4) 2225 FIELD(ID_AA64ISAR1, FRINTTS, 32, 4) 2226 FIELD(ID_AA64ISAR1, SB, 36, 4) 2227 FIELD(ID_AA64ISAR1, SPECRES, 40, 4) 2228 FIELD(ID_AA64ISAR1, BF16, 44, 4) 2229 FIELD(ID_AA64ISAR1, DGH, 48, 4) 2230 FIELD(ID_AA64ISAR1, I8MM, 52, 4) 2231 FIELD(ID_AA64ISAR1, XS, 56, 4) 2232 FIELD(ID_AA64ISAR1, LS64, 60, 4) 2233 2234 FIELD(ID_AA64ISAR2, WFXT, 0, 4) 2235 FIELD(ID_AA64ISAR2, RPRES, 4, 4) 2236 FIELD(ID_AA64ISAR2, GPA3, 8, 4) 2237 FIELD(ID_AA64ISAR2, APA3, 12, 4) 2238 FIELD(ID_AA64ISAR2, MOPS, 16, 4) 2239 FIELD(ID_AA64ISAR2, BC, 20, 4) 2240 FIELD(ID_AA64ISAR2, PAC_FRAC, 24, 4) 2241 FIELD(ID_AA64ISAR2, CLRBHB, 28, 4) 2242 FIELD(ID_AA64ISAR2, SYSREG_128, 32, 4) 2243 FIELD(ID_AA64ISAR2, SYSINSTR_128, 36, 4) 2244 FIELD(ID_AA64ISAR2, PRFMSLC, 40, 4) 2245 FIELD(ID_AA64ISAR2, RPRFM, 48, 4) 2246 FIELD(ID_AA64ISAR2, CSSC, 52, 4) 2247 FIELD(ID_AA64ISAR2, ATS1A, 60, 4) 2248 2249 FIELD(ID_AA64PFR0, EL0, 0, 4) 2250 FIELD(ID_AA64PFR0, EL1, 4, 4) 2251 FIELD(ID_AA64PFR0, EL2, 8, 4) 2252 FIELD(ID_AA64PFR0, EL3, 12, 4) 2253 FIELD(ID_AA64PFR0, FP, 16, 4) 2254 FIELD(ID_AA64PFR0, ADVSIMD, 20, 4) 2255 FIELD(ID_AA64PFR0, GIC, 24, 4) 2256 FIELD(ID_AA64PFR0, RAS, 28, 4) 2257 FIELD(ID_AA64PFR0, SVE, 32, 4) 2258 FIELD(ID_AA64PFR0, SEL2, 36, 4) 2259 FIELD(ID_AA64PFR0, MPAM, 40, 4) 2260 FIELD(ID_AA64PFR0, AMU, 44, 4) 2261 FIELD(ID_AA64PFR0, DIT, 48, 4) 2262 FIELD(ID_AA64PFR0, RME, 52, 4) 2263 FIELD(ID_AA64PFR0, CSV2, 56, 4) 2264 FIELD(ID_AA64PFR0, CSV3, 60, 4) 2265 2266 FIELD(ID_AA64PFR1, BT, 0, 4) 2267 FIELD(ID_AA64PFR1, SSBS, 4, 4) 2268 FIELD(ID_AA64PFR1, MTE, 8, 4) 2269 FIELD(ID_AA64PFR1, RAS_FRAC, 12, 4) 2270 FIELD(ID_AA64PFR1, MPAM_FRAC, 16, 4) 2271 FIELD(ID_AA64PFR1, SME, 24, 4) 2272 FIELD(ID_AA64PFR1, RNDR_TRAP, 28, 4) 2273 FIELD(ID_AA64PFR1, CSV2_FRAC, 32, 4) 2274 FIELD(ID_AA64PFR1, NMI, 36, 4) 2275 FIELD(ID_AA64PFR1, MTE_FRAC, 40, 4) 2276 FIELD(ID_AA64PFR1, GCS, 44, 4) 2277 FIELD(ID_AA64PFR1, THE, 48, 4) 2278 FIELD(ID_AA64PFR1, MTEX, 52, 4) 2279 FIELD(ID_AA64PFR1, DF2, 56, 4) 2280 FIELD(ID_AA64PFR1, PFAR, 60, 4) 2281 2282 FIELD(ID_AA64MMFR0, PARANGE, 0, 4) 2283 FIELD(ID_AA64MMFR0, ASIDBITS, 4, 4) 2284 FIELD(ID_AA64MMFR0, BIGEND, 8, 4) 2285 FIELD(ID_AA64MMFR0, SNSMEM, 12, 4) 2286 FIELD(ID_AA64MMFR0, BIGENDEL0, 16, 4) 2287 FIELD(ID_AA64MMFR0, TGRAN16, 20, 4) 2288 FIELD(ID_AA64MMFR0, TGRAN64, 24, 4) 2289 FIELD(ID_AA64MMFR0, TGRAN4, 28, 4) 2290 FIELD(ID_AA64MMFR0, TGRAN16_2, 32, 4) 2291 FIELD(ID_AA64MMFR0, TGRAN64_2, 36, 4) 2292 FIELD(ID_AA64MMFR0, TGRAN4_2, 40, 4) 2293 FIELD(ID_AA64MMFR0, EXS, 44, 4) 2294 FIELD(ID_AA64MMFR0, FGT, 56, 4) 2295 FIELD(ID_AA64MMFR0, ECV, 60, 4) 2296 2297 FIELD(ID_AA64MMFR1, HAFDBS, 0, 4) 2298 FIELD(ID_AA64MMFR1, VMIDBITS, 4, 4) 2299 FIELD(ID_AA64MMFR1, VH, 8, 4) 2300 FIELD(ID_AA64MMFR1, HPDS, 12, 4) 2301 FIELD(ID_AA64MMFR1, LO, 16, 4) 2302 FIELD(ID_AA64MMFR1, PAN, 20, 4) 2303 FIELD(ID_AA64MMFR1, SPECSEI, 24, 4) 2304 FIELD(ID_AA64MMFR1, XNX, 28, 4) 2305 FIELD(ID_AA64MMFR1, TWED, 32, 4) 2306 FIELD(ID_AA64MMFR1, ETS, 36, 4) 2307 FIELD(ID_AA64MMFR1, HCX, 40, 4) 2308 FIELD(ID_AA64MMFR1, AFP, 44, 4) 2309 FIELD(ID_AA64MMFR1, NTLBPA, 48, 4) 2310 FIELD(ID_AA64MMFR1, TIDCP1, 52, 4) 2311 FIELD(ID_AA64MMFR1, CMOW, 56, 4) 2312 FIELD(ID_AA64MMFR1, ECBHB, 60, 4) 2313 2314 FIELD(ID_AA64MMFR2, CNP, 0, 4) 2315 FIELD(ID_AA64MMFR2, UAO, 4, 4) 2316 FIELD(ID_AA64MMFR2, LSM, 8, 4) 2317 FIELD(ID_AA64MMFR2, IESB, 12, 4) 2318 FIELD(ID_AA64MMFR2, VARANGE, 16, 4) 2319 FIELD(ID_AA64MMFR2, CCIDX, 20, 4) 2320 FIELD(ID_AA64MMFR2, NV, 24, 4) 2321 FIELD(ID_AA64MMFR2, ST, 28, 4) 2322 FIELD(ID_AA64MMFR2, AT, 32, 4) 2323 FIELD(ID_AA64MMFR2, IDS, 36, 4) 2324 FIELD(ID_AA64MMFR2, FWB, 40, 4) 2325 FIELD(ID_AA64MMFR2, TTL, 48, 4) 2326 FIELD(ID_AA64MMFR2, BBM, 52, 4) 2327 FIELD(ID_AA64MMFR2, EVT, 56, 4) 2328 FIELD(ID_AA64MMFR2, E0PD, 60, 4) 2329 2330 FIELD(ID_AA64DFR0, DEBUGVER, 0, 4) 2331 FIELD(ID_AA64DFR0, TRACEVER, 4, 4) 2332 FIELD(ID_AA64DFR0, PMUVER, 8, 4) 2333 FIELD(ID_AA64DFR0, BRPS, 12, 4) 2334 FIELD(ID_AA64DFR0, PMSS, 16, 4) 2335 FIELD(ID_AA64DFR0, WRPS, 20, 4) 2336 FIELD(ID_AA64DFR0, SEBEP, 24, 4) 2337 FIELD(ID_AA64DFR0, CTX_CMPS, 28, 4) 2338 FIELD(ID_AA64DFR0, PMSVER, 32, 4) 2339 FIELD(ID_AA64DFR0, DOUBLELOCK, 36, 4) 2340 FIELD(ID_AA64DFR0, TRACEFILT, 40, 4) 2341 FIELD(ID_AA64DFR0, TRACEBUFFER, 44, 4) 2342 FIELD(ID_AA64DFR0, MTPMU, 48, 4) 2343 FIELD(ID_AA64DFR0, BRBE, 52, 4) 2344 FIELD(ID_AA64DFR0, EXTTRCBUFF, 56, 4) 2345 FIELD(ID_AA64DFR0, HPMN0, 60, 4) 2346 2347 FIELD(ID_AA64ZFR0, SVEVER, 0, 4) 2348 FIELD(ID_AA64ZFR0, AES, 4, 4) 2349 FIELD(ID_AA64ZFR0, BITPERM, 16, 4) 2350 FIELD(ID_AA64ZFR0, BFLOAT16, 20, 4) 2351 FIELD(ID_AA64ZFR0, B16B16, 24, 4) 2352 FIELD(ID_AA64ZFR0, SHA3, 32, 4) 2353 FIELD(ID_AA64ZFR0, SM4, 40, 4) 2354 FIELD(ID_AA64ZFR0, I8MM, 44, 4) 2355 FIELD(ID_AA64ZFR0, F32MM, 52, 4) 2356 FIELD(ID_AA64ZFR0, F64MM, 56, 4) 2357 2358 FIELD(ID_AA64SMFR0, F32F32, 32, 1) 2359 FIELD(ID_AA64SMFR0, BI32I32, 33, 1) 2360 FIELD(ID_AA64SMFR0, B16F32, 34, 1) 2361 FIELD(ID_AA64SMFR0, F16F32, 35, 1) 2362 FIELD(ID_AA64SMFR0, I8I32, 36, 4) 2363 FIELD(ID_AA64SMFR0, F16F16, 42, 1) 2364 FIELD(ID_AA64SMFR0, B16B16, 43, 1) 2365 FIELD(ID_AA64SMFR0, I16I32, 44, 4) 2366 FIELD(ID_AA64SMFR0, F64F64, 48, 1) 2367 FIELD(ID_AA64SMFR0, I16I64, 52, 4) 2368 FIELD(ID_AA64SMFR0, SMEVER, 56, 4) 2369 FIELD(ID_AA64SMFR0, FA64, 63, 1) 2370 2371 FIELD(ID_DFR0, COPDBG, 0, 4) 2372 FIELD(ID_DFR0, COPSDBG, 4, 4) 2373 FIELD(ID_DFR0, MMAPDBG, 8, 4) 2374 FIELD(ID_DFR0, COPTRC, 12, 4) 2375 FIELD(ID_DFR0, MMAPTRC, 16, 4) 2376 FIELD(ID_DFR0, MPROFDBG, 20, 4) 2377 FIELD(ID_DFR0, PERFMON, 24, 4) 2378 FIELD(ID_DFR0, TRACEFILT, 28, 4) 2379 2380 FIELD(ID_DFR1, MTPMU, 0, 4) 2381 FIELD(ID_DFR1, HPMN0, 4, 4) 2382 2383 FIELD(DBGDIDR, SE_IMP, 12, 1) 2384 FIELD(DBGDIDR, NSUHD_IMP, 14, 1) 2385 FIELD(DBGDIDR, VERSION, 16, 4) 2386 FIELD(DBGDIDR, CTX_CMPS, 20, 4) 2387 FIELD(DBGDIDR, BRPS, 24, 4) 2388 FIELD(DBGDIDR, WRPS, 28, 4) 2389 2390 FIELD(DBGDEVID, PCSAMPLE, 0, 4) 2391 FIELD(DBGDEVID, WPADDRMASK, 4, 4) 2392 FIELD(DBGDEVID, BPADDRMASK, 8, 4) 2393 FIELD(DBGDEVID, VECTORCATCH, 12, 4) 2394 FIELD(DBGDEVID, VIRTEXTNS, 16, 4) 2395 FIELD(DBGDEVID, DOUBLELOCK, 20, 4) 2396 FIELD(DBGDEVID, AUXREGS, 24, 4) 2397 FIELD(DBGDEVID, CIDMASK, 28, 4) 2398 2399 FIELD(MVFR0, SIMDREG, 0, 4) 2400 FIELD(MVFR0, FPSP, 4, 4) 2401 FIELD(MVFR0, FPDP, 8, 4) 2402 FIELD(MVFR0, FPTRAP, 12, 4) 2403 FIELD(MVFR0, FPDIVIDE, 16, 4) 2404 FIELD(MVFR0, FPSQRT, 20, 4) 2405 FIELD(MVFR0, FPSHVEC, 24, 4) 2406 FIELD(MVFR0, FPROUND, 28, 4) 2407 2408 FIELD(MVFR1, FPFTZ, 0, 4) 2409 FIELD(MVFR1, FPDNAN, 4, 4) 2410 FIELD(MVFR1, SIMDLS, 8, 4) /* A-profile only */ 2411 FIELD(MVFR1, SIMDINT, 12, 4) /* A-profile only */ 2412 FIELD(MVFR1, SIMDSP, 16, 4) /* A-profile only */ 2413 FIELD(MVFR1, SIMDHP, 20, 4) /* A-profile only */ 2414 FIELD(MVFR1, MVE, 8, 4) /* M-profile only */ 2415 FIELD(MVFR1, FP16, 20, 4) /* M-profile only */ 2416 FIELD(MVFR1, FPHP, 24, 4) 2417 FIELD(MVFR1, SIMDFMAC, 28, 4) 2418 2419 FIELD(MVFR2, SIMDMISC, 0, 4) 2420 FIELD(MVFR2, FPMISC, 4, 4) 2421 2422 FIELD(GPCCR, PPS, 0, 3) 2423 FIELD(GPCCR, IRGN, 8, 2) 2424 FIELD(GPCCR, ORGN, 10, 2) 2425 FIELD(GPCCR, SH, 12, 2) 2426 FIELD(GPCCR, PGS, 14, 2) 2427 FIELD(GPCCR, GPC, 16, 1) 2428 FIELD(GPCCR, GPCP, 17, 1) 2429 FIELD(GPCCR, L0GPTSZ, 20, 4) 2430 2431 FIELD(MFAR, FPA, 12, 40) 2432 FIELD(MFAR, NSE, 62, 1) 2433 FIELD(MFAR, NS, 63, 1) 2434 2435 QEMU_BUILD_BUG_ON(ARRAY_SIZE(((ARMCPU *)0)->ccsidr) <= R_V7M_CSSELR_INDEX_MASK); 2436 2437 /* If adding a feature bit which corresponds to a Linux ELF 2438 * HWCAP bit, remember to update the feature-bit-to-hwcap 2439 * mapping in linux-user/elfload.c:get_elf_hwcap(). 2440 */ 2441 enum arm_features { 2442 ARM_FEATURE_AUXCR, /* ARM1026 Auxiliary control register. */ 2443 ARM_FEATURE_XSCALE, /* Intel XScale extensions. */ 2444 ARM_FEATURE_IWMMXT, /* Intel iwMMXt extension. */ 2445 ARM_FEATURE_V6, 2446 ARM_FEATURE_V6K, 2447 ARM_FEATURE_V7, 2448 ARM_FEATURE_THUMB2, 2449 ARM_FEATURE_PMSA, /* no MMU; may have Memory Protection Unit */ 2450 ARM_FEATURE_NEON, 2451 ARM_FEATURE_M, /* Microcontroller profile. */ 2452 ARM_FEATURE_OMAPCP, /* OMAP specific CP15 ops handling. */ 2453 ARM_FEATURE_THUMB2EE, 2454 ARM_FEATURE_V7MP, /* v7 Multiprocessing Extensions */ 2455 ARM_FEATURE_V7VE, /* v7 Virtualization Extensions (non-EL2 parts) */ 2456 ARM_FEATURE_V4T, 2457 ARM_FEATURE_V5, 2458 ARM_FEATURE_STRONGARM, 2459 ARM_FEATURE_VAPA, /* cp15 VA to PA lookups */ 2460 ARM_FEATURE_GENERIC_TIMER, 2461 ARM_FEATURE_MVFR, /* Media and VFP Feature Registers 0 and 1 */ 2462 ARM_FEATURE_DUMMY_C15_REGS, /* RAZ/WI all of cp15 crn=15 */ 2463 ARM_FEATURE_CACHE_TEST_CLEAN, /* 926/1026 style test-and-clean ops */ 2464 ARM_FEATURE_CACHE_DIRTY_REG, /* 1136/1176 cache dirty status register */ 2465 ARM_FEATURE_CACHE_BLOCK_OPS, /* v6 optional cache block operations */ 2466 ARM_FEATURE_MPIDR, /* has cp15 MPIDR */ 2467 ARM_FEATURE_LPAE, /* has Large Physical Address Extension */ 2468 ARM_FEATURE_V8, 2469 ARM_FEATURE_AARCH64, /* supports 64 bit mode */ 2470 ARM_FEATURE_CBAR, /* has cp15 CBAR */ 2471 ARM_FEATURE_CBAR_RO, /* has cp15 CBAR and it is read-only */ 2472 ARM_FEATURE_EL2, /* has EL2 Virtualization support */ 2473 ARM_FEATURE_EL3, /* has EL3 Secure monitor support */ 2474 ARM_FEATURE_THUMB_DSP, /* DSP insns supported in the Thumb encodings */ 2475 ARM_FEATURE_PMU, /* has PMU support */ 2476 ARM_FEATURE_VBAR, /* has cp15 VBAR */ 2477 ARM_FEATURE_M_SECURITY, /* M profile Security Extension */ 2478 ARM_FEATURE_M_MAIN, /* M profile Main Extension */ 2479 ARM_FEATURE_V8_1M, /* M profile extras only in v8.1M and later */ 2480 }; 2481 2482 static inline int arm_feature(CPUARMState *env, int feature) 2483 { 2484 return (env->features & (1ULL << feature)) != 0; 2485 } 2486 2487 void arm_cpu_finalize_features(ARMCPU *cpu, Error **errp); 2488 2489 /* 2490 * ARM v9 security states. 2491 * The ordering of the enumeration corresponds to the low 2 bits 2492 * of the GPI value, and (except for Root) the concat of NSE:NS. 2493 */ 2494 2495 typedef enum ARMSecuritySpace { 2496 ARMSS_Secure = 0, 2497 ARMSS_NonSecure = 1, 2498 ARMSS_Root = 2, 2499 ARMSS_Realm = 3, 2500 } ARMSecuritySpace; 2501 2502 /* Return true if @space is secure, in the pre-v9 sense. */ 2503 static inline bool arm_space_is_secure(ARMSecuritySpace space) 2504 { 2505 return space == ARMSS_Secure || space == ARMSS_Root; 2506 } 2507 2508 /* Return the ARMSecuritySpace for @secure, assuming !RME or EL[0-2]. */ 2509 static inline ARMSecuritySpace arm_secure_to_space(bool secure) 2510 { 2511 return secure ? ARMSS_Secure : ARMSS_NonSecure; 2512 } 2513 2514 #if !defined(CONFIG_USER_ONLY) 2515 /** 2516 * arm_security_space_below_el3: 2517 * @env: cpu context 2518 * 2519 * Return the security space of exception levels below EL3, following 2520 * an exception return to those levels. Unlike arm_security_space, 2521 * this doesn't care about the current EL. 2522 */ 2523 ARMSecuritySpace arm_security_space_below_el3(CPUARMState *env); 2524 2525 /** 2526 * arm_is_secure_below_el3: 2527 * @env: cpu context 2528 * 2529 * Return true if exception levels below EL3 are in secure state, 2530 * or would be following an exception return to those levels. 2531 */ 2532 static inline bool arm_is_secure_below_el3(CPUARMState *env) 2533 { 2534 ARMSecuritySpace ss = arm_security_space_below_el3(env); 2535 return ss == ARMSS_Secure; 2536 } 2537 2538 /* Return true if the CPU is AArch64 EL3 or AArch32 Mon */ 2539 static inline bool arm_is_el3_or_mon(CPUARMState *env) 2540 { 2541 assert(!arm_feature(env, ARM_FEATURE_M)); 2542 if (arm_feature(env, ARM_FEATURE_EL3)) { 2543 if (is_a64(env) && extract32(env->pstate, 2, 2) == 3) { 2544 /* CPU currently in AArch64 state and EL3 */ 2545 return true; 2546 } else if (!is_a64(env) && 2547 (env->uncached_cpsr & CPSR_M) == ARM_CPU_MODE_MON) { 2548 /* CPU currently in AArch32 state and monitor mode */ 2549 return true; 2550 } 2551 } 2552 return false; 2553 } 2554 2555 /** 2556 * arm_security_space: 2557 * @env: cpu context 2558 * 2559 * Return the current security space of the cpu. 2560 */ 2561 ARMSecuritySpace arm_security_space(CPUARMState *env); 2562 2563 /** 2564 * arm_is_secure: 2565 * @env: cpu context 2566 * 2567 * Return true if the processor is in secure state. 2568 */ 2569 static inline bool arm_is_secure(CPUARMState *env) 2570 { 2571 return arm_space_is_secure(arm_security_space(env)); 2572 } 2573 2574 /* 2575 * Return true if the current security state has AArch64 EL2 or AArch32 Hyp. 2576 * This corresponds to the pseudocode EL2Enabled(). 2577 */ 2578 static inline bool arm_is_el2_enabled_secstate(CPUARMState *env, 2579 ARMSecuritySpace space) 2580 { 2581 assert(space != ARMSS_Root); 2582 return arm_feature(env, ARM_FEATURE_EL2) 2583 && (space != ARMSS_Secure || (env->cp15.scr_el3 & SCR_EEL2)); 2584 } 2585 2586 static inline bool arm_is_el2_enabled(CPUARMState *env) 2587 { 2588 return arm_is_el2_enabled_secstate(env, arm_security_space_below_el3(env)); 2589 } 2590 2591 #else 2592 static inline ARMSecuritySpace arm_security_space_below_el3(CPUARMState *env) 2593 { 2594 return ARMSS_NonSecure; 2595 } 2596 2597 static inline bool arm_is_secure_below_el3(CPUARMState *env) 2598 { 2599 return false; 2600 } 2601 2602 static inline ARMSecuritySpace arm_security_space(CPUARMState *env) 2603 { 2604 return ARMSS_NonSecure; 2605 } 2606 2607 static inline bool arm_is_secure(CPUARMState *env) 2608 { 2609 return false; 2610 } 2611 2612 static inline bool arm_is_el2_enabled_secstate(CPUARMState *env, 2613 ARMSecuritySpace space) 2614 { 2615 return false; 2616 } 2617 2618 static inline bool arm_is_el2_enabled(CPUARMState *env) 2619 { 2620 return false; 2621 } 2622 #endif 2623 2624 /** 2625 * arm_hcr_el2_eff(): Return the effective value of HCR_EL2. 2626 * E.g. when in secure state, fields in HCR_EL2 are suppressed, 2627 * "for all purposes other than a direct read or write access of HCR_EL2." 2628 * Not included here is HCR_RW. 2629 */ 2630 uint64_t arm_hcr_el2_eff_secstate(CPUARMState *env, ARMSecuritySpace space); 2631 uint64_t arm_hcr_el2_eff(CPUARMState *env); 2632 uint64_t arm_hcrx_el2_eff(CPUARMState *env); 2633 2634 /* Return true if the specified exception level is running in AArch64 state. */ 2635 static inline bool arm_el_is_aa64(CPUARMState *env, int el) 2636 { 2637 /* This isn't valid for EL0 (if we're in EL0, is_a64() is what you want, 2638 * and if we're not in EL0 then the state of EL0 isn't well defined.) 2639 */ 2640 assert(el >= 1 && el <= 3); 2641 bool aa64 = arm_feature(env, ARM_FEATURE_AARCH64); 2642 2643 /* The highest exception level is always at the maximum supported 2644 * register width, and then lower levels have a register width controlled 2645 * by bits in the SCR or HCR registers. 2646 */ 2647 if (el == 3) { 2648 return aa64; 2649 } 2650 2651 if (arm_feature(env, ARM_FEATURE_EL3) && 2652 ((env->cp15.scr_el3 & SCR_NS) || !(env->cp15.scr_el3 & SCR_EEL2))) { 2653 aa64 = aa64 && (env->cp15.scr_el3 & SCR_RW); 2654 } 2655 2656 if (el == 2) { 2657 return aa64; 2658 } 2659 2660 if (arm_is_el2_enabled(env)) { 2661 aa64 = aa64 && (env->cp15.hcr_el2 & HCR_RW); 2662 } 2663 2664 return aa64; 2665 } 2666 2667 /* Function for determining whether guest cp register reads and writes should 2668 * access the secure or non-secure bank of a cp register. When EL3 is 2669 * operating in AArch32 state, the NS-bit determines whether the secure 2670 * instance of a cp register should be used. When EL3 is AArch64 (or if 2671 * it doesn't exist at all) then there is no register banking, and all 2672 * accesses are to the non-secure version. 2673 */ 2674 static inline bool access_secure_reg(CPUARMState *env) 2675 { 2676 bool ret = (arm_feature(env, ARM_FEATURE_EL3) && 2677 !arm_el_is_aa64(env, 3) && 2678 !(env->cp15.scr_el3 & SCR_NS)); 2679 2680 return ret; 2681 } 2682 2683 /* Macros for accessing a specified CP register bank */ 2684 #define A32_BANKED_REG_GET(_env, _regname, _secure) \ 2685 ((_secure) ? (_env)->cp15._regname##_s : (_env)->cp15._regname##_ns) 2686 2687 #define A32_BANKED_REG_SET(_env, _regname, _secure, _val) \ 2688 do { \ 2689 if (_secure) { \ 2690 (_env)->cp15._regname##_s = (_val); \ 2691 } else { \ 2692 (_env)->cp15._regname##_ns = (_val); \ 2693 } \ 2694 } while (0) 2695 2696 /* Macros for automatically accessing a specific CP register bank depending on 2697 * the current secure state of the system. These macros are not intended for 2698 * supporting instruction translation reads/writes as these are dependent 2699 * solely on the SCR.NS bit and not the mode. 2700 */ 2701 #define A32_BANKED_CURRENT_REG_GET(_env, _regname) \ 2702 A32_BANKED_REG_GET((_env), _regname, \ 2703 (arm_is_secure(_env) && !arm_el_is_aa64((_env), 3))) 2704 2705 #define A32_BANKED_CURRENT_REG_SET(_env, _regname, _val) \ 2706 A32_BANKED_REG_SET((_env), _regname, \ 2707 (arm_is_secure(_env) && !arm_el_is_aa64((_env), 3)), \ 2708 (_val)) 2709 2710 uint32_t arm_phys_excp_target_el(CPUState *cs, uint32_t excp_idx, 2711 uint32_t cur_el, bool secure); 2712 2713 /* Return the highest implemented Exception Level */ 2714 static inline int arm_highest_el(CPUARMState *env) 2715 { 2716 if (arm_feature(env, ARM_FEATURE_EL3)) { 2717 return 3; 2718 } 2719 if (arm_feature(env, ARM_FEATURE_EL2)) { 2720 return 2; 2721 } 2722 return 1; 2723 } 2724 2725 /* Return true if a v7M CPU is in Handler mode */ 2726 static inline bool arm_v7m_is_handler_mode(CPUARMState *env) 2727 { 2728 return env->v7m.exception != 0; 2729 } 2730 2731 /* Return the current Exception Level (as per ARMv8; note that this differs 2732 * from the ARMv7 Privilege Level). 2733 */ 2734 static inline int arm_current_el(CPUARMState *env) 2735 { 2736 if (arm_feature(env, ARM_FEATURE_M)) { 2737 return arm_v7m_is_handler_mode(env) || 2738 !(env->v7m.control[env->v7m.secure] & 1); 2739 } 2740 2741 if (is_a64(env)) { 2742 return extract32(env->pstate, 2, 2); 2743 } 2744 2745 switch (env->uncached_cpsr & 0x1f) { 2746 case ARM_CPU_MODE_USR: 2747 return 0; 2748 case ARM_CPU_MODE_HYP: 2749 return 2; 2750 case ARM_CPU_MODE_MON: 2751 return 3; 2752 default: 2753 if (arm_is_secure(env) && !arm_el_is_aa64(env, 3)) { 2754 /* If EL3 is 32-bit then all secure privileged modes run in 2755 * EL3 2756 */ 2757 return 3; 2758 } 2759 2760 return 1; 2761 } 2762 } 2763 2764 /** 2765 * write_list_to_cpustate 2766 * @cpu: ARMCPU 2767 * 2768 * For each register listed in the ARMCPU cpreg_indexes list, write 2769 * its value from the cpreg_values list into the ARMCPUState structure. 2770 * This updates TCG's working data structures from KVM data or 2771 * from incoming migration state. 2772 * 2773 * Returns: true if all register values were updated correctly, 2774 * false if some register was unknown or could not be written. 2775 * Note that we do not stop early on failure -- we will attempt 2776 * writing all registers in the list. 2777 */ 2778 bool write_list_to_cpustate(ARMCPU *cpu); 2779 2780 /** 2781 * write_cpustate_to_list: 2782 * @cpu: ARMCPU 2783 * @kvm_sync: true if this is for syncing back to KVM 2784 * 2785 * For each register listed in the ARMCPU cpreg_indexes list, write 2786 * its value from the ARMCPUState structure into the cpreg_values list. 2787 * This is used to copy info from TCG's working data structures into 2788 * KVM or for outbound migration. 2789 * 2790 * @kvm_sync is true if we are doing this in order to sync the 2791 * register state back to KVM. In this case we will only update 2792 * values in the list if the previous list->cpustate sync actually 2793 * successfully wrote the CPU state. Otherwise we will keep the value 2794 * that is in the list. 2795 * 2796 * Returns: true if all register values were read correctly, 2797 * false if some register was unknown or could not be read. 2798 * Note that we do not stop early on failure -- we will attempt 2799 * reading all registers in the list. 2800 */ 2801 bool write_cpustate_to_list(ARMCPU *cpu, bool kvm_sync); 2802 2803 #define ARM_CPUID_TI915T 0x54029152 2804 #define ARM_CPUID_TI925T 0x54029252 2805 2806 #define CPU_RESOLVING_TYPE TYPE_ARM_CPU 2807 2808 #define TYPE_ARM_HOST_CPU "host-" TYPE_ARM_CPU 2809 2810 /* ARM has the following "translation regimes" (as the ARM ARM calls them): 2811 * 2812 * If EL3 is 64-bit: 2813 * + NonSecure EL1 & 0 stage 1 2814 * + NonSecure EL1 & 0 stage 2 2815 * + NonSecure EL2 2816 * + NonSecure EL2 & 0 (ARMv8.1-VHE) 2817 * + Secure EL1 & 0 2818 * + Secure EL3 2819 * If EL3 is 32-bit: 2820 * + NonSecure PL1 & 0 stage 1 2821 * + NonSecure PL1 & 0 stage 2 2822 * + NonSecure PL2 2823 * + Secure PL0 2824 * + Secure PL1 2825 * (reminder: for 32 bit EL3, Secure PL1 is *EL3*, not EL1.) 2826 * 2827 * For QEMU, an mmu_idx is not quite the same as a translation regime because: 2828 * 1. we need to split the "EL1 & 0" and "EL2 & 0" regimes into two mmu_idxes, 2829 * because they may differ in access permissions even if the VA->PA map is 2830 * the same 2831 * 2. we want to cache in our TLB the full VA->IPA->PA lookup for a stage 1+2 2832 * translation, which means that we have one mmu_idx that deals with two 2833 * concatenated translation regimes [this sort of combined s1+2 TLB is 2834 * architecturally permitted] 2835 * 3. we don't need to allocate an mmu_idx to translations that we won't be 2836 * handling via the TLB. The only way to do a stage 1 translation without 2837 * the immediate stage 2 translation is via the ATS or AT system insns, 2838 * which can be slow-pathed and always do a page table walk. 2839 * The only use of stage 2 translations is either as part of an s1+2 2840 * lookup or when loading the descriptors during a stage 1 page table walk, 2841 * and in both those cases we don't use the TLB. 2842 * 4. we can also safely fold together the "32 bit EL3" and "64 bit EL3" 2843 * translation regimes, because they map reasonably well to each other 2844 * and they can't both be active at the same time. 2845 * 5. we want to be able to use the TLB for accesses done as part of a 2846 * stage1 page table walk, rather than having to walk the stage2 page 2847 * table over and over. 2848 * 6. we need separate EL1/EL2 mmu_idx for handling the Privileged Access 2849 * Never (PAN) bit within PSTATE. 2850 * 7. we fold together the secure and non-secure regimes for A-profile, 2851 * because there are no banked system registers for aarch64, so the 2852 * process of switching between secure and non-secure is 2853 * already heavyweight. 2854 * 2855 * This gives us the following list of cases: 2856 * 2857 * EL0 EL1&0 stage 1+2 (aka NS PL0) 2858 * EL1 EL1&0 stage 1+2 (aka NS PL1) 2859 * EL1 EL1&0 stage 1+2 +PAN 2860 * EL0 EL2&0 2861 * EL2 EL2&0 2862 * EL2 EL2&0 +PAN 2863 * EL2 (aka NS PL2) 2864 * EL3 (aka S PL1) 2865 * Physical (NS & S) 2866 * Stage2 (NS & S) 2867 * 2868 * for a total of 12 different mmu_idx. 2869 * 2870 * R profile CPUs have an MPU, but can use the same set of MMU indexes 2871 * as A profile. They only need to distinguish EL0 and EL1 (and 2872 * EL2 if we ever model a Cortex-R52). 2873 * 2874 * M profile CPUs are rather different as they do not have a true MMU. 2875 * They have the following different MMU indexes: 2876 * User 2877 * Privileged 2878 * User, execution priority negative (ie the MPU HFNMIENA bit may apply) 2879 * Privileged, execution priority negative (ditto) 2880 * If the CPU supports the v8M Security Extension then there are also: 2881 * Secure User 2882 * Secure Privileged 2883 * Secure User, execution priority negative 2884 * Secure Privileged, execution priority negative 2885 * 2886 * The ARMMMUIdx and the mmu index value used by the core QEMU TLB code 2887 * are not quite the same -- different CPU types (most notably M profile 2888 * vs A/R profile) would like to use MMU indexes with different semantics, 2889 * but since we don't ever need to use all of those in a single CPU we 2890 * can avoid having to set NB_MMU_MODES to "total number of A profile MMU 2891 * modes + total number of M profile MMU modes". The lower bits of 2892 * ARMMMUIdx are the core TLB mmu index, and the higher bits are always 2893 * the same for any particular CPU. 2894 * Variables of type ARMMUIdx are always full values, and the core 2895 * index values are in variables of type 'int'. 2896 * 2897 * Our enumeration includes at the end some entries which are not "true" 2898 * mmu_idx values in that they don't have corresponding TLBs and are only 2899 * valid for doing slow path page table walks. 2900 * 2901 * The constant names here are patterned after the general style of the names 2902 * of the AT/ATS operations. 2903 * The values used are carefully arranged to make mmu_idx => EL lookup easy. 2904 * For M profile we arrange them to have a bit for priv, a bit for negpri 2905 * and a bit for secure. 2906 */ 2907 #define ARM_MMU_IDX_A 0x10 /* A profile */ 2908 #define ARM_MMU_IDX_NOTLB 0x20 /* does not have a TLB */ 2909 #define ARM_MMU_IDX_M 0x40 /* M profile */ 2910 2911 /* Meanings of the bits for M profile mmu idx values */ 2912 #define ARM_MMU_IDX_M_PRIV 0x1 2913 #define ARM_MMU_IDX_M_NEGPRI 0x2 2914 #define ARM_MMU_IDX_M_S 0x4 /* Secure */ 2915 2916 #define ARM_MMU_IDX_TYPE_MASK \ 2917 (ARM_MMU_IDX_A | ARM_MMU_IDX_M | ARM_MMU_IDX_NOTLB) 2918 #define ARM_MMU_IDX_COREIDX_MASK 0xf 2919 2920 typedef enum ARMMMUIdx { 2921 /* 2922 * A-profile. 2923 */ 2924 ARMMMUIdx_E10_0 = 0 | ARM_MMU_IDX_A, 2925 ARMMMUIdx_E20_0 = 1 | ARM_MMU_IDX_A, 2926 ARMMMUIdx_E10_1 = 2 | ARM_MMU_IDX_A, 2927 ARMMMUIdx_E20_2 = 3 | ARM_MMU_IDX_A, 2928 ARMMMUIdx_E10_1_PAN = 4 | ARM_MMU_IDX_A, 2929 ARMMMUIdx_E20_2_PAN = 5 | ARM_MMU_IDX_A, 2930 ARMMMUIdx_E2 = 6 | ARM_MMU_IDX_A, 2931 ARMMMUIdx_E3 = 7 | ARM_MMU_IDX_A, 2932 2933 /* 2934 * Used for second stage of an S12 page table walk, or for descriptor 2935 * loads during first stage of an S1 page table walk. Note that both 2936 * are in use simultaneously for SecureEL2: the security state for 2937 * the S2 ptw is selected by the NS bit from the S1 ptw. 2938 */ 2939 ARMMMUIdx_Stage2_S = 8 | ARM_MMU_IDX_A, 2940 ARMMMUIdx_Stage2 = 9 | ARM_MMU_IDX_A, 2941 2942 /* TLBs with 1-1 mapping to the physical address spaces. */ 2943 ARMMMUIdx_Phys_S = 10 | ARM_MMU_IDX_A, 2944 ARMMMUIdx_Phys_NS = 11 | ARM_MMU_IDX_A, 2945 ARMMMUIdx_Phys_Root = 12 | ARM_MMU_IDX_A, 2946 ARMMMUIdx_Phys_Realm = 13 | ARM_MMU_IDX_A, 2947 2948 /* 2949 * These are not allocated TLBs and are used only for AT system 2950 * instructions or for the first stage of an S12 page table walk. 2951 */ 2952 ARMMMUIdx_Stage1_E0 = 0 | ARM_MMU_IDX_NOTLB, 2953 ARMMMUIdx_Stage1_E1 = 1 | ARM_MMU_IDX_NOTLB, 2954 ARMMMUIdx_Stage1_E1_PAN = 2 | ARM_MMU_IDX_NOTLB, 2955 2956 /* 2957 * M-profile. 2958 */ 2959 ARMMMUIdx_MUser = ARM_MMU_IDX_M, 2960 ARMMMUIdx_MPriv = ARM_MMU_IDX_M | ARM_MMU_IDX_M_PRIV, 2961 ARMMMUIdx_MUserNegPri = ARMMMUIdx_MUser | ARM_MMU_IDX_M_NEGPRI, 2962 ARMMMUIdx_MPrivNegPri = ARMMMUIdx_MPriv | ARM_MMU_IDX_M_NEGPRI, 2963 ARMMMUIdx_MSUser = ARMMMUIdx_MUser | ARM_MMU_IDX_M_S, 2964 ARMMMUIdx_MSPriv = ARMMMUIdx_MPriv | ARM_MMU_IDX_M_S, 2965 ARMMMUIdx_MSUserNegPri = ARMMMUIdx_MUserNegPri | ARM_MMU_IDX_M_S, 2966 ARMMMUIdx_MSPrivNegPri = ARMMMUIdx_MPrivNegPri | ARM_MMU_IDX_M_S, 2967 } ARMMMUIdx; 2968 2969 /* 2970 * Bit macros for the core-mmu-index values for each index, 2971 * for use when calling tlb_flush_by_mmuidx() and friends. 2972 */ 2973 #define TO_CORE_BIT(NAME) \ 2974 ARMMMUIdxBit_##NAME = 1 << (ARMMMUIdx_##NAME & ARM_MMU_IDX_COREIDX_MASK) 2975 2976 typedef enum ARMMMUIdxBit { 2977 TO_CORE_BIT(E10_0), 2978 TO_CORE_BIT(E20_0), 2979 TO_CORE_BIT(E10_1), 2980 TO_CORE_BIT(E10_1_PAN), 2981 TO_CORE_BIT(E2), 2982 TO_CORE_BIT(E20_2), 2983 TO_CORE_BIT(E20_2_PAN), 2984 TO_CORE_BIT(E3), 2985 TO_CORE_BIT(Stage2), 2986 TO_CORE_BIT(Stage2_S), 2987 2988 TO_CORE_BIT(MUser), 2989 TO_CORE_BIT(MPriv), 2990 TO_CORE_BIT(MUserNegPri), 2991 TO_CORE_BIT(MPrivNegPri), 2992 TO_CORE_BIT(MSUser), 2993 TO_CORE_BIT(MSPriv), 2994 TO_CORE_BIT(MSUserNegPri), 2995 TO_CORE_BIT(MSPrivNegPri), 2996 } ARMMMUIdxBit; 2997 2998 #undef TO_CORE_BIT 2999 3000 #define MMU_USER_IDX 0 3001 3002 /* Indexes used when registering address spaces with cpu_address_space_init */ 3003 typedef enum ARMASIdx { 3004 ARMASIdx_NS = 0, 3005 ARMASIdx_S = 1, 3006 ARMASIdx_TagNS = 2, 3007 ARMASIdx_TagS = 3, 3008 } ARMASIdx; 3009 3010 static inline ARMMMUIdx arm_space_to_phys(ARMSecuritySpace space) 3011 { 3012 /* Assert the relative order of the physical mmu indexes. */ 3013 QEMU_BUILD_BUG_ON(ARMSS_Secure != 0); 3014 QEMU_BUILD_BUG_ON(ARMMMUIdx_Phys_NS != ARMMMUIdx_Phys_S + ARMSS_NonSecure); 3015 QEMU_BUILD_BUG_ON(ARMMMUIdx_Phys_Root != ARMMMUIdx_Phys_S + ARMSS_Root); 3016 QEMU_BUILD_BUG_ON(ARMMMUIdx_Phys_Realm != ARMMMUIdx_Phys_S + ARMSS_Realm); 3017 3018 return ARMMMUIdx_Phys_S + space; 3019 } 3020 3021 static inline ARMSecuritySpace arm_phys_to_space(ARMMMUIdx idx) 3022 { 3023 assert(idx >= ARMMMUIdx_Phys_S && idx <= ARMMMUIdx_Phys_Realm); 3024 return idx - ARMMMUIdx_Phys_S; 3025 } 3026 3027 static inline bool arm_v7m_csselr_razwi(ARMCPU *cpu) 3028 { 3029 /* If all the CLIDR.Ctypem bits are 0 there are no caches, and 3030 * CSSELR is RAZ/WI. 3031 */ 3032 return (cpu->clidr & R_V7M_CLIDR_CTYPE_ALL_MASK) != 0; 3033 } 3034 3035 static inline bool arm_sctlr_b(CPUARMState *env) 3036 { 3037 return 3038 /* We need not implement SCTLR.ITD in user-mode emulation, so 3039 * let linux-user ignore the fact that it conflicts with SCTLR_B. 3040 * This lets people run BE32 binaries with "-cpu any". 3041 */ 3042 #ifndef CONFIG_USER_ONLY 3043 !arm_feature(env, ARM_FEATURE_V7) && 3044 #endif 3045 (env->cp15.sctlr_el[1] & SCTLR_B) != 0; 3046 } 3047 3048 uint64_t arm_sctlr(CPUARMState *env, int el); 3049 3050 static inline bool arm_cpu_data_is_big_endian_a32(CPUARMState *env, 3051 bool sctlr_b) 3052 { 3053 #ifdef CONFIG_USER_ONLY 3054 /* 3055 * In system mode, BE32 is modelled in line with the 3056 * architecture (as word-invariant big-endianness), where loads 3057 * and stores are done little endian but from addresses which 3058 * are adjusted by XORing with the appropriate constant. So the 3059 * endianness to use for the raw data access is not affected by 3060 * SCTLR.B. 3061 * In user mode, however, we model BE32 as byte-invariant 3062 * big-endianness (because user-only code cannot tell the 3063 * difference), and so we need to use a data access endianness 3064 * that depends on SCTLR.B. 3065 */ 3066 if (sctlr_b) { 3067 return true; 3068 } 3069 #endif 3070 /* In 32bit endianness is determined by looking at CPSR's E bit */ 3071 return env->uncached_cpsr & CPSR_E; 3072 } 3073 3074 static inline bool arm_cpu_data_is_big_endian_a64(int el, uint64_t sctlr) 3075 { 3076 return sctlr & (el ? SCTLR_EE : SCTLR_E0E); 3077 } 3078 3079 /* Return true if the processor is in big-endian mode. */ 3080 static inline bool arm_cpu_data_is_big_endian(CPUARMState *env) 3081 { 3082 if (!is_a64(env)) { 3083 return arm_cpu_data_is_big_endian_a32(env, arm_sctlr_b(env)); 3084 } else { 3085 int cur_el = arm_current_el(env); 3086 uint64_t sctlr = arm_sctlr(env, cur_el); 3087 return arm_cpu_data_is_big_endian_a64(cur_el, sctlr); 3088 } 3089 } 3090 3091 #include "exec/cpu-all.h" 3092 3093 /* 3094 * We have more than 32-bits worth of state per TB, so we split the data 3095 * between tb->flags and tb->cs_base, which is otherwise unused for ARM. 3096 * We collect these two parts in CPUARMTBFlags where they are named 3097 * flags and flags2 respectively. 3098 * 3099 * The flags that are shared between all execution modes, TBFLAG_ANY, 3100 * are stored in flags. The flags that are specific to a given mode 3101 * are stores in flags2. Since cs_base is sized on the configured 3102 * address size, flags2 always has 64-bits for A64, and a minimum of 3103 * 32-bits for A32 and M32. 3104 * 3105 * The bits for 32-bit A-profile and M-profile partially overlap: 3106 * 3107 * 31 23 11 10 0 3108 * +-------------+----------+----------------+ 3109 * | | | TBFLAG_A32 | 3110 * | TBFLAG_AM32 | +-----+----------+ 3111 * | | |TBFLAG_M32| 3112 * +-------------+----------------+----------+ 3113 * 31 23 6 5 0 3114 * 3115 * Unless otherwise noted, these bits are cached in env->hflags. 3116 */ 3117 FIELD(TBFLAG_ANY, AARCH64_STATE, 0, 1) 3118 FIELD(TBFLAG_ANY, SS_ACTIVE, 1, 1) 3119 FIELD(TBFLAG_ANY, PSTATE__SS, 2, 1) /* Not cached. */ 3120 FIELD(TBFLAG_ANY, BE_DATA, 3, 1) 3121 FIELD(TBFLAG_ANY, MMUIDX, 4, 4) 3122 /* Target EL if we take a floating-point-disabled exception */ 3123 FIELD(TBFLAG_ANY, FPEXC_EL, 8, 2) 3124 /* Memory operations require alignment: SCTLR_ELx.A or CCR.UNALIGN_TRP */ 3125 FIELD(TBFLAG_ANY, ALIGN_MEM, 10, 1) 3126 FIELD(TBFLAG_ANY, PSTATE__IL, 11, 1) 3127 FIELD(TBFLAG_ANY, FGT_ACTIVE, 12, 1) 3128 FIELD(TBFLAG_ANY, FGT_SVC, 13, 1) 3129 3130 /* 3131 * Bit usage when in AArch32 state, both A- and M-profile. 3132 */ 3133 FIELD(TBFLAG_AM32, CONDEXEC, 24, 8) /* Not cached. */ 3134 FIELD(TBFLAG_AM32, THUMB, 23, 1) /* Not cached. */ 3135 3136 /* 3137 * Bit usage when in AArch32 state, for A-profile only. 3138 */ 3139 FIELD(TBFLAG_A32, VECLEN, 0, 3) /* Not cached. */ 3140 FIELD(TBFLAG_A32, VECSTRIDE, 3, 2) /* Not cached. */ 3141 /* 3142 * We store the bottom two bits of the CPAR as TB flags and handle 3143 * checks on the other bits at runtime. This shares the same bits as 3144 * VECSTRIDE, which is OK as no XScale CPU has VFP. 3145 * Not cached, because VECLEN+VECSTRIDE are not cached. 3146 */ 3147 FIELD(TBFLAG_A32, XSCALE_CPAR, 5, 2) 3148 FIELD(TBFLAG_A32, VFPEN, 7, 1) /* Partially cached, minus FPEXC. */ 3149 FIELD(TBFLAG_A32, SCTLR__B, 8, 1) /* Cannot overlap with SCTLR_B */ 3150 FIELD(TBFLAG_A32, HSTR_ACTIVE, 9, 1) 3151 /* 3152 * Indicates whether cp register reads and writes by guest code should access 3153 * the secure or nonsecure bank of banked registers; note that this is not 3154 * the same thing as the current security state of the processor! 3155 */ 3156 FIELD(TBFLAG_A32, NS, 10, 1) 3157 /* 3158 * Indicates that SME Streaming mode is active, and SMCR_ELx.FA64 is not. 3159 * This requires an SME trap from AArch32 mode when using NEON. 3160 */ 3161 FIELD(TBFLAG_A32, SME_TRAP_NONSTREAMING, 11, 1) 3162 3163 /* 3164 * Bit usage when in AArch32 state, for M-profile only. 3165 */ 3166 /* Handler (ie not Thread) mode */ 3167 FIELD(TBFLAG_M32, HANDLER, 0, 1) 3168 /* Whether we should generate stack-limit checks */ 3169 FIELD(TBFLAG_M32, STACKCHECK, 1, 1) 3170 /* Set if FPCCR.LSPACT is set */ 3171 FIELD(TBFLAG_M32, LSPACT, 2, 1) /* Not cached. */ 3172 /* Set if we must create a new FP context */ 3173 FIELD(TBFLAG_M32, NEW_FP_CTXT_NEEDED, 3, 1) /* Not cached. */ 3174 /* Set if FPCCR.S does not match current security state */ 3175 FIELD(TBFLAG_M32, FPCCR_S_WRONG, 4, 1) /* Not cached. */ 3176 /* Set if MVE insns are definitely not predicated by VPR or LTPSIZE */ 3177 FIELD(TBFLAG_M32, MVE_NO_PRED, 5, 1) /* Not cached. */ 3178 /* Set if in secure mode */ 3179 FIELD(TBFLAG_M32, SECURE, 6, 1) 3180 3181 /* 3182 * Bit usage when in AArch64 state 3183 */ 3184 FIELD(TBFLAG_A64, TBII, 0, 2) 3185 FIELD(TBFLAG_A64, SVEEXC_EL, 2, 2) 3186 /* The current vector length, either NVL or SVL. */ 3187 FIELD(TBFLAG_A64, VL, 4, 4) 3188 FIELD(TBFLAG_A64, PAUTH_ACTIVE, 8, 1) 3189 FIELD(TBFLAG_A64, BT, 9, 1) 3190 FIELD(TBFLAG_A64, BTYPE, 10, 2) /* Not cached. */ 3191 FIELD(TBFLAG_A64, TBID, 12, 2) 3192 FIELD(TBFLAG_A64, UNPRIV, 14, 1) 3193 FIELD(TBFLAG_A64, ATA, 15, 1) 3194 FIELD(TBFLAG_A64, TCMA, 16, 2) 3195 FIELD(TBFLAG_A64, MTE_ACTIVE, 18, 1) 3196 FIELD(TBFLAG_A64, MTE0_ACTIVE, 19, 1) 3197 FIELD(TBFLAG_A64, SMEEXC_EL, 20, 2) 3198 FIELD(TBFLAG_A64, PSTATE_SM, 22, 1) 3199 FIELD(TBFLAG_A64, PSTATE_ZA, 23, 1) 3200 FIELD(TBFLAG_A64, SVL, 24, 4) 3201 /* Indicates that SME Streaming mode is active, and SMCR_ELx.FA64 is not. */ 3202 FIELD(TBFLAG_A64, SME_TRAP_NONSTREAMING, 28, 1) 3203 FIELD(TBFLAG_A64, TRAP_ERET, 29, 1) 3204 FIELD(TBFLAG_A64, NAA, 30, 1) 3205 FIELD(TBFLAG_A64, ATA0, 31, 1) 3206 FIELD(TBFLAG_A64, NV, 32, 1) 3207 FIELD(TBFLAG_A64, NV1, 33, 1) 3208 FIELD(TBFLAG_A64, NV2, 34, 1) 3209 /* Set if FEAT_NV2 RAM accesses use the EL2&0 translation regime */ 3210 FIELD(TBFLAG_A64, NV2_MEM_E20, 35, 1) 3211 /* Set if FEAT_NV2 RAM accesses are big-endian */ 3212 FIELD(TBFLAG_A64, NV2_MEM_BE, 36, 1) 3213 3214 /* 3215 * Helpers for using the above. Note that only the A64 accessors use 3216 * FIELD_DP64() and FIELD_EX64(), because in the other cases the flags 3217 * word either is or might be 32 bits only. 3218 */ 3219 #define DP_TBFLAG_ANY(DST, WHICH, VAL) \ 3220 (DST.flags = FIELD_DP32(DST.flags, TBFLAG_ANY, WHICH, VAL)) 3221 #define DP_TBFLAG_A64(DST, WHICH, VAL) \ 3222 (DST.flags2 = FIELD_DP64(DST.flags2, TBFLAG_A64, WHICH, VAL)) 3223 #define DP_TBFLAG_A32(DST, WHICH, VAL) \ 3224 (DST.flags2 = FIELD_DP32(DST.flags2, TBFLAG_A32, WHICH, VAL)) 3225 #define DP_TBFLAG_M32(DST, WHICH, VAL) \ 3226 (DST.flags2 = FIELD_DP32(DST.flags2, TBFLAG_M32, WHICH, VAL)) 3227 #define DP_TBFLAG_AM32(DST, WHICH, VAL) \ 3228 (DST.flags2 = FIELD_DP32(DST.flags2, TBFLAG_AM32, WHICH, VAL)) 3229 3230 #define EX_TBFLAG_ANY(IN, WHICH) FIELD_EX32(IN.flags, TBFLAG_ANY, WHICH) 3231 #define EX_TBFLAG_A64(IN, WHICH) FIELD_EX64(IN.flags2, TBFLAG_A64, WHICH) 3232 #define EX_TBFLAG_A32(IN, WHICH) FIELD_EX32(IN.flags2, TBFLAG_A32, WHICH) 3233 #define EX_TBFLAG_M32(IN, WHICH) FIELD_EX32(IN.flags2, TBFLAG_M32, WHICH) 3234 #define EX_TBFLAG_AM32(IN, WHICH) FIELD_EX32(IN.flags2, TBFLAG_AM32, WHICH) 3235 3236 /** 3237 * sve_vq 3238 * @env: the cpu context 3239 * 3240 * Return the VL cached within env->hflags, in units of quadwords. 3241 */ 3242 static inline int sve_vq(CPUARMState *env) 3243 { 3244 return EX_TBFLAG_A64(env->hflags, VL) + 1; 3245 } 3246 3247 /** 3248 * sme_vq 3249 * @env: the cpu context 3250 * 3251 * Return the SVL cached within env->hflags, in units of quadwords. 3252 */ 3253 static inline int sme_vq(CPUARMState *env) 3254 { 3255 return EX_TBFLAG_A64(env->hflags, SVL) + 1; 3256 } 3257 3258 static inline bool bswap_code(bool sctlr_b) 3259 { 3260 #ifdef CONFIG_USER_ONLY 3261 /* BE8 (SCTLR.B = 0, TARGET_BIG_ENDIAN = 1) is mixed endian. 3262 * The invalid combination SCTLR.B=1/CPSR.E=1/TARGET_BIG_ENDIAN=0 3263 * would also end up as a mixed-endian mode with BE code, LE data. 3264 */ 3265 return TARGET_BIG_ENDIAN ^ sctlr_b; 3266 #else 3267 /* All code access in ARM is little endian, and there are no loaders 3268 * doing swaps that need to be reversed 3269 */ 3270 return 0; 3271 #endif 3272 } 3273 3274 #ifdef CONFIG_USER_ONLY 3275 static inline bool arm_cpu_bswap_data(CPUARMState *env) 3276 { 3277 return TARGET_BIG_ENDIAN ^ arm_cpu_data_is_big_endian(env); 3278 } 3279 #endif 3280 3281 void cpu_get_tb_cpu_state(CPUARMState *env, vaddr *pc, 3282 uint64_t *cs_base, uint32_t *flags); 3283 3284 enum { 3285 QEMU_PSCI_CONDUIT_DISABLED = 0, 3286 QEMU_PSCI_CONDUIT_SMC = 1, 3287 QEMU_PSCI_CONDUIT_HVC = 2, 3288 }; 3289 3290 #ifndef CONFIG_USER_ONLY 3291 /* Return the address space index to use for a memory access */ 3292 static inline int arm_asidx_from_attrs(CPUState *cs, MemTxAttrs attrs) 3293 { 3294 return attrs.secure ? ARMASIdx_S : ARMASIdx_NS; 3295 } 3296 3297 /* Return the AddressSpace to use for a memory access 3298 * (which depends on whether the access is S or NS, and whether 3299 * the board gave us a separate AddressSpace for S accesses). 3300 */ 3301 static inline AddressSpace *arm_addressspace(CPUState *cs, MemTxAttrs attrs) 3302 { 3303 return cpu_get_address_space(cs, arm_asidx_from_attrs(cs, attrs)); 3304 } 3305 #endif 3306 3307 /** 3308 * arm_register_pre_el_change_hook: 3309 * Register a hook function which will be called immediately before this 3310 * CPU changes exception level or mode. The hook function will be 3311 * passed a pointer to the ARMCPU and the opaque data pointer passed 3312 * to this function when the hook was registered. 3313 * 3314 * Note that if a pre-change hook is called, any registered post-change hooks 3315 * are guaranteed to subsequently be called. 3316 */ 3317 void arm_register_pre_el_change_hook(ARMCPU *cpu, ARMELChangeHookFn *hook, 3318 void *opaque); 3319 /** 3320 * arm_register_el_change_hook: 3321 * Register a hook function which will be called immediately after this 3322 * CPU changes exception level or mode. The hook function will be 3323 * passed a pointer to the ARMCPU and the opaque data pointer passed 3324 * to this function when the hook was registered. 3325 * 3326 * Note that any registered hooks registered here are guaranteed to be called 3327 * if pre-change hooks have been. 3328 */ 3329 void arm_register_el_change_hook(ARMCPU *cpu, ARMELChangeHookFn *hook, void 3330 *opaque); 3331 3332 /** 3333 * arm_rebuild_hflags: 3334 * Rebuild the cached TBFLAGS for arbitrary changed processor state. 3335 */ 3336 void arm_rebuild_hflags(CPUARMState *env); 3337 3338 /** 3339 * aa32_vfp_dreg: 3340 * Return a pointer to the Dn register within env in 32-bit mode. 3341 */ 3342 static inline uint64_t *aa32_vfp_dreg(CPUARMState *env, unsigned regno) 3343 { 3344 return &env->vfp.zregs[regno >> 1].d[regno & 1]; 3345 } 3346 3347 /** 3348 * aa32_vfp_qreg: 3349 * Return a pointer to the Qn register within env in 32-bit mode. 3350 */ 3351 static inline uint64_t *aa32_vfp_qreg(CPUARMState *env, unsigned regno) 3352 { 3353 return &env->vfp.zregs[regno].d[0]; 3354 } 3355 3356 /** 3357 * aa64_vfp_qreg: 3358 * Return a pointer to the Qn register within env in 64-bit mode. 3359 */ 3360 static inline uint64_t *aa64_vfp_qreg(CPUARMState *env, unsigned regno) 3361 { 3362 return &env->vfp.zregs[regno].d[0]; 3363 } 3364 3365 /* Shared between translate-sve.c and sve_helper.c. */ 3366 extern const uint64_t pred_esz_masks[5]; 3367 3368 /* 3369 * AArch64 usage of the PAGE_TARGET_* bits for linux-user. 3370 * Note that with the Linux kernel, PROT_MTE may not be cleared by mprotect 3371 * mprotect but PROT_BTI may be cleared. C.f. the kernel's VM_ARCH_CLEAR. 3372 */ 3373 #define PAGE_BTI PAGE_TARGET_1 3374 #define PAGE_MTE PAGE_TARGET_2 3375 #define PAGE_TARGET_STICKY PAGE_MTE 3376 3377 /* We associate one allocation tag per 16 bytes, the minimum. */ 3378 #define LOG2_TAG_GRANULE 4 3379 #define TAG_GRANULE (1 << LOG2_TAG_GRANULE) 3380 3381 #ifdef CONFIG_USER_ONLY 3382 #define TARGET_PAGE_DATA_SIZE (TARGET_PAGE_SIZE >> (LOG2_TAG_GRANULE + 1)) 3383 #endif 3384 3385 #ifdef TARGET_TAGGED_ADDRESSES 3386 /** 3387 * cpu_untagged_addr: 3388 * @cs: CPU context 3389 * @x: tagged address 3390 * 3391 * Remove any address tag from @x. This is explicitly related to the 3392 * linux syscall TIF_TAGGED_ADDR setting, not TBI in general. 3393 * 3394 * There should be a better place to put this, but we need this in 3395 * include/exec/cpu_ldst.h, and not some place linux-user specific. 3396 */ 3397 static inline target_ulong cpu_untagged_addr(CPUState *cs, target_ulong x) 3398 { 3399 ARMCPU *cpu = ARM_CPU(cs); 3400 if (cpu->env.tagged_addr_enable) { 3401 /* 3402 * TBI is enabled for userspace but not kernelspace addresses. 3403 * Only clear the tag if bit 55 is clear. 3404 */ 3405 x &= sextract64(x, 0, 56); 3406 } 3407 return x; 3408 } 3409 #endif 3410 3411 #endif 3412