1 /* 2 * ARM virtual CPU header 3 * 4 * Copyright (c) 2003 Fabrice Bellard 5 * 6 * This library is free software; you can redistribute it and/or 7 * modify it under the terms of the GNU Lesser General Public 8 * License as published by the Free Software Foundation; either 9 * version 2 of the License, or (at your option) any later version. 10 * 11 * This library is distributed in the hope that it will be useful, 12 * but WITHOUT ANY WARRANTY; without even the implied warranty of 13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU 14 * Lesser General Public License for more details. 15 * 16 * You should have received a copy of the GNU Lesser General Public 17 * License along with this library; if not, see <http://www.gnu.org/licenses/>. 18 */ 19 20 #ifndef ARM_CPU_H 21 #define ARM_CPU_H 22 23 #include "kvm-consts.h" 24 #include "hw/registerfields.h" 25 26 #if defined(TARGET_AARCH64) 27 /* AArch64 definitions */ 28 # define TARGET_LONG_BITS 64 29 #else 30 # define TARGET_LONG_BITS 32 31 #endif 32 33 /* ARM processors have a weak memory model */ 34 #define TCG_GUEST_DEFAULT_MO (0) 35 36 #define CPUArchState struct CPUARMState 37 38 #include "qemu-common.h" 39 #include "cpu-qom.h" 40 #include "exec/cpu-defs.h" 41 42 #include "fpu/softfloat.h" 43 44 #define EXCP_UDEF 1 /* undefined instruction */ 45 #define EXCP_SWI 2 /* software interrupt */ 46 #define EXCP_PREFETCH_ABORT 3 47 #define EXCP_DATA_ABORT 4 48 #define EXCP_IRQ 5 49 #define EXCP_FIQ 6 50 #define EXCP_BKPT 7 51 #define EXCP_EXCEPTION_EXIT 8 /* Return from v7M exception. */ 52 #define EXCP_KERNEL_TRAP 9 /* Jumped to kernel code page. */ 53 #define EXCP_HVC 11 /* HyperVisor Call */ 54 #define EXCP_HYP_TRAP 12 55 #define EXCP_SMC 13 /* Secure Monitor Call */ 56 #define EXCP_VIRQ 14 57 #define EXCP_VFIQ 15 58 #define EXCP_SEMIHOST 16 /* semihosting call */ 59 #define EXCP_NOCP 17 /* v7M NOCP UsageFault */ 60 #define EXCP_INVSTATE 18 /* v7M INVSTATE UsageFault */ 61 /* NB: add new EXCP_ defines to the array in arm_log_exception() too */ 62 63 #define ARMV7M_EXCP_RESET 1 64 #define ARMV7M_EXCP_NMI 2 65 #define ARMV7M_EXCP_HARD 3 66 #define ARMV7M_EXCP_MEM 4 67 #define ARMV7M_EXCP_BUS 5 68 #define ARMV7M_EXCP_USAGE 6 69 #define ARMV7M_EXCP_SVC 11 70 #define ARMV7M_EXCP_DEBUG 12 71 #define ARMV7M_EXCP_PENDSV 14 72 #define ARMV7M_EXCP_SYSTICK 15 73 74 /* ARM-specific interrupt pending bits. */ 75 #define CPU_INTERRUPT_FIQ CPU_INTERRUPT_TGT_EXT_1 76 #define CPU_INTERRUPT_VIRQ CPU_INTERRUPT_TGT_EXT_2 77 #define CPU_INTERRUPT_VFIQ CPU_INTERRUPT_TGT_EXT_3 78 79 /* The usual mapping for an AArch64 system register to its AArch32 80 * counterpart is for the 32 bit world to have access to the lower 81 * half only (with writes leaving the upper half untouched). It's 82 * therefore useful to be able to pass TCG the offset of the least 83 * significant half of a uint64_t struct member. 84 */ 85 #ifdef HOST_WORDS_BIGENDIAN 86 #define offsetoflow32(S, M) (offsetof(S, M) + sizeof(uint32_t)) 87 #define offsetofhigh32(S, M) offsetof(S, M) 88 #else 89 #define offsetoflow32(S, M) offsetof(S, M) 90 #define offsetofhigh32(S, M) (offsetof(S, M) + sizeof(uint32_t)) 91 #endif 92 93 /* Meanings of the ARMCPU object's four inbound GPIO lines */ 94 #define ARM_CPU_IRQ 0 95 #define ARM_CPU_FIQ 1 96 #define ARM_CPU_VIRQ 2 97 #define ARM_CPU_VFIQ 3 98 99 #define NB_MMU_MODES 7 100 /* ARM-specific extra insn start words: 101 * 1: Conditional execution bits 102 * 2: Partial exception syndrome for data aborts 103 */ 104 #define TARGET_INSN_START_EXTRA_WORDS 2 105 106 /* The 2nd extra word holding syndrome info for data aborts does not use 107 * the upper 6 bits nor the lower 14 bits. We mask and shift it down to 108 * help the sleb128 encoder do a better job. 109 * When restoring the CPU state, we shift it back up. 110 */ 111 #define ARM_INSN_START_WORD2_MASK ((1 << 26) - 1) 112 #define ARM_INSN_START_WORD2_SHIFT 14 113 114 /* We currently assume float and double are IEEE single and double 115 precision respectively. 116 Doing runtime conversions is tricky because VFP registers may contain 117 integer values (eg. as the result of a FTOSI instruction). 118 s<2n> maps to the least significant half of d<n> 119 s<2n+1> maps to the most significant half of d<n> 120 */ 121 122 /* CPU state for each instance of a generic timer (in cp15 c14) */ 123 typedef struct ARMGenericTimer { 124 uint64_t cval; /* Timer CompareValue register */ 125 uint64_t ctl; /* Timer Control register */ 126 } ARMGenericTimer; 127 128 #define GTIMER_PHYS 0 129 #define GTIMER_VIRT 1 130 #define GTIMER_HYP 2 131 #define GTIMER_SEC 3 132 #define NUM_GTIMERS 4 133 134 typedef struct { 135 uint64_t raw_tcr; 136 uint32_t mask; 137 uint32_t base_mask; 138 } TCR; 139 140 typedef struct CPUARMState { 141 /* Regs for current mode. */ 142 uint32_t regs[16]; 143 144 /* 32/64 switch only happens when taking and returning from 145 * exceptions so the overlap semantics are taken care of then 146 * instead of having a complicated union. 147 */ 148 /* Regs for A64 mode. */ 149 uint64_t xregs[32]; 150 uint64_t pc; 151 /* PSTATE isn't an architectural register for ARMv8. However, it is 152 * convenient for us to assemble the underlying state into a 32 bit format 153 * identical to the architectural format used for the SPSR. (This is also 154 * what the Linux kernel's 'pstate' field in signal handlers and KVM's 155 * 'pstate' register are.) Of the PSTATE bits: 156 * NZCV are kept in the split out env->CF/VF/NF/ZF, (which have the same 157 * semantics as for AArch32, as described in the comments on each field) 158 * nRW (also known as M[4]) is kept, inverted, in env->aarch64 159 * DAIF (exception masks) are kept in env->daif 160 * all other bits are stored in their correct places in env->pstate 161 */ 162 uint32_t pstate; 163 uint32_t aarch64; /* 1 if CPU is in aarch64 state; inverse of PSTATE.nRW */ 164 165 /* Frequently accessed CPSR bits are stored separately for efficiency. 166 This contains all the other bits. Use cpsr_{read,write} to access 167 the whole CPSR. */ 168 uint32_t uncached_cpsr; 169 uint32_t spsr; 170 171 /* Banked registers. */ 172 uint64_t banked_spsr[8]; 173 uint32_t banked_r13[8]; 174 uint32_t banked_r14[8]; 175 176 /* These hold r8-r12. */ 177 uint32_t usr_regs[5]; 178 uint32_t fiq_regs[5]; 179 180 /* cpsr flag cache for faster execution */ 181 uint32_t CF; /* 0 or 1 */ 182 uint32_t VF; /* V is the bit 31. All other bits are undefined */ 183 uint32_t NF; /* N is bit 31. All other bits are undefined. */ 184 uint32_t ZF; /* Z set if zero. */ 185 uint32_t QF; /* 0 or 1 */ 186 uint32_t GE; /* cpsr[19:16] */ 187 uint32_t thumb; /* cpsr[5]. 0 = arm mode, 1 = thumb mode. */ 188 uint32_t condexec_bits; /* IT bits. cpsr[15:10,26:25]. */ 189 uint64_t daif; /* exception masks, in the bits they are in PSTATE */ 190 191 uint64_t elr_el[4]; /* AArch64 exception link regs */ 192 uint64_t sp_el[4]; /* AArch64 banked stack pointers */ 193 194 /* System control coprocessor (cp15) */ 195 struct { 196 uint32_t c0_cpuid; 197 union { /* Cache size selection */ 198 struct { 199 uint64_t _unused_csselr0; 200 uint64_t csselr_ns; 201 uint64_t _unused_csselr1; 202 uint64_t csselr_s; 203 }; 204 uint64_t csselr_el[4]; 205 }; 206 union { /* System control register. */ 207 struct { 208 uint64_t _unused_sctlr; 209 uint64_t sctlr_ns; 210 uint64_t hsctlr; 211 uint64_t sctlr_s; 212 }; 213 uint64_t sctlr_el[4]; 214 }; 215 uint64_t cpacr_el1; /* Architectural feature access control register */ 216 uint64_t cptr_el[4]; /* ARMv8 feature trap registers */ 217 uint32_t c1_xscaleauxcr; /* XScale auxiliary control register. */ 218 uint64_t sder; /* Secure debug enable register. */ 219 uint32_t nsacr; /* Non-secure access control register. */ 220 union { /* MMU translation table base 0. */ 221 struct { 222 uint64_t _unused_ttbr0_0; 223 uint64_t ttbr0_ns; 224 uint64_t _unused_ttbr0_1; 225 uint64_t ttbr0_s; 226 }; 227 uint64_t ttbr0_el[4]; 228 }; 229 union { /* MMU translation table base 1. */ 230 struct { 231 uint64_t _unused_ttbr1_0; 232 uint64_t ttbr1_ns; 233 uint64_t _unused_ttbr1_1; 234 uint64_t ttbr1_s; 235 }; 236 uint64_t ttbr1_el[4]; 237 }; 238 uint64_t vttbr_el2; /* Virtualization Translation Table Base. */ 239 /* MMU translation table base control. */ 240 TCR tcr_el[4]; 241 TCR vtcr_el2; /* Virtualization Translation Control. */ 242 uint32_t c2_data; /* MPU data cacheable bits. */ 243 uint32_t c2_insn; /* MPU instruction cacheable bits. */ 244 union { /* MMU domain access control register 245 * MPU write buffer control. 246 */ 247 struct { 248 uint64_t dacr_ns; 249 uint64_t dacr_s; 250 }; 251 struct { 252 uint64_t dacr32_el2; 253 }; 254 }; 255 uint32_t pmsav5_data_ap; /* PMSAv5 MPU data access permissions */ 256 uint32_t pmsav5_insn_ap; /* PMSAv5 MPU insn access permissions */ 257 uint64_t hcr_el2; /* Hypervisor configuration register */ 258 uint64_t scr_el3; /* Secure configuration register. */ 259 union { /* Fault status registers. */ 260 struct { 261 uint64_t ifsr_ns; 262 uint64_t ifsr_s; 263 }; 264 struct { 265 uint64_t ifsr32_el2; 266 }; 267 }; 268 union { 269 struct { 270 uint64_t _unused_dfsr; 271 uint64_t dfsr_ns; 272 uint64_t hsr; 273 uint64_t dfsr_s; 274 }; 275 uint64_t esr_el[4]; 276 }; 277 uint32_t c6_region[8]; /* MPU base/size registers. */ 278 union { /* Fault address registers. */ 279 struct { 280 uint64_t _unused_far0; 281 #ifdef HOST_WORDS_BIGENDIAN 282 uint32_t ifar_ns; 283 uint32_t dfar_ns; 284 uint32_t ifar_s; 285 uint32_t dfar_s; 286 #else 287 uint32_t dfar_ns; 288 uint32_t ifar_ns; 289 uint32_t dfar_s; 290 uint32_t ifar_s; 291 #endif 292 uint64_t _unused_far3; 293 }; 294 uint64_t far_el[4]; 295 }; 296 uint64_t hpfar_el2; 297 uint64_t hstr_el2; 298 union { /* Translation result. */ 299 struct { 300 uint64_t _unused_par_0; 301 uint64_t par_ns; 302 uint64_t _unused_par_1; 303 uint64_t par_s; 304 }; 305 uint64_t par_el[4]; 306 }; 307 308 uint32_t c9_insn; /* Cache lockdown registers. */ 309 uint32_t c9_data; 310 uint64_t c9_pmcr; /* performance monitor control register */ 311 uint64_t c9_pmcnten; /* perf monitor counter enables */ 312 uint32_t c9_pmovsr; /* perf monitor overflow status */ 313 uint32_t c9_pmuserenr; /* perf monitor user enable */ 314 uint64_t c9_pmselr; /* perf monitor counter selection register */ 315 uint64_t c9_pminten; /* perf monitor interrupt enables */ 316 union { /* Memory attribute redirection */ 317 struct { 318 #ifdef HOST_WORDS_BIGENDIAN 319 uint64_t _unused_mair_0; 320 uint32_t mair1_ns; 321 uint32_t mair0_ns; 322 uint64_t _unused_mair_1; 323 uint32_t mair1_s; 324 uint32_t mair0_s; 325 #else 326 uint64_t _unused_mair_0; 327 uint32_t mair0_ns; 328 uint32_t mair1_ns; 329 uint64_t _unused_mair_1; 330 uint32_t mair0_s; 331 uint32_t mair1_s; 332 #endif 333 }; 334 uint64_t mair_el[4]; 335 }; 336 union { /* vector base address register */ 337 struct { 338 uint64_t _unused_vbar; 339 uint64_t vbar_ns; 340 uint64_t hvbar; 341 uint64_t vbar_s; 342 }; 343 uint64_t vbar_el[4]; 344 }; 345 uint32_t mvbar; /* (monitor) vector base address register */ 346 struct { /* FCSE PID. */ 347 uint32_t fcseidr_ns; 348 uint32_t fcseidr_s; 349 }; 350 union { /* Context ID. */ 351 struct { 352 uint64_t _unused_contextidr_0; 353 uint64_t contextidr_ns; 354 uint64_t _unused_contextidr_1; 355 uint64_t contextidr_s; 356 }; 357 uint64_t contextidr_el[4]; 358 }; 359 union { /* User RW Thread register. */ 360 struct { 361 uint64_t tpidrurw_ns; 362 uint64_t tpidrprw_ns; 363 uint64_t htpidr; 364 uint64_t _tpidr_el3; 365 }; 366 uint64_t tpidr_el[4]; 367 }; 368 /* The secure banks of these registers don't map anywhere */ 369 uint64_t tpidrurw_s; 370 uint64_t tpidrprw_s; 371 uint64_t tpidruro_s; 372 373 union { /* User RO Thread register. */ 374 uint64_t tpidruro_ns; 375 uint64_t tpidrro_el[1]; 376 }; 377 uint64_t c14_cntfrq; /* Counter Frequency register */ 378 uint64_t c14_cntkctl; /* Timer Control register */ 379 uint32_t cnthctl_el2; /* Counter/Timer Hyp Control register */ 380 uint64_t cntvoff_el2; /* Counter Virtual Offset register */ 381 ARMGenericTimer c14_timer[NUM_GTIMERS]; 382 uint32_t c15_cpar; /* XScale Coprocessor Access Register */ 383 uint32_t c15_ticonfig; /* TI925T configuration byte. */ 384 uint32_t c15_i_max; /* Maximum D-cache dirty line index. */ 385 uint32_t c15_i_min; /* Minimum D-cache dirty line index. */ 386 uint32_t c15_threadid; /* TI debugger thread-ID. */ 387 uint32_t c15_config_base_address; /* SCU base address. */ 388 uint32_t c15_diagnostic; /* diagnostic register */ 389 uint32_t c15_power_diagnostic; 390 uint32_t c15_power_control; /* power control */ 391 uint64_t dbgbvr[16]; /* breakpoint value registers */ 392 uint64_t dbgbcr[16]; /* breakpoint control registers */ 393 uint64_t dbgwvr[16]; /* watchpoint value registers */ 394 uint64_t dbgwcr[16]; /* watchpoint control registers */ 395 uint64_t mdscr_el1; 396 uint64_t oslsr_el1; /* OS Lock Status */ 397 uint64_t mdcr_el2; 398 uint64_t mdcr_el3; 399 /* If the counter is enabled, this stores the last time the counter 400 * was reset. Otherwise it stores the counter value 401 */ 402 uint64_t c15_ccnt; 403 uint64_t pmccfiltr_el0; /* Performance Monitor Filter Register */ 404 uint64_t vpidr_el2; /* Virtualization Processor ID Register */ 405 uint64_t vmpidr_el2; /* Virtualization Multiprocessor ID Register */ 406 } cp15; 407 408 struct { 409 uint32_t other_sp; 410 uint32_t vecbase; 411 uint32_t basepri; 412 uint32_t control; 413 uint32_t ccr; /* Configuration and Control */ 414 uint32_t cfsr; /* Configurable Fault Status */ 415 uint32_t hfsr; /* HardFault Status */ 416 uint32_t dfsr; /* Debug Fault Status Register */ 417 uint32_t mmfar; /* MemManage Fault Address */ 418 uint32_t bfar; /* BusFault Address */ 419 unsigned mpu_ctrl; /* MPU_CTRL */ 420 int exception; 421 uint32_t primask; 422 uint32_t faultmask; 423 } v7m; 424 425 /* Information associated with an exception about to be taken: 426 * code which raises an exception must set cs->exception_index and 427 * the relevant parts of this structure; the cpu_do_interrupt function 428 * will then set the guest-visible registers as part of the exception 429 * entry process. 430 */ 431 struct { 432 uint32_t syndrome; /* AArch64 format syndrome register */ 433 uint32_t fsr; /* AArch32 format fault status register info */ 434 uint64_t vaddress; /* virtual addr associated with exception, if any */ 435 uint32_t target_el; /* EL the exception should be targeted for */ 436 /* If we implement EL2 we will also need to store information 437 * about the intermediate physical address for stage 2 faults. 438 */ 439 } exception; 440 441 /* Thumb-2 EE state. */ 442 uint32_t teecr; 443 uint32_t teehbr; 444 445 /* VFP coprocessor state. */ 446 struct { 447 /* VFP/Neon register state. Note that the mapping between S, D and Q 448 * views of the register bank differs between AArch64 and AArch32: 449 * In AArch32: 450 * Qn = regs[2n+1]:regs[2n] 451 * Dn = regs[n] 452 * Sn = regs[n/2] bits 31..0 for even n, and bits 63..32 for odd n 453 * (and regs[32] to regs[63] are inaccessible) 454 * In AArch64: 455 * Qn = regs[2n+1]:regs[2n] 456 * Dn = regs[2n] 457 * Sn = regs[2n] bits 31..0 458 * This corresponds to the architecturally defined mapping between 459 * the two execution states, and means we do not need to explicitly 460 * map these registers when changing states. 461 */ 462 float64 regs[64]; 463 464 uint32_t xregs[16]; 465 /* We store these fpcsr fields separately for convenience. */ 466 int vec_len; 467 int vec_stride; 468 469 /* scratch space when Tn are not sufficient. */ 470 uint32_t scratch[8]; 471 472 /* fp_status is the "normal" fp status. standard_fp_status retains 473 * values corresponding to the ARM "Standard FPSCR Value", ie 474 * default-NaN, flush-to-zero, round-to-nearest and is used by 475 * any operations (generally Neon) which the architecture defines 476 * as controlled by the standard FPSCR value rather than the FPSCR. 477 * 478 * To avoid having to transfer exception bits around, we simply 479 * say that the FPSCR cumulative exception flags are the logical 480 * OR of the flags in the two fp statuses. This relies on the 481 * only thing which needs to read the exception flags being 482 * an explicit FPSCR read. 483 */ 484 float_status fp_status; 485 float_status standard_fp_status; 486 } vfp; 487 uint64_t exclusive_addr; 488 uint64_t exclusive_val; 489 uint64_t exclusive_high; 490 491 /* iwMMXt coprocessor state. */ 492 struct { 493 uint64_t regs[16]; 494 uint64_t val; 495 496 uint32_t cregs[16]; 497 } iwmmxt; 498 499 #if defined(CONFIG_USER_ONLY) 500 /* For usermode syscall translation. */ 501 int eabi; 502 #endif 503 504 struct CPUBreakpoint *cpu_breakpoint[16]; 505 struct CPUWatchpoint *cpu_watchpoint[16]; 506 507 /* Fields up to this point are cleared by a CPU reset */ 508 struct {} end_reset_fields; 509 510 CPU_COMMON 511 512 /* Fields after CPU_COMMON are preserved across CPU reset. */ 513 514 /* Internal CPU feature flags. */ 515 uint64_t features; 516 517 /* PMSAv7 MPU */ 518 struct { 519 uint32_t *drbar; 520 uint32_t *drsr; 521 uint32_t *dracr; 522 uint32_t rnr; 523 } pmsav7; 524 525 /* PMSAv8 MPU */ 526 struct { 527 /* The PMSAv8 implementation also shares some PMSAv7 config 528 * and state: 529 * pmsav7.rnr (region number register) 530 * pmsav7_dregion (number of configured regions) 531 */ 532 uint32_t *rbar; 533 uint32_t *rlar; 534 uint32_t mair0; 535 uint32_t mair1; 536 } pmsav8; 537 538 void *nvic; 539 const struct arm_boot_info *boot_info; 540 /* Store GICv3CPUState to access from this struct */ 541 void *gicv3state; 542 } CPUARMState; 543 544 /** 545 * ARMELChangeHook: 546 * type of a function which can be registered via arm_register_el_change_hook() 547 * to get callbacks when the CPU changes its exception level or mode. 548 */ 549 typedef void ARMELChangeHook(ARMCPU *cpu, void *opaque); 550 551 552 /* These values map onto the return values for 553 * QEMU_PSCI_0_2_FN_AFFINITY_INFO */ 554 typedef enum ARMPSCIState { 555 PSCI_ON = 0, 556 PSCI_OFF = 1, 557 PSCI_ON_PENDING = 2 558 } ARMPSCIState; 559 560 /** 561 * ARMCPU: 562 * @env: #CPUARMState 563 * 564 * An ARM CPU core. 565 */ 566 struct ARMCPU { 567 /*< private >*/ 568 CPUState parent_obj; 569 /*< public >*/ 570 571 CPUARMState env; 572 573 /* Coprocessor information */ 574 GHashTable *cp_regs; 575 /* For marshalling (mostly coprocessor) register state between the 576 * kernel and QEMU (for KVM) and between two QEMUs (for migration), 577 * we use these arrays. 578 */ 579 /* List of register indexes managed via these arrays; (full KVM style 580 * 64 bit indexes, not CPRegInfo 32 bit indexes) 581 */ 582 uint64_t *cpreg_indexes; 583 /* Values of the registers (cpreg_indexes[i]'s value is cpreg_values[i]) */ 584 uint64_t *cpreg_values; 585 /* Length of the indexes, values, reset_values arrays */ 586 int32_t cpreg_array_len; 587 /* These are used only for migration: incoming data arrives in 588 * these fields and is sanity checked in post_load before copying 589 * to the working data structures above. 590 */ 591 uint64_t *cpreg_vmstate_indexes; 592 uint64_t *cpreg_vmstate_values; 593 int32_t cpreg_vmstate_array_len; 594 595 /* Timers used by the generic (architected) timer */ 596 QEMUTimer *gt_timer[NUM_GTIMERS]; 597 /* GPIO outputs for generic timer */ 598 qemu_irq gt_timer_outputs[NUM_GTIMERS]; 599 /* GPIO output for GICv3 maintenance interrupt signal */ 600 qemu_irq gicv3_maintenance_interrupt; 601 /* GPIO output for the PMU interrupt */ 602 qemu_irq pmu_interrupt; 603 604 /* MemoryRegion to use for secure physical accesses */ 605 MemoryRegion *secure_memory; 606 607 /* 'compatible' string for this CPU for Linux device trees */ 608 const char *dtb_compatible; 609 610 /* PSCI version for this CPU 611 * Bits[31:16] = Major Version 612 * Bits[15:0] = Minor Version 613 */ 614 uint32_t psci_version; 615 616 /* Should CPU start in PSCI powered-off state? */ 617 bool start_powered_off; 618 619 /* Current power state, access guarded by BQL */ 620 ARMPSCIState power_state; 621 622 /* CPU has virtualization extension */ 623 bool has_el2; 624 /* CPU has security extension */ 625 bool has_el3; 626 /* CPU has PMU (Performance Monitor Unit) */ 627 bool has_pmu; 628 629 /* CPU has memory protection unit */ 630 bool has_mpu; 631 /* PMSAv7 MPU number of supported regions */ 632 uint32_t pmsav7_dregion; 633 634 /* PSCI conduit used to invoke PSCI methods 635 * 0 - disabled, 1 - smc, 2 - hvc 636 */ 637 uint32_t psci_conduit; 638 639 /* [QEMU_]KVM_ARM_TARGET_* constant for this CPU, or 640 * QEMU_KVM_ARM_TARGET_NONE if the kernel doesn't support this CPU type. 641 */ 642 uint32_t kvm_target; 643 644 /* KVM init features for this CPU */ 645 uint32_t kvm_init_features[7]; 646 647 /* Uniprocessor system with MP extensions */ 648 bool mp_is_up; 649 650 /* The instance init functions for implementation-specific subclasses 651 * set these fields to specify the implementation-dependent values of 652 * various constant registers and reset values of non-constant 653 * registers. 654 * Some of these might become QOM properties eventually. 655 * Field names match the official register names as defined in the 656 * ARMv7AR ARM Architecture Reference Manual. A reset_ prefix 657 * is used for reset values of non-constant registers; no reset_ 658 * prefix means a constant register. 659 */ 660 uint32_t midr; 661 uint32_t revidr; 662 uint32_t reset_fpsid; 663 uint32_t mvfr0; 664 uint32_t mvfr1; 665 uint32_t mvfr2; 666 uint32_t ctr; 667 uint32_t reset_sctlr; 668 uint32_t id_pfr0; 669 uint32_t id_pfr1; 670 uint32_t id_dfr0; 671 uint32_t pmceid0; 672 uint32_t pmceid1; 673 uint32_t id_afr0; 674 uint32_t id_mmfr0; 675 uint32_t id_mmfr1; 676 uint32_t id_mmfr2; 677 uint32_t id_mmfr3; 678 uint32_t id_mmfr4; 679 uint32_t id_isar0; 680 uint32_t id_isar1; 681 uint32_t id_isar2; 682 uint32_t id_isar3; 683 uint32_t id_isar4; 684 uint32_t id_isar5; 685 uint64_t id_aa64pfr0; 686 uint64_t id_aa64pfr1; 687 uint64_t id_aa64dfr0; 688 uint64_t id_aa64dfr1; 689 uint64_t id_aa64afr0; 690 uint64_t id_aa64afr1; 691 uint64_t id_aa64isar0; 692 uint64_t id_aa64isar1; 693 uint64_t id_aa64mmfr0; 694 uint64_t id_aa64mmfr1; 695 uint32_t dbgdidr; 696 uint32_t clidr; 697 uint64_t mp_affinity; /* MP ID without feature bits */ 698 /* The elements of this array are the CCSIDR values for each cache, 699 * in the order L1DCache, L1ICache, L2DCache, L2ICache, etc. 700 */ 701 uint32_t ccsidr[16]; 702 uint64_t reset_cbar; 703 uint32_t reset_auxcr; 704 bool reset_hivecs; 705 /* DCZ blocksize, in log_2(words), ie low 4 bits of DCZID_EL0 */ 706 uint32_t dcz_blocksize; 707 uint64_t rvbar; 708 709 /* Configurable aspects of GIC cpu interface (which is part of the CPU) */ 710 int gic_num_lrs; /* number of list registers */ 711 int gic_vpribits; /* number of virtual priority bits */ 712 int gic_vprebits; /* number of virtual preemption bits */ 713 714 /* Whether the cfgend input is high (i.e. this CPU should reset into 715 * big-endian mode). This setting isn't used directly: instead it modifies 716 * the reset_sctlr value to have SCTLR_B or SCTLR_EE set, depending on the 717 * architecture version. 718 */ 719 bool cfgend; 720 721 ARMELChangeHook *el_change_hook; 722 void *el_change_hook_opaque; 723 724 int32_t node_id; /* NUMA node this CPU belongs to */ 725 726 /* Used to synchronize KVM and QEMU in-kernel device levels */ 727 uint8_t device_irq_level; 728 }; 729 730 static inline ARMCPU *arm_env_get_cpu(CPUARMState *env) 731 { 732 return container_of(env, ARMCPU, env); 733 } 734 735 uint64_t arm_cpu_mp_affinity(int idx, uint8_t clustersz); 736 737 #define ENV_GET_CPU(e) CPU(arm_env_get_cpu(e)) 738 739 #define ENV_OFFSET offsetof(ARMCPU, env) 740 741 #ifndef CONFIG_USER_ONLY 742 extern const struct VMStateDescription vmstate_arm_cpu; 743 #endif 744 745 void arm_cpu_do_interrupt(CPUState *cpu); 746 void arm_v7m_cpu_do_interrupt(CPUState *cpu); 747 bool arm_cpu_exec_interrupt(CPUState *cpu, int int_req); 748 749 void arm_cpu_dump_state(CPUState *cs, FILE *f, fprintf_function cpu_fprintf, 750 int flags); 751 752 hwaddr arm_cpu_get_phys_page_attrs_debug(CPUState *cpu, vaddr addr, 753 MemTxAttrs *attrs); 754 755 int arm_cpu_gdb_read_register(CPUState *cpu, uint8_t *buf, int reg); 756 int arm_cpu_gdb_write_register(CPUState *cpu, uint8_t *buf, int reg); 757 758 int arm_cpu_write_elf64_note(WriteCoreDumpFunction f, CPUState *cs, 759 int cpuid, void *opaque); 760 int arm_cpu_write_elf32_note(WriteCoreDumpFunction f, CPUState *cs, 761 int cpuid, void *opaque); 762 763 #ifdef TARGET_AARCH64 764 int aarch64_cpu_gdb_read_register(CPUState *cpu, uint8_t *buf, int reg); 765 int aarch64_cpu_gdb_write_register(CPUState *cpu, uint8_t *buf, int reg); 766 #endif 767 768 target_ulong do_arm_semihosting(CPUARMState *env); 769 void aarch64_sync_32_to_64(CPUARMState *env); 770 void aarch64_sync_64_to_32(CPUARMState *env); 771 772 static inline bool is_a64(CPUARMState *env) 773 { 774 return env->aarch64; 775 } 776 777 /* you can call this signal handler from your SIGBUS and SIGSEGV 778 signal handlers to inform the virtual CPU of exceptions. non zero 779 is returned if the signal was handled by the virtual CPU. */ 780 int cpu_arm_signal_handler(int host_signum, void *pinfo, 781 void *puc); 782 783 /** 784 * pmccntr_sync 785 * @env: CPUARMState 786 * 787 * Synchronises the counter in the PMCCNTR. This must always be called twice, 788 * once before any action that might affect the timer and again afterwards. 789 * The function is used to swap the state of the register if required. 790 * This only happens when not in user mode (!CONFIG_USER_ONLY) 791 */ 792 void pmccntr_sync(CPUARMState *env); 793 794 /* SCTLR bit meanings. Several bits have been reused in newer 795 * versions of the architecture; in that case we define constants 796 * for both old and new bit meanings. Code which tests against those 797 * bits should probably check or otherwise arrange that the CPU 798 * is the architectural version it expects. 799 */ 800 #define SCTLR_M (1U << 0) 801 #define SCTLR_A (1U << 1) 802 #define SCTLR_C (1U << 2) 803 #define SCTLR_W (1U << 3) /* up to v6; RAO in v7 */ 804 #define SCTLR_SA (1U << 3) 805 #define SCTLR_P (1U << 4) /* up to v5; RAO in v6 and v7 */ 806 #define SCTLR_SA0 (1U << 4) /* v8 onward, AArch64 only */ 807 #define SCTLR_D (1U << 5) /* up to v5; RAO in v6 */ 808 #define SCTLR_CP15BEN (1U << 5) /* v7 onward */ 809 #define SCTLR_L (1U << 6) /* up to v5; RAO in v6 and v7; RAZ in v8 */ 810 #define SCTLR_B (1U << 7) /* up to v6; RAZ in v7 */ 811 #define SCTLR_ITD (1U << 7) /* v8 onward */ 812 #define SCTLR_S (1U << 8) /* up to v6; RAZ in v7 */ 813 #define SCTLR_SED (1U << 8) /* v8 onward */ 814 #define SCTLR_R (1U << 9) /* up to v6; RAZ in v7 */ 815 #define SCTLR_UMA (1U << 9) /* v8 onward, AArch64 only */ 816 #define SCTLR_F (1U << 10) /* up to v6 */ 817 #define SCTLR_SW (1U << 10) /* v7 onward */ 818 #define SCTLR_Z (1U << 11) 819 #define SCTLR_I (1U << 12) 820 #define SCTLR_V (1U << 13) 821 #define SCTLR_RR (1U << 14) /* up to v7 */ 822 #define SCTLR_DZE (1U << 14) /* v8 onward, AArch64 only */ 823 #define SCTLR_L4 (1U << 15) /* up to v6; RAZ in v7 */ 824 #define SCTLR_UCT (1U << 15) /* v8 onward, AArch64 only */ 825 #define SCTLR_DT (1U << 16) /* up to ??, RAO in v6 and v7 */ 826 #define SCTLR_nTWI (1U << 16) /* v8 onward */ 827 #define SCTLR_HA (1U << 17) 828 #define SCTLR_BR (1U << 17) /* PMSA only */ 829 #define SCTLR_IT (1U << 18) /* up to ??, RAO in v6 and v7 */ 830 #define SCTLR_nTWE (1U << 18) /* v8 onward */ 831 #define SCTLR_WXN (1U << 19) 832 #define SCTLR_ST (1U << 20) /* up to ??, RAZ in v6 */ 833 #define SCTLR_UWXN (1U << 20) /* v7 onward */ 834 #define SCTLR_FI (1U << 21) 835 #define SCTLR_U (1U << 22) 836 #define SCTLR_XP (1U << 23) /* up to v6; v7 onward RAO */ 837 #define SCTLR_VE (1U << 24) /* up to v7 */ 838 #define SCTLR_E0E (1U << 24) /* v8 onward, AArch64 only */ 839 #define SCTLR_EE (1U << 25) 840 #define SCTLR_L2 (1U << 26) /* up to v6, RAZ in v7 */ 841 #define SCTLR_UCI (1U << 26) /* v8 onward, AArch64 only */ 842 #define SCTLR_NMFI (1U << 27) 843 #define SCTLR_TRE (1U << 28) 844 #define SCTLR_AFE (1U << 29) 845 #define SCTLR_TE (1U << 30) 846 847 #define CPTR_TCPAC (1U << 31) 848 #define CPTR_TTA (1U << 20) 849 #define CPTR_TFP (1U << 10) 850 851 #define MDCR_EPMAD (1U << 21) 852 #define MDCR_EDAD (1U << 20) 853 #define MDCR_SPME (1U << 17) 854 #define MDCR_SDD (1U << 16) 855 #define MDCR_SPD (3U << 14) 856 #define MDCR_TDRA (1U << 11) 857 #define MDCR_TDOSA (1U << 10) 858 #define MDCR_TDA (1U << 9) 859 #define MDCR_TDE (1U << 8) 860 #define MDCR_HPME (1U << 7) 861 #define MDCR_TPM (1U << 6) 862 #define MDCR_TPMCR (1U << 5) 863 864 /* Not all of the MDCR_EL3 bits are present in the 32-bit SDCR */ 865 #define SDCR_VALID_MASK (MDCR_EPMAD | MDCR_EDAD | MDCR_SPME | MDCR_SPD) 866 867 #define CPSR_M (0x1fU) 868 #define CPSR_T (1U << 5) 869 #define CPSR_F (1U << 6) 870 #define CPSR_I (1U << 7) 871 #define CPSR_A (1U << 8) 872 #define CPSR_E (1U << 9) 873 #define CPSR_IT_2_7 (0xfc00U) 874 #define CPSR_GE (0xfU << 16) 875 #define CPSR_IL (1U << 20) 876 /* Note that the RESERVED bits include bit 21, which is PSTATE_SS in 877 * an AArch64 SPSR but RES0 in AArch32 SPSR and CPSR. In QEMU we use 878 * env->uncached_cpsr bit 21 to store PSTATE.SS when executing in AArch32, 879 * where it is live state but not accessible to the AArch32 code. 880 */ 881 #define CPSR_RESERVED (0x7U << 21) 882 #define CPSR_J (1U << 24) 883 #define CPSR_IT_0_1 (3U << 25) 884 #define CPSR_Q (1U << 27) 885 #define CPSR_V (1U << 28) 886 #define CPSR_C (1U << 29) 887 #define CPSR_Z (1U << 30) 888 #define CPSR_N (1U << 31) 889 #define CPSR_NZCV (CPSR_N | CPSR_Z | CPSR_C | CPSR_V) 890 #define CPSR_AIF (CPSR_A | CPSR_I | CPSR_F) 891 892 #define CPSR_IT (CPSR_IT_0_1 | CPSR_IT_2_7) 893 #define CACHED_CPSR_BITS (CPSR_T | CPSR_AIF | CPSR_GE | CPSR_IT | CPSR_Q \ 894 | CPSR_NZCV) 895 /* Bits writable in user mode. */ 896 #define CPSR_USER (CPSR_NZCV | CPSR_Q | CPSR_GE) 897 /* Execution state bits. MRS read as zero, MSR writes ignored. */ 898 #define CPSR_EXEC (CPSR_T | CPSR_IT | CPSR_J | CPSR_IL) 899 /* Mask of bits which may be set by exception return copying them from SPSR */ 900 #define CPSR_ERET_MASK (~CPSR_RESERVED) 901 902 /* Bit definitions for M profile XPSR. Most are the same as CPSR. */ 903 #define XPSR_EXCP 0x1ffU 904 #define XPSR_SPREALIGN (1U << 9) /* Only set in exception stack frames */ 905 #define XPSR_IT_2_7 CPSR_IT_2_7 906 #define XPSR_GE CPSR_GE 907 #define XPSR_SFPA (1U << 20) /* Only set in exception stack frames */ 908 #define XPSR_T (1U << 24) /* Not the same as CPSR_T ! */ 909 #define XPSR_IT_0_1 CPSR_IT_0_1 910 #define XPSR_Q CPSR_Q 911 #define XPSR_V CPSR_V 912 #define XPSR_C CPSR_C 913 #define XPSR_Z CPSR_Z 914 #define XPSR_N CPSR_N 915 #define XPSR_NZCV CPSR_NZCV 916 #define XPSR_IT CPSR_IT 917 918 #define TTBCR_N (7U << 0) /* TTBCR.EAE==0 */ 919 #define TTBCR_T0SZ (7U << 0) /* TTBCR.EAE==1 */ 920 #define TTBCR_PD0 (1U << 4) 921 #define TTBCR_PD1 (1U << 5) 922 #define TTBCR_EPD0 (1U << 7) 923 #define TTBCR_IRGN0 (3U << 8) 924 #define TTBCR_ORGN0 (3U << 10) 925 #define TTBCR_SH0 (3U << 12) 926 #define TTBCR_T1SZ (3U << 16) 927 #define TTBCR_A1 (1U << 22) 928 #define TTBCR_EPD1 (1U << 23) 929 #define TTBCR_IRGN1 (3U << 24) 930 #define TTBCR_ORGN1 (3U << 26) 931 #define TTBCR_SH1 (1U << 28) 932 #define TTBCR_EAE (1U << 31) 933 934 /* Bit definitions for ARMv8 SPSR (PSTATE) format. 935 * Only these are valid when in AArch64 mode; in 936 * AArch32 mode SPSRs are basically CPSR-format. 937 */ 938 #define PSTATE_SP (1U) 939 #define PSTATE_M (0xFU) 940 #define PSTATE_nRW (1U << 4) 941 #define PSTATE_F (1U << 6) 942 #define PSTATE_I (1U << 7) 943 #define PSTATE_A (1U << 8) 944 #define PSTATE_D (1U << 9) 945 #define PSTATE_IL (1U << 20) 946 #define PSTATE_SS (1U << 21) 947 #define PSTATE_V (1U << 28) 948 #define PSTATE_C (1U << 29) 949 #define PSTATE_Z (1U << 30) 950 #define PSTATE_N (1U << 31) 951 #define PSTATE_NZCV (PSTATE_N | PSTATE_Z | PSTATE_C | PSTATE_V) 952 #define PSTATE_DAIF (PSTATE_D | PSTATE_A | PSTATE_I | PSTATE_F) 953 #define CACHED_PSTATE_BITS (PSTATE_NZCV | PSTATE_DAIF) 954 /* Mode values for AArch64 */ 955 #define PSTATE_MODE_EL3h 13 956 #define PSTATE_MODE_EL3t 12 957 #define PSTATE_MODE_EL2h 9 958 #define PSTATE_MODE_EL2t 8 959 #define PSTATE_MODE_EL1h 5 960 #define PSTATE_MODE_EL1t 4 961 #define PSTATE_MODE_EL0t 0 962 963 /* Map EL and handler into a PSTATE_MODE. */ 964 static inline unsigned int aarch64_pstate_mode(unsigned int el, bool handler) 965 { 966 return (el << 2) | handler; 967 } 968 969 /* Return the current PSTATE value. For the moment we don't support 32<->64 bit 970 * interprocessing, so we don't attempt to sync with the cpsr state used by 971 * the 32 bit decoder. 972 */ 973 static inline uint32_t pstate_read(CPUARMState *env) 974 { 975 int ZF; 976 977 ZF = (env->ZF == 0); 978 return (env->NF & 0x80000000) | (ZF << 30) 979 | (env->CF << 29) | ((env->VF & 0x80000000) >> 3) 980 | env->pstate | env->daif; 981 } 982 983 static inline void pstate_write(CPUARMState *env, uint32_t val) 984 { 985 env->ZF = (~val) & PSTATE_Z; 986 env->NF = val; 987 env->CF = (val >> 29) & 1; 988 env->VF = (val << 3) & 0x80000000; 989 env->daif = val & PSTATE_DAIF; 990 env->pstate = val & ~CACHED_PSTATE_BITS; 991 } 992 993 /* Return the current CPSR value. */ 994 uint32_t cpsr_read(CPUARMState *env); 995 996 typedef enum CPSRWriteType { 997 CPSRWriteByInstr = 0, /* from guest MSR or CPS */ 998 CPSRWriteExceptionReturn = 1, /* from guest exception return insn */ 999 CPSRWriteRaw = 2, /* trust values, do not switch reg banks */ 1000 CPSRWriteByGDBStub = 3, /* from the GDB stub */ 1001 } CPSRWriteType; 1002 1003 /* Set the CPSR. Note that some bits of mask must be all-set or all-clear.*/ 1004 void cpsr_write(CPUARMState *env, uint32_t val, uint32_t mask, 1005 CPSRWriteType write_type); 1006 1007 /* Return the current xPSR value. */ 1008 static inline uint32_t xpsr_read(CPUARMState *env) 1009 { 1010 int ZF; 1011 ZF = (env->ZF == 0); 1012 return (env->NF & 0x80000000) | (ZF << 30) 1013 | (env->CF << 29) | ((env->VF & 0x80000000) >> 3) | (env->QF << 27) 1014 | (env->thumb << 24) | ((env->condexec_bits & 3) << 25) 1015 | ((env->condexec_bits & 0xfc) << 8) 1016 | env->v7m.exception; 1017 } 1018 1019 /* Set the xPSR. Note that some bits of mask must be all-set or all-clear. */ 1020 static inline void xpsr_write(CPUARMState *env, uint32_t val, uint32_t mask) 1021 { 1022 if (mask & XPSR_NZCV) { 1023 env->ZF = (~val) & XPSR_Z; 1024 env->NF = val; 1025 env->CF = (val >> 29) & 1; 1026 env->VF = (val << 3) & 0x80000000; 1027 } 1028 if (mask & XPSR_Q) { 1029 env->QF = ((val & XPSR_Q) != 0); 1030 } 1031 if (mask & XPSR_T) { 1032 env->thumb = ((val & XPSR_T) != 0); 1033 } 1034 if (mask & XPSR_IT_0_1) { 1035 env->condexec_bits &= ~3; 1036 env->condexec_bits |= (val >> 25) & 3; 1037 } 1038 if (mask & XPSR_IT_2_7) { 1039 env->condexec_bits &= 3; 1040 env->condexec_bits |= (val >> 8) & 0xfc; 1041 } 1042 if (mask & XPSR_EXCP) { 1043 env->v7m.exception = val & XPSR_EXCP; 1044 } 1045 } 1046 1047 #define HCR_VM (1ULL << 0) 1048 #define HCR_SWIO (1ULL << 1) 1049 #define HCR_PTW (1ULL << 2) 1050 #define HCR_FMO (1ULL << 3) 1051 #define HCR_IMO (1ULL << 4) 1052 #define HCR_AMO (1ULL << 5) 1053 #define HCR_VF (1ULL << 6) 1054 #define HCR_VI (1ULL << 7) 1055 #define HCR_VSE (1ULL << 8) 1056 #define HCR_FB (1ULL << 9) 1057 #define HCR_BSU_MASK (3ULL << 10) 1058 #define HCR_DC (1ULL << 12) 1059 #define HCR_TWI (1ULL << 13) 1060 #define HCR_TWE (1ULL << 14) 1061 #define HCR_TID0 (1ULL << 15) 1062 #define HCR_TID1 (1ULL << 16) 1063 #define HCR_TID2 (1ULL << 17) 1064 #define HCR_TID3 (1ULL << 18) 1065 #define HCR_TSC (1ULL << 19) 1066 #define HCR_TIDCP (1ULL << 20) 1067 #define HCR_TACR (1ULL << 21) 1068 #define HCR_TSW (1ULL << 22) 1069 #define HCR_TPC (1ULL << 23) 1070 #define HCR_TPU (1ULL << 24) 1071 #define HCR_TTLB (1ULL << 25) 1072 #define HCR_TVM (1ULL << 26) 1073 #define HCR_TGE (1ULL << 27) 1074 #define HCR_TDZ (1ULL << 28) 1075 #define HCR_HCD (1ULL << 29) 1076 #define HCR_TRVM (1ULL << 30) 1077 #define HCR_RW (1ULL << 31) 1078 #define HCR_CD (1ULL << 32) 1079 #define HCR_ID (1ULL << 33) 1080 #define HCR_MASK ((1ULL << 34) - 1) 1081 1082 #define SCR_NS (1U << 0) 1083 #define SCR_IRQ (1U << 1) 1084 #define SCR_FIQ (1U << 2) 1085 #define SCR_EA (1U << 3) 1086 #define SCR_FW (1U << 4) 1087 #define SCR_AW (1U << 5) 1088 #define SCR_NET (1U << 6) 1089 #define SCR_SMD (1U << 7) 1090 #define SCR_HCE (1U << 8) 1091 #define SCR_SIF (1U << 9) 1092 #define SCR_RW (1U << 10) 1093 #define SCR_ST (1U << 11) 1094 #define SCR_TWI (1U << 12) 1095 #define SCR_TWE (1U << 13) 1096 #define SCR_AARCH32_MASK (0x3fff & ~(SCR_RW | SCR_ST)) 1097 #define SCR_AARCH64_MASK (0x3fff & ~SCR_NET) 1098 1099 /* Return the current FPSCR value. */ 1100 uint32_t vfp_get_fpscr(CPUARMState *env); 1101 void vfp_set_fpscr(CPUARMState *env, uint32_t val); 1102 1103 /* For A64 the FPSCR is split into two logically distinct registers, 1104 * FPCR and FPSR. However since they still use non-overlapping bits 1105 * we store the underlying state in fpscr and just mask on read/write. 1106 */ 1107 #define FPSR_MASK 0xf800009f 1108 #define FPCR_MASK 0x07f79f00 1109 static inline uint32_t vfp_get_fpsr(CPUARMState *env) 1110 { 1111 return vfp_get_fpscr(env) & FPSR_MASK; 1112 } 1113 1114 static inline void vfp_set_fpsr(CPUARMState *env, uint32_t val) 1115 { 1116 uint32_t new_fpscr = (vfp_get_fpscr(env) & ~FPSR_MASK) | (val & FPSR_MASK); 1117 vfp_set_fpscr(env, new_fpscr); 1118 } 1119 1120 static inline uint32_t vfp_get_fpcr(CPUARMState *env) 1121 { 1122 return vfp_get_fpscr(env) & FPCR_MASK; 1123 } 1124 1125 static inline void vfp_set_fpcr(CPUARMState *env, uint32_t val) 1126 { 1127 uint32_t new_fpscr = (vfp_get_fpscr(env) & ~FPCR_MASK) | (val & FPCR_MASK); 1128 vfp_set_fpscr(env, new_fpscr); 1129 } 1130 1131 enum arm_cpu_mode { 1132 ARM_CPU_MODE_USR = 0x10, 1133 ARM_CPU_MODE_FIQ = 0x11, 1134 ARM_CPU_MODE_IRQ = 0x12, 1135 ARM_CPU_MODE_SVC = 0x13, 1136 ARM_CPU_MODE_MON = 0x16, 1137 ARM_CPU_MODE_ABT = 0x17, 1138 ARM_CPU_MODE_HYP = 0x1a, 1139 ARM_CPU_MODE_UND = 0x1b, 1140 ARM_CPU_MODE_SYS = 0x1f 1141 }; 1142 1143 /* VFP system registers. */ 1144 #define ARM_VFP_FPSID 0 1145 #define ARM_VFP_FPSCR 1 1146 #define ARM_VFP_MVFR2 5 1147 #define ARM_VFP_MVFR1 6 1148 #define ARM_VFP_MVFR0 7 1149 #define ARM_VFP_FPEXC 8 1150 #define ARM_VFP_FPINST 9 1151 #define ARM_VFP_FPINST2 10 1152 1153 /* iwMMXt coprocessor control registers. */ 1154 #define ARM_IWMMXT_wCID 0 1155 #define ARM_IWMMXT_wCon 1 1156 #define ARM_IWMMXT_wCSSF 2 1157 #define ARM_IWMMXT_wCASF 3 1158 #define ARM_IWMMXT_wCGR0 8 1159 #define ARM_IWMMXT_wCGR1 9 1160 #define ARM_IWMMXT_wCGR2 10 1161 #define ARM_IWMMXT_wCGR3 11 1162 1163 /* V7M CCR bits */ 1164 FIELD(V7M_CCR, NONBASETHRDENA, 0, 1) 1165 FIELD(V7M_CCR, USERSETMPEND, 1, 1) 1166 FIELD(V7M_CCR, UNALIGN_TRP, 3, 1) 1167 FIELD(V7M_CCR, DIV_0_TRP, 4, 1) 1168 FIELD(V7M_CCR, BFHFNMIGN, 8, 1) 1169 FIELD(V7M_CCR, STKALIGN, 9, 1) 1170 FIELD(V7M_CCR, DC, 16, 1) 1171 FIELD(V7M_CCR, IC, 17, 1) 1172 1173 /* V7M CFSR bits for MMFSR */ 1174 FIELD(V7M_CFSR, IACCVIOL, 0, 1) 1175 FIELD(V7M_CFSR, DACCVIOL, 1, 1) 1176 FIELD(V7M_CFSR, MUNSTKERR, 3, 1) 1177 FIELD(V7M_CFSR, MSTKERR, 4, 1) 1178 FIELD(V7M_CFSR, MLSPERR, 5, 1) 1179 FIELD(V7M_CFSR, MMARVALID, 7, 1) 1180 1181 /* V7M CFSR bits for BFSR */ 1182 FIELD(V7M_CFSR, IBUSERR, 8 + 0, 1) 1183 FIELD(V7M_CFSR, PRECISERR, 8 + 1, 1) 1184 FIELD(V7M_CFSR, IMPRECISERR, 8 + 2, 1) 1185 FIELD(V7M_CFSR, UNSTKERR, 8 + 3, 1) 1186 FIELD(V7M_CFSR, STKERR, 8 + 4, 1) 1187 FIELD(V7M_CFSR, LSPERR, 8 + 5, 1) 1188 FIELD(V7M_CFSR, BFARVALID, 8 + 7, 1) 1189 1190 /* V7M CFSR bits for UFSR */ 1191 FIELD(V7M_CFSR, UNDEFINSTR, 16 + 0, 1) 1192 FIELD(V7M_CFSR, INVSTATE, 16 + 1, 1) 1193 FIELD(V7M_CFSR, INVPC, 16 + 2, 1) 1194 FIELD(V7M_CFSR, NOCP, 16 + 3, 1) 1195 FIELD(V7M_CFSR, UNALIGNED, 16 + 8, 1) 1196 FIELD(V7M_CFSR, DIVBYZERO, 16 + 9, 1) 1197 1198 /* V7M HFSR bits */ 1199 FIELD(V7M_HFSR, VECTTBL, 1, 1) 1200 FIELD(V7M_HFSR, FORCED, 30, 1) 1201 FIELD(V7M_HFSR, DEBUGEVT, 31, 1) 1202 1203 /* V7M DFSR bits */ 1204 FIELD(V7M_DFSR, HALTED, 0, 1) 1205 FIELD(V7M_DFSR, BKPT, 1, 1) 1206 FIELD(V7M_DFSR, DWTTRAP, 2, 1) 1207 FIELD(V7M_DFSR, VCATCH, 3, 1) 1208 FIELD(V7M_DFSR, EXTERNAL, 4, 1) 1209 1210 /* v7M MPU_CTRL bits */ 1211 FIELD(V7M_MPU_CTRL, ENABLE, 0, 1) 1212 FIELD(V7M_MPU_CTRL, HFNMIENA, 1, 1) 1213 FIELD(V7M_MPU_CTRL, PRIVDEFENA, 2, 1) 1214 1215 /* If adding a feature bit which corresponds to a Linux ELF 1216 * HWCAP bit, remember to update the feature-bit-to-hwcap 1217 * mapping in linux-user/elfload.c:get_elf_hwcap(). 1218 */ 1219 enum arm_features { 1220 ARM_FEATURE_VFP, 1221 ARM_FEATURE_AUXCR, /* ARM1026 Auxiliary control register. */ 1222 ARM_FEATURE_XSCALE, /* Intel XScale extensions. */ 1223 ARM_FEATURE_IWMMXT, /* Intel iwMMXt extension. */ 1224 ARM_FEATURE_V6, 1225 ARM_FEATURE_V6K, 1226 ARM_FEATURE_V7, 1227 ARM_FEATURE_THUMB2, 1228 ARM_FEATURE_PMSA, /* no MMU; may have Memory Protection Unit */ 1229 ARM_FEATURE_VFP3, 1230 ARM_FEATURE_VFP_FP16, 1231 ARM_FEATURE_NEON, 1232 ARM_FEATURE_THUMB_DIV, /* divide supported in Thumb encoding */ 1233 ARM_FEATURE_M, /* Microcontroller profile. */ 1234 ARM_FEATURE_OMAPCP, /* OMAP specific CP15 ops handling. */ 1235 ARM_FEATURE_THUMB2EE, 1236 ARM_FEATURE_V7MP, /* v7 Multiprocessing Extensions */ 1237 ARM_FEATURE_V4T, 1238 ARM_FEATURE_V5, 1239 ARM_FEATURE_STRONGARM, 1240 ARM_FEATURE_VAPA, /* cp15 VA to PA lookups */ 1241 ARM_FEATURE_ARM_DIV, /* divide supported in ARM encoding */ 1242 ARM_FEATURE_VFP4, /* VFPv4 (implies that NEON is v2) */ 1243 ARM_FEATURE_GENERIC_TIMER, 1244 ARM_FEATURE_MVFR, /* Media and VFP Feature Registers 0 and 1 */ 1245 ARM_FEATURE_DUMMY_C15_REGS, /* RAZ/WI all of cp15 crn=15 */ 1246 ARM_FEATURE_CACHE_TEST_CLEAN, /* 926/1026 style test-and-clean ops */ 1247 ARM_FEATURE_CACHE_DIRTY_REG, /* 1136/1176 cache dirty status register */ 1248 ARM_FEATURE_CACHE_BLOCK_OPS, /* v6 optional cache block operations */ 1249 ARM_FEATURE_MPIDR, /* has cp15 MPIDR */ 1250 ARM_FEATURE_PXN, /* has Privileged Execute Never bit */ 1251 ARM_FEATURE_LPAE, /* has Large Physical Address Extension */ 1252 ARM_FEATURE_V8, 1253 ARM_FEATURE_AARCH64, /* supports 64 bit mode */ 1254 ARM_FEATURE_V8_AES, /* implements AES part of v8 Crypto Extensions */ 1255 ARM_FEATURE_CBAR, /* has cp15 CBAR */ 1256 ARM_FEATURE_CRC, /* ARMv8 CRC instructions */ 1257 ARM_FEATURE_CBAR_RO, /* has cp15 CBAR and it is read-only */ 1258 ARM_FEATURE_EL2, /* has EL2 Virtualization support */ 1259 ARM_FEATURE_EL3, /* has EL3 Secure monitor support */ 1260 ARM_FEATURE_V8_SHA1, /* implements SHA1 part of v8 Crypto Extensions */ 1261 ARM_FEATURE_V8_SHA256, /* implements SHA256 part of v8 Crypto Extensions */ 1262 ARM_FEATURE_V8_PMULL, /* implements PMULL part of v8 Crypto Extensions */ 1263 ARM_FEATURE_THUMB_DSP, /* DSP insns supported in the Thumb encodings */ 1264 ARM_FEATURE_PMU, /* has PMU support */ 1265 ARM_FEATURE_VBAR, /* has cp15 VBAR */ 1266 }; 1267 1268 static inline int arm_feature(CPUARMState *env, int feature) 1269 { 1270 return (env->features & (1ULL << feature)) != 0; 1271 } 1272 1273 #if !defined(CONFIG_USER_ONLY) 1274 /* Return true if exception levels below EL3 are in secure state, 1275 * or would be following an exception return to that level. 1276 * Unlike arm_is_secure() (which is always a question about the 1277 * _current_ state of the CPU) this doesn't care about the current 1278 * EL or mode. 1279 */ 1280 static inline bool arm_is_secure_below_el3(CPUARMState *env) 1281 { 1282 if (arm_feature(env, ARM_FEATURE_EL3)) { 1283 return !(env->cp15.scr_el3 & SCR_NS); 1284 } else { 1285 /* If EL3 is not supported then the secure state is implementation 1286 * defined, in which case QEMU defaults to non-secure. 1287 */ 1288 return false; 1289 } 1290 } 1291 1292 /* Return true if the CPU is AArch64 EL3 or AArch32 Mon */ 1293 static inline bool arm_is_el3_or_mon(CPUARMState *env) 1294 { 1295 if (arm_feature(env, ARM_FEATURE_EL3)) { 1296 if (is_a64(env) && extract32(env->pstate, 2, 2) == 3) { 1297 /* CPU currently in AArch64 state and EL3 */ 1298 return true; 1299 } else if (!is_a64(env) && 1300 (env->uncached_cpsr & CPSR_M) == ARM_CPU_MODE_MON) { 1301 /* CPU currently in AArch32 state and monitor mode */ 1302 return true; 1303 } 1304 } 1305 return false; 1306 } 1307 1308 /* Return true if the processor is in secure state */ 1309 static inline bool arm_is_secure(CPUARMState *env) 1310 { 1311 if (arm_is_el3_or_mon(env)) { 1312 return true; 1313 } 1314 return arm_is_secure_below_el3(env); 1315 } 1316 1317 #else 1318 static inline bool arm_is_secure_below_el3(CPUARMState *env) 1319 { 1320 return false; 1321 } 1322 1323 static inline bool arm_is_secure(CPUARMState *env) 1324 { 1325 return false; 1326 } 1327 #endif 1328 1329 /* Return true if the specified exception level is running in AArch64 state. */ 1330 static inline bool arm_el_is_aa64(CPUARMState *env, int el) 1331 { 1332 /* This isn't valid for EL0 (if we're in EL0, is_a64() is what you want, 1333 * and if we're not in EL0 then the state of EL0 isn't well defined.) 1334 */ 1335 assert(el >= 1 && el <= 3); 1336 bool aa64 = arm_feature(env, ARM_FEATURE_AARCH64); 1337 1338 /* The highest exception level is always at the maximum supported 1339 * register width, and then lower levels have a register width controlled 1340 * by bits in the SCR or HCR registers. 1341 */ 1342 if (el == 3) { 1343 return aa64; 1344 } 1345 1346 if (arm_feature(env, ARM_FEATURE_EL3)) { 1347 aa64 = aa64 && (env->cp15.scr_el3 & SCR_RW); 1348 } 1349 1350 if (el == 2) { 1351 return aa64; 1352 } 1353 1354 if (arm_feature(env, ARM_FEATURE_EL2) && !arm_is_secure_below_el3(env)) { 1355 aa64 = aa64 && (env->cp15.hcr_el2 & HCR_RW); 1356 } 1357 1358 return aa64; 1359 } 1360 1361 /* Function for determing whether guest cp register reads and writes should 1362 * access the secure or non-secure bank of a cp register. When EL3 is 1363 * operating in AArch32 state, the NS-bit determines whether the secure 1364 * instance of a cp register should be used. When EL3 is AArch64 (or if 1365 * it doesn't exist at all) then there is no register banking, and all 1366 * accesses are to the non-secure version. 1367 */ 1368 static inline bool access_secure_reg(CPUARMState *env) 1369 { 1370 bool ret = (arm_feature(env, ARM_FEATURE_EL3) && 1371 !arm_el_is_aa64(env, 3) && 1372 !(env->cp15.scr_el3 & SCR_NS)); 1373 1374 return ret; 1375 } 1376 1377 /* Macros for accessing a specified CP register bank */ 1378 #define A32_BANKED_REG_GET(_env, _regname, _secure) \ 1379 ((_secure) ? (_env)->cp15._regname##_s : (_env)->cp15._regname##_ns) 1380 1381 #define A32_BANKED_REG_SET(_env, _regname, _secure, _val) \ 1382 do { \ 1383 if (_secure) { \ 1384 (_env)->cp15._regname##_s = (_val); \ 1385 } else { \ 1386 (_env)->cp15._regname##_ns = (_val); \ 1387 } \ 1388 } while (0) 1389 1390 /* Macros for automatically accessing a specific CP register bank depending on 1391 * the current secure state of the system. These macros are not intended for 1392 * supporting instruction translation reads/writes as these are dependent 1393 * solely on the SCR.NS bit and not the mode. 1394 */ 1395 #define A32_BANKED_CURRENT_REG_GET(_env, _regname) \ 1396 A32_BANKED_REG_GET((_env), _regname, \ 1397 (arm_is_secure(_env) && !arm_el_is_aa64((_env), 3))) 1398 1399 #define A32_BANKED_CURRENT_REG_SET(_env, _regname, _val) \ 1400 A32_BANKED_REG_SET((_env), _regname, \ 1401 (arm_is_secure(_env) && !arm_el_is_aa64((_env), 3)), \ 1402 (_val)) 1403 1404 void arm_cpu_list(FILE *f, fprintf_function cpu_fprintf); 1405 uint32_t arm_phys_excp_target_el(CPUState *cs, uint32_t excp_idx, 1406 uint32_t cur_el, bool secure); 1407 1408 /* Interface between CPU and Interrupt controller. */ 1409 #ifndef CONFIG_USER_ONLY 1410 bool armv7m_nvic_can_take_pending_exception(void *opaque); 1411 #else 1412 static inline bool armv7m_nvic_can_take_pending_exception(void *opaque) 1413 { 1414 return true; 1415 } 1416 #endif 1417 void armv7m_nvic_set_pending(void *opaque, int irq); 1418 void armv7m_nvic_acknowledge_irq(void *opaque); 1419 /** 1420 * armv7m_nvic_complete_irq: complete specified interrupt or exception 1421 * @opaque: the NVIC 1422 * @irq: the exception number to complete 1423 * 1424 * Returns: -1 if the irq was not active 1425 * 1 if completing this irq brought us back to base (no active irqs) 1426 * 0 if there is still an irq active after this one was completed 1427 * (Ignoring -1, this is the same as the RETTOBASE value before completion.) 1428 */ 1429 int armv7m_nvic_complete_irq(void *opaque, int irq); 1430 1431 /* Interface for defining coprocessor registers. 1432 * Registers are defined in tables of arm_cp_reginfo structs 1433 * which are passed to define_arm_cp_regs(). 1434 */ 1435 1436 /* When looking up a coprocessor register we look for it 1437 * via an integer which encodes all of: 1438 * coprocessor number 1439 * Crn, Crm, opc1, opc2 fields 1440 * 32 or 64 bit register (ie is it accessed via MRC/MCR 1441 * or via MRRC/MCRR?) 1442 * non-secure/secure bank (AArch32 only) 1443 * We allow 4 bits for opc1 because MRRC/MCRR have a 4 bit field. 1444 * (In this case crn and opc2 should be zero.) 1445 * For AArch64, there is no 32/64 bit size distinction; 1446 * instead all registers have a 2 bit op0, 3 bit op1 and op2, 1447 * and 4 bit CRn and CRm. The encoding patterns are chosen 1448 * to be easy to convert to and from the KVM encodings, and also 1449 * so that the hashtable can contain both AArch32 and AArch64 1450 * registers (to allow for interprocessing where we might run 1451 * 32 bit code on a 64 bit core). 1452 */ 1453 /* This bit is private to our hashtable cpreg; in KVM register 1454 * IDs the AArch64/32 distinction is the KVM_REG_ARM/ARM64 1455 * in the upper bits of the 64 bit ID. 1456 */ 1457 #define CP_REG_AA64_SHIFT 28 1458 #define CP_REG_AA64_MASK (1 << CP_REG_AA64_SHIFT) 1459 1460 /* To enable banking of coprocessor registers depending on ns-bit we 1461 * add a bit to distinguish between secure and non-secure cpregs in the 1462 * hashtable. 1463 */ 1464 #define CP_REG_NS_SHIFT 29 1465 #define CP_REG_NS_MASK (1 << CP_REG_NS_SHIFT) 1466 1467 #define ENCODE_CP_REG(cp, is64, ns, crn, crm, opc1, opc2) \ 1468 ((ns) << CP_REG_NS_SHIFT | ((cp) << 16) | ((is64) << 15) | \ 1469 ((crn) << 11) | ((crm) << 7) | ((opc1) << 3) | (opc2)) 1470 1471 #define ENCODE_AA64_CP_REG(cp, crn, crm, op0, op1, op2) \ 1472 (CP_REG_AA64_MASK | \ 1473 ((cp) << CP_REG_ARM_COPROC_SHIFT) | \ 1474 ((op0) << CP_REG_ARM64_SYSREG_OP0_SHIFT) | \ 1475 ((op1) << CP_REG_ARM64_SYSREG_OP1_SHIFT) | \ 1476 ((crn) << CP_REG_ARM64_SYSREG_CRN_SHIFT) | \ 1477 ((crm) << CP_REG_ARM64_SYSREG_CRM_SHIFT) | \ 1478 ((op2) << CP_REG_ARM64_SYSREG_OP2_SHIFT)) 1479 1480 /* Convert a full 64 bit KVM register ID to the truncated 32 bit 1481 * version used as a key for the coprocessor register hashtable 1482 */ 1483 static inline uint32_t kvm_to_cpreg_id(uint64_t kvmid) 1484 { 1485 uint32_t cpregid = kvmid; 1486 if ((kvmid & CP_REG_ARCH_MASK) == CP_REG_ARM64) { 1487 cpregid |= CP_REG_AA64_MASK; 1488 } else { 1489 if ((kvmid & CP_REG_SIZE_MASK) == CP_REG_SIZE_U64) { 1490 cpregid |= (1 << 15); 1491 } 1492 1493 /* KVM is always non-secure so add the NS flag on AArch32 register 1494 * entries. 1495 */ 1496 cpregid |= 1 << CP_REG_NS_SHIFT; 1497 } 1498 return cpregid; 1499 } 1500 1501 /* Convert a truncated 32 bit hashtable key into the full 1502 * 64 bit KVM register ID. 1503 */ 1504 static inline uint64_t cpreg_to_kvm_id(uint32_t cpregid) 1505 { 1506 uint64_t kvmid; 1507 1508 if (cpregid & CP_REG_AA64_MASK) { 1509 kvmid = cpregid & ~CP_REG_AA64_MASK; 1510 kvmid |= CP_REG_SIZE_U64 | CP_REG_ARM64; 1511 } else { 1512 kvmid = cpregid & ~(1 << 15); 1513 if (cpregid & (1 << 15)) { 1514 kvmid |= CP_REG_SIZE_U64 | CP_REG_ARM; 1515 } else { 1516 kvmid |= CP_REG_SIZE_U32 | CP_REG_ARM; 1517 } 1518 } 1519 return kvmid; 1520 } 1521 1522 /* ARMCPRegInfo type field bits. If the SPECIAL bit is set this is a 1523 * special-behaviour cp reg and bits [15..8] indicate what behaviour 1524 * it has. Otherwise it is a simple cp reg, where CONST indicates that 1525 * TCG can assume the value to be constant (ie load at translate time) 1526 * and 64BIT indicates a 64 bit wide coprocessor register. SUPPRESS_TB_END 1527 * indicates that the TB should not be ended after a write to this register 1528 * (the default is that the TB ends after cp writes). OVERRIDE permits 1529 * a register definition to override a previous definition for the 1530 * same (cp, is64, crn, crm, opc1, opc2) tuple: either the new or the 1531 * old must have the OVERRIDE bit set. 1532 * ALIAS indicates that this register is an alias view of some underlying 1533 * state which is also visible via another register, and that the other 1534 * register is handling migration and reset; registers marked ALIAS will not be 1535 * migrated but may have their state set by syncing of register state from KVM. 1536 * NO_RAW indicates that this register has no underlying state and does not 1537 * support raw access for state saving/loading; it will not be used for either 1538 * migration or KVM state synchronization. (Typically this is for "registers" 1539 * which are actually used as instructions for cache maintenance and so on.) 1540 * IO indicates that this register does I/O and therefore its accesses 1541 * need to be surrounded by gen_io_start()/gen_io_end(). In particular, 1542 * registers which implement clocks or timers require this. 1543 */ 1544 #define ARM_CP_SPECIAL 1 1545 #define ARM_CP_CONST 2 1546 #define ARM_CP_64BIT 4 1547 #define ARM_CP_SUPPRESS_TB_END 8 1548 #define ARM_CP_OVERRIDE 16 1549 #define ARM_CP_ALIAS 32 1550 #define ARM_CP_IO 64 1551 #define ARM_CP_NO_RAW 128 1552 #define ARM_CP_NOP (ARM_CP_SPECIAL | (1 << 8)) 1553 #define ARM_CP_WFI (ARM_CP_SPECIAL | (2 << 8)) 1554 #define ARM_CP_NZCV (ARM_CP_SPECIAL | (3 << 8)) 1555 #define ARM_CP_CURRENTEL (ARM_CP_SPECIAL | (4 << 8)) 1556 #define ARM_CP_DC_ZVA (ARM_CP_SPECIAL | (5 << 8)) 1557 #define ARM_LAST_SPECIAL ARM_CP_DC_ZVA 1558 /* Used only as a terminator for ARMCPRegInfo lists */ 1559 #define ARM_CP_SENTINEL 0xffff 1560 /* Mask of only the flag bits in a type field */ 1561 #define ARM_CP_FLAG_MASK 0xff 1562 1563 /* Valid values for ARMCPRegInfo state field, indicating which of 1564 * the AArch32 and AArch64 execution states this register is visible in. 1565 * If the reginfo doesn't explicitly specify then it is AArch32 only. 1566 * If the reginfo is declared to be visible in both states then a second 1567 * reginfo is synthesised for the AArch32 view of the AArch64 register, 1568 * such that the AArch32 view is the lower 32 bits of the AArch64 one. 1569 * Note that we rely on the values of these enums as we iterate through 1570 * the various states in some places. 1571 */ 1572 enum { 1573 ARM_CP_STATE_AA32 = 0, 1574 ARM_CP_STATE_AA64 = 1, 1575 ARM_CP_STATE_BOTH = 2, 1576 }; 1577 1578 /* ARM CP register secure state flags. These flags identify security state 1579 * attributes for a given CP register entry. 1580 * The existence of both or neither secure and non-secure flags indicates that 1581 * the register has both a secure and non-secure hash entry. A single one of 1582 * these flags causes the register to only be hashed for the specified 1583 * security state. 1584 * Although definitions may have any combination of the S/NS bits, each 1585 * registered entry will only have one to identify whether the entry is secure 1586 * or non-secure. 1587 */ 1588 enum { 1589 ARM_CP_SECSTATE_S = (1 << 0), /* bit[0]: Secure state register */ 1590 ARM_CP_SECSTATE_NS = (1 << 1), /* bit[1]: Non-secure state register */ 1591 }; 1592 1593 /* Return true if cptype is a valid type field. This is used to try to 1594 * catch errors where the sentinel has been accidentally left off the end 1595 * of a list of registers. 1596 */ 1597 static inline bool cptype_valid(int cptype) 1598 { 1599 return ((cptype & ~ARM_CP_FLAG_MASK) == 0) 1600 || ((cptype & ARM_CP_SPECIAL) && 1601 ((cptype & ~ARM_CP_FLAG_MASK) <= ARM_LAST_SPECIAL)); 1602 } 1603 1604 /* Access rights: 1605 * We define bits for Read and Write access for what rev C of the v7-AR ARM ARM 1606 * defines as PL0 (user), PL1 (fiq/irq/svc/abt/und/sys, ie privileged), and 1607 * PL2 (hyp). The other level which has Read and Write bits is Secure PL1 1608 * (ie any of the privileged modes in Secure state, or Monitor mode). 1609 * If a register is accessible in one privilege level it's always accessible 1610 * in higher privilege levels too. Since "Secure PL1" also follows this rule 1611 * (ie anything visible in PL2 is visible in S-PL1, some things are only 1612 * visible in S-PL1) but "Secure PL1" is a bit of a mouthful, we bend the 1613 * terminology a little and call this PL3. 1614 * In AArch64 things are somewhat simpler as the PLx bits line up exactly 1615 * with the ELx exception levels. 1616 * 1617 * If access permissions for a register are more complex than can be 1618 * described with these bits, then use a laxer set of restrictions, and 1619 * do the more restrictive/complex check inside a helper function. 1620 */ 1621 #define PL3_R 0x80 1622 #define PL3_W 0x40 1623 #define PL2_R (0x20 | PL3_R) 1624 #define PL2_W (0x10 | PL3_W) 1625 #define PL1_R (0x08 | PL2_R) 1626 #define PL1_W (0x04 | PL2_W) 1627 #define PL0_R (0x02 | PL1_R) 1628 #define PL0_W (0x01 | PL1_W) 1629 1630 #define PL3_RW (PL3_R | PL3_W) 1631 #define PL2_RW (PL2_R | PL2_W) 1632 #define PL1_RW (PL1_R | PL1_W) 1633 #define PL0_RW (PL0_R | PL0_W) 1634 1635 /* Return the highest implemented Exception Level */ 1636 static inline int arm_highest_el(CPUARMState *env) 1637 { 1638 if (arm_feature(env, ARM_FEATURE_EL3)) { 1639 return 3; 1640 } 1641 if (arm_feature(env, ARM_FEATURE_EL2)) { 1642 return 2; 1643 } 1644 return 1; 1645 } 1646 1647 /* Return true if a v7M CPU is in Handler mode */ 1648 static inline bool arm_v7m_is_handler_mode(CPUARMState *env) 1649 { 1650 return env->v7m.exception != 0; 1651 } 1652 1653 /* Return the current Exception Level (as per ARMv8; note that this differs 1654 * from the ARMv7 Privilege Level). 1655 */ 1656 static inline int arm_current_el(CPUARMState *env) 1657 { 1658 if (arm_feature(env, ARM_FEATURE_M)) { 1659 return arm_v7m_is_handler_mode(env) || !(env->v7m.control & 1); 1660 } 1661 1662 if (is_a64(env)) { 1663 return extract32(env->pstate, 2, 2); 1664 } 1665 1666 switch (env->uncached_cpsr & 0x1f) { 1667 case ARM_CPU_MODE_USR: 1668 return 0; 1669 case ARM_CPU_MODE_HYP: 1670 return 2; 1671 case ARM_CPU_MODE_MON: 1672 return 3; 1673 default: 1674 if (arm_is_secure(env) && !arm_el_is_aa64(env, 3)) { 1675 /* If EL3 is 32-bit then all secure privileged modes run in 1676 * EL3 1677 */ 1678 return 3; 1679 } 1680 1681 return 1; 1682 } 1683 } 1684 1685 typedef struct ARMCPRegInfo ARMCPRegInfo; 1686 1687 typedef enum CPAccessResult { 1688 /* Access is permitted */ 1689 CP_ACCESS_OK = 0, 1690 /* Access fails due to a configurable trap or enable which would 1691 * result in a categorized exception syndrome giving information about 1692 * the failing instruction (ie syndrome category 0x3, 0x4, 0x5, 0x6, 1693 * 0xc or 0x18). The exception is taken to the usual target EL (EL1 or 1694 * PL1 if in EL0, otherwise to the current EL). 1695 */ 1696 CP_ACCESS_TRAP = 1, 1697 /* Access fails and results in an exception syndrome 0x0 ("uncategorized"). 1698 * Note that this is not a catch-all case -- the set of cases which may 1699 * result in this failure is specifically defined by the architecture. 1700 */ 1701 CP_ACCESS_TRAP_UNCATEGORIZED = 2, 1702 /* As CP_ACCESS_TRAP, but for traps directly to EL2 or EL3 */ 1703 CP_ACCESS_TRAP_EL2 = 3, 1704 CP_ACCESS_TRAP_EL3 = 4, 1705 /* As CP_ACCESS_UNCATEGORIZED, but for traps directly to EL2 or EL3 */ 1706 CP_ACCESS_TRAP_UNCATEGORIZED_EL2 = 5, 1707 CP_ACCESS_TRAP_UNCATEGORIZED_EL3 = 6, 1708 /* Access fails and results in an exception syndrome for an FP access, 1709 * trapped directly to EL2 or EL3 1710 */ 1711 CP_ACCESS_TRAP_FP_EL2 = 7, 1712 CP_ACCESS_TRAP_FP_EL3 = 8, 1713 } CPAccessResult; 1714 1715 /* Access functions for coprocessor registers. These cannot fail and 1716 * may not raise exceptions. 1717 */ 1718 typedef uint64_t CPReadFn(CPUARMState *env, const ARMCPRegInfo *opaque); 1719 typedef void CPWriteFn(CPUARMState *env, const ARMCPRegInfo *opaque, 1720 uint64_t value); 1721 /* Access permission check functions for coprocessor registers. */ 1722 typedef CPAccessResult CPAccessFn(CPUARMState *env, 1723 const ARMCPRegInfo *opaque, 1724 bool isread); 1725 /* Hook function for register reset */ 1726 typedef void CPResetFn(CPUARMState *env, const ARMCPRegInfo *opaque); 1727 1728 #define CP_ANY 0xff 1729 1730 /* Definition of an ARM coprocessor register */ 1731 struct ARMCPRegInfo { 1732 /* Name of register (useful mainly for debugging, need not be unique) */ 1733 const char *name; 1734 /* Location of register: coprocessor number and (crn,crm,opc1,opc2) 1735 * tuple. Any of crm, opc1 and opc2 may be CP_ANY to indicate a 1736 * 'wildcard' field -- any value of that field in the MRC/MCR insn 1737 * will be decoded to this register. The register read and write 1738 * callbacks will be passed an ARMCPRegInfo with the crn/crm/opc1/opc2 1739 * used by the program, so it is possible to register a wildcard and 1740 * then behave differently on read/write if necessary. 1741 * For 64 bit registers, only crm and opc1 are relevant; crn and opc2 1742 * must both be zero. 1743 * For AArch64-visible registers, opc0 is also used. 1744 * Since there are no "coprocessors" in AArch64, cp is purely used as a 1745 * way to distinguish (for KVM's benefit) guest-visible system registers 1746 * from demuxed ones provided to preserve the "no side effects on 1747 * KVM register read/write from QEMU" semantics. cp==0x13 is guest 1748 * visible (to match KVM's encoding); cp==0 will be converted to 1749 * cp==0x13 when the ARMCPRegInfo is registered, for convenience. 1750 */ 1751 uint8_t cp; 1752 uint8_t crn; 1753 uint8_t crm; 1754 uint8_t opc0; 1755 uint8_t opc1; 1756 uint8_t opc2; 1757 /* Execution state in which this register is visible: ARM_CP_STATE_* */ 1758 int state; 1759 /* Register type: ARM_CP_* bits/values */ 1760 int type; 1761 /* Access rights: PL*_[RW] */ 1762 int access; 1763 /* Security state: ARM_CP_SECSTATE_* bits/values */ 1764 int secure; 1765 /* The opaque pointer passed to define_arm_cp_regs_with_opaque() when 1766 * this register was defined: can be used to hand data through to the 1767 * register read/write functions, since they are passed the ARMCPRegInfo*. 1768 */ 1769 void *opaque; 1770 /* Value of this register, if it is ARM_CP_CONST. Otherwise, if 1771 * fieldoffset is non-zero, the reset value of the register. 1772 */ 1773 uint64_t resetvalue; 1774 /* Offset of the field in CPUARMState for this register. 1775 * 1776 * This is not needed if either: 1777 * 1. type is ARM_CP_CONST or one of the ARM_CP_SPECIALs 1778 * 2. both readfn and writefn are specified 1779 */ 1780 ptrdiff_t fieldoffset; /* offsetof(CPUARMState, field) */ 1781 1782 /* Offsets of the secure and non-secure fields in CPUARMState for the 1783 * register if it is banked. These fields are only used during the static 1784 * registration of a register. During hashing the bank associated 1785 * with a given security state is copied to fieldoffset which is used from 1786 * there on out. 1787 * 1788 * It is expected that register definitions use either fieldoffset or 1789 * bank_fieldoffsets in the definition but not both. It is also expected 1790 * that both bank offsets are set when defining a banked register. This 1791 * use indicates that a register is banked. 1792 */ 1793 ptrdiff_t bank_fieldoffsets[2]; 1794 1795 /* Function for making any access checks for this register in addition to 1796 * those specified by the 'access' permissions bits. If NULL, no extra 1797 * checks required. The access check is performed at runtime, not at 1798 * translate time. 1799 */ 1800 CPAccessFn *accessfn; 1801 /* Function for handling reads of this register. If NULL, then reads 1802 * will be done by loading from the offset into CPUARMState specified 1803 * by fieldoffset. 1804 */ 1805 CPReadFn *readfn; 1806 /* Function for handling writes of this register. If NULL, then writes 1807 * will be done by writing to the offset into CPUARMState specified 1808 * by fieldoffset. 1809 */ 1810 CPWriteFn *writefn; 1811 /* Function for doing a "raw" read; used when we need to copy 1812 * coprocessor state to the kernel for KVM or out for 1813 * migration. This only needs to be provided if there is also a 1814 * readfn and it has side effects (for instance clear-on-read bits). 1815 */ 1816 CPReadFn *raw_readfn; 1817 /* Function for doing a "raw" write; used when we need to copy KVM 1818 * kernel coprocessor state into userspace, or for inbound 1819 * migration. This only needs to be provided if there is also a 1820 * writefn and it masks out "unwritable" bits or has write-one-to-clear 1821 * or similar behaviour. 1822 */ 1823 CPWriteFn *raw_writefn; 1824 /* Function for resetting the register. If NULL, then reset will be done 1825 * by writing resetvalue to the field specified in fieldoffset. If 1826 * fieldoffset is 0 then no reset will be done. 1827 */ 1828 CPResetFn *resetfn; 1829 }; 1830 1831 /* Macros which are lvalues for the field in CPUARMState for the 1832 * ARMCPRegInfo *ri. 1833 */ 1834 #define CPREG_FIELD32(env, ri) \ 1835 (*(uint32_t *)((char *)(env) + (ri)->fieldoffset)) 1836 #define CPREG_FIELD64(env, ri) \ 1837 (*(uint64_t *)((char *)(env) + (ri)->fieldoffset)) 1838 1839 #define REGINFO_SENTINEL { .type = ARM_CP_SENTINEL } 1840 1841 void define_arm_cp_regs_with_opaque(ARMCPU *cpu, 1842 const ARMCPRegInfo *regs, void *opaque); 1843 void define_one_arm_cp_reg_with_opaque(ARMCPU *cpu, 1844 const ARMCPRegInfo *regs, void *opaque); 1845 static inline void define_arm_cp_regs(ARMCPU *cpu, const ARMCPRegInfo *regs) 1846 { 1847 define_arm_cp_regs_with_opaque(cpu, regs, 0); 1848 } 1849 static inline void define_one_arm_cp_reg(ARMCPU *cpu, const ARMCPRegInfo *regs) 1850 { 1851 define_one_arm_cp_reg_with_opaque(cpu, regs, 0); 1852 } 1853 const ARMCPRegInfo *get_arm_cp_reginfo(GHashTable *cpregs, uint32_t encoded_cp); 1854 1855 /* CPWriteFn that can be used to implement writes-ignored behaviour */ 1856 void arm_cp_write_ignore(CPUARMState *env, const ARMCPRegInfo *ri, 1857 uint64_t value); 1858 /* CPReadFn that can be used for read-as-zero behaviour */ 1859 uint64_t arm_cp_read_zero(CPUARMState *env, const ARMCPRegInfo *ri); 1860 1861 /* CPResetFn that does nothing, for use if no reset is required even 1862 * if fieldoffset is non zero. 1863 */ 1864 void arm_cp_reset_ignore(CPUARMState *env, const ARMCPRegInfo *opaque); 1865 1866 /* Return true if this reginfo struct's field in the cpu state struct 1867 * is 64 bits wide. 1868 */ 1869 static inline bool cpreg_field_is_64bit(const ARMCPRegInfo *ri) 1870 { 1871 return (ri->state == ARM_CP_STATE_AA64) || (ri->type & ARM_CP_64BIT); 1872 } 1873 1874 static inline bool cp_access_ok(int current_el, 1875 const ARMCPRegInfo *ri, int isread) 1876 { 1877 return (ri->access >> ((current_el * 2) + isread)) & 1; 1878 } 1879 1880 /* Raw read of a coprocessor register (as needed for migration, etc) */ 1881 uint64_t read_raw_cp_reg(CPUARMState *env, const ARMCPRegInfo *ri); 1882 1883 /** 1884 * write_list_to_cpustate 1885 * @cpu: ARMCPU 1886 * 1887 * For each register listed in the ARMCPU cpreg_indexes list, write 1888 * its value from the cpreg_values list into the ARMCPUState structure. 1889 * This updates TCG's working data structures from KVM data or 1890 * from incoming migration state. 1891 * 1892 * Returns: true if all register values were updated correctly, 1893 * false if some register was unknown or could not be written. 1894 * Note that we do not stop early on failure -- we will attempt 1895 * writing all registers in the list. 1896 */ 1897 bool write_list_to_cpustate(ARMCPU *cpu); 1898 1899 /** 1900 * write_cpustate_to_list: 1901 * @cpu: ARMCPU 1902 * 1903 * For each register listed in the ARMCPU cpreg_indexes list, write 1904 * its value from the ARMCPUState structure into the cpreg_values list. 1905 * This is used to copy info from TCG's working data structures into 1906 * KVM or for outbound migration. 1907 * 1908 * Returns: true if all register values were read correctly, 1909 * false if some register was unknown or could not be read. 1910 * Note that we do not stop early on failure -- we will attempt 1911 * reading all registers in the list. 1912 */ 1913 bool write_cpustate_to_list(ARMCPU *cpu); 1914 1915 #define ARM_CPUID_TI915T 0x54029152 1916 #define ARM_CPUID_TI925T 0x54029252 1917 1918 #if defined(CONFIG_USER_ONLY) 1919 #define TARGET_PAGE_BITS 12 1920 #else 1921 /* ARMv7 and later CPUs have 4K pages minimum, but ARMv5 and v6 1922 * have to support 1K tiny pages. 1923 */ 1924 #define TARGET_PAGE_BITS_VARY 1925 #define TARGET_PAGE_BITS_MIN 10 1926 #endif 1927 1928 #if defined(TARGET_AARCH64) 1929 # define TARGET_PHYS_ADDR_SPACE_BITS 48 1930 # define TARGET_VIRT_ADDR_SPACE_BITS 64 1931 #else 1932 # define TARGET_PHYS_ADDR_SPACE_BITS 40 1933 # define TARGET_VIRT_ADDR_SPACE_BITS 32 1934 #endif 1935 1936 static inline bool arm_excp_unmasked(CPUState *cs, unsigned int excp_idx, 1937 unsigned int target_el) 1938 { 1939 CPUARMState *env = cs->env_ptr; 1940 unsigned int cur_el = arm_current_el(env); 1941 bool secure = arm_is_secure(env); 1942 bool pstate_unmasked; 1943 int8_t unmasked = 0; 1944 1945 /* Don't take exceptions if they target a lower EL. 1946 * This check should catch any exceptions that would not be taken but left 1947 * pending. 1948 */ 1949 if (cur_el > target_el) { 1950 return false; 1951 } 1952 1953 switch (excp_idx) { 1954 case EXCP_FIQ: 1955 pstate_unmasked = !(env->daif & PSTATE_F); 1956 break; 1957 1958 case EXCP_IRQ: 1959 pstate_unmasked = !(env->daif & PSTATE_I); 1960 break; 1961 1962 case EXCP_VFIQ: 1963 if (secure || !(env->cp15.hcr_el2 & HCR_FMO)) { 1964 /* VFIQs are only taken when hypervized and non-secure. */ 1965 return false; 1966 } 1967 return !(env->daif & PSTATE_F); 1968 case EXCP_VIRQ: 1969 if (secure || !(env->cp15.hcr_el2 & HCR_IMO)) { 1970 /* VIRQs are only taken when hypervized and non-secure. */ 1971 return false; 1972 } 1973 return !(env->daif & PSTATE_I); 1974 default: 1975 g_assert_not_reached(); 1976 } 1977 1978 /* Use the target EL, current execution state and SCR/HCR settings to 1979 * determine whether the corresponding CPSR bit is used to mask the 1980 * interrupt. 1981 */ 1982 if ((target_el > cur_el) && (target_el != 1)) { 1983 /* Exceptions targeting a higher EL may not be maskable */ 1984 if (arm_feature(env, ARM_FEATURE_AARCH64)) { 1985 /* 64-bit masking rules are simple: exceptions to EL3 1986 * can't be masked, and exceptions to EL2 can only be 1987 * masked from Secure state. The HCR and SCR settings 1988 * don't affect the masking logic, only the interrupt routing. 1989 */ 1990 if (target_el == 3 || !secure) { 1991 unmasked = 1; 1992 } 1993 } else { 1994 /* The old 32-bit-only environment has a more complicated 1995 * masking setup. HCR and SCR bits not only affect interrupt 1996 * routing but also change the behaviour of masking. 1997 */ 1998 bool hcr, scr; 1999 2000 switch (excp_idx) { 2001 case EXCP_FIQ: 2002 /* If FIQs are routed to EL3 or EL2 then there are cases where 2003 * we override the CPSR.F in determining if the exception is 2004 * masked or not. If neither of these are set then we fall back 2005 * to the CPSR.F setting otherwise we further assess the state 2006 * below. 2007 */ 2008 hcr = (env->cp15.hcr_el2 & HCR_FMO); 2009 scr = (env->cp15.scr_el3 & SCR_FIQ); 2010 2011 /* When EL3 is 32-bit, the SCR.FW bit controls whether the 2012 * CPSR.F bit masks FIQ interrupts when taken in non-secure 2013 * state. If SCR.FW is set then FIQs can be masked by CPSR.F 2014 * when non-secure but only when FIQs are only routed to EL3. 2015 */ 2016 scr = scr && !((env->cp15.scr_el3 & SCR_FW) && !hcr); 2017 break; 2018 case EXCP_IRQ: 2019 /* When EL3 execution state is 32-bit, if HCR.IMO is set then 2020 * we may override the CPSR.I masking when in non-secure state. 2021 * The SCR.IRQ setting has already been taken into consideration 2022 * when setting the target EL, so it does not have a further 2023 * affect here. 2024 */ 2025 hcr = (env->cp15.hcr_el2 & HCR_IMO); 2026 scr = false; 2027 break; 2028 default: 2029 g_assert_not_reached(); 2030 } 2031 2032 if ((scr || hcr) && !secure) { 2033 unmasked = 1; 2034 } 2035 } 2036 } 2037 2038 /* The PSTATE bits only mask the interrupt if we have not overriden the 2039 * ability above. 2040 */ 2041 return unmasked || pstate_unmasked; 2042 } 2043 2044 #define cpu_init(cpu_model) cpu_generic_init(TYPE_ARM_CPU, cpu_model) 2045 2046 #define cpu_signal_handler cpu_arm_signal_handler 2047 #define cpu_list arm_cpu_list 2048 2049 /* ARM has the following "translation regimes" (as the ARM ARM calls them): 2050 * 2051 * If EL3 is 64-bit: 2052 * + NonSecure EL1 & 0 stage 1 2053 * + NonSecure EL1 & 0 stage 2 2054 * + NonSecure EL2 2055 * + Secure EL1 & EL0 2056 * + Secure EL3 2057 * If EL3 is 32-bit: 2058 * + NonSecure PL1 & 0 stage 1 2059 * + NonSecure PL1 & 0 stage 2 2060 * + NonSecure PL2 2061 * + Secure PL0 & PL1 2062 * (reminder: for 32 bit EL3, Secure PL1 is *EL3*, not EL1.) 2063 * 2064 * For QEMU, an mmu_idx is not quite the same as a translation regime because: 2065 * 1. we need to split the "EL1 & 0" regimes into two mmu_idxes, because they 2066 * may differ in access permissions even if the VA->PA map is the same 2067 * 2. we want to cache in our TLB the full VA->IPA->PA lookup for a stage 1+2 2068 * translation, which means that we have one mmu_idx that deals with two 2069 * concatenated translation regimes [this sort of combined s1+2 TLB is 2070 * architecturally permitted] 2071 * 3. we don't need to allocate an mmu_idx to translations that we won't be 2072 * handling via the TLB. The only way to do a stage 1 translation without 2073 * the immediate stage 2 translation is via the ATS or AT system insns, 2074 * which can be slow-pathed and always do a page table walk. 2075 * 4. we can also safely fold together the "32 bit EL3" and "64 bit EL3" 2076 * translation regimes, because they map reasonably well to each other 2077 * and they can't both be active at the same time. 2078 * This gives us the following list of mmu_idx values: 2079 * 2080 * NS EL0 (aka NS PL0) stage 1+2 2081 * NS EL1 (aka NS PL1) stage 1+2 2082 * NS EL2 (aka NS PL2) 2083 * S EL3 (aka S PL1) 2084 * S EL0 (aka S PL0) 2085 * S EL1 (not used if EL3 is 32 bit) 2086 * NS EL0+1 stage 2 2087 * 2088 * (The last of these is an mmu_idx because we want to be able to use the TLB 2089 * for the accesses done as part of a stage 1 page table walk, rather than 2090 * having to walk the stage 2 page table over and over.) 2091 * 2092 * R profile CPUs have an MPU, but can use the same set of MMU indexes 2093 * as A profile. They only need to distinguish NS EL0 and NS EL1 (and 2094 * NS EL2 if we ever model a Cortex-R52). 2095 * 2096 * M profile CPUs are rather different as they do not have a true MMU. 2097 * They have the following different MMU indexes: 2098 * User 2099 * Privileged 2100 * Execution priority negative (this is like privileged, but the 2101 * MPU HFNMIENA bit means that it may have different access permission 2102 * check results to normal privileged code, so can't share a TLB). 2103 * 2104 * The ARMMMUIdx and the mmu index value used by the core QEMU TLB code 2105 * are not quite the same -- different CPU types (most notably M profile 2106 * vs A/R profile) would like to use MMU indexes with different semantics, 2107 * but since we don't ever need to use all of those in a single CPU we 2108 * can avoid setting NB_MMU_MODES to more than 8. The lower bits of 2109 * ARMMMUIdx are the core TLB mmu index, and the higher bits are always 2110 * the same for any particular CPU. 2111 * Variables of type ARMMUIdx are always full values, and the core 2112 * index values are in variables of type 'int'. 2113 * 2114 * Our enumeration includes at the end some entries which are not "true" 2115 * mmu_idx values in that they don't have corresponding TLBs and are only 2116 * valid for doing slow path page table walks. 2117 * 2118 * The constant names here are patterned after the general style of the names 2119 * of the AT/ATS operations. 2120 * The values used are carefully arranged to make mmu_idx => EL lookup easy. 2121 */ 2122 #define ARM_MMU_IDX_A 0x10 /* A profile */ 2123 #define ARM_MMU_IDX_NOTLB 0x20 /* does not have a TLB */ 2124 #define ARM_MMU_IDX_M 0x40 /* M profile */ 2125 2126 #define ARM_MMU_IDX_TYPE_MASK (~0x7) 2127 #define ARM_MMU_IDX_COREIDX_MASK 0x7 2128 2129 typedef enum ARMMMUIdx { 2130 ARMMMUIdx_S12NSE0 = 0 | ARM_MMU_IDX_A, 2131 ARMMMUIdx_S12NSE1 = 1 | ARM_MMU_IDX_A, 2132 ARMMMUIdx_S1E2 = 2 | ARM_MMU_IDX_A, 2133 ARMMMUIdx_S1E3 = 3 | ARM_MMU_IDX_A, 2134 ARMMMUIdx_S1SE0 = 4 | ARM_MMU_IDX_A, 2135 ARMMMUIdx_S1SE1 = 5 | ARM_MMU_IDX_A, 2136 ARMMMUIdx_S2NS = 6 | ARM_MMU_IDX_A, 2137 ARMMMUIdx_MUser = 0 | ARM_MMU_IDX_M, 2138 ARMMMUIdx_MPriv = 1 | ARM_MMU_IDX_M, 2139 ARMMMUIdx_MNegPri = 2 | ARM_MMU_IDX_M, 2140 /* Indexes below here don't have TLBs and are used only for AT system 2141 * instructions or for the first stage of an S12 page table walk. 2142 */ 2143 ARMMMUIdx_S1NSE0 = 0 | ARM_MMU_IDX_NOTLB, 2144 ARMMMUIdx_S1NSE1 = 1 | ARM_MMU_IDX_NOTLB, 2145 } ARMMMUIdx; 2146 2147 /* Bit macros for the core-mmu-index values for each index, 2148 * for use when calling tlb_flush_by_mmuidx() and friends. 2149 */ 2150 typedef enum ARMMMUIdxBit { 2151 ARMMMUIdxBit_S12NSE0 = 1 << 0, 2152 ARMMMUIdxBit_S12NSE1 = 1 << 1, 2153 ARMMMUIdxBit_S1E2 = 1 << 2, 2154 ARMMMUIdxBit_S1E3 = 1 << 3, 2155 ARMMMUIdxBit_S1SE0 = 1 << 4, 2156 ARMMMUIdxBit_S1SE1 = 1 << 5, 2157 ARMMMUIdxBit_S2NS = 1 << 6, 2158 ARMMMUIdxBit_MUser = 1 << 0, 2159 ARMMMUIdxBit_MPriv = 1 << 1, 2160 ARMMMUIdxBit_MNegPri = 1 << 2, 2161 } ARMMMUIdxBit; 2162 2163 #define MMU_USER_IDX 0 2164 2165 static inline int arm_to_core_mmu_idx(ARMMMUIdx mmu_idx) 2166 { 2167 return mmu_idx & ARM_MMU_IDX_COREIDX_MASK; 2168 } 2169 2170 static inline ARMMMUIdx core_to_arm_mmu_idx(CPUARMState *env, int mmu_idx) 2171 { 2172 if (arm_feature(env, ARM_FEATURE_M)) { 2173 return mmu_idx | ARM_MMU_IDX_M; 2174 } else { 2175 return mmu_idx | ARM_MMU_IDX_A; 2176 } 2177 } 2178 2179 /* Return the exception level we're running at if this is our mmu_idx */ 2180 static inline int arm_mmu_idx_to_el(ARMMMUIdx mmu_idx) 2181 { 2182 switch (mmu_idx & ARM_MMU_IDX_TYPE_MASK) { 2183 case ARM_MMU_IDX_A: 2184 return mmu_idx & 3; 2185 case ARM_MMU_IDX_M: 2186 return mmu_idx == ARMMMUIdx_MUser ? 0 : 1; 2187 default: 2188 g_assert_not_reached(); 2189 } 2190 } 2191 2192 /* Determine the current mmu_idx to use for normal loads/stores */ 2193 static inline int cpu_mmu_index(CPUARMState *env, bool ifetch) 2194 { 2195 int el = arm_current_el(env); 2196 2197 if (arm_feature(env, ARM_FEATURE_M)) { 2198 ARMMMUIdx mmu_idx = el == 0 ? ARMMMUIdx_MUser : ARMMMUIdx_MPriv; 2199 2200 /* Execution priority is negative if FAULTMASK is set or 2201 * we're in a HardFault or NMI handler. 2202 */ 2203 if ((env->v7m.exception > 0 && env->v7m.exception <= 3) 2204 || env->v7m.faultmask) { 2205 return arm_to_core_mmu_idx(ARMMMUIdx_MNegPri); 2206 } 2207 2208 return arm_to_core_mmu_idx(mmu_idx); 2209 } 2210 2211 if (el < 2 && arm_is_secure_below_el3(env)) { 2212 return arm_to_core_mmu_idx(ARMMMUIdx_S1SE0 + el); 2213 } 2214 return el; 2215 } 2216 2217 /* Indexes used when registering address spaces with cpu_address_space_init */ 2218 typedef enum ARMASIdx { 2219 ARMASIdx_NS = 0, 2220 ARMASIdx_S = 1, 2221 } ARMASIdx; 2222 2223 /* Return the Exception Level targeted by debug exceptions. */ 2224 static inline int arm_debug_target_el(CPUARMState *env) 2225 { 2226 bool secure = arm_is_secure(env); 2227 bool route_to_el2 = false; 2228 2229 if (arm_feature(env, ARM_FEATURE_EL2) && !secure) { 2230 route_to_el2 = env->cp15.hcr_el2 & HCR_TGE || 2231 env->cp15.mdcr_el2 & (1 << 8); 2232 } 2233 2234 if (route_to_el2) { 2235 return 2; 2236 } else if (arm_feature(env, ARM_FEATURE_EL3) && 2237 !arm_el_is_aa64(env, 3) && secure) { 2238 return 3; 2239 } else { 2240 return 1; 2241 } 2242 } 2243 2244 static inline bool aa64_generate_debug_exceptions(CPUARMState *env) 2245 { 2246 if (arm_is_secure(env)) { 2247 /* MDCR_EL3.SDD disables debug events from Secure state */ 2248 if (extract32(env->cp15.mdcr_el3, 16, 1) != 0 2249 || arm_current_el(env) == 3) { 2250 return false; 2251 } 2252 } 2253 2254 if (arm_current_el(env) == arm_debug_target_el(env)) { 2255 if ((extract32(env->cp15.mdscr_el1, 13, 1) == 0) 2256 || (env->daif & PSTATE_D)) { 2257 return false; 2258 } 2259 } 2260 return true; 2261 } 2262 2263 static inline bool aa32_generate_debug_exceptions(CPUARMState *env) 2264 { 2265 int el = arm_current_el(env); 2266 2267 if (el == 0 && arm_el_is_aa64(env, 1)) { 2268 return aa64_generate_debug_exceptions(env); 2269 } 2270 2271 if (arm_is_secure(env)) { 2272 int spd; 2273 2274 if (el == 0 && (env->cp15.sder & 1)) { 2275 /* SDER.SUIDEN means debug exceptions from Secure EL0 2276 * are always enabled. Otherwise they are controlled by 2277 * SDCR.SPD like those from other Secure ELs. 2278 */ 2279 return true; 2280 } 2281 2282 spd = extract32(env->cp15.mdcr_el3, 14, 2); 2283 switch (spd) { 2284 case 1: 2285 /* SPD == 0b01 is reserved, but behaves as 0b00. */ 2286 case 0: 2287 /* For 0b00 we return true if external secure invasive debug 2288 * is enabled. On real hardware this is controlled by external 2289 * signals to the core. QEMU always permits debug, and behaves 2290 * as if DBGEN, SPIDEN, NIDEN and SPNIDEN are all tied high. 2291 */ 2292 return true; 2293 case 2: 2294 return false; 2295 case 3: 2296 return true; 2297 } 2298 } 2299 2300 return el != 2; 2301 } 2302 2303 /* Return true if debugging exceptions are currently enabled. 2304 * This corresponds to what in ARM ARM pseudocode would be 2305 * if UsingAArch32() then 2306 * return AArch32.GenerateDebugExceptions() 2307 * else 2308 * return AArch64.GenerateDebugExceptions() 2309 * We choose to push the if() down into this function for clarity, 2310 * since the pseudocode has it at all callsites except for the one in 2311 * CheckSoftwareStep(), where it is elided because both branches would 2312 * always return the same value. 2313 * 2314 * Parts of the pseudocode relating to EL2 and EL3 are omitted because we 2315 * don't yet implement those exception levels or their associated trap bits. 2316 */ 2317 static inline bool arm_generate_debug_exceptions(CPUARMState *env) 2318 { 2319 if (env->aarch64) { 2320 return aa64_generate_debug_exceptions(env); 2321 } else { 2322 return aa32_generate_debug_exceptions(env); 2323 } 2324 } 2325 2326 /* Is single-stepping active? (Note that the "is EL_D AArch64?" check 2327 * implicitly means this always returns false in pre-v8 CPUs.) 2328 */ 2329 static inline bool arm_singlestep_active(CPUARMState *env) 2330 { 2331 return extract32(env->cp15.mdscr_el1, 0, 1) 2332 && arm_el_is_aa64(env, arm_debug_target_el(env)) 2333 && arm_generate_debug_exceptions(env); 2334 } 2335 2336 static inline bool arm_sctlr_b(CPUARMState *env) 2337 { 2338 return 2339 /* We need not implement SCTLR.ITD in user-mode emulation, so 2340 * let linux-user ignore the fact that it conflicts with SCTLR_B. 2341 * This lets people run BE32 binaries with "-cpu any". 2342 */ 2343 #ifndef CONFIG_USER_ONLY 2344 !arm_feature(env, ARM_FEATURE_V7) && 2345 #endif 2346 (env->cp15.sctlr_el[1] & SCTLR_B) != 0; 2347 } 2348 2349 /* Return true if the processor is in big-endian mode. */ 2350 static inline bool arm_cpu_data_is_big_endian(CPUARMState *env) 2351 { 2352 int cur_el; 2353 2354 /* In 32bit endianness is determined by looking at CPSR's E bit */ 2355 if (!is_a64(env)) { 2356 return 2357 #ifdef CONFIG_USER_ONLY 2358 /* In system mode, BE32 is modelled in line with the 2359 * architecture (as word-invariant big-endianness), where loads 2360 * and stores are done little endian but from addresses which 2361 * are adjusted by XORing with the appropriate constant. So the 2362 * endianness to use for the raw data access is not affected by 2363 * SCTLR.B. 2364 * In user mode, however, we model BE32 as byte-invariant 2365 * big-endianness (because user-only code cannot tell the 2366 * difference), and so we need to use a data access endianness 2367 * that depends on SCTLR.B. 2368 */ 2369 arm_sctlr_b(env) || 2370 #endif 2371 ((env->uncached_cpsr & CPSR_E) ? 1 : 0); 2372 } 2373 2374 cur_el = arm_current_el(env); 2375 2376 if (cur_el == 0) { 2377 return (env->cp15.sctlr_el[1] & SCTLR_E0E) != 0; 2378 } 2379 2380 return (env->cp15.sctlr_el[cur_el] & SCTLR_EE) != 0; 2381 } 2382 2383 #include "exec/cpu-all.h" 2384 2385 /* Bit usage in the TB flags field: bit 31 indicates whether we are 2386 * in 32 or 64 bit mode. The meaning of the other bits depends on that. 2387 * We put flags which are shared between 32 and 64 bit mode at the top 2388 * of the word, and flags which apply to only one mode at the bottom. 2389 */ 2390 #define ARM_TBFLAG_AARCH64_STATE_SHIFT 31 2391 #define ARM_TBFLAG_AARCH64_STATE_MASK (1U << ARM_TBFLAG_AARCH64_STATE_SHIFT) 2392 #define ARM_TBFLAG_MMUIDX_SHIFT 28 2393 #define ARM_TBFLAG_MMUIDX_MASK (0x7 << ARM_TBFLAG_MMUIDX_SHIFT) 2394 #define ARM_TBFLAG_SS_ACTIVE_SHIFT 27 2395 #define ARM_TBFLAG_SS_ACTIVE_MASK (1 << ARM_TBFLAG_SS_ACTIVE_SHIFT) 2396 #define ARM_TBFLAG_PSTATE_SS_SHIFT 26 2397 #define ARM_TBFLAG_PSTATE_SS_MASK (1 << ARM_TBFLAG_PSTATE_SS_SHIFT) 2398 /* Target EL if we take a floating-point-disabled exception */ 2399 #define ARM_TBFLAG_FPEXC_EL_SHIFT 24 2400 #define ARM_TBFLAG_FPEXC_EL_MASK (0x3 << ARM_TBFLAG_FPEXC_EL_SHIFT) 2401 2402 /* Bit usage when in AArch32 state: */ 2403 #define ARM_TBFLAG_THUMB_SHIFT 0 2404 #define ARM_TBFLAG_THUMB_MASK (1 << ARM_TBFLAG_THUMB_SHIFT) 2405 #define ARM_TBFLAG_VECLEN_SHIFT 1 2406 #define ARM_TBFLAG_VECLEN_MASK (0x7 << ARM_TBFLAG_VECLEN_SHIFT) 2407 #define ARM_TBFLAG_VECSTRIDE_SHIFT 4 2408 #define ARM_TBFLAG_VECSTRIDE_MASK (0x3 << ARM_TBFLAG_VECSTRIDE_SHIFT) 2409 #define ARM_TBFLAG_VFPEN_SHIFT 7 2410 #define ARM_TBFLAG_VFPEN_MASK (1 << ARM_TBFLAG_VFPEN_SHIFT) 2411 #define ARM_TBFLAG_CONDEXEC_SHIFT 8 2412 #define ARM_TBFLAG_CONDEXEC_MASK (0xff << ARM_TBFLAG_CONDEXEC_SHIFT) 2413 #define ARM_TBFLAG_SCTLR_B_SHIFT 16 2414 #define ARM_TBFLAG_SCTLR_B_MASK (1 << ARM_TBFLAG_SCTLR_B_SHIFT) 2415 /* We store the bottom two bits of the CPAR as TB flags and handle 2416 * checks on the other bits at runtime 2417 */ 2418 #define ARM_TBFLAG_XSCALE_CPAR_SHIFT 17 2419 #define ARM_TBFLAG_XSCALE_CPAR_MASK (3 << ARM_TBFLAG_XSCALE_CPAR_SHIFT) 2420 /* Indicates whether cp register reads and writes by guest code should access 2421 * the secure or nonsecure bank of banked registers; note that this is not 2422 * the same thing as the current security state of the processor! 2423 */ 2424 #define ARM_TBFLAG_NS_SHIFT 19 2425 #define ARM_TBFLAG_NS_MASK (1 << ARM_TBFLAG_NS_SHIFT) 2426 #define ARM_TBFLAG_BE_DATA_SHIFT 20 2427 #define ARM_TBFLAG_BE_DATA_MASK (1 << ARM_TBFLAG_BE_DATA_SHIFT) 2428 /* For M profile only, Handler (ie not Thread) mode */ 2429 #define ARM_TBFLAG_HANDLER_SHIFT 21 2430 #define ARM_TBFLAG_HANDLER_MASK (1 << ARM_TBFLAG_HANDLER_SHIFT) 2431 2432 /* Bit usage when in AArch64 state */ 2433 #define ARM_TBFLAG_TBI0_SHIFT 0 /* TBI0 for EL0/1 or TBI for EL2/3 */ 2434 #define ARM_TBFLAG_TBI0_MASK (0x1ull << ARM_TBFLAG_TBI0_SHIFT) 2435 #define ARM_TBFLAG_TBI1_SHIFT 1 /* TBI1 for EL0/1 */ 2436 #define ARM_TBFLAG_TBI1_MASK (0x1ull << ARM_TBFLAG_TBI1_SHIFT) 2437 2438 /* some convenience accessor macros */ 2439 #define ARM_TBFLAG_AARCH64_STATE(F) \ 2440 (((F) & ARM_TBFLAG_AARCH64_STATE_MASK) >> ARM_TBFLAG_AARCH64_STATE_SHIFT) 2441 #define ARM_TBFLAG_MMUIDX(F) \ 2442 (((F) & ARM_TBFLAG_MMUIDX_MASK) >> ARM_TBFLAG_MMUIDX_SHIFT) 2443 #define ARM_TBFLAG_SS_ACTIVE(F) \ 2444 (((F) & ARM_TBFLAG_SS_ACTIVE_MASK) >> ARM_TBFLAG_SS_ACTIVE_SHIFT) 2445 #define ARM_TBFLAG_PSTATE_SS(F) \ 2446 (((F) & ARM_TBFLAG_PSTATE_SS_MASK) >> ARM_TBFLAG_PSTATE_SS_SHIFT) 2447 #define ARM_TBFLAG_FPEXC_EL(F) \ 2448 (((F) & ARM_TBFLAG_FPEXC_EL_MASK) >> ARM_TBFLAG_FPEXC_EL_SHIFT) 2449 #define ARM_TBFLAG_THUMB(F) \ 2450 (((F) & ARM_TBFLAG_THUMB_MASK) >> ARM_TBFLAG_THUMB_SHIFT) 2451 #define ARM_TBFLAG_VECLEN(F) \ 2452 (((F) & ARM_TBFLAG_VECLEN_MASK) >> ARM_TBFLAG_VECLEN_SHIFT) 2453 #define ARM_TBFLAG_VECSTRIDE(F) \ 2454 (((F) & ARM_TBFLAG_VECSTRIDE_MASK) >> ARM_TBFLAG_VECSTRIDE_SHIFT) 2455 #define ARM_TBFLAG_VFPEN(F) \ 2456 (((F) & ARM_TBFLAG_VFPEN_MASK) >> ARM_TBFLAG_VFPEN_SHIFT) 2457 #define ARM_TBFLAG_CONDEXEC(F) \ 2458 (((F) & ARM_TBFLAG_CONDEXEC_MASK) >> ARM_TBFLAG_CONDEXEC_SHIFT) 2459 #define ARM_TBFLAG_SCTLR_B(F) \ 2460 (((F) & ARM_TBFLAG_SCTLR_B_MASK) >> ARM_TBFLAG_SCTLR_B_SHIFT) 2461 #define ARM_TBFLAG_XSCALE_CPAR(F) \ 2462 (((F) & ARM_TBFLAG_XSCALE_CPAR_MASK) >> ARM_TBFLAG_XSCALE_CPAR_SHIFT) 2463 #define ARM_TBFLAG_NS(F) \ 2464 (((F) & ARM_TBFLAG_NS_MASK) >> ARM_TBFLAG_NS_SHIFT) 2465 #define ARM_TBFLAG_BE_DATA(F) \ 2466 (((F) & ARM_TBFLAG_BE_DATA_MASK) >> ARM_TBFLAG_BE_DATA_SHIFT) 2467 #define ARM_TBFLAG_HANDLER(F) \ 2468 (((F) & ARM_TBFLAG_HANDLER_MASK) >> ARM_TBFLAG_HANDLER_SHIFT) 2469 #define ARM_TBFLAG_TBI0(F) \ 2470 (((F) & ARM_TBFLAG_TBI0_MASK) >> ARM_TBFLAG_TBI0_SHIFT) 2471 #define ARM_TBFLAG_TBI1(F) \ 2472 (((F) & ARM_TBFLAG_TBI1_MASK) >> ARM_TBFLAG_TBI1_SHIFT) 2473 2474 static inline bool bswap_code(bool sctlr_b) 2475 { 2476 #ifdef CONFIG_USER_ONLY 2477 /* BE8 (SCTLR.B = 0, TARGET_WORDS_BIGENDIAN = 1) is mixed endian. 2478 * The invalid combination SCTLR.B=1/CPSR.E=1/TARGET_WORDS_BIGENDIAN=0 2479 * would also end up as a mixed-endian mode with BE code, LE data. 2480 */ 2481 return 2482 #ifdef TARGET_WORDS_BIGENDIAN 2483 1 ^ 2484 #endif 2485 sctlr_b; 2486 #else 2487 /* All code access in ARM is little endian, and there are no loaders 2488 * doing swaps that need to be reversed 2489 */ 2490 return 0; 2491 #endif 2492 } 2493 2494 /* Return the exception level to which FP-disabled exceptions should 2495 * be taken, or 0 if FP is enabled. 2496 */ 2497 static inline int fp_exception_el(CPUARMState *env) 2498 { 2499 int fpen; 2500 int cur_el = arm_current_el(env); 2501 2502 /* CPACR and the CPTR registers don't exist before v6, so FP is 2503 * always accessible 2504 */ 2505 if (!arm_feature(env, ARM_FEATURE_V6)) { 2506 return 0; 2507 } 2508 2509 /* The CPACR controls traps to EL1, or PL1 if we're 32 bit: 2510 * 0, 2 : trap EL0 and EL1/PL1 accesses 2511 * 1 : trap only EL0 accesses 2512 * 3 : trap no accesses 2513 */ 2514 fpen = extract32(env->cp15.cpacr_el1, 20, 2); 2515 switch (fpen) { 2516 case 0: 2517 case 2: 2518 if (cur_el == 0 || cur_el == 1) { 2519 /* Trap to PL1, which might be EL1 or EL3 */ 2520 if (arm_is_secure(env) && !arm_el_is_aa64(env, 3)) { 2521 return 3; 2522 } 2523 return 1; 2524 } 2525 if (cur_el == 3 && !is_a64(env)) { 2526 /* Secure PL1 running at EL3 */ 2527 return 3; 2528 } 2529 break; 2530 case 1: 2531 if (cur_el == 0) { 2532 return 1; 2533 } 2534 break; 2535 case 3: 2536 break; 2537 } 2538 2539 /* For the CPTR registers we don't need to guard with an ARM_FEATURE 2540 * check because zero bits in the registers mean "don't trap". 2541 */ 2542 2543 /* CPTR_EL2 : present in v7VE or v8 */ 2544 if (cur_el <= 2 && extract32(env->cp15.cptr_el[2], 10, 1) 2545 && !arm_is_secure_below_el3(env)) { 2546 /* Trap FP ops at EL2, NS-EL1 or NS-EL0 to EL2 */ 2547 return 2; 2548 } 2549 2550 /* CPTR_EL3 : present in v8 */ 2551 if (extract32(env->cp15.cptr_el[3], 10, 1)) { 2552 /* Trap all FP ops to EL3 */ 2553 return 3; 2554 } 2555 2556 return 0; 2557 } 2558 2559 #ifdef CONFIG_USER_ONLY 2560 static inline bool arm_cpu_bswap_data(CPUARMState *env) 2561 { 2562 return 2563 #ifdef TARGET_WORDS_BIGENDIAN 2564 1 ^ 2565 #endif 2566 arm_cpu_data_is_big_endian(env); 2567 } 2568 #endif 2569 2570 #ifndef CONFIG_USER_ONLY 2571 /** 2572 * arm_regime_tbi0: 2573 * @env: CPUARMState 2574 * @mmu_idx: MMU index indicating required translation regime 2575 * 2576 * Extracts the TBI0 value from the appropriate TCR for the current EL 2577 * 2578 * Returns: the TBI0 value. 2579 */ 2580 uint32_t arm_regime_tbi0(CPUARMState *env, ARMMMUIdx mmu_idx); 2581 2582 /** 2583 * arm_regime_tbi1: 2584 * @env: CPUARMState 2585 * @mmu_idx: MMU index indicating required translation regime 2586 * 2587 * Extracts the TBI1 value from the appropriate TCR for the current EL 2588 * 2589 * Returns: the TBI1 value. 2590 */ 2591 uint32_t arm_regime_tbi1(CPUARMState *env, ARMMMUIdx mmu_idx); 2592 #else 2593 /* We can't handle tagged addresses properly in user-only mode */ 2594 static inline uint32_t arm_regime_tbi0(CPUARMState *env, ARMMMUIdx mmu_idx) 2595 { 2596 return 0; 2597 } 2598 2599 static inline uint32_t arm_regime_tbi1(CPUARMState *env, ARMMMUIdx mmu_idx) 2600 { 2601 return 0; 2602 } 2603 #endif 2604 2605 static inline void cpu_get_tb_cpu_state(CPUARMState *env, target_ulong *pc, 2606 target_ulong *cs_base, uint32_t *flags) 2607 { 2608 ARMMMUIdx mmu_idx = core_to_arm_mmu_idx(env, cpu_mmu_index(env, false)); 2609 if (is_a64(env)) { 2610 *pc = env->pc; 2611 *flags = ARM_TBFLAG_AARCH64_STATE_MASK; 2612 /* Get control bits for tagged addresses */ 2613 *flags |= (arm_regime_tbi0(env, mmu_idx) << ARM_TBFLAG_TBI0_SHIFT); 2614 *flags |= (arm_regime_tbi1(env, mmu_idx) << ARM_TBFLAG_TBI1_SHIFT); 2615 } else { 2616 *pc = env->regs[15]; 2617 *flags = (env->thumb << ARM_TBFLAG_THUMB_SHIFT) 2618 | (env->vfp.vec_len << ARM_TBFLAG_VECLEN_SHIFT) 2619 | (env->vfp.vec_stride << ARM_TBFLAG_VECSTRIDE_SHIFT) 2620 | (env->condexec_bits << ARM_TBFLAG_CONDEXEC_SHIFT) 2621 | (arm_sctlr_b(env) << ARM_TBFLAG_SCTLR_B_SHIFT); 2622 if (!(access_secure_reg(env))) { 2623 *flags |= ARM_TBFLAG_NS_MASK; 2624 } 2625 if (env->vfp.xregs[ARM_VFP_FPEXC] & (1 << 30) 2626 || arm_el_is_aa64(env, 1)) { 2627 *flags |= ARM_TBFLAG_VFPEN_MASK; 2628 } 2629 *flags |= (extract32(env->cp15.c15_cpar, 0, 2) 2630 << ARM_TBFLAG_XSCALE_CPAR_SHIFT); 2631 } 2632 2633 *flags |= (arm_to_core_mmu_idx(mmu_idx) << ARM_TBFLAG_MMUIDX_SHIFT); 2634 2635 /* The SS_ACTIVE and PSTATE_SS bits correspond to the state machine 2636 * states defined in the ARM ARM for software singlestep: 2637 * SS_ACTIVE PSTATE.SS State 2638 * 0 x Inactive (the TB flag for SS is always 0) 2639 * 1 0 Active-pending 2640 * 1 1 Active-not-pending 2641 */ 2642 if (arm_singlestep_active(env)) { 2643 *flags |= ARM_TBFLAG_SS_ACTIVE_MASK; 2644 if (is_a64(env)) { 2645 if (env->pstate & PSTATE_SS) { 2646 *flags |= ARM_TBFLAG_PSTATE_SS_MASK; 2647 } 2648 } else { 2649 if (env->uncached_cpsr & PSTATE_SS) { 2650 *flags |= ARM_TBFLAG_PSTATE_SS_MASK; 2651 } 2652 } 2653 } 2654 if (arm_cpu_data_is_big_endian(env)) { 2655 *flags |= ARM_TBFLAG_BE_DATA_MASK; 2656 } 2657 *flags |= fp_exception_el(env) << ARM_TBFLAG_FPEXC_EL_SHIFT; 2658 2659 if (arm_v7m_is_handler_mode(env)) { 2660 *flags |= ARM_TBFLAG_HANDLER_MASK; 2661 } 2662 2663 *cs_base = 0; 2664 } 2665 2666 enum { 2667 QEMU_PSCI_CONDUIT_DISABLED = 0, 2668 QEMU_PSCI_CONDUIT_SMC = 1, 2669 QEMU_PSCI_CONDUIT_HVC = 2, 2670 }; 2671 2672 #ifndef CONFIG_USER_ONLY 2673 /* Return the address space index to use for a memory access */ 2674 static inline int arm_asidx_from_attrs(CPUState *cs, MemTxAttrs attrs) 2675 { 2676 return attrs.secure ? ARMASIdx_S : ARMASIdx_NS; 2677 } 2678 2679 /* Return the AddressSpace to use for a memory access 2680 * (which depends on whether the access is S or NS, and whether 2681 * the board gave us a separate AddressSpace for S accesses). 2682 */ 2683 static inline AddressSpace *arm_addressspace(CPUState *cs, MemTxAttrs attrs) 2684 { 2685 return cpu_get_address_space(cs, arm_asidx_from_attrs(cs, attrs)); 2686 } 2687 #endif 2688 2689 /** 2690 * arm_register_el_change_hook: 2691 * Register a hook function which will be called back whenever this 2692 * CPU changes exception level or mode. The hook function will be 2693 * passed a pointer to the ARMCPU and the opaque data pointer passed 2694 * to this function when the hook was registered. 2695 * 2696 * Note that we currently only support registering a single hook function, 2697 * and will assert if this function is called twice. 2698 * This facility is intended for the use of the GICv3 emulation. 2699 */ 2700 void arm_register_el_change_hook(ARMCPU *cpu, ARMELChangeHook *hook, 2701 void *opaque); 2702 2703 /** 2704 * arm_get_el_change_hook_opaque: 2705 * Return the opaque data that will be used by the el_change_hook 2706 * for this CPU. 2707 */ 2708 static inline void *arm_get_el_change_hook_opaque(ARMCPU *cpu) 2709 { 2710 return cpu->el_change_hook_opaque; 2711 } 2712 2713 #endif 2714