1 /* 2 * ARM virtual CPU header 3 * 4 * Copyright (c) 2003 Fabrice Bellard 5 * 6 * This library is free software; you can redistribute it and/or 7 * modify it under the terms of the GNU Lesser General Public 8 * License as published by the Free Software Foundation; either 9 * version 2.1 of the License, or (at your option) any later version. 10 * 11 * This library is distributed in the hope that it will be useful, 12 * but WITHOUT ANY WARRANTY; without even the implied warranty of 13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU 14 * Lesser General Public License for more details. 15 * 16 * You should have received a copy of the GNU Lesser General Public 17 * License along with this library; if not, see <http://www.gnu.org/licenses/>. 18 */ 19 20 #ifndef ARM_CPU_H 21 #define ARM_CPU_H 22 23 #include "kvm-consts.h" 24 #include "qemu/cpu-float.h" 25 #include "hw/registerfields.h" 26 #include "cpu-qom.h" 27 #include "exec/cpu-common.h" 28 #include "exec/cpu-defs.h" 29 #include "exec/cpu-interrupt.h" 30 #include "exec/gdbstub.h" 31 #include "exec/page-protection.h" 32 #include "qapi/qapi-types-common.h" 33 #include "target/arm/multiprocessing.h" 34 #include "target/arm/gtimer.h" 35 36 #ifdef TARGET_AARCH64 37 #define KVM_HAVE_MCE_INJECTION 1 38 #endif 39 40 #define EXCP_UDEF 1 /* undefined instruction */ 41 #define EXCP_SWI 2 /* software interrupt */ 42 #define EXCP_PREFETCH_ABORT 3 43 #define EXCP_DATA_ABORT 4 44 #define EXCP_IRQ 5 45 #define EXCP_FIQ 6 46 #define EXCP_BKPT 7 47 #define EXCP_EXCEPTION_EXIT 8 /* Return from v7M exception. */ 48 #define EXCP_KERNEL_TRAP 9 /* Jumped to kernel code page. */ 49 #define EXCP_HVC 11 /* HyperVisor Call */ 50 #define EXCP_HYP_TRAP 12 51 #define EXCP_SMC 13 /* Secure Monitor Call */ 52 #define EXCP_VIRQ 14 53 #define EXCP_VFIQ 15 54 #define EXCP_SEMIHOST 16 /* semihosting call */ 55 #define EXCP_NOCP 17 /* v7M NOCP UsageFault */ 56 #define EXCP_INVSTATE 18 /* v7M INVSTATE UsageFault */ 57 #define EXCP_STKOF 19 /* v8M STKOF UsageFault */ 58 #define EXCP_LAZYFP 20 /* v7M fault during lazy FP stacking */ 59 #define EXCP_LSERR 21 /* v8M LSERR SecureFault */ 60 #define EXCP_UNALIGNED 22 /* v7M UNALIGNED UsageFault */ 61 #define EXCP_DIVBYZERO 23 /* v7M DIVBYZERO UsageFault */ 62 #define EXCP_VSERR 24 63 #define EXCP_GPC 25 /* v9 Granule Protection Check Fault */ 64 #define EXCP_NMI 26 65 #define EXCP_VINMI 27 66 #define EXCP_VFNMI 28 67 #define EXCP_MON_TRAP 29 /* AArch32 trap to Monitor mode */ 68 /* NB: add new EXCP_ defines to the array in arm_log_exception() too */ 69 70 #define ARMV7M_EXCP_RESET 1 71 #define ARMV7M_EXCP_NMI 2 72 #define ARMV7M_EXCP_HARD 3 73 #define ARMV7M_EXCP_MEM 4 74 #define ARMV7M_EXCP_BUS 5 75 #define ARMV7M_EXCP_USAGE 6 76 #define ARMV7M_EXCP_SECURE 7 77 #define ARMV7M_EXCP_SVC 11 78 #define ARMV7M_EXCP_DEBUG 12 79 #define ARMV7M_EXCP_PENDSV 14 80 #define ARMV7M_EXCP_SYSTICK 15 81 82 /* ARM-specific interrupt pending bits. */ 83 #define CPU_INTERRUPT_FIQ CPU_INTERRUPT_TGT_EXT_1 84 #define CPU_INTERRUPT_VIRQ CPU_INTERRUPT_TGT_EXT_2 85 #define CPU_INTERRUPT_VFIQ CPU_INTERRUPT_TGT_EXT_3 86 #define CPU_INTERRUPT_VSERR CPU_INTERRUPT_TGT_INT_0 87 #define CPU_INTERRUPT_NMI CPU_INTERRUPT_TGT_EXT_4 88 #define CPU_INTERRUPT_VINMI CPU_INTERRUPT_TGT_EXT_0 89 #define CPU_INTERRUPT_VFNMI CPU_INTERRUPT_TGT_INT_1 90 91 /* The usual mapping for an AArch64 system register to its AArch32 92 * counterpart is for the 32 bit world to have access to the lower 93 * half only (with writes leaving the upper half untouched). It's 94 * therefore useful to be able to pass TCG the offset of the least 95 * significant half of a uint64_t struct member. 96 */ 97 #if HOST_BIG_ENDIAN 98 #define offsetoflow32(S, M) (offsetof(S, M) + sizeof(uint32_t)) 99 #define offsetofhigh32(S, M) offsetof(S, M) 100 #else 101 #define offsetoflow32(S, M) offsetof(S, M) 102 #define offsetofhigh32(S, M) (offsetof(S, M) + sizeof(uint32_t)) 103 #endif 104 105 /* ARM-specific extra insn start words: 106 * 1: Conditional execution bits 107 * 2: Partial exception syndrome for data aborts 108 */ 109 #define TARGET_INSN_START_EXTRA_WORDS 2 110 111 /* The 2nd extra word holding syndrome info for data aborts does not use 112 * the upper 6 bits nor the lower 13 bits. We mask and shift it down to 113 * help the sleb128 encoder do a better job. 114 * When restoring the CPU state, we shift it back up. 115 */ 116 #define ARM_INSN_START_WORD2_MASK ((1 << 26) - 1) 117 #define ARM_INSN_START_WORD2_SHIFT 13 118 119 /* We currently assume float and double are IEEE single and double 120 precision respectively. 121 Doing runtime conversions is tricky because VFP registers may contain 122 integer values (eg. as the result of a FTOSI instruction). 123 s<2n> maps to the least significant half of d<n> 124 s<2n+1> maps to the most significant half of d<n> 125 */ 126 127 /** 128 * DynamicGDBFeatureInfo: 129 * @desc: Contains the feature descriptions. 130 * @data: A union with data specific to the set of registers 131 * @cpregs_keys: Array that contains the corresponding Key of 132 * a given cpreg with the same order of the cpreg 133 * in the XML description. 134 */ 135 typedef struct DynamicGDBFeatureInfo { 136 GDBFeature desc; 137 union { 138 struct { 139 uint32_t *keys; 140 } cpregs; 141 } data; 142 } DynamicGDBFeatureInfo; 143 144 /* CPU state for each instance of a generic timer (in cp15 c14) */ 145 typedef struct ARMGenericTimer { 146 uint64_t cval; /* Timer CompareValue register */ 147 uint64_t ctl; /* Timer Control register */ 148 } ARMGenericTimer; 149 150 /* Define a maximum sized vector register. 151 * For 32-bit, this is a 128-bit NEON/AdvSIMD register. 152 * For 64-bit, this is a 2048-bit SVE register. 153 * 154 * Note that the mapping between S, D, and Q views of the register bank 155 * differs between AArch64 and AArch32. 156 * In AArch32: 157 * Qn = regs[n].d[1]:regs[n].d[0] 158 * Dn = regs[n / 2].d[n & 1] 159 * Sn = regs[n / 4].d[n % 4 / 2], 160 * bits 31..0 for even n, and bits 63..32 for odd n 161 * (and regs[16] to regs[31] are inaccessible) 162 * In AArch64: 163 * Zn = regs[n].d[*] 164 * Qn = regs[n].d[1]:regs[n].d[0] 165 * Dn = regs[n].d[0] 166 * Sn = regs[n].d[0] bits 31..0 167 * Hn = regs[n].d[0] bits 15..0 168 * 169 * This corresponds to the architecturally defined mapping between 170 * the two execution states, and means we do not need to explicitly 171 * map these registers when changing states. 172 * 173 * Align the data for use with TCG host vector operations. 174 */ 175 176 #ifdef TARGET_AARCH64 177 # define ARM_MAX_VQ 16 178 #else 179 # define ARM_MAX_VQ 1 180 #endif 181 182 typedef struct ARMVectorReg { 183 uint64_t d[2 * ARM_MAX_VQ] QEMU_ALIGNED(16); 184 } ARMVectorReg; 185 186 #ifdef TARGET_AARCH64 187 /* In AArch32 mode, predicate registers do not exist at all. */ 188 typedef struct ARMPredicateReg { 189 uint64_t p[DIV_ROUND_UP(2 * ARM_MAX_VQ, 8)] QEMU_ALIGNED(16); 190 } ARMPredicateReg; 191 192 /* In AArch32 mode, PAC keys do not exist at all. */ 193 typedef struct ARMPACKey { 194 uint64_t lo, hi; 195 } ARMPACKey; 196 #endif 197 198 /* See the commentary above the TBFLAG field definitions. */ 199 typedef struct CPUARMTBFlags { 200 uint32_t flags; 201 target_ulong flags2; 202 } CPUARMTBFlags; 203 204 typedef struct ARMMMUFaultInfo ARMMMUFaultInfo; 205 206 typedef struct NVICState NVICState; 207 208 /* 209 * Enum for indexing vfp.fp_status[]. 210 * 211 * FPST_A32: is the "normal" fp status for AArch32 insns 212 * FPST_A64: is the "normal" fp status for AArch64 insns 213 * FPST_A32_F16: used for AArch32 half-precision calculations 214 * FPST_A64_F16: used for AArch64 half-precision calculations 215 * FPST_STD: the ARM "Standard FPSCR Value" 216 * FPST_STD_F16: used for half-precision 217 * calculations with the ARM "Standard FPSCR Value" 218 * FPST_AH: used for the A64 insns which change behaviour 219 * when FPCR.AH == 1 (bfloat16 conversions and multiplies, 220 * and the reciprocal and square root estimate/step insns) 221 * FPST_AH_F16: used for the A64 insns which change behaviour 222 * when FPCR.AH == 1 (bfloat16 conversions and multiplies, 223 * and the reciprocal and square root estimate/step insns); 224 * for half-precision 225 * 226 * Half-precision operations are governed by a separate 227 * flush-to-zero control bit in FPSCR:FZ16. We pass a separate 228 * status structure to control this. 229 * 230 * The "Standard FPSCR", ie default-NaN, flush-to-zero, 231 * round-to-nearest and is used by any operations (generally 232 * Neon) which the architecture defines as controlled by the 233 * standard FPSCR value rather than the FPSCR. 234 * 235 * The "standard FPSCR but for fp16 ops" is needed because 236 * the "standard FPSCR" tracks the FPSCR.FZ16 bit rather than 237 * using a fixed value for it. 238 * 239 * FPST_AH is needed because some insns have different 240 * behaviour when FPCR.AH == 1: they don't update cumulative 241 * exception flags, they act like FPCR.{FZ,FIZ} = {1,1} and 242 * they ignore FPCR.RMode. But they don't ignore FPCR.FZ16, 243 * which means we need an FPST_AH_F16 as well. 244 * 245 * To avoid having to transfer exception bits around, we simply 246 * say that the FPSCR cumulative exception flags are the logical 247 * OR of the flags in the four fp statuses. This relies on the 248 * only thing which needs to read the exception flags being 249 * an explicit FPSCR read. 250 */ 251 typedef enum ARMFPStatusFlavour { 252 FPST_A32, 253 FPST_A64, 254 FPST_A32_F16, 255 FPST_A64_F16, 256 FPST_AH, 257 FPST_AH_F16, 258 FPST_STD, 259 FPST_STD_F16, 260 } ARMFPStatusFlavour; 261 #define FPST_COUNT 8 262 263 typedef struct CPUArchState { 264 /* Regs for current mode. */ 265 uint32_t regs[16]; 266 267 /* 32/64 switch only happens when taking and returning from 268 * exceptions so the overlap semantics are taken care of then 269 * instead of having a complicated union. 270 */ 271 /* Regs for A64 mode. */ 272 uint64_t xregs[32]; 273 uint64_t pc; 274 /* PSTATE isn't an architectural register for ARMv8. However, it is 275 * convenient for us to assemble the underlying state into a 32 bit format 276 * identical to the architectural format used for the SPSR. (This is also 277 * what the Linux kernel's 'pstate' field in signal handlers and KVM's 278 * 'pstate' register are.) Of the PSTATE bits: 279 * NZCV are kept in the split out env->CF/VF/NF/ZF, (which have the same 280 * semantics as for AArch32, as described in the comments on each field) 281 * nRW (also known as M[4]) is kept, inverted, in env->aarch64 282 * DAIF (exception masks) are kept in env->daif 283 * BTYPE is kept in env->btype 284 * SM and ZA are kept in env->svcr 285 * all other bits are stored in their correct places in env->pstate 286 */ 287 uint32_t pstate; 288 bool aarch64; /* True if CPU is in aarch64 state; inverse of PSTATE.nRW */ 289 bool thumb; /* True if CPU is in thumb mode; cpsr[5] */ 290 291 /* Cached TBFLAGS state. See below for which bits are included. */ 292 CPUARMTBFlags hflags; 293 294 /* Frequently accessed CPSR bits are stored separately for efficiency. 295 This contains all the other bits. Use cpsr_{read,write} to access 296 the whole CPSR. */ 297 uint32_t uncached_cpsr; 298 uint32_t spsr; 299 300 /* Banked registers. */ 301 uint64_t banked_spsr[8]; 302 uint32_t banked_r13[8]; 303 uint32_t banked_r14[8]; 304 305 /* These hold r8-r12. */ 306 uint32_t usr_regs[5]; 307 uint32_t fiq_regs[5]; 308 309 /* cpsr flag cache for faster execution */ 310 uint32_t CF; /* 0 or 1 */ 311 uint32_t VF; /* V is the bit 31. All other bits are undefined */ 312 uint32_t NF; /* N is bit 31. All other bits are undefined. */ 313 uint32_t ZF; /* Z set if zero. */ 314 uint32_t QF; /* 0 or 1 */ 315 uint32_t GE; /* cpsr[19:16] */ 316 uint32_t condexec_bits; /* IT bits. cpsr[15:10,26:25]. */ 317 uint32_t btype; /* BTI branch type. spsr[11:10]. */ 318 uint64_t daif; /* exception masks, in the bits they are in PSTATE */ 319 uint64_t svcr; /* PSTATE.{SM,ZA} in the bits they are in SVCR */ 320 321 uint64_t elr_el[4]; /* AArch64 exception link regs */ 322 uint64_t sp_el[4]; /* AArch64 banked stack pointers */ 323 324 /* System control coprocessor (cp15) */ 325 struct { 326 uint32_t c0_cpuid; 327 union { /* Cache size selection */ 328 struct { 329 uint64_t _unused_csselr0; 330 uint64_t csselr_ns; 331 uint64_t _unused_csselr1; 332 uint64_t csselr_s; 333 }; 334 uint64_t csselr_el[4]; 335 }; 336 union { /* System control register. */ 337 struct { 338 uint64_t _unused_sctlr; 339 uint64_t sctlr_ns; 340 uint64_t hsctlr; 341 uint64_t sctlr_s; 342 }; 343 uint64_t sctlr_el[4]; 344 }; 345 uint64_t vsctlr; /* Virtualization System control register. */ 346 uint64_t cpacr_el1; /* Architectural feature access control register */ 347 uint64_t cptr_el[4]; /* ARMv8 feature trap registers */ 348 uint32_t c1_xscaleauxcr; /* XScale auxiliary control register. */ 349 uint64_t sder; /* Secure debug enable register. */ 350 uint32_t nsacr; /* Non-secure access control register. */ 351 union { /* MMU translation table base 0. */ 352 struct { 353 uint64_t _unused_ttbr0_0; 354 uint64_t ttbr0_ns; 355 uint64_t _unused_ttbr0_1; 356 uint64_t ttbr0_s; 357 }; 358 uint64_t ttbr0_el[4]; 359 }; 360 union { /* MMU translation table base 1. */ 361 struct { 362 uint64_t _unused_ttbr1_0; 363 uint64_t ttbr1_ns; 364 uint64_t _unused_ttbr1_1; 365 uint64_t ttbr1_s; 366 }; 367 uint64_t ttbr1_el[4]; 368 }; 369 uint64_t vttbr_el2; /* Virtualization Translation Table Base. */ 370 uint64_t vsttbr_el2; /* Secure Virtualization Translation Table. */ 371 /* MMU translation table base control. */ 372 uint64_t tcr_el[4]; 373 uint64_t vtcr_el2; /* Virtualization Translation Control. */ 374 uint64_t vstcr_el2; /* Secure Virtualization Translation Control. */ 375 uint32_t c2_data; /* MPU data cacheable bits. */ 376 uint32_t c2_insn; /* MPU instruction cacheable bits. */ 377 union { /* MMU domain access control register 378 * MPU write buffer control. 379 */ 380 struct { 381 uint64_t dacr_ns; 382 uint64_t dacr_s; 383 }; 384 struct { 385 uint64_t dacr32_el2; 386 }; 387 }; 388 uint32_t pmsav5_data_ap; /* PMSAv5 MPU data access permissions */ 389 uint32_t pmsav5_insn_ap; /* PMSAv5 MPU insn access permissions */ 390 uint64_t hcr_el2; /* Hypervisor configuration register */ 391 uint64_t hcrx_el2; /* Extended Hypervisor configuration register */ 392 uint64_t scr_el3; /* Secure configuration register. */ 393 union { /* Fault status registers. */ 394 struct { 395 uint64_t ifsr_ns; 396 uint64_t ifsr_s; 397 }; 398 struct { 399 uint64_t ifsr32_el2; 400 }; 401 }; 402 union { 403 struct { 404 uint64_t _unused_dfsr; 405 uint64_t dfsr_ns; 406 uint64_t hsr; 407 uint64_t dfsr_s; 408 }; 409 uint64_t esr_el[4]; 410 }; 411 uint32_t c6_region[8]; /* MPU base/size registers. */ 412 union { /* Fault address registers. */ 413 struct { 414 uint64_t _unused_far0; 415 #if HOST_BIG_ENDIAN 416 uint32_t ifar_ns; 417 uint32_t dfar_ns; 418 uint32_t ifar_s; 419 uint32_t dfar_s; 420 #else 421 uint32_t dfar_ns; 422 uint32_t ifar_ns; 423 uint32_t dfar_s; 424 uint32_t ifar_s; 425 #endif 426 uint64_t _unused_far3; 427 }; 428 uint64_t far_el[4]; 429 }; 430 uint64_t hpfar_el2; 431 uint64_t hstr_el2; 432 union { /* Translation result. */ 433 struct { 434 uint64_t _unused_par_0; 435 uint64_t par_ns; 436 uint64_t _unused_par_1; 437 uint64_t par_s; 438 }; 439 uint64_t par_el[4]; 440 }; 441 442 uint32_t c9_insn; /* Cache lockdown registers. */ 443 uint32_t c9_data; 444 uint64_t c9_pmcr; /* performance monitor control register */ 445 uint64_t c9_pmcnten; /* perf monitor counter enables */ 446 uint64_t c9_pmovsr; /* perf monitor overflow status */ 447 uint64_t c9_pmuserenr; /* perf monitor user enable */ 448 uint64_t c9_pmselr; /* perf monitor counter selection register */ 449 uint64_t c9_pminten; /* perf monitor interrupt enables */ 450 union { /* Memory attribute redirection */ 451 struct { 452 #if HOST_BIG_ENDIAN 453 uint64_t _unused_mair_0; 454 uint32_t mair1_ns; 455 uint32_t mair0_ns; 456 uint64_t _unused_mair_1; 457 uint32_t mair1_s; 458 uint32_t mair0_s; 459 #else 460 uint64_t _unused_mair_0; 461 uint32_t mair0_ns; 462 uint32_t mair1_ns; 463 uint64_t _unused_mair_1; 464 uint32_t mair0_s; 465 uint32_t mair1_s; 466 #endif 467 }; 468 uint64_t mair_el[4]; 469 }; 470 union { /* vector base address register */ 471 struct { 472 uint64_t _unused_vbar; 473 uint64_t vbar_ns; 474 uint64_t hvbar; 475 uint64_t vbar_s; 476 }; 477 uint64_t vbar_el[4]; 478 }; 479 uint32_t mvbar; /* (monitor) vector base address register */ 480 uint64_t rvbar; /* rvbar sampled from rvbar property at reset */ 481 struct { /* FCSE PID. */ 482 uint32_t fcseidr_ns; 483 uint32_t fcseidr_s; 484 }; 485 union { /* Context ID. */ 486 struct { 487 uint64_t _unused_contextidr_0; 488 uint64_t contextidr_ns; 489 uint64_t _unused_contextidr_1; 490 uint64_t contextidr_s; 491 }; 492 uint64_t contextidr_el[4]; 493 }; 494 union { /* User RW Thread register. */ 495 struct { 496 uint64_t tpidrurw_ns; 497 uint64_t tpidrprw_ns; 498 uint64_t htpidr; 499 uint64_t _tpidr_el3; 500 }; 501 uint64_t tpidr_el[4]; 502 }; 503 uint64_t tpidr2_el0; 504 /* The secure banks of these registers don't map anywhere */ 505 uint64_t tpidrurw_s; 506 uint64_t tpidrprw_s; 507 uint64_t tpidruro_s; 508 509 union { /* User RO Thread register. */ 510 uint64_t tpidruro_ns; 511 uint64_t tpidrro_el[1]; 512 }; 513 uint64_t c14_cntfrq; /* Counter Frequency register */ 514 uint64_t c14_cntkctl; /* Timer Control register */ 515 uint64_t cnthctl_el2; /* Counter/Timer Hyp Control register */ 516 uint64_t cntvoff_el2; /* Counter Virtual Offset register */ 517 uint64_t cntpoff_el2; /* Counter Physical Offset register */ 518 ARMGenericTimer c14_timer[NUM_GTIMERS]; 519 uint32_t c15_cpar; /* XScale Coprocessor Access Register */ 520 uint32_t c15_ticonfig; /* TI925T configuration byte. */ 521 uint32_t c15_i_max; /* Maximum D-cache dirty line index. */ 522 uint32_t c15_i_min; /* Minimum D-cache dirty line index. */ 523 uint32_t c15_threadid; /* TI debugger thread-ID. */ 524 uint32_t c15_config_base_address; /* SCU base address. */ 525 uint32_t c15_diagnostic; /* diagnostic register */ 526 uint32_t c15_power_diagnostic; 527 uint32_t c15_power_control; /* power control */ 528 uint64_t dbgbvr[16]; /* breakpoint value registers */ 529 uint64_t dbgbcr[16]; /* breakpoint control registers */ 530 uint64_t dbgwvr[16]; /* watchpoint value registers */ 531 uint64_t dbgwcr[16]; /* watchpoint control registers */ 532 uint64_t dbgclaim; /* DBGCLAIM bits */ 533 uint64_t mdscr_el1; 534 uint64_t oslsr_el1; /* OS Lock Status */ 535 uint64_t osdlr_el1; /* OS DoubleLock status */ 536 uint64_t mdcr_el2; 537 uint64_t mdcr_el3; 538 /* Stores the architectural value of the counter *the last time it was 539 * updated* by pmccntr_op_start. Accesses should always be surrounded 540 * by pmccntr_op_start/pmccntr_op_finish to guarantee the latest 541 * architecturally-correct value is being read/set. 542 */ 543 uint64_t c15_ccnt; 544 /* Stores the delta between the architectural value and the underlying 545 * cycle count during normal operation. It is used to update c15_ccnt 546 * to be the correct architectural value before accesses. During 547 * accesses, c15_ccnt_delta contains the underlying count being used 548 * for the access, after which it reverts to the delta value in 549 * pmccntr_op_finish. 550 */ 551 uint64_t c15_ccnt_delta; 552 uint64_t c14_pmevcntr[31]; 553 uint64_t c14_pmevcntr_delta[31]; 554 uint64_t c14_pmevtyper[31]; 555 uint64_t pmccfiltr_el0; /* Performance Monitor Filter Register */ 556 uint64_t vpidr_el2; /* Virtualization Processor ID Register */ 557 uint64_t vmpidr_el2; /* Virtualization Multiprocessor ID Register */ 558 uint64_t tfsr_el[4]; /* tfsre0_el1 is index 0. */ 559 uint64_t gcr_el1; 560 uint64_t rgsr_el1; 561 562 /* Minimal RAS registers */ 563 uint64_t disr_el1; 564 uint64_t vdisr_el2; 565 uint64_t vsesr_el2; 566 567 /* 568 * Fine-Grained Trap registers. We store these as arrays so the 569 * access checking code doesn't have to manually select 570 * HFGRTR_EL2 vs HFDFGRTR_EL2 etc when looking up the bit to test. 571 * FEAT_FGT2 will add more elements to these arrays. 572 */ 573 uint64_t fgt_read[2]; /* HFGRTR, HDFGRTR */ 574 uint64_t fgt_write[2]; /* HFGWTR, HDFGWTR */ 575 uint64_t fgt_exec[1]; /* HFGITR */ 576 577 /* RME registers */ 578 uint64_t gpccr_el3; 579 uint64_t gptbr_el3; 580 uint64_t mfar_el3; 581 582 /* NV2 register */ 583 uint64_t vncr_el2; 584 } cp15; 585 586 struct { 587 /* M profile has up to 4 stack pointers: 588 * a Main Stack Pointer and a Process Stack Pointer for each 589 * of the Secure and Non-Secure states. (If the CPU doesn't support 590 * the security extension then it has only two SPs.) 591 * In QEMU we always store the currently active SP in regs[13], 592 * and the non-active SP for the current security state in 593 * v7m.other_sp. The stack pointers for the inactive security state 594 * are stored in other_ss_msp and other_ss_psp. 595 * switch_v7m_security_state() is responsible for rearranging them 596 * when we change security state. 597 */ 598 uint32_t other_sp; 599 uint32_t other_ss_msp; 600 uint32_t other_ss_psp; 601 uint32_t vecbase[M_REG_NUM_BANKS]; 602 uint32_t basepri[M_REG_NUM_BANKS]; 603 uint32_t control[M_REG_NUM_BANKS]; 604 uint32_t ccr[M_REG_NUM_BANKS]; /* Configuration and Control */ 605 uint32_t cfsr[M_REG_NUM_BANKS]; /* Configurable Fault Status */ 606 uint32_t hfsr; /* HardFault Status */ 607 uint32_t dfsr; /* Debug Fault Status Register */ 608 uint32_t sfsr; /* Secure Fault Status Register */ 609 uint32_t mmfar[M_REG_NUM_BANKS]; /* MemManage Fault Address */ 610 uint32_t bfar; /* BusFault Address */ 611 uint32_t sfar; /* Secure Fault Address Register */ 612 unsigned mpu_ctrl[M_REG_NUM_BANKS]; /* MPU_CTRL */ 613 int exception; 614 uint32_t primask[M_REG_NUM_BANKS]; 615 uint32_t faultmask[M_REG_NUM_BANKS]; 616 uint32_t aircr; /* only holds r/w state if security extn implemented */ 617 uint32_t secure; /* Is CPU in Secure state? (not guest visible) */ 618 uint32_t csselr[M_REG_NUM_BANKS]; 619 uint32_t scr[M_REG_NUM_BANKS]; 620 uint32_t msplim[M_REG_NUM_BANKS]; 621 uint32_t psplim[M_REG_NUM_BANKS]; 622 uint32_t fpcar[M_REG_NUM_BANKS]; 623 uint32_t fpccr[M_REG_NUM_BANKS]; 624 uint32_t fpdscr[M_REG_NUM_BANKS]; 625 uint32_t cpacr[M_REG_NUM_BANKS]; 626 uint32_t nsacr; 627 uint32_t ltpsize; 628 uint32_t vpr; 629 } v7m; 630 631 /* Information associated with an exception about to be taken: 632 * code which raises an exception must set cs->exception_index and 633 * the relevant parts of this structure; the cpu_do_interrupt function 634 * will then set the guest-visible registers as part of the exception 635 * entry process. 636 */ 637 struct { 638 uint32_t syndrome; /* AArch64 format syndrome register */ 639 uint32_t fsr; /* AArch32 format fault status register info */ 640 uint64_t vaddress; /* virtual addr associated with exception, if any */ 641 uint32_t target_el; /* EL the exception should be targeted for */ 642 /* If we implement EL2 we will also need to store information 643 * about the intermediate physical address for stage 2 faults. 644 */ 645 } exception; 646 647 /* Information associated with an SError */ 648 struct { 649 uint8_t pending; 650 uint8_t has_esr; 651 uint64_t esr; 652 } serror; 653 654 uint8_t ext_dabt_raised; /* Tracking/verifying injection of ext DABT */ 655 656 /* State of our input IRQ/FIQ/VIRQ/VFIQ lines */ 657 uint32_t irq_line_state; 658 659 /* Thumb-2 EE state. */ 660 uint32_t teecr; 661 uint32_t teehbr; 662 663 /* VFP coprocessor state. */ 664 struct { 665 ARMVectorReg zregs[32]; 666 667 #ifdef TARGET_AARCH64 668 /* Store FFR as pregs[16] to make it easier to treat as any other. */ 669 #define FFR_PRED_NUM 16 670 ARMPredicateReg pregs[17]; 671 /* Scratch space for aa64 sve predicate temporary. */ 672 ARMPredicateReg preg_tmp; 673 #endif 674 675 /* We store these fpcsr fields separately for convenience. */ 676 uint32_t qc[4] QEMU_ALIGNED(16); 677 int vec_len; 678 int vec_stride; 679 680 /* 681 * Floating point status and control registers. Some bits are 682 * stored separately in other fields or in the float_status below. 683 */ 684 uint64_t fpsr; 685 uint64_t fpcr; 686 687 uint32_t xregs[16]; 688 689 /* Scratch space for aa32 neon expansion. */ 690 uint32_t scratch[8]; 691 692 /* There are a number of distinct float control structures. */ 693 float_status fp_status[FPST_COUNT]; 694 695 uint64_t zcr_el[4]; /* ZCR_EL[1-3] */ 696 uint64_t smcr_el[4]; /* SMCR_EL[1-3] */ 697 } vfp; 698 699 uint64_t exclusive_addr; 700 uint64_t exclusive_val; 701 /* 702 * Contains the 'val' for the second 64-bit register of LDXP, which comes 703 * from the higher address, not the high part of a complete 128-bit value. 704 * In some ways it might be more convenient to record the exclusive value 705 * as the low and high halves of a 128 bit data value, but the current 706 * semantics of these fields are baked into the migration format. 707 */ 708 uint64_t exclusive_high; 709 710 /* iwMMXt coprocessor state. */ 711 struct { 712 uint64_t regs[16]; 713 uint64_t val; 714 715 uint32_t cregs[16]; 716 } iwmmxt; 717 718 #ifdef TARGET_AARCH64 719 struct { 720 ARMPACKey apia; 721 ARMPACKey apib; 722 ARMPACKey apda; 723 ARMPACKey apdb; 724 ARMPACKey apga; 725 } keys; 726 727 uint64_t scxtnum_el[4]; 728 729 /* 730 * SME ZA storage -- 256 x 256 byte array, with bytes in host word order, 731 * as we do with vfp.zregs[]. This corresponds to the architectural ZA 732 * array, where ZA[N] is in the least-significant bytes of env->zarray[N]. 733 * When SVL is less than the architectural maximum, the accessible 734 * storage is restricted, such that if the SVL is X bytes the guest can 735 * see only the bottom X elements of zarray[], and only the least 736 * significant X bytes of each element of the array. (In other words, 737 * the observable part is always square.) 738 * 739 * The ZA storage can also be considered as a set of square tiles of 740 * elements of different sizes. The mapping from tiles to the ZA array 741 * is architecturally defined, such that for tiles of elements of esz 742 * bytes, the Nth row (or "horizontal slice") of tile T is in 743 * ZA[T + N * esz]. Note that this means that each tile is not contiguous 744 * in the ZA storage, because its rows are striped through the ZA array. 745 * 746 * Because this is so large, keep this toward the end of the reset area, 747 * to keep the offsets into the rest of the structure smaller. 748 */ 749 ARMVectorReg zarray[ARM_MAX_VQ * 16]; 750 #endif 751 752 struct CPUBreakpoint *cpu_breakpoint[16]; 753 struct CPUWatchpoint *cpu_watchpoint[16]; 754 755 /* Optional fault info across tlb lookup. */ 756 ARMMMUFaultInfo *tlb_fi; 757 758 /* Fields up to this point are cleared by a CPU reset */ 759 struct {} end_reset_fields; 760 761 /* Fields after this point are preserved across CPU reset. */ 762 763 /* Internal CPU feature flags. */ 764 uint64_t features; 765 766 /* PMSAv7 MPU */ 767 struct { 768 uint32_t *drbar; 769 uint32_t *drsr; 770 uint32_t *dracr; 771 uint32_t rnr[M_REG_NUM_BANKS]; 772 } pmsav7; 773 774 /* PMSAv8 MPU */ 775 struct { 776 /* The PMSAv8 implementation also shares some PMSAv7 config 777 * and state: 778 * pmsav7.rnr (region number register) 779 * pmsav7_dregion (number of configured regions) 780 */ 781 uint32_t *rbar[M_REG_NUM_BANKS]; 782 uint32_t *rlar[M_REG_NUM_BANKS]; 783 uint32_t *hprbar; 784 uint32_t *hprlar; 785 uint32_t mair0[M_REG_NUM_BANKS]; 786 uint32_t mair1[M_REG_NUM_BANKS]; 787 uint32_t hprselr; 788 } pmsav8; 789 790 /* v8M SAU */ 791 struct { 792 uint32_t *rbar; 793 uint32_t *rlar; 794 uint32_t rnr; 795 uint32_t ctrl; 796 } sau; 797 798 #if !defined(CONFIG_USER_ONLY) 799 NVICState *nvic; 800 const struct arm_boot_info *boot_info; 801 /* Store GICv3CPUState to access from this struct */ 802 void *gicv3state; 803 #else /* CONFIG_USER_ONLY */ 804 /* For usermode syscall translation. */ 805 bool eabi; 806 #endif /* CONFIG_USER_ONLY */ 807 808 #ifdef TARGET_TAGGED_ADDRESSES 809 /* Linux syscall tagged address support */ 810 bool tagged_addr_enable; 811 #endif 812 } CPUARMState; 813 814 static inline void set_feature(CPUARMState *env, int feature) 815 { 816 env->features |= 1ULL << feature; 817 } 818 819 static inline void unset_feature(CPUARMState *env, int feature) 820 { 821 env->features &= ~(1ULL << feature); 822 } 823 824 /** 825 * ARMELChangeHookFn: 826 * type of a function which can be registered via arm_register_el_change_hook() 827 * to get callbacks when the CPU changes its exception level or mode. 828 */ 829 typedef void ARMELChangeHookFn(ARMCPU *cpu, void *opaque); 830 typedef struct ARMELChangeHook ARMELChangeHook; 831 struct ARMELChangeHook { 832 ARMELChangeHookFn *hook; 833 void *opaque; 834 QLIST_ENTRY(ARMELChangeHook) node; 835 }; 836 837 /* These values map onto the return values for 838 * QEMU_PSCI_0_2_FN_AFFINITY_INFO */ 839 typedef enum ARMPSCIState { 840 PSCI_ON = 0, 841 PSCI_OFF = 1, 842 PSCI_ON_PENDING = 2 843 } ARMPSCIState; 844 845 typedef struct ARMISARegisters ARMISARegisters; 846 847 /* 848 * In map, each set bit is a supported vector length of (bit-number + 1) * 16 849 * bytes, i.e. each bit number + 1 is the vector length in quadwords. 850 * 851 * While processing properties during initialization, corresponding init bits 852 * are set for bits in sve_vq_map that have been set by properties. 853 * 854 * Bits set in supported represent valid vector lengths for the CPU type. 855 */ 856 typedef struct { 857 uint32_t map, init, supported; 858 } ARMVQMap; 859 860 /** 861 * ARMCPU: 862 * @env: #CPUARMState 863 * 864 * An ARM CPU core. 865 */ 866 struct ArchCPU { 867 CPUState parent_obj; 868 869 CPUARMState env; 870 871 /* Coprocessor information */ 872 GHashTable *cp_regs; 873 /* For marshalling (mostly coprocessor) register state between the 874 * kernel and QEMU (for KVM) and between two QEMUs (for migration), 875 * we use these arrays. 876 */ 877 /* List of register indexes managed via these arrays; (full KVM style 878 * 64 bit indexes, not CPRegInfo 32 bit indexes) 879 */ 880 uint64_t *cpreg_indexes; 881 /* Values of the registers (cpreg_indexes[i]'s value is cpreg_values[i]) */ 882 uint64_t *cpreg_values; 883 /* Length of the indexes, values, reset_values arrays */ 884 int32_t cpreg_array_len; 885 /* These are used only for migration: incoming data arrives in 886 * these fields and is sanity checked in post_load before copying 887 * to the working data structures above. 888 */ 889 uint64_t *cpreg_vmstate_indexes; 890 uint64_t *cpreg_vmstate_values; 891 int32_t cpreg_vmstate_array_len; 892 893 DynamicGDBFeatureInfo dyn_sysreg_feature; 894 DynamicGDBFeatureInfo dyn_svereg_feature; 895 DynamicGDBFeatureInfo dyn_m_systemreg_feature; 896 DynamicGDBFeatureInfo dyn_m_secextreg_feature; 897 898 /* Timers used by the generic (architected) timer */ 899 QEMUTimer *gt_timer[NUM_GTIMERS]; 900 /* 901 * Timer used by the PMU. Its state is restored after migration by 902 * pmu_op_finish() - it does not need other handling during migration 903 */ 904 QEMUTimer *pmu_timer; 905 /* Timer used for WFxT timeouts */ 906 QEMUTimer *wfxt_timer; 907 908 /* GPIO outputs for generic timer */ 909 qemu_irq gt_timer_outputs[NUM_GTIMERS]; 910 /* GPIO output for GICv3 maintenance interrupt signal */ 911 qemu_irq gicv3_maintenance_interrupt; 912 /* GPIO output for the PMU interrupt */ 913 qemu_irq pmu_interrupt; 914 915 /* MemoryRegion to use for secure physical accesses */ 916 MemoryRegion *secure_memory; 917 918 /* MemoryRegion to use for allocation tag accesses */ 919 MemoryRegion *tag_memory; 920 MemoryRegion *secure_tag_memory; 921 922 /* For v8M, pointer to the IDAU interface provided by board/SoC */ 923 Object *idau; 924 925 /* 'compatible' string for this CPU for Linux device trees */ 926 const char *dtb_compatible; 927 928 /* PSCI version for this CPU 929 * Bits[31:16] = Major Version 930 * Bits[15:0] = Minor Version 931 */ 932 uint32_t psci_version; 933 934 /* Current power state, access guarded by BQL */ 935 ARMPSCIState power_state; 936 937 /* CPU has virtualization extension */ 938 bool has_el2; 939 /* CPU has security extension */ 940 bool has_el3; 941 /* CPU has PMU (Performance Monitor Unit) */ 942 bool has_pmu; 943 /* CPU has VFP */ 944 bool has_vfp; 945 /* CPU has 32 VFP registers */ 946 bool has_vfp_d32; 947 /* CPU has Neon */ 948 bool has_neon; 949 /* CPU has M-profile DSP extension */ 950 bool has_dsp; 951 952 /* CPU has memory protection unit */ 953 bool has_mpu; 954 /* CPU has MTE enabled in KVM mode */ 955 bool kvm_mte; 956 /* PMSAv7 MPU number of supported regions */ 957 uint32_t pmsav7_dregion; 958 /* PMSAv8 MPU number of supported hyp regions */ 959 uint32_t pmsav8r_hdregion; 960 /* v8M SAU number of supported regions */ 961 uint32_t sau_sregion; 962 963 /* PSCI conduit used to invoke PSCI methods 964 * 0 - disabled, 1 - smc, 2 - hvc 965 */ 966 uint32_t psci_conduit; 967 968 /* For v8M, initial value of the Secure VTOR */ 969 uint32_t init_svtor; 970 /* For v8M, initial value of the Non-secure VTOR */ 971 uint32_t init_nsvtor; 972 973 /* [QEMU_]KVM_ARM_TARGET_* constant for this CPU, or 974 * QEMU_KVM_ARM_TARGET_NONE if the kernel doesn't support this CPU type. 975 */ 976 uint32_t kvm_target; 977 978 #ifdef CONFIG_KVM 979 /* KVM init features for this CPU */ 980 uint32_t kvm_init_features[7]; 981 982 /* KVM CPU state */ 983 984 /* KVM virtual time adjustment */ 985 bool kvm_adjvtime; 986 bool kvm_vtime_dirty; 987 uint64_t kvm_vtime; 988 989 /* KVM steal time */ 990 OnOffAuto kvm_steal_time; 991 #endif /* CONFIG_KVM */ 992 993 /* Uniprocessor system with MP extensions */ 994 bool mp_is_up; 995 996 /* True if we tried kvm_arm_host_cpu_features() during CPU instance_init 997 * and the probe failed (so we need to report the error in realize) 998 */ 999 bool host_cpu_probe_failed; 1000 1001 /* QOM property to indicate we should use the back-compat CNTFRQ default */ 1002 bool backcompat_cntfrq; 1003 1004 /* QOM property to indicate we should use the back-compat QARMA5 default */ 1005 bool backcompat_pauth_default_use_qarma5; 1006 1007 /* Specify the number of cores in this CPU cluster. Used for the L2CTLR 1008 * register. 1009 */ 1010 int32_t core_count; 1011 1012 /* The instance init functions for implementation-specific subclasses 1013 * set these fields to specify the implementation-dependent values of 1014 * various constant registers and reset values of non-constant 1015 * registers. 1016 * Some of these might become QOM properties eventually. 1017 * Field names match the official register names as defined in the 1018 * ARMv7AR ARM Architecture Reference Manual. A reset_ prefix 1019 * is used for reset values of non-constant registers; no reset_ 1020 * prefix means a constant register. 1021 * Some of these registers are split out into a substructure that 1022 * is shared with the translators to control the ISA. 1023 * 1024 * Note that if you add an ID register to the ARMISARegisters struct 1025 * you need to also update the 32-bit and 64-bit versions of the 1026 * kvm_arm_get_host_cpu_features() function to correctly populate the 1027 * field by reading the value from the KVM vCPU. 1028 */ 1029 struct ARMISARegisters { 1030 uint32_t id_isar0; 1031 uint32_t id_isar1; 1032 uint32_t id_isar2; 1033 uint32_t id_isar3; 1034 uint32_t id_isar4; 1035 uint32_t id_isar5; 1036 uint32_t id_isar6; 1037 uint32_t id_mmfr0; 1038 uint32_t id_mmfr1; 1039 uint32_t id_mmfr2; 1040 uint32_t id_mmfr3; 1041 uint32_t id_mmfr4; 1042 uint32_t id_mmfr5; 1043 uint32_t id_pfr0; 1044 uint32_t id_pfr1; 1045 uint32_t id_pfr2; 1046 uint32_t mvfr0; 1047 uint32_t mvfr1; 1048 uint32_t mvfr2; 1049 uint32_t id_dfr0; 1050 uint32_t id_dfr1; 1051 uint32_t dbgdidr; 1052 uint32_t dbgdevid; 1053 uint32_t dbgdevid1; 1054 uint64_t id_aa64isar0; 1055 uint64_t id_aa64isar1; 1056 uint64_t id_aa64isar2; 1057 uint64_t id_aa64pfr0; 1058 uint64_t id_aa64pfr1; 1059 uint64_t id_aa64mmfr0; 1060 uint64_t id_aa64mmfr1; 1061 uint64_t id_aa64mmfr2; 1062 uint64_t id_aa64mmfr3; 1063 uint64_t id_aa64dfr0; 1064 uint64_t id_aa64dfr1; 1065 uint64_t id_aa64zfr0; 1066 uint64_t id_aa64smfr0; 1067 uint64_t reset_pmcr_el0; 1068 } isar; 1069 uint64_t midr; 1070 uint32_t revidr; 1071 uint32_t reset_fpsid; 1072 uint64_t ctr; 1073 uint32_t reset_sctlr; 1074 uint64_t pmceid0; 1075 uint64_t pmceid1; 1076 uint32_t id_afr0; 1077 uint64_t id_aa64afr0; 1078 uint64_t id_aa64afr1; 1079 uint64_t clidr; 1080 uint64_t mp_affinity; /* MP ID without feature bits */ 1081 /* The elements of this array are the CCSIDR values for each cache, 1082 * in the order L1DCache, L1ICache, L2DCache, L2ICache, etc. 1083 */ 1084 uint64_t ccsidr[16]; 1085 uint64_t reset_cbar; 1086 uint32_t reset_auxcr; 1087 bool reset_hivecs; 1088 uint8_t reset_l0gptsz; 1089 1090 /* 1091 * Intermediate values used during property parsing. 1092 * Once finalized, the values should be read from ID_AA64*. 1093 */ 1094 bool prop_pauth; 1095 bool prop_pauth_impdef; 1096 bool prop_pauth_qarma3; 1097 bool prop_pauth_qarma5; 1098 bool prop_lpa2; 1099 1100 /* DCZ blocksize, in log_2(words), ie low 4 bits of DCZID_EL0 */ 1101 uint8_t dcz_blocksize; 1102 /* GM blocksize, in log_2(words), ie low 4 bits of GMID_EL0 */ 1103 uint8_t gm_blocksize; 1104 1105 uint64_t rvbar_prop; /* Property/input signals. */ 1106 1107 /* Configurable aspects of GIC cpu interface (which is part of the CPU) */ 1108 int gic_num_lrs; /* number of list registers */ 1109 int gic_vpribits; /* number of virtual priority bits */ 1110 int gic_vprebits; /* number of virtual preemption bits */ 1111 int gic_pribits; /* number of physical priority bits */ 1112 1113 /* Whether the cfgend input is high (i.e. this CPU should reset into 1114 * big-endian mode). This setting isn't used directly: instead it modifies 1115 * the reset_sctlr value to have SCTLR_B or SCTLR_EE set, depending on the 1116 * architecture version. 1117 */ 1118 bool cfgend; 1119 1120 QLIST_HEAD(, ARMELChangeHook) pre_el_change_hooks; 1121 QLIST_HEAD(, ARMELChangeHook) el_change_hooks; 1122 1123 int32_t node_id; /* NUMA node this CPU belongs to */ 1124 1125 /* Used to synchronize KVM and QEMU in-kernel device levels */ 1126 uint8_t device_irq_level; 1127 1128 /* Used to set the maximum vector length the cpu will support. */ 1129 uint32_t sve_max_vq; 1130 1131 #ifdef CONFIG_USER_ONLY 1132 /* Used to set the default vector length at process start. */ 1133 uint32_t sve_default_vq; 1134 uint32_t sme_default_vq; 1135 #endif 1136 1137 ARMVQMap sve_vq; 1138 ARMVQMap sme_vq; 1139 1140 /* Generic timer counter frequency, in Hz */ 1141 uint64_t gt_cntfrq_hz; 1142 }; 1143 1144 typedef struct ARMCPUInfo { 1145 const char *name; 1146 const char *deprecation_note; 1147 void (*initfn)(Object *obj); 1148 void (*class_init)(ObjectClass *oc, void *data); 1149 } ARMCPUInfo; 1150 1151 /** 1152 * ARMCPUClass: 1153 * @parent_realize: The parent class' realize handler. 1154 * @parent_phases: The parent class' reset phase handlers. 1155 * 1156 * An ARM CPU model. 1157 */ 1158 struct ARMCPUClass { 1159 CPUClass parent_class; 1160 1161 const ARMCPUInfo *info; 1162 DeviceRealize parent_realize; 1163 ResettablePhases parent_phases; 1164 }; 1165 1166 struct AArch64CPUClass { 1167 ARMCPUClass parent_class; 1168 }; 1169 1170 /* Callback functions for the generic timer's timers. */ 1171 void arm_gt_ptimer_cb(void *opaque); 1172 void arm_gt_vtimer_cb(void *opaque); 1173 void arm_gt_htimer_cb(void *opaque); 1174 void arm_gt_stimer_cb(void *opaque); 1175 void arm_gt_hvtimer_cb(void *opaque); 1176 void arm_gt_sel2timer_cb(void *opaque); 1177 void arm_gt_sel2vtimer_cb(void *opaque); 1178 1179 unsigned int gt_cntfrq_period_ns(ARMCPU *cpu); 1180 void gt_rme_post_el_change(ARMCPU *cpu, void *opaque); 1181 1182 void arm_cpu_post_init(Object *obj); 1183 1184 #define ARM_AFF0_SHIFT 0 1185 #define ARM_AFF0_MASK (0xFFULL << ARM_AFF0_SHIFT) 1186 #define ARM_AFF1_SHIFT 8 1187 #define ARM_AFF1_MASK (0xFFULL << ARM_AFF1_SHIFT) 1188 #define ARM_AFF2_SHIFT 16 1189 #define ARM_AFF2_MASK (0xFFULL << ARM_AFF2_SHIFT) 1190 #define ARM_AFF3_SHIFT 32 1191 #define ARM_AFF3_MASK (0xFFULL << ARM_AFF3_SHIFT) 1192 #define ARM_DEFAULT_CPUS_PER_CLUSTER 8 1193 1194 #define ARM32_AFFINITY_MASK (ARM_AFF0_MASK | ARM_AFF1_MASK | ARM_AFF2_MASK) 1195 #define ARM64_AFFINITY_MASK \ 1196 (ARM_AFF0_MASK | ARM_AFF1_MASK | ARM_AFF2_MASK | ARM_AFF3_MASK) 1197 #define ARM64_AFFINITY_INVALID (~ARM64_AFFINITY_MASK) 1198 1199 uint64_t arm_build_mp_affinity(int idx, uint8_t clustersz); 1200 1201 #ifndef CONFIG_USER_ONLY 1202 extern const VMStateDescription vmstate_arm_cpu; 1203 1204 void arm_cpu_do_interrupt(CPUState *cpu); 1205 void arm_v7m_cpu_do_interrupt(CPUState *cpu); 1206 1207 hwaddr arm_cpu_get_phys_page_attrs_debug(CPUState *cpu, vaddr addr, 1208 MemTxAttrs *attrs); 1209 #endif /* !CONFIG_USER_ONLY */ 1210 1211 int arm_cpu_gdb_read_register(CPUState *cpu, GByteArray *buf, int reg); 1212 int arm_cpu_gdb_write_register(CPUState *cpu, uint8_t *buf, int reg); 1213 1214 int arm_cpu_write_elf64_note(WriteCoreDumpFunction f, CPUState *cs, 1215 int cpuid, DumpState *s); 1216 int arm_cpu_write_elf32_note(WriteCoreDumpFunction f, CPUState *cs, 1217 int cpuid, DumpState *s); 1218 1219 /** 1220 * arm_emulate_firmware_reset: Emulate firmware CPU reset handling 1221 * @cpu: CPU (which must have been freshly reset) 1222 * @target_el: exception level to put the CPU into 1223 * @secure: whether to put the CPU in secure state 1224 * 1225 * When QEMU is directly running a guest kernel at a lower level than 1226 * EL3 it implicitly emulates some aspects of the guest firmware. 1227 * This includes that on reset we need to configure the parts of the 1228 * CPU corresponding to EL3 so that the real guest code can run at its 1229 * lower exception level. This function does that post-reset CPU setup, 1230 * for when we do direct boot of a guest kernel, and for when we 1231 * emulate PSCI and similar firmware interfaces starting a CPU at a 1232 * lower exception level. 1233 * 1234 * @target_el must be an EL implemented by the CPU between 1 and 3. 1235 * We do not support dropping into a Secure EL other than 3. 1236 * 1237 * It is the responsibility of the caller to call arm_rebuild_hflags(). 1238 */ 1239 void arm_emulate_firmware_reset(CPUState *cpustate, int target_el); 1240 1241 #ifdef TARGET_AARCH64 1242 int aarch64_cpu_gdb_read_register(CPUState *cpu, GByteArray *buf, int reg); 1243 int aarch64_cpu_gdb_write_register(CPUState *cpu, uint8_t *buf, int reg); 1244 void aarch64_sve_narrow_vq(CPUARMState *env, unsigned vq); 1245 void aarch64_sve_change_el(CPUARMState *env, int old_el, 1246 int new_el, bool el0_a64); 1247 void aarch64_set_svcr(CPUARMState *env, uint64_t new, uint64_t mask); 1248 1249 /* 1250 * SVE registers are encoded in KVM's memory in an endianness-invariant format. 1251 * The byte at offset i from the start of the in-memory representation contains 1252 * the bits [(7 + 8 * i) : (8 * i)] of the register value. As this means the 1253 * lowest offsets are stored in the lowest memory addresses, then that nearly 1254 * matches QEMU's representation, which is to use an array of host-endian 1255 * uint64_t's, where the lower offsets are at the lower indices. To complete 1256 * the translation we just need to byte swap the uint64_t's on big-endian hosts. 1257 */ 1258 static inline uint64_t *sve_bswap64(uint64_t *dst, uint64_t *src, int nr) 1259 { 1260 #if HOST_BIG_ENDIAN 1261 int i; 1262 1263 for (i = 0; i < nr; ++i) { 1264 dst[i] = bswap64(src[i]); 1265 } 1266 1267 return dst; 1268 #else 1269 return src; 1270 #endif 1271 } 1272 1273 #else 1274 static inline void aarch64_sve_narrow_vq(CPUARMState *env, unsigned vq) { } 1275 static inline void aarch64_sve_change_el(CPUARMState *env, int o, 1276 int n, bool a) 1277 { } 1278 #endif 1279 1280 void aarch64_sync_32_to_64(CPUARMState *env); 1281 void aarch64_sync_64_to_32(CPUARMState *env); 1282 1283 int fp_exception_el(CPUARMState *env, int cur_el); 1284 int sve_exception_el(CPUARMState *env, int cur_el); 1285 int sme_exception_el(CPUARMState *env, int cur_el); 1286 1287 /** 1288 * sve_vqm1_for_el_sm: 1289 * @env: CPUARMState 1290 * @el: exception level 1291 * @sm: streaming mode 1292 * 1293 * Compute the current vector length for @el & @sm, in units of 1294 * Quadwords Minus 1 -- the same scale used for ZCR_ELx.LEN. 1295 * If @sm, compute for SVL, otherwise NVL. 1296 */ 1297 uint32_t sve_vqm1_for_el_sm(CPUARMState *env, int el, bool sm); 1298 1299 /* Likewise, but using @sm = PSTATE.SM. */ 1300 uint32_t sve_vqm1_for_el(CPUARMState *env, int el); 1301 1302 static inline bool is_a64(CPUARMState *env) 1303 { 1304 return env->aarch64; 1305 } 1306 1307 /** 1308 * pmu_op_start/finish 1309 * @env: CPUARMState 1310 * 1311 * Convert all PMU counters between their delta form (the typical mode when 1312 * they are enabled) and the guest-visible values. These two calls must 1313 * surround any action which might affect the counters. 1314 */ 1315 void pmu_op_start(CPUARMState *env); 1316 void pmu_op_finish(CPUARMState *env); 1317 1318 /* 1319 * Called when a PMU counter is due to overflow 1320 */ 1321 void arm_pmu_timer_cb(void *opaque); 1322 1323 /** 1324 * Functions to register as EL change hooks for PMU mode filtering 1325 */ 1326 void pmu_pre_el_change(ARMCPU *cpu, void *ignored); 1327 void pmu_post_el_change(ARMCPU *cpu, void *ignored); 1328 1329 /* 1330 * pmu_init 1331 * @cpu: ARMCPU 1332 * 1333 * Initialize the CPU's PMCEID[01]_EL0 registers and associated internal state 1334 * for the current configuration 1335 */ 1336 void pmu_init(ARMCPU *cpu); 1337 1338 /* SCTLR bit meanings. Several bits have been reused in newer 1339 * versions of the architecture; in that case we define constants 1340 * for both old and new bit meanings. Code which tests against those 1341 * bits should probably check or otherwise arrange that the CPU 1342 * is the architectural version it expects. 1343 */ 1344 #define SCTLR_M (1U << 0) 1345 #define SCTLR_A (1U << 1) 1346 #define SCTLR_C (1U << 2) 1347 #define SCTLR_W (1U << 3) /* up to v6; RAO in v7 */ 1348 #define SCTLR_nTLSMD_32 (1U << 3) /* v8.2-LSMAOC, AArch32 only */ 1349 #define SCTLR_SA (1U << 3) /* AArch64 only */ 1350 #define SCTLR_P (1U << 4) /* up to v5; RAO in v6 and v7 */ 1351 #define SCTLR_LSMAOE_32 (1U << 4) /* v8.2-LSMAOC, AArch32 only */ 1352 #define SCTLR_SA0 (1U << 4) /* v8 onward, AArch64 only */ 1353 #define SCTLR_D (1U << 5) /* up to v5; RAO in v6 */ 1354 #define SCTLR_CP15BEN (1U << 5) /* v7 onward */ 1355 #define SCTLR_L (1U << 6) /* up to v5; RAO in v6 and v7; RAZ in v8 */ 1356 #define SCTLR_nAA (1U << 6) /* when FEAT_LSE2 is implemented */ 1357 #define SCTLR_B (1U << 7) /* up to v6; RAZ in v7 */ 1358 #define SCTLR_ITD (1U << 7) /* v8 onward */ 1359 #define SCTLR_S (1U << 8) /* up to v6; RAZ in v7 */ 1360 #define SCTLR_SED (1U << 8) /* v8 onward */ 1361 #define SCTLR_R (1U << 9) /* up to v6; RAZ in v7 */ 1362 #define SCTLR_UMA (1U << 9) /* v8 onward, AArch64 only */ 1363 #define SCTLR_F (1U << 10) /* up to v6 */ 1364 #define SCTLR_SW (1U << 10) /* v7 */ 1365 #define SCTLR_EnRCTX (1U << 10) /* in v8.0-PredInv */ 1366 #define SCTLR_Z (1U << 11) /* in v7, RES1 in v8 */ 1367 #define SCTLR_EOS (1U << 11) /* v8.5-ExS */ 1368 #define SCTLR_I (1U << 12) 1369 #define SCTLR_V (1U << 13) /* AArch32 only */ 1370 #define SCTLR_EnDB (1U << 13) /* v8.3, AArch64 only */ 1371 #define SCTLR_RR (1U << 14) /* up to v7 */ 1372 #define SCTLR_DZE (1U << 14) /* v8 onward, AArch64 only */ 1373 #define SCTLR_L4 (1U << 15) /* up to v6; RAZ in v7 */ 1374 #define SCTLR_UCT (1U << 15) /* v8 onward, AArch64 only */ 1375 #define SCTLR_DT (1U << 16) /* up to ??, RAO in v6 and v7 */ 1376 #define SCTLR_nTWI (1U << 16) /* v8 onward */ 1377 #define SCTLR_HA (1U << 17) /* up to v7, RES0 in v8 */ 1378 #define SCTLR_BR (1U << 17) /* PMSA only */ 1379 #define SCTLR_IT (1U << 18) /* up to ??, RAO in v6 and v7 */ 1380 #define SCTLR_nTWE (1U << 18) /* v8 onward */ 1381 #define SCTLR_WXN (1U << 19) 1382 #define SCTLR_ST (1U << 20) /* up to ??, RAZ in v6 */ 1383 #define SCTLR_UWXN (1U << 20) /* v7 onward, AArch32 only */ 1384 #define SCTLR_TSCXT (1U << 20) /* FEAT_CSV2_1p2, AArch64 only */ 1385 #define SCTLR_FI (1U << 21) /* up to v7, v8 RES0 */ 1386 #define SCTLR_IESB (1U << 21) /* v8.2-IESB, AArch64 only */ 1387 #define SCTLR_U (1U << 22) /* up to v6, RAO in v7 */ 1388 #define SCTLR_EIS (1U << 22) /* v8.5-ExS */ 1389 #define SCTLR_XP (1U << 23) /* up to v6; v7 onward RAO */ 1390 #define SCTLR_SPAN (1U << 23) /* v8.1-PAN */ 1391 #define SCTLR_VE (1U << 24) /* up to v7 */ 1392 #define SCTLR_E0E (1U << 24) /* v8 onward, AArch64 only */ 1393 #define SCTLR_EE (1U << 25) 1394 #define SCTLR_L2 (1U << 26) /* up to v6, RAZ in v7 */ 1395 #define SCTLR_UCI (1U << 26) /* v8 onward, AArch64 only */ 1396 #define SCTLR_NMFI (1U << 27) /* up to v7, RAZ in v7VE and v8 */ 1397 #define SCTLR_EnDA (1U << 27) /* v8.3, AArch64 only */ 1398 #define SCTLR_TRE (1U << 28) /* AArch32 only */ 1399 #define SCTLR_nTLSMD_64 (1U << 28) /* v8.2-LSMAOC, AArch64 only */ 1400 #define SCTLR_AFE (1U << 29) /* AArch32 only */ 1401 #define SCTLR_LSMAOE_64 (1U << 29) /* v8.2-LSMAOC, AArch64 only */ 1402 #define SCTLR_TE (1U << 30) /* AArch32 only */ 1403 #define SCTLR_EnIB (1U << 30) /* v8.3, AArch64 only */ 1404 #define SCTLR_EnIA (1U << 31) /* v8.3, AArch64 only */ 1405 #define SCTLR_DSSBS_32 (1U << 31) /* v8.5, AArch32 only */ 1406 #define SCTLR_CMOW (1ULL << 32) /* FEAT_CMOW */ 1407 #define SCTLR_MSCEN (1ULL << 33) /* FEAT_MOPS */ 1408 #define SCTLR_BT0 (1ULL << 35) /* v8.5-BTI */ 1409 #define SCTLR_BT1 (1ULL << 36) /* v8.5-BTI */ 1410 #define SCTLR_ITFSB (1ULL << 37) /* v8.5-MemTag */ 1411 #define SCTLR_TCF0 (3ULL << 38) /* v8.5-MemTag */ 1412 #define SCTLR_TCF (3ULL << 40) /* v8.5-MemTag */ 1413 #define SCTLR_ATA0 (1ULL << 42) /* v8.5-MemTag */ 1414 #define SCTLR_ATA (1ULL << 43) /* v8.5-MemTag */ 1415 #define SCTLR_DSSBS_64 (1ULL << 44) /* v8.5, AArch64 only */ 1416 #define SCTLR_TWEDEn (1ULL << 45) /* FEAT_TWED */ 1417 #define SCTLR_TWEDEL MAKE_64_MASK(46, 4) /* FEAT_TWED */ 1418 #define SCTLR_TMT0 (1ULL << 50) /* FEAT_TME */ 1419 #define SCTLR_TMT (1ULL << 51) /* FEAT_TME */ 1420 #define SCTLR_TME0 (1ULL << 52) /* FEAT_TME */ 1421 #define SCTLR_TME (1ULL << 53) /* FEAT_TME */ 1422 #define SCTLR_EnASR (1ULL << 54) /* FEAT_LS64_V */ 1423 #define SCTLR_EnAS0 (1ULL << 55) /* FEAT_LS64_ACCDATA */ 1424 #define SCTLR_EnALS (1ULL << 56) /* FEAT_LS64 */ 1425 #define SCTLR_EPAN (1ULL << 57) /* FEAT_PAN3 */ 1426 #define SCTLR_EnTP2 (1ULL << 60) /* FEAT_SME */ 1427 #define SCTLR_NMI (1ULL << 61) /* FEAT_NMI */ 1428 #define SCTLR_SPINTMASK (1ULL << 62) /* FEAT_NMI */ 1429 #define SCTLR_TIDCP (1ULL << 63) /* FEAT_TIDCP1 */ 1430 1431 #define CPSR_M (0x1fU) 1432 #define CPSR_T (1U << 5) 1433 #define CPSR_F (1U << 6) 1434 #define CPSR_I (1U << 7) 1435 #define CPSR_A (1U << 8) 1436 #define CPSR_E (1U << 9) 1437 #define CPSR_IT_2_7 (0xfc00U) 1438 #define CPSR_GE (0xfU << 16) 1439 #define CPSR_IL (1U << 20) 1440 #define CPSR_DIT (1U << 21) 1441 #define CPSR_PAN (1U << 22) 1442 #define CPSR_SSBS (1U << 23) 1443 #define CPSR_J (1U << 24) 1444 #define CPSR_IT_0_1 (3U << 25) 1445 #define CPSR_Q (1U << 27) 1446 #define CPSR_V (1U << 28) 1447 #define CPSR_C (1U << 29) 1448 #define CPSR_Z (1U << 30) 1449 #define CPSR_N (1U << 31) 1450 #define CPSR_NZCV (CPSR_N | CPSR_Z | CPSR_C | CPSR_V) 1451 #define CPSR_AIF (CPSR_A | CPSR_I | CPSR_F) 1452 #define ISR_FS (1U << 9) 1453 #define ISR_IS (1U << 10) 1454 1455 #define CPSR_IT (CPSR_IT_0_1 | CPSR_IT_2_7) 1456 #define CACHED_CPSR_BITS (CPSR_T | CPSR_AIF | CPSR_GE | CPSR_IT | CPSR_Q \ 1457 | CPSR_NZCV) 1458 /* Bits writable in user mode. */ 1459 #define CPSR_USER (CPSR_NZCV | CPSR_Q | CPSR_GE | CPSR_E) 1460 /* Execution state bits. MRS read as zero, MSR writes ignored. */ 1461 #define CPSR_EXEC (CPSR_T | CPSR_IT | CPSR_J | CPSR_IL) 1462 1463 /* Bit definitions for M profile XPSR. Most are the same as CPSR. */ 1464 #define XPSR_EXCP 0x1ffU 1465 #define XPSR_SPREALIGN (1U << 9) /* Only set in exception stack frames */ 1466 #define XPSR_IT_2_7 CPSR_IT_2_7 1467 #define XPSR_GE CPSR_GE 1468 #define XPSR_SFPA (1U << 20) /* Only set in exception stack frames */ 1469 #define XPSR_T (1U << 24) /* Not the same as CPSR_T ! */ 1470 #define XPSR_IT_0_1 CPSR_IT_0_1 1471 #define XPSR_Q CPSR_Q 1472 #define XPSR_V CPSR_V 1473 #define XPSR_C CPSR_C 1474 #define XPSR_Z CPSR_Z 1475 #define XPSR_N CPSR_N 1476 #define XPSR_NZCV CPSR_NZCV 1477 #define XPSR_IT CPSR_IT 1478 1479 /* Bit definitions for ARMv8 SPSR (PSTATE) format. 1480 * Only these are valid when in AArch64 mode; in 1481 * AArch32 mode SPSRs are basically CPSR-format. 1482 */ 1483 #define PSTATE_SP (1U) 1484 #define PSTATE_M (0xFU) 1485 #define PSTATE_nRW (1U << 4) 1486 #define PSTATE_F (1U << 6) 1487 #define PSTATE_I (1U << 7) 1488 #define PSTATE_A (1U << 8) 1489 #define PSTATE_D (1U << 9) 1490 #define PSTATE_BTYPE (3U << 10) 1491 #define PSTATE_SSBS (1U << 12) 1492 #define PSTATE_ALLINT (1U << 13) 1493 #define PSTATE_IL (1U << 20) 1494 #define PSTATE_SS (1U << 21) 1495 #define PSTATE_PAN (1U << 22) 1496 #define PSTATE_UAO (1U << 23) 1497 #define PSTATE_DIT (1U << 24) 1498 #define PSTATE_TCO (1U << 25) 1499 #define PSTATE_V (1U << 28) 1500 #define PSTATE_C (1U << 29) 1501 #define PSTATE_Z (1U << 30) 1502 #define PSTATE_N (1U << 31) 1503 #define PSTATE_NZCV (PSTATE_N | PSTATE_Z | PSTATE_C | PSTATE_V) 1504 #define PSTATE_DAIF (PSTATE_D | PSTATE_A | PSTATE_I | PSTATE_F) 1505 #define CACHED_PSTATE_BITS (PSTATE_NZCV | PSTATE_DAIF | PSTATE_BTYPE) 1506 /* Mode values for AArch64 */ 1507 #define PSTATE_MODE_EL3h 13 1508 #define PSTATE_MODE_EL3t 12 1509 #define PSTATE_MODE_EL2h 9 1510 #define PSTATE_MODE_EL2t 8 1511 #define PSTATE_MODE_EL1h 5 1512 #define PSTATE_MODE_EL1t 4 1513 #define PSTATE_MODE_EL0t 0 1514 1515 /* PSTATE bits that are accessed via SVCR and not stored in SPSR_ELx. */ 1516 FIELD(SVCR, SM, 0, 1) 1517 FIELD(SVCR, ZA, 1, 1) 1518 1519 /* Fields for SMCR_ELx. */ 1520 FIELD(SMCR, LEN, 0, 4) 1521 FIELD(SMCR, FA64, 31, 1) 1522 1523 /* Write a new value to v7m.exception, thus transitioning into or out 1524 * of Handler mode; this may result in a change of active stack pointer. 1525 */ 1526 void write_v7m_exception(CPUARMState *env, uint32_t new_exc); 1527 1528 /* Map EL and handler into a PSTATE_MODE. */ 1529 static inline unsigned int aarch64_pstate_mode(unsigned int el, bool handler) 1530 { 1531 return (el << 2) | handler; 1532 } 1533 1534 /* Return the current PSTATE value. For the moment we don't support 32<->64 bit 1535 * interprocessing, so we don't attempt to sync with the cpsr state used by 1536 * the 32 bit decoder. 1537 */ 1538 static inline uint32_t pstate_read(CPUARMState *env) 1539 { 1540 int ZF; 1541 1542 ZF = (env->ZF == 0); 1543 return (env->NF & 0x80000000) | (ZF << 30) 1544 | (env->CF << 29) | ((env->VF & 0x80000000) >> 3) 1545 | env->pstate | env->daif | (env->btype << 10); 1546 } 1547 1548 static inline void pstate_write(CPUARMState *env, uint32_t val) 1549 { 1550 env->ZF = (~val) & PSTATE_Z; 1551 env->NF = val; 1552 env->CF = (val >> 29) & 1; 1553 env->VF = (val << 3) & 0x80000000; 1554 env->daif = val & PSTATE_DAIF; 1555 env->btype = (val >> 10) & 3; 1556 env->pstate = val & ~CACHED_PSTATE_BITS; 1557 } 1558 1559 /* Return the current CPSR value. */ 1560 uint32_t cpsr_read(CPUARMState *env); 1561 1562 typedef enum CPSRWriteType { 1563 CPSRWriteByInstr = 0, /* from guest MSR or CPS */ 1564 CPSRWriteExceptionReturn = 1, /* from guest exception return insn */ 1565 CPSRWriteRaw = 2, 1566 /* trust values, no reg bank switch, no hflags rebuild */ 1567 CPSRWriteByGDBStub = 3, /* from the GDB stub */ 1568 } CPSRWriteType; 1569 1570 /* 1571 * Set the CPSR. Note that some bits of mask must be all-set or all-clear. 1572 * This will do an arm_rebuild_hflags() if any of the bits in @mask 1573 * correspond to TB flags bits cached in the hflags, unless @write_type 1574 * is CPSRWriteRaw. 1575 */ 1576 void cpsr_write(CPUARMState *env, uint32_t val, uint32_t mask, 1577 CPSRWriteType write_type); 1578 1579 /* Return the current xPSR value. */ 1580 static inline uint32_t xpsr_read(CPUARMState *env) 1581 { 1582 int ZF; 1583 ZF = (env->ZF == 0); 1584 return (env->NF & 0x80000000) | (ZF << 30) 1585 | (env->CF << 29) | ((env->VF & 0x80000000) >> 3) | (env->QF << 27) 1586 | (env->thumb << 24) | ((env->condexec_bits & 3) << 25) 1587 | ((env->condexec_bits & 0xfc) << 8) 1588 | (env->GE << 16) 1589 | env->v7m.exception; 1590 } 1591 1592 /* Set the xPSR. Note that some bits of mask must be all-set or all-clear. */ 1593 static inline void xpsr_write(CPUARMState *env, uint32_t val, uint32_t mask) 1594 { 1595 if (mask & XPSR_NZCV) { 1596 env->ZF = (~val) & XPSR_Z; 1597 env->NF = val; 1598 env->CF = (val >> 29) & 1; 1599 env->VF = (val << 3) & 0x80000000; 1600 } 1601 if (mask & XPSR_Q) { 1602 env->QF = ((val & XPSR_Q) != 0); 1603 } 1604 if (mask & XPSR_GE) { 1605 env->GE = (val & XPSR_GE) >> 16; 1606 } 1607 #ifndef CONFIG_USER_ONLY 1608 if (mask & XPSR_T) { 1609 env->thumb = ((val & XPSR_T) != 0); 1610 } 1611 if (mask & XPSR_IT_0_1) { 1612 env->condexec_bits &= ~3; 1613 env->condexec_bits |= (val >> 25) & 3; 1614 } 1615 if (mask & XPSR_IT_2_7) { 1616 env->condexec_bits &= 3; 1617 env->condexec_bits |= (val >> 8) & 0xfc; 1618 } 1619 if (mask & XPSR_EXCP) { 1620 /* Note that this only happens on exception exit */ 1621 write_v7m_exception(env, val & XPSR_EXCP); 1622 } 1623 #endif 1624 } 1625 1626 #define HCR_VM (1ULL << 0) 1627 #define HCR_SWIO (1ULL << 1) 1628 #define HCR_PTW (1ULL << 2) 1629 #define HCR_FMO (1ULL << 3) 1630 #define HCR_IMO (1ULL << 4) 1631 #define HCR_AMO (1ULL << 5) 1632 #define HCR_VF (1ULL << 6) 1633 #define HCR_VI (1ULL << 7) 1634 #define HCR_VSE (1ULL << 8) 1635 #define HCR_FB (1ULL << 9) 1636 #define HCR_BSU_MASK (3ULL << 10) 1637 #define HCR_DC (1ULL << 12) 1638 #define HCR_TWI (1ULL << 13) 1639 #define HCR_TWE (1ULL << 14) 1640 #define HCR_TID0 (1ULL << 15) 1641 #define HCR_TID1 (1ULL << 16) 1642 #define HCR_TID2 (1ULL << 17) 1643 #define HCR_TID3 (1ULL << 18) 1644 #define HCR_TSC (1ULL << 19) 1645 #define HCR_TIDCP (1ULL << 20) 1646 #define HCR_TACR (1ULL << 21) 1647 #define HCR_TSW (1ULL << 22) 1648 #define HCR_TPCP (1ULL << 23) 1649 #define HCR_TPU (1ULL << 24) 1650 #define HCR_TTLB (1ULL << 25) 1651 #define HCR_TVM (1ULL << 26) 1652 #define HCR_TGE (1ULL << 27) 1653 #define HCR_TDZ (1ULL << 28) 1654 #define HCR_HCD (1ULL << 29) 1655 #define HCR_TRVM (1ULL << 30) 1656 #define HCR_RW (1ULL << 31) 1657 #define HCR_CD (1ULL << 32) 1658 #define HCR_ID (1ULL << 33) 1659 #define HCR_E2H (1ULL << 34) 1660 #define HCR_TLOR (1ULL << 35) 1661 #define HCR_TERR (1ULL << 36) 1662 #define HCR_TEA (1ULL << 37) 1663 #define HCR_MIOCNCE (1ULL << 38) 1664 #define HCR_TME (1ULL << 39) 1665 #define HCR_APK (1ULL << 40) 1666 #define HCR_API (1ULL << 41) 1667 #define HCR_NV (1ULL << 42) 1668 #define HCR_NV1 (1ULL << 43) 1669 #define HCR_AT (1ULL << 44) 1670 #define HCR_NV2 (1ULL << 45) 1671 #define HCR_FWB (1ULL << 46) 1672 #define HCR_FIEN (1ULL << 47) 1673 #define HCR_GPF (1ULL << 48) 1674 #define HCR_TID4 (1ULL << 49) 1675 #define HCR_TICAB (1ULL << 50) 1676 #define HCR_AMVOFFEN (1ULL << 51) 1677 #define HCR_TOCU (1ULL << 52) 1678 #define HCR_ENSCXT (1ULL << 53) 1679 #define HCR_TTLBIS (1ULL << 54) 1680 #define HCR_TTLBOS (1ULL << 55) 1681 #define HCR_ATA (1ULL << 56) 1682 #define HCR_DCT (1ULL << 57) 1683 #define HCR_TID5 (1ULL << 58) 1684 #define HCR_TWEDEN (1ULL << 59) 1685 #define HCR_TWEDEL MAKE_64BIT_MASK(60, 4) 1686 1687 #define SCR_NS (1ULL << 0) 1688 #define SCR_IRQ (1ULL << 1) 1689 #define SCR_FIQ (1ULL << 2) 1690 #define SCR_EA (1ULL << 3) 1691 #define SCR_FW (1ULL << 4) 1692 #define SCR_AW (1ULL << 5) 1693 #define SCR_NET (1ULL << 6) 1694 #define SCR_SMD (1ULL << 7) 1695 #define SCR_HCE (1ULL << 8) 1696 #define SCR_SIF (1ULL << 9) 1697 #define SCR_RW (1ULL << 10) 1698 #define SCR_ST (1ULL << 11) 1699 #define SCR_TWI (1ULL << 12) 1700 #define SCR_TWE (1ULL << 13) 1701 #define SCR_TLOR (1ULL << 14) 1702 #define SCR_TERR (1ULL << 15) 1703 #define SCR_APK (1ULL << 16) 1704 #define SCR_API (1ULL << 17) 1705 #define SCR_EEL2 (1ULL << 18) 1706 #define SCR_EASE (1ULL << 19) 1707 #define SCR_NMEA (1ULL << 20) 1708 #define SCR_FIEN (1ULL << 21) 1709 #define SCR_ENSCXT (1ULL << 25) 1710 #define SCR_ATA (1ULL << 26) 1711 #define SCR_FGTEN (1ULL << 27) 1712 #define SCR_ECVEN (1ULL << 28) 1713 #define SCR_TWEDEN (1ULL << 29) 1714 #define SCR_TWEDEL MAKE_64BIT_MASK(30, 4) 1715 #define SCR_TME (1ULL << 34) 1716 #define SCR_AMVOFFEN (1ULL << 35) 1717 #define SCR_ENAS0 (1ULL << 36) 1718 #define SCR_ADEN (1ULL << 37) 1719 #define SCR_HXEN (1ULL << 38) 1720 #define SCR_TRNDR (1ULL << 40) 1721 #define SCR_ENTP2 (1ULL << 41) 1722 #define SCR_GPF (1ULL << 48) 1723 #define SCR_NSE (1ULL << 62) 1724 1725 /* Return the current FPSCR value. */ 1726 uint32_t vfp_get_fpscr(CPUARMState *env); 1727 void vfp_set_fpscr(CPUARMState *env, uint32_t val); 1728 1729 /* 1730 * FPCR, Floating Point Control Register 1731 * FPSR, Floating Point Status Register 1732 * 1733 * For A64 floating point control and status bits are stored in 1734 * two logically distinct registers, FPCR and FPSR. We store these 1735 * in QEMU in vfp.fpcr and vfp.fpsr. 1736 * For A32 there was only one register, FPSCR. The bits are arranged 1737 * such that FPSCR bits map to FPCR or FPSR bits in the same bit positions, 1738 * so we can use appropriate masking to handle FPSCR reads and writes. 1739 * Note that the FPCR has some bits which are not visible in the 1740 * AArch32 view (for FEAT_AFP). Writing the FPSCR leaves these unchanged. 1741 */ 1742 1743 /* FPCR bits */ 1744 #define FPCR_FIZ (1 << 0) /* Flush Inputs to Zero (FEAT_AFP) */ 1745 #define FPCR_AH (1 << 1) /* Alternate Handling (FEAT_AFP) */ 1746 #define FPCR_NEP (1 << 2) /* SIMD scalar ops preserve elts (FEAT_AFP) */ 1747 #define FPCR_IOE (1 << 8) /* Invalid Operation exception trap enable */ 1748 #define FPCR_DZE (1 << 9) /* Divide by Zero exception trap enable */ 1749 #define FPCR_OFE (1 << 10) /* Overflow exception trap enable */ 1750 #define FPCR_UFE (1 << 11) /* Underflow exception trap enable */ 1751 #define FPCR_IXE (1 << 12) /* Inexact exception trap enable */ 1752 #define FPCR_EBF (1 << 13) /* Extended BFloat16 behaviors */ 1753 #define FPCR_IDE (1 << 15) /* Input Denormal exception trap enable */ 1754 #define FPCR_LEN_MASK (7 << 16) /* LEN, A-profile only */ 1755 #define FPCR_FZ16 (1 << 19) /* ARMv8.2+, FP16 flush-to-zero */ 1756 #define FPCR_STRIDE_MASK (3 << 20) /* Stride */ 1757 #define FPCR_RMODE_MASK (3 << 22) /* Rounding mode */ 1758 #define FPCR_FZ (1 << 24) /* Flush-to-zero enable bit */ 1759 #define FPCR_DN (1 << 25) /* Default NaN enable bit */ 1760 #define FPCR_AHP (1 << 26) /* Alternative half-precision */ 1761 1762 #define FPCR_LTPSIZE_SHIFT 16 /* LTPSIZE, M-profile only */ 1763 #define FPCR_LTPSIZE_MASK (7 << FPCR_LTPSIZE_SHIFT) 1764 #define FPCR_LTPSIZE_LENGTH 3 1765 1766 /* Cumulative exception trap enable bits */ 1767 #define FPCR_EEXC_MASK (FPCR_IOE | FPCR_DZE | FPCR_OFE | FPCR_UFE | FPCR_IXE | FPCR_IDE) 1768 1769 /* FPSR bits */ 1770 #define FPSR_IOC (1 << 0) /* Invalid Operation cumulative exception */ 1771 #define FPSR_DZC (1 << 1) /* Divide by Zero cumulative exception */ 1772 #define FPSR_OFC (1 << 2) /* Overflow cumulative exception */ 1773 #define FPSR_UFC (1 << 3) /* Underflow cumulative exception */ 1774 #define FPSR_IXC (1 << 4) /* Inexact cumulative exception */ 1775 #define FPSR_IDC (1 << 7) /* Input Denormal cumulative exception */ 1776 #define FPSR_QC (1 << 27) /* Cumulative saturation bit */ 1777 #define FPSR_V (1 << 28) /* FP overflow flag */ 1778 #define FPSR_C (1 << 29) /* FP carry flag */ 1779 #define FPSR_Z (1 << 30) /* FP zero flag */ 1780 #define FPSR_N (1 << 31) /* FP negative flag */ 1781 1782 /* Cumulative exception status bits */ 1783 #define FPSR_CEXC_MASK (FPSR_IOC | FPSR_DZC | FPSR_OFC | FPSR_UFC | FPSR_IXC | FPSR_IDC) 1784 1785 #define FPSR_NZCV_MASK (FPSR_N | FPSR_Z | FPSR_C | FPSR_V) 1786 #define FPSR_NZCVQC_MASK (FPSR_NZCV_MASK | FPSR_QC) 1787 1788 /* A32 FPSCR bits which architecturally map to FPSR bits */ 1789 #define FPSCR_FPSR_MASK (FPSR_NZCVQC_MASK | FPSR_CEXC_MASK) 1790 /* A32 FPSCR bits which architecturally map to FPCR bits */ 1791 #define FPSCR_FPCR_MASK (FPCR_EEXC_MASK | FPCR_LEN_MASK | FPCR_FZ16 | \ 1792 FPCR_STRIDE_MASK | FPCR_RMODE_MASK | \ 1793 FPCR_FZ | FPCR_DN | FPCR_AHP) 1794 /* These masks don't overlap: each bit lives in only one place */ 1795 QEMU_BUILD_BUG_ON(FPSCR_FPSR_MASK & FPSCR_FPCR_MASK); 1796 1797 /** 1798 * vfp_get_fpsr: read the AArch64 FPSR 1799 * @env: CPU context 1800 * 1801 * Return the current AArch64 FPSR value 1802 */ 1803 uint32_t vfp_get_fpsr(CPUARMState *env); 1804 1805 /** 1806 * vfp_get_fpcr: read the AArch64 FPCR 1807 * @env: CPU context 1808 * 1809 * Return the current AArch64 FPCR value 1810 */ 1811 uint32_t vfp_get_fpcr(CPUARMState *env); 1812 1813 /** 1814 * vfp_set_fpsr: write the AArch64 FPSR 1815 * @env: CPU context 1816 * @value: new value 1817 */ 1818 void vfp_set_fpsr(CPUARMState *env, uint32_t value); 1819 1820 /** 1821 * vfp_set_fpcr: write the AArch64 FPCR 1822 * @env: CPU context 1823 * @value: new value 1824 */ 1825 void vfp_set_fpcr(CPUARMState *env, uint32_t value); 1826 1827 enum arm_cpu_mode { 1828 ARM_CPU_MODE_USR = 0x10, 1829 ARM_CPU_MODE_FIQ = 0x11, 1830 ARM_CPU_MODE_IRQ = 0x12, 1831 ARM_CPU_MODE_SVC = 0x13, 1832 ARM_CPU_MODE_MON = 0x16, 1833 ARM_CPU_MODE_ABT = 0x17, 1834 ARM_CPU_MODE_HYP = 0x1a, 1835 ARM_CPU_MODE_UND = 0x1b, 1836 ARM_CPU_MODE_SYS = 0x1f 1837 }; 1838 1839 /* VFP system registers. */ 1840 #define ARM_VFP_FPSID 0 1841 #define ARM_VFP_FPSCR 1 1842 #define ARM_VFP_MVFR2 5 1843 #define ARM_VFP_MVFR1 6 1844 #define ARM_VFP_MVFR0 7 1845 #define ARM_VFP_FPEXC 8 1846 #define ARM_VFP_FPINST 9 1847 #define ARM_VFP_FPINST2 10 1848 /* These ones are M-profile only */ 1849 #define ARM_VFP_FPSCR_NZCVQC 2 1850 #define ARM_VFP_VPR 12 1851 #define ARM_VFP_P0 13 1852 #define ARM_VFP_FPCXT_NS 14 1853 #define ARM_VFP_FPCXT_S 15 1854 1855 /* QEMU-internal value meaning "FPSCR, but we care only about NZCV" */ 1856 #define QEMU_VFP_FPSCR_NZCV 0xffff 1857 1858 /* iwMMXt coprocessor control registers. */ 1859 #define ARM_IWMMXT_wCID 0 1860 #define ARM_IWMMXT_wCon 1 1861 #define ARM_IWMMXT_wCSSF 2 1862 #define ARM_IWMMXT_wCASF 3 1863 #define ARM_IWMMXT_wCGR0 8 1864 #define ARM_IWMMXT_wCGR1 9 1865 #define ARM_IWMMXT_wCGR2 10 1866 #define ARM_IWMMXT_wCGR3 11 1867 1868 /* V7M CCR bits */ 1869 FIELD(V7M_CCR, NONBASETHRDENA, 0, 1) 1870 FIELD(V7M_CCR, USERSETMPEND, 1, 1) 1871 FIELD(V7M_CCR, UNALIGN_TRP, 3, 1) 1872 FIELD(V7M_CCR, DIV_0_TRP, 4, 1) 1873 FIELD(V7M_CCR, BFHFNMIGN, 8, 1) 1874 FIELD(V7M_CCR, STKALIGN, 9, 1) 1875 FIELD(V7M_CCR, STKOFHFNMIGN, 10, 1) 1876 FIELD(V7M_CCR, DC, 16, 1) 1877 FIELD(V7M_CCR, IC, 17, 1) 1878 FIELD(V7M_CCR, BP, 18, 1) 1879 FIELD(V7M_CCR, LOB, 19, 1) 1880 FIELD(V7M_CCR, TRD, 20, 1) 1881 1882 /* V7M SCR bits */ 1883 FIELD(V7M_SCR, SLEEPONEXIT, 1, 1) 1884 FIELD(V7M_SCR, SLEEPDEEP, 2, 1) 1885 FIELD(V7M_SCR, SLEEPDEEPS, 3, 1) 1886 FIELD(V7M_SCR, SEVONPEND, 4, 1) 1887 1888 /* V7M AIRCR bits */ 1889 FIELD(V7M_AIRCR, VECTRESET, 0, 1) 1890 FIELD(V7M_AIRCR, VECTCLRACTIVE, 1, 1) 1891 FIELD(V7M_AIRCR, SYSRESETREQ, 2, 1) 1892 FIELD(V7M_AIRCR, SYSRESETREQS, 3, 1) 1893 FIELD(V7M_AIRCR, PRIGROUP, 8, 3) 1894 FIELD(V7M_AIRCR, BFHFNMINS, 13, 1) 1895 FIELD(V7M_AIRCR, PRIS, 14, 1) 1896 FIELD(V7M_AIRCR, ENDIANNESS, 15, 1) 1897 FIELD(V7M_AIRCR, VECTKEY, 16, 16) 1898 1899 /* V7M CFSR bits for MMFSR */ 1900 FIELD(V7M_CFSR, IACCVIOL, 0, 1) 1901 FIELD(V7M_CFSR, DACCVIOL, 1, 1) 1902 FIELD(V7M_CFSR, MUNSTKERR, 3, 1) 1903 FIELD(V7M_CFSR, MSTKERR, 4, 1) 1904 FIELD(V7M_CFSR, MLSPERR, 5, 1) 1905 FIELD(V7M_CFSR, MMARVALID, 7, 1) 1906 1907 /* V7M CFSR bits for BFSR */ 1908 FIELD(V7M_CFSR, IBUSERR, 8 + 0, 1) 1909 FIELD(V7M_CFSR, PRECISERR, 8 + 1, 1) 1910 FIELD(V7M_CFSR, IMPRECISERR, 8 + 2, 1) 1911 FIELD(V7M_CFSR, UNSTKERR, 8 + 3, 1) 1912 FIELD(V7M_CFSR, STKERR, 8 + 4, 1) 1913 FIELD(V7M_CFSR, LSPERR, 8 + 5, 1) 1914 FIELD(V7M_CFSR, BFARVALID, 8 + 7, 1) 1915 1916 /* V7M CFSR bits for UFSR */ 1917 FIELD(V7M_CFSR, UNDEFINSTR, 16 + 0, 1) 1918 FIELD(V7M_CFSR, INVSTATE, 16 + 1, 1) 1919 FIELD(V7M_CFSR, INVPC, 16 + 2, 1) 1920 FIELD(V7M_CFSR, NOCP, 16 + 3, 1) 1921 FIELD(V7M_CFSR, STKOF, 16 + 4, 1) 1922 FIELD(V7M_CFSR, UNALIGNED, 16 + 8, 1) 1923 FIELD(V7M_CFSR, DIVBYZERO, 16 + 9, 1) 1924 1925 /* V7M CFSR bit masks covering all of the subregister bits */ 1926 FIELD(V7M_CFSR, MMFSR, 0, 8) 1927 FIELD(V7M_CFSR, BFSR, 8, 8) 1928 FIELD(V7M_CFSR, UFSR, 16, 16) 1929 1930 /* V7M HFSR bits */ 1931 FIELD(V7M_HFSR, VECTTBL, 1, 1) 1932 FIELD(V7M_HFSR, FORCED, 30, 1) 1933 FIELD(V7M_HFSR, DEBUGEVT, 31, 1) 1934 1935 /* V7M DFSR bits */ 1936 FIELD(V7M_DFSR, HALTED, 0, 1) 1937 FIELD(V7M_DFSR, BKPT, 1, 1) 1938 FIELD(V7M_DFSR, DWTTRAP, 2, 1) 1939 FIELD(V7M_DFSR, VCATCH, 3, 1) 1940 FIELD(V7M_DFSR, EXTERNAL, 4, 1) 1941 1942 /* V7M SFSR bits */ 1943 FIELD(V7M_SFSR, INVEP, 0, 1) 1944 FIELD(V7M_SFSR, INVIS, 1, 1) 1945 FIELD(V7M_SFSR, INVER, 2, 1) 1946 FIELD(V7M_SFSR, AUVIOL, 3, 1) 1947 FIELD(V7M_SFSR, INVTRAN, 4, 1) 1948 FIELD(V7M_SFSR, LSPERR, 5, 1) 1949 FIELD(V7M_SFSR, SFARVALID, 6, 1) 1950 FIELD(V7M_SFSR, LSERR, 7, 1) 1951 1952 /* v7M MPU_CTRL bits */ 1953 FIELD(V7M_MPU_CTRL, ENABLE, 0, 1) 1954 FIELD(V7M_MPU_CTRL, HFNMIENA, 1, 1) 1955 FIELD(V7M_MPU_CTRL, PRIVDEFENA, 2, 1) 1956 1957 /* v7M CLIDR bits */ 1958 FIELD(V7M_CLIDR, CTYPE_ALL, 0, 21) 1959 FIELD(V7M_CLIDR, LOUIS, 21, 3) 1960 FIELD(V7M_CLIDR, LOC, 24, 3) 1961 FIELD(V7M_CLIDR, LOUU, 27, 3) 1962 FIELD(V7M_CLIDR, ICB, 30, 2) 1963 1964 FIELD(V7M_CSSELR, IND, 0, 1) 1965 FIELD(V7M_CSSELR, LEVEL, 1, 3) 1966 /* We use the combination of InD and Level to index into cpu->ccsidr[]; 1967 * define a mask for this and check that it doesn't permit running off 1968 * the end of the array. 1969 */ 1970 FIELD(V7M_CSSELR, INDEX, 0, 4) 1971 1972 /* v7M FPCCR bits */ 1973 FIELD(V7M_FPCCR, LSPACT, 0, 1) 1974 FIELD(V7M_FPCCR, USER, 1, 1) 1975 FIELD(V7M_FPCCR, S, 2, 1) 1976 FIELD(V7M_FPCCR, THREAD, 3, 1) 1977 FIELD(V7M_FPCCR, HFRDY, 4, 1) 1978 FIELD(V7M_FPCCR, MMRDY, 5, 1) 1979 FIELD(V7M_FPCCR, BFRDY, 6, 1) 1980 FIELD(V7M_FPCCR, SFRDY, 7, 1) 1981 FIELD(V7M_FPCCR, MONRDY, 8, 1) 1982 FIELD(V7M_FPCCR, SPLIMVIOL, 9, 1) 1983 FIELD(V7M_FPCCR, UFRDY, 10, 1) 1984 FIELD(V7M_FPCCR, RES0, 11, 15) 1985 FIELD(V7M_FPCCR, TS, 26, 1) 1986 FIELD(V7M_FPCCR, CLRONRETS, 27, 1) 1987 FIELD(V7M_FPCCR, CLRONRET, 28, 1) 1988 FIELD(V7M_FPCCR, LSPENS, 29, 1) 1989 FIELD(V7M_FPCCR, LSPEN, 30, 1) 1990 FIELD(V7M_FPCCR, ASPEN, 31, 1) 1991 /* These bits are banked. Others are non-banked and live in the M_REG_S bank */ 1992 #define R_V7M_FPCCR_BANKED_MASK \ 1993 (R_V7M_FPCCR_LSPACT_MASK | \ 1994 R_V7M_FPCCR_USER_MASK | \ 1995 R_V7M_FPCCR_THREAD_MASK | \ 1996 R_V7M_FPCCR_MMRDY_MASK | \ 1997 R_V7M_FPCCR_SPLIMVIOL_MASK | \ 1998 R_V7M_FPCCR_UFRDY_MASK | \ 1999 R_V7M_FPCCR_ASPEN_MASK) 2000 2001 /* v7M VPR bits */ 2002 FIELD(V7M_VPR, P0, 0, 16) 2003 FIELD(V7M_VPR, MASK01, 16, 4) 2004 FIELD(V7M_VPR, MASK23, 20, 4) 2005 2006 /* 2007 * System register ID fields. 2008 */ 2009 FIELD(CLIDR_EL1, CTYPE1, 0, 3) 2010 FIELD(CLIDR_EL1, CTYPE2, 3, 3) 2011 FIELD(CLIDR_EL1, CTYPE3, 6, 3) 2012 FIELD(CLIDR_EL1, CTYPE4, 9, 3) 2013 FIELD(CLIDR_EL1, CTYPE5, 12, 3) 2014 FIELD(CLIDR_EL1, CTYPE6, 15, 3) 2015 FIELD(CLIDR_EL1, CTYPE7, 18, 3) 2016 FIELD(CLIDR_EL1, LOUIS, 21, 3) 2017 FIELD(CLIDR_EL1, LOC, 24, 3) 2018 FIELD(CLIDR_EL1, LOUU, 27, 3) 2019 FIELD(CLIDR_EL1, ICB, 30, 3) 2020 2021 /* When FEAT_CCIDX is implemented */ 2022 FIELD(CCSIDR_EL1, CCIDX_LINESIZE, 0, 3) 2023 FIELD(CCSIDR_EL1, CCIDX_ASSOCIATIVITY, 3, 21) 2024 FIELD(CCSIDR_EL1, CCIDX_NUMSETS, 32, 24) 2025 2026 /* When FEAT_CCIDX is not implemented */ 2027 FIELD(CCSIDR_EL1, LINESIZE, 0, 3) 2028 FIELD(CCSIDR_EL1, ASSOCIATIVITY, 3, 10) 2029 FIELD(CCSIDR_EL1, NUMSETS, 13, 15) 2030 2031 FIELD(CTR_EL0, IMINLINE, 0, 4) 2032 FIELD(CTR_EL0, L1IP, 14, 2) 2033 FIELD(CTR_EL0, DMINLINE, 16, 4) 2034 FIELD(CTR_EL0, ERG, 20, 4) 2035 FIELD(CTR_EL0, CWG, 24, 4) 2036 FIELD(CTR_EL0, IDC, 28, 1) 2037 FIELD(CTR_EL0, DIC, 29, 1) 2038 FIELD(CTR_EL0, TMINLINE, 32, 6) 2039 2040 FIELD(MIDR_EL1, REVISION, 0, 4) 2041 FIELD(MIDR_EL1, PARTNUM, 4, 12) 2042 FIELD(MIDR_EL1, ARCHITECTURE, 16, 4) 2043 FIELD(MIDR_EL1, VARIANT, 20, 4) 2044 FIELD(MIDR_EL1, IMPLEMENTER, 24, 8) 2045 2046 FIELD(ID_ISAR0, SWAP, 0, 4) 2047 FIELD(ID_ISAR0, BITCOUNT, 4, 4) 2048 FIELD(ID_ISAR0, BITFIELD, 8, 4) 2049 FIELD(ID_ISAR0, CMPBRANCH, 12, 4) 2050 FIELD(ID_ISAR0, COPROC, 16, 4) 2051 FIELD(ID_ISAR0, DEBUG, 20, 4) 2052 FIELD(ID_ISAR0, DIVIDE, 24, 4) 2053 2054 FIELD(ID_ISAR1, ENDIAN, 0, 4) 2055 FIELD(ID_ISAR1, EXCEPT, 4, 4) 2056 FIELD(ID_ISAR1, EXCEPT_AR, 8, 4) 2057 FIELD(ID_ISAR1, EXTEND, 12, 4) 2058 FIELD(ID_ISAR1, IFTHEN, 16, 4) 2059 FIELD(ID_ISAR1, IMMEDIATE, 20, 4) 2060 FIELD(ID_ISAR1, INTERWORK, 24, 4) 2061 FIELD(ID_ISAR1, JAZELLE, 28, 4) 2062 2063 FIELD(ID_ISAR2, LOADSTORE, 0, 4) 2064 FIELD(ID_ISAR2, MEMHINT, 4, 4) 2065 FIELD(ID_ISAR2, MULTIACCESSINT, 8, 4) 2066 FIELD(ID_ISAR2, MULT, 12, 4) 2067 FIELD(ID_ISAR2, MULTS, 16, 4) 2068 FIELD(ID_ISAR2, MULTU, 20, 4) 2069 FIELD(ID_ISAR2, PSR_AR, 24, 4) 2070 FIELD(ID_ISAR2, REVERSAL, 28, 4) 2071 2072 FIELD(ID_ISAR3, SATURATE, 0, 4) 2073 FIELD(ID_ISAR3, SIMD, 4, 4) 2074 FIELD(ID_ISAR3, SVC, 8, 4) 2075 FIELD(ID_ISAR3, SYNCHPRIM, 12, 4) 2076 FIELD(ID_ISAR3, TABBRANCH, 16, 4) 2077 FIELD(ID_ISAR3, T32COPY, 20, 4) 2078 FIELD(ID_ISAR3, TRUENOP, 24, 4) 2079 FIELD(ID_ISAR3, T32EE, 28, 4) 2080 2081 FIELD(ID_ISAR4, UNPRIV, 0, 4) 2082 FIELD(ID_ISAR4, WITHSHIFTS, 4, 4) 2083 FIELD(ID_ISAR4, WRITEBACK, 8, 4) 2084 FIELD(ID_ISAR4, SMC, 12, 4) 2085 FIELD(ID_ISAR4, BARRIER, 16, 4) 2086 FIELD(ID_ISAR4, SYNCHPRIM_FRAC, 20, 4) 2087 FIELD(ID_ISAR4, PSR_M, 24, 4) 2088 FIELD(ID_ISAR4, SWP_FRAC, 28, 4) 2089 2090 FIELD(ID_ISAR5, SEVL, 0, 4) 2091 FIELD(ID_ISAR5, AES, 4, 4) 2092 FIELD(ID_ISAR5, SHA1, 8, 4) 2093 FIELD(ID_ISAR5, SHA2, 12, 4) 2094 FIELD(ID_ISAR5, CRC32, 16, 4) 2095 FIELD(ID_ISAR5, RDM, 24, 4) 2096 FIELD(ID_ISAR5, VCMA, 28, 4) 2097 2098 FIELD(ID_ISAR6, JSCVT, 0, 4) 2099 FIELD(ID_ISAR6, DP, 4, 4) 2100 FIELD(ID_ISAR6, FHM, 8, 4) 2101 FIELD(ID_ISAR6, SB, 12, 4) 2102 FIELD(ID_ISAR6, SPECRES, 16, 4) 2103 FIELD(ID_ISAR6, BF16, 20, 4) 2104 FIELD(ID_ISAR6, I8MM, 24, 4) 2105 2106 FIELD(ID_MMFR0, VMSA, 0, 4) 2107 FIELD(ID_MMFR0, PMSA, 4, 4) 2108 FIELD(ID_MMFR0, OUTERSHR, 8, 4) 2109 FIELD(ID_MMFR0, SHARELVL, 12, 4) 2110 FIELD(ID_MMFR0, TCM, 16, 4) 2111 FIELD(ID_MMFR0, AUXREG, 20, 4) 2112 FIELD(ID_MMFR0, FCSE, 24, 4) 2113 FIELD(ID_MMFR0, INNERSHR, 28, 4) 2114 2115 FIELD(ID_MMFR1, L1HVDVA, 0, 4) 2116 FIELD(ID_MMFR1, L1UNIVA, 4, 4) 2117 FIELD(ID_MMFR1, L1HVDSW, 8, 4) 2118 FIELD(ID_MMFR1, L1UNISW, 12, 4) 2119 FIELD(ID_MMFR1, L1HVD, 16, 4) 2120 FIELD(ID_MMFR1, L1UNI, 20, 4) 2121 FIELD(ID_MMFR1, L1TSTCLN, 24, 4) 2122 FIELD(ID_MMFR1, BPRED, 28, 4) 2123 2124 FIELD(ID_MMFR2, L1HVDFG, 0, 4) 2125 FIELD(ID_MMFR2, L1HVDBG, 4, 4) 2126 FIELD(ID_MMFR2, L1HVDRNG, 8, 4) 2127 FIELD(ID_MMFR2, HVDTLB, 12, 4) 2128 FIELD(ID_MMFR2, UNITLB, 16, 4) 2129 FIELD(ID_MMFR2, MEMBARR, 20, 4) 2130 FIELD(ID_MMFR2, WFISTALL, 24, 4) 2131 FIELD(ID_MMFR2, HWACCFLG, 28, 4) 2132 2133 FIELD(ID_MMFR3, CMAINTVA, 0, 4) 2134 FIELD(ID_MMFR3, CMAINTSW, 4, 4) 2135 FIELD(ID_MMFR3, BPMAINT, 8, 4) 2136 FIELD(ID_MMFR3, MAINTBCST, 12, 4) 2137 FIELD(ID_MMFR3, PAN, 16, 4) 2138 FIELD(ID_MMFR3, COHWALK, 20, 4) 2139 FIELD(ID_MMFR3, CMEMSZ, 24, 4) 2140 FIELD(ID_MMFR3, SUPERSEC, 28, 4) 2141 2142 FIELD(ID_MMFR4, SPECSEI, 0, 4) 2143 FIELD(ID_MMFR4, AC2, 4, 4) 2144 FIELD(ID_MMFR4, XNX, 8, 4) 2145 FIELD(ID_MMFR4, CNP, 12, 4) 2146 FIELD(ID_MMFR4, HPDS, 16, 4) 2147 FIELD(ID_MMFR4, LSM, 20, 4) 2148 FIELD(ID_MMFR4, CCIDX, 24, 4) 2149 FIELD(ID_MMFR4, EVT, 28, 4) 2150 2151 FIELD(ID_MMFR5, ETS, 0, 4) 2152 FIELD(ID_MMFR5, NTLBPA, 4, 4) 2153 2154 FIELD(ID_PFR0, STATE0, 0, 4) 2155 FIELD(ID_PFR0, STATE1, 4, 4) 2156 FIELD(ID_PFR0, STATE2, 8, 4) 2157 FIELD(ID_PFR0, STATE3, 12, 4) 2158 FIELD(ID_PFR0, CSV2, 16, 4) 2159 FIELD(ID_PFR0, AMU, 20, 4) 2160 FIELD(ID_PFR0, DIT, 24, 4) 2161 FIELD(ID_PFR0, RAS, 28, 4) 2162 2163 FIELD(ID_PFR1, PROGMOD, 0, 4) 2164 FIELD(ID_PFR1, SECURITY, 4, 4) 2165 FIELD(ID_PFR1, MPROGMOD, 8, 4) 2166 FIELD(ID_PFR1, VIRTUALIZATION, 12, 4) 2167 FIELD(ID_PFR1, GENTIMER, 16, 4) 2168 FIELD(ID_PFR1, SEC_FRAC, 20, 4) 2169 FIELD(ID_PFR1, VIRT_FRAC, 24, 4) 2170 FIELD(ID_PFR1, GIC, 28, 4) 2171 2172 FIELD(ID_PFR2, CSV3, 0, 4) 2173 FIELD(ID_PFR2, SSBS, 4, 4) 2174 FIELD(ID_PFR2, RAS_FRAC, 8, 4) 2175 2176 FIELD(ID_AA64ISAR0, AES, 4, 4) 2177 FIELD(ID_AA64ISAR0, SHA1, 8, 4) 2178 FIELD(ID_AA64ISAR0, SHA2, 12, 4) 2179 FIELD(ID_AA64ISAR0, CRC32, 16, 4) 2180 FIELD(ID_AA64ISAR0, ATOMIC, 20, 4) 2181 FIELD(ID_AA64ISAR0, TME, 24, 4) 2182 FIELD(ID_AA64ISAR0, RDM, 28, 4) 2183 FIELD(ID_AA64ISAR0, SHA3, 32, 4) 2184 FIELD(ID_AA64ISAR0, SM3, 36, 4) 2185 FIELD(ID_AA64ISAR0, SM4, 40, 4) 2186 FIELD(ID_AA64ISAR0, DP, 44, 4) 2187 FIELD(ID_AA64ISAR0, FHM, 48, 4) 2188 FIELD(ID_AA64ISAR0, TS, 52, 4) 2189 FIELD(ID_AA64ISAR0, TLB, 56, 4) 2190 FIELD(ID_AA64ISAR0, RNDR, 60, 4) 2191 2192 FIELD(ID_AA64ISAR1, DPB, 0, 4) 2193 FIELD(ID_AA64ISAR1, APA, 4, 4) 2194 FIELD(ID_AA64ISAR1, API, 8, 4) 2195 FIELD(ID_AA64ISAR1, JSCVT, 12, 4) 2196 FIELD(ID_AA64ISAR1, FCMA, 16, 4) 2197 FIELD(ID_AA64ISAR1, LRCPC, 20, 4) 2198 FIELD(ID_AA64ISAR1, GPA, 24, 4) 2199 FIELD(ID_AA64ISAR1, GPI, 28, 4) 2200 FIELD(ID_AA64ISAR1, FRINTTS, 32, 4) 2201 FIELD(ID_AA64ISAR1, SB, 36, 4) 2202 FIELD(ID_AA64ISAR1, SPECRES, 40, 4) 2203 FIELD(ID_AA64ISAR1, BF16, 44, 4) 2204 FIELD(ID_AA64ISAR1, DGH, 48, 4) 2205 FIELD(ID_AA64ISAR1, I8MM, 52, 4) 2206 FIELD(ID_AA64ISAR1, XS, 56, 4) 2207 FIELD(ID_AA64ISAR1, LS64, 60, 4) 2208 2209 FIELD(ID_AA64ISAR2, WFXT, 0, 4) 2210 FIELD(ID_AA64ISAR2, RPRES, 4, 4) 2211 FIELD(ID_AA64ISAR2, GPA3, 8, 4) 2212 FIELD(ID_AA64ISAR2, APA3, 12, 4) 2213 FIELD(ID_AA64ISAR2, MOPS, 16, 4) 2214 FIELD(ID_AA64ISAR2, BC, 20, 4) 2215 FIELD(ID_AA64ISAR2, PAC_FRAC, 24, 4) 2216 FIELD(ID_AA64ISAR2, CLRBHB, 28, 4) 2217 FIELD(ID_AA64ISAR2, SYSREG_128, 32, 4) 2218 FIELD(ID_AA64ISAR2, SYSINSTR_128, 36, 4) 2219 FIELD(ID_AA64ISAR2, PRFMSLC, 40, 4) 2220 FIELD(ID_AA64ISAR2, RPRFM, 48, 4) 2221 FIELD(ID_AA64ISAR2, CSSC, 52, 4) 2222 FIELD(ID_AA64ISAR2, ATS1A, 60, 4) 2223 2224 FIELD(ID_AA64PFR0, EL0, 0, 4) 2225 FIELD(ID_AA64PFR0, EL1, 4, 4) 2226 FIELD(ID_AA64PFR0, EL2, 8, 4) 2227 FIELD(ID_AA64PFR0, EL3, 12, 4) 2228 FIELD(ID_AA64PFR0, FP, 16, 4) 2229 FIELD(ID_AA64PFR0, ADVSIMD, 20, 4) 2230 FIELD(ID_AA64PFR0, GIC, 24, 4) 2231 FIELD(ID_AA64PFR0, RAS, 28, 4) 2232 FIELD(ID_AA64PFR0, SVE, 32, 4) 2233 FIELD(ID_AA64PFR0, SEL2, 36, 4) 2234 FIELD(ID_AA64PFR0, MPAM, 40, 4) 2235 FIELD(ID_AA64PFR0, AMU, 44, 4) 2236 FIELD(ID_AA64PFR0, DIT, 48, 4) 2237 FIELD(ID_AA64PFR0, RME, 52, 4) 2238 FIELD(ID_AA64PFR0, CSV2, 56, 4) 2239 FIELD(ID_AA64PFR0, CSV3, 60, 4) 2240 2241 FIELD(ID_AA64PFR1, BT, 0, 4) 2242 FIELD(ID_AA64PFR1, SSBS, 4, 4) 2243 FIELD(ID_AA64PFR1, MTE, 8, 4) 2244 FIELD(ID_AA64PFR1, RAS_FRAC, 12, 4) 2245 FIELD(ID_AA64PFR1, MPAM_FRAC, 16, 4) 2246 FIELD(ID_AA64PFR1, SME, 24, 4) 2247 FIELD(ID_AA64PFR1, RNDR_TRAP, 28, 4) 2248 FIELD(ID_AA64PFR1, CSV2_FRAC, 32, 4) 2249 FIELD(ID_AA64PFR1, NMI, 36, 4) 2250 FIELD(ID_AA64PFR1, MTE_FRAC, 40, 4) 2251 FIELD(ID_AA64PFR1, GCS, 44, 4) 2252 FIELD(ID_AA64PFR1, THE, 48, 4) 2253 FIELD(ID_AA64PFR1, MTEX, 52, 4) 2254 FIELD(ID_AA64PFR1, DF2, 56, 4) 2255 FIELD(ID_AA64PFR1, PFAR, 60, 4) 2256 2257 FIELD(ID_AA64MMFR0, PARANGE, 0, 4) 2258 FIELD(ID_AA64MMFR0, ASIDBITS, 4, 4) 2259 FIELD(ID_AA64MMFR0, BIGEND, 8, 4) 2260 FIELD(ID_AA64MMFR0, SNSMEM, 12, 4) 2261 FIELD(ID_AA64MMFR0, BIGENDEL0, 16, 4) 2262 FIELD(ID_AA64MMFR0, TGRAN16, 20, 4) 2263 FIELD(ID_AA64MMFR0, TGRAN64, 24, 4) 2264 FIELD(ID_AA64MMFR0, TGRAN4, 28, 4) 2265 FIELD(ID_AA64MMFR0, TGRAN16_2, 32, 4) 2266 FIELD(ID_AA64MMFR0, TGRAN64_2, 36, 4) 2267 FIELD(ID_AA64MMFR0, TGRAN4_2, 40, 4) 2268 FIELD(ID_AA64MMFR0, EXS, 44, 4) 2269 FIELD(ID_AA64MMFR0, FGT, 56, 4) 2270 FIELD(ID_AA64MMFR0, ECV, 60, 4) 2271 2272 FIELD(ID_AA64MMFR1, HAFDBS, 0, 4) 2273 FIELD(ID_AA64MMFR1, VMIDBITS, 4, 4) 2274 FIELD(ID_AA64MMFR1, VH, 8, 4) 2275 FIELD(ID_AA64MMFR1, HPDS, 12, 4) 2276 FIELD(ID_AA64MMFR1, LO, 16, 4) 2277 FIELD(ID_AA64MMFR1, PAN, 20, 4) 2278 FIELD(ID_AA64MMFR1, SPECSEI, 24, 4) 2279 FIELD(ID_AA64MMFR1, XNX, 28, 4) 2280 FIELD(ID_AA64MMFR1, TWED, 32, 4) 2281 FIELD(ID_AA64MMFR1, ETS, 36, 4) 2282 FIELD(ID_AA64MMFR1, HCX, 40, 4) 2283 FIELD(ID_AA64MMFR1, AFP, 44, 4) 2284 FIELD(ID_AA64MMFR1, NTLBPA, 48, 4) 2285 FIELD(ID_AA64MMFR1, TIDCP1, 52, 4) 2286 FIELD(ID_AA64MMFR1, CMOW, 56, 4) 2287 FIELD(ID_AA64MMFR1, ECBHB, 60, 4) 2288 2289 FIELD(ID_AA64MMFR2, CNP, 0, 4) 2290 FIELD(ID_AA64MMFR2, UAO, 4, 4) 2291 FIELD(ID_AA64MMFR2, LSM, 8, 4) 2292 FIELD(ID_AA64MMFR2, IESB, 12, 4) 2293 FIELD(ID_AA64MMFR2, VARANGE, 16, 4) 2294 FIELD(ID_AA64MMFR2, CCIDX, 20, 4) 2295 FIELD(ID_AA64MMFR2, NV, 24, 4) 2296 FIELD(ID_AA64MMFR2, ST, 28, 4) 2297 FIELD(ID_AA64MMFR2, AT, 32, 4) 2298 FIELD(ID_AA64MMFR2, IDS, 36, 4) 2299 FIELD(ID_AA64MMFR2, FWB, 40, 4) 2300 FIELD(ID_AA64MMFR2, TTL, 48, 4) 2301 FIELD(ID_AA64MMFR2, BBM, 52, 4) 2302 FIELD(ID_AA64MMFR2, EVT, 56, 4) 2303 FIELD(ID_AA64MMFR2, E0PD, 60, 4) 2304 2305 FIELD(ID_AA64MMFR3, TCRX, 0, 4) 2306 FIELD(ID_AA64MMFR3, SCTLRX, 4, 4) 2307 FIELD(ID_AA64MMFR3, S1PIE, 8, 4) 2308 FIELD(ID_AA64MMFR3, S2PIE, 12, 4) 2309 FIELD(ID_AA64MMFR3, S1POE, 16, 4) 2310 FIELD(ID_AA64MMFR3, S2POE, 20, 4) 2311 FIELD(ID_AA64MMFR3, AIE, 24, 4) 2312 FIELD(ID_AA64MMFR3, MEC, 28, 4) 2313 FIELD(ID_AA64MMFR3, D128, 32, 4) 2314 FIELD(ID_AA64MMFR3, D128_2, 36, 4) 2315 FIELD(ID_AA64MMFR3, SNERR, 40, 4) 2316 FIELD(ID_AA64MMFR3, ANERR, 44, 4) 2317 FIELD(ID_AA64MMFR3, SDERR, 52, 4) 2318 FIELD(ID_AA64MMFR3, ADERR, 56, 4) 2319 FIELD(ID_AA64MMFR3, SPEC_FPACC, 60, 4) 2320 2321 FIELD(ID_AA64DFR0, DEBUGVER, 0, 4) 2322 FIELD(ID_AA64DFR0, TRACEVER, 4, 4) 2323 FIELD(ID_AA64DFR0, PMUVER, 8, 4) 2324 FIELD(ID_AA64DFR0, BRPS, 12, 4) 2325 FIELD(ID_AA64DFR0, PMSS, 16, 4) 2326 FIELD(ID_AA64DFR0, WRPS, 20, 4) 2327 FIELD(ID_AA64DFR0, SEBEP, 24, 4) 2328 FIELD(ID_AA64DFR0, CTX_CMPS, 28, 4) 2329 FIELD(ID_AA64DFR0, PMSVER, 32, 4) 2330 FIELD(ID_AA64DFR0, DOUBLELOCK, 36, 4) 2331 FIELD(ID_AA64DFR0, TRACEFILT, 40, 4) 2332 FIELD(ID_AA64DFR0, TRACEBUFFER, 44, 4) 2333 FIELD(ID_AA64DFR0, MTPMU, 48, 4) 2334 FIELD(ID_AA64DFR0, BRBE, 52, 4) 2335 FIELD(ID_AA64DFR0, EXTTRCBUFF, 56, 4) 2336 FIELD(ID_AA64DFR0, HPMN0, 60, 4) 2337 2338 FIELD(ID_AA64ZFR0, SVEVER, 0, 4) 2339 FIELD(ID_AA64ZFR0, AES, 4, 4) 2340 FIELD(ID_AA64ZFR0, BITPERM, 16, 4) 2341 FIELD(ID_AA64ZFR0, BFLOAT16, 20, 4) 2342 FIELD(ID_AA64ZFR0, B16B16, 24, 4) 2343 FIELD(ID_AA64ZFR0, SHA3, 32, 4) 2344 FIELD(ID_AA64ZFR0, SM4, 40, 4) 2345 FIELD(ID_AA64ZFR0, I8MM, 44, 4) 2346 FIELD(ID_AA64ZFR0, F32MM, 52, 4) 2347 FIELD(ID_AA64ZFR0, F64MM, 56, 4) 2348 2349 FIELD(ID_AA64SMFR0, F32F32, 32, 1) 2350 FIELD(ID_AA64SMFR0, BI32I32, 33, 1) 2351 FIELD(ID_AA64SMFR0, B16F32, 34, 1) 2352 FIELD(ID_AA64SMFR0, F16F32, 35, 1) 2353 FIELD(ID_AA64SMFR0, I8I32, 36, 4) 2354 FIELD(ID_AA64SMFR0, F16F16, 42, 1) 2355 FIELD(ID_AA64SMFR0, B16B16, 43, 1) 2356 FIELD(ID_AA64SMFR0, I16I32, 44, 4) 2357 FIELD(ID_AA64SMFR0, F64F64, 48, 1) 2358 FIELD(ID_AA64SMFR0, I16I64, 52, 4) 2359 FIELD(ID_AA64SMFR0, SMEVER, 56, 4) 2360 FIELD(ID_AA64SMFR0, FA64, 63, 1) 2361 2362 FIELD(ID_DFR0, COPDBG, 0, 4) 2363 FIELD(ID_DFR0, COPSDBG, 4, 4) 2364 FIELD(ID_DFR0, MMAPDBG, 8, 4) 2365 FIELD(ID_DFR0, COPTRC, 12, 4) 2366 FIELD(ID_DFR0, MMAPTRC, 16, 4) 2367 FIELD(ID_DFR0, MPROFDBG, 20, 4) 2368 FIELD(ID_DFR0, PERFMON, 24, 4) 2369 FIELD(ID_DFR0, TRACEFILT, 28, 4) 2370 2371 FIELD(ID_DFR1, MTPMU, 0, 4) 2372 FIELD(ID_DFR1, HPMN0, 4, 4) 2373 2374 FIELD(DBGDIDR, SE_IMP, 12, 1) 2375 FIELD(DBGDIDR, NSUHD_IMP, 14, 1) 2376 FIELD(DBGDIDR, VERSION, 16, 4) 2377 FIELD(DBGDIDR, CTX_CMPS, 20, 4) 2378 FIELD(DBGDIDR, BRPS, 24, 4) 2379 FIELD(DBGDIDR, WRPS, 28, 4) 2380 2381 FIELD(DBGDEVID, PCSAMPLE, 0, 4) 2382 FIELD(DBGDEVID, WPADDRMASK, 4, 4) 2383 FIELD(DBGDEVID, BPADDRMASK, 8, 4) 2384 FIELD(DBGDEVID, VECTORCATCH, 12, 4) 2385 FIELD(DBGDEVID, VIRTEXTNS, 16, 4) 2386 FIELD(DBGDEVID, DOUBLELOCK, 20, 4) 2387 FIELD(DBGDEVID, AUXREGS, 24, 4) 2388 FIELD(DBGDEVID, CIDMASK, 28, 4) 2389 2390 FIELD(DBGDEVID1, PCSROFFSET, 0, 4) 2391 2392 FIELD(MVFR0, SIMDREG, 0, 4) 2393 FIELD(MVFR0, FPSP, 4, 4) 2394 FIELD(MVFR0, FPDP, 8, 4) 2395 FIELD(MVFR0, FPTRAP, 12, 4) 2396 FIELD(MVFR0, FPDIVIDE, 16, 4) 2397 FIELD(MVFR0, FPSQRT, 20, 4) 2398 FIELD(MVFR0, FPSHVEC, 24, 4) 2399 FIELD(MVFR0, FPROUND, 28, 4) 2400 2401 FIELD(MVFR1, FPFTZ, 0, 4) 2402 FIELD(MVFR1, FPDNAN, 4, 4) 2403 FIELD(MVFR1, SIMDLS, 8, 4) /* A-profile only */ 2404 FIELD(MVFR1, SIMDINT, 12, 4) /* A-profile only */ 2405 FIELD(MVFR1, SIMDSP, 16, 4) /* A-profile only */ 2406 FIELD(MVFR1, SIMDHP, 20, 4) /* A-profile only */ 2407 FIELD(MVFR1, MVE, 8, 4) /* M-profile only */ 2408 FIELD(MVFR1, FP16, 20, 4) /* M-profile only */ 2409 FIELD(MVFR1, FPHP, 24, 4) 2410 FIELD(MVFR1, SIMDFMAC, 28, 4) 2411 2412 FIELD(MVFR2, SIMDMISC, 0, 4) 2413 FIELD(MVFR2, FPMISC, 4, 4) 2414 2415 FIELD(GPCCR, PPS, 0, 3) 2416 FIELD(GPCCR, IRGN, 8, 2) 2417 FIELD(GPCCR, ORGN, 10, 2) 2418 FIELD(GPCCR, SH, 12, 2) 2419 FIELD(GPCCR, PGS, 14, 2) 2420 FIELD(GPCCR, GPC, 16, 1) 2421 FIELD(GPCCR, GPCP, 17, 1) 2422 FIELD(GPCCR, L0GPTSZ, 20, 4) 2423 2424 FIELD(MFAR, FPA, 12, 40) 2425 FIELD(MFAR, NSE, 62, 1) 2426 FIELD(MFAR, NS, 63, 1) 2427 2428 QEMU_BUILD_BUG_ON(ARRAY_SIZE(((ARMCPU *)0)->ccsidr) <= R_V7M_CSSELR_INDEX_MASK); 2429 2430 /* If adding a feature bit which corresponds to a Linux ELF 2431 * HWCAP bit, remember to update the feature-bit-to-hwcap 2432 * mapping in linux-user/elfload.c:get_elf_hwcap(). 2433 */ 2434 enum arm_features { 2435 ARM_FEATURE_AUXCR, /* ARM1026 Auxiliary control register. */ 2436 ARM_FEATURE_XSCALE, /* Intel XScale extensions. */ 2437 ARM_FEATURE_IWMMXT, /* Intel iwMMXt extension. */ 2438 ARM_FEATURE_V6, 2439 ARM_FEATURE_V6K, 2440 ARM_FEATURE_V7, 2441 ARM_FEATURE_THUMB2, 2442 ARM_FEATURE_PMSA, /* no MMU; may have Memory Protection Unit */ 2443 ARM_FEATURE_NEON, 2444 ARM_FEATURE_M, /* Microcontroller profile. */ 2445 ARM_FEATURE_OMAPCP, /* OMAP specific CP15 ops handling. */ 2446 ARM_FEATURE_THUMB2EE, 2447 ARM_FEATURE_V7MP, /* v7 Multiprocessing Extensions */ 2448 ARM_FEATURE_V7VE, /* v7 Virtualization Extensions (non-EL2 parts) */ 2449 ARM_FEATURE_V4T, 2450 ARM_FEATURE_V5, 2451 ARM_FEATURE_STRONGARM, 2452 ARM_FEATURE_VAPA, /* cp15 VA to PA lookups */ 2453 ARM_FEATURE_GENERIC_TIMER, 2454 ARM_FEATURE_MVFR, /* Media and VFP Feature Registers 0 and 1 */ 2455 ARM_FEATURE_DUMMY_C15_REGS, /* RAZ/WI all of cp15 crn=15 */ 2456 ARM_FEATURE_CACHE_TEST_CLEAN, /* 926/1026 style test-and-clean ops */ 2457 ARM_FEATURE_CACHE_DIRTY_REG, /* 1136/1176 cache dirty status register */ 2458 ARM_FEATURE_CACHE_BLOCK_OPS, /* v6 optional cache block operations */ 2459 ARM_FEATURE_MPIDR, /* has cp15 MPIDR */ 2460 ARM_FEATURE_LPAE, /* has Large Physical Address Extension */ 2461 ARM_FEATURE_V8, 2462 ARM_FEATURE_AARCH64, /* supports 64 bit mode */ 2463 ARM_FEATURE_CBAR, /* has cp15 CBAR */ 2464 ARM_FEATURE_CBAR_RO, /* has cp15 CBAR and it is read-only */ 2465 ARM_FEATURE_EL2, /* has EL2 Virtualization support */ 2466 ARM_FEATURE_EL3, /* has EL3 Secure monitor support */ 2467 ARM_FEATURE_THUMB_DSP, /* DSP insns supported in the Thumb encodings */ 2468 ARM_FEATURE_PMU, /* has PMU support */ 2469 ARM_FEATURE_VBAR, /* has cp15 VBAR */ 2470 ARM_FEATURE_M_SECURITY, /* M profile Security Extension */ 2471 ARM_FEATURE_M_MAIN, /* M profile Main Extension */ 2472 ARM_FEATURE_V8_1M, /* M profile extras only in v8.1M and later */ 2473 /* 2474 * ARM_FEATURE_BACKCOMPAT_CNTFRQ makes the CPU default cntfrq be 62.5MHz 2475 * if the board doesn't set a value, instead of 1GHz. It is for backwards 2476 * compatibility and used only with CPU definitions that were already 2477 * in QEMU before we changed the default. It should not be set on any 2478 * CPU types added in future. 2479 */ 2480 ARM_FEATURE_BACKCOMPAT_CNTFRQ, /* 62.5MHz timer default */ 2481 }; 2482 2483 static inline int arm_feature(CPUARMState *env, int feature) 2484 { 2485 return (env->features & (1ULL << feature)) != 0; 2486 } 2487 2488 void arm_cpu_finalize_features(ARMCPU *cpu, Error **errp); 2489 2490 /* 2491 * ARM v9 security states. 2492 * The ordering of the enumeration corresponds to the low 2 bits 2493 * of the GPI value, and (except for Root) the concat of NSE:NS. 2494 */ 2495 2496 typedef enum ARMSecuritySpace { 2497 ARMSS_Secure = 0, 2498 ARMSS_NonSecure = 1, 2499 ARMSS_Root = 2, 2500 ARMSS_Realm = 3, 2501 } ARMSecuritySpace; 2502 2503 /* Return true if @space is secure, in the pre-v9 sense. */ 2504 static inline bool arm_space_is_secure(ARMSecuritySpace space) 2505 { 2506 return space == ARMSS_Secure || space == ARMSS_Root; 2507 } 2508 2509 /* Return the ARMSecuritySpace for @secure, assuming !RME or EL[0-2]. */ 2510 static inline ARMSecuritySpace arm_secure_to_space(bool secure) 2511 { 2512 return secure ? ARMSS_Secure : ARMSS_NonSecure; 2513 } 2514 2515 #if !defined(CONFIG_USER_ONLY) 2516 /** 2517 * arm_security_space_below_el3: 2518 * @env: cpu context 2519 * 2520 * Return the security space of exception levels below EL3, following 2521 * an exception return to those levels. Unlike arm_security_space, 2522 * this doesn't care about the current EL. 2523 */ 2524 ARMSecuritySpace arm_security_space_below_el3(CPUARMState *env); 2525 2526 /** 2527 * arm_is_secure_below_el3: 2528 * @env: cpu context 2529 * 2530 * Return true if exception levels below EL3 are in secure state, 2531 * or would be following an exception return to those levels. 2532 */ 2533 static inline bool arm_is_secure_below_el3(CPUARMState *env) 2534 { 2535 ARMSecuritySpace ss = arm_security_space_below_el3(env); 2536 return ss == ARMSS_Secure; 2537 } 2538 2539 /* Return true if the CPU is AArch64 EL3 or AArch32 Mon */ 2540 static inline bool arm_is_el3_or_mon(CPUARMState *env) 2541 { 2542 assert(!arm_feature(env, ARM_FEATURE_M)); 2543 if (arm_feature(env, ARM_FEATURE_EL3)) { 2544 if (is_a64(env) && extract32(env->pstate, 2, 2) == 3) { 2545 /* CPU currently in AArch64 state and EL3 */ 2546 return true; 2547 } else if (!is_a64(env) && 2548 (env->uncached_cpsr & CPSR_M) == ARM_CPU_MODE_MON) { 2549 /* CPU currently in AArch32 state and monitor mode */ 2550 return true; 2551 } 2552 } 2553 return false; 2554 } 2555 2556 /** 2557 * arm_security_space: 2558 * @env: cpu context 2559 * 2560 * Return the current security space of the cpu. 2561 */ 2562 ARMSecuritySpace arm_security_space(CPUARMState *env); 2563 2564 /** 2565 * arm_is_secure: 2566 * @env: cpu context 2567 * 2568 * Return true if the processor is in secure state. 2569 */ 2570 static inline bool arm_is_secure(CPUARMState *env) 2571 { 2572 return arm_space_is_secure(arm_security_space(env)); 2573 } 2574 2575 /* 2576 * Return true if the current security state has AArch64 EL2 or AArch32 Hyp. 2577 * This corresponds to the pseudocode EL2Enabled(). 2578 */ 2579 static inline bool arm_is_el2_enabled_secstate(CPUARMState *env, 2580 ARMSecuritySpace space) 2581 { 2582 assert(space != ARMSS_Root); 2583 return arm_feature(env, ARM_FEATURE_EL2) 2584 && (space != ARMSS_Secure || (env->cp15.scr_el3 & SCR_EEL2)); 2585 } 2586 2587 static inline bool arm_is_el2_enabled(CPUARMState *env) 2588 { 2589 return arm_is_el2_enabled_secstate(env, arm_security_space_below_el3(env)); 2590 } 2591 2592 #else 2593 static inline ARMSecuritySpace arm_security_space_below_el3(CPUARMState *env) 2594 { 2595 return ARMSS_NonSecure; 2596 } 2597 2598 static inline bool arm_is_secure_below_el3(CPUARMState *env) 2599 { 2600 return false; 2601 } 2602 2603 static inline bool arm_is_el3_or_mon(CPUARMState *env) 2604 { 2605 return false; 2606 } 2607 2608 static inline ARMSecuritySpace arm_security_space(CPUARMState *env) 2609 { 2610 return ARMSS_NonSecure; 2611 } 2612 2613 static inline bool arm_is_secure(CPUARMState *env) 2614 { 2615 return false; 2616 } 2617 2618 static inline bool arm_is_el2_enabled_secstate(CPUARMState *env, 2619 ARMSecuritySpace space) 2620 { 2621 return false; 2622 } 2623 2624 static inline bool arm_is_el2_enabled(CPUARMState *env) 2625 { 2626 return false; 2627 } 2628 #endif 2629 2630 /** 2631 * arm_hcr_el2_eff(): Return the effective value of HCR_EL2. 2632 * E.g. when in secure state, fields in HCR_EL2 are suppressed, 2633 * "for all purposes other than a direct read or write access of HCR_EL2." 2634 * Not included here is HCR_RW. 2635 */ 2636 uint64_t arm_hcr_el2_eff_secstate(CPUARMState *env, ARMSecuritySpace space); 2637 uint64_t arm_hcr_el2_eff(CPUARMState *env); 2638 uint64_t arm_hcrx_el2_eff(CPUARMState *env); 2639 2640 /* 2641 * Function for determining whether guest cp register reads and writes should 2642 * access the secure or non-secure bank of a cp register. When EL3 is 2643 * operating in AArch32 state, the NS-bit determines whether the secure 2644 * instance of a cp register should be used. When EL3 is AArch64 (or if 2645 * it doesn't exist at all) then there is no register banking, and all 2646 * accesses are to the non-secure version. 2647 */ 2648 bool access_secure_reg(CPUARMState *env); 2649 2650 uint32_t arm_phys_excp_target_el(CPUState *cs, uint32_t excp_idx, 2651 uint32_t cur_el, bool secure); 2652 2653 /* Return the highest implemented Exception Level */ 2654 static inline int arm_highest_el(CPUARMState *env) 2655 { 2656 if (arm_feature(env, ARM_FEATURE_EL3)) { 2657 return 3; 2658 } 2659 if (arm_feature(env, ARM_FEATURE_EL2)) { 2660 return 2; 2661 } 2662 return 1; 2663 } 2664 2665 /* Return true if a v7M CPU is in Handler mode */ 2666 static inline bool arm_v7m_is_handler_mode(CPUARMState *env) 2667 { 2668 return env->v7m.exception != 0; 2669 } 2670 2671 /** 2672 * write_list_to_cpustate 2673 * @cpu: ARMCPU 2674 * 2675 * For each register listed in the ARMCPU cpreg_indexes list, write 2676 * its value from the cpreg_values list into the ARMCPUState structure. 2677 * This updates TCG's working data structures from KVM data or 2678 * from incoming migration state. 2679 * 2680 * Returns: true if all register values were updated correctly, 2681 * false if some register was unknown or could not be written. 2682 * Note that we do not stop early on failure -- we will attempt 2683 * writing all registers in the list. 2684 */ 2685 bool write_list_to_cpustate(ARMCPU *cpu); 2686 2687 /** 2688 * write_cpustate_to_list: 2689 * @cpu: ARMCPU 2690 * @kvm_sync: true if this is for syncing back to KVM 2691 * 2692 * For each register listed in the ARMCPU cpreg_indexes list, write 2693 * its value from the ARMCPUState structure into the cpreg_values list. 2694 * This is used to copy info from TCG's working data structures into 2695 * KVM or for outbound migration. 2696 * 2697 * @kvm_sync is true if we are doing this in order to sync the 2698 * register state back to KVM. In this case we will only update 2699 * values in the list if the previous list->cpustate sync actually 2700 * successfully wrote the CPU state. Otherwise we will keep the value 2701 * that is in the list. 2702 * 2703 * Returns: true if all register values were read correctly, 2704 * false if some register was unknown or could not be read. 2705 * Note that we do not stop early on failure -- we will attempt 2706 * reading all registers in the list. 2707 */ 2708 bool write_cpustate_to_list(ARMCPU *cpu, bool kvm_sync); 2709 2710 #define ARM_CPUID_TI915T 0x54029152 2711 #define ARM_CPUID_TI925T 0x54029252 2712 2713 #define CPU_RESOLVING_TYPE TYPE_ARM_CPU 2714 2715 #define TYPE_ARM_HOST_CPU "host-" TYPE_ARM_CPU 2716 2717 /* ARM has the following "translation regimes" (as the ARM ARM calls them): 2718 * 2719 * If EL3 is 64-bit: 2720 * + NonSecure EL1 & 0 stage 1 2721 * + NonSecure EL1 & 0 stage 2 2722 * + NonSecure EL2 2723 * + NonSecure EL2 & 0 (ARMv8.1-VHE) 2724 * + Secure EL1 & 0 stage 1 2725 * + Secure EL1 & 0 stage 2 (FEAT_SEL2) 2726 * + Secure EL2 (FEAT_SEL2) 2727 * + Secure EL2 & 0 (FEAT_SEL2) 2728 * + Realm EL1 & 0 stage 1 (FEAT_RME) 2729 * + Realm EL1 & 0 stage 2 (FEAT_RME) 2730 * + Realm EL2 (FEAT_RME) 2731 * + EL3 2732 * If EL3 is 32-bit: 2733 * + NonSecure PL1 & 0 stage 1 2734 * + NonSecure PL1 & 0 stage 2 2735 * + NonSecure PL2 2736 * + Secure PL1 & 0 2737 * (reminder: for 32 bit EL3, Secure PL1 is *EL3*, not EL1.) 2738 * 2739 * For QEMU, an mmu_idx is not quite the same as a translation regime because: 2740 * 1. we need to split the "EL1 & 0" and "EL2 & 0" regimes into two mmu_idxes, 2741 * because they may differ in access permissions even if the VA->PA map is 2742 * the same 2743 * 2. we want to cache in our TLB the full VA->IPA->PA lookup for a stage 1+2 2744 * translation, which means that we have one mmu_idx that deals with two 2745 * concatenated translation regimes [this sort of combined s1+2 TLB is 2746 * architecturally permitted] 2747 * 3. we don't need to allocate an mmu_idx to translations that we won't be 2748 * handling via the TLB. The only way to do a stage 1 translation without 2749 * the immediate stage 2 translation is via the ATS or AT system insns, 2750 * which can be slow-pathed and always do a page table walk. 2751 * The only use of stage 2 translations is either as part of an s1+2 2752 * lookup or when loading the descriptors during a stage 1 page table walk, 2753 * and in both those cases we don't use the TLB. 2754 * 4. we can also safely fold together the "32 bit EL3" and "64 bit EL3" 2755 * translation regimes, because they map reasonably well to each other 2756 * and they can't both be active at the same time. 2757 * 5. we want to be able to use the TLB for accesses done as part of a 2758 * stage1 page table walk, rather than having to walk the stage2 page 2759 * table over and over. 2760 * 6. we need separate EL1/EL2 mmu_idx for handling the Privileged Access 2761 * Never (PAN) bit within PSTATE. 2762 * 7. we fold together most secure and non-secure regimes for A-profile, 2763 * because there are no banked system registers for aarch64, so the 2764 * process of switching between secure and non-secure is 2765 * already heavyweight. 2766 * 8. we cannot fold together Stage 2 Secure and Stage 2 NonSecure, 2767 * because both are in use simultaneously for Secure EL2. 2768 * 2769 * This gives us the following list of cases: 2770 * 2771 * EL0 EL1&0 stage 1+2 (aka NS PL0 PL1&0 stage 1+2) 2772 * EL1 EL1&0 stage 1+2 (aka NS PL1 PL1&0 stage 1+2) 2773 * EL1 EL1&0 stage 1+2 +PAN (aka NS PL1 P1&0 stage 1+2 +PAN) 2774 * EL0 EL2&0 2775 * EL2 EL2&0 2776 * EL2 EL2&0 +PAN 2777 * EL2 (aka NS PL2) 2778 * EL3 (aka AArch32 S PL1 PL1&0) 2779 * AArch32 S PL0 PL1&0 (we call this EL30_0) 2780 * AArch32 S PL1 PL1&0 +PAN (we call this EL30_3_PAN) 2781 * Stage2 Secure 2782 * Stage2 NonSecure 2783 * plus one TLB per Physical address space: S, NS, Realm, Root 2784 * 2785 * for a total of 16 different mmu_idx. 2786 * 2787 * R profile CPUs have an MPU, but can use the same set of MMU indexes 2788 * as A profile. They only need to distinguish EL0 and EL1 (and 2789 * EL2 for cores like the Cortex-R52). 2790 * 2791 * M profile CPUs are rather different as they do not have a true MMU. 2792 * They have the following different MMU indexes: 2793 * User 2794 * Privileged 2795 * User, execution priority negative (ie the MPU HFNMIENA bit may apply) 2796 * Privileged, execution priority negative (ditto) 2797 * If the CPU supports the v8M Security Extension then there are also: 2798 * Secure User 2799 * Secure Privileged 2800 * Secure User, execution priority negative 2801 * Secure Privileged, execution priority negative 2802 * 2803 * The ARMMMUIdx and the mmu index value used by the core QEMU TLB code 2804 * are not quite the same -- different CPU types (most notably M profile 2805 * vs A/R profile) would like to use MMU indexes with different semantics, 2806 * but since we don't ever need to use all of those in a single CPU we 2807 * can avoid having to set NB_MMU_MODES to "total number of A profile MMU 2808 * modes + total number of M profile MMU modes". The lower bits of 2809 * ARMMMUIdx are the core TLB mmu index, and the higher bits are always 2810 * the same for any particular CPU. 2811 * Variables of type ARMMUIdx are always full values, and the core 2812 * index values are in variables of type 'int'. 2813 * 2814 * Our enumeration includes at the end some entries which are not "true" 2815 * mmu_idx values in that they don't have corresponding TLBs and are only 2816 * valid for doing slow path page table walks. 2817 * 2818 * The constant names here are patterned after the general style of the names 2819 * of the AT/ATS operations. 2820 * The values used are carefully arranged to make mmu_idx => EL lookup easy. 2821 * For M profile we arrange them to have a bit for priv, a bit for negpri 2822 * and a bit for secure. 2823 */ 2824 #define ARM_MMU_IDX_A 0x10 /* A profile */ 2825 #define ARM_MMU_IDX_NOTLB 0x20 /* does not have a TLB */ 2826 #define ARM_MMU_IDX_M 0x40 /* M profile */ 2827 2828 /* Meanings of the bits for M profile mmu idx values */ 2829 #define ARM_MMU_IDX_M_PRIV 0x1 2830 #define ARM_MMU_IDX_M_NEGPRI 0x2 2831 #define ARM_MMU_IDX_M_S 0x4 /* Secure */ 2832 2833 #define ARM_MMU_IDX_TYPE_MASK \ 2834 (ARM_MMU_IDX_A | ARM_MMU_IDX_M | ARM_MMU_IDX_NOTLB) 2835 #define ARM_MMU_IDX_COREIDX_MASK 0xf 2836 2837 typedef enum ARMMMUIdx { 2838 /* 2839 * A-profile. 2840 */ 2841 ARMMMUIdx_E10_0 = 0 | ARM_MMU_IDX_A, 2842 ARMMMUIdx_E20_0 = 1 | ARM_MMU_IDX_A, 2843 ARMMMUIdx_E10_1 = 2 | ARM_MMU_IDX_A, 2844 ARMMMUIdx_E20_2 = 3 | ARM_MMU_IDX_A, 2845 ARMMMUIdx_E10_1_PAN = 4 | ARM_MMU_IDX_A, 2846 ARMMMUIdx_E20_2_PAN = 5 | ARM_MMU_IDX_A, 2847 ARMMMUIdx_E2 = 6 | ARM_MMU_IDX_A, 2848 ARMMMUIdx_E3 = 7 | ARM_MMU_IDX_A, 2849 ARMMMUIdx_E30_0 = 8 | ARM_MMU_IDX_A, 2850 ARMMMUIdx_E30_3_PAN = 9 | ARM_MMU_IDX_A, 2851 2852 /* 2853 * Used for second stage of an S12 page table walk, or for descriptor 2854 * loads during first stage of an S1 page table walk. Note that both 2855 * are in use simultaneously for SecureEL2: the security state for 2856 * the S2 ptw is selected by the NS bit from the S1 ptw. 2857 */ 2858 ARMMMUIdx_Stage2_S = 10 | ARM_MMU_IDX_A, 2859 ARMMMUIdx_Stage2 = 11 | ARM_MMU_IDX_A, 2860 2861 /* TLBs with 1-1 mapping to the physical address spaces. */ 2862 ARMMMUIdx_Phys_S = 12 | ARM_MMU_IDX_A, 2863 ARMMMUIdx_Phys_NS = 13 | ARM_MMU_IDX_A, 2864 ARMMMUIdx_Phys_Root = 14 | ARM_MMU_IDX_A, 2865 ARMMMUIdx_Phys_Realm = 15 | ARM_MMU_IDX_A, 2866 2867 /* 2868 * These are not allocated TLBs and are used only for AT system 2869 * instructions or for the first stage of an S12 page table walk. 2870 */ 2871 ARMMMUIdx_Stage1_E0 = 0 | ARM_MMU_IDX_NOTLB, 2872 ARMMMUIdx_Stage1_E1 = 1 | ARM_MMU_IDX_NOTLB, 2873 ARMMMUIdx_Stage1_E1_PAN = 2 | ARM_MMU_IDX_NOTLB, 2874 2875 /* 2876 * M-profile. 2877 */ 2878 ARMMMUIdx_MUser = ARM_MMU_IDX_M, 2879 ARMMMUIdx_MPriv = ARM_MMU_IDX_M | ARM_MMU_IDX_M_PRIV, 2880 ARMMMUIdx_MUserNegPri = ARMMMUIdx_MUser | ARM_MMU_IDX_M_NEGPRI, 2881 ARMMMUIdx_MPrivNegPri = ARMMMUIdx_MPriv | ARM_MMU_IDX_M_NEGPRI, 2882 ARMMMUIdx_MSUser = ARMMMUIdx_MUser | ARM_MMU_IDX_M_S, 2883 ARMMMUIdx_MSPriv = ARMMMUIdx_MPriv | ARM_MMU_IDX_M_S, 2884 ARMMMUIdx_MSUserNegPri = ARMMMUIdx_MUserNegPri | ARM_MMU_IDX_M_S, 2885 ARMMMUIdx_MSPrivNegPri = ARMMMUIdx_MPrivNegPri | ARM_MMU_IDX_M_S, 2886 } ARMMMUIdx; 2887 2888 /* 2889 * Bit macros for the core-mmu-index values for each index, 2890 * for use when calling tlb_flush_by_mmuidx() and friends. 2891 */ 2892 #define TO_CORE_BIT(NAME) \ 2893 ARMMMUIdxBit_##NAME = 1 << (ARMMMUIdx_##NAME & ARM_MMU_IDX_COREIDX_MASK) 2894 2895 typedef enum ARMMMUIdxBit { 2896 TO_CORE_BIT(E10_0), 2897 TO_CORE_BIT(E20_0), 2898 TO_CORE_BIT(E10_1), 2899 TO_CORE_BIT(E10_1_PAN), 2900 TO_CORE_BIT(E2), 2901 TO_CORE_BIT(E20_2), 2902 TO_CORE_BIT(E20_2_PAN), 2903 TO_CORE_BIT(E3), 2904 TO_CORE_BIT(E30_0), 2905 TO_CORE_BIT(E30_3_PAN), 2906 TO_CORE_BIT(Stage2), 2907 TO_CORE_BIT(Stage2_S), 2908 2909 TO_CORE_BIT(MUser), 2910 TO_CORE_BIT(MPriv), 2911 TO_CORE_BIT(MUserNegPri), 2912 TO_CORE_BIT(MPrivNegPri), 2913 TO_CORE_BIT(MSUser), 2914 TO_CORE_BIT(MSPriv), 2915 TO_CORE_BIT(MSUserNegPri), 2916 TO_CORE_BIT(MSPrivNegPri), 2917 } ARMMMUIdxBit; 2918 2919 #undef TO_CORE_BIT 2920 2921 #define MMU_USER_IDX 0 2922 2923 /* Indexes used when registering address spaces with cpu_address_space_init */ 2924 typedef enum ARMASIdx { 2925 ARMASIdx_NS = 0, 2926 ARMASIdx_S = 1, 2927 ARMASIdx_TagNS = 2, 2928 ARMASIdx_TagS = 3, 2929 } ARMASIdx; 2930 2931 static inline ARMMMUIdx arm_space_to_phys(ARMSecuritySpace space) 2932 { 2933 /* Assert the relative order of the physical mmu indexes. */ 2934 QEMU_BUILD_BUG_ON(ARMSS_Secure != 0); 2935 QEMU_BUILD_BUG_ON(ARMMMUIdx_Phys_NS != ARMMMUIdx_Phys_S + ARMSS_NonSecure); 2936 QEMU_BUILD_BUG_ON(ARMMMUIdx_Phys_Root != ARMMMUIdx_Phys_S + ARMSS_Root); 2937 QEMU_BUILD_BUG_ON(ARMMMUIdx_Phys_Realm != ARMMMUIdx_Phys_S + ARMSS_Realm); 2938 2939 return ARMMMUIdx_Phys_S + space; 2940 } 2941 2942 static inline ARMSecuritySpace arm_phys_to_space(ARMMMUIdx idx) 2943 { 2944 assert(idx >= ARMMMUIdx_Phys_S && idx <= ARMMMUIdx_Phys_Realm); 2945 return idx - ARMMMUIdx_Phys_S; 2946 } 2947 2948 static inline bool arm_v7m_csselr_razwi(ARMCPU *cpu) 2949 { 2950 /* If all the CLIDR.Ctypem bits are 0 there are no caches, and 2951 * CSSELR is RAZ/WI. 2952 */ 2953 return (cpu->clidr & R_V7M_CLIDR_CTYPE_ALL_MASK) != 0; 2954 } 2955 2956 static inline bool arm_sctlr_b(CPUARMState *env) 2957 { 2958 return 2959 /* We need not implement SCTLR.ITD in user-mode emulation, so 2960 * let linux-user ignore the fact that it conflicts with SCTLR_B. 2961 * This lets people run BE32 binaries with "-cpu any". 2962 */ 2963 #ifndef CONFIG_USER_ONLY 2964 !arm_feature(env, ARM_FEATURE_V7) && 2965 #endif 2966 (env->cp15.sctlr_el[1] & SCTLR_B) != 0; 2967 } 2968 2969 uint64_t arm_sctlr(CPUARMState *env, int el); 2970 2971 /* 2972 * We have more than 32-bits worth of state per TB, so we split the data 2973 * between tb->flags and tb->cs_base, which is otherwise unused for ARM. 2974 * We collect these two parts in CPUARMTBFlags where they are named 2975 * flags and flags2 respectively. 2976 * 2977 * The flags that are shared between all execution modes, TBFLAG_ANY, 2978 * are stored in flags. The flags that are specific to a given mode 2979 * are stores in flags2. Since cs_base is sized on the configured 2980 * address size, flags2 always has 64-bits for A64, and a minimum of 2981 * 32-bits for A32 and M32. 2982 * 2983 * The bits for 32-bit A-profile and M-profile partially overlap: 2984 * 2985 * 31 23 11 10 0 2986 * +-------------+----------+----------------+ 2987 * | | | TBFLAG_A32 | 2988 * | TBFLAG_AM32 | +-----+----------+ 2989 * | | |TBFLAG_M32| 2990 * +-------------+----------------+----------+ 2991 * 31 23 6 5 0 2992 * 2993 * Unless otherwise noted, these bits are cached in env->hflags. 2994 */ 2995 FIELD(TBFLAG_ANY, AARCH64_STATE, 0, 1) 2996 FIELD(TBFLAG_ANY, SS_ACTIVE, 1, 1) 2997 FIELD(TBFLAG_ANY, PSTATE__SS, 2, 1) /* Not cached. */ 2998 FIELD(TBFLAG_ANY, BE_DATA, 3, 1) 2999 FIELD(TBFLAG_ANY, MMUIDX, 4, 4) 3000 /* Target EL if we take a floating-point-disabled exception */ 3001 FIELD(TBFLAG_ANY, FPEXC_EL, 8, 2) 3002 /* Memory operations require alignment: SCTLR_ELx.A or CCR.UNALIGN_TRP */ 3003 FIELD(TBFLAG_ANY, ALIGN_MEM, 10, 1) 3004 FIELD(TBFLAG_ANY, PSTATE__IL, 11, 1) 3005 FIELD(TBFLAG_ANY, FGT_ACTIVE, 12, 1) 3006 FIELD(TBFLAG_ANY, FGT_SVC, 13, 1) 3007 3008 /* 3009 * Bit usage when in AArch32 state, both A- and M-profile. 3010 */ 3011 FIELD(TBFLAG_AM32, CONDEXEC, 24, 8) /* Not cached. */ 3012 FIELD(TBFLAG_AM32, THUMB, 23, 1) /* Not cached. */ 3013 3014 /* 3015 * Bit usage when in AArch32 state, for A-profile only. 3016 */ 3017 FIELD(TBFLAG_A32, VECLEN, 0, 3) /* Not cached. */ 3018 FIELD(TBFLAG_A32, VECSTRIDE, 3, 2) /* Not cached. */ 3019 /* 3020 * We store the bottom two bits of the CPAR as TB flags and handle 3021 * checks on the other bits at runtime. This shares the same bits as 3022 * VECSTRIDE, which is OK as no XScale CPU has VFP. 3023 * Not cached, because VECLEN+VECSTRIDE are not cached. 3024 */ 3025 FIELD(TBFLAG_A32, XSCALE_CPAR, 5, 2) 3026 FIELD(TBFLAG_A32, VFPEN, 7, 1) /* Partially cached, minus FPEXC. */ 3027 FIELD(TBFLAG_A32, SCTLR__B, 8, 1) /* Cannot overlap with SCTLR_B */ 3028 FIELD(TBFLAG_A32, HSTR_ACTIVE, 9, 1) 3029 /* 3030 * Indicates whether cp register reads and writes by guest code should access 3031 * the secure or nonsecure bank of banked registers; note that this is not 3032 * the same thing as the current security state of the processor! 3033 */ 3034 FIELD(TBFLAG_A32, NS, 10, 1) 3035 /* 3036 * Indicates that SME Streaming mode is active, and SMCR_ELx.FA64 is not. 3037 * This requires an SME trap from AArch32 mode when using NEON. 3038 */ 3039 FIELD(TBFLAG_A32, SME_TRAP_NONSTREAMING, 11, 1) 3040 3041 /* 3042 * Bit usage when in AArch32 state, for M-profile only. 3043 */ 3044 /* Handler (ie not Thread) mode */ 3045 FIELD(TBFLAG_M32, HANDLER, 0, 1) 3046 /* Whether we should generate stack-limit checks */ 3047 FIELD(TBFLAG_M32, STACKCHECK, 1, 1) 3048 /* Set if FPCCR.LSPACT is set */ 3049 FIELD(TBFLAG_M32, LSPACT, 2, 1) /* Not cached. */ 3050 /* Set if we must create a new FP context */ 3051 FIELD(TBFLAG_M32, NEW_FP_CTXT_NEEDED, 3, 1) /* Not cached. */ 3052 /* Set if FPCCR.S does not match current security state */ 3053 FIELD(TBFLAG_M32, FPCCR_S_WRONG, 4, 1) /* Not cached. */ 3054 /* Set if MVE insns are definitely not predicated by VPR or LTPSIZE */ 3055 FIELD(TBFLAG_M32, MVE_NO_PRED, 5, 1) /* Not cached. */ 3056 /* Set if in secure mode */ 3057 FIELD(TBFLAG_M32, SECURE, 6, 1) 3058 3059 /* 3060 * Bit usage when in AArch64 state 3061 */ 3062 FIELD(TBFLAG_A64, TBII, 0, 2) 3063 FIELD(TBFLAG_A64, SVEEXC_EL, 2, 2) 3064 /* The current vector length, either NVL or SVL. */ 3065 FIELD(TBFLAG_A64, VL, 4, 4) 3066 FIELD(TBFLAG_A64, PAUTH_ACTIVE, 8, 1) 3067 FIELD(TBFLAG_A64, BT, 9, 1) 3068 FIELD(TBFLAG_A64, BTYPE, 10, 2) /* Not cached. */ 3069 FIELD(TBFLAG_A64, TBID, 12, 2) 3070 FIELD(TBFLAG_A64, UNPRIV, 14, 1) 3071 FIELD(TBFLAG_A64, ATA, 15, 1) 3072 FIELD(TBFLAG_A64, TCMA, 16, 2) 3073 FIELD(TBFLAG_A64, MTE_ACTIVE, 18, 1) 3074 FIELD(TBFLAG_A64, MTE0_ACTIVE, 19, 1) 3075 FIELD(TBFLAG_A64, SMEEXC_EL, 20, 2) 3076 FIELD(TBFLAG_A64, PSTATE_SM, 22, 1) 3077 FIELD(TBFLAG_A64, PSTATE_ZA, 23, 1) 3078 FIELD(TBFLAG_A64, SVL, 24, 4) 3079 /* Indicates that SME Streaming mode is active, and SMCR_ELx.FA64 is not. */ 3080 FIELD(TBFLAG_A64, SME_TRAP_NONSTREAMING, 28, 1) 3081 FIELD(TBFLAG_A64, TRAP_ERET, 29, 1) 3082 FIELD(TBFLAG_A64, NAA, 30, 1) 3083 FIELD(TBFLAG_A64, ATA0, 31, 1) 3084 FIELD(TBFLAG_A64, NV, 32, 1) 3085 FIELD(TBFLAG_A64, NV1, 33, 1) 3086 FIELD(TBFLAG_A64, NV2, 34, 1) 3087 /* Set if FEAT_NV2 RAM accesses use the EL2&0 translation regime */ 3088 FIELD(TBFLAG_A64, NV2_MEM_E20, 35, 1) 3089 /* Set if FEAT_NV2 RAM accesses are big-endian */ 3090 FIELD(TBFLAG_A64, NV2_MEM_BE, 36, 1) 3091 FIELD(TBFLAG_A64, AH, 37, 1) /* FPCR.AH */ 3092 FIELD(TBFLAG_A64, NEP, 38, 1) /* FPCR.NEP */ 3093 3094 /* 3095 * Helpers for using the above. Note that only the A64 accessors use 3096 * FIELD_DP64() and FIELD_EX64(), because in the other cases the flags 3097 * word either is or might be 32 bits only. 3098 */ 3099 #define DP_TBFLAG_ANY(DST, WHICH, VAL) \ 3100 (DST.flags = FIELD_DP32(DST.flags, TBFLAG_ANY, WHICH, VAL)) 3101 #define DP_TBFLAG_A64(DST, WHICH, VAL) \ 3102 (DST.flags2 = FIELD_DP64(DST.flags2, TBFLAG_A64, WHICH, VAL)) 3103 #define DP_TBFLAG_A32(DST, WHICH, VAL) \ 3104 (DST.flags2 = FIELD_DP32(DST.flags2, TBFLAG_A32, WHICH, VAL)) 3105 #define DP_TBFLAG_M32(DST, WHICH, VAL) \ 3106 (DST.flags2 = FIELD_DP32(DST.flags2, TBFLAG_M32, WHICH, VAL)) 3107 #define DP_TBFLAG_AM32(DST, WHICH, VAL) \ 3108 (DST.flags2 = FIELD_DP32(DST.flags2, TBFLAG_AM32, WHICH, VAL)) 3109 3110 #define EX_TBFLAG_ANY(IN, WHICH) FIELD_EX32(IN.flags, TBFLAG_ANY, WHICH) 3111 #define EX_TBFLAG_A64(IN, WHICH) FIELD_EX64(IN.flags2, TBFLAG_A64, WHICH) 3112 #define EX_TBFLAG_A32(IN, WHICH) FIELD_EX32(IN.flags2, TBFLAG_A32, WHICH) 3113 #define EX_TBFLAG_M32(IN, WHICH) FIELD_EX32(IN.flags2, TBFLAG_M32, WHICH) 3114 #define EX_TBFLAG_AM32(IN, WHICH) FIELD_EX32(IN.flags2, TBFLAG_AM32, WHICH) 3115 3116 /** 3117 * sve_vq 3118 * @env: the cpu context 3119 * 3120 * Return the VL cached within env->hflags, in units of quadwords. 3121 */ 3122 static inline int sve_vq(CPUARMState *env) 3123 { 3124 return EX_TBFLAG_A64(env->hflags, VL) + 1; 3125 } 3126 3127 /** 3128 * sme_vq 3129 * @env: the cpu context 3130 * 3131 * Return the SVL cached within env->hflags, in units of quadwords. 3132 */ 3133 static inline int sme_vq(CPUARMState *env) 3134 { 3135 return EX_TBFLAG_A64(env->hflags, SVL) + 1; 3136 } 3137 3138 static inline bool bswap_code(bool sctlr_b) 3139 { 3140 #ifdef CONFIG_USER_ONLY 3141 /* BE8 (SCTLR.B = 0, TARGET_BIG_ENDIAN = 1) is mixed endian. 3142 * The invalid combination SCTLR.B=1/CPSR.E=1/TARGET_BIG_ENDIAN=0 3143 * would also end up as a mixed-endian mode with BE code, LE data. 3144 */ 3145 return TARGET_BIG_ENDIAN ^ sctlr_b; 3146 #else 3147 /* All code access in ARM is little endian, and there are no loaders 3148 * doing swaps that need to be reversed 3149 */ 3150 return 0; 3151 #endif 3152 } 3153 3154 void cpu_get_tb_cpu_state(CPUARMState *env, vaddr *pc, 3155 uint64_t *cs_base, uint32_t *flags); 3156 3157 enum { 3158 QEMU_PSCI_CONDUIT_DISABLED = 0, 3159 QEMU_PSCI_CONDUIT_SMC = 1, 3160 QEMU_PSCI_CONDUIT_HVC = 2, 3161 }; 3162 3163 #ifndef CONFIG_USER_ONLY 3164 /* Return the address space index to use for a memory access */ 3165 static inline int arm_asidx_from_attrs(CPUState *cs, MemTxAttrs attrs) 3166 { 3167 return attrs.secure ? ARMASIdx_S : ARMASIdx_NS; 3168 } 3169 3170 /* Return the AddressSpace to use for a memory access 3171 * (which depends on whether the access is S or NS, and whether 3172 * the board gave us a separate AddressSpace for S accesses). 3173 */ 3174 static inline AddressSpace *arm_addressspace(CPUState *cs, MemTxAttrs attrs) 3175 { 3176 return cpu_get_address_space(cs, arm_asidx_from_attrs(cs, attrs)); 3177 } 3178 #endif 3179 3180 /** 3181 * arm_register_pre_el_change_hook: 3182 * Register a hook function which will be called immediately before this 3183 * CPU changes exception level or mode. The hook function will be 3184 * passed a pointer to the ARMCPU and the opaque data pointer passed 3185 * to this function when the hook was registered. 3186 * 3187 * Note that if a pre-change hook is called, any registered post-change hooks 3188 * are guaranteed to subsequently be called. 3189 */ 3190 void arm_register_pre_el_change_hook(ARMCPU *cpu, ARMELChangeHookFn *hook, 3191 void *opaque); 3192 /** 3193 * arm_register_el_change_hook: 3194 * Register a hook function which will be called immediately after this 3195 * CPU changes exception level or mode. The hook function will be 3196 * passed a pointer to the ARMCPU and the opaque data pointer passed 3197 * to this function when the hook was registered. 3198 * 3199 * Note that any registered hooks registered here are guaranteed to be called 3200 * if pre-change hooks have been. 3201 */ 3202 void arm_register_el_change_hook(ARMCPU *cpu, ARMELChangeHookFn *hook, void 3203 *opaque); 3204 3205 /** 3206 * arm_rebuild_hflags: 3207 * Rebuild the cached TBFLAGS for arbitrary changed processor state. 3208 */ 3209 void arm_rebuild_hflags(CPUARMState *env); 3210 3211 /** 3212 * aa32_vfp_dreg: 3213 * Return a pointer to the Dn register within env in 32-bit mode. 3214 */ 3215 static inline uint64_t *aa32_vfp_dreg(CPUARMState *env, unsigned regno) 3216 { 3217 return &env->vfp.zregs[regno >> 1].d[regno & 1]; 3218 } 3219 3220 /** 3221 * aa32_vfp_qreg: 3222 * Return a pointer to the Qn register within env in 32-bit mode. 3223 */ 3224 static inline uint64_t *aa32_vfp_qreg(CPUARMState *env, unsigned regno) 3225 { 3226 return &env->vfp.zregs[regno].d[0]; 3227 } 3228 3229 /** 3230 * aa64_vfp_qreg: 3231 * Return a pointer to the Qn register within env in 64-bit mode. 3232 */ 3233 static inline uint64_t *aa64_vfp_qreg(CPUARMState *env, unsigned regno) 3234 { 3235 return &env->vfp.zregs[regno].d[0]; 3236 } 3237 3238 /* Shared between translate-sve.c and sve_helper.c. */ 3239 extern const uint64_t pred_esz_masks[5]; 3240 3241 /* 3242 * AArch64 usage of the PAGE_TARGET_* bits for linux-user. 3243 * Note that with the Linux kernel, PROT_MTE may not be cleared by mprotect 3244 * mprotect but PROT_BTI may be cleared. C.f. the kernel's VM_ARCH_CLEAR. 3245 */ 3246 #define PAGE_BTI PAGE_TARGET_1 3247 #define PAGE_MTE PAGE_TARGET_2 3248 #define PAGE_TARGET_STICKY PAGE_MTE 3249 3250 /* We associate one allocation tag per 16 bytes, the minimum. */ 3251 #define LOG2_TAG_GRANULE 4 3252 #define TAG_GRANULE (1 << LOG2_TAG_GRANULE) 3253 3254 #ifdef CONFIG_USER_ONLY 3255 3256 #define TARGET_PAGE_DATA_SIZE (TARGET_PAGE_SIZE >> (LOG2_TAG_GRANULE + 1)) 3257 3258 #ifdef TARGET_TAGGED_ADDRESSES 3259 /** 3260 * cpu_untagged_addr: 3261 * @cs: CPU context 3262 * @x: tagged address 3263 * 3264 * Remove any address tag from @x. This is explicitly related to the 3265 * linux syscall TIF_TAGGED_ADDR setting, not TBI in general. 3266 * 3267 * There should be a better place to put this, but we need this in 3268 * include/exec/cpu_ldst.h, and not some place linux-user specific. 3269 */ 3270 static inline target_ulong cpu_untagged_addr(CPUState *cs, target_ulong x) 3271 { 3272 CPUARMState *env = cpu_env(cs); 3273 if (env->tagged_addr_enable) { 3274 /* 3275 * TBI is enabled for userspace but not kernelspace addresses. 3276 * Only clear the tag if bit 55 is clear. 3277 */ 3278 x &= sextract64(x, 0, 56); 3279 } 3280 return x; 3281 } 3282 #endif /* TARGET_TAGGED_ADDRESSES */ 3283 #endif /* CONFIG_USER_ONLY */ 3284 3285 #endif 3286