1 /* 2 * ARM virtual CPU header 3 * 4 * Copyright (c) 2003 Fabrice Bellard 5 * 6 * This library is free software; you can redistribute it and/or 7 * modify it under the terms of the GNU Lesser General Public 8 * License as published by the Free Software Foundation; either 9 * version 2 of the License, or (at your option) any later version. 10 * 11 * This library is distributed in the hope that it will be useful, 12 * but WITHOUT ANY WARRANTY; without even the implied warranty of 13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU 14 * Lesser General Public License for more details. 15 * 16 * You should have received a copy of the GNU Lesser General Public 17 * License along with this library; if not, see <http://www.gnu.org/licenses/>. 18 */ 19 20 #ifndef ARM_CPU_H 21 #define ARM_CPU_H 22 23 #include "kvm-consts.h" 24 #include "hw/registerfields.h" 25 #include "qemu-common.h" 26 #include "cpu-qom.h" 27 #include "exec/cpu-defs.h" 28 29 /* ARM processors have a weak memory model */ 30 #define TCG_GUEST_DEFAULT_MO (0) 31 32 #define EXCP_UDEF 1 /* undefined instruction */ 33 #define EXCP_SWI 2 /* software interrupt */ 34 #define EXCP_PREFETCH_ABORT 3 35 #define EXCP_DATA_ABORT 4 36 #define EXCP_IRQ 5 37 #define EXCP_FIQ 6 38 #define EXCP_BKPT 7 39 #define EXCP_EXCEPTION_EXIT 8 /* Return from v7M exception. */ 40 #define EXCP_KERNEL_TRAP 9 /* Jumped to kernel code page. */ 41 #define EXCP_HVC 11 /* HyperVisor Call */ 42 #define EXCP_HYP_TRAP 12 43 #define EXCP_SMC 13 /* Secure Monitor Call */ 44 #define EXCP_VIRQ 14 45 #define EXCP_VFIQ 15 46 #define EXCP_SEMIHOST 16 /* semihosting call */ 47 #define EXCP_NOCP 17 /* v7M NOCP UsageFault */ 48 #define EXCP_INVSTATE 18 /* v7M INVSTATE UsageFault */ 49 #define EXCP_STKOF 19 /* v8M STKOF UsageFault */ 50 #define EXCP_LAZYFP 20 /* v7M fault during lazy FP stacking */ 51 #define EXCP_LSERR 21 /* v8M LSERR SecureFault */ 52 #define EXCP_UNALIGNED 22 /* v7M UNALIGNED UsageFault */ 53 /* NB: add new EXCP_ defines to the array in arm_log_exception() too */ 54 55 #define ARMV7M_EXCP_RESET 1 56 #define ARMV7M_EXCP_NMI 2 57 #define ARMV7M_EXCP_HARD 3 58 #define ARMV7M_EXCP_MEM 4 59 #define ARMV7M_EXCP_BUS 5 60 #define ARMV7M_EXCP_USAGE 6 61 #define ARMV7M_EXCP_SECURE 7 62 #define ARMV7M_EXCP_SVC 11 63 #define ARMV7M_EXCP_DEBUG 12 64 #define ARMV7M_EXCP_PENDSV 14 65 #define ARMV7M_EXCP_SYSTICK 15 66 67 /* For M profile, some registers are banked secure vs non-secure; 68 * these are represented as a 2-element array where the first element 69 * is the non-secure copy and the second is the secure copy. 70 * When the CPU does not have implement the security extension then 71 * only the first element is used. 72 * This means that the copy for the current security state can be 73 * accessed via env->registerfield[env->v7m.secure] (whether the security 74 * extension is implemented or not). 75 */ 76 enum { 77 M_REG_NS = 0, 78 M_REG_S = 1, 79 M_REG_NUM_BANKS = 2, 80 }; 81 82 /* ARM-specific interrupt pending bits. */ 83 #define CPU_INTERRUPT_FIQ CPU_INTERRUPT_TGT_EXT_1 84 #define CPU_INTERRUPT_VIRQ CPU_INTERRUPT_TGT_EXT_2 85 #define CPU_INTERRUPT_VFIQ CPU_INTERRUPT_TGT_EXT_3 86 87 /* The usual mapping for an AArch64 system register to its AArch32 88 * counterpart is for the 32 bit world to have access to the lower 89 * half only (with writes leaving the upper half untouched). It's 90 * therefore useful to be able to pass TCG the offset of the least 91 * significant half of a uint64_t struct member. 92 */ 93 #ifdef HOST_WORDS_BIGENDIAN 94 #define offsetoflow32(S, M) (offsetof(S, M) + sizeof(uint32_t)) 95 #define offsetofhigh32(S, M) offsetof(S, M) 96 #else 97 #define offsetoflow32(S, M) offsetof(S, M) 98 #define offsetofhigh32(S, M) (offsetof(S, M) + sizeof(uint32_t)) 99 #endif 100 101 /* Meanings of the ARMCPU object's four inbound GPIO lines */ 102 #define ARM_CPU_IRQ 0 103 #define ARM_CPU_FIQ 1 104 #define ARM_CPU_VIRQ 2 105 #define ARM_CPU_VFIQ 3 106 107 /* ARM-specific extra insn start words: 108 * 1: Conditional execution bits 109 * 2: Partial exception syndrome for data aborts 110 */ 111 #define TARGET_INSN_START_EXTRA_WORDS 2 112 113 /* The 2nd extra word holding syndrome info for data aborts does not use 114 * the upper 6 bits nor the lower 14 bits. We mask and shift it down to 115 * help the sleb128 encoder do a better job. 116 * When restoring the CPU state, we shift it back up. 117 */ 118 #define ARM_INSN_START_WORD2_MASK ((1 << 26) - 1) 119 #define ARM_INSN_START_WORD2_SHIFT 14 120 121 /* We currently assume float and double are IEEE single and double 122 precision respectively. 123 Doing runtime conversions is tricky because VFP registers may contain 124 integer values (eg. as the result of a FTOSI instruction). 125 s<2n> maps to the least significant half of d<n> 126 s<2n+1> maps to the most significant half of d<n> 127 */ 128 129 /** 130 * DynamicGDBXMLInfo: 131 * @desc: Contains the XML descriptions. 132 * @num_cpregs: Number of the Coprocessor registers seen by GDB. 133 * @cpregs_keys: Array that contains the corresponding Key of 134 * a given cpreg with the same order of the cpreg in the XML description. 135 */ 136 typedef struct DynamicGDBXMLInfo { 137 char *desc; 138 int num_cpregs; 139 uint32_t *cpregs_keys; 140 } DynamicGDBXMLInfo; 141 142 /* CPU state for each instance of a generic timer (in cp15 c14) */ 143 typedef struct ARMGenericTimer { 144 uint64_t cval; /* Timer CompareValue register */ 145 uint64_t ctl; /* Timer Control register */ 146 } ARMGenericTimer; 147 148 #define GTIMER_PHYS 0 149 #define GTIMER_VIRT 1 150 #define GTIMER_HYP 2 151 #define GTIMER_SEC 3 152 #define NUM_GTIMERS 4 153 154 typedef struct { 155 uint64_t raw_tcr; 156 uint32_t mask; 157 uint32_t base_mask; 158 } TCR; 159 160 /* Define a maximum sized vector register. 161 * For 32-bit, this is a 128-bit NEON/AdvSIMD register. 162 * For 64-bit, this is a 2048-bit SVE register. 163 * 164 * Note that the mapping between S, D, and Q views of the register bank 165 * differs between AArch64 and AArch32. 166 * In AArch32: 167 * Qn = regs[n].d[1]:regs[n].d[0] 168 * Dn = regs[n / 2].d[n & 1] 169 * Sn = regs[n / 4].d[n % 4 / 2], 170 * bits 31..0 for even n, and bits 63..32 for odd n 171 * (and regs[16] to regs[31] are inaccessible) 172 * In AArch64: 173 * Zn = regs[n].d[*] 174 * Qn = regs[n].d[1]:regs[n].d[0] 175 * Dn = regs[n].d[0] 176 * Sn = regs[n].d[0] bits 31..0 177 * Hn = regs[n].d[0] bits 15..0 178 * 179 * This corresponds to the architecturally defined mapping between 180 * the two execution states, and means we do not need to explicitly 181 * map these registers when changing states. 182 * 183 * Align the data for use with TCG host vector operations. 184 */ 185 186 #ifdef TARGET_AARCH64 187 # define ARM_MAX_VQ 16 188 #else 189 # define ARM_MAX_VQ 1 190 #endif 191 192 typedef struct ARMVectorReg { 193 uint64_t d[2 * ARM_MAX_VQ] QEMU_ALIGNED(16); 194 } ARMVectorReg; 195 196 #ifdef TARGET_AARCH64 197 /* In AArch32 mode, predicate registers do not exist at all. */ 198 typedef struct ARMPredicateReg { 199 uint64_t p[2 * ARM_MAX_VQ / 8] QEMU_ALIGNED(16); 200 } ARMPredicateReg; 201 202 /* In AArch32 mode, PAC keys do not exist at all. */ 203 typedef struct ARMPACKey { 204 uint64_t lo, hi; 205 } ARMPACKey; 206 #endif 207 208 209 typedef struct CPUARMState { 210 /* Regs for current mode. */ 211 uint32_t regs[16]; 212 213 /* 32/64 switch only happens when taking and returning from 214 * exceptions so the overlap semantics are taken care of then 215 * instead of having a complicated union. 216 */ 217 /* Regs for A64 mode. */ 218 uint64_t xregs[32]; 219 uint64_t pc; 220 /* PSTATE isn't an architectural register for ARMv8. However, it is 221 * convenient for us to assemble the underlying state into a 32 bit format 222 * identical to the architectural format used for the SPSR. (This is also 223 * what the Linux kernel's 'pstate' field in signal handlers and KVM's 224 * 'pstate' register are.) Of the PSTATE bits: 225 * NZCV are kept in the split out env->CF/VF/NF/ZF, (which have the same 226 * semantics as for AArch32, as described in the comments on each field) 227 * nRW (also known as M[4]) is kept, inverted, in env->aarch64 228 * DAIF (exception masks) are kept in env->daif 229 * BTYPE is kept in env->btype 230 * all other bits are stored in their correct places in env->pstate 231 */ 232 uint32_t pstate; 233 uint32_t aarch64; /* 1 if CPU is in aarch64 state; inverse of PSTATE.nRW */ 234 235 /* Frequently accessed CPSR bits are stored separately for efficiency. 236 This contains all the other bits. Use cpsr_{read,write} to access 237 the whole CPSR. */ 238 uint32_t uncached_cpsr; 239 uint32_t spsr; 240 241 /* Banked registers. */ 242 uint64_t banked_spsr[8]; 243 uint32_t banked_r13[8]; 244 uint32_t banked_r14[8]; 245 246 /* These hold r8-r12. */ 247 uint32_t usr_regs[5]; 248 uint32_t fiq_regs[5]; 249 250 /* cpsr flag cache for faster execution */ 251 uint32_t CF; /* 0 or 1 */ 252 uint32_t VF; /* V is the bit 31. All other bits are undefined */ 253 uint32_t NF; /* N is bit 31. All other bits are undefined. */ 254 uint32_t ZF; /* Z set if zero. */ 255 uint32_t QF; /* 0 or 1 */ 256 uint32_t GE; /* cpsr[19:16] */ 257 uint32_t thumb; /* cpsr[5]. 0 = arm mode, 1 = thumb mode. */ 258 uint32_t condexec_bits; /* IT bits. cpsr[15:10,26:25]. */ 259 uint32_t btype; /* BTI branch type. spsr[11:10]. */ 260 uint64_t daif; /* exception masks, in the bits they are in PSTATE */ 261 262 uint64_t elr_el[4]; /* AArch64 exception link regs */ 263 uint64_t sp_el[4]; /* AArch64 banked stack pointers */ 264 265 /* System control coprocessor (cp15) */ 266 struct { 267 uint32_t c0_cpuid; 268 union { /* Cache size selection */ 269 struct { 270 uint64_t _unused_csselr0; 271 uint64_t csselr_ns; 272 uint64_t _unused_csselr1; 273 uint64_t csselr_s; 274 }; 275 uint64_t csselr_el[4]; 276 }; 277 union { /* System control register. */ 278 struct { 279 uint64_t _unused_sctlr; 280 uint64_t sctlr_ns; 281 uint64_t hsctlr; 282 uint64_t sctlr_s; 283 }; 284 uint64_t sctlr_el[4]; 285 }; 286 uint64_t cpacr_el1; /* Architectural feature access control register */ 287 uint64_t cptr_el[4]; /* ARMv8 feature trap registers */ 288 uint32_t c1_xscaleauxcr; /* XScale auxiliary control register. */ 289 uint64_t sder; /* Secure debug enable register. */ 290 uint32_t nsacr; /* Non-secure access control register. */ 291 union { /* MMU translation table base 0. */ 292 struct { 293 uint64_t _unused_ttbr0_0; 294 uint64_t ttbr0_ns; 295 uint64_t _unused_ttbr0_1; 296 uint64_t ttbr0_s; 297 }; 298 uint64_t ttbr0_el[4]; 299 }; 300 union { /* MMU translation table base 1. */ 301 struct { 302 uint64_t _unused_ttbr1_0; 303 uint64_t ttbr1_ns; 304 uint64_t _unused_ttbr1_1; 305 uint64_t ttbr1_s; 306 }; 307 uint64_t ttbr1_el[4]; 308 }; 309 uint64_t vttbr_el2; /* Virtualization Translation Table Base. */ 310 /* MMU translation table base control. */ 311 TCR tcr_el[4]; 312 TCR vtcr_el2; /* Virtualization Translation Control. */ 313 uint32_t c2_data; /* MPU data cacheable bits. */ 314 uint32_t c2_insn; /* MPU instruction cacheable bits. */ 315 union { /* MMU domain access control register 316 * MPU write buffer control. 317 */ 318 struct { 319 uint64_t dacr_ns; 320 uint64_t dacr_s; 321 }; 322 struct { 323 uint64_t dacr32_el2; 324 }; 325 }; 326 uint32_t pmsav5_data_ap; /* PMSAv5 MPU data access permissions */ 327 uint32_t pmsav5_insn_ap; /* PMSAv5 MPU insn access permissions */ 328 uint64_t hcr_el2; /* Hypervisor configuration register */ 329 uint64_t scr_el3; /* Secure configuration register. */ 330 union { /* Fault status registers. */ 331 struct { 332 uint64_t ifsr_ns; 333 uint64_t ifsr_s; 334 }; 335 struct { 336 uint64_t ifsr32_el2; 337 }; 338 }; 339 union { 340 struct { 341 uint64_t _unused_dfsr; 342 uint64_t dfsr_ns; 343 uint64_t hsr; 344 uint64_t dfsr_s; 345 }; 346 uint64_t esr_el[4]; 347 }; 348 uint32_t c6_region[8]; /* MPU base/size registers. */ 349 union { /* Fault address registers. */ 350 struct { 351 uint64_t _unused_far0; 352 #ifdef HOST_WORDS_BIGENDIAN 353 uint32_t ifar_ns; 354 uint32_t dfar_ns; 355 uint32_t ifar_s; 356 uint32_t dfar_s; 357 #else 358 uint32_t dfar_ns; 359 uint32_t ifar_ns; 360 uint32_t dfar_s; 361 uint32_t ifar_s; 362 #endif 363 uint64_t _unused_far3; 364 }; 365 uint64_t far_el[4]; 366 }; 367 uint64_t hpfar_el2; 368 uint64_t hstr_el2; 369 union { /* Translation result. */ 370 struct { 371 uint64_t _unused_par_0; 372 uint64_t par_ns; 373 uint64_t _unused_par_1; 374 uint64_t par_s; 375 }; 376 uint64_t par_el[4]; 377 }; 378 379 uint32_t c9_insn; /* Cache lockdown registers. */ 380 uint32_t c9_data; 381 uint64_t c9_pmcr; /* performance monitor control register */ 382 uint64_t c9_pmcnten; /* perf monitor counter enables */ 383 uint64_t c9_pmovsr; /* perf monitor overflow status */ 384 uint64_t c9_pmuserenr; /* perf monitor user enable */ 385 uint64_t c9_pmselr; /* perf monitor counter selection register */ 386 uint64_t c9_pminten; /* perf monitor interrupt enables */ 387 union { /* Memory attribute redirection */ 388 struct { 389 #ifdef HOST_WORDS_BIGENDIAN 390 uint64_t _unused_mair_0; 391 uint32_t mair1_ns; 392 uint32_t mair0_ns; 393 uint64_t _unused_mair_1; 394 uint32_t mair1_s; 395 uint32_t mair0_s; 396 #else 397 uint64_t _unused_mair_0; 398 uint32_t mair0_ns; 399 uint32_t mair1_ns; 400 uint64_t _unused_mair_1; 401 uint32_t mair0_s; 402 uint32_t mair1_s; 403 #endif 404 }; 405 uint64_t mair_el[4]; 406 }; 407 union { /* vector base address register */ 408 struct { 409 uint64_t _unused_vbar; 410 uint64_t vbar_ns; 411 uint64_t hvbar; 412 uint64_t vbar_s; 413 }; 414 uint64_t vbar_el[4]; 415 }; 416 uint32_t mvbar; /* (monitor) vector base address register */ 417 struct { /* FCSE PID. */ 418 uint32_t fcseidr_ns; 419 uint32_t fcseidr_s; 420 }; 421 union { /* Context ID. */ 422 struct { 423 uint64_t _unused_contextidr_0; 424 uint64_t contextidr_ns; 425 uint64_t _unused_contextidr_1; 426 uint64_t contextidr_s; 427 }; 428 uint64_t contextidr_el[4]; 429 }; 430 union { /* User RW Thread register. */ 431 struct { 432 uint64_t tpidrurw_ns; 433 uint64_t tpidrprw_ns; 434 uint64_t htpidr; 435 uint64_t _tpidr_el3; 436 }; 437 uint64_t tpidr_el[4]; 438 }; 439 /* The secure banks of these registers don't map anywhere */ 440 uint64_t tpidrurw_s; 441 uint64_t tpidrprw_s; 442 uint64_t tpidruro_s; 443 444 union { /* User RO Thread register. */ 445 uint64_t tpidruro_ns; 446 uint64_t tpidrro_el[1]; 447 }; 448 uint64_t c14_cntfrq; /* Counter Frequency register */ 449 uint64_t c14_cntkctl; /* Timer Control register */ 450 uint32_t cnthctl_el2; /* Counter/Timer Hyp Control register */ 451 uint64_t cntvoff_el2; /* Counter Virtual Offset register */ 452 ARMGenericTimer c14_timer[NUM_GTIMERS]; 453 uint32_t c15_cpar; /* XScale Coprocessor Access Register */ 454 uint32_t c15_ticonfig; /* TI925T configuration byte. */ 455 uint32_t c15_i_max; /* Maximum D-cache dirty line index. */ 456 uint32_t c15_i_min; /* Minimum D-cache dirty line index. */ 457 uint32_t c15_threadid; /* TI debugger thread-ID. */ 458 uint32_t c15_config_base_address; /* SCU base address. */ 459 uint32_t c15_diagnostic; /* diagnostic register */ 460 uint32_t c15_power_diagnostic; 461 uint32_t c15_power_control; /* power control */ 462 uint64_t dbgbvr[16]; /* breakpoint value registers */ 463 uint64_t dbgbcr[16]; /* breakpoint control registers */ 464 uint64_t dbgwvr[16]; /* watchpoint value registers */ 465 uint64_t dbgwcr[16]; /* watchpoint control registers */ 466 uint64_t mdscr_el1; 467 uint64_t oslsr_el1; /* OS Lock Status */ 468 uint64_t mdcr_el2; 469 uint64_t mdcr_el3; 470 /* Stores the architectural value of the counter *the last time it was 471 * updated* by pmccntr_op_start. Accesses should always be surrounded 472 * by pmccntr_op_start/pmccntr_op_finish to guarantee the latest 473 * architecturally-correct value is being read/set. 474 */ 475 uint64_t c15_ccnt; 476 /* Stores the delta between the architectural value and the underlying 477 * cycle count during normal operation. It is used to update c15_ccnt 478 * to be the correct architectural value before accesses. During 479 * accesses, c15_ccnt_delta contains the underlying count being used 480 * for the access, after which it reverts to the delta value in 481 * pmccntr_op_finish. 482 */ 483 uint64_t c15_ccnt_delta; 484 uint64_t c14_pmevcntr[31]; 485 uint64_t c14_pmevcntr_delta[31]; 486 uint64_t c14_pmevtyper[31]; 487 uint64_t pmccfiltr_el0; /* Performance Monitor Filter Register */ 488 uint64_t vpidr_el2; /* Virtualization Processor ID Register */ 489 uint64_t vmpidr_el2; /* Virtualization Multiprocessor ID Register */ 490 } cp15; 491 492 struct { 493 /* M profile has up to 4 stack pointers: 494 * a Main Stack Pointer and a Process Stack Pointer for each 495 * of the Secure and Non-Secure states. (If the CPU doesn't support 496 * the security extension then it has only two SPs.) 497 * In QEMU we always store the currently active SP in regs[13], 498 * and the non-active SP for the current security state in 499 * v7m.other_sp. The stack pointers for the inactive security state 500 * are stored in other_ss_msp and other_ss_psp. 501 * switch_v7m_security_state() is responsible for rearranging them 502 * when we change security state. 503 */ 504 uint32_t other_sp; 505 uint32_t other_ss_msp; 506 uint32_t other_ss_psp; 507 uint32_t vecbase[M_REG_NUM_BANKS]; 508 uint32_t basepri[M_REG_NUM_BANKS]; 509 uint32_t control[M_REG_NUM_BANKS]; 510 uint32_t ccr[M_REG_NUM_BANKS]; /* Configuration and Control */ 511 uint32_t cfsr[M_REG_NUM_BANKS]; /* Configurable Fault Status */ 512 uint32_t hfsr; /* HardFault Status */ 513 uint32_t dfsr; /* Debug Fault Status Register */ 514 uint32_t sfsr; /* Secure Fault Status Register */ 515 uint32_t mmfar[M_REG_NUM_BANKS]; /* MemManage Fault Address */ 516 uint32_t bfar; /* BusFault Address */ 517 uint32_t sfar; /* Secure Fault Address Register */ 518 unsigned mpu_ctrl[M_REG_NUM_BANKS]; /* MPU_CTRL */ 519 int exception; 520 uint32_t primask[M_REG_NUM_BANKS]; 521 uint32_t faultmask[M_REG_NUM_BANKS]; 522 uint32_t aircr; /* only holds r/w state if security extn implemented */ 523 uint32_t secure; /* Is CPU in Secure state? (not guest visible) */ 524 uint32_t csselr[M_REG_NUM_BANKS]; 525 uint32_t scr[M_REG_NUM_BANKS]; 526 uint32_t msplim[M_REG_NUM_BANKS]; 527 uint32_t psplim[M_REG_NUM_BANKS]; 528 uint32_t fpcar[M_REG_NUM_BANKS]; 529 uint32_t fpccr[M_REG_NUM_BANKS]; 530 uint32_t fpdscr[M_REG_NUM_BANKS]; 531 uint32_t cpacr[M_REG_NUM_BANKS]; 532 uint32_t nsacr; 533 } v7m; 534 535 /* Information associated with an exception about to be taken: 536 * code which raises an exception must set cs->exception_index and 537 * the relevant parts of this structure; the cpu_do_interrupt function 538 * will then set the guest-visible registers as part of the exception 539 * entry process. 540 */ 541 struct { 542 uint32_t syndrome; /* AArch64 format syndrome register */ 543 uint32_t fsr; /* AArch32 format fault status register info */ 544 uint64_t vaddress; /* virtual addr associated with exception, if any */ 545 uint32_t target_el; /* EL the exception should be targeted for */ 546 /* If we implement EL2 we will also need to store information 547 * about the intermediate physical address for stage 2 faults. 548 */ 549 } exception; 550 551 /* Information associated with an SError */ 552 struct { 553 uint8_t pending; 554 uint8_t has_esr; 555 uint64_t esr; 556 } serror; 557 558 /* State of our input IRQ/FIQ/VIRQ/VFIQ lines */ 559 uint32_t irq_line_state; 560 561 /* Thumb-2 EE state. */ 562 uint32_t teecr; 563 uint32_t teehbr; 564 565 /* VFP coprocessor state. */ 566 struct { 567 ARMVectorReg zregs[32]; 568 569 #ifdef TARGET_AARCH64 570 /* Store FFR as pregs[16] to make it easier to treat as any other. */ 571 #define FFR_PRED_NUM 16 572 ARMPredicateReg pregs[17]; 573 /* Scratch space for aa64 sve predicate temporary. */ 574 ARMPredicateReg preg_tmp; 575 #endif 576 577 /* We store these fpcsr fields separately for convenience. */ 578 uint32_t qc[4] QEMU_ALIGNED(16); 579 int vec_len; 580 int vec_stride; 581 582 uint32_t xregs[16]; 583 584 /* Scratch space for aa32 neon expansion. */ 585 uint32_t scratch[8]; 586 587 /* There are a number of distinct float control structures: 588 * 589 * fp_status: is the "normal" fp status. 590 * fp_status_fp16: used for half-precision calculations 591 * standard_fp_status : the ARM "Standard FPSCR Value" 592 * 593 * Half-precision operations are governed by a separate 594 * flush-to-zero control bit in FPSCR:FZ16. We pass a separate 595 * status structure to control this. 596 * 597 * The "Standard FPSCR", ie default-NaN, flush-to-zero, 598 * round-to-nearest and is used by any operations (generally 599 * Neon) which the architecture defines as controlled by the 600 * standard FPSCR value rather than the FPSCR. 601 * 602 * To avoid having to transfer exception bits around, we simply 603 * say that the FPSCR cumulative exception flags are the logical 604 * OR of the flags in the three fp statuses. This relies on the 605 * only thing which needs to read the exception flags being 606 * an explicit FPSCR read. 607 */ 608 float_status fp_status; 609 float_status fp_status_f16; 610 float_status standard_fp_status; 611 612 /* ZCR_EL[1-3] */ 613 uint64_t zcr_el[4]; 614 } vfp; 615 uint64_t exclusive_addr; 616 uint64_t exclusive_val; 617 uint64_t exclusive_high; 618 619 /* iwMMXt coprocessor state. */ 620 struct { 621 uint64_t regs[16]; 622 uint64_t val; 623 624 uint32_t cregs[16]; 625 } iwmmxt; 626 627 #ifdef TARGET_AARCH64 628 struct { 629 ARMPACKey apia; 630 ARMPACKey apib; 631 ARMPACKey apda; 632 ARMPACKey apdb; 633 ARMPACKey apga; 634 } keys; 635 #endif 636 637 #if defined(CONFIG_USER_ONLY) 638 /* For usermode syscall translation. */ 639 int eabi; 640 #endif 641 642 struct CPUBreakpoint *cpu_breakpoint[16]; 643 struct CPUWatchpoint *cpu_watchpoint[16]; 644 645 /* Fields up to this point are cleared by a CPU reset */ 646 struct {} end_reset_fields; 647 648 /* Fields after this point are preserved across CPU reset. */ 649 650 /* Internal CPU feature flags. */ 651 uint64_t features; 652 653 /* PMSAv7 MPU */ 654 struct { 655 uint32_t *drbar; 656 uint32_t *drsr; 657 uint32_t *dracr; 658 uint32_t rnr[M_REG_NUM_BANKS]; 659 } pmsav7; 660 661 /* PMSAv8 MPU */ 662 struct { 663 /* The PMSAv8 implementation also shares some PMSAv7 config 664 * and state: 665 * pmsav7.rnr (region number register) 666 * pmsav7_dregion (number of configured regions) 667 */ 668 uint32_t *rbar[M_REG_NUM_BANKS]; 669 uint32_t *rlar[M_REG_NUM_BANKS]; 670 uint32_t mair0[M_REG_NUM_BANKS]; 671 uint32_t mair1[M_REG_NUM_BANKS]; 672 } pmsav8; 673 674 /* v8M SAU */ 675 struct { 676 uint32_t *rbar; 677 uint32_t *rlar; 678 uint32_t rnr; 679 uint32_t ctrl; 680 } sau; 681 682 void *nvic; 683 const struct arm_boot_info *boot_info; 684 /* Store GICv3CPUState to access from this struct */ 685 void *gicv3state; 686 } CPUARMState; 687 688 /** 689 * ARMELChangeHookFn: 690 * type of a function which can be registered via arm_register_el_change_hook() 691 * to get callbacks when the CPU changes its exception level or mode. 692 */ 693 typedef void ARMELChangeHookFn(ARMCPU *cpu, void *opaque); 694 typedef struct ARMELChangeHook ARMELChangeHook; 695 struct ARMELChangeHook { 696 ARMELChangeHookFn *hook; 697 void *opaque; 698 QLIST_ENTRY(ARMELChangeHook) node; 699 }; 700 701 /* These values map onto the return values for 702 * QEMU_PSCI_0_2_FN_AFFINITY_INFO */ 703 typedef enum ARMPSCIState { 704 PSCI_ON = 0, 705 PSCI_OFF = 1, 706 PSCI_ON_PENDING = 2 707 } ARMPSCIState; 708 709 typedef struct ARMISARegisters ARMISARegisters; 710 711 /** 712 * ARMCPU: 713 * @env: #CPUARMState 714 * 715 * An ARM CPU core. 716 */ 717 struct ARMCPU { 718 /*< private >*/ 719 CPUState parent_obj; 720 /*< public >*/ 721 722 CPUNegativeOffsetState neg; 723 CPUARMState env; 724 725 /* Coprocessor information */ 726 GHashTable *cp_regs; 727 /* For marshalling (mostly coprocessor) register state between the 728 * kernel and QEMU (for KVM) and between two QEMUs (for migration), 729 * we use these arrays. 730 */ 731 /* List of register indexes managed via these arrays; (full KVM style 732 * 64 bit indexes, not CPRegInfo 32 bit indexes) 733 */ 734 uint64_t *cpreg_indexes; 735 /* Values of the registers (cpreg_indexes[i]'s value is cpreg_values[i]) */ 736 uint64_t *cpreg_values; 737 /* Length of the indexes, values, reset_values arrays */ 738 int32_t cpreg_array_len; 739 /* These are used only for migration: incoming data arrives in 740 * these fields and is sanity checked in post_load before copying 741 * to the working data structures above. 742 */ 743 uint64_t *cpreg_vmstate_indexes; 744 uint64_t *cpreg_vmstate_values; 745 int32_t cpreg_vmstate_array_len; 746 747 DynamicGDBXMLInfo dyn_xml; 748 749 /* Timers used by the generic (architected) timer */ 750 QEMUTimer *gt_timer[NUM_GTIMERS]; 751 /* 752 * Timer used by the PMU. Its state is restored after migration by 753 * pmu_op_finish() - it does not need other handling during migration 754 */ 755 QEMUTimer *pmu_timer; 756 /* GPIO outputs for generic timer */ 757 qemu_irq gt_timer_outputs[NUM_GTIMERS]; 758 /* GPIO output for GICv3 maintenance interrupt signal */ 759 qemu_irq gicv3_maintenance_interrupt; 760 /* GPIO output for the PMU interrupt */ 761 qemu_irq pmu_interrupt; 762 763 /* MemoryRegion to use for secure physical accesses */ 764 MemoryRegion *secure_memory; 765 766 /* For v8M, pointer to the IDAU interface provided by board/SoC */ 767 Object *idau; 768 769 /* 'compatible' string for this CPU for Linux device trees */ 770 const char *dtb_compatible; 771 772 /* PSCI version for this CPU 773 * Bits[31:16] = Major Version 774 * Bits[15:0] = Minor Version 775 */ 776 uint32_t psci_version; 777 778 /* Should CPU start in PSCI powered-off state? */ 779 bool start_powered_off; 780 781 /* Current power state, access guarded by BQL */ 782 ARMPSCIState power_state; 783 784 /* CPU has virtualization extension */ 785 bool has_el2; 786 /* CPU has security extension */ 787 bool has_el3; 788 /* CPU has PMU (Performance Monitor Unit) */ 789 bool has_pmu; 790 791 /* CPU has memory protection unit */ 792 bool has_mpu; 793 /* PMSAv7 MPU number of supported regions */ 794 uint32_t pmsav7_dregion; 795 /* v8M SAU number of supported regions */ 796 uint32_t sau_sregion; 797 798 /* PSCI conduit used to invoke PSCI methods 799 * 0 - disabled, 1 - smc, 2 - hvc 800 */ 801 uint32_t psci_conduit; 802 803 /* For v8M, initial value of the Secure VTOR */ 804 uint32_t init_svtor; 805 806 /* [QEMU_]KVM_ARM_TARGET_* constant for this CPU, or 807 * QEMU_KVM_ARM_TARGET_NONE if the kernel doesn't support this CPU type. 808 */ 809 uint32_t kvm_target; 810 811 /* KVM init features for this CPU */ 812 uint32_t kvm_init_features[7]; 813 814 /* Uniprocessor system with MP extensions */ 815 bool mp_is_up; 816 817 /* True if we tried kvm_arm_host_cpu_features() during CPU instance_init 818 * and the probe failed (so we need to report the error in realize) 819 */ 820 bool host_cpu_probe_failed; 821 822 /* Specify the number of cores in this CPU cluster. Used for the L2CTLR 823 * register. 824 */ 825 int32_t core_count; 826 827 /* The instance init functions for implementation-specific subclasses 828 * set these fields to specify the implementation-dependent values of 829 * various constant registers and reset values of non-constant 830 * registers. 831 * Some of these might become QOM properties eventually. 832 * Field names match the official register names as defined in the 833 * ARMv7AR ARM Architecture Reference Manual. A reset_ prefix 834 * is used for reset values of non-constant registers; no reset_ 835 * prefix means a constant register. 836 * Some of these registers are split out into a substructure that 837 * is shared with the translators to control the ISA. 838 */ 839 struct ARMISARegisters { 840 uint32_t id_isar0; 841 uint32_t id_isar1; 842 uint32_t id_isar2; 843 uint32_t id_isar3; 844 uint32_t id_isar4; 845 uint32_t id_isar5; 846 uint32_t id_isar6; 847 uint32_t mvfr0; 848 uint32_t mvfr1; 849 uint32_t mvfr2; 850 uint64_t id_aa64isar0; 851 uint64_t id_aa64isar1; 852 uint64_t id_aa64pfr0; 853 uint64_t id_aa64pfr1; 854 uint64_t id_aa64mmfr0; 855 uint64_t id_aa64mmfr1; 856 } isar; 857 uint32_t midr; 858 uint32_t revidr; 859 uint32_t reset_fpsid; 860 uint32_t ctr; 861 uint32_t reset_sctlr; 862 uint32_t id_pfr0; 863 uint32_t id_pfr1; 864 uint32_t id_dfr0; 865 uint64_t pmceid0; 866 uint64_t pmceid1; 867 uint32_t id_afr0; 868 uint32_t id_mmfr0; 869 uint32_t id_mmfr1; 870 uint32_t id_mmfr2; 871 uint32_t id_mmfr3; 872 uint32_t id_mmfr4; 873 uint64_t id_aa64dfr0; 874 uint64_t id_aa64dfr1; 875 uint64_t id_aa64afr0; 876 uint64_t id_aa64afr1; 877 uint32_t dbgdidr; 878 uint32_t clidr; 879 uint64_t mp_affinity; /* MP ID without feature bits */ 880 /* The elements of this array are the CCSIDR values for each cache, 881 * in the order L1DCache, L1ICache, L2DCache, L2ICache, etc. 882 */ 883 uint32_t ccsidr[16]; 884 uint64_t reset_cbar; 885 uint32_t reset_auxcr; 886 bool reset_hivecs; 887 /* DCZ blocksize, in log_2(words), ie low 4 bits of DCZID_EL0 */ 888 uint32_t dcz_blocksize; 889 uint64_t rvbar; 890 891 /* Configurable aspects of GIC cpu interface (which is part of the CPU) */ 892 int gic_num_lrs; /* number of list registers */ 893 int gic_vpribits; /* number of virtual priority bits */ 894 int gic_vprebits; /* number of virtual preemption bits */ 895 896 /* Whether the cfgend input is high (i.e. this CPU should reset into 897 * big-endian mode). This setting isn't used directly: instead it modifies 898 * the reset_sctlr value to have SCTLR_B or SCTLR_EE set, depending on the 899 * architecture version. 900 */ 901 bool cfgend; 902 903 QLIST_HEAD(, ARMELChangeHook) pre_el_change_hooks; 904 QLIST_HEAD(, ARMELChangeHook) el_change_hooks; 905 906 int32_t node_id; /* NUMA node this CPU belongs to */ 907 908 /* Used to synchronize KVM and QEMU in-kernel device levels */ 909 uint8_t device_irq_level; 910 911 /* Used to set the maximum vector length the cpu will support. */ 912 uint32_t sve_max_vq; 913 }; 914 915 void arm_cpu_post_init(Object *obj); 916 917 uint64_t arm_cpu_mp_affinity(int idx, uint8_t clustersz); 918 919 #ifndef CONFIG_USER_ONLY 920 extern const struct VMStateDescription vmstate_arm_cpu; 921 #endif 922 923 void arm_cpu_do_interrupt(CPUState *cpu); 924 void arm_v7m_cpu_do_interrupt(CPUState *cpu); 925 bool arm_cpu_exec_interrupt(CPUState *cpu, int int_req); 926 927 void arm_cpu_dump_state(CPUState *cs, FILE *f, int flags); 928 929 hwaddr arm_cpu_get_phys_page_attrs_debug(CPUState *cpu, vaddr addr, 930 MemTxAttrs *attrs); 931 932 int arm_cpu_gdb_read_register(CPUState *cpu, uint8_t *buf, int reg); 933 int arm_cpu_gdb_write_register(CPUState *cpu, uint8_t *buf, int reg); 934 935 /* Dynamically generates for gdb stub an XML description of the sysregs from 936 * the cp_regs hashtable. Returns the registered sysregs number. 937 */ 938 int arm_gen_dynamic_xml(CPUState *cpu); 939 940 /* Returns the dynamically generated XML for the gdb stub. 941 * Returns a pointer to the XML contents for the specified XML file or NULL 942 * if the XML name doesn't match the predefined one. 943 */ 944 const char *arm_gdb_get_dynamic_xml(CPUState *cpu, const char *xmlname); 945 946 int arm_cpu_write_elf64_note(WriteCoreDumpFunction f, CPUState *cs, 947 int cpuid, void *opaque); 948 int arm_cpu_write_elf32_note(WriteCoreDumpFunction f, CPUState *cs, 949 int cpuid, void *opaque); 950 951 #ifdef TARGET_AARCH64 952 int aarch64_cpu_gdb_read_register(CPUState *cpu, uint8_t *buf, int reg); 953 int aarch64_cpu_gdb_write_register(CPUState *cpu, uint8_t *buf, int reg); 954 void aarch64_sve_narrow_vq(CPUARMState *env, unsigned vq); 955 void aarch64_sve_change_el(CPUARMState *env, int old_el, 956 int new_el, bool el0_a64); 957 #else 958 static inline void aarch64_sve_narrow_vq(CPUARMState *env, unsigned vq) { } 959 static inline void aarch64_sve_change_el(CPUARMState *env, int o, 960 int n, bool a) 961 { } 962 #endif 963 964 target_ulong do_arm_semihosting(CPUARMState *env); 965 void aarch64_sync_32_to_64(CPUARMState *env); 966 void aarch64_sync_64_to_32(CPUARMState *env); 967 968 int fp_exception_el(CPUARMState *env, int cur_el); 969 int sve_exception_el(CPUARMState *env, int cur_el); 970 uint32_t sve_zcr_len_for_el(CPUARMState *env, int el); 971 972 static inline bool is_a64(CPUARMState *env) 973 { 974 return env->aarch64; 975 } 976 977 /* you can call this signal handler from your SIGBUS and SIGSEGV 978 signal handlers to inform the virtual CPU of exceptions. non zero 979 is returned if the signal was handled by the virtual CPU. */ 980 int cpu_arm_signal_handler(int host_signum, void *pinfo, 981 void *puc); 982 983 /** 984 * pmu_op_start/finish 985 * @env: CPUARMState 986 * 987 * Convert all PMU counters between their delta form (the typical mode when 988 * they are enabled) and the guest-visible values. These two calls must 989 * surround any action which might affect the counters. 990 */ 991 void pmu_op_start(CPUARMState *env); 992 void pmu_op_finish(CPUARMState *env); 993 994 /* 995 * Called when a PMU counter is due to overflow 996 */ 997 void arm_pmu_timer_cb(void *opaque); 998 999 /** 1000 * Functions to register as EL change hooks for PMU mode filtering 1001 */ 1002 void pmu_pre_el_change(ARMCPU *cpu, void *ignored); 1003 void pmu_post_el_change(ARMCPU *cpu, void *ignored); 1004 1005 /* 1006 * pmu_init 1007 * @cpu: ARMCPU 1008 * 1009 * Initialize the CPU's PMCEID[01]_EL0 registers and associated internal state 1010 * for the current configuration 1011 */ 1012 void pmu_init(ARMCPU *cpu); 1013 1014 /* SCTLR bit meanings. Several bits have been reused in newer 1015 * versions of the architecture; in that case we define constants 1016 * for both old and new bit meanings. Code which tests against those 1017 * bits should probably check or otherwise arrange that the CPU 1018 * is the architectural version it expects. 1019 */ 1020 #define SCTLR_M (1U << 0) 1021 #define SCTLR_A (1U << 1) 1022 #define SCTLR_C (1U << 2) 1023 #define SCTLR_W (1U << 3) /* up to v6; RAO in v7 */ 1024 #define SCTLR_nTLSMD_32 (1U << 3) /* v8.2-LSMAOC, AArch32 only */ 1025 #define SCTLR_SA (1U << 3) /* AArch64 only */ 1026 #define SCTLR_P (1U << 4) /* up to v5; RAO in v6 and v7 */ 1027 #define SCTLR_LSMAOE_32 (1U << 4) /* v8.2-LSMAOC, AArch32 only */ 1028 #define SCTLR_SA0 (1U << 4) /* v8 onward, AArch64 only */ 1029 #define SCTLR_D (1U << 5) /* up to v5; RAO in v6 */ 1030 #define SCTLR_CP15BEN (1U << 5) /* v7 onward */ 1031 #define SCTLR_L (1U << 6) /* up to v5; RAO in v6 and v7; RAZ in v8 */ 1032 #define SCTLR_nAA (1U << 6) /* when v8.4-LSE is implemented */ 1033 #define SCTLR_B (1U << 7) /* up to v6; RAZ in v7 */ 1034 #define SCTLR_ITD (1U << 7) /* v8 onward */ 1035 #define SCTLR_S (1U << 8) /* up to v6; RAZ in v7 */ 1036 #define SCTLR_SED (1U << 8) /* v8 onward */ 1037 #define SCTLR_R (1U << 9) /* up to v6; RAZ in v7 */ 1038 #define SCTLR_UMA (1U << 9) /* v8 onward, AArch64 only */ 1039 #define SCTLR_F (1U << 10) /* up to v6 */ 1040 #define SCTLR_SW (1U << 10) /* v7 */ 1041 #define SCTLR_EnRCTX (1U << 10) /* in v8.0-PredInv */ 1042 #define SCTLR_Z (1U << 11) /* in v7, RES1 in v8 */ 1043 #define SCTLR_EOS (1U << 11) /* v8.5-ExS */ 1044 #define SCTLR_I (1U << 12) 1045 #define SCTLR_V (1U << 13) /* AArch32 only */ 1046 #define SCTLR_EnDB (1U << 13) /* v8.3, AArch64 only */ 1047 #define SCTLR_RR (1U << 14) /* up to v7 */ 1048 #define SCTLR_DZE (1U << 14) /* v8 onward, AArch64 only */ 1049 #define SCTLR_L4 (1U << 15) /* up to v6; RAZ in v7 */ 1050 #define SCTLR_UCT (1U << 15) /* v8 onward, AArch64 only */ 1051 #define SCTLR_DT (1U << 16) /* up to ??, RAO in v6 and v7 */ 1052 #define SCTLR_nTWI (1U << 16) /* v8 onward */ 1053 #define SCTLR_HA (1U << 17) /* up to v7, RES0 in v8 */ 1054 #define SCTLR_BR (1U << 17) /* PMSA only */ 1055 #define SCTLR_IT (1U << 18) /* up to ??, RAO in v6 and v7 */ 1056 #define SCTLR_nTWE (1U << 18) /* v8 onward */ 1057 #define SCTLR_WXN (1U << 19) 1058 #define SCTLR_ST (1U << 20) /* up to ??, RAZ in v6 */ 1059 #define SCTLR_UWXN (1U << 20) /* v7 onward, AArch32 only */ 1060 #define SCTLR_FI (1U << 21) /* up to v7, v8 RES0 */ 1061 #define SCTLR_IESB (1U << 21) /* v8.2-IESB, AArch64 only */ 1062 #define SCTLR_U (1U << 22) /* up to v6, RAO in v7 */ 1063 #define SCTLR_EIS (1U << 22) /* v8.5-ExS */ 1064 #define SCTLR_XP (1U << 23) /* up to v6; v7 onward RAO */ 1065 #define SCTLR_SPAN (1U << 23) /* v8.1-PAN */ 1066 #define SCTLR_VE (1U << 24) /* up to v7 */ 1067 #define SCTLR_E0E (1U << 24) /* v8 onward, AArch64 only */ 1068 #define SCTLR_EE (1U << 25) 1069 #define SCTLR_L2 (1U << 26) /* up to v6, RAZ in v7 */ 1070 #define SCTLR_UCI (1U << 26) /* v8 onward, AArch64 only */ 1071 #define SCTLR_NMFI (1U << 27) /* up to v7, RAZ in v7VE and v8 */ 1072 #define SCTLR_EnDA (1U << 27) /* v8.3, AArch64 only */ 1073 #define SCTLR_TRE (1U << 28) /* AArch32 only */ 1074 #define SCTLR_nTLSMD_64 (1U << 28) /* v8.2-LSMAOC, AArch64 only */ 1075 #define SCTLR_AFE (1U << 29) /* AArch32 only */ 1076 #define SCTLR_LSMAOE_64 (1U << 29) /* v8.2-LSMAOC, AArch64 only */ 1077 #define SCTLR_TE (1U << 30) /* AArch32 only */ 1078 #define SCTLR_EnIB (1U << 30) /* v8.3, AArch64 only */ 1079 #define SCTLR_EnIA (1U << 31) /* v8.3, AArch64 only */ 1080 #define SCTLR_BT0 (1ULL << 35) /* v8.5-BTI */ 1081 #define SCTLR_BT1 (1ULL << 36) /* v8.5-BTI */ 1082 #define SCTLR_ITFSB (1ULL << 37) /* v8.5-MemTag */ 1083 #define SCTLR_TCF0 (3ULL << 38) /* v8.5-MemTag */ 1084 #define SCTLR_TCF (3ULL << 40) /* v8.5-MemTag */ 1085 #define SCTLR_ATA0 (1ULL << 42) /* v8.5-MemTag */ 1086 #define SCTLR_ATA (1ULL << 43) /* v8.5-MemTag */ 1087 #define SCTLR_DSSBS (1ULL << 44) /* v8.5 */ 1088 1089 #define CPTR_TCPAC (1U << 31) 1090 #define CPTR_TTA (1U << 20) 1091 #define CPTR_TFP (1U << 10) 1092 #define CPTR_TZ (1U << 8) /* CPTR_EL2 */ 1093 #define CPTR_EZ (1U << 8) /* CPTR_EL3 */ 1094 1095 #define MDCR_EPMAD (1U << 21) 1096 #define MDCR_EDAD (1U << 20) 1097 #define MDCR_SPME (1U << 17) /* MDCR_EL3 */ 1098 #define MDCR_HPMD (1U << 17) /* MDCR_EL2 */ 1099 #define MDCR_SDD (1U << 16) 1100 #define MDCR_SPD (3U << 14) 1101 #define MDCR_TDRA (1U << 11) 1102 #define MDCR_TDOSA (1U << 10) 1103 #define MDCR_TDA (1U << 9) 1104 #define MDCR_TDE (1U << 8) 1105 #define MDCR_HPME (1U << 7) 1106 #define MDCR_TPM (1U << 6) 1107 #define MDCR_TPMCR (1U << 5) 1108 #define MDCR_HPMN (0x1fU) 1109 1110 /* Not all of the MDCR_EL3 bits are present in the 32-bit SDCR */ 1111 #define SDCR_VALID_MASK (MDCR_EPMAD | MDCR_EDAD | MDCR_SPME | MDCR_SPD) 1112 1113 #define CPSR_M (0x1fU) 1114 #define CPSR_T (1U << 5) 1115 #define CPSR_F (1U << 6) 1116 #define CPSR_I (1U << 7) 1117 #define CPSR_A (1U << 8) 1118 #define CPSR_E (1U << 9) 1119 #define CPSR_IT_2_7 (0xfc00U) 1120 #define CPSR_GE (0xfU << 16) 1121 #define CPSR_IL (1U << 20) 1122 /* Note that the RESERVED bits include bit 21, which is PSTATE_SS in 1123 * an AArch64 SPSR but RES0 in AArch32 SPSR and CPSR. In QEMU we use 1124 * env->uncached_cpsr bit 21 to store PSTATE.SS when executing in AArch32, 1125 * where it is live state but not accessible to the AArch32 code. 1126 */ 1127 #define CPSR_RESERVED (0x7U << 21) 1128 #define CPSR_J (1U << 24) 1129 #define CPSR_IT_0_1 (3U << 25) 1130 #define CPSR_Q (1U << 27) 1131 #define CPSR_V (1U << 28) 1132 #define CPSR_C (1U << 29) 1133 #define CPSR_Z (1U << 30) 1134 #define CPSR_N (1U << 31) 1135 #define CPSR_NZCV (CPSR_N | CPSR_Z | CPSR_C | CPSR_V) 1136 #define CPSR_AIF (CPSR_A | CPSR_I | CPSR_F) 1137 1138 #define CPSR_IT (CPSR_IT_0_1 | CPSR_IT_2_7) 1139 #define CACHED_CPSR_BITS (CPSR_T | CPSR_AIF | CPSR_GE | CPSR_IT | CPSR_Q \ 1140 | CPSR_NZCV) 1141 /* Bits writable in user mode. */ 1142 #define CPSR_USER (CPSR_NZCV | CPSR_Q | CPSR_GE) 1143 /* Execution state bits. MRS read as zero, MSR writes ignored. */ 1144 #define CPSR_EXEC (CPSR_T | CPSR_IT | CPSR_J | CPSR_IL) 1145 /* Mask of bits which may be set by exception return copying them from SPSR */ 1146 #define CPSR_ERET_MASK (~CPSR_RESERVED) 1147 1148 /* Bit definitions for M profile XPSR. Most are the same as CPSR. */ 1149 #define XPSR_EXCP 0x1ffU 1150 #define XPSR_SPREALIGN (1U << 9) /* Only set in exception stack frames */ 1151 #define XPSR_IT_2_7 CPSR_IT_2_7 1152 #define XPSR_GE CPSR_GE 1153 #define XPSR_SFPA (1U << 20) /* Only set in exception stack frames */ 1154 #define XPSR_T (1U << 24) /* Not the same as CPSR_T ! */ 1155 #define XPSR_IT_0_1 CPSR_IT_0_1 1156 #define XPSR_Q CPSR_Q 1157 #define XPSR_V CPSR_V 1158 #define XPSR_C CPSR_C 1159 #define XPSR_Z CPSR_Z 1160 #define XPSR_N CPSR_N 1161 #define XPSR_NZCV CPSR_NZCV 1162 #define XPSR_IT CPSR_IT 1163 1164 #define TTBCR_N (7U << 0) /* TTBCR.EAE==0 */ 1165 #define TTBCR_T0SZ (7U << 0) /* TTBCR.EAE==1 */ 1166 #define TTBCR_PD0 (1U << 4) 1167 #define TTBCR_PD1 (1U << 5) 1168 #define TTBCR_EPD0 (1U << 7) 1169 #define TTBCR_IRGN0 (3U << 8) 1170 #define TTBCR_ORGN0 (3U << 10) 1171 #define TTBCR_SH0 (3U << 12) 1172 #define TTBCR_T1SZ (3U << 16) 1173 #define TTBCR_A1 (1U << 22) 1174 #define TTBCR_EPD1 (1U << 23) 1175 #define TTBCR_IRGN1 (3U << 24) 1176 #define TTBCR_ORGN1 (3U << 26) 1177 #define TTBCR_SH1 (1U << 28) 1178 #define TTBCR_EAE (1U << 31) 1179 1180 /* Bit definitions for ARMv8 SPSR (PSTATE) format. 1181 * Only these are valid when in AArch64 mode; in 1182 * AArch32 mode SPSRs are basically CPSR-format. 1183 */ 1184 #define PSTATE_SP (1U) 1185 #define PSTATE_M (0xFU) 1186 #define PSTATE_nRW (1U << 4) 1187 #define PSTATE_F (1U << 6) 1188 #define PSTATE_I (1U << 7) 1189 #define PSTATE_A (1U << 8) 1190 #define PSTATE_D (1U << 9) 1191 #define PSTATE_BTYPE (3U << 10) 1192 #define PSTATE_IL (1U << 20) 1193 #define PSTATE_SS (1U << 21) 1194 #define PSTATE_V (1U << 28) 1195 #define PSTATE_C (1U << 29) 1196 #define PSTATE_Z (1U << 30) 1197 #define PSTATE_N (1U << 31) 1198 #define PSTATE_NZCV (PSTATE_N | PSTATE_Z | PSTATE_C | PSTATE_V) 1199 #define PSTATE_DAIF (PSTATE_D | PSTATE_A | PSTATE_I | PSTATE_F) 1200 #define CACHED_PSTATE_BITS (PSTATE_NZCV | PSTATE_DAIF | PSTATE_BTYPE) 1201 /* Mode values for AArch64 */ 1202 #define PSTATE_MODE_EL3h 13 1203 #define PSTATE_MODE_EL3t 12 1204 #define PSTATE_MODE_EL2h 9 1205 #define PSTATE_MODE_EL2t 8 1206 #define PSTATE_MODE_EL1h 5 1207 #define PSTATE_MODE_EL1t 4 1208 #define PSTATE_MODE_EL0t 0 1209 1210 /* Write a new value to v7m.exception, thus transitioning into or out 1211 * of Handler mode; this may result in a change of active stack pointer. 1212 */ 1213 void write_v7m_exception(CPUARMState *env, uint32_t new_exc); 1214 1215 /* Map EL and handler into a PSTATE_MODE. */ 1216 static inline unsigned int aarch64_pstate_mode(unsigned int el, bool handler) 1217 { 1218 return (el << 2) | handler; 1219 } 1220 1221 /* Return the current PSTATE value. For the moment we don't support 32<->64 bit 1222 * interprocessing, so we don't attempt to sync with the cpsr state used by 1223 * the 32 bit decoder. 1224 */ 1225 static inline uint32_t pstate_read(CPUARMState *env) 1226 { 1227 int ZF; 1228 1229 ZF = (env->ZF == 0); 1230 return (env->NF & 0x80000000) | (ZF << 30) 1231 | (env->CF << 29) | ((env->VF & 0x80000000) >> 3) 1232 | env->pstate | env->daif | (env->btype << 10); 1233 } 1234 1235 static inline void pstate_write(CPUARMState *env, uint32_t val) 1236 { 1237 env->ZF = (~val) & PSTATE_Z; 1238 env->NF = val; 1239 env->CF = (val >> 29) & 1; 1240 env->VF = (val << 3) & 0x80000000; 1241 env->daif = val & PSTATE_DAIF; 1242 env->btype = (val >> 10) & 3; 1243 env->pstate = val & ~CACHED_PSTATE_BITS; 1244 } 1245 1246 /* Return the current CPSR value. */ 1247 uint32_t cpsr_read(CPUARMState *env); 1248 1249 typedef enum CPSRWriteType { 1250 CPSRWriteByInstr = 0, /* from guest MSR or CPS */ 1251 CPSRWriteExceptionReturn = 1, /* from guest exception return insn */ 1252 CPSRWriteRaw = 2, /* trust values, do not switch reg banks */ 1253 CPSRWriteByGDBStub = 3, /* from the GDB stub */ 1254 } CPSRWriteType; 1255 1256 /* Set the CPSR. Note that some bits of mask must be all-set or all-clear.*/ 1257 void cpsr_write(CPUARMState *env, uint32_t val, uint32_t mask, 1258 CPSRWriteType write_type); 1259 1260 /* Return the current xPSR value. */ 1261 static inline uint32_t xpsr_read(CPUARMState *env) 1262 { 1263 int ZF; 1264 ZF = (env->ZF == 0); 1265 return (env->NF & 0x80000000) | (ZF << 30) 1266 | (env->CF << 29) | ((env->VF & 0x80000000) >> 3) | (env->QF << 27) 1267 | (env->thumb << 24) | ((env->condexec_bits & 3) << 25) 1268 | ((env->condexec_bits & 0xfc) << 8) 1269 | (env->GE << 16) 1270 | env->v7m.exception; 1271 } 1272 1273 /* Set the xPSR. Note that some bits of mask must be all-set or all-clear. */ 1274 static inline void xpsr_write(CPUARMState *env, uint32_t val, uint32_t mask) 1275 { 1276 if (mask & XPSR_NZCV) { 1277 env->ZF = (~val) & XPSR_Z; 1278 env->NF = val; 1279 env->CF = (val >> 29) & 1; 1280 env->VF = (val << 3) & 0x80000000; 1281 } 1282 if (mask & XPSR_Q) { 1283 env->QF = ((val & XPSR_Q) != 0); 1284 } 1285 if (mask & XPSR_GE) { 1286 env->GE = (val & XPSR_GE) >> 16; 1287 } 1288 if (mask & XPSR_T) { 1289 env->thumb = ((val & XPSR_T) != 0); 1290 } 1291 if (mask & XPSR_IT_0_1) { 1292 env->condexec_bits &= ~3; 1293 env->condexec_bits |= (val >> 25) & 3; 1294 } 1295 if (mask & XPSR_IT_2_7) { 1296 env->condexec_bits &= 3; 1297 env->condexec_bits |= (val >> 8) & 0xfc; 1298 } 1299 if (mask & XPSR_EXCP) { 1300 /* Note that this only happens on exception exit */ 1301 write_v7m_exception(env, val & XPSR_EXCP); 1302 } 1303 } 1304 1305 #define HCR_VM (1ULL << 0) 1306 #define HCR_SWIO (1ULL << 1) 1307 #define HCR_PTW (1ULL << 2) 1308 #define HCR_FMO (1ULL << 3) 1309 #define HCR_IMO (1ULL << 4) 1310 #define HCR_AMO (1ULL << 5) 1311 #define HCR_VF (1ULL << 6) 1312 #define HCR_VI (1ULL << 7) 1313 #define HCR_VSE (1ULL << 8) 1314 #define HCR_FB (1ULL << 9) 1315 #define HCR_BSU_MASK (3ULL << 10) 1316 #define HCR_DC (1ULL << 12) 1317 #define HCR_TWI (1ULL << 13) 1318 #define HCR_TWE (1ULL << 14) 1319 #define HCR_TID0 (1ULL << 15) 1320 #define HCR_TID1 (1ULL << 16) 1321 #define HCR_TID2 (1ULL << 17) 1322 #define HCR_TID3 (1ULL << 18) 1323 #define HCR_TSC (1ULL << 19) 1324 #define HCR_TIDCP (1ULL << 20) 1325 #define HCR_TACR (1ULL << 21) 1326 #define HCR_TSW (1ULL << 22) 1327 #define HCR_TPCP (1ULL << 23) 1328 #define HCR_TPU (1ULL << 24) 1329 #define HCR_TTLB (1ULL << 25) 1330 #define HCR_TVM (1ULL << 26) 1331 #define HCR_TGE (1ULL << 27) 1332 #define HCR_TDZ (1ULL << 28) 1333 #define HCR_HCD (1ULL << 29) 1334 #define HCR_TRVM (1ULL << 30) 1335 #define HCR_RW (1ULL << 31) 1336 #define HCR_CD (1ULL << 32) 1337 #define HCR_ID (1ULL << 33) 1338 #define HCR_E2H (1ULL << 34) 1339 #define HCR_TLOR (1ULL << 35) 1340 #define HCR_TERR (1ULL << 36) 1341 #define HCR_TEA (1ULL << 37) 1342 #define HCR_MIOCNCE (1ULL << 38) 1343 #define HCR_APK (1ULL << 40) 1344 #define HCR_API (1ULL << 41) 1345 #define HCR_NV (1ULL << 42) 1346 #define HCR_NV1 (1ULL << 43) 1347 #define HCR_AT (1ULL << 44) 1348 #define HCR_NV2 (1ULL << 45) 1349 #define HCR_FWB (1ULL << 46) 1350 #define HCR_FIEN (1ULL << 47) 1351 #define HCR_TID4 (1ULL << 49) 1352 #define HCR_TICAB (1ULL << 50) 1353 #define HCR_TOCU (1ULL << 52) 1354 #define HCR_TTLBIS (1ULL << 54) 1355 #define HCR_TTLBOS (1ULL << 55) 1356 #define HCR_ATA (1ULL << 56) 1357 #define HCR_DCT (1ULL << 57) 1358 1359 /* 1360 * When we actually implement ARMv8.1-VHE we should add HCR_E2H to 1361 * HCR_MASK and then clear it again if the feature bit is not set in 1362 * hcr_write(). 1363 */ 1364 #define HCR_MASK ((1ULL << 34) - 1) 1365 1366 #define SCR_NS (1U << 0) 1367 #define SCR_IRQ (1U << 1) 1368 #define SCR_FIQ (1U << 2) 1369 #define SCR_EA (1U << 3) 1370 #define SCR_FW (1U << 4) 1371 #define SCR_AW (1U << 5) 1372 #define SCR_NET (1U << 6) 1373 #define SCR_SMD (1U << 7) 1374 #define SCR_HCE (1U << 8) 1375 #define SCR_SIF (1U << 9) 1376 #define SCR_RW (1U << 10) 1377 #define SCR_ST (1U << 11) 1378 #define SCR_TWI (1U << 12) 1379 #define SCR_TWE (1U << 13) 1380 #define SCR_TLOR (1U << 14) 1381 #define SCR_TERR (1U << 15) 1382 #define SCR_APK (1U << 16) 1383 #define SCR_API (1U << 17) 1384 #define SCR_EEL2 (1U << 18) 1385 #define SCR_EASE (1U << 19) 1386 #define SCR_NMEA (1U << 20) 1387 #define SCR_FIEN (1U << 21) 1388 #define SCR_ENSCXT (1U << 25) 1389 #define SCR_ATA (1U << 26) 1390 1391 /* Return the current FPSCR value. */ 1392 uint32_t vfp_get_fpscr(CPUARMState *env); 1393 void vfp_set_fpscr(CPUARMState *env, uint32_t val); 1394 1395 /* FPCR, Floating Point Control Register 1396 * FPSR, Floating Poiht Status Register 1397 * 1398 * For A64 the FPSCR is split into two logically distinct registers, 1399 * FPCR and FPSR. However since they still use non-overlapping bits 1400 * we store the underlying state in fpscr and just mask on read/write. 1401 */ 1402 #define FPSR_MASK 0xf800009f 1403 #define FPCR_MASK 0x07ff9f00 1404 1405 #define FPCR_IOE (1 << 8) /* Invalid Operation exception trap enable */ 1406 #define FPCR_DZE (1 << 9) /* Divide by Zero exception trap enable */ 1407 #define FPCR_OFE (1 << 10) /* Overflow exception trap enable */ 1408 #define FPCR_UFE (1 << 11) /* Underflow exception trap enable */ 1409 #define FPCR_IXE (1 << 12) /* Inexact exception trap enable */ 1410 #define FPCR_IDE (1 << 15) /* Input Denormal exception trap enable */ 1411 #define FPCR_FZ16 (1 << 19) /* ARMv8.2+, FP16 flush-to-zero */ 1412 #define FPCR_FZ (1 << 24) /* Flush-to-zero enable bit */ 1413 #define FPCR_DN (1 << 25) /* Default NaN enable bit */ 1414 #define FPCR_QC (1 << 27) /* Cumulative saturation bit */ 1415 1416 static inline uint32_t vfp_get_fpsr(CPUARMState *env) 1417 { 1418 return vfp_get_fpscr(env) & FPSR_MASK; 1419 } 1420 1421 static inline void vfp_set_fpsr(CPUARMState *env, uint32_t val) 1422 { 1423 uint32_t new_fpscr = (vfp_get_fpscr(env) & ~FPSR_MASK) | (val & FPSR_MASK); 1424 vfp_set_fpscr(env, new_fpscr); 1425 } 1426 1427 static inline uint32_t vfp_get_fpcr(CPUARMState *env) 1428 { 1429 return vfp_get_fpscr(env) & FPCR_MASK; 1430 } 1431 1432 static inline void vfp_set_fpcr(CPUARMState *env, uint32_t val) 1433 { 1434 uint32_t new_fpscr = (vfp_get_fpscr(env) & ~FPCR_MASK) | (val & FPCR_MASK); 1435 vfp_set_fpscr(env, new_fpscr); 1436 } 1437 1438 enum arm_cpu_mode { 1439 ARM_CPU_MODE_USR = 0x10, 1440 ARM_CPU_MODE_FIQ = 0x11, 1441 ARM_CPU_MODE_IRQ = 0x12, 1442 ARM_CPU_MODE_SVC = 0x13, 1443 ARM_CPU_MODE_MON = 0x16, 1444 ARM_CPU_MODE_ABT = 0x17, 1445 ARM_CPU_MODE_HYP = 0x1a, 1446 ARM_CPU_MODE_UND = 0x1b, 1447 ARM_CPU_MODE_SYS = 0x1f 1448 }; 1449 1450 /* VFP system registers. */ 1451 #define ARM_VFP_FPSID 0 1452 #define ARM_VFP_FPSCR 1 1453 #define ARM_VFP_MVFR2 5 1454 #define ARM_VFP_MVFR1 6 1455 #define ARM_VFP_MVFR0 7 1456 #define ARM_VFP_FPEXC 8 1457 #define ARM_VFP_FPINST 9 1458 #define ARM_VFP_FPINST2 10 1459 1460 /* iwMMXt coprocessor control registers. */ 1461 #define ARM_IWMMXT_wCID 0 1462 #define ARM_IWMMXT_wCon 1 1463 #define ARM_IWMMXT_wCSSF 2 1464 #define ARM_IWMMXT_wCASF 3 1465 #define ARM_IWMMXT_wCGR0 8 1466 #define ARM_IWMMXT_wCGR1 9 1467 #define ARM_IWMMXT_wCGR2 10 1468 #define ARM_IWMMXT_wCGR3 11 1469 1470 /* V7M CCR bits */ 1471 FIELD(V7M_CCR, NONBASETHRDENA, 0, 1) 1472 FIELD(V7M_CCR, USERSETMPEND, 1, 1) 1473 FIELD(V7M_CCR, UNALIGN_TRP, 3, 1) 1474 FIELD(V7M_CCR, DIV_0_TRP, 4, 1) 1475 FIELD(V7M_CCR, BFHFNMIGN, 8, 1) 1476 FIELD(V7M_CCR, STKALIGN, 9, 1) 1477 FIELD(V7M_CCR, STKOFHFNMIGN, 10, 1) 1478 FIELD(V7M_CCR, DC, 16, 1) 1479 FIELD(V7M_CCR, IC, 17, 1) 1480 FIELD(V7M_CCR, BP, 18, 1) 1481 1482 /* V7M SCR bits */ 1483 FIELD(V7M_SCR, SLEEPONEXIT, 1, 1) 1484 FIELD(V7M_SCR, SLEEPDEEP, 2, 1) 1485 FIELD(V7M_SCR, SLEEPDEEPS, 3, 1) 1486 FIELD(V7M_SCR, SEVONPEND, 4, 1) 1487 1488 /* V7M AIRCR bits */ 1489 FIELD(V7M_AIRCR, VECTRESET, 0, 1) 1490 FIELD(V7M_AIRCR, VECTCLRACTIVE, 1, 1) 1491 FIELD(V7M_AIRCR, SYSRESETREQ, 2, 1) 1492 FIELD(V7M_AIRCR, SYSRESETREQS, 3, 1) 1493 FIELD(V7M_AIRCR, PRIGROUP, 8, 3) 1494 FIELD(V7M_AIRCR, BFHFNMINS, 13, 1) 1495 FIELD(V7M_AIRCR, PRIS, 14, 1) 1496 FIELD(V7M_AIRCR, ENDIANNESS, 15, 1) 1497 FIELD(V7M_AIRCR, VECTKEY, 16, 16) 1498 1499 /* V7M CFSR bits for MMFSR */ 1500 FIELD(V7M_CFSR, IACCVIOL, 0, 1) 1501 FIELD(V7M_CFSR, DACCVIOL, 1, 1) 1502 FIELD(V7M_CFSR, MUNSTKERR, 3, 1) 1503 FIELD(V7M_CFSR, MSTKERR, 4, 1) 1504 FIELD(V7M_CFSR, MLSPERR, 5, 1) 1505 FIELD(V7M_CFSR, MMARVALID, 7, 1) 1506 1507 /* V7M CFSR bits for BFSR */ 1508 FIELD(V7M_CFSR, IBUSERR, 8 + 0, 1) 1509 FIELD(V7M_CFSR, PRECISERR, 8 + 1, 1) 1510 FIELD(V7M_CFSR, IMPRECISERR, 8 + 2, 1) 1511 FIELD(V7M_CFSR, UNSTKERR, 8 + 3, 1) 1512 FIELD(V7M_CFSR, STKERR, 8 + 4, 1) 1513 FIELD(V7M_CFSR, LSPERR, 8 + 5, 1) 1514 FIELD(V7M_CFSR, BFARVALID, 8 + 7, 1) 1515 1516 /* V7M CFSR bits for UFSR */ 1517 FIELD(V7M_CFSR, UNDEFINSTR, 16 + 0, 1) 1518 FIELD(V7M_CFSR, INVSTATE, 16 + 1, 1) 1519 FIELD(V7M_CFSR, INVPC, 16 + 2, 1) 1520 FIELD(V7M_CFSR, NOCP, 16 + 3, 1) 1521 FIELD(V7M_CFSR, STKOF, 16 + 4, 1) 1522 FIELD(V7M_CFSR, UNALIGNED, 16 + 8, 1) 1523 FIELD(V7M_CFSR, DIVBYZERO, 16 + 9, 1) 1524 1525 /* V7M CFSR bit masks covering all of the subregister bits */ 1526 FIELD(V7M_CFSR, MMFSR, 0, 8) 1527 FIELD(V7M_CFSR, BFSR, 8, 8) 1528 FIELD(V7M_CFSR, UFSR, 16, 16) 1529 1530 /* V7M HFSR bits */ 1531 FIELD(V7M_HFSR, VECTTBL, 1, 1) 1532 FIELD(V7M_HFSR, FORCED, 30, 1) 1533 FIELD(V7M_HFSR, DEBUGEVT, 31, 1) 1534 1535 /* V7M DFSR bits */ 1536 FIELD(V7M_DFSR, HALTED, 0, 1) 1537 FIELD(V7M_DFSR, BKPT, 1, 1) 1538 FIELD(V7M_DFSR, DWTTRAP, 2, 1) 1539 FIELD(V7M_DFSR, VCATCH, 3, 1) 1540 FIELD(V7M_DFSR, EXTERNAL, 4, 1) 1541 1542 /* V7M SFSR bits */ 1543 FIELD(V7M_SFSR, INVEP, 0, 1) 1544 FIELD(V7M_SFSR, INVIS, 1, 1) 1545 FIELD(V7M_SFSR, INVER, 2, 1) 1546 FIELD(V7M_SFSR, AUVIOL, 3, 1) 1547 FIELD(V7M_SFSR, INVTRAN, 4, 1) 1548 FIELD(V7M_SFSR, LSPERR, 5, 1) 1549 FIELD(V7M_SFSR, SFARVALID, 6, 1) 1550 FIELD(V7M_SFSR, LSERR, 7, 1) 1551 1552 /* v7M MPU_CTRL bits */ 1553 FIELD(V7M_MPU_CTRL, ENABLE, 0, 1) 1554 FIELD(V7M_MPU_CTRL, HFNMIENA, 1, 1) 1555 FIELD(V7M_MPU_CTRL, PRIVDEFENA, 2, 1) 1556 1557 /* v7M CLIDR bits */ 1558 FIELD(V7M_CLIDR, CTYPE_ALL, 0, 21) 1559 FIELD(V7M_CLIDR, LOUIS, 21, 3) 1560 FIELD(V7M_CLIDR, LOC, 24, 3) 1561 FIELD(V7M_CLIDR, LOUU, 27, 3) 1562 FIELD(V7M_CLIDR, ICB, 30, 2) 1563 1564 FIELD(V7M_CSSELR, IND, 0, 1) 1565 FIELD(V7M_CSSELR, LEVEL, 1, 3) 1566 /* We use the combination of InD and Level to index into cpu->ccsidr[]; 1567 * define a mask for this and check that it doesn't permit running off 1568 * the end of the array. 1569 */ 1570 FIELD(V7M_CSSELR, INDEX, 0, 4) 1571 1572 /* v7M FPCCR bits */ 1573 FIELD(V7M_FPCCR, LSPACT, 0, 1) 1574 FIELD(V7M_FPCCR, USER, 1, 1) 1575 FIELD(V7M_FPCCR, S, 2, 1) 1576 FIELD(V7M_FPCCR, THREAD, 3, 1) 1577 FIELD(V7M_FPCCR, HFRDY, 4, 1) 1578 FIELD(V7M_FPCCR, MMRDY, 5, 1) 1579 FIELD(V7M_FPCCR, BFRDY, 6, 1) 1580 FIELD(V7M_FPCCR, SFRDY, 7, 1) 1581 FIELD(V7M_FPCCR, MONRDY, 8, 1) 1582 FIELD(V7M_FPCCR, SPLIMVIOL, 9, 1) 1583 FIELD(V7M_FPCCR, UFRDY, 10, 1) 1584 FIELD(V7M_FPCCR, RES0, 11, 15) 1585 FIELD(V7M_FPCCR, TS, 26, 1) 1586 FIELD(V7M_FPCCR, CLRONRETS, 27, 1) 1587 FIELD(V7M_FPCCR, CLRONRET, 28, 1) 1588 FIELD(V7M_FPCCR, LSPENS, 29, 1) 1589 FIELD(V7M_FPCCR, LSPEN, 30, 1) 1590 FIELD(V7M_FPCCR, ASPEN, 31, 1) 1591 /* These bits are banked. Others are non-banked and live in the M_REG_S bank */ 1592 #define R_V7M_FPCCR_BANKED_MASK \ 1593 (R_V7M_FPCCR_LSPACT_MASK | \ 1594 R_V7M_FPCCR_USER_MASK | \ 1595 R_V7M_FPCCR_THREAD_MASK | \ 1596 R_V7M_FPCCR_MMRDY_MASK | \ 1597 R_V7M_FPCCR_SPLIMVIOL_MASK | \ 1598 R_V7M_FPCCR_UFRDY_MASK | \ 1599 R_V7M_FPCCR_ASPEN_MASK) 1600 1601 /* 1602 * System register ID fields. 1603 */ 1604 FIELD(ID_ISAR0, SWAP, 0, 4) 1605 FIELD(ID_ISAR0, BITCOUNT, 4, 4) 1606 FIELD(ID_ISAR0, BITFIELD, 8, 4) 1607 FIELD(ID_ISAR0, CMPBRANCH, 12, 4) 1608 FIELD(ID_ISAR0, COPROC, 16, 4) 1609 FIELD(ID_ISAR0, DEBUG, 20, 4) 1610 FIELD(ID_ISAR0, DIVIDE, 24, 4) 1611 1612 FIELD(ID_ISAR1, ENDIAN, 0, 4) 1613 FIELD(ID_ISAR1, EXCEPT, 4, 4) 1614 FIELD(ID_ISAR1, EXCEPT_AR, 8, 4) 1615 FIELD(ID_ISAR1, EXTEND, 12, 4) 1616 FIELD(ID_ISAR1, IFTHEN, 16, 4) 1617 FIELD(ID_ISAR1, IMMEDIATE, 20, 4) 1618 FIELD(ID_ISAR1, INTERWORK, 24, 4) 1619 FIELD(ID_ISAR1, JAZELLE, 28, 4) 1620 1621 FIELD(ID_ISAR2, LOADSTORE, 0, 4) 1622 FIELD(ID_ISAR2, MEMHINT, 4, 4) 1623 FIELD(ID_ISAR2, MULTIACCESSINT, 8, 4) 1624 FIELD(ID_ISAR2, MULT, 12, 4) 1625 FIELD(ID_ISAR2, MULTS, 16, 4) 1626 FIELD(ID_ISAR2, MULTU, 20, 4) 1627 FIELD(ID_ISAR2, PSR_AR, 24, 4) 1628 FIELD(ID_ISAR2, REVERSAL, 28, 4) 1629 1630 FIELD(ID_ISAR3, SATURATE, 0, 4) 1631 FIELD(ID_ISAR3, SIMD, 4, 4) 1632 FIELD(ID_ISAR3, SVC, 8, 4) 1633 FIELD(ID_ISAR3, SYNCHPRIM, 12, 4) 1634 FIELD(ID_ISAR3, TABBRANCH, 16, 4) 1635 FIELD(ID_ISAR3, T32COPY, 20, 4) 1636 FIELD(ID_ISAR3, TRUENOP, 24, 4) 1637 FIELD(ID_ISAR3, T32EE, 28, 4) 1638 1639 FIELD(ID_ISAR4, UNPRIV, 0, 4) 1640 FIELD(ID_ISAR4, WITHSHIFTS, 4, 4) 1641 FIELD(ID_ISAR4, WRITEBACK, 8, 4) 1642 FIELD(ID_ISAR4, SMC, 12, 4) 1643 FIELD(ID_ISAR4, BARRIER, 16, 4) 1644 FIELD(ID_ISAR4, SYNCHPRIM_FRAC, 20, 4) 1645 FIELD(ID_ISAR4, PSR_M, 24, 4) 1646 FIELD(ID_ISAR4, SWP_FRAC, 28, 4) 1647 1648 FIELD(ID_ISAR5, SEVL, 0, 4) 1649 FIELD(ID_ISAR5, AES, 4, 4) 1650 FIELD(ID_ISAR5, SHA1, 8, 4) 1651 FIELD(ID_ISAR5, SHA2, 12, 4) 1652 FIELD(ID_ISAR5, CRC32, 16, 4) 1653 FIELD(ID_ISAR5, RDM, 24, 4) 1654 FIELD(ID_ISAR5, VCMA, 28, 4) 1655 1656 FIELD(ID_ISAR6, JSCVT, 0, 4) 1657 FIELD(ID_ISAR6, DP, 4, 4) 1658 FIELD(ID_ISAR6, FHM, 8, 4) 1659 FIELD(ID_ISAR6, SB, 12, 4) 1660 FIELD(ID_ISAR6, SPECRES, 16, 4) 1661 1662 FIELD(ID_MMFR4, SPECSEI, 0, 4) 1663 FIELD(ID_MMFR4, AC2, 4, 4) 1664 FIELD(ID_MMFR4, XNX, 8, 4) 1665 FIELD(ID_MMFR4, CNP, 12, 4) 1666 FIELD(ID_MMFR4, HPDS, 16, 4) 1667 FIELD(ID_MMFR4, LSM, 20, 4) 1668 FIELD(ID_MMFR4, CCIDX, 24, 4) 1669 FIELD(ID_MMFR4, EVT, 28, 4) 1670 1671 FIELD(ID_AA64ISAR0, AES, 4, 4) 1672 FIELD(ID_AA64ISAR0, SHA1, 8, 4) 1673 FIELD(ID_AA64ISAR0, SHA2, 12, 4) 1674 FIELD(ID_AA64ISAR0, CRC32, 16, 4) 1675 FIELD(ID_AA64ISAR0, ATOMIC, 20, 4) 1676 FIELD(ID_AA64ISAR0, RDM, 28, 4) 1677 FIELD(ID_AA64ISAR0, SHA3, 32, 4) 1678 FIELD(ID_AA64ISAR0, SM3, 36, 4) 1679 FIELD(ID_AA64ISAR0, SM4, 40, 4) 1680 FIELD(ID_AA64ISAR0, DP, 44, 4) 1681 FIELD(ID_AA64ISAR0, FHM, 48, 4) 1682 FIELD(ID_AA64ISAR0, TS, 52, 4) 1683 FIELD(ID_AA64ISAR0, TLB, 56, 4) 1684 FIELD(ID_AA64ISAR0, RNDR, 60, 4) 1685 1686 FIELD(ID_AA64ISAR1, DPB, 0, 4) 1687 FIELD(ID_AA64ISAR1, APA, 4, 4) 1688 FIELD(ID_AA64ISAR1, API, 8, 4) 1689 FIELD(ID_AA64ISAR1, JSCVT, 12, 4) 1690 FIELD(ID_AA64ISAR1, FCMA, 16, 4) 1691 FIELD(ID_AA64ISAR1, LRCPC, 20, 4) 1692 FIELD(ID_AA64ISAR1, GPA, 24, 4) 1693 FIELD(ID_AA64ISAR1, GPI, 28, 4) 1694 FIELD(ID_AA64ISAR1, FRINTTS, 32, 4) 1695 FIELD(ID_AA64ISAR1, SB, 36, 4) 1696 FIELD(ID_AA64ISAR1, SPECRES, 40, 4) 1697 1698 FIELD(ID_AA64PFR0, EL0, 0, 4) 1699 FIELD(ID_AA64PFR0, EL1, 4, 4) 1700 FIELD(ID_AA64PFR0, EL2, 8, 4) 1701 FIELD(ID_AA64PFR0, EL3, 12, 4) 1702 FIELD(ID_AA64PFR0, FP, 16, 4) 1703 FIELD(ID_AA64PFR0, ADVSIMD, 20, 4) 1704 FIELD(ID_AA64PFR0, GIC, 24, 4) 1705 FIELD(ID_AA64PFR0, RAS, 28, 4) 1706 FIELD(ID_AA64PFR0, SVE, 32, 4) 1707 1708 FIELD(ID_AA64PFR1, BT, 0, 4) 1709 FIELD(ID_AA64PFR1, SBSS, 4, 4) 1710 FIELD(ID_AA64PFR1, MTE, 8, 4) 1711 FIELD(ID_AA64PFR1, RAS_FRAC, 12, 4) 1712 1713 FIELD(ID_AA64MMFR0, PARANGE, 0, 4) 1714 FIELD(ID_AA64MMFR0, ASIDBITS, 4, 4) 1715 FIELD(ID_AA64MMFR0, BIGEND, 8, 4) 1716 FIELD(ID_AA64MMFR0, SNSMEM, 12, 4) 1717 FIELD(ID_AA64MMFR0, BIGENDEL0, 16, 4) 1718 FIELD(ID_AA64MMFR0, TGRAN16, 20, 4) 1719 FIELD(ID_AA64MMFR0, TGRAN64, 24, 4) 1720 FIELD(ID_AA64MMFR0, TGRAN4, 28, 4) 1721 FIELD(ID_AA64MMFR0, TGRAN16_2, 32, 4) 1722 FIELD(ID_AA64MMFR0, TGRAN64_2, 36, 4) 1723 FIELD(ID_AA64MMFR0, TGRAN4_2, 40, 4) 1724 FIELD(ID_AA64MMFR0, EXS, 44, 4) 1725 1726 FIELD(ID_AA64MMFR1, HAFDBS, 0, 4) 1727 FIELD(ID_AA64MMFR1, VMIDBITS, 4, 4) 1728 FIELD(ID_AA64MMFR1, VH, 8, 4) 1729 FIELD(ID_AA64MMFR1, HPDS, 12, 4) 1730 FIELD(ID_AA64MMFR1, LO, 16, 4) 1731 FIELD(ID_AA64MMFR1, PAN, 20, 4) 1732 FIELD(ID_AA64MMFR1, SPECSEI, 24, 4) 1733 FIELD(ID_AA64MMFR1, XNX, 28, 4) 1734 1735 FIELD(ID_DFR0, COPDBG, 0, 4) 1736 FIELD(ID_DFR0, COPSDBG, 4, 4) 1737 FIELD(ID_DFR0, MMAPDBG, 8, 4) 1738 FIELD(ID_DFR0, COPTRC, 12, 4) 1739 FIELD(ID_DFR0, MMAPTRC, 16, 4) 1740 FIELD(ID_DFR0, MPROFDBG, 20, 4) 1741 FIELD(ID_DFR0, PERFMON, 24, 4) 1742 FIELD(ID_DFR0, TRACEFILT, 28, 4) 1743 1744 FIELD(MVFR0, SIMDREG, 0, 4) 1745 FIELD(MVFR0, FPSP, 4, 4) 1746 FIELD(MVFR0, FPDP, 8, 4) 1747 FIELD(MVFR0, FPTRAP, 12, 4) 1748 FIELD(MVFR0, FPDIVIDE, 16, 4) 1749 FIELD(MVFR0, FPSQRT, 20, 4) 1750 FIELD(MVFR0, FPSHVEC, 24, 4) 1751 FIELD(MVFR0, FPROUND, 28, 4) 1752 1753 FIELD(MVFR1, FPFTZ, 0, 4) 1754 FIELD(MVFR1, FPDNAN, 4, 4) 1755 FIELD(MVFR1, SIMDLS, 8, 4) 1756 FIELD(MVFR1, SIMDINT, 12, 4) 1757 FIELD(MVFR1, SIMDSP, 16, 4) 1758 FIELD(MVFR1, SIMDHP, 20, 4) 1759 FIELD(MVFR1, FPHP, 24, 4) 1760 FIELD(MVFR1, SIMDFMAC, 28, 4) 1761 1762 FIELD(MVFR2, SIMDMISC, 0, 4) 1763 FIELD(MVFR2, FPMISC, 4, 4) 1764 1765 QEMU_BUILD_BUG_ON(ARRAY_SIZE(((ARMCPU *)0)->ccsidr) <= R_V7M_CSSELR_INDEX_MASK); 1766 1767 /* If adding a feature bit which corresponds to a Linux ELF 1768 * HWCAP bit, remember to update the feature-bit-to-hwcap 1769 * mapping in linux-user/elfload.c:get_elf_hwcap(). 1770 */ 1771 enum arm_features { 1772 ARM_FEATURE_VFP, 1773 ARM_FEATURE_AUXCR, /* ARM1026 Auxiliary control register. */ 1774 ARM_FEATURE_XSCALE, /* Intel XScale extensions. */ 1775 ARM_FEATURE_IWMMXT, /* Intel iwMMXt extension. */ 1776 ARM_FEATURE_V6, 1777 ARM_FEATURE_V6K, 1778 ARM_FEATURE_V7, 1779 ARM_FEATURE_THUMB2, 1780 ARM_FEATURE_PMSA, /* no MMU; may have Memory Protection Unit */ 1781 ARM_FEATURE_VFP3, 1782 ARM_FEATURE_NEON, 1783 ARM_FEATURE_M, /* Microcontroller profile. */ 1784 ARM_FEATURE_OMAPCP, /* OMAP specific CP15 ops handling. */ 1785 ARM_FEATURE_THUMB2EE, 1786 ARM_FEATURE_V7MP, /* v7 Multiprocessing Extensions */ 1787 ARM_FEATURE_V7VE, /* v7 Virtualization Extensions (non-EL2 parts) */ 1788 ARM_FEATURE_V4T, 1789 ARM_FEATURE_V5, 1790 ARM_FEATURE_STRONGARM, 1791 ARM_FEATURE_VAPA, /* cp15 VA to PA lookups */ 1792 ARM_FEATURE_VFP4, /* VFPv4 (implies that NEON is v2) */ 1793 ARM_FEATURE_GENERIC_TIMER, 1794 ARM_FEATURE_MVFR, /* Media and VFP Feature Registers 0 and 1 */ 1795 ARM_FEATURE_DUMMY_C15_REGS, /* RAZ/WI all of cp15 crn=15 */ 1796 ARM_FEATURE_CACHE_TEST_CLEAN, /* 926/1026 style test-and-clean ops */ 1797 ARM_FEATURE_CACHE_DIRTY_REG, /* 1136/1176 cache dirty status register */ 1798 ARM_FEATURE_CACHE_BLOCK_OPS, /* v6 optional cache block operations */ 1799 ARM_FEATURE_MPIDR, /* has cp15 MPIDR */ 1800 ARM_FEATURE_PXN, /* has Privileged Execute Never bit */ 1801 ARM_FEATURE_LPAE, /* has Large Physical Address Extension */ 1802 ARM_FEATURE_V8, 1803 ARM_FEATURE_AARCH64, /* supports 64 bit mode */ 1804 ARM_FEATURE_CBAR, /* has cp15 CBAR */ 1805 ARM_FEATURE_CRC, /* ARMv8 CRC instructions */ 1806 ARM_FEATURE_CBAR_RO, /* has cp15 CBAR and it is read-only */ 1807 ARM_FEATURE_EL2, /* has EL2 Virtualization support */ 1808 ARM_FEATURE_EL3, /* has EL3 Secure monitor support */ 1809 ARM_FEATURE_THUMB_DSP, /* DSP insns supported in the Thumb encodings */ 1810 ARM_FEATURE_PMU, /* has PMU support */ 1811 ARM_FEATURE_VBAR, /* has cp15 VBAR */ 1812 ARM_FEATURE_M_SECURITY, /* M profile Security Extension */ 1813 ARM_FEATURE_M_MAIN, /* M profile Main Extension */ 1814 }; 1815 1816 static inline int arm_feature(CPUARMState *env, int feature) 1817 { 1818 return (env->features & (1ULL << feature)) != 0; 1819 } 1820 1821 #if !defined(CONFIG_USER_ONLY) 1822 /* Return true if exception levels below EL3 are in secure state, 1823 * or would be following an exception return to that level. 1824 * Unlike arm_is_secure() (which is always a question about the 1825 * _current_ state of the CPU) this doesn't care about the current 1826 * EL or mode. 1827 */ 1828 static inline bool arm_is_secure_below_el3(CPUARMState *env) 1829 { 1830 if (arm_feature(env, ARM_FEATURE_EL3)) { 1831 return !(env->cp15.scr_el3 & SCR_NS); 1832 } else { 1833 /* If EL3 is not supported then the secure state is implementation 1834 * defined, in which case QEMU defaults to non-secure. 1835 */ 1836 return false; 1837 } 1838 } 1839 1840 /* Return true if the CPU is AArch64 EL3 or AArch32 Mon */ 1841 static inline bool arm_is_el3_or_mon(CPUARMState *env) 1842 { 1843 if (arm_feature(env, ARM_FEATURE_EL3)) { 1844 if (is_a64(env) && extract32(env->pstate, 2, 2) == 3) { 1845 /* CPU currently in AArch64 state and EL3 */ 1846 return true; 1847 } else if (!is_a64(env) && 1848 (env->uncached_cpsr & CPSR_M) == ARM_CPU_MODE_MON) { 1849 /* CPU currently in AArch32 state and monitor mode */ 1850 return true; 1851 } 1852 } 1853 return false; 1854 } 1855 1856 /* Return true if the processor is in secure state */ 1857 static inline bool arm_is_secure(CPUARMState *env) 1858 { 1859 if (arm_is_el3_or_mon(env)) { 1860 return true; 1861 } 1862 return arm_is_secure_below_el3(env); 1863 } 1864 1865 #else 1866 static inline bool arm_is_secure_below_el3(CPUARMState *env) 1867 { 1868 return false; 1869 } 1870 1871 static inline bool arm_is_secure(CPUARMState *env) 1872 { 1873 return false; 1874 } 1875 #endif 1876 1877 /** 1878 * arm_hcr_el2_eff(): Return the effective value of HCR_EL2. 1879 * E.g. when in secure state, fields in HCR_EL2 are suppressed, 1880 * "for all purposes other than a direct read or write access of HCR_EL2." 1881 * Not included here is HCR_RW. 1882 */ 1883 uint64_t arm_hcr_el2_eff(CPUARMState *env); 1884 1885 /* Return true if the specified exception level is running in AArch64 state. */ 1886 static inline bool arm_el_is_aa64(CPUARMState *env, int el) 1887 { 1888 /* This isn't valid for EL0 (if we're in EL0, is_a64() is what you want, 1889 * and if we're not in EL0 then the state of EL0 isn't well defined.) 1890 */ 1891 assert(el >= 1 && el <= 3); 1892 bool aa64 = arm_feature(env, ARM_FEATURE_AARCH64); 1893 1894 /* The highest exception level is always at the maximum supported 1895 * register width, and then lower levels have a register width controlled 1896 * by bits in the SCR or HCR registers. 1897 */ 1898 if (el == 3) { 1899 return aa64; 1900 } 1901 1902 if (arm_feature(env, ARM_FEATURE_EL3)) { 1903 aa64 = aa64 && (env->cp15.scr_el3 & SCR_RW); 1904 } 1905 1906 if (el == 2) { 1907 return aa64; 1908 } 1909 1910 if (arm_feature(env, ARM_FEATURE_EL2) && !arm_is_secure_below_el3(env)) { 1911 aa64 = aa64 && (env->cp15.hcr_el2 & HCR_RW); 1912 } 1913 1914 return aa64; 1915 } 1916 1917 /* Function for determing whether guest cp register reads and writes should 1918 * access the secure or non-secure bank of a cp register. When EL3 is 1919 * operating in AArch32 state, the NS-bit determines whether the secure 1920 * instance of a cp register should be used. When EL3 is AArch64 (or if 1921 * it doesn't exist at all) then there is no register banking, and all 1922 * accesses are to the non-secure version. 1923 */ 1924 static inline bool access_secure_reg(CPUARMState *env) 1925 { 1926 bool ret = (arm_feature(env, ARM_FEATURE_EL3) && 1927 !arm_el_is_aa64(env, 3) && 1928 !(env->cp15.scr_el3 & SCR_NS)); 1929 1930 return ret; 1931 } 1932 1933 /* Macros for accessing a specified CP register bank */ 1934 #define A32_BANKED_REG_GET(_env, _regname, _secure) \ 1935 ((_secure) ? (_env)->cp15._regname##_s : (_env)->cp15._regname##_ns) 1936 1937 #define A32_BANKED_REG_SET(_env, _regname, _secure, _val) \ 1938 do { \ 1939 if (_secure) { \ 1940 (_env)->cp15._regname##_s = (_val); \ 1941 } else { \ 1942 (_env)->cp15._regname##_ns = (_val); \ 1943 } \ 1944 } while (0) 1945 1946 /* Macros for automatically accessing a specific CP register bank depending on 1947 * the current secure state of the system. These macros are not intended for 1948 * supporting instruction translation reads/writes as these are dependent 1949 * solely on the SCR.NS bit and not the mode. 1950 */ 1951 #define A32_BANKED_CURRENT_REG_GET(_env, _regname) \ 1952 A32_BANKED_REG_GET((_env), _regname, \ 1953 (arm_is_secure(_env) && !arm_el_is_aa64((_env), 3))) 1954 1955 #define A32_BANKED_CURRENT_REG_SET(_env, _regname, _val) \ 1956 A32_BANKED_REG_SET((_env), _regname, \ 1957 (arm_is_secure(_env) && !arm_el_is_aa64((_env), 3)), \ 1958 (_val)) 1959 1960 void arm_cpu_list(void); 1961 uint32_t arm_phys_excp_target_el(CPUState *cs, uint32_t excp_idx, 1962 uint32_t cur_el, bool secure); 1963 1964 /* Interface between CPU and Interrupt controller. */ 1965 #ifndef CONFIG_USER_ONLY 1966 bool armv7m_nvic_can_take_pending_exception(void *opaque); 1967 #else 1968 static inline bool armv7m_nvic_can_take_pending_exception(void *opaque) 1969 { 1970 return true; 1971 } 1972 #endif 1973 /** 1974 * armv7m_nvic_set_pending: mark the specified exception as pending 1975 * @opaque: the NVIC 1976 * @irq: the exception number to mark pending 1977 * @secure: false for non-banked exceptions or for the nonsecure 1978 * version of a banked exception, true for the secure version of a banked 1979 * exception. 1980 * 1981 * Marks the specified exception as pending. Note that we will assert() 1982 * if @secure is true and @irq does not specify one of the fixed set 1983 * of architecturally banked exceptions. 1984 */ 1985 void armv7m_nvic_set_pending(void *opaque, int irq, bool secure); 1986 /** 1987 * armv7m_nvic_set_pending_derived: mark this derived exception as pending 1988 * @opaque: the NVIC 1989 * @irq: the exception number to mark pending 1990 * @secure: false for non-banked exceptions or for the nonsecure 1991 * version of a banked exception, true for the secure version of a banked 1992 * exception. 1993 * 1994 * Similar to armv7m_nvic_set_pending(), but specifically for derived 1995 * exceptions (exceptions generated in the course of trying to take 1996 * a different exception). 1997 */ 1998 void armv7m_nvic_set_pending_derived(void *opaque, int irq, bool secure); 1999 /** 2000 * armv7m_nvic_set_pending_lazyfp: mark this lazy FP exception as pending 2001 * @opaque: the NVIC 2002 * @irq: the exception number to mark pending 2003 * @secure: false for non-banked exceptions or for the nonsecure 2004 * version of a banked exception, true for the secure version of a banked 2005 * exception. 2006 * 2007 * Similar to armv7m_nvic_set_pending(), but specifically for exceptions 2008 * generated in the course of lazy stacking of FP registers. 2009 */ 2010 void armv7m_nvic_set_pending_lazyfp(void *opaque, int irq, bool secure); 2011 /** 2012 * armv7m_nvic_get_pending_irq_info: return highest priority pending 2013 * exception, and whether it targets Secure state 2014 * @opaque: the NVIC 2015 * @pirq: set to pending exception number 2016 * @ptargets_secure: set to whether pending exception targets Secure 2017 * 2018 * This function writes the number of the highest priority pending 2019 * exception (the one which would be made active by 2020 * armv7m_nvic_acknowledge_irq()) to @pirq, and sets @ptargets_secure 2021 * to true if the current highest priority pending exception should 2022 * be taken to Secure state, false for NS. 2023 */ 2024 void armv7m_nvic_get_pending_irq_info(void *opaque, int *pirq, 2025 bool *ptargets_secure); 2026 /** 2027 * armv7m_nvic_acknowledge_irq: make highest priority pending exception active 2028 * @opaque: the NVIC 2029 * 2030 * Move the current highest priority pending exception from the pending 2031 * state to the active state, and update v7m.exception to indicate that 2032 * it is the exception currently being handled. 2033 */ 2034 void armv7m_nvic_acknowledge_irq(void *opaque); 2035 /** 2036 * armv7m_nvic_complete_irq: complete specified interrupt or exception 2037 * @opaque: the NVIC 2038 * @irq: the exception number to complete 2039 * @secure: true if this exception was secure 2040 * 2041 * Returns: -1 if the irq was not active 2042 * 1 if completing this irq brought us back to base (no active irqs) 2043 * 0 if there is still an irq active after this one was completed 2044 * (Ignoring -1, this is the same as the RETTOBASE value before completion.) 2045 */ 2046 int armv7m_nvic_complete_irq(void *opaque, int irq, bool secure); 2047 /** 2048 * armv7m_nvic_get_ready_status(void *opaque, int irq, bool secure) 2049 * @opaque: the NVIC 2050 * @irq: the exception number to mark pending 2051 * @secure: false for non-banked exceptions or for the nonsecure 2052 * version of a banked exception, true for the secure version of a banked 2053 * exception. 2054 * 2055 * Return whether an exception is "ready", i.e. whether the exception is 2056 * enabled and is configured at a priority which would allow it to 2057 * interrupt the current execution priority. This controls whether the 2058 * RDY bit for it in the FPCCR is set. 2059 */ 2060 bool armv7m_nvic_get_ready_status(void *opaque, int irq, bool secure); 2061 /** 2062 * armv7m_nvic_raw_execution_priority: return the raw execution priority 2063 * @opaque: the NVIC 2064 * 2065 * Returns: the raw execution priority as defined by the v8M architecture. 2066 * This is the execution priority minus the effects of AIRCR.PRIS, 2067 * and minus any PRIMASK/FAULTMASK/BASEPRI priority boosting. 2068 * (v8M ARM ARM I_PKLD.) 2069 */ 2070 int armv7m_nvic_raw_execution_priority(void *opaque); 2071 /** 2072 * armv7m_nvic_neg_prio_requested: return true if the requested execution 2073 * priority is negative for the specified security state. 2074 * @opaque: the NVIC 2075 * @secure: the security state to test 2076 * This corresponds to the pseudocode IsReqExecPriNeg(). 2077 */ 2078 #ifndef CONFIG_USER_ONLY 2079 bool armv7m_nvic_neg_prio_requested(void *opaque, bool secure); 2080 #else 2081 static inline bool armv7m_nvic_neg_prio_requested(void *opaque, bool secure) 2082 { 2083 return false; 2084 } 2085 #endif 2086 2087 /* Interface for defining coprocessor registers. 2088 * Registers are defined in tables of arm_cp_reginfo structs 2089 * which are passed to define_arm_cp_regs(). 2090 */ 2091 2092 /* When looking up a coprocessor register we look for it 2093 * via an integer which encodes all of: 2094 * coprocessor number 2095 * Crn, Crm, opc1, opc2 fields 2096 * 32 or 64 bit register (ie is it accessed via MRC/MCR 2097 * or via MRRC/MCRR?) 2098 * non-secure/secure bank (AArch32 only) 2099 * We allow 4 bits for opc1 because MRRC/MCRR have a 4 bit field. 2100 * (In this case crn and opc2 should be zero.) 2101 * For AArch64, there is no 32/64 bit size distinction; 2102 * instead all registers have a 2 bit op0, 3 bit op1 and op2, 2103 * and 4 bit CRn and CRm. The encoding patterns are chosen 2104 * to be easy to convert to and from the KVM encodings, and also 2105 * so that the hashtable can contain both AArch32 and AArch64 2106 * registers (to allow for interprocessing where we might run 2107 * 32 bit code on a 64 bit core). 2108 */ 2109 /* This bit is private to our hashtable cpreg; in KVM register 2110 * IDs the AArch64/32 distinction is the KVM_REG_ARM/ARM64 2111 * in the upper bits of the 64 bit ID. 2112 */ 2113 #define CP_REG_AA64_SHIFT 28 2114 #define CP_REG_AA64_MASK (1 << CP_REG_AA64_SHIFT) 2115 2116 /* To enable banking of coprocessor registers depending on ns-bit we 2117 * add a bit to distinguish between secure and non-secure cpregs in the 2118 * hashtable. 2119 */ 2120 #define CP_REG_NS_SHIFT 29 2121 #define CP_REG_NS_MASK (1 << CP_REG_NS_SHIFT) 2122 2123 #define ENCODE_CP_REG(cp, is64, ns, crn, crm, opc1, opc2) \ 2124 ((ns) << CP_REG_NS_SHIFT | ((cp) << 16) | ((is64) << 15) | \ 2125 ((crn) << 11) | ((crm) << 7) | ((opc1) << 3) | (opc2)) 2126 2127 #define ENCODE_AA64_CP_REG(cp, crn, crm, op0, op1, op2) \ 2128 (CP_REG_AA64_MASK | \ 2129 ((cp) << CP_REG_ARM_COPROC_SHIFT) | \ 2130 ((op0) << CP_REG_ARM64_SYSREG_OP0_SHIFT) | \ 2131 ((op1) << CP_REG_ARM64_SYSREG_OP1_SHIFT) | \ 2132 ((crn) << CP_REG_ARM64_SYSREG_CRN_SHIFT) | \ 2133 ((crm) << CP_REG_ARM64_SYSREG_CRM_SHIFT) | \ 2134 ((op2) << CP_REG_ARM64_SYSREG_OP2_SHIFT)) 2135 2136 /* Convert a full 64 bit KVM register ID to the truncated 32 bit 2137 * version used as a key for the coprocessor register hashtable 2138 */ 2139 static inline uint32_t kvm_to_cpreg_id(uint64_t kvmid) 2140 { 2141 uint32_t cpregid = kvmid; 2142 if ((kvmid & CP_REG_ARCH_MASK) == CP_REG_ARM64) { 2143 cpregid |= CP_REG_AA64_MASK; 2144 } else { 2145 if ((kvmid & CP_REG_SIZE_MASK) == CP_REG_SIZE_U64) { 2146 cpregid |= (1 << 15); 2147 } 2148 2149 /* KVM is always non-secure so add the NS flag on AArch32 register 2150 * entries. 2151 */ 2152 cpregid |= 1 << CP_REG_NS_SHIFT; 2153 } 2154 return cpregid; 2155 } 2156 2157 /* Convert a truncated 32 bit hashtable key into the full 2158 * 64 bit KVM register ID. 2159 */ 2160 static inline uint64_t cpreg_to_kvm_id(uint32_t cpregid) 2161 { 2162 uint64_t kvmid; 2163 2164 if (cpregid & CP_REG_AA64_MASK) { 2165 kvmid = cpregid & ~CP_REG_AA64_MASK; 2166 kvmid |= CP_REG_SIZE_U64 | CP_REG_ARM64; 2167 } else { 2168 kvmid = cpregid & ~(1 << 15); 2169 if (cpregid & (1 << 15)) { 2170 kvmid |= CP_REG_SIZE_U64 | CP_REG_ARM; 2171 } else { 2172 kvmid |= CP_REG_SIZE_U32 | CP_REG_ARM; 2173 } 2174 } 2175 return kvmid; 2176 } 2177 2178 /* ARMCPRegInfo type field bits. If the SPECIAL bit is set this is a 2179 * special-behaviour cp reg and bits [11..8] indicate what behaviour 2180 * it has. Otherwise it is a simple cp reg, where CONST indicates that 2181 * TCG can assume the value to be constant (ie load at translate time) 2182 * and 64BIT indicates a 64 bit wide coprocessor register. SUPPRESS_TB_END 2183 * indicates that the TB should not be ended after a write to this register 2184 * (the default is that the TB ends after cp writes). OVERRIDE permits 2185 * a register definition to override a previous definition for the 2186 * same (cp, is64, crn, crm, opc1, opc2) tuple: either the new or the 2187 * old must have the OVERRIDE bit set. 2188 * ALIAS indicates that this register is an alias view of some underlying 2189 * state which is also visible via another register, and that the other 2190 * register is handling migration and reset; registers marked ALIAS will not be 2191 * migrated but may have their state set by syncing of register state from KVM. 2192 * NO_RAW indicates that this register has no underlying state and does not 2193 * support raw access for state saving/loading; it will not be used for either 2194 * migration or KVM state synchronization. (Typically this is for "registers" 2195 * which are actually used as instructions for cache maintenance and so on.) 2196 * IO indicates that this register does I/O and therefore its accesses 2197 * need to be surrounded by gen_io_start()/gen_io_end(). In particular, 2198 * registers which implement clocks or timers require this. 2199 */ 2200 #define ARM_CP_SPECIAL 0x0001 2201 #define ARM_CP_CONST 0x0002 2202 #define ARM_CP_64BIT 0x0004 2203 #define ARM_CP_SUPPRESS_TB_END 0x0008 2204 #define ARM_CP_OVERRIDE 0x0010 2205 #define ARM_CP_ALIAS 0x0020 2206 #define ARM_CP_IO 0x0040 2207 #define ARM_CP_NO_RAW 0x0080 2208 #define ARM_CP_NOP (ARM_CP_SPECIAL | 0x0100) 2209 #define ARM_CP_WFI (ARM_CP_SPECIAL | 0x0200) 2210 #define ARM_CP_NZCV (ARM_CP_SPECIAL | 0x0300) 2211 #define ARM_CP_CURRENTEL (ARM_CP_SPECIAL | 0x0400) 2212 #define ARM_CP_DC_ZVA (ARM_CP_SPECIAL | 0x0500) 2213 #define ARM_LAST_SPECIAL ARM_CP_DC_ZVA 2214 #define ARM_CP_FPU 0x1000 2215 #define ARM_CP_SVE 0x2000 2216 #define ARM_CP_NO_GDB 0x4000 2217 /* Used only as a terminator for ARMCPRegInfo lists */ 2218 #define ARM_CP_SENTINEL 0xffff 2219 /* Mask of only the flag bits in a type field */ 2220 #define ARM_CP_FLAG_MASK 0x70ff 2221 2222 /* Valid values for ARMCPRegInfo state field, indicating which of 2223 * the AArch32 and AArch64 execution states this register is visible in. 2224 * If the reginfo doesn't explicitly specify then it is AArch32 only. 2225 * If the reginfo is declared to be visible in both states then a second 2226 * reginfo is synthesised for the AArch32 view of the AArch64 register, 2227 * such that the AArch32 view is the lower 32 bits of the AArch64 one. 2228 * Note that we rely on the values of these enums as we iterate through 2229 * the various states in some places. 2230 */ 2231 enum { 2232 ARM_CP_STATE_AA32 = 0, 2233 ARM_CP_STATE_AA64 = 1, 2234 ARM_CP_STATE_BOTH = 2, 2235 }; 2236 2237 /* ARM CP register secure state flags. These flags identify security state 2238 * attributes for a given CP register entry. 2239 * The existence of both or neither secure and non-secure flags indicates that 2240 * the register has both a secure and non-secure hash entry. A single one of 2241 * these flags causes the register to only be hashed for the specified 2242 * security state. 2243 * Although definitions may have any combination of the S/NS bits, each 2244 * registered entry will only have one to identify whether the entry is secure 2245 * or non-secure. 2246 */ 2247 enum { 2248 ARM_CP_SECSTATE_S = (1 << 0), /* bit[0]: Secure state register */ 2249 ARM_CP_SECSTATE_NS = (1 << 1), /* bit[1]: Non-secure state register */ 2250 }; 2251 2252 /* Return true if cptype is a valid type field. This is used to try to 2253 * catch errors where the sentinel has been accidentally left off the end 2254 * of a list of registers. 2255 */ 2256 static inline bool cptype_valid(int cptype) 2257 { 2258 return ((cptype & ~ARM_CP_FLAG_MASK) == 0) 2259 || ((cptype & ARM_CP_SPECIAL) && 2260 ((cptype & ~ARM_CP_FLAG_MASK) <= ARM_LAST_SPECIAL)); 2261 } 2262 2263 /* Access rights: 2264 * We define bits for Read and Write access for what rev C of the v7-AR ARM ARM 2265 * defines as PL0 (user), PL1 (fiq/irq/svc/abt/und/sys, ie privileged), and 2266 * PL2 (hyp). The other level which has Read and Write bits is Secure PL1 2267 * (ie any of the privileged modes in Secure state, or Monitor mode). 2268 * If a register is accessible in one privilege level it's always accessible 2269 * in higher privilege levels too. Since "Secure PL1" also follows this rule 2270 * (ie anything visible in PL2 is visible in S-PL1, some things are only 2271 * visible in S-PL1) but "Secure PL1" is a bit of a mouthful, we bend the 2272 * terminology a little and call this PL3. 2273 * In AArch64 things are somewhat simpler as the PLx bits line up exactly 2274 * with the ELx exception levels. 2275 * 2276 * If access permissions for a register are more complex than can be 2277 * described with these bits, then use a laxer set of restrictions, and 2278 * do the more restrictive/complex check inside a helper function. 2279 */ 2280 #define PL3_R 0x80 2281 #define PL3_W 0x40 2282 #define PL2_R (0x20 | PL3_R) 2283 #define PL2_W (0x10 | PL3_W) 2284 #define PL1_R (0x08 | PL2_R) 2285 #define PL1_W (0x04 | PL2_W) 2286 #define PL0_R (0x02 | PL1_R) 2287 #define PL0_W (0x01 | PL1_W) 2288 2289 /* 2290 * For user-mode some registers are accessible to EL0 via a kernel 2291 * trap-and-emulate ABI. In this case we define the read permissions 2292 * as actually being PL0_R. However some bits of any given register 2293 * may still be masked. 2294 */ 2295 #ifdef CONFIG_USER_ONLY 2296 #define PL0U_R PL0_R 2297 #else 2298 #define PL0U_R PL1_R 2299 #endif 2300 2301 #define PL3_RW (PL3_R | PL3_W) 2302 #define PL2_RW (PL2_R | PL2_W) 2303 #define PL1_RW (PL1_R | PL1_W) 2304 #define PL0_RW (PL0_R | PL0_W) 2305 2306 /* Return the highest implemented Exception Level */ 2307 static inline int arm_highest_el(CPUARMState *env) 2308 { 2309 if (arm_feature(env, ARM_FEATURE_EL3)) { 2310 return 3; 2311 } 2312 if (arm_feature(env, ARM_FEATURE_EL2)) { 2313 return 2; 2314 } 2315 return 1; 2316 } 2317 2318 /* Return true if a v7M CPU is in Handler mode */ 2319 static inline bool arm_v7m_is_handler_mode(CPUARMState *env) 2320 { 2321 return env->v7m.exception != 0; 2322 } 2323 2324 /* Return the current Exception Level (as per ARMv8; note that this differs 2325 * from the ARMv7 Privilege Level). 2326 */ 2327 static inline int arm_current_el(CPUARMState *env) 2328 { 2329 if (arm_feature(env, ARM_FEATURE_M)) { 2330 return arm_v7m_is_handler_mode(env) || 2331 !(env->v7m.control[env->v7m.secure] & 1); 2332 } 2333 2334 if (is_a64(env)) { 2335 return extract32(env->pstate, 2, 2); 2336 } 2337 2338 switch (env->uncached_cpsr & 0x1f) { 2339 case ARM_CPU_MODE_USR: 2340 return 0; 2341 case ARM_CPU_MODE_HYP: 2342 return 2; 2343 case ARM_CPU_MODE_MON: 2344 return 3; 2345 default: 2346 if (arm_is_secure(env) && !arm_el_is_aa64(env, 3)) { 2347 /* If EL3 is 32-bit then all secure privileged modes run in 2348 * EL3 2349 */ 2350 return 3; 2351 } 2352 2353 return 1; 2354 } 2355 } 2356 2357 typedef struct ARMCPRegInfo ARMCPRegInfo; 2358 2359 typedef enum CPAccessResult { 2360 /* Access is permitted */ 2361 CP_ACCESS_OK = 0, 2362 /* Access fails due to a configurable trap or enable which would 2363 * result in a categorized exception syndrome giving information about 2364 * the failing instruction (ie syndrome category 0x3, 0x4, 0x5, 0x6, 2365 * 0xc or 0x18). The exception is taken to the usual target EL (EL1 or 2366 * PL1 if in EL0, otherwise to the current EL). 2367 */ 2368 CP_ACCESS_TRAP = 1, 2369 /* Access fails and results in an exception syndrome 0x0 ("uncategorized"). 2370 * Note that this is not a catch-all case -- the set of cases which may 2371 * result in this failure is specifically defined by the architecture. 2372 */ 2373 CP_ACCESS_TRAP_UNCATEGORIZED = 2, 2374 /* As CP_ACCESS_TRAP, but for traps directly to EL2 or EL3 */ 2375 CP_ACCESS_TRAP_EL2 = 3, 2376 CP_ACCESS_TRAP_EL3 = 4, 2377 /* As CP_ACCESS_UNCATEGORIZED, but for traps directly to EL2 or EL3 */ 2378 CP_ACCESS_TRAP_UNCATEGORIZED_EL2 = 5, 2379 CP_ACCESS_TRAP_UNCATEGORIZED_EL3 = 6, 2380 /* Access fails and results in an exception syndrome for an FP access, 2381 * trapped directly to EL2 or EL3 2382 */ 2383 CP_ACCESS_TRAP_FP_EL2 = 7, 2384 CP_ACCESS_TRAP_FP_EL3 = 8, 2385 } CPAccessResult; 2386 2387 /* Access functions for coprocessor registers. These cannot fail and 2388 * may not raise exceptions. 2389 */ 2390 typedef uint64_t CPReadFn(CPUARMState *env, const ARMCPRegInfo *opaque); 2391 typedef void CPWriteFn(CPUARMState *env, const ARMCPRegInfo *opaque, 2392 uint64_t value); 2393 /* Access permission check functions for coprocessor registers. */ 2394 typedef CPAccessResult CPAccessFn(CPUARMState *env, 2395 const ARMCPRegInfo *opaque, 2396 bool isread); 2397 /* Hook function for register reset */ 2398 typedef void CPResetFn(CPUARMState *env, const ARMCPRegInfo *opaque); 2399 2400 #define CP_ANY 0xff 2401 2402 /* Definition of an ARM coprocessor register */ 2403 struct ARMCPRegInfo { 2404 /* Name of register (useful mainly for debugging, need not be unique) */ 2405 const char *name; 2406 /* Location of register: coprocessor number and (crn,crm,opc1,opc2) 2407 * tuple. Any of crm, opc1 and opc2 may be CP_ANY to indicate a 2408 * 'wildcard' field -- any value of that field in the MRC/MCR insn 2409 * will be decoded to this register. The register read and write 2410 * callbacks will be passed an ARMCPRegInfo with the crn/crm/opc1/opc2 2411 * used by the program, so it is possible to register a wildcard and 2412 * then behave differently on read/write if necessary. 2413 * For 64 bit registers, only crm and opc1 are relevant; crn and opc2 2414 * must both be zero. 2415 * For AArch64-visible registers, opc0 is also used. 2416 * Since there are no "coprocessors" in AArch64, cp is purely used as a 2417 * way to distinguish (for KVM's benefit) guest-visible system registers 2418 * from demuxed ones provided to preserve the "no side effects on 2419 * KVM register read/write from QEMU" semantics. cp==0x13 is guest 2420 * visible (to match KVM's encoding); cp==0 will be converted to 2421 * cp==0x13 when the ARMCPRegInfo is registered, for convenience. 2422 */ 2423 uint8_t cp; 2424 uint8_t crn; 2425 uint8_t crm; 2426 uint8_t opc0; 2427 uint8_t opc1; 2428 uint8_t opc2; 2429 /* Execution state in which this register is visible: ARM_CP_STATE_* */ 2430 int state; 2431 /* Register type: ARM_CP_* bits/values */ 2432 int type; 2433 /* Access rights: PL*_[RW] */ 2434 int access; 2435 /* Security state: ARM_CP_SECSTATE_* bits/values */ 2436 int secure; 2437 /* The opaque pointer passed to define_arm_cp_regs_with_opaque() when 2438 * this register was defined: can be used to hand data through to the 2439 * register read/write functions, since they are passed the ARMCPRegInfo*. 2440 */ 2441 void *opaque; 2442 /* Value of this register, if it is ARM_CP_CONST. Otherwise, if 2443 * fieldoffset is non-zero, the reset value of the register. 2444 */ 2445 uint64_t resetvalue; 2446 /* Offset of the field in CPUARMState for this register. 2447 * 2448 * This is not needed if either: 2449 * 1. type is ARM_CP_CONST or one of the ARM_CP_SPECIALs 2450 * 2. both readfn and writefn are specified 2451 */ 2452 ptrdiff_t fieldoffset; /* offsetof(CPUARMState, field) */ 2453 2454 /* Offsets of the secure and non-secure fields in CPUARMState for the 2455 * register if it is banked. These fields are only used during the static 2456 * registration of a register. During hashing the bank associated 2457 * with a given security state is copied to fieldoffset which is used from 2458 * there on out. 2459 * 2460 * It is expected that register definitions use either fieldoffset or 2461 * bank_fieldoffsets in the definition but not both. It is also expected 2462 * that both bank offsets are set when defining a banked register. This 2463 * use indicates that a register is banked. 2464 */ 2465 ptrdiff_t bank_fieldoffsets[2]; 2466 2467 /* Function for making any access checks for this register in addition to 2468 * those specified by the 'access' permissions bits. If NULL, no extra 2469 * checks required. The access check is performed at runtime, not at 2470 * translate time. 2471 */ 2472 CPAccessFn *accessfn; 2473 /* Function for handling reads of this register. If NULL, then reads 2474 * will be done by loading from the offset into CPUARMState specified 2475 * by fieldoffset. 2476 */ 2477 CPReadFn *readfn; 2478 /* Function for handling writes of this register. If NULL, then writes 2479 * will be done by writing to the offset into CPUARMState specified 2480 * by fieldoffset. 2481 */ 2482 CPWriteFn *writefn; 2483 /* Function for doing a "raw" read; used when we need to copy 2484 * coprocessor state to the kernel for KVM or out for 2485 * migration. This only needs to be provided if there is also a 2486 * readfn and it has side effects (for instance clear-on-read bits). 2487 */ 2488 CPReadFn *raw_readfn; 2489 /* Function for doing a "raw" write; used when we need to copy KVM 2490 * kernel coprocessor state into userspace, or for inbound 2491 * migration. This only needs to be provided if there is also a 2492 * writefn and it masks out "unwritable" bits or has write-one-to-clear 2493 * or similar behaviour. 2494 */ 2495 CPWriteFn *raw_writefn; 2496 /* Function for resetting the register. If NULL, then reset will be done 2497 * by writing resetvalue to the field specified in fieldoffset. If 2498 * fieldoffset is 0 then no reset will be done. 2499 */ 2500 CPResetFn *resetfn; 2501 }; 2502 2503 /* Macros which are lvalues for the field in CPUARMState for the 2504 * ARMCPRegInfo *ri. 2505 */ 2506 #define CPREG_FIELD32(env, ri) \ 2507 (*(uint32_t *)((char *)(env) + (ri)->fieldoffset)) 2508 #define CPREG_FIELD64(env, ri) \ 2509 (*(uint64_t *)((char *)(env) + (ri)->fieldoffset)) 2510 2511 #define REGINFO_SENTINEL { .type = ARM_CP_SENTINEL } 2512 2513 void define_arm_cp_regs_with_opaque(ARMCPU *cpu, 2514 const ARMCPRegInfo *regs, void *opaque); 2515 void define_one_arm_cp_reg_with_opaque(ARMCPU *cpu, 2516 const ARMCPRegInfo *regs, void *opaque); 2517 static inline void define_arm_cp_regs(ARMCPU *cpu, const ARMCPRegInfo *regs) 2518 { 2519 define_arm_cp_regs_with_opaque(cpu, regs, 0); 2520 } 2521 static inline void define_one_arm_cp_reg(ARMCPU *cpu, const ARMCPRegInfo *regs) 2522 { 2523 define_one_arm_cp_reg_with_opaque(cpu, regs, 0); 2524 } 2525 const ARMCPRegInfo *get_arm_cp_reginfo(GHashTable *cpregs, uint32_t encoded_cp); 2526 2527 /* 2528 * Definition of an ARM co-processor register as viewed from 2529 * userspace. This is used for presenting sanitised versions of 2530 * registers to userspace when emulating the Linux AArch64 CPU 2531 * ID/feature ABI (advertised as HWCAP_CPUID). 2532 */ 2533 typedef struct ARMCPRegUserSpaceInfo { 2534 /* Name of register */ 2535 const char *name; 2536 2537 /* Is the name actually a glob pattern */ 2538 bool is_glob; 2539 2540 /* Only some bits are exported to user space */ 2541 uint64_t exported_bits; 2542 2543 /* Fixed bits are applied after the mask */ 2544 uint64_t fixed_bits; 2545 } ARMCPRegUserSpaceInfo; 2546 2547 #define REGUSERINFO_SENTINEL { .name = NULL } 2548 2549 void modify_arm_cp_regs(ARMCPRegInfo *regs, const ARMCPRegUserSpaceInfo *mods); 2550 2551 /* CPWriteFn that can be used to implement writes-ignored behaviour */ 2552 void arm_cp_write_ignore(CPUARMState *env, const ARMCPRegInfo *ri, 2553 uint64_t value); 2554 /* CPReadFn that can be used for read-as-zero behaviour */ 2555 uint64_t arm_cp_read_zero(CPUARMState *env, const ARMCPRegInfo *ri); 2556 2557 /* CPResetFn that does nothing, for use if no reset is required even 2558 * if fieldoffset is non zero. 2559 */ 2560 void arm_cp_reset_ignore(CPUARMState *env, const ARMCPRegInfo *opaque); 2561 2562 /* Return true if this reginfo struct's field in the cpu state struct 2563 * is 64 bits wide. 2564 */ 2565 static inline bool cpreg_field_is_64bit(const ARMCPRegInfo *ri) 2566 { 2567 return (ri->state == ARM_CP_STATE_AA64) || (ri->type & ARM_CP_64BIT); 2568 } 2569 2570 static inline bool cp_access_ok(int current_el, 2571 const ARMCPRegInfo *ri, int isread) 2572 { 2573 return (ri->access >> ((current_el * 2) + isread)) & 1; 2574 } 2575 2576 /* Raw read of a coprocessor register (as needed for migration, etc) */ 2577 uint64_t read_raw_cp_reg(CPUARMState *env, const ARMCPRegInfo *ri); 2578 2579 /** 2580 * write_list_to_cpustate 2581 * @cpu: ARMCPU 2582 * 2583 * For each register listed in the ARMCPU cpreg_indexes list, write 2584 * its value from the cpreg_values list into the ARMCPUState structure. 2585 * This updates TCG's working data structures from KVM data or 2586 * from incoming migration state. 2587 * 2588 * Returns: true if all register values were updated correctly, 2589 * false if some register was unknown or could not be written. 2590 * Note that we do not stop early on failure -- we will attempt 2591 * writing all registers in the list. 2592 */ 2593 bool write_list_to_cpustate(ARMCPU *cpu); 2594 2595 /** 2596 * write_cpustate_to_list: 2597 * @cpu: ARMCPU 2598 * @kvm_sync: true if this is for syncing back to KVM 2599 * 2600 * For each register listed in the ARMCPU cpreg_indexes list, write 2601 * its value from the ARMCPUState structure into the cpreg_values list. 2602 * This is used to copy info from TCG's working data structures into 2603 * KVM or for outbound migration. 2604 * 2605 * @kvm_sync is true if we are doing this in order to sync the 2606 * register state back to KVM. In this case we will only update 2607 * values in the list if the previous list->cpustate sync actually 2608 * successfully wrote the CPU state. Otherwise we will keep the value 2609 * that is in the list. 2610 * 2611 * Returns: true if all register values were read correctly, 2612 * false if some register was unknown or could not be read. 2613 * Note that we do not stop early on failure -- we will attempt 2614 * reading all registers in the list. 2615 */ 2616 bool write_cpustate_to_list(ARMCPU *cpu, bool kvm_sync); 2617 2618 #define ARM_CPUID_TI915T 0x54029152 2619 #define ARM_CPUID_TI925T 0x54029252 2620 2621 static inline bool arm_excp_unmasked(CPUState *cs, unsigned int excp_idx, 2622 unsigned int target_el) 2623 { 2624 CPUARMState *env = cs->env_ptr; 2625 unsigned int cur_el = arm_current_el(env); 2626 bool secure = arm_is_secure(env); 2627 bool pstate_unmasked; 2628 int8_t unmasked = 0; 2629 uint64_t hcr_el2; 2630 2631 /* Don't take exceptions if they target a lower EL. 2632 * This check should catch any exceptions that would not be taken but left 2633 * pending. 2634 */ 2635 if (cur_el > target_el) { 2636 return false; 2637 } 2638 2639 hcr_el2 = arm_hcr_el2_eff(env); 2640 2641 switch (excp_idx) { 2642 case EXCP_FIQ: 2643 pstate_unmasked = !(env->daif & PSTATE_F); 2644 break; 2645 2646 case EXCP_IRQ: 2647 pstate_unmasked = !(env->daif & PSTATE_I); 2648 break; 2649 2650 case EXCP_VFIQ: 2651 if (secure || !(hcr_el2 & HCR_FMO) || (hcr_el2 & HCR_TGE)) { 2652 /* VFIQs are only taken when hypervized and non-secure. */ 2653 return false; 2654 } 2655 return !(env->daif & PSTATE_F); 2656 case EXCP_VIRQ: 2657 if (secure || !(hcr_el2 & HCR_IMO) || (hcr_el2 & HCR_TGE)) { 2658 /* VIRQs are only taken when hypervized and non-secure. */ 2659 return false; 2660 } 2661 return !(env->daif & PSTATE_I); 2662 default: 2663 g_assert_not_reached(); 2664 } 2665 2666 /* Use the target EL, current execution state and SCR/HCR settings to 2667 * determine whether the corresponding CPSR bit is used to mask the 2668 * interrupt. 2669 */ 2670 if ((target_el > cur_el) && (target_el != 1)) { 2671 /* Exceptions targeting a higher EL may not be maskable */ 2672 if (arm_feature(env, ARM_FEATURE_AARCH64)) { 2673 /* 64-bit masking rules are simple: exceptions to EL3 2674 * can't be masked, and exceptions to EL2 can only be 2675 * masked from Secure state. The HCR and SCR settings 2676 * don't affect the masking logic, only the interrupt routing. 2677 */ 2678 if (target_el == 3 || !secure) { 2679 unmasked = 1; 2680 } 2681 } else { 2682 /* The old 32-bit-only environment has a more complicated 2683 * masking setup. HCR and SCR bits not only affect interrupt 2684 * routing but also change the behaviour of masking. 2685 */ 2686 bool hcr, scr; 2687 2688 switch (excp_idx) { 2689 case EXCP_FIQ: 2690 /* If FIQs are routed to EL3 or EL2 then there are cases where 2691 * we override the CPSR.F in determining if the exception is 2692 * masked or not. If neither of these are set then we fall back 2693 * to the CPSR.F setting otherwise we further assess the state 2694 * below. 2695 */ 2696 hcr = hcr_el2 & HCR_FMO; 2697 scr = (env->cp15.scr_el3 & SCR_FIQ); 2698 2699 /* When EL3 is 32-bit, the SCR.FW bit controls whether the 2700 * CPSR.F bit masks FIQ interrupts when taken in non-secure 2701 * state. If SCR.FW is set then FIQs can be masked by CPSR.F 2702 * when non-secure but only when FIQs are only routed to EL3. 2703 */ 2704 scr = scr && !((env->cp15.scr_el3 & SCR_FW) && !hcr); 2705 break; 2706 case EXCP_IRQ: 2707 /* When EL3 execution state is 32-bit, if HCR.IMO is set then 2708 * we may override the CPSR.I masking when in non-secure state. 2709 * The SCR.IRQ setting has already been taken into consideration 2710 * when setting the target EL, so it does not have a further 2711 * affect here. 2712 */ 2713 hcr = hcr_el2 & HCR_IMO; 2714 scr = false; 2715 break; 2716 default: 2717 g_assert_not_reached(); 2718 } 2719 2720 if ((scr || hcr) && !secure) { 2721 unmasked = 1; 2722 } 2723 } 2724 } 2725 2726 /* The PSTATE bits only mask the interrupt if we have not overriden the 2727 * ability above. 2728 */ 2729 return unmasked || pstate_unmasked; 2730 } 2731 2732 #define ARM_CPU_TYPE_SUFFIX "-" TYPE_ARM_CPU 2733 #define ARM_CPU_TYPE_NAME(name) (name ARM_CPU_TYPE_SUFFIX) 2734 #define CPU_RESOLVING_TYPE TYPE_ARM_CPU 2735 2736 #define cpu_signal_handler cpu_arm_signal_handler 2737 #define cpu_list arm_cpu_list 2738 2739 /* ARM has the following "translation regimes" (as the ARM ARM calls them): 2740 * 2741 * If EL3 is 64-bit: 2742 * + NonSecure EL1 & 0 stage 1 2743 * + NonSecure EL1 & 0 stage 2 2744 * + NonSecure EL2 2745 * + Secure EL1 & EL0 2746 * + Secure EL3 2747 * If EL3 is 32-bit: 2748 * + NonSecure PL1 & 0 stage 1 2749 * + NonSecure PL1 & 0 stage 2 2750 * + NonSecure PL2 2751 * + Secure PL0 & PL1 2752 * (reminder: for 32 bit EL3, Secure PL1 is *EL3*, not EL1.) 2753 * 2754 * For QEMU, an mmu_idx is not quite the same as a translation regime because: 2755 * 1. we need to split the "EL1 & 0" regimes into two mmu_idxes, because they 2756 * may differ in access permissions even if the VA->PA map is the same 2757 * 2. we want to cache in our TLB the full VA->IPA->PA lookup for a stage 1+2 2758 * translation, which means that we have one mmu_idx that deals with two 2759 * concatenated translation regimes [this sort of combined s1+2 TLB is 2760 * architecturally permitted] 2761 * 3. we don't need to allocate an mmu_idx to translations that we won't be 2762 * handling via the TLB. The only way to do a stage 1 translation without 2763 * the immediate stage 2 translation is via the ATS or AT system insns, 2764 * which can be slow-pathed and always do a page table walk. 2765 * 4. we can also safely fold together the "32 bit EL3" and "64 bit EL3" 2766 * translation regimes, because they map reasonably well to each other 2767 * and they can't both be active at the same time. 2768 * This gives us the following list of mmu_idx values: 2769 * 2770 * NS EL0 (aka NS PL0) stage 1+2 2771 * NS EL1 (aka NS PL1) stage 1+2 2772 * NS EL2 (aka NS PL2) 2773 * S EL3 (aka S PL1) 2774 * S EL0 (aka S PL0) 2775 * S EL1 (not used if EL3 is 32 bit) 2776 * NS EL0+1 stage 2 2777 * 2778 * (The last of these is an mmu_idx because we want to be able to use the TLB 2779 * for the accesses done as part of a stage 1 page table walk, rather than 2780 * having to walk the stage 2 page table over and over.) 2781 * 2782 * R profile CPUs have an MPU, but can use the same set of MMU indexes 2783 * as A profile. They only need to distinguish NS EL0 and NS EL1 (and 2784 * NS EL2 if we ever model a Cortex-R52). 2785 * 2786 * M profile CPUs are rather different as they do not have a true MMU. 2787 * They have the following different MMU indexes: 2788 * User 2789 * Privileged 2790 * User, execution priority negative (ie the MPU HFNMIENA bit may apply) 2791 * Privileged, execution priority negative (ditto) 2792 * If the CPU supports the v8M Security Extension then there are also: 2793 * Secure User 2794 * Secure Privileged 2795 * Secure User, execution priority negative 2796 * Secure Privileged, execution priority negative 2797 * 2798 * The ARMMMUIdx and the mmu index value used by the core QEMU TLB code 2799 * are not quite the same -- different CPU types (most notably M profile 2800 * vs A/R profile) would like to use MMU indexes with different semantics, 2801 * but since we don't ever need to use all of those in a single CPU we 2802 * can avoid setting NB_MMU_MODES to more than 8. The lower bits of 2803 * ARMMMUIdx are the core TLB mmu index, and the higher bits are always 2804 * the same for any particular CPU. 2805 * Variables of type ARMMUIdx are always full values, and the core 2806 * index values are in variables of type 'int'. 2807 * 2808 * Our enumeration includes at the end some entries which are not "true" 2809 * mmu_idx values in that they don't have corresponding TLBs and are only 2810 * valid for doing slow path page table walks. 2811 * 2812 * The constant names here are patterned after the general style of the names 2813 * of the AT/ATS operations. 2814 * The values used are carefully arranged to make mmu_idx => EL lookup easy. 2815 * For M profile we arrange them to have a bit for priv, a bit for negpri 2816 * and a bit for secure. 2817 */ 2818 #define ARM_MMU_IDX_A 0x10 /* A profile */ 2819 #define ARM_MMU_IDX_NOTLB 0x20 /* does not have a TLB */ 2820 #define ARM_MMU_IDX_M 0x40 /* M profile */ 2821 2822 /* meanings of the bits for M profile mmu idx values */ 2823 #define ARM_MMU_IDX_M_PRIV 0x1 2824 #define ARM_MMU_IDX_M_NEGPRI 0x2 2825 #define ARM_MMU_IDX_M_S 0x4 2826 2827 #define ARM_MMU_IDX_TYPE_MASK (~0x7) 2828 #define ARM_MMU_IDX_COREIDX_MASK 0x7 2829 2830 typedef enum ARMMMUIdx { 2831 ARMMMUIdx_S12NSE0 = 0 | ARM_MMU_IDX_A, 2832 ARMMMUIdx_S12NSE1 = 1 | ARM_MMU_IDX_A, 2833 ARMMMUIdx_S1E2 = 2 | ARM_MMU_IDX_A, 2834 ARMMMUIdx_S1E3 = 3 | ARM_MMU_IDX_A, 2835 ARMMMUIdx_S1SE0 = 4 | ARM_MMU_IDX_A, 2836 ARMMMUIdx_S1SE1 = 5 | ARM_MMU_IDX_A, 2837 ARMMMUIdx_S2NS = 6 | ARM_MMU_IDX_A, 2838 ARMMMUIdx_MUser = 0 | ARM_MMU_IDX_M, 2839 ARMMMUIdx_MPriv = 1 | ARM_MMU_IDX_M, 2840 ARMMMUIdx_MUserNegPri = 2 | ARM_MMU_IDX_M, 2841 ARMMMUIdx_MPrivNegPri = 3 | ARM_MMU_IDX_M, 2842 ARMMMUIdx_MSUser = 4 | ARM_MMU_IDX_M, 2843 ARMMMUIdx_MSPriv = 5 | ARM_MMU_IDX_M, 2844 ARMMMUIdx_MSUserNegPri = 6 | ARM_MMU_IDX_M, 2845 ARMMMUIdx_MSPrivNegPri = 7 | ARM_MMU_IDX_M, 2846 /* Indexes below here don't have TLBs and are used only for AT system 2847 * instructions or for the first stage of an S12 page table walk. 2848 */ 2849 ARMMMUIdx_S1NSE0 = 0 | ARM_MMU_IDX_NOTLB, 2850 ARMMMUIdx_S1NSE1 = 1 | ARM_MMU_IDX_NOTLB, 2851 } ARMMMUIdx; 2852 2853 /* Bit macros for the core-mmu-index values for each index, 2854 * for use when calling tlb_flush_by_mmuidx() and friends. 2855 */ 2856 typedef enum ARMMMUIdxBit { 2857 ARMMMUIdxBit_S12NSE0 = 1 << 0, 2858 ARMMMUIdxBit_S12NSE1 = 1 << 1, 2859 ARMMMUIdxBit_S1E2 = 1 << 2, 2860 ARMMMUIdxBit_S1E3 = 1 << 3, 2861 ARMMMUIdxBit_S1SE0 = 1 << 4, 2862 ARMMMUIdxBit_S1SE1 = 1 << 5, 2863 ARMMMUIdxBit_S2NS = 1 << 6, 2864 ARMMMUIdxBit_MUser = 1 << 0, 2865 ARMMMUIdxBit_MPriv = 1 << 1, 2866 ARMMMUIdxBit_MUserNegPri = 1 << 2, 2867 ARMMMUIdxBit_MPrivNegPri = 1 << 3, 2868 ARMMMUIdxBit_MSUser = 1 << 4, 2869 ARMMMUIdxBit_MSPriv = 1 << 5, 2870 ARMMMUIdxBit_MSUserNegPri = 1 << 6, 2871 ARMMMUIdxBit_MSPrivNegPri = 1 << 7, 2872 } ARMMMUIdxBit; 2873 2874 #define MMU_USER_IDX 0 2875 2876 static inline int arm_to_core_mmu_idx(ARMMMUIdx mmu_idx) 2877 { 2878 return mmu_idx & ARM_MMU_IDX_COREIDX_MASK; 2879 } 2880 2881 static inline ARMMMUIdx core_to_arm_mmu_idx(CPUARMState *env, int mmu_idx) 2882 { 2883 if (arm_feature(env, ARM_FEATURE_M)) { 2884 return mmu_idx | ARM_MMU_IDX_M; 2885 } else { 2886 return mmu_idx | ARM_MMU_IDX_A; 2887 } 2888 } 2889 2890 /* Return the exception level we're running at if this is our mmu_idx */ 2891 static inline int arm_mmu_idx_to_el(ARMMMUIdx mmu_idx) 2892 { 2893 switch (mmu_idx & ARM_MMU_IDX_TYPE_MASK) { 2894 case ARM_MMU_IDX_A: 2895 return mmu_idx & 3; 2896 case ARM_MMU_IDX_M: 2897 return mmu_idx & ARM_MMU_IDX_M_PRIV; 2898 default: 2899 g_assert_not_reached(); 2900 } 2901 } 2902 2903 /* 2904 * Return the MMU index for a v7M CPU with all relevant information 2905 * manually specified. 2906 */ 2907 ARMMMUIdx arm_v7m_mmu_idx_all(CPUARMState *env, 2908 bool secstate, bool priv, bool negpri); 2909 2910 /* Return the MMU index for a v7M CPU in the specified security and 2911 * privilege state. 2912 */ 2913 ARMMMUIdx arm_v7m_mmu_idx_for_secstate_and_priv(CPUARMState *env, 2914 bool secstate, bool priv); 2915 2916 /* Return the MMU index for a v7M CPU in the specified security state */ 2917 ARMMMUIdx arm_v7m_mmu_idx_for_secstate(CPUARMState *env, bool secstate); 2918 2919 /** 2920 * cpu_mmu_index: 2921 * @env: The cpu environment 2922 * @ifetch: True for code access, false for data access. 2923 * 2924 * Return the core mmu index for the current translation regime. 2925 * This function is used by generic TCG code paths. 2926 */ 2927 int cpu_mmu_index(CPUARMState *env, bool ifetch); 2928 2929 /* Indexes used when registering address spaces with cpu_address_space_init */ 2930 typedef enum ARMASIdx { 2931 ARMASIdx_NS = 0, 2932 ARMASIdx_S = 1, 2933 } ARMASIdx; 2934 2935 /* Return the Exception Level targeted by debug exceptions. */ 2936 static inline int arm_debug_target_el(CPUARMState *env) 2937 { 2938 bool secure = arm_is_secure(env); 2939 bool route_to_el2 = false; 2940 2941 if (arm_feature(env, ARM_FEATURE_EL2) && !secure) { 2942 route_to_el2 = env->cp15.hcr_el2 & HCR_TGE || 2943 env->cp15.mdcr_el2 & MDCR_TDE; 2944 } 2945 2946 if (route_to_el2) { 2947 return 2; 2948 } else if (arm_feature(env, ARM_FEATURE_EL3) && 2949 !arm_el_is_aa64(env, 3) && secure) { 2950 return 3; 2951 } else { 2952 return 1; 2953 } 2954 } 2955 2956 static inline bool arm_v7m_csselr_razwi(ARMCPU *cpu) 2957 { 2958 /* If all the CLIDR.Ctypem bits are 0 there are no caches, and 2959 * CSSELR is RAZ/WI. 2960 */ 2961 return (cpu->clidr & R_V7M_CLIDR_CTYPE_ALL_MASK) != 0; 2962 } 2963 2964 /* See AArch64.GenerateDebugExceptionsFrom() in ARM ARM pseudocode */ 2965 static inline bool aa64_generate_debug_exceptions(CPUARMState *env) 2966 { 2967 int cur_el = arm_current_el(env); 2968 int debug_el; 2969 2970 if (cur_el == 3) { 2971 return false; 2972 } 2973 2974 /* MDCR_EL3.SDD disables debug events from Secure state */ 2975 if (arm_is_secure_below_el3(env) 2976 && extract32(env->cp15.mdcr_el3, 16, 1)) { 2977 return false; 2978 } 2979 2980 /* 2981 * Same EL to same EL debug exceptions need MDSCR_KDE enabled 2982 * while not masking the (D)ebug bit in DAIF. 2983 */ 2984 debug_el = arm_debug_target_el(env); 2985 2986 if (cur_el == debug_el) { 2987 return extract32(env->cp15.mdscr_el1, 13, 1) 2988 && !(env->daif & PSTATE_D); 2989 } 2990 2991 /* Otherwise the debug target needs to be a higher EL */ 2992 return debug_el > cur_el; 2993 } 2994 2995 static inline bool aa32_generate_debug_exceptions(CPUARMState *env) 2996 { 2997 int el = arm_current_el(env); 2998 2999 if (el == 0 && arm_el_is_aa64(env, 1)) { 3000 return aa64_generate_debug_exceptions(env); 3001 } 3002 3003 if (arm_is_secure(env)) { 3004 int spd; 3005 3006 if (el == 0 && (env->cp15.sder & 1)) { 3007 /* SDER.SUIDEN means debug exceptions from Secure EL0 3008 * are always enabled. Otherwise they are controlled by 3009 * SDCR.SPD like those from other Secure ELs. 3010 */ 3011 return true; 3012 } 3013 3014 spd = extract32(env->cp15.mdcr_el3, 14, 2); 3015 switch (spd) { 3016 case 1: 3017 /* SPD == 0b01 is reserved, but behaves as 0b00. */ 3018 case 0: 3019 /* For 0b00 we return true if external secure invasive debug 3020 * is enabled. On real hardware this is controlled by external 3021 * signals to the core. QEMU always permits debug, and behaves 3022 * as if DBGEN, SPIDEN, NIDEN and SPNIDEN are all tied high. 3023 */ 3024 return true; 3025 case 2: 3026 return false; 3027 case 3: 3028 return true; 3029 } 3030 } 3031 3032 return el != 2; 3033 } 3034 3035 /* Return true if debugging exceptions are currently enabled. 3036 * This corresponds to what in ARM ARM pseudocode would be 3037 * if UsingAArch32() then 3038 * return AArch32.GenerateDebugExceptions() 3039 * else 3040 * return AArch64.GenerateDebugExceptions() 3041 * We choose to push the if() down into this function for clarity, 3042 * since the pseudocode has it at all callsites except for the one in 3043 * CheckSoftwareStep(), where it is elided because both branches would 3044 * always return the same value. 3045 */ 3046 static inline bool arm_generate_debug_exceptions(CPUARMState *env) 3047 { 3048 if (env->aarch64) { 3049 return aa64_generate_debug_exceptions(env); 3050 } else { 3051 return aa32_generate_debug_exceptions(env); 3052 } 3053 } 3054 3055 /* Is single-stepping active? (Note that the "is EL_D AArch64?" check 3056 * implicitly means this always returns false in pre-v8 CPUs.) 3057 */ 3058 static inline bool arm_singlestep_active(CPUARMState *env) 3059 { 3060 return extract32(env->cp15.mdscr_el1, 0, 1) 3061 && arm_el_is_aa64(env, arm_debug_target_el(env)) 3062 && arm_generate_debug_exceptions(env); 3063 } 3064 3065 static inline bool arm_sctlr_b(CPUARMState *env) 3066 { 3067 return 3068 /* We need not implement SCTLR.ITD in user-mode emulation, so 3069 * let linux-user ignore the fact that it conflicts with SCTLR_B. 3070 * This lets people run BE32 binaries with "-cpu any". 3071 */ 3072 #ifndef CONFIG_USER_ONLY 3073 !arm_feature(env, ARM_FEATURE_V7) && 3074 #endif 3075 (env->cp15.sctlr_el[1] & SCTLR_B) != 0; 3076 } 3077 3078 static inline uint64_t arm_sctlr(CPUARMState *env, int el) 3079 { 3080 if (el == 0) { 3081 /* FIXME: ARMv8.1-VHE S2 translation regime. */ 3082 return env->cp15.sctlr_el[1]; 3083 } else { 3084 return env->cp15.sctlr_el[el]; 3085 } 3086 } 3087 3088 3089 /* Return true if the processor is in big-endian mode. */ 3090 static inline bool arm_cpu_data_is_big_endian(CPUARMState *env) 3091 { 3092 /* In 32bit endianness is determined by looking at CPSR's E bit */ 3093 if (!is_a64(env)) { 3094 return 3095 #ifdef CONFIG_USER_ONLY 3096 /* In system mode, BE32 is modelled in line with the 3097 * architecture (as word-invariant big-endianness), where loads 3098 * and stores are done little endian but from addresses which 3099 * are adjusted by XORing with the appropriate constant. So the 3100 * endianness to use for the raw data access is not affected by 3101 * SCTLR.B. 3102 * In user mode, however, we model BE32 as byte-invariant 3103 * big-endianness (because user-only code cannot tell the 3104 * difference), and so we need to use a data access endianness 3105 * that depends on SCTLR.B. 3106 */ 3107 arm_sctlr_b(env) || 3108 #endif 3109 ((env->uncached_cpsr & CPSR_E) ? 1 : 0); 3110 } else { 3111 int cur_el = arm_current_el(env); 3112 uint64_t sctlr = arm_sctlr(env, cur_el); 3113 3114 return (sctlr & (cur_el ? SCTLR_EE : SCTLR_E0E)) != 0; 3115 } 3116 } 3117 3118 typedef CPUARMState CPUArchState; 3119 typedef ARMCPU ArchCPU; 3120 3121 #include "exec/cpu-all.h" 3122 3123 /* Bit usage in the TB flags field: bit 31 indicates whether we are 3124 * in 32 or 64 bit mode. The meaning of the other bits depends on that. 3125 * We put flags which are shared between 32 and 64 bit mode at the top 3126 * of the word, and flags which apply to only one mode at the bottom. 3127 */ 3128 FIELD(TBFLAG_ANY, AARCH64_STATE, 31, 1) 3129 FIELD(TBFLAG_ANY, MMUIDX, 28, 3) 3130 FIELD(TBFLAG_ANY, SS_ACTIVE, 27, 1) 3131 FIELD(TBFLAG_ANY, PSTATE_SS, 26, 1) 3132 /* Target EL if we take a floating-point-disabled exception */ 3133 FIELD(TBFLAG_ANY, FPEXC_EL, 24, 2) 3134 FIELD(TBFLAG_ANY, BE_DATA, 23, 1) 3135 3136 /* Bit usage when in AArch32 state: */ 3137 FIELD(TBFLAG_A32, THUMB, 0, 1) 3138 FIELD(TBFLAG_A32, VECLEN, 1, 3) 3139 FIELD(TBFLAG_A32, VECSTRIDE, 4, 2) 3140 /* 3141 * We store the bottom two bits of the CPAR as TB flags and handle 3142 * checks on the other bits at runtime. This shares the same bits as 3143 * VECSTRIDE, which is OK as no XScale CPU has VFP. 3144 */ 3145 FIELD(TBFLAG_A32, XSCALE_CPAR, 4, 2) 3146 /* 3147 * Indicates whether cp register reads and writes by guest code should access 3148 * the secure or nonsecure bank of banked registers; note that this is not 3149 * the same thing as the current security state of the processor! 3150 */ 3151 FIELD(TBFLAG_A32, NS, 6, 1) 3152 FIELD(TBFLAG_A32, VFPEN, 7, 1) 3153 FIELD(TBFLAG_A32, CONDEXEC, 8, 8) 3154 FIELD(TBFLAG_A32, SCTLR_B, 16, 1) 3155 /* For M profile only, set if FPCCR.LSPACT is set */ 3156 FIELD(TBFLAG_A32, LSPACT, 18, 1) 3157 /* For M profile only, set if we must create a new FP context */ 3158 FIELD(TBFLAG_A32, NEW_FP_CTXT_NEEDED, 19, 1) 3159 /* For M profile only, set if FPCCR.S does not match current security state */ 3160 FIELD(TBFLAG_A32, FPCCR_S_WRONG, 20, 1) 3161 /* For M profile only, Handler (ie not Thread) mode */ 3162 FIELD(TBFLAG_A32, HANDLER, 21, 1) 3163 /* For M profile only, whether we should generate stack-limit checks */ 3164 FIELD(TBFLAG_A32, STACKCHECK, 22, 1) 3165 3166 /* Bit usage when in AArch64 state */ 3167 FIELD(TBFLAG_A64, TBII, 0, 2) 3168 FIELD(TBFLAG_A64, SVEEXC_EL, 2, 2) 3169 FIELD(TBFLAG_A64, ZCR_LEN, 4, 4) 3170 FIELD(TBFLAG_A64, PAUTH_ACTIVE, 8, 1) 3171 FIELD(TBFLAG_A64, BT, 9, 1) 3172 FIELD(TBFLAG_A64, BTYPE, 10, 2) 3173 FIELD(TBFLAG_A64, TBID, 12, 2) 3174 3175 static inline bool bswap_code(bool sctlr_b) 3176 { 3177 #ifdef CONFIG_USER_ONLY 3178 /* BE8 (SCTLR.B = 0, TARGET_WORDS_BIGENDIAN = 1) is mixed endian. 3179 * The invalid combination SCTLR.B=1/CPSR.E=1/TARGET_WORDS_BIGENDIAN=0 3180 * would also end up as a mixed-endian mode with BE code, LE data. 3181 */ 3182 return 3183 #ifdef TARGET_WORDS_BIGENDIAN 3184 1 ^ 3185 #endif 3186 sctlr_b; 3187 #else 3188 /* All code access in ARM is little endian, and there are no loaders 3189 * doing swaps that need to be reversed 3190 */ 3191 return 0; 3192 #endif 3193 } 3194 3195 #ifdef CONFIG_USER_ONLY 3196 static inline bool arm_cpu_bswap_data(CPUARMState *env) 3197 { 3198 return 3199 #ifdef TARGET_WORDS_BIGENDIAN 3200 1 ^ 3201 #endif 3202 arm_cpu_data_is_big_endian(env); 3203 } 3204 #endif 3205 3206 void cpu_get_tb_cpu_state(CPUARMState *env, target_ulong *pc, 3207 target_ulong *cs_base, uint32_t *flags); 3208 3209 enum { 3210 QEMU_PSCI_CONDUIT_DISABLED = 0, 3211 QEMU_PSCI_CONDUIT_SMC = 1, 3212 QEMU_PSCI_CONDUIT_HVC = 2, 3213 }; 3214 3215 #ifndef CONFIG_USER_ONLY 3216 /* Return the address space index to use for a memory access */ 3217 static inline int arm_asidx_from_attrs(CPUState *cs, MemTxAttrs attrs) 3218 { 3219 return attrs.secure ? ARMASIdx_S : ARMASIdx_NS; 3220 } 3221 3222 /* Return the AddressSpace to use for a memory access 3223 * (which depends on whether the access is S or NS, and whether 3224 * the board gave us a separate AddressSpace for S accesses). 3225 */ 3226 static inline AddressSpace *arm_addressspace(CPUState *cs, MemTxAttrs attrs) 3227 { 3228 return cpu_get_address_space(cs, arm_asidx_from_attrs(cs, attrs)); 3229 } 3230 #endif 3231 3232 /** 3233 * arm_register_pre_el_change_hook: 3234 * Register a hook function which will be called immediately before this 3235 * CPU changes exception level or mode. The hook function will be 3236 * passed a pointer to the ARMCPU and the opaque data pointer passed 3237 * to this function when the hook was registered. 3238 * 3239 * Note that if a pre-change hook is called, any registered post-change hooks 3240 * are guaranteed to subsequently be called. 3241 */ 3242 void arm_register_pre_el_change_hook(ARMCPU *cpu, ARMELChangeHookFn *hook, 3243 void *opaque); 3244 /** 3245 * arm_register_el_change_hook: 3246 * Register a hook function which will be called immediately after this 3247 * CPU changes exception level or mode. The hook function will be 3248 * passed a pointer to the ARMCPU and the opaque data pointer passed 3249 * to this function when the hook was registered. 3250 * 3251 * Note that any registered hooks registered here are guaranteed to be called 3252 * if pre-change hooks have been. 3253 */ 3254 void arm_register_el_change_hook(ARMCPU *cpu, ARMELChangeHookFn *hook, void 3255 *opaque); 3256 3257 /** 3258 * aa32_vfp_dreg: 3259 * Return a pointer to the Dn register within env in 32-bit mode. 3260 */ 3261 static inline uint64_t *aa32_vfp_dreg(CPUARMState *env, unsigned regno) 3262 { 3263 return &env->vfp.zregs[regno >> 1].d[regno & 1]; 3264 } 3265 3266 /** 3267 * aa32_vfp_qreg: 3268 * Return a pointer to the Qn register within env in 32-bit mode. 3269 */ 3270 static inline uint64_t *aa32_vfp_qreg(CPUARMState *env, unsigned regno) 3271 { 3272 return &env->vfp.zregs[regno].d[0]; 3273 } 3274 3275 /** 3276 * aa64_vfp_qreg: 3277 * Return a pointer to the Qn register within env in 64-bit mode. 3278 */ 3279 static inline uint64_t *aa64_vfp_qreg(CPUARMState *env, unsigned regno) 3280 { 3281 return &env->vfp.zregs[regno].d[0]; 3282 } 3283 3284 /* Shared between translate-sve.c and sve_helper.c. */ 3285 extern const uint64_t pred_esz_masks[4]; 3286 3287 /* 3288 * 32-bit feature tests via id registers. 3289 */ 3290 static inline bool isar_feature_thumb_div(const ARMISARegisters *id) 3291 { 3292 return FIELD_EX32(id->id_isar0, ID_ISAR0, DIVIDE) != 0; 3293 } 3294 3295 static inline bool isar_feature_arm_div(const ARMISARegisters *id) 3296 { 3297 return FIELD_EX32(id->id_isar0, ID_ISAR0, DIVIDE) > 1; 3298 } 3299 3300 static inline bool isar_feature_jazelle(const ARMISARegisters *id) 3301 { 3302 return FIELD_EX32(id->id_isar1, ID_ISAR1, JAZELLE) != 0; 3303 } 3304 3305 static inline bool isar_feature_aa32_aes(const ARMISARegisters *id) 3306 { 3307 return FIELD_EX32(id->id_isar5, ID_ISAR5, AES) != 0; 3308 } 3309 3310 static inline bool isar_feature_aa32_pmull(const ARMISARegisters *id) 3311 { 3312 return FIELD_EX32(id->id_isar5, ID_ISAR5, AES) > 1; 3313 } 3314 3315 static inline bool isar_feature_aa32_sha1(const ARMISARegisters *id) 3316 { 3317 return FIELD_EX32(id->id_isar5, ID_ISAR5, SHA1) != 0; 3318 } 3319 3320 static inline bool isar_feature_aa32_sha2(const ARMISARegisters *id) 3321 { 3322 return FIELD_EX32(id->id_isar5, ID_ISAR5, SHA2) != 0; 3323 } 3324 3325 static inline bool isar_feature_aa32_crc32(const ARMISARegisters *id) 3326 { 3327 return FIELD_EX32(id->id_isar5, ID_ISAR5, CRC32) != 0; 3328 } 3329 3330 static inline bool isar_feature_aa32_rdm(const ARMISARegisters *id) 3331 { 3332 return FIELD_EX32(id->id_isar5, ID_ISAR5, RDM) != 0; 3333 } 3334 3335 static inline bool isar_feature_aa32_vcma(const ARMISARegisters *id) 3336 { 3337 return FIELD_EX32(id->id_isar5, ID_ISAR5, VCMA) != 0; 3338 } 3339 3340 static inline bool isar_feature_aa32_jscvt(const ARMISARegisters *id) 3341 { 3342 return FIELD_EX32(id->id_isar6, ID_ISAR6, JSCVT) != 0; 3343 } 3344 3345 static inline bool isar_feature_aa32_dp(const ARMISARegisters *id) 3346 { 3347 return FIELD_EX32(id->id_isar6, ID_ISAR6, DP) != 0; 3348 } 3349 3350 static inline bool isar_feature_aa32_fhm(const ARMISARegisters *id) 3351 { 3352 return FIELD_EX32(id->id_isar6, ID_ISAR6, FHM) != 0; 3353 } 3354 3355 static inline bool isar_feature_aa32_sb(const ARMISARegisters *id) 3356 { 3357 return FIELD_EX32(id->id_isar6, ID_ISAR6, SB) != 0; 3358 } 3359 3360 static inline bool isar_feature_aa32_predinv(const ARMISARegisters *id) 3361 { 3362 return FIELD_EX32(id->id_isar6, ID_ISAR6, SPECRES) != 0; 3363 } 3364 3365 static inline bool isar_feature_aa32_fp16_arith(const ARMISARegisters *id) 3366 { 3367 /* 3368 * This is a placeholder for use by VCMA until the rest of 3369 * the ARMv8.2-FP16 extension is implemented for aa32 mode. 3370 * At which point we can properly set and check MVFR1.FPHP. 3371 */ 3372 return FIELD_EX64(id->id_aa64pfr0, ID_AA64PFR0, FP) == 1; 3373 } 3374 3375 /* 3376 * We always set the FP and SIMD FP16 fields to indicate identical 3377 * levels of support (assuming SIMD is implemented at all), so 3378 * we only need one set of accessors. 3379 */ 3380 static inline bool isar_feature_aa32_fp16_spconv(const ARMISARegisters *id) 3381 { 3382 return FIELD_EX64(id->mvfr1, MVFR1, FPHP) > 0; 3383 } 3384 3385 static inline bool isar_feature_aa32_fp16_dpconv(const ARMISARegisters *id) 3386 { 3387 return FIELD_EX64(id->mvfr1, MVFR1, FPHP) > 1; 3388 } 3389 3390 static inline bool isar_feature_aa32_vsel(const ARMISARegisters *id) 3391 { 3392 return FIELD_EX64(id->mvfr2, MVFR2, FPMISC) >= 1; 3393 } 3394 3395 static inline bool isar_feature_aa32_vcvt_dr(const ARMISARegisters *id) 3396 { 3397 return FIELD_EX64(id->mvfr2, MVFR2, FPMISC) >= 2; 3398 } 3399 3400 static inline bool isar_feature_aa32_vrint(const ARMISARegisters *id) 3401 { 3402 return FIELD_EX64(id->mvfr2, MVFR2, FPMISC) >= 3; 3403 } 3404 3405 static inline bool isar_feature_aa32_vminmaxnm(const ARMISARegisters *id) 3406 { 3407 return FIELD_EX64(id->mvfr2, MVFR2, FPMISC) >= 4; 3408 } 3409 3410 /* 3411 * 64-bit feature tests via id registers. 3412 */ 3413 static inline bool isar_feature_aa64_aes(const ARMISARegisters *id) 3414 { 3415 return FIELD_EX64(id->id_aa64isar0, ID_AA64ISAR0, AES) != 0; 3416 } 3417 3418 static inline bool isar_feature_aa64_pmull(const ARMISARegisters *id) 3419 { 3420 return FIELD_EX64(id->id_aa64isar0, ID_AA64ISAR0, AES) > 1; 3421 } 3422 3423 static inline bool isar_feature_aa64_sha1(const ARMISARegisters *id) 3424 { 3425 return FIELD_EX64(id->id_aa64isar0, ID_AA64ISAR0, SHA1) != 0; 3426 } 3427 3428 static inline bool isar_feature_aa64_sha256(const ARMISARegisters *id) 3429 { 3430 return FIELD_EX64(id->id_aa64isar0, ID_AA64ISAR0, SHA2) != 0; 3431 } 3432 3433 static inline bool isar_feature_aa64_sha512(const ARMISARegisters *id) 3434 { 3435 return FIELD_EX64(id->id_aa64isar0, ID_AA64ISAR0, SHA2) > 1; 3436 } 3437 3438 static inline bool isar_feature_aa64_crc32(const ARMISARegisters *id) 3439 { 3440 return FIELD_EX64(id->id_aa64isar0, ID_AA64ISAR0, CRC32) != 0; 3441 } 3442 3443 static inline bool isar_feature_aa64_atomics(const ARMISARegisters *id) 3444 { 3445 return FIELD_EX64(id->id_aa64isar0, ID_AA64ISAR0, ATOMIC) != 0; 3446 } 3447 3448 static inline bool isar_feature_aa64_rdm(const ARMISARegisters *id) 3449 { 3450 return FIELD_EX64(id->id_aa64isar0, ID_AA64ISAR0, RDM) != 0; 3451 } 3452 3453 static inline bool isar_feature_aa64_sha3(const ARMISARegisters *id) 3454 { 3455 return FIELD_EX64(id->id_aa64isar0, ID_AA64ISAR0, SHA3) != 0; 3456 } 3457 3458 static inline bool isar_feature_aa64_sm3(const ARMISARegisters *id) 3459 { 3460 return FIELD_EX64(id->id_aa64isar0, ID_AA64ISAR0, SM3) != 0; 3461 } 3462 3463 static inline bool isar_feature_aa64_sm4(const ARMISARegisters *id) 3464 { 3465 return FIELD_EX64(id->id_aa64isar0, ID_AA64ISAR0, SM4) != 0; 3466 } 3467 3468 static inline bool isar_feature_aa64_dp(const ARMISARegisters *id) 3469 { 3470 return FIELD_EX64(id->id_aa64isar0, ID_AA64ISAR0, DP) != 0; 3471 } 3472 3473 static inline bool isar_feature_aa64_fhm(const ARMISARegisters *id) 3474 { 3475 return FIELD_EX64(id->id_aa64isar0, ID_AA64ISAR0, FHM) != 0; 3476 } 3477 3478 static inline bool isar_feature_aa64_condm_4(const ARMISARegisters *id) 3479 { 3480 return FIELD_EX64(id->id_aa64isar0, ID_AA64ISAR0, TS) != 0; 3481 } 3482 3483 static inline bool isar_feature_aa64_condm_5(const ARMISARegisters *id) 3484 { 3485 return FIELD_EX64(id->id_aa64isar0, ID_AA64ISAR0, TS) >= 2; 3486 } 3487 3488 static inline bool isar_feature_aa64_rndr(const ARMISARegisters *id) 3489 { 3490 return FIELD_EX64(id->id_aa64isar0, ID_AA64ISAR0, RNDR) != 0; 3491 } 3492 3493 static inline bool isar_feature_aa64_jscvt(const ARMISARegisters *id) 3494 { 3495 return FIELD_EX64(id->id_aa64isar1, ID_AA64ISAR1, JSCVT) != 0; 3496 } 3497 3498 static inline bool isar_feature_aa64_fcma(const ARMISARegisters *id) 3499 { 3500 return FIELD_EX64(id->id_aa64isar1, ID_AA64ISAR1, FCMA) != 0; 3501 } 3502 3503 static inline bool isar_feature_aa64_pauth(const ARMISARegisters *id) 3504 { 3505 /* 3506 * Note that while QEMU will only implement the architected algorithm 3507 * QARMA, and thus APA+GPA, the host cpu for kvm may use implementation 3508 * defined algorithms, and thus API+GPI, and this predicate controls 3509 * migration of the 128-bit keys. 3510 */ 3511 return (id->id_aa64isar1 & 3512 (FIELD_DP64(0, ID_AA64ISAR1, APA, 0xf) | 3513 FIELD_DP64(0, ID_AA64ISAR1, API, 0xf) | 3514 FIELD_DP64(0, ID_AA64ISAR1, GPA, 0xf) | 3515 FIELD_DP64(0, ID_AA64ISAR1, GPI, 0xf))) != 0; 3516 } 3517 3518 static inline bool isar_feature_aa64_sb(const ARMISARegisters *id) 3519 { 3520 return FIELD_EX64(id->id_aa64isar1, ID_AA64ISAR1, SB) != 0; 3521 } 3522 3523 static inline bool isar_feature_aa64_predinv(const ARMISARegisters *id) 3524 { 3525 return FIELD_EX64(id->id_aa64isar1, ID_AA64ISAR1, SPECRES) != 0; 3526 } 3527 3528 static inline bool isar_feature_aa64_frint(const ARMISARegisters *id) 3529 { 3530 return FIELD_EX64(id->id_aa64isar1, ID_AA64ISAR1, FRINTTS) != 0; 3531 } 3532 3533 static inline bool isar_feature_aa64_fp16(const ARMISARegisters *id) 3534 { 3535 /* We always set the AdvSIMD and FP fields identically wrt FP16. */ 3536 return FIELD_EX64(id->id_aa64pfr0, ID_AA64PFR0, FP) == 1; 3537 } 3538 3539 static inline bool isar_feature_aa64_aa32(const ARMISARegisters *id) 3540 { 3541 return FIELD_EX64(id->id_aa64pfr0, ID_AA64PFR0, EL0) >= 2; 3542 } 3543 3544 static inline bool isar_feature_aa64_sve(const ARMISARegisters *id) 3545 { 3546 return FIELD_EX64(id->id_aa64pfr0, ID_AA64PFR0, SVE) != 0; 3547 } 3548 3549 static inline bool isar_feature_aa64_lor(const ARMISARegisters *id) 3550 { 3551 return FIELD_EX64(id->id_aa64mmfr1, ID_AA64MMFR1, LO) != 0; 3552 } 3553 3554 static inline bool isar_feature_aa64_bti(const ARMISARegisters *id) 3555 { 3556 return FIELD_EX64(id->id_aa64pfr1, ID_AA64PFR1, BT) != 0; 3557 } 3558 3559 /* 3560 * Forward to the above feature tests given an ARMCPU pointer. 3561 */ 3562 #define cpu_isar_feature(name, cpu) \ 3563 ({ ARMCPU *cpu_ = (cpu); isar_feature_##name(&cpu_->isar); }) 3564 3565 #endif 3566