1 /* 2 * ARM virtual CPU header 3 * 4 * Copyright (c) 2003 Fabrice Bellard 5 * 6 * This library is free software; you can redistribute it and/or 7 * modify it under the terms of the GNU Lesser General Public 8 * License as published by the Free Software Foundation; either 9 * version 2 of the License, or (at your option) any later version. 10 * 11 * This library is distributed in the hope that it will be useful, 12 * but WITHOUT ANY WARRANTY; without even the implied warranty of 13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU 14 * Lesser General Public License for more details. 15 * 16 * You should have received a copy of the GNU Lesser General Public 17 * License along with this library; if not, see <http://www.gnu.org/licenses/>. 18 */ 19 20 #ifndef ARM_CPU_H 21 #define ARM_CPU_H 22 23 #include "kvm-consts.h" 24 #include "hw/registerfields.h" 25 26 #if defined(TARGET_AARCH64) 27 /* AArch64 definitions */ 28 # define TARGET_LONG_BITS 64 29 #else 30 # define TARGET_LONG_BITS 32 31 #endif 32 33 /* ARM processors have a weak memory model */ 34 #define TCG_GUEST_DEFAULT_MO (0) 35 36 #define CPUArchState struct CPUARMState 37 38 #include "qemu-common.h" 39 #include "cpu-qom.h" 40 #include "exec/cpu-defs.h" 41 42 #include "fpu/softfloat.h" 43 44 #define EXCP_UDEF 1 /* undefined instruction */ 45 #define EXCP_SWI 2 /* software interrupt */ 46 #define EXCP_PREFETCH_ABORT 3 47 #define EXCP_DATA_ABORT 4 48 #define EXCP_IRQ 5 49 #define EXCP_FIQ 6 50 #define EXCP_BKPT 7 51 #define EXCP_EXCEPTION_EXIT 8 /* Return from v7M exception. */ 52 #define EXCP_KERNEL_TRAP 9 /* Jumped to kernel code page. */ 53 #define EXCP_HVC 11 /* HyperVisor Call */ 54 #define EXCP_HYP_TRAP 12 55 #define EXCP_SMC 13 /* Secure Monitor Call */ 56 #define EXCP_VIRQ 14 57 #define EXCP_VFIQ 15 58 #define EXCP_SEMIHOST 16 /* semihosting call */ 59 #define EXCP_NOCP 17 /* v7M NOCP UsageFault */ 60 #define EXCP_INVSTATE 18 /* v7M INVSTATE UsageFault */ 61 /* NB: add new EXCP_ defines to the array in arm_log_exception() too */ 62 63 #define ARMV7M_EXCP_RESET 1 64 #define ARMV7M_EXCP_NMI 2 65 #define ARMV7M_EXCP_HARD 3 66 #define ARMV7M_EXCP_MEM 4 67 #define ARMV7M_EXCP_BUS 5 68 #define ARMV7M_EXCP_USAGE 6 69 #define ARMV7M_EXCP_SECURE 7 70 #define ARMV7M_EXCP_SVC 11 71 #define ARMV7M_EXCP_DEBUG 12 72 #define ARMV7M_EXCP_PENDSV 14 73 #define ARMV7M_EXCP_SYSTICK 15 74 75 /* For M profile, some registers are banked secure vs non-secure; 76 * these are represented as a 2-element array where the first element 77 * is the non-secure copy and the second is the secure copy. 78 * When the CPU does not have implement the security extension then 79 * only the first element is used. 80 * This means that the copy for the current security state can be 81 * accessed via env->registerfield[env->v7m.secure] (whether the security 82 * extension is implemented or not). 83 */ 84 enum { 85 M_REG_NS = 0, 86 M_REG_S = 1, 87 M_REG_NUM_BANKS = 2, 88 }; 89 90 /* ARM-specific interrupt pending bits. */ 91 #define CPU_INTERRUPT_FIQ CPU_INTERRUPT_TGT_EXT_1 92 #define CPU_INTERRUPT_VIRQ CPU_INTERRUPT_TGT_EXT_2 93 #define CPU_INTERRUPT_VFIQ CPU_INTERRUPT_TGT_EXT_3 94 95 /* The usual mapping for an AArch64 system register to its AArch32 96 * counterpart is for the 32 bit world to have access to the lower 97 * half only (with writes leaving the upper half untouched). It's 98 * therefore useful to be able to pass TCG the offset of the least 99 * significant half of a uint64_t struct member. 100 */ 101 #ifdef HOST_WORDS_BIGENDIAN 102 #define offsetoflow32(S, M) (offsetof(S, M) + sizeof(uint32_t)) 103 #define offsetofhigh32(S, M) offsetof(S, M) 104 #else 105 #define offsetoflow32(S, M) offsetof(S, M) 106 #define offsetofhigh32(S, M) (offsetof(S, M) + sizeof(uint32_t)) 107 #endif 108 109 /* Meanings of the ARMCPU object's four inbound GPIO lines */ 110 #define ARM_CPU_IRQ 0 111 #define ARM_CPU_FIQ 1 112 #define ARM_CPU_VIRQ 2 113 #define ARM_CPU_VFIQ 3 114 115 #define NB_MMU_MODES 8 116 /* ARM-specific extra insn start words: 117 * 1: Conditional execution bits 118 * 2: Partial exception syndrome for data aborts 119 */ 120 #define TARGET_INSN_START_EXTRA_WORDS 2 121 122 /* The 2nd extra word holding syndrome info for data aborts does not use 123 * the upper 6 bits nor the lower 14 bits. We mask and shift it down to 124 * help the sleb128 encoder do a better job. 125 * When restoring the CPU state, we shift it back up. 126 */ 127 #define ARM_INSN_START_WORD2_MASK ((1 << 26) - 1) 128 #define ARM_INSN_START_WORD2_SHIFT 14 129 130 /* We currently assume float and double are IEEE single and double 131 precision respectively. 132 Doing runtime conversions is tricky because VFP registers may contain 133 integer values (eg. as the result of a FTOSI instruction). 134 s<2n> maps to the least significant half of d<n> 135 s<2n+1> maps to the most significant half of d<n> 136 */ 137 138 /* CPU state for each instance of a generic timer (in cp15 c14) */ 139 typedef struct ARMGenericTimer { 140 uint64_t cval; /* Timer CompareValue register */ 141 uint64_t ctl; /* Timer Control register */ 142 } ARMGenericTimer; 143 144 #define GTIMER_PHYS 0 145 #define GTIMER_VIRT 1 146 #define GTIMER_HYP 2 147 #define GTIMER_SEC 3 148 #define NUM_GTIMERS 4 149 150 typedef struct { 151 uint64_t raw_tcr; 152 uint32_t mask; 153 uint32_t base_mask; 154 } TCR; 155 156 typedef struct CPUARMState { 157 /* Regs for current mode. */ 158 uint32_t regs[16]; 159 160 /* 32/64 switch only happens when taking and returning from 161 * exceptions so the overlap semantics are taken care of then 162 * instead of having a complicated union. 163 */ 164 /* Regs for A64 mode. */ 165 uint64_t xregs[32]; 166 uint64_t pc; 167 /* PSTATE isn't an architectural register for ARMv8. However, it is 168 * convenient for us to assemble the underlying state into a 32 bit format 169 * identical to the architectural format used for the SPSR. (This is also 170 * what the Linux kernel's 'pstate' field in signal handlers and KVM's 171 * 'pstate' register are.) Of the PSTATE bits: 172 * NZCV are kept in the split out env->CF/VF/NF/ZF, (which have the same 173 * semantics as for AArch32, as described in the comments on each field) 174 * nRW (also known as M[4]) is kept, inverted, in env->aarch64 175 * DAIF (exception masks) are kept in env->daif 176 * all other bits are stored in their correct places in env->pstate 177 */ 178 uint32_t pstate; 179 uint32_t aarch64; /* 1 if CPU is in aarch64 state; inverse of PSTATE.nRW */ 180 181 /* Frequently accessed CPSR bits are stored separately for efficiency. 182 This contains all the other bits. Use cpsr_{read,write} to access 183 the whole CPSR. */ 184 uint32_t uncached_cpsr; 185 uint32_t spsr; 186 187 /* Banked registers. */ 188 uint64_t banked_spsr[8]; 189 uint32_t banked_r13[8]; 190 uint32_t banked_r14[8]; 191 192 /* These hold r8-r12. */ 193 uint32_t usr_regs[5]; 194 uint32_t fiq_regs[5]; 195 196 /* cpsr flag cache for faster execution */ 197 uint32_t CF; /* 0 or 1 */ 198 uint32_t VF; /* V is the bit 31. All other bits are undefined */ 199 uint32_t NF; /* N is bit 31. All other bits are undefined. */ 200 uint32_t ZF; /* Z set if zero. */ 201 uint32_t QF; /* 0 or 1 */ 202 uint32_t GE; /* cpsr[19:16] */ 203 uint32_t thumb; /* cpsr[5]. 0 = arm mode, 1 = thumb mode. */ 204 uint32_t condexec_bits; /* IT bits. cpsr[15:10,26:25]. */ 205 uint64_t daif; /* exception masks, in the bits they are in PSTATE */ 206 207 uint64_t elr_el[4]; /* AArch64 exception link regs */ 208 uint64_t sp_el[4]; /* AArch64 banked stack pointers */ 209 210 /* System control coprocessor (cp15) */ 211 struct { 212 uint32_t c0_cpuid; 213 union { /* Cache size selection */ 214 struct { 215 uint64_t _unused_csselr0; 216 uint64_t csselr_ns; 217 uint64_t _unused_csselr1; 218 uint64_t csselr_s; 219 }; 220 uint64_t csselr_el[4]; 221 }; 222 union { /* System control register. */ 223 struct { 224 uint64_t _unused_sctlr; 225 uint64_t sctlr_ns; 226 uint64_t hsctlr; 227 uint64_t sctlr_s; 228 }; 229 uint64_t sctlr_el[4]; 230 }; 231 uint64_t cpacr_el1; /* Architectural feature access control register */ 232 uint64_t cptr_el[4]; /* ARMv8 feature trap registers */ 233 uint32_t c1_xscaleauxcr; /* XScale auxiliary control register. */ 234 uint64_t sder; /* Secure debug enable register. */ 235 uint32_t nsacr; /* Non-secure access control register. */ 236 union { /* MMU translation table base 0. */ 237 struct { 238 uint64_t _unused_ttbr0_0; 239 uint64_t ttbr0_ns; 240 uint64_t _unused_ttbr0_1; 241 uint64_t ttbr0_s; 242 }; 243 uint64_t ttbr0_el[4]; 244 }; 245 union { /* MMU translation table base 1. */ 246 struct { 247 uint64_t _unused_ttbr1_0; 248 uint64_t ttbr1_ns; 249 uint64_t _unused_ttbr1_1; 250 uint64_t ttbr1_s; 251 }; 252 uint64_t ttbr1_el[4]; 253 }; 254 uint64_t vttbr_el2; /* Virtualization Translation Table Base. */ 255 /* MMU translation table base control. */ 256 TCR tcr_el[4]; 257 TCR vtcr_el2; /* Virtualization Translation Control. */ 258 uint32_t c2_data; /* MPU data cacheable bits. */ 259 uint32_t c2_insn; /* MPU instruction cacheable bits. */ 260 union { /* MMU domain access control register 261 * MPU write buffer control. 262 */ 263 struct { 264 uint64_t dacr_ns; 265 uint64_t dacr_s; 266 }; 267 struct { 268 uint64_t dacr32_el2; 269 }; 270 }; 271 uint32_t pmsav5_data_ap; /* PMSAv5 MPU data access permissions */ 272 uint32_t pmsav5_insn_ap; /* PMSAv5 MPU insn access permissions */ 273 uint64_t hcr_el2; /* Hypervisor configuration register */ 274 uint64_t scr_el3; /* Secure configuration register. */ 275 union { /* Fault status registers. */ 276 struct { 277 uint64_t ifsr_ns; 278 uint64_t ifsr_s; 279 }; 280 struct { 281 uint64_t ifsr32_el2; 282 }; 283 }; 284 union { 285 struct { 286 uint64_t _unused_dfsr; 287 uint64_t dfsr_ns; 288 uint64_t hsr; 289 uint64_t dfsr_s; 290 }; 291 uint64_t esr_el[4]; 292 }; 293 uint32_t c6_region[8]; /* MPU base/size registers. */ 294 union { /* Fault address registers. */ 295 struct { 296 uint64_t _unused_far0; 297 #ifdef HOST_WORDS_BIGENDIAN 298 uint32_t ifar_ns; 299 uint32_t dfar_ns; 300 uint32_t ifar_s; 301 uint32_t dfar_s; 302 #else 303 uint32_t dfar_ns; 304 uint32_t ifar_ns; 305 uint32_t dfar_s; 306 uint32_t ifar_s; 307 #endif 308 uint64_t _unused_far3; 309 }; 310 uint64_t far_el[4]; 311 }; 312 uint64_t hpfar_el2; 313 uint64_t hstr_el2; 314 union { /* Translation result. */ 315 struct { 316 uint64_t _unused_par_0; 317 uint64_t par_ns; 318 uint64_t _unused_par_1; 319 uint64_t par_s; 320 }; 321 uint64_t par_el[4]; 322 }; 323 324 uint32_t c9_insn; /* Cache lockdown registers. */ 325 uint32_t c9_data; 326 uint64_t c9_pmcr; /* performance monitor control register */ 327 uint64_t c9_pmcnten; /* perf monitor counter enables */ 328 uint32_t c9_pmovsr; /* perf monitor overflow status */ 329 uint32_t c9_pmuserenr; /* perf monitor user enable */ 330 uint64_t c9_pmselr; /* perf monitor counter selection register */ 331 uint64_t c9_pminten; /* perf monitor interrupt enables */ 332 union { /* Memory attribute redirection */ 333 struct { 334 #ifdef HOST_WORDS_BIGENDIAN 335 uint64_t _unused_mair_0; 336 uint32_t mair1_ns; 337 uint32_t mair0_ns; 338 uint64_t _unused_mair_1; 339 uint32_t mair1_s; 340 uint32_t mair0_s; 341 #else 342 uint64_t _unused_mair_0; 343 uint32_t mair0_ns; 344 uint32_t mair1_ns; 345 uint64_t _unused_mair_1; 346 uint32_t mair0_s; 347 uint32_t mair1_s; 348 #endif 349 }; 350 uint64_t mair_el[4]; 351 }; 352 union { /* vector base address register */ 353 struct { 354 uint64_t _unused_vbar; 355 uint64_t vbar_ns; 356 uint64_t hvbar; 357 uint64_t vbar_s; 358 }; 359 uint64_t vbar_el[4]; 360 }; 361 uint32_t mvbar; /* (monitor) vector base address register */ 362 struct { /* FCSE PID. */ 363 uint32_t fcseidr_ns; 364 uint32_t fcseidr_s; 365 }; 366 union { /* Context ID. */ 367 struct { 368 uint64_t _unused_contextidr_0; 369 uint64_t contextidr_ns; 370 uint64_t _unused_contextidr_1; 371 uint64_t contextidr_s; 372 }; 373 uint64_t contextidr_el[4]; 374 }; 375 union { /* User RW Thread register. */ 376 struct { 377 uint64_t tpidrurw_ns; 378 uint64_t tpidrprw_ns; 379 uint64_t htpidr; 380 uint64_t _tpidr_el3; 381 }; 382 uint64_t tpidr_el[4]; 383 }; 384 /* The secure banks of these registers don't map anywhere */ 385 uint64_t tpidrurw_s; 386 uint64_t tpidrprw_s; 387 uint64_t tpidruro_s; 388 389 union { /* User RO Thread register. */ 390 uint64_t tpidruro_ns; 391 uint64_t tpidrro_el[1]; 392 }; 393 uint64_t c14_cntfrq; /* Counter Frequency register */ 394 uint64_t c14_cntkctl; /* Timer Control register */ 395 uint32_t cnthctl_el2; /* Counter/Timer Hyp Control register */ 396 uint64_t cntvoff_el2; /* Counter Virtual Offset register */ 397 ARMGenericTimer c14_timer[NUM_GTIMERS]; 398 uint32_t c15_cpar; /* XScale Coprocessor Access Register */ 399 uint32_t c15_ticonfig; /* TI925T configuration byte. */ 400 uint32_t c15_i_max; /* Maximum D-cache dirty line index. */ 401 uint32_t c15_i_min; /* Minimum D-cache dirty line index. */ 402 uint32_t c15_threadid; /* TI debugger thread-ID. */ 403 uint32_t c15_config_base_address; /* SCU base address. */ 404 uint32_t c15_diagnostic; /* diagnostic register */ 405 uint32_t c15_power_diagnostic; 406 uint32_t c15_power_control; /* power control */ 407 uint64_t dbgbvr[16]; /* breakpoint value registers */ 408 uint64_t dbgbcr[16]; /* breakpoint control registers */ 409 uint64_t dbgwvr[16]; /* watchpoint value registers */ 410 uint64_t dbgwcr[16]; /* watchpoint control registers */ 411 uint64_t mdscr_el1; 412 uint64_t oslsr_el1; /* OS Lock Status */ 413 uint64_t mdcr_el2; 414 uint64_t mdcr_el3; 415 /* If the counter is enabled, this stores the last time the counter 416 * was reset. Otherwise it stores the counter value 417 */ 418 uint64_t c15_ccnt; 419 uint64_t pmccfiltr_el0; /* Performance Monitor Filter Register */ 420 uint64_t vpidr_el2; /* Virtualization Processor ID Register */ 421 uint64_t vmpidr_el2; /* Virtualization Multiprocessor ID Register */ 422 } cp15; 423 424 struct { 425 /* M profile has up to 4 stack pointers: 426 * a Main Stack Pointer and a Process Stack Pointer for each 427 * of the Secure and Non-Secure states. (If the CPU doesn't support 428 * the security extension then it has only two SPs.) 429 * In QEMU we always store the currently active SP in regs[13], 430 * and the non-active SP for the current security state in 431 * v7m.other_sp. The stack pointers for the inactive security state 432 * are stored in other_ss_msp and other_ss_psp. 433 * switch_v7m_security_state() is responsible for rearranging them 434 * when we change security state. 435 */ 436 uint32_t other_sp; 437 uint32_t other_ss_msp; 438 uint32_t other_ss_psp; 439 uint32_t vecbase[M_REG_NUM_BANKS]; 440 uint32_t basepri[M_REG_NUM_BANKS]; 441 uint32_t control[M_REG_NUM_BANKS]; 442 uint32_t ccr[M_REG_NUM_BANKS]; /* Configuration and Control */ 443 uint32_t cfsr[M_REG_NUM_BANKS]; /* Configurable Fault Status */ 444 uint32_t hfsr; /* HardFault Status */ 445 uint32_t dfsr; /* Debug Fault Status Register */ 446 uint32_t sfsr; /* Secure Fault Status Register */ 447 uint32_t mmfar[M_REG_NUM_BANKS]; /* MemManage Fault Address */ 448 uint32_t bfar; /* BusFault Address */ 449 uint32_t sfar; /* Secure Fault Address Register */ 450 unsigned mpu_ctrl[M_REG_NUM_BANKS]; /* MPU_CTRL */ 451 int exception; 452 uint32_t primask[M_REG_NUM_BANKS]; 453 uint32_t faultmask[M_REG_NUM_BANKS]; 454 uint32_t aircr; /* only holds r/w state if security extn implemented */ 455 uint32_t secure; /* Is CPU in Secure state? (not guest visible) */ 456 } v7m; 457 458 /* Information associated with an exception about to be taken: 459 * code which raises an exception must set cs->exception_index and 460 * the relevant parts of this structure; the cpu_do_interrupt function 461 * will then set the guest-visible registers as part of the exception 462 * entry process. 463 */ 464 struct { 465 uint32_t syndrome; /* AArch64 format syndrome register */ 466 uint32_t fsr; /* AArch32 format fault status register info */ 467 uint64_t vaddress; /* virtual addr associated with exception, if any */ 468 uint32_t target_el; /* EL the exception should be targeted for */ 469 /* If we implement EL2 we will also need to store information 470 * about the intermediate physical address for stage 2 faults. 471 */ 472 } exception; 473 474 /* Thumb-2 EE state. */ 475 uint32_t teecr; 476 uint32_t teehbr; 477 478 /* VFP coprocessor state. */ 479 struct { 480 /* VFP/Neon register state. Note that the mapping between S, D and Q 481 * views of the register bank differs between AArch64 and AArch32: 482 * In AArch32: 483 * Qn = regs[2n+1]:regs[2n] 484 * Dn = regs[n] 485 * Sn = regs[n/2] bits 31..0 for even n, and bits 63..32 for odd n 486 * (and regs[32] to regs[63] are inaccessible) 487 * In AArch64: 488 * Qn = regs[2n+1]:regs[2n] 489 * Dn = regs[2n] 490 * Sn = regs[2n] bits 31..0 491 * This corresponds to the architecturally defined mapping between 492 * the two execution states, and means we do not need to explicitly 493 * map these registers when changing states. 494 */ 495 uint64_t regs[64] QEMU_ALIGNED(16); 496 497 uint32_t xregs[16]; 498 /* We store these fpcsr fields separately for convenience. */ 499 int vec_len; 500 int vec_stride; 501 502 /* scratch space when Tn are not sufficient. */ 503 uint32_t scratch[8]; 504 505 /* fp_status is the "normal" fp status. standard_fp_status retains 506 * values corresponding to the ARM "Standard FPSCR Value", ie 507 * default-NaN, flush-to-zero, round-to-nearest and is used by 508 * any operations (generally Neon) which the architecture defines 509 * as controlled by the standard FPSCR value rather than the FPSCR. 510 * 511 * To avoid having to transfer exception bits around, we simply 512 * say that the FPSCR cumulative exception flags are the logical 513 * OR of the flags in the two fp statuses. This relies on the 514 * only thing which needs to read the exception flags being 515 * an explicit FPSCR read. 516 */ 517 float_status fp_status; 518 float_status standard_fp_status; 519 } vfp; 520 uint64_t exclusive_addr; 521 uint64_t exclusive_val; 522 uint64_t exclusive_high; 523 524 /* iwMMXt coprocessor state. */ 525 struct { 526 uint64_t regs[16]; 527 uint64_t val; 528 529 uint32_t cregs[16]; 530 } iwmmxt; 531 532 #if defined(CONFIG_USER_ONLY) 533 /* For usermode syscall translation. */ 534 int eabi; 535 #endif 536 537 struct CPUBreakpoint *cpu_breakpoint[16]; 538 struct CPUWatchpoint *cpu_watchpoint[16]; 539 540 /* Fields up to this point are cleared by a CPU reset */ 541 struct {} end_reset_fields; 542 543 CPU_COMMON 544 545 /* Fields after CPU_COMMON are preserved across CPU reset. */ 546 547 /* Internal CPU feature flags. */ 548 uint64_t features; 549 550 /* PMSAv7 MPU */ 551 struct { 552 uint32_t *drbar; 553 uint32_t *drsr; 554 uint32_t *dracr; 555 uint32_t rnr[M_REG_NUM_BANKS]; 556 } pmsav7; 557 558 /* PMSAv8 MPU */ 559 struct { 560 /* The PMSAv8 implementation also shares some PMSAv7 config 561 * and state: 562 * pmsav7.rnr (region number register) 563 * pmsav7_dregion (number of configured regions) 564 */ 565 uint32_t *rbar[M_REG_NUM_BANKS]; 566 uint32_t *rlar[M_REG_NUM_BANKS]; 567 uint32_t mair0[M_REG_NUM_BANKS]; 568 uint32_t mair1[M_REG_NUM_BANKS]; 569 } pmsav8; 570 571 /* v8M SAU */ 572 struct { 573 uint32_t *rbar; 574 uint32_t *rlar; 575 uint32_t rnr; 576 uint32_t ctrl; 577 } sau; 578 579 void *nvic; 580 const struct arm_boot_info *boot_info; 581 /* Store GICv3CPUState to access from this struct */ 582 void *gicv3state; 583 } CPUARMState; 584 585 /** 586 * ARMELChangeHook: 587 * type of a function which can be registered via arm_register_el_change_hook() 588 * to get callbacks when the CPU changes its exception level or mode. 589 */ 590 typedef void ARMELChangeHook(ARMCPU *cpu, void *opaque); 591 592 593 /* These values map onto the return values for 594 * QEMU_PSCI_0_2_FN_AFFINITY_INFO */ 595 typedef enum ARMPSCIState { 596 PSCI_ON = 0, 597 PSCI_OFF = 1, 598 PSCI_ON_PENDING = 2 599 } ARMPSCIState; 600 601 /** 602 * ARMCPU: 603 * @env: #CPUARMState 604 * 605 * An ARM CPU core. 606 */ 607 struct ARMCPU { 608 /*< private >*/ 609 CPUState parent_obj; 610 /*< public >*/ 611 612 CPUARMState env; 613 614 /* Coprocessor information */ 615 GHashTable *cp_regs; 616 /* For marshalling (mostly coprocessor) register state between the 617 * kernel and QEMU (for KVM) and between two QEMUs (for migration), 618 * we use these arrays. 619 */ 620 /* List of register indexes managed via these arrays; (full KVM style 621 * 64 bit indexes, not CPRegInfo 32 bit indexes) 622 */ 623 uint64_t *cpreg_indexes; 624 /* Values of the registers (cpreg_indexes[i]'s value is cpreg_values[i]) */ 625 uint64_t *cpreg_values; 626 /* Length of the indexes, values, reset_values arrays */ 627 int32_t cpreg_array_len; 628 /* These are used only for migration: incoming data arrives in 629 * these fields and is sanity checked in post_load before copying 630 * to the working data structures above. 631 */ 632 uint64_t *cpreg_vmstate_indexes; 633 uint64_t *cpreg_vmstate_values; 634 int32_t cpreg_vmstate_array_len; 635 636 /* Timers used by the generic (architected) timer */ 637 QEMUTimer *gt_timer[NUM_GTIMERS]; 638 /* GPIO outputs for generic timer */ 639 qemu_irq gt_timer_outputs[NUM_GTIMERS]; 640 /* GPIO output for GICv3 maintenance interrupt signal */ 641 qemu_irq gicv3_maintenance_interrupt; 642 /* GPIO output for the PMU interrupt */ 643 qemu_irq pmu_interrupt; 644 645 /* MemoryRegion to use for secure physical accesses */ 646 MemoryRegion *secure_memory; 647 648 /* 'compatible' string for this CPU for Linux device trees */ 649 const char *dtb_compatible; 650 651 /* PSCI version for this CPU 652 * Bits[31:16] = Major Version 653 * Bits[15:0] = Minor Version 654 */ 655 uint32_t psci_version; 656 657 /* Should CPU start in PSCI powered-off state? */ 658 bool start_powered_off; 659 660 /* Current power state, access guarded by BQL */ 661 ARMPSCIState power_state; 662 663 /* CPU has virtualization extension */ 664 bool has_el2; 665 /* CPU has security extension */ 666 bool has_el3; 667 /* CPU has PMU (Performance Monitor Unit) */ 668 bool has_pmu; 669 670 /* CPU has memory protection unit */ 671 bool has_mpu; 672 /* PMSAv7 MPU number of supported regions */ 673 uint32_t pmsav7_dregion; 674 /* v8M SAU number of supported regions */ 675 uint32_t sau_sregion; 676 677 /* PSCI conduit used to invoke PSCI methods 678 * 0 - disabled, 1 - smc, 2 - hvc 679 */ 680 uint32_t psci_conduit; 681 682 /* [QEMU_]KVM_ARM_TARGET_* constant for this CPU, or 683 * QEMU_KVM_ARM_TARGET_NONE if the kernel doesn't support this CPU type. 684 */ 685 uint32_t kvm_target; 686 687 /* KVM init features for this CPU */ 688 uint32_t kvm_init_features[7]; 689 690 /* Uniprocessor system with MP extensions */ 691 bool mp_is_up; 692 693 /* The instance init functions for implementation-specific subclasses 694 * set these fields to specify the implementation-dependent values of 695 * various constant registers and reset values of non-constant 696 * registers. 697 * Some of these might become QOM properties eventually. 698 * Field names match the official register names as defined in the 699 * ARMv7AR ARM Architecture Reference Manual. A reset_ prefix 700 * is used for reset values of non-constant registers; no reset_ 701 * prefix means a constant register. 702 */ 703 uint32_t midr; 704 uint32_t revidr; 705 uint32_t reset_fpsid; 706 uint32_t mvfr0; 707 uint32_t mvfr1; 708 uint32_t mvfr2; 709 uint32_t ctr; 710 uint32_t reset_sctlr; 711 uint32_t id_pfr0; 712 uint32_t id_pfr1; 713 uint32_t id_dfr0; 714 uint32_t pmceid0; 715 uint32_t pmceid1; 716 uint32_t id_afr0; 717 uint32_t id_mmfr0; 718 uint32_t id_mmfr1; 719 uint32_t id_mmfr2; 720 uint32_t id_mmfr3; 721 uint32_t id_mmfr4; 722 uint32_t id_isar0; 723 uint32_t id_isar1; 724 uint32_t id_isar2; 725 uint32_t id_isar3; 726 uint32_t id_isar4; 727 uint32_t id_isar5; 728 uint64_t id_aa64pfr0; 729 uint64_t id_aa64pfr1; 730 uint64_t id_aa64dfr0; 731 uint64_t id_aa64dfr1; 732 uint64_t id_aa64afr0; 733 uint64_t id_aa64afr1; 734 uint64_t id_aa64isar0; 735 uint64_t id_aa64isar1; 736 uint64_t id_aa64mmfr0; 737 uint64_t id_aa64mmfr1; 738 uint32_t dbgdidr; 739 uint32_t clidr; 740 uint64_t mp_affinity; /* MP ID without feature bits */ 741 /* The elements of this array are the CCSIDR values for each cache, 742 * in the order L1DCache, L1ICache, L2DCache, L2ICache, etc. 743 */ 744 uint32_t ccsidr[16]; 745 uint64_t reset_cbar; 746 uint32_t reset_auxcr; 747 bool reset_hivecs; 748 /* DCZ blocksize, in log_2(words), ie low 4 bits of DCZID_EL0 */ 749 uint32_t dcz_blocksize; 750 uint64_t rvbar; 751 752 /* Configurable aspects of GIC cpu interface (which is part of the CPU) */ 753 int gic_num_lrs; /* number of list registers */ 754 int gic_vpribits; /* number of virtual priority bits */ 755 int gic_vprebits; /* number of virtual preemption bits */ 756 757 /* Whether the cfgend input is high (i.e. this CPU should reset into 758 * big-endian mode). This setting isn't used directly: instead it modifies 759 * the reset_sctlr value to have SCTLR_B or SCTLR_EE set, depending on the 760 * architecture version. 761 */ 762 bool cfgend; 763 764 ARMELChangeHook *el_change_hook; 765 void *el_change_hook_opaque; 766 767 int32_t node_id; /* NUMA node this CPU belongs to */ 768 769 /* Used to synchronize KVM and QEMU in-kernel device levels */ 770 uint8_t device_irq_level; 771 }; 772 773 static inline ARMCPU *arm_env_get_cpu(CPUARMState *env) 774 { 775 return container_of(env, ARMCPU, env); 776 } 777 778 uint64_t arm_cpu_mp_affinity(int idx, uint8_t clustersz); 779 780 #define ENV_GET_CPU(e) CPU(arm_env_get_cpu(e)) 781 782 #define ENV_OFFSET offsetof(ARMCPU, env) 783 784 #ifndef CONFIG_USER_ONLY 785 extern const struct VMStateDescription vmstate_arm_cpu; 786 #endif 787 788 void arm_cpu_do_interrupt(CPUState *cpu); 789 void arm_v7m_cpu_do_interrupt(CPUState *cpu); 790 bool arm_cpu_exec_interrupt(CPUState *cpu, int int_req); 791 792 void arm_cpu_dump_state(CPUState *cs, FILE *f, fprintf_function cpu_fprintf, 793 int flags); 794 795 hwaddr arm_cpu_get_phys_page_attrs_debug(CPUState *cpu, vaddr addr, 796 MemTxAttrs *attrs); 797 798 int arm_cpu_gdb_read_register(CPUState *cpu, uint8_t *buf, int reg); 799 int arm_cpu_gdb_write_register(CPUState *cpu, uint8_t *buf, int reg); 800 801 int arm_cpu_write_elf64_note(WriteCoreDumpFunction f, CPUState *cs, 802 int cpuid, void *opaque); 803 int arm_cpu_write_elf32_note(WriteCoreDumpFunction f, CPUState *cs, 804 int cpuid, void *opaque); 805 806 #ifdef TARGET_AARCH64 807 int aarch64_cpu_gdb_read_register(CPUState *cpu, uint8_t *buf, int reg); 808 int aarch64_cpu_gdb_write_register(CPUState *cpu, uint8_t *buf, int reg); 809 #endif 810 811 target_ulong do_arm_semihosting(CPUARMState *env); 812 void aarch64_sync_32_to_64(CPUARMState *env); 813 void aarch64_sync_64_to_32(CPUARMState *env); 814 815 static inline bool is_a64(CPUARMState *env) 816 { 817 return env->aarch64; 818 } 819 820 /* you can call this signal handler from your SIGBUS and SIGSEGV 821 signal handlers to inform the virtual CPU of exceptions. non zero 822 is returned if the signal was handled by the virtual CPU. */ 823 int cpu_arm_signal_handler(int host_signum, void *pinfo, 824 void *puc); 825 826 /** 827 * pmccntr_sync 828 * @env: CPUARMState 829 * 830 * Synchronises the counter in the PMCCNTR. This must always be called twice, 831 * once before any action that might affect the timer and again afterwards. 832 * The function is used to swap the state of the register if required. 833 * This only happens when not in user mode (!CONFIG_USER_ONLY) 834 */ 835 void pmccntr_sync(CPUARMState *env); 836 837 /* SCTLR bit meanings. Several bits have been reused in newer 838 * versions of the architecture; in that case we define constants 839 * for both old and new bit meanings. Code which tests against those 840 * bits should probably check or otherwise arrange that the CPU 841 * is the architectural version it expects. 842 */ 843 #define SCTLR_M (1U << 0) 844 #define SCTLR_A (1U << 1) 845 #define SCTLR_C (1U << 2) 846 #define SCTLR_W (1U << 3) /* up to v6; RAO in v7 */ 847 #define SCTLR_SA (1U << 3) 848 #define SCTLR_P (1U << 4) /* up to v5; RAO in v6 and v7 */ 849 #define SCTLR_SA0 (1U << 4) /* v8 onward, AArch64 only */ 850 #define SCTLR_D (1U << 5) /* up to v5; RAO in v6 */ 851 #define SCTLR_CP15BEN (1U << 5) /* v7 onward */ 852 #define SCTLR_L (1U << 6) /* up to v5; RAO in v6 and v7; RAZ in v8 */ 853 #define SCTLR_B (1U << 7) /* up to v6; RAZ in v7 */ 854 #define SCTLR_ITD (1U << 7) /* v8 onward */ 855 #define SCTLR_S (1U << 8) /* up to v6; RAZ in v7 */ 856 #define SCTLR_SED (1U << 8) /* v8 onward */ 857 #define SCTLR_R (1U << 9) /* up to v6; RAZ in v7 */ 858 #define SCTLR_UMA (1U << 9) /* v8 onward, AArch64 only */ 859 #define SCTLR_F (1U << 10) /* up to v6 */ 860 #define SCTLR_SW (1U << 10) /* v7 onward */ 861 #define SCTLR_Z (1U << 11) 862 #define SCTLR_I (1U << 12) 863 #define SCTLR_V (1U << 13) 864 #define SCTLR_RR (1U << 14) /* up to v7 */ 865 #define SCTLR_DZE (1U << 14) /* v8 onward, AArch64 only */ 866 #define SCTLR_L4 (1U << 15) /* up to v6; RAZ in v7 */ 867 #define SCTLR_UCT (1U << 15) /* v8 onward, AArch64 only */ 868 #define SCTLR_DT (1U << 16) /* up to ??, RAO in v6 and v7 */ 869 #define SCTLR_nTWI (1U << 16) /* v8 onward */ 870 #define SCTLR_HA (1U << 17) 871 #define SCTLR_BR (1U << 17) /* PMSA only */ 872 #define SCTLR_IT (1U << 18) /* up to ??, RAO in v6 and v7 */ 873 #define SCTLR_nTWE (1U << 18) /* v8 onward */ 874 #define SCTLR_WXN (1U << 19) 875 #define SCTLR_ST (1U << 20) /* up to ??, RAZ in v6 */ 876 #define SCTLR_UWXN (1U << 20) /* v7 onward */ 877 #define SCTLR_FI (1U << 21) 878 #define SCTLR_U (1U << 22) 879 #define SCTLR_XP (1U << 23) /* up to v6; v7 onward RAO */ 880 #define SCTLR_VE (1U << 24) /* up to v7 */ 881 #define SCTLR_E0E (1U << 24) /* v8 onward, AArch64 only */ 882 #define SCTLR_EE (1U << 25) 883 #define SCTLR_L2 (1U << 26) /* up to v6, RAZ in v7 */ 884 #define SCTLR_UCI (1U << 26) /* v8 onward, AArch64 only */ 885 #define SCTLR_NMFI (1U << 27) 886 #define SCTLR_TRE (1U << 28) 887 #define SCTLR_AFE (1U << 29) 888 #define SCTLR_TE (1U << 30) 889 890 #define CPTR_TCPAC (1U << 31) 891 #define CPTR_TTA (1U << 20) 892 #define CPTR_TFP (1U << 10) 893 894 #define MDCR_EPMAD (1U << 21) 895 #define MDCR_EDAD (1U << 20) 896 #define MDCR_SPME (1U << 17) 897 #define MDCR_SDD (1U << 16) 898 #define MDCR_SPD (3U << 14) 899 #define MDCR_TDRA (1U << 11) 900 #define MDCR_TDOSA (1U << 10) 901 #define MDCR_TDA (1U << 9) 902 #define MDCR_TDE (1U << 8) 903 #define MDCR_HPME (1U << 7) 904 #define MDCR_TPM (1U << 6) 905 #define MDCR_TPMCR (1U << 5) 906 907 /* Not all of the MDCR_EL3 bits are present in the 32-bit SDCR */ 908 #define SDCR_VALID_MASK (MDCR_EPMAD | MDCR_EDAD | MDCR_SPME | MDCR_SPD) 909 910 #define CPSR_M (0x1fU) 911 #define CPSR_T (1U << 5) 912 #define CPSR_F (1U << 6) 913 #define CPSR_I (1U << 7) 914 #define CPSR_A (1U << 8) 915 #define CPSR_E (1U << 9) 916 #define CPSR_IT_2_7 (0xfc00U) 917 #define CPSR_GE (0xfU << 16) 918 #define CPSR_IL (1U << 20) 919 /* Note that the RESERVED bits include bit 21, which is PSTATE_SS in 920 * an AArch64 SPSR but RES0 in AArch32 SPSR and CPSR. In QEMU we use 921 * env->uncached_cpsr bit 21 to store PSTATE.SS when executing in AArch32, 922 * where it is live state but not accessible to the AArch32 code. 923 */ 924 #define CPSR_RESERVED (0x7U << 21) 925 #define CPSR_J (1U << 24) 926 #define CPSR_IT_0_1 (3U << 25) 927 #define CPSR_Q (1U << 27) 928 #define CPSR_V (1U << 28) 929 #define CPSR_C (1U << 29) 930 #define CPSR_Z (1U << 30) 931 #define CPSR_N (1U << 31) 932 #define CPSR_NZCV (CPSR_N | CPSR_Z | CPSR_C | CPSR_V) 933 #define CPSR_AIF (CPSR_A | CPSR_I | CPSR_F) 934 935 #define CPSR_IT (CPSR_IT_0_1 | CPSR_IT_2_7) 936 #define CACHED_CPSR_BITS (CPSR_T | CPSR_AIF | CPSR_GE | CPSR_IT | CPSR_Q \ 937 | CPSR_NZCV) 938 /* Bits writable in user mode. */ 939 #define CPSR_USER (CPSR_NZCV | CPSR_Q | CPSR_GE) 940 /* Execution state bits. MRS read as zero, MSR writes ignored. */ 941 #define CPSR_EXEC (CPSR_T | CPSR_IT | CPSR_J | CPSR_IL) 942 /* Mask of bits which may be set by exception return copying them from SPSR */ 943 #define CPSR_ERET_MASK (~CPSR_RESERVED) 944 945 /* Bit definitions for M profile XPSR. Most are the same as CPSR. */ 946 #define XPSR_EXCP 0x1ffU 947 #define XPSR_SPREALIGN (1U << 9) /* Only set in exception stack frames */ 948 #define XPSR_IT_2_7 CPSR_IT_2_7 949 #define XPSR_GE CPSR_GE 950 #define XPSR_SFPA (1U << 20) /* Only set in exception stack frames */ 951 #define XPSR_T (1U << 24) /* Not the same as CPSR_T ! */ 952 #define XPSR_IT_0_1 CPSR_IT_0_1 953 #define XPSR_Q CPSR_Q 954 #define XPSR_V CPSR_V 955 #define XPSR_C CPSR_C 956 #define XPSR_Z CPSR_Z 957 #define XPSR_N CPSR_N 958 #define XPSR_NZCV CPSR_NZCV 959 #define XPSR_IT CPSR_IT 960 961 #define TTBCR_N (7U << 0) /* TTBCR.EAE==0 */ 962 #define TTBCR_T0SZ (7U << 0) /* TTBCR.EAE==1 */ 963 #define TTBCR_PD0 (1U << 4) 964 #define TTBCR_PD1 (1U << 5) 965 #define TTBCR_EPD0 (1U << 7) 966 #define TTBCR_IRGN0 (3U << 8) 967 #define TTBCR_ORGN0 (3U << 10) 968 #define TTBCR_SH0 (3U << 12) 969 #define TTBCR_T1SZ (3U << 16) 970 #define TTBCR_A1 (1U << 22) 971 #define TTBCR_EPD1 (1U << 23) 972 #define TTBCR_IRGN1 (3U << 24) 973 #define TTBCR_ORGN1 (3U << 26) 974 #define TTBCR_SH1 (1U << 28) 975 #define TTBCR_EAE (1U << 31) 976 977 /* Bit definitions for ARMv8 SPSR (PSTATE) format. 978 * Only these are valid when in AArch64 mode; in 979 * AArch32 mode SPSRs are basically CPSR-format. 980 */ 981 #define PSTATE_SP (1U) 982 #define PSTATE_M (0xFU) 983 #define PSTATE_nRW (1U << 4) 984 #define PSTATE_F (1U << 6) 985 #define PSTATE_I (1U << 7) 986 #define PSTATE_A (1U << 8) 987 #define PSTATE_D (1U << 9) 988 #define PSTATE_IL (1U << 20) 989 #define PSTATE_SS (1U << 21) 990 #define PSTATE_V (1U << 28) 991 #define PSTATE_C (1U << 29) 992 #define PSTATE_Z (1U << 30) 993 #define PSTATE_N (1U << 31) 994 #define PSTATE_NZCV (PSTATE_N | PSTATE_Z | PSTATE_C | PSTATE_V) 995 #define PSTATE_DAIF (PSTATE_D | PSTATE_A | PSTATE_I | PSTATE_F) 996 #define CACHED_PSTATE_BITS (PSTATE_NZCV | PSTATE_DAIF) 997 /* Mode values for AArch64 */ 998 #define PSTATE_MODE_EL3h 13 999 #define PSTATE_MODE_EL3t 12 1000 #define PSTATE_MODE_EL2h 9 1001 #define PSTATE_MODE_EL2t 8 1002 #define PSTATE_MODE_EL1h 5 1003 #define PSTATE_MODE_EL1t 4 1004 #define PSTATE_MODE_EL0t 0 1005 1006 /* Write a new value to v7m.exception, thus transitioning into or out 1007 * of Handler mode; this may result in a change of active stack pointer. 1008 */ 1009 void write_v7m_exception(CPUARMState *env, uint32_t new_exc); 1010 1011 /* Map EL and handler into a PSTATE_MODE. */ 1012 static inline unsigned int aarch64_pstate_mode(unsigned int el, bool handler) 1013 { 1014 return (el << 2) | handler; 1015 } 1016 1017 /* Return the current PSTATE value. For the moment we don't support 32<->64 bit 1018 * interprocessing, so we don't attempt to sync with the cpsr state used by 1019 * the 32 bit decoder. 1020 */ 1021 static inline uint32_t pstate_read(CPUARMState *env) 1022 { 1023 int ZF; 1024 1025 ZF = (env->ZF == 0); 1026 return (env->NF & 0x80000000) | (ZF << 30) 1027 | (env->CF << 29) | ((env->VF & 0x80000000) >> 3) 1028 | env->pstate | env->daif; 1029 } 1030 1031 static inline void pstate_write(CPUARMState *env, uint32_t val) 1032 { 1033 env->ZF = (~val) & PSTATE_Z; 1034 env->NF = val; 1035 env->CF = (val >> 29) & 1; 1036 env->VF = (val << 3) & 0x80000000; 1037 env->daif = val & PSTATE_DAIF; 1038 env->pstate = val & ~CACHED_PSTATE_BITS; 1039 } 1040 1041 /* Return the current CPSR value. */ 1042 uint32_t cpsr_read(CPUARMState *env); 1043 1044 typedef enum CPSRWriteType { 1045 CPSRWriteByInstr = 0, /* from guest MSR or CPS */ 1046 CPSRWriteExceptionReturn = 1, /* from guest exception return insn */ 1047 CPSRWriteRaw = 2, /* trust values, do not switch reg banks */ 1048 CPSRWriteByGDBStub = 3, /* from the GDB stub */ 1049 } CPSRWriteType; 1050 1051 /* Set the CPSR. Note that some bits of mask must be all-set or all-clear.*/ 1052 void cpsr_write(CPUARMState *env, uint32_t val, uint32_t mask, 1053 CPSRWriteType write_type); 1054 1055 /* Return the current xPSR value. */ 1056 static inline uint32_t xpsr_read(CPUARMState *env) 1057 { 1058 int ZF; 1059 ZF = (env->ZF == 0); 1060 return (env->NF & 0x80000000) | (ZF << 30) 1061 | (env->CF << 29) | ((env->VF & 0x80000000) >> 3) | (env->QF << 27) 1062 | (env->thumb << 24) | ((env->condexec_bits & 3) << 25) 1063 | ((env->condexec_bits & 0xfc) << 8) 1064 | env->v7m.exception; 1065 } 1066 1067 /* Set the xPSR. Note that some bits of mask must be all-set or all-clear. */ 1068 static inline void xpsr_write(CPUARMState *env, uint32_t val, uint32_t mask) 1069 { 1070 if (mask & XPSR_NZCV) { 1071 env->ZF = (~val) & XPSR_Z; 1072 env->NF = val; 1073 env->CF = (val >> 29) & 1; 1074 env->VF = (val << 3) & 0x80000000; 1075 } 1076 if (mask & XPSR_Q) { 1077 env->QF = ((val & XPSR_Q) != 0); 1078 } 1079 if (mask & XPSR_T) { 1080 env->thumb = ((val & XPSR_T) != 0); 1081 } 1082 if (mask & XPSR_IT_0_1) { 1083 env->condexec_bits &= ~3; 1084 env->condexec_bits |= (val >> 25) & 3; 1085 } 1086 if (mask & XPSR_IT_2_7) { 1087 env->condexec_bits &= 3; 1088 env->condexec_bits |= (val >> 8) & 0xfc; 1089 } 1090 if (mask & XPSR_EXCP) { 1091 /* Note that this only happens on exception exit */ 1092 write_v7m_exception(env, val & XPSR_EXCP); 1093 } 1094 } 1095 1096 #define HCR_VM (1ULL << 0) 1097 #define HCR_SWIO (1ULL << 1) 1098 #define HCR_PTW (1ULL << 2) 1099 #define HCR_FMO (1ULL << 3) 1100 #define HCR_IMO (1ULL << 4) 1101 #define HCR_AMO (1ULL << 5) 1102 #define HCR_VF (1ULL << 6) 1103 #define HCR_VI (1ULL << 7) 1104 #define HCR_VSE (1ULL << 8) 1105 #define HCR_FB (1ULL << 9) 1106 #define HCR_BSU_MASK (3ULL << 10) 1107 #define HCR_DC (1ULL << 12) 1108 #define HCR_TWI (1ULL << 13) 1109 #define HCR_TWE (1ULL << 14) 1110 #define HCR_TID0 (1ULL << 15) 1111 #define HCR_TID1 (1ULL << 16) 1112 #define HCR_TID2 (1ULL << 17) 1113 #define HCR_TID3 (1ULL << 18) 1114 #define HCR_TSC (1ULL << 19) 1115 #define HCR_TIDCP (1ULL << 20) 1116 #define HCR_TACR (1ULL << 21) 1117 #define HCR_TSW (1ULL << 22) 1118 #define HCR_TPC (1ULL << 23) 1119 #define HCR_TPU (1ULL << 24) 1120 #define HCR_TTLB (1ULL << 25) 1121 #define HCR_TVM (1ULL << 26) 1122 #define HCR_TGE (1ULL << 27) 1123 #define HCR_TDZ (1ULL << 28) 1124 #define HCR_HCD (1ULL << 29) 1125 #define HCR_TRVM (1ULL << 30) 1126 #define HCR_RW (1ULL << 31) 1127 #define HCR_CD (1ULL << 32) 1128 #define HCR_ID (1ULL << 33) 1129 #define HCR_MASK ((1ULL << 34) - 1) 1130 1131 #define SCR_NS (1U << 0) 1132 #define SCR_IRQ (1U << 1) 1133 #define SCR_FIQ (1U << 2) 1134 #define SCR_EA (1U << 3) 1135 #define SCR_FW (1U << 4) 1136 #define SCR_AW (1U << 5) 1137 #define SCR_NET (1U << 6) 1138 #define SCR_SMD (1U << 7) 1139 #define SCR_HCE (1U << 8) 1140 #define SCR_SIF (1U << 9) 1141 #define SCR_RW (1U << 10) 1142 #define SCR_ST (1U << 11) 1143 #define SCR_TWI (1U << 12) 1144 #define SCR_TWE (1U << 13) 1145 #define SCR_AARCH32_MASK (0x3fff & ~(SCR_RW | SCR_ST)) 1146 #define SCR_AARCH64_MASK (0x3fff & ~SCR_NET) 1147 1148 /* Return the current FPSCR value. */ 1149 uint32_t vfp_get_fpscr(CPUARMState *env); 1150 void vfp_set_fpscr(CPUARMState *env, uint32_t val); 1151 1152 /* For A64 the FPSCR is split into two logically distinct registers, 1153 * FPCR and FPSR. However since they still use non-overlapping bits 1154 * we store the underlying state in fpscr and just mask on read/write. 1155 */ 1156 #define FPSR_MASK 0xf800009f 1157 #define FPCR_MASK 0x07f79f00 1158 static inline uint32_t vfp_get_fpsr(CPUARMState *env) 1159 { 1160 return vfp_get_fpscr(env) & FPSR_MASK; 1161 } 1162 1163 static inline void vfp_set_fpsr(CPUARMState *env, uint32_t val) 1164 { 1165 uint32_t new_fpscr = (vfp_get_fpscr(env) & ~FPSR_MASK) | (val & FPSR_MASK); 1166 vfp_set_fpscr(env, new_fpscr); 1167 } 1168 1169 static inline uint32_t vfp_get_fpcr(CPUARMState *env) 1170 { 1171 return vfp_get_fpscr(env) & FPCR_MASK; 1172 } 1173 1174 static inline void vfp_set_fpcr(CPUARMState *env, uint32_t val) 1175 { 1176 uint32_t new_fpscr = (vfp_get_fpscr(env) & ~FPCR_MASK) | (val & FPCR_MASK); 1177 vfp_set_fpscr(env, new_fpscr); 1178 } 1179 1180 enum arm_cpu_mode { 1181 ARM_CPU_MODE_USR = 0x10, 1182 ARM_CPU_MODE_FIQ = 0x11, 1183 ARM_CPU_MODE_IRQ = 0x12, 1184 ARM_CPU_MODE_SVC = 0x13, 1185 ARM_CPU_MODE_MON = 0x16, 1186 ARM_CPU_MODE_ABT = 0x17, 1187 ARM_CPU_MODE_HYP = 0x1a, 1188 ARM_CPU_MODE_UND = 0x1b, 1189 ARM_CPU_MODE_SYS = 0x1f 1190 }; 1191 1192 /* VFP system registers. */ 1193 #define ARM_VFP_FPSID 0 1194 #define ARM_VFP_FPSCR 1 1195 #define ARM_VFP_MVFR2 5 1196 #define ARM_VFP_MVFR1 6 1197 #define ARM_VFP_MVFR0 7 1198 #define ARM_VFP_FPEXC 8 1199 #define ARM_VFP_FPINST 9 1200 #define ARM_VFP_FPINST2 10 1201 1202 /* iwMMXt coprocessor control registers. */ 1203 #define ARM_IWMMXT_wCID 0 1204 #define ARM_IWMMXT_wCon 1 1205 #define ARM_IWMMXT_wCSSF 2 1206 #define ARM_IWMMXT_wCASF 3 1207 #define ARM_IWMMXT_wCGR0 8 1208 #define ARM_IWMMXT_wCGR1 9 1209 #define ARM_IWMMXT_wCGR2 10 1210 #define ARM_IWMMXT_wCGR3 11 1211 1212 /* V7M CCR bits */ 1213 FIELD(V7M_CCR, NONBASETHRDENA, 0, 1) 1214 FIELD(V7M_CCR, USERSETMPEND, 1, 1) 1215 FIELD(V7M_CCR, UNALIGN_TRP, 3, 1) 1216 FIELD(V7M_CCR, DIV_0_TRP, 4, 1) 1217 FIELD(V7M_CCR, BFHFNMIGN, 8, 1) 1218 FIELD(V7M_CCR, STKALIGN, 9, 1) 1219 FIELD(V7M_CCR, DC, 16, 1) 1220 FIELD(V7M_CCR, IC, 17, 1) 1221 1222 /* V7M AIRCR bits */ 1223 FIELD(V7M_AIRCR, VECTRESET, 0, 1) 1224 FIELD(V7M_AIRCR, VECTCLRACTIVE, 1, 1) 1225 FIELD(V7M_AIRCR, SYSRESETREQ, 2, 1) 1226 FIELD(V7M_AIRCR, SYSRESETREQS, 3, 1) 1227 FIELD(V7M_AIRCR, PRIGROUP, 8, 3) 1228 FIELD(V7M_AIRCR, BFHFNMINS, 13, 1) 1229 FIELD(V7M_AIRCR, PRIS, 14, 1) 1230 FIELD(V7M_AIRCR, ENDIANNESS, 15, 1) 1231 FIELD(V7M_AIRCR, VECTKEY, 16, 16) 1232 1233 /* V7M CFSR bits for MMFSR */ 1234 FIELD(V7M_CFSR, IACCVIOL, 0, 1) 1235 FIELD(V7M_CFSR, DACCVIOL, 1, 1) 1236 FIELD(V7M_CFSR, MUNSTKERR, 3, 1) 1237 FIELD(V7M_CFSR, MSTKERR, 4, 1) 1238 FIELD(V7M_CFSR, MLSPERR, 5, 1) 1239 FIELD(V7M_CFSR, MMARVALID, 7, 1) 1240 1241 /* V7M CFSR bits for BFSR */ 1242 FIELD(V7M_CFSR, IBUSERR, 8 + 0, 1) 1243 FIELD(V7M_CFSR, PRECISERR, 8 + 1, 1) 1244 FIELD(V7M_CFSR, IMPRECISERR, 8 + 2, 1) 1245 FIELD(V7M_CFSR, UNSTKERR, 8 + 3, 1) 1246 FIELD(V7M_CFSR, STKERR, 8 + 4, 1) 1247 FIELD(V7M_CFSR, LSPERR, 8 + 5, 1) 1248 FIELD(V7M_CFSR, BFARVALID, 8 + 7, 1) 1249 1250 /* V7M CFSR bits for UFSR */ 1251 FIELD(V7M_CFSR, UNDEFINSTR, 16 + 0, 1) 1252 FIELD(V7M_CFSR, INVSTATE, 16 + 1, 1) 1253 FIELD(V7M_CFSR, INVPC, 16 + 2, 1) 1254 FIELD(V7M_CFSR, NOCP, 16 + 3, 1) 1255 FIELD(V7M_CFSR, UNALIGNED, 16 + 8, 1) 1256 FIELD(V7M_CFSR, DIVBYZERO, 16 + 9, 1) 1257 1258 /* V7M CFSR bit masks covering all of the subregister bits */ 1259 FIELD(V7M_CFSR, MMFSR, 0, 8) 1260 FIELD(V7M_CFSR, BFSR, 8, 8) 1261 FIELD(V7M_CFSR, UFSR, 16, 16) 1262 1263 /* V7M HFSR bits */ 1264 FIELD(V7M_HFSR, VECTTBL, 1, 1) 1265 FIELD(V7M_HFSR, FORCED, 30, 1) 1266 FIELD(V7M_HFSR, DEBUGEVT, 31, 1) 1267 1268 /* V7M DFSR bits */ 1269 FIELD(V7M_DFSR, HALTED, 0, 1) 1270 FIELD(V7M_DFSR, BKPT, 1, 1) 1271 FIELD(V7M_DFSR, DWTTRAP, 2, 1) 1272 FIELD(V7M_DFSR, VCATCH, 3, 1) 1273 FIELD(V7M_DFSR, EXTERNAL, 4, 1) 1274 1275 /* V7M SFSR bits */ 1276 FIELD(V7M_SFSR, INVEP, 0, 1) 1277 FIELD(V7M_SFSR, INVIS, 1, 1) 1278 FIELD(V7M_SFSR, INVER, 2, 1) 1279 FIELD(V7M_SFSR, AUVIOL, 3, 1) 1280 FIELD(V7M_SFSR, INVTRAN, 4, 1) 1281 FIELD(V7M_SFSR, LSPERR, 5, 1) 1282 FIELD(V7M_SFSR, SFARVALID, 6, 1) 1283 FIELD(V7M_SFSR, LSERR, 7, 1) 1284 1285 /* v7M MPU_CTRL bits */ 1286 FIELD(V7M_MPU_CTRL, ENABLE, 0, 1) 1287 FIELD(V7M_MPU_CTRL, HFNMIENA, 1, 1) 1288 FIELD(V7M_MPU_CTRL, PRIVDEFENA, 2, 1) 1289 1290 /* If adding a feature bit which corresponds to a Linux ELF 1291 * HWCAP bit, remember to update the feature-bit-to-hwcap 1292 * mapping in linux-user/elfload.c:get_elf_hwcap(). 1293 */ 1294 enum arm_features { 1295 ARM_FEATURE_VFP, 1296 ARM_FEATURE_AUXCR, /* ARM1026 Auxiliary control register. */ 1297 ARM_FEATURE_XSCALE, /* Intel XScale extensions. */ 1298 ARM_FEATURE_IWMMXT, /* Intel iwMMXt extension. */ 1299 ARM_FEATURE_V6, 1300 ARM_FEATURE_V6K, 1301 ARM_FEATURE_V7, 1302 ARM_FEATURE_THUMB2, 1303 ARM_FEATURE_PMSA, /* no MMU; may have Memory Protection Unit */ 1304 ARM_FEATURE_VFP3, 1305 ARM_FEATURE_VFP_FP16, 1306 ARM_FEATURE_NEON, 1307 ARM_FEATURE_THUMB_DIV, /* divide supported in Thumb encoding */ 1308 ARM_FEATURE_M, /* Microcontroller profile. */ 1309 ARM_FEATURE_OMAPCP, /* OMAP specific CP15 ops handling. */ 1310 ARM_FEATURE_THUMB2EE, 1311 ARM_FEATURE_V7MP, /* v7 Multiprocessing Extensions */ 1312 ARM_FEATURE_V4T, 1313 ARM_FEATURE_V5, 1314 ARM_FEATURE_STRONGARM, 1315 ARM_FEATURE_VAPA, /* cp15 VA to PA lookups */ 1316 ARM_FEATURE_ARM_DIV, /* divide supported in ARM encoding */ 1317 ARM_FEATURE_VFP4, /* VFPv4 (implies that NEON is v2) */ 1318 ARM_FEATURE_GENERIC_TIMER, 1319 ARM_FEATURE_MVFR, /* Media and VFP Feature Registers 0 and 1 */ 1320 ARM_FEATURE_DUMMY_C15_REGS, /* RAZ/WI all of cp15 crn=15 */ 1321 ARM_FEATURE_CACHE_TEST_CLEAN, /* 926/1026 style test-and-clean ops */ 1322 ARM_FEATURE_CACHE_DIRTY_REG, /* 1136/1176 cache dirty status register */ 1323 ARM_FEATURE_CACHE_BLOCK_OPS, /* v6 optional cache block operations */ 1324 ARM_FEATURE_MPIDR, /* has cp15 MPIDR */ 1325 ARM_FEATURE_PXN, /* has Privileged Execute Never bit */ 1326 ARM_FEATURE_LPAE, /* has Large Physical Address Extension */ 1327 ARM_FEATURE_V8, 1328 ARM_FEATURE_AARCH64, /* supports 64 bit mode */ 1329 ARM_FEATURE_V8_AES, /* implements AES part of v8 Crypto Extensions */ 1330 ARM_FEATURE_CBAR, /* has cp15 CBAR */ 1331 ARM_FEATURE_CRC, /* ARMv8 CRC instructions */ 1332 ARM_FEATURE_CBAR_RO, /* has cp15 CBAR and it is read-only */ 1333 ARM_FEATURE_EL2, /* has EL2 Virtualization support */ 1334 ARM_FEATURE_EL3, /* has EL3 Secure monitor support */ 1335 ARM_FEATURE_V8_SHA1, /* implements SHA1 part of v8 Crypto Extensions */ 1336 ARM_FEATURE_V8_SHA256, /* implements SHA256 part of v8 Crypto Extensions */ 1337 ARM_FEATURE_V8_PMULL, /* implements PMULL part of v8 Crypto Extensions */ 1338 ARM_FEATURE_THUMB_DSP, /* DSP insns supported in the Thumb encodings */ 1339 ARM_FEATURE_PMU, /* has PMU support */ 1340 ARM_FEATURE_VBAR, /* has cp15 VBAR */ 1341 ARM_FEATURE_M_SECURITY, /* M profile Security Extension */ 1342 ARM_FEATURE_JAZELLE, /* has (trivial) Jazelle implementation */ 1343 ARM_FEATURE_SVE, /* has Scalable Vector Extension */ 1344 ARM_FEATURE_V8_SHA512, /* implements SHA512 part of v8 Crypto Extensions */ 1345 ARM_FEATURE_V8_SHA3, /* implements SHA3 part of v8 Crypto Extensions */ 1346 ARM_FEATURE_V8_SM3, /* implements SM3 part of v8 Crypto Extensions */ 1347 ARM_FEATURE_V8_SM4, /* implements SM4 part of v8 Crypto Extensions */ 1348 }; 1349 1350 static inline int arm_feature(CPUARMState *env, int feature) 1351 { 1352 return (env->features & (1ULL << feature)) != 0; 1353 } 1354 1355 #if !defined(CONFIG_USER_ONLY) 1356 /* Return true if exception levels below EL3 are in secure state, 1357 * or would be following an exception return to that level. 1358 * Unlike arm_is_secure() (which is always a question about the 1359 * _current_ state of the CPU) this doesn't care about the current 1360 * EL or mode. 1361 */ 1362 static inline bool arm_is_secure_below_el3(CPUARMState *env) 1363 { 1364 if (arm_feature(env, ARM_FEATURE_EL3)) { 1365 return !(env->cp15.scr_el3 & SCR_NS); 1366 } else { 1367 /* If EL3 is not supported then the secure state is implementation 1368 * defined, in which case QEMU defaults to non-secure. 1369 */ 1370 return false; 1371 } 1372 } 1373 1374 /* Return true if the CPU is AArch64 EL3 or AArch32 Mon */ 1375 static inline bool arm_is_el3_or_mon(CPUARMState *env) 1376 { 1377 if (arm_feature(env, ARM_FEATURE_EL3)) { 1378 if (is_a64(env) && extract32(env->pstate, 2, 2) == 3) { 1379 /* CPU currently in AArch64 state and EL3 */ 1380 return true; 1381 } else if (!is_a64(env) && 1382 (env->uncached_cpsr & CPSR_M) == ARM_CPU_MODE_MON) { 1383 /* CPU currently in AArch32 state and monitor mode */ 1384 return true; 1385 } 1386 } 1387 return false; 1388 } 1389 1390 /* Return true if the processor is in secure state */ 1391 static inline bool arm_is_secure(CPUARMState *env) 1392 { 1393 if (arm_is_el3_or_mon(env)) { 1394 return true; 1395 } 1396 return arm_is_secure_below_el3(env); 1397 } 1398 1399 #else 1400 static inline bool arm_is_secure_below_el3(CPUARMState *env) 1401 { 1402 return false; 1403 } 1404 1405 static inline bool arm_is_secure(CPUARMState *env) 1406 { 1407 return false; 1408 } 1409 #endif 1410 1411 /* Return true if the specified exception level is running in AArch64 state. */ 1412 static inline bool arm_el_is_aa64(CPUARMState *env, int el) 1413 { 1414 /* This isn't valid for EL0 (if we're in EL0, is_a64() is what you want, 1415 * and if we're not in EL0 then the state of EL0 isn't well defined.) 1416 */ 1417 assert(el >= 1 && el <= 3); 1418 bool aa64 = arm_feature(env, ARM_FEATURE_AARCH64); 1419 1420 /* The highest exception level is always at the maximum supported 1421 * register width, and then lower levels have a register width controlled 1422 * by bits in the SCR or HCR registers. 1423 */ 1424 if (el == 3) { 1425 return aa64; 1426 } 1427 1428 if (arm_feature(env, ARM_FEATURE_EL3)) { 1429 aa64 = aa64 && (env->cp15.scr_el3 & SCR_RW); 1430 } 1431 1432 if (el == 2) { 1433 return aa64; 1434 } 1435 1436 if (arm_feature(env, ARM_FEATURE_EL2) && !arm_is_secure_below_el3(env)) { 1437 aa64 = aa64 && (env->cp15.hcr_el2 & HCR_RW); 1438 } 1439 1440 return aa64; 1441 } 1442 1443 /* Function for determing whether guest cp register reads and writes should 1444 * access the secure or non-secure bank of a cp register. When EL3 is 1445 * operating in AArch32 state, the NS-bit determines whether the secure 1446 * instance of a cp register should be used. When EL3 is AArch64 (or if 1447 * it doesn't exist at all) then there is no register banking, and all 1448 * accesses are to the non-secure version. 1449 */ 1450 static inline bool access_secure_reg(CPUARMState *env) 1451 { 1452 bool ret = (arm_feature(env, ARM_FEATURE_EL3) && 1453 !arm_el_is_aa64(env, 3) && 1454 !(env->cp15.scr_el3 & SCR_NS)); 1455 1456 return ret; 1457 } 1458 1459 /* Macros for accessing a specified CP register bank */ 1460 #define A32_BANKED_REG_GET(_env, _regname, _secure) \ 1461 ((_secure) ? (_env)->cp15._regname##_s : (_env)->cp15._regname##_ns) 1462 1463 #define A32_BANKED_REG_SET(_env, _regname, _secure, _val) \ 1464 do { \ 1465 if (_secure) { \ 1466 (_env)->cp15._regname##_s = (_val); \ 1467 } else { \ 1468 (_env)->cp15._regname##_ns = (_val); \ 1469 } \ 1470 } while (0) 1471 1472 /* Macros for automatically accessing a specific CP register bank depending on 1473 * the current secure state of the system. These macros are not intended for 1474 * supporting instruction translation reads/writes as these are dependent 1475 * solely on the SCR.NS bit and not the mode. 1476 */ 1477 #define A32_BANKED_CURRENT_REG_GET(_env, _regname) \ 1478 A32_BANKED_REG_GET((_env), _regname, \ 1479 (arm_is_secure(_env) && !arm_el_is_aa64((_env), 3))) 1480 1481 #define A32_BANKED_CURRENT_REG_SET(_env, _regname, _val) \ 1482 A32_BANKED_REG_SET((_env), _regname, \ 1483 (arm_is_secure(_env) && !arm_el_is_aa64((_env), 3)), \ 1484 (_val)) 1485 1486 void arm_cpu_list(FILE *f, fprintf_function cpu_fprintf); 1487 uint32_t arm_phys_excp_target_el(CPUState *cs, uint32_t excp_idx, 1488 uint32_t cur_el, bool secure); 1489 1490 /* Interface between CPU and Interrupt controller. */ 1491 #ifndef CONFIG_USER_ONLY 1492 bool armv7m_nvic_can_take_pending_exception(void *opaque); 1493 #else 1494 static inline bool armv7m_nvic_can_take_pending_exception(void *opaque) 1495 { 1496 return true; 1497 } 1498 #endif 1499 /** 1500 * armv7m_nvic_set_pending: mark the specified exception as pending 1501 * @opaque: the NVIC 1502 * @irq: the exception number to mark pending 1503 * @secure: false for non-banked exceptions or for the nonsecure 1504 * version of a banked exception, true for the secure version of a banked 1505 * exception. 1506 * 1507 * Marks the specified exception as pending. Note that we will assert() 1508 * if @secure is true and @irq does not specify one of the fixed set 1509 * of architecturally banked exceptions. 1510 */ 1511 void armv7m_nvic_set_pending(void *opaque, int irq, bool secure); 1512 /** 1513 * armv7m_nvic_set_pending_derived: mark this derived exception as pending 1514 * @opaque: the NVIC 1515 * @irq: the exception number to mark pending 1516 * @secure: false for non-banked exceptions or for the nonsecure 1517 * version of a banked exception, true for the secure version of a banked 1518 * exception. 1519 * 1520 * Similar to armv7m_nvic_set_pending(), but specifically for derived 1521 * exceptions (exceptions generated in the course of trying to take 1522 * a different exception). 1523 */ 1524 void armv7m_nvic_set_pending_derived(void *opaque, int irq, bool secure); 1525 /** 1526 * armv7m_nvic_get_pending_irq_info: return highest priority pending 1527 * exception, and whether it targets Secure state 1528 * @opaque: the NVIC 1529 * @pirq: set to pending exception number 1530 * @ptargets_secure: set to whether pending exception targets Secure 1531 * 1532 * This function writes the number of the highest priority pending 1533 * exception (the one which would be made active by 1534 * armv7m_nvic_acknowledge_irq()) to @pirq, and sets @ptargets_secure 1535 * to true if the current highest priority pending exception should 1536 * be taken to Secure state, false for NS. 1537 */ 1538 void armv7m_nvic_get_pending_irq_info(void *opaque, int *pirq, 1539 bool *ptargets_secure); 1540 /** 1541 * armv7m_nvic_acknowledge_irq: make highest priority pending exception active 1542 * @opaque: the NVIC 1543 * 1544 * Move the current highest priority pending exception from the pending 1545 * state to the active state, and update v7m.exception to indicate that 1546 * it is the exception currently being handled. 1547 */ 1548 void armv7m_nvic_acknowledge_irq(void *opaque); 1549 /** 1550 * armv7m_nvic_complete_irq: complete specified interrupt or exception 1551 * @opaque: the NVIC 1552 * @irq: the exception number to complete 1553 * @secure: true if this exception was secure 1554 * 1555 * Returns: -1 if the irq was not active 1556 * 1 if completing this irq brought us back to base (no active irqs) 1557 * 0 if there is still an irq active after this one was completed 1558 * (Ignoring -1, this is the same as the RETTOBASE value before completion.) 1559 */ 1560 int armv7m_nvic_complete_irq(void *opaque, int irq, bool secure); 1561 /** 1562 * armv7m_nvic_raw_execution_priority: return the raw execution priority 1563 * @opaque: the NVIC 1564 * 1565 * Returns: the raw execution priority as defined by the v8M architecture. 1566 * This is the execution priority minus the effects of AIRCR.PRIS, 1567 * and minus any PRIMASK/FAULTMASK/BASEPRI priority boosting. 1568 * (v8M ARM ARM I_PKLD.) 1569 */ 1570 int armv7m_nvic_raw_execution_priority(void *opaque); 1571 /** 1572 * armv7m_nvic_neg_prio_requested: return true if the requested execution 1573 * priority is negative for the specified security state. 1574 * @opaque: the NVIC 1575 * @secure: the security state to test 1576 * This corresponds to the pseudocode IsReqExecPriNeg(). 1577 */ 1578 #ifndef CONFIG_USER_ONLY 1579 bool armv7m_nvic_neg_prio_requested(void *opaque, bool secure); 1580 #else 1581 static inline bool armv7m_nvic_neg_prio_requested(void *opaque, bool secure) 1582 { 1583 return false; 1584 } 1585 #endif 1586 1587 /* Interface for defining coprocessor registers. 1588 * Registers are defined in tables of arm_cp_reginfo structs 1589 * which are passed to define_arm_cp_regs(). 1590 */ 1591 1592 /* When looking up a coprocessor register we look for it 1593 * via an integer which encodes all of: 1594 * coprocessor number 1595 * Crn, Crm, opc1, opc2 fields 1596 * 32 or 64 bit register (ie is it accessed via MRC/MCR 1597 * or via MRRC/MCRR?) 1598 * non-secure/secure bank (AArch32 only) 1599 * We allow 4 bits for opc1 because MRRC/MCRR have a 4 bit field. 1600 * (In this case crn and opc2 should be zero.) 1601 * For AArch64, there is no 32/64 bit size distinction; 1602 * instead all registers have a 2 bit op0, 3 bit op1 and op2, 1603 * and 4 bit CRn and CRm. The encoding patterns are chosen 1604 * to be easy to convert to and from the KVM encodings, and also 1605 * so that the hashtable can contain both AArch32 and AArch64 1606 * registers (to allow for interprocessing where we might run 1607 * 32 bit code on a 64 bit core). 1608 */ 1609 /* This bit is private to our hashtable cpreg; in KVM register 1610 * IDs the AArch64/32 distinction is the KVM_REG_ARM/ARM64 1611 * in the upper bits of the 64 bit ID. 1612 */ 1613 #define CP_REG_AA64_SHIFT 28 1614 #define CP_REG_AA64_MASK (1 << CP_REG_AA64_SHIFT) 1615 1616 /* To enable banking of coprocessor registers depending on ns-bit we 1617 * add a bit to distinguish between secure and non-secure cpregs in the 1618 * hashtable. 1619 */ 1620 #define CP_REG_NS_SHIFT 29 1621 #define CP_REG_NS_MASK (1 << CP_REG_NS_SHIFT) 1622 1623 #define ENCODE_CP_REG(cp, is64, ns, crn, crm, opc1, opc2) \ 1624 ((ns) << CP_REG_NS_SHIFT | ((cp) << 16) | ((is64) << 15) | \ 1625 ((crn) << 11) | ((crm) << 7) | ((opc1) << 3) | (opc2)) 1626 1627 #define ENCODE_AA64_CP_REG(cp, crn, crm, op0, op1, op2) \ 1628 (CP_REG_AA64_MASK | \ 1629 ((cp) << CP_REG_ARM_COPROC_SHIFT) | \ 1630 ((op0) << CP_REG_ARM64_SYSREG_OP0_SHIFT) | \ 1631 ((op1) << CP_REG_ARM64_SYSREG_OP1_SHIFT) | \ 1632 ((crn) << CP_REG_ARM64_SYSREG_CRN_SHIFT) | \ 1633 ((crm) << CP_REG_ARM64_SYSREG_CRM_SHIFT) | \ 1634 ((op2) << CP_REG_ARM64_SYSREG_OP2_SHIFT)) 1635 1636 /* Convert a full 64 bit KVM register ID to the truncated 32 bit 1637 * version used as a key for the coprocessor register hashtable 1638 */ 1639 static inline uint32_t kvm_to_cpreg_id(uint64_t kvmid) 1640 { 1641 uint32_t cpregid = kvmid; 1642 if ((kvmid & CP_REG_ARCH_MASK) == CP_REG_ARM64) { 1643 cpregid |= CP_REG_AA64_MASK; 1644 } else { 1645 if ((kvmid & CP_REG_SIZE_MASK) == CP_REG_SIZE_U64) { 1646 cpregid |= (1 << 15); 1647 } 1648 1649 /* KVM is always non-secure so add the NS flag on AArch32 register 1650 * entries. 1651 */ 1652 cpregid |= 1 << CP_REG_NS_SHIFT; 1653 } 1654 return cpregid; 1655 } 1656 1657 /* Convert a truncated 32 bit hashtable key into the full 1658 * 64 bit KVM register ID. 1659 */ 1660 static inline uint64_t cpreg_to_kvm_id(uint32_t cpregid) 1661 { 1662 uint64_t kvmid; 1663 1664 if (cpregid & CP_REG_AA64_MASK) { 1665 kvmid = cpregid & ~CP_REG_AA64_MASK; 1666 kvmid |= CP_REG_SIZE_U64 | CP_REG_ARM64; 1667 } else { 1668 kvmid = cpregid & ~(1 << 15); 1669 if (cpregid & (1 << 15)) { 1670 kvmid |= CP_REG_SIZE_U64 | CP_REG_ARM; 1671 } else { 1672 kvmid |= CP_REG_SIZE_U32 | CP_REG_ARM; 1673 } 1674 } 1675 return kvmid; 1676 } 1677 1678 /* ARMCPRegInfo type field bits. If the SPECIAL bit is set this is a 1679 * special-behaviour cp reg and bits [15..8] indicate what behaviour 1680 * it has. Otherwise it is a simple cp reg, where CONST indicates that 1681 * TCG can assume the value to be constant (ie load at translate time) 1682 * and 64BIT indicates a 64 bit wide coprocessor register. SUPPRESS_TB_END 1683 * indicates that the TB should not be ended after a write to this register 1684 * (the default is that the TB ends after cp writes). OVERRIDE permits 1685 * a register definition to override a previous definition for the 1686 * same (cp, is64, crn, crm, opc1, opc2) tuple: either the new or the 1687 * old must have the OVERRIDE bit set. 1688 * ALIAS indicates that this register is an alias view of some underlying 1689 * state which is also visible via another register, and that the other 1690 * register is handling migration and reset; registers marked ALIAS will not be 1691 * migrated but may have their state set by syncing of register state from KVM. 1692 * NO_RAW indicates that this register has no underlying state and does not 1693 * support raw access for state saving/loading; it will not be used for either 1694 * migration or KVM state synchronization. (Typically this is for "registers" 1695 * which are actually used as instructions for cache maintenance and so on.) 1696 * IO indicates that this register does I/O and therefore its accesses 1697 * need to be surrounded by gen_io_start()/gen_io_end(). In particular, 1698 * registers which implement clocks or timers require this. 1699 */ 1700 #define ARM_CP_SPECIAL 1 1701 #define ARM_CP_CONST 2 1702 #define ARM_CP_64BIT 4 1703 #define ARM_CP_SUPPRESS_TB_END 8 1704 #define ARM_CP_OVERRIDE 16 1705 #define ARM_CP_ALIAS 32 1706 #define ARM_CP_IO 64 1707 #define ARM_CP_NO_RAW 128 1708 #define ARM_CP_NOP (ARM_CP_SPECIAL | (1 << 8)) 1709 #define ARM_CP_WFI (ARM_CP_SPECIAL | (2 << 8)) 1710 #define ARM_CP_NZCV (ARM_CP_SPECIAL | (3 << 8)) 1711 #define ARM_CP_CURRENTEL (ARM_CP_SPECIAL | (4 << 8)) 1712 #define ARM_CP_DC_ZVA (ARM_CP_SPECIAL | (5 << 8)) 1713 #define ARM_LAST_SPECIAL ARM_CP_DC_ZVA 1714 /* Used only as a terminator for ARMCPRegInfo lists */ 1715 #define ARM_CP_SENTINEL 0xffff 1716 /* Mask of only the flag bits in a type field */ 1717 #define ARM_CP_FLAG_MASK 0xff 1718 1719 /* Valid values for ARMCPRegInfo state field, indicating which of 1720 * the AArch32 and AArch64 execution states this register is visible in. 1721 * If the reginfo doesn't explicitly specify then it is AArch32 only. 1722 * If the reginfo is declared to be visible in both states then a second 1723 * reginfo is synthesised for the AArch32 view of the AArch64 register, 1724 * such that the AArch32 view is the lower 32 bits of the AArch64 one. 1725 * Note that we rely on the values of these enums as we iterate through 1726 * the various states in some places. 1727 */ 1728 enum { 1729 ARM_CP_STATE_AA32 = 0, 1730 ARM_CP_STATE_AA64 = 1, 1731 ARM_CP_STATE_BOTH = 2, 1732 }; 1733 1734 /* ARM CP register secure state flags. These flags identify security state 1735 * attributes for a given CP register entry. 1736 * The existence of both or neither secure and non-secure flags indicates that 1737 * the register has both a secure and non-secure hash entry. A single one of 1738 * these flags causes the register to only be hashed for the specified 1739 * security state. 1740 * Although definitions may have any combination of the S/NS bits, each 1741 * registered entry will only have one to identify whether the entry is secure 1742 * or non-secure. 1743 */ 1744 enum { 1745 ARM_CP_SECSTATE_S = (1 << 0), /* bit[0]: Secure state register */ 1746 ARM_CP_SECSTATE_NS = (1 << 1), /* bit[1]: Non-secure state register */ 1747 }; 1748 1749 /* Return true if cptype is a valid type field. This is used to try to 1750 * catch errors where the sentinel has been accidentally left off the end 1751 * of a list of registers. 1752 */ 1753 static inline bool cptype_valid(int cptype) 1754 { 1755 return ((cptype & ~ARM_CP_FLAG_MASK) == 0) 1756 || ((cptype & ARM_CP_SPECIAL) && 1757 ((cptype & ~ARM_CP_FLAG_MASK) <= ARM_LAST_SPECIAL)); 1758 } 1759 1760 /* Access rights: 1761 * We define bits for Read and Write access for what rev C of the v7-AR ARM ARM 1762 * defines as PL0 (user), PL1 (fiq/irq/svc/abt/und/sys, ie privileged), and 1763 * PL2 (hyp). The other level which has Read and Write bits is Secure PL1 1764 * (ie any of the privileged modes in Secure state, or Monitor mode). 1765 * If a register is accessible in one privilege level it's always accessible 1766 * in higher privilege levels too. Since "Secure PL1" also follows this rule 1767 * (ie anything visible in PL2 is visible in S-PL1, some things are only 1768 * visible in S-PL1) but "Secure PL1" is a bit of a mouthful, we bend the 1769 * terminology a little and call this PL3. 1770 * In AArch64 things are somewhat simpler as the PLx bits line up exactly 1771 * with the ELx exception levels. 1772 * 1773 * If access permissions for a register are more complex than can be 1774 * described with these bits, then use a laxer set of restrictions, and 1775 * do the more restrictive/complex check inside a helper function. 1776 */ 1777 #define PL3_R 0x80 1778 #define PL3_W 0x40 1779 #define PL2_R (0x20 | PL3_R) 1780 #define PL2_W (0x10 | PL3_W) 1781 #define PL1_R (0x08 | PL2_R) 1782 #define PL1_W (0x04 | PL2_W) 1783 #define PL0_R (0x02 | PL1_R) 1784 #define PL0_W (0x01 | PL1_W) 1785 1786 #define PL3_RW (PL3_R | PL3_W) 1787 #define PL2_RW (PL2_R | PL2_W) 1788 #define PL1_RW (PL1_R | PL1_W) 1789 #define PL0_RW (PL0_R | PL0_W) 1790 1791 /* Return the highest implemented Exception Level */ 1792 static inline int arm_highest_el(CPUARMState *env) 1793 { 1794 if (arm_feature(env, ARM_FEATURE_EL3)) { 1795 return 3; 1796 } 1797 if (arm_feature(env, ARM_FEATURE_EL2)) { 1798 return 2; 1799 } 1800 return 1; 1801 } 1802 1803 /* Return true if a v7M CPU is in Handler mode */ 1804 static inline bool arm_v7m_is_handler_mode(CPUARMState *env) 1805 { 1806 return env->v7m.exception != 0; 1807 } 1808 1809 /* Return the current Exception Level (as per ARMv8; note that this differs 1810 * from the ARMv7 Privilege Level). 1811 */ 1812 static inline int arm_current_el(CPUARMState *env) 1813 { 1814 if (arm_feature(env, ARM_FEATURE_M)) { 1815 return arm_v7m_is_handler_mode(env) || 1816 !(env->v7m.control[env->v7m.secure] & 1); 1817 } 1818 1819 if (is_a64(env)) { 1820 return extract32(env->pstate, 2, 2); 1821 } 1822 1823 switch (env->uncached_cpsr & 0x1f) { 1824 case ARM_CPU_MODE_USR: 1825 return 0; 1826 case ARM_CPU_MODE_HYP: 1827 return 2; 1828 case ARM_CPU_MODE_MON: 1829 return 3; 1830 default: 1831 if (arm_is_secure(env) && !arm_el_is_aa64(env, 3)) { 1832 /* If EL3 is 32-bit then all secure privileged modes run in 1833 * EL3 1834 */ 1835 return 3; 1836 } 1837 1838 return 1; 1839 } 1840 } 1841 1842 typedef struct ARMCPRegInfo ARMCPRegInfo; 1843 1844 typedef enum CPAccessResult { 1845 /* Access is permitted */ 1846 CP_ACCESS_OK = 0, 1847 /* Access fails due to a configurable trap or enable which would 1848 * result in a categorized exception syndrome giving information about 1849 * the failing instruction (ie syndrome category 0x3, 0x4, 0x5, 0x6, 1850 * 0xc or 0x18). The exception is taken to the usual target EL (EL1 or 1851 * PL1 if in EL0, otherwise to the current EL). 1852 */ 1853 CP_ACCESS_TRAP = 1, 1854 /* Access fails and results in an exception syndrome 0x0 ("uncategorized"). 1855 * Note that this is not a catch-all case -- the set of cases which may 1856 * result in this failure is specifically defined by the architecture. 1857 */ 1858 CP_ACCESS_TRAP_UNCATEGORIZED = 2, 1859 /* As CP_ACCESS_TRAP, but for traps directly to EL2 or EL3 */ 1860 CP_ACCESS_TRAP_EL2 = 3, 1861 CP_ACCESS_TRAP_EL3 = 4, 1862 /* As CP_ACCESS_UNCATEGORIZED, but for traps directly to EL2 or EL3 */ 1863 CP_ACCESS_TRAP_UNCATEGORIZED_EL2 = 5, 1864 CP_ACCESS_TRAP_UNCATEGORIZED_EL3 = 6, 1865 /* Access fails and results in an exception syndrome for an FP access, 1866 * trapped directly to EL2 or EL3 1867 */ 1868 CP_ACCESS_TRAP_FP_EL2 = 7, 1869 CP_ACCESS_TRAP_FP_EL3 = 8, 1870 } CPAccessResult; 1871 1872 /* Access functions for coprocessor registers. These cannot fail and 1873 * may not raise exceptions. 1874 */ 1875 typedef uint64_t CPReadFn(CPUARMState *env, const ARMCPRegInfo *opaque); 1876 typedef void CPWriteFn(CPUARMState *env, const ARMCPRegInfo *opaque, 1877 uint64_t value); 1878 /* Access permission check functions for coprocessor registers. */ 1879 typedef CPAccessResult CPAccessFn(CPUARMState *env, 1880 const ARMCPRegInfo *opaque, 1881 bool isread); 1882 /* Hook function for register reset */ 1883 typedef void CPResetFn(CPUARMState *env, const ARMCPRegInfo *opaque); 1884 1885 #define CP_ANY 0xff 1886 1887 /* Definition of an ARM coprocessor register */ 1888 struct ARMCPRegInfo { 1889 /* Name of register (useful mainly for debugging, need not be unique) */ 1890 const char *name; 1891 /* Location of register: coprocessor number and (crn,crm,opc1,opc2) 1892 * tuple. Any of crm, opc1 and opc2 may be CP_ANY to indicate a 1893 * 'wildcard' field -- any value of that field in the MRC/MCR insn 1894 * will be decoded to this register. The register read and write 1895 * callbacks will be passed an ARMCPRegInfo with the crn/crm/opc1/opc2 1896 * used by the program, so it is possible to register a wildcard and 1897 * then behave differently on read/write if necessary. 1898 * For 64 bit registers, only crm and opc1 are relevant; crn and opc2 1899 * must both be zero. 1900 * For AArch64-visible registers, opc0 is also used. 1901 * Since there are no "coprocessors" in AArch64, cp is purely used as a 1902 * way to distinguish (for KVM's benefit) guest-visible system registers 1903 * from demuxed ones provided to preserve the "no side effects on 1904 * KVM register read/write from QEMU" semantics. cp==0x13 is guest 1905 * visible (to match KVM's encoding); cp==0 will be converted to 1906 * cp==0x13 when the ARMCPRegInfo is registered, for convenience. 1907 */ 1908 uint8_t cp; 1909 uint8_t crn; 1910 uint8_t crm; 1911 uint8_t opc0; 1912 uint8_t opc1; 1913 uint8_t opc2; 1914 /* Execution state in which this register is visible: ARM_CP_STATE_* */ 1915 int state; 1916 /* Register type: ARM_CP_* bits/values */ 1917 int type; 1918 /* Access rights: PL*_[RW] */ 1919 int access; 1920 /* Security state: ARM_CP_SECSTATE_* bits/values */ 1921 int secure; 1922 /* The opaque pointer passed to define_arm_cp_regs_with_opaque() when 1923 * this register was defined: can be used to hand data through to the 1924 * register read/write functions, since they are passed the ARMCPRegInfo*. 1925 */ 1926 void *opaque; 1927 /* Value of this register, if it is ARM_CP_CONST. Otherwise, if 1928 * fieldoffset is non-zero, the reset value of the register. 1929 */ 1930 uint64_t resetvalue; 1931 /* Offset of the field in CPUARMState for this register. 1932 * 1933 * This is not needed if either: 1934 * 1. type is ARM_CP_CONST or one of the ARM_CP_SPECIALs 1935 * 2. both readfn and writefn are specified 1936 */ 1937 ptrdiff_t fieldoffset; /* offsetof(CPUARMState, field) */ 1938 1939 /* Offsets of the secure and non-secure fields in CPUARMState for the 1940 * register if it is banked. These fields are only used during the static 1941 * registration of a register. During hashing the bank associated 1942 * with a given security state is copied to fieldoffset which is used from 1943 * there on out. 1944 * 1945 * It is expected that register definitions use either fieldoffset or 1946 * bank_fieldoffsets in the definition but not both. It is also expected 1947 * that both bank offsets are set when defining a banked register. This 1948 * use indicates that a register is banked. 1949 */ 1950 ptrdiff_t bank_fieldoffsets[2]; 1951 1952 /* Function for making any access checks for this register in addition to 1953 * those specified by the 'access' permissions bits. If NULL, no extra 1954 * checks required. The access check is performed at runtime, not at 1955 * translate time. 1956 */ 1957 CPAccessFn *accessfn; 1958 /* Function for handling reads of this register. If NULL, then reads 1959 * will be done by loading from the offset into CPUARMState specified 1960 * by fieldoffset. 1961 */ 1962 CPReadFn *readfn; 1963 /* Function for handling writes of this register. If NULL, then writes 1964 * will be done by writing to the offset into CPUARMState specified 1965 * by fieldoffset. 1966 */ 1967 CPWriteFn *writefn; 1968 /* Function for doing a "raw" read; used when we need to copy 1969 * coprocessor state to the kernel for KVM or out for 1970 * migration. This only needs to be provided if there is also a 1971 * readfn and it has side effects (for instance clear-on-read bits). 1972 */ 1973 CPReadFn *raw_readfn; 1974 /* Function for doing a "raw" write; used when we need to copy KVM 1975 * kernel coprocessor state into userspace, or for inbound 1976 * migration. This only needs to be provided if there is also a 1977 * writefn and it masks out "unwritable" bits or has write-one-to-clear 1978 * or similar behaviour. 1979 */ 1980 CPWriteFn *raw_writefn; 1981 /* Function for resetting the register. If NULL, then reset will be done 1982 * by writing resetvalue to the field specified in fieldoffset. If 1983 * fieldoffset is 0 then no reset will be done. 1984 */ 1985 CPResetFn *resetfn; 1986 }; 1987 1988 /* Macros which are lvalues for the field in CPUARMState for the 1989 * ARMCPRegInfo *ri. 1990 */ 1991 #define CPREG_FIELD32(env, ri) \ 1992 (*(uint32_t *)((char *)(env) + (ri)->fieldoffset)) 1993 #define CPREG_FIELD64(env, ri) \ 1994 (*(uint64_t *)((char *)(env) + (ri)->fieldoffset)) 1995 1996 #define REGINFO_SENTINEL { .type = ARM_CP_SENTINEL } 1997 1998 void define_arm_cp_regs_with_opaque(ARMCPU *cpu, 1999 const ARMCPRegInfo *regs, void *opaque); 2000 void define_one_arm_cp_reg_with_opaque(ARMCPU *cpu, 2001 const ARMCPRegInfo *regs, void *opaque); 2002 static inline void define_arm_cp_regs(ARMCPU *cpu, const ARMCPRegInfo *regs) 2003 { 2004 define_arm_cp_regs_with_opaque(cpu, regs, 0); 2005 } 2006 static inline void define_one_arm_cp_reg(ARMCPU *cpu, const ARMCPRegInfo *regs) 2007 { 2008 define_one_arm_cp_reg_with_opaque(cpu, regs, 0); 2009 } 2010 const ARMCPRegInfo *get_arm_cp_reginfo(GHashTable *cpregs, uint32_t encoded_cp); 2011 2012 /* CPWriteFn that can be used to implement writes-ignored behaviour */ 2013 void arm_cp_write_ignore(CPUARMState *env, const ARMCPRegInfo *ri, 2014 uint64_t value); 2015 /* CPReadFn that can be used for read-as-zero behaviour */ 2016 uint64_t arm_cp_read_zero(CPUARMState *env, const ARMCPRegInfo *ri); 2017 2018 /* CPResetFn that does nothing, for use if no reset is required even 2019 * if fieldoffset is non zero. 2020 */ 2021 void arm_cp_reset_ignore(CPUARMState *env, const ARMCPRegInfo *opaque); 2022 2023 /* Return true if this reginfo struct's field in the cpu state struct 2024 * is 64 bits wide. 2025 */ 2026 static inline bool cpreg_field_is_64bit(const ARMCPRegInfo *ri) 2027 { 2028 return (ri->state == ARM_CP_STATE_AA64) || (ri->type & ARM_CP_64BIT); 2029 } 2030 2031 static inline bool cp_access_ok(int current_el, 2032 const ARMCPRegInfo *ri, int isread) 2033 { 2034 return (ri->access >> ((current_el * 2) + isread)) & 1; 2035 } 2036 2037 /* Raw read of a coprocessor register (as needed for migration, etc) */ 2038 uint64_t read_raw_cp_reg(CPUARMState *env, const ARMCPRegInfo *ri); 2039 2040 /** 2041 * write_list_to_cpustate 2042 * @cpu: ARMCPU 2043 * 2044 * For each register listed in the ARMCPU cpreg_indexes list, write 2045 * its value from the cpreg_values list into the ARMCPUState structure. 2046 * This updates TCG's working data structures from KVM data or 2047 * from incoming migration state. 2048 * 2049 * Returns: true if all register values were updated correctly, 2050 * false if some register was unknown or could not be written. 2051 * Note that we do not stop early on failure -- we will attempt 2052 * writing all registers in the list. 2053 */ 2054 bool write_list_to_cpustate(ARMCPU *cpu); 2055 2056 /** 2057 * write_cpustate_to_list: 2058 * @cpu: ARMCPU 2059 * 2060 * For each register listed in the ARMCPU cpreg_indexes list, write 2061 * its value from the ARMCPUState structure into the cpreg_values list. 2062 * This is used to copy info from TCG's working data structures into 2063 * KVM or for outbound migration. 2064 * 2065 * Returns: true if all register values were read correctly, 2066 * false if some register was unknown or could not be read. 2067 * Note that we do not stop early on failure -- we will attempt 2068 * reading all registers in the list. 2069 */ 2070 bool write_cpustate_to_list(ARMCPU *cpu); 2071 2072 #define ARM_CPUID_TI915T 0x54029152 2073 #define ARM_CPUID_TI925T 0x54029252 2074 2075 #if defined(CONFIG_USER_ONLY) 2076 #define TARGET_PAGE_BITS 12 2077 #else 2078 /* ARMv7 and later CPUs have 4K pages minimum, but ARMv5 and v6 2079 * have to support 1K tiny pages. 2080 */ 2081 #define TARGET_PAGE_BITS_VARY 2082 #define TARGET_PAGE_BITS_MIN 10 2083 #endif 2084 2085 #if defined(TARGET_AARCH64) 2086 # define TARGET_PHYS_ADDR_SPACE_BITS 48 2087 # define TARGET_VIRT_ADDR_SPACE_BITS 64 2088 #else 2089 # define TARGET_PHYS_ADDR_SPACE_BITS 40 2090 # define TARGET_VIRT_ADDR_SPACE_BITS 32 2091 #endif 2092 2093 static inline bool arm_excp_unmasked(CPUState *cs, unsigned int excp_idx, 2094 unsigned int target_el) 2095 { 2096 CPUARMState *env = cs->env_ptr; 2097 unsigned int cur_el = arm_current_el(env); 2098 bool secure = arm_is_secure(env); 2099 bool pstate_unmasked; 2100 int8_t unmasked = 0; 2101 2102 /* Don't take exceptions if they target a lower EL. 2103 * This check should catch any exceptions that would not be taken but left 2104 * pending. 2105 */ 2106 if (cur_el > target_el) { 2107 return false; 2108 } 2109 2110 switch (excp_idx) { 2111 case EXCP_FIQ: 2112 pstate_unmasked = !(env->daif & PSTATE_F); 2113 break; 2114 2115 case EXCP_IRQ: 2116 pstate_unmasked = !(env->daif & PSTATE_I); 2117 break; 2118 2119 case EXCP_VFIQ: 2120 if (secure || !(env->cp15.hcr_el2 & HCR_FMO)) { 2121 /* VFIQs are only taken when hypervized and non-secure. */ 2122 return false; 2123 } 2124 return !(env->daif & PSTATE_F); 2125 case EXCP_VIRQ: 2126 if (secure || !(env->cp15.hcr_el2 & HCR_IMO)) { 2127 /* VIRQs are only taken when hypervized and non-secure. */ 2128 return false; 2129 } 2130 return !(env->daif & PSTATE_I); 2131 default: 2132 g_assert_not_reached(); 2133 } 2134 2135 /* Use the target EL, current execution state and SCR/HCR settings to 2136 * determine whether the corresponding CPSR bit is used to mask the 2137 * interrupt. 2138 */ 2139 if ((target_el > cur_el) && (target_el != 1)) { 2140 /* Exceptions targeting a higher EL may not be maskable */ 2141 if (arm_feature(env, ARM_FEATURE_AARCH64)) { 2142 /* 64-bit masking rules are simple: exceptions to EL3 2143 * can't be masked, and exceptions to EL2 can only be 2144 * masked from Secure state. The HCR and SCR settings 2145 * don't affect the masking logic, only the interrupt routing. 2146 */ 2147 if (target_el == 3 || !secure) { 2148 unmasked = 1; 2149 } 2150 } else { 2151 /* The old 32-bit-only environment has a more complicated 2152 * masking setup. HCR and SCR bits not only affect interrupt 2153 * routing but also change the behaviour of masking. 2154 */ 2155 bool hcr, scr; 2156 2157 switch (excp_idx) { 2158 case EXCP_FIQ: 2159 /* If FIQs are routed to EL3 or EL2 then there are cases where 2160 * we override the CPSR.F in determining if the exception is 2161 * masked or not. If neither of these are set then we fall back 2162 * to the CPSR.F setting otherwise we further assess the state 2163 * below. 2164 */ 2165 hcr = (env->cp15.hcr_el2 & HCR_FMO); 2166 scr = (env->cp15.scr_el3 & SCR_FIQ); 2167 2168 /* When EL3 is 32-bit, the SCR.FW bit controls whether the 2169 * CPSR.F bit masks FIQ interrupts when taken in non-secure 2170 * state. If SCR.FW is set then FIQs can be masked by CPSR.F 2171 * when non-secure but only when FIQs are only routed to EL3. 2172 */ 2173 scr = scr && !((env->cp15.scr_el3 & SCR_FW) && !hcr); 2174 break; 2175 case EXCP_IRQ: 2176 /* When EL3 execution state is 32-bit, if HCR.IMO is set then 2177 * we may override the CPSR.I masking when in non-secure state. 2178 * The SCR.IRQ setting has already been taken into consideration 2179 * when setting the target EL, so it does not have a further 2180 * affect here. 2181 */ 2182 hcr = (env->cp15.hcr_el2 & HCR_IMO); 2183 scr = false; 2184 break; 2185 default: 2186 g_assert_not_reached(); 2187 } 2188 2189 if ((scr || hcr) && !secure) { 2190 unmasked = 1; 2191 } 2192 } 2193 } 2194 2195 /* The PSTATE bits only mask the interrupt if we have not overriden the 2196 * ability above. 2197 */ 2198 return unmasked || pstate_unmasked; 2199 } 2200 2201 #define cpu_init(cpu_model) cpu_generic_init(TYPE_ARM_CPU, cpu_model) 2202 2203 #define ARM_CPU_TYPE_SUFFIX "-" TYPE_ARM_CPU 2204 #define ARM_CPU_TYPE_NAME(name) (name ARM_CPU_TYPE_SUFFIX) 2205 2206 #define cpu_signal_handler cpu_arm_signal_handler 2207 #define cpu_list arm_cpu_list 2208 2209 /* ARM has the following "translation regimes" (as the ARM ARM calls them): 2210 * 2211 * If EL3 is 64-bit: 2212 * + NonSecure EL1 & 0 stage 1 2213 * + NonSecure EL1 & 0 stage 2 2214 * + NonSecure EL2 2215 * + Secure EL1 & EL0 2216 * + Secure EL3 2217 * If EL3 is 32-bit: 2218 * + NonSecure PL1 & 0 stage 1 2219 * + NonSecure PL1 & 0 stage 2 2220 * + NonSecure PL2 2221 * + Secure PL0 & PL1 2222 * (reminder: for 32 bit EL3, Secure PL1 is *EL3*, not EL1.) 2223 * 2224 * For QEMU, an mmu_idx is not quite the same as a translation regime because: 2225 * 1. we need to split the "EL1 & 0" regimes into two mmu_idxes, because they 2226 * may differ in access permissions even if the VA->PA map is the same 2227 * 2. we want to cache in our TLB the full VA->IPA->PA lookup for a stage 1+2 2228 * translation, which means that we have one mmu_idx that deals with two 2229 * concatenated translation regimes [this sort of combined s1+2 TLB is 2230 * architecturally permitted] 2231 * 3. we don't need to allocate an mmu_idx to translations that we won't be 2232 * handling via the TLB. The only way to do a stage 1 translation without 2233 * the immediate stage 2 translation is via the ATS or AT system insns, 2234 * which can be slow-pathed and always do a page table walk. 2235 * 4. we can also safely fold together the "32 bit EL3" and "64 bit EL3" 2236 * translation regimes, because they map reasonably well to each other 2237 * and they can't both be active at the same time. 2238 * This gives us the following list of mmu_idx values: 2239 * 2240 * NS EL0 (aka NS PL0) stage 1+2 2241 * NS EL1 (aka NS PL1) stage 1+2 2242 * NS EL2 (aka NS PL2) 2243 * S EL3 (aka S PL1) 2244 * S EL0 (aka S PL0) 2245 * S EL1 (not used if EL3 is 32 bit) 2246 * NS EL0+1 stage 2 2247 * 2248 * (The last of these is an mmu_idx because we want to be able to use the TLB 2249 * for the accesses done as part of a stage 1 page table walk, rather than 2250 * having to walk the stage 2 page table over and over.) 2251 * 2252 * R profile CPUs have an MPU, but can use the same set of MMU indexes 2253 * as A profile. They only need to distinguish NS EL0 and NS EL1 (and 2254 * NS EL2 if we ever model a Cortex-R52). 2255 * 2256 * M profile CPUs are rather different as they do not have a true MMU. 2257 * They have the following different MMU indexes: 2258 * User 2259 * Privileged 2260 * User, execution priority negative (ie the MPU HFNMIENA bit may apply) 2261 * Privileged, execution priority negative (ditto) 2262 * If the CPU supports the v8M Security Extension then there are also: 2263 * Secure User 2264 * Secure Privileged 2265 * Secure User, execution priority negative 2266 * Secure Privileged, execution priority negative 2267 * 2268 * The ARMMMUIdx and the mmu index value used by the core QEMU TLB code 2269 * are not quite the same -- different CPU types (most notably M profile 2270 * vs A/R profile) would like to use MMU indexes with different semantics, 2271 * but since we don't ever need to use all of those in a single CPU we 2272 * can avoid setting NB_MMU_MODES to more than 8. The lower bits of 2273 * ARMMMUIdx are the core TLB mmu index, and the higher bits are always 2274 * the same for any particular CPU. 2275 * Variables of type ARMMUIdx are always full values, and the core 2276 * index values are in variables of type 'int'. 2277 * 2278 * Our enumeration includes at the end some entries which are not "true" 2279 * mmu_idx values in that they don't have corresponding TLBs and are only 2280 * valid for doing slow path page table walks. 2281 * 2282 * The constant names here are patterned after the general style of the names 2283 * of the AT/ATS operations. 2284 * The values used are carefully arranged to make mmu_idx => EL lookup easy. 2285 * For M profile we arrange them to have a bit for priv, a bit for negpri 2286 * and a bit for secure. 2287 */ 2288 #define ARM_MMU_IDX_A 0x10 /* A profile */ 2289 #define ARM_MMU_IDX_NOTLB 0x20 /* does not have a TLB */ 2290 #define ARM_MMU_IDX_M 0x40 /* M profile */ 2291 2292 /* meanings of the bits for M profile mmu idx values */ 2293 #define ARM_MMU_IDX_M_PRIV 0x1 2294 #define ARM_MMU_IDX_M_NEGPRI 0x2 2295 #define ARM_MMU_IDX_M_S 0x4 2296 2297 #define ARM_MMU_IDX_TYPE_MASK (~0x7) 2298 #define ARM_MMU_IDX_COREIDX_MASK 0x7 2299 2300 typedef enum ARMMMUIdx { 2301 ARMMMUIdx_S12NSE0 = 0 | ARM_MMU_IDX_A, 2302 ARMMMUIdx_S12NSE1 = 1 | ARM_MMU_IDX_A, 2303 ARMMMUIdx_S1E2 = 2 | ARM_MMU_IDX_A, 2304 ARMMMUIdx_S1E3 = 3 | ARM_MMU_IDX_A, 2305 ARMMMUIdx_S1SE0 = 4 | ARM_MMU_IDX_A, 2306 ARMMMUIdx_S1SE1 = 5 | ARM_MMU_IDX_A, 2307 ARMMMUIdx_S2NS = 6 | ARM_MMU_IDX_A, 2308 ARMMMUIdx_MUser = 0 | ARM_MMU_IDX_M, 2309 ARMMMUIdx_MPriv = 1 | ARM_MMU_IDX_M, 2310 ARMMMUIdx_MUserNegPri = 2 | ARM_MMU_IDX_M, 2311 ARMMMUIdx_MPrivNegPri = 3 | ARM_MMU_IDX_M, 2312 ARMMMUIdx_MSUser = 4 | ARM_MMU_IDX_M, 2313 ARMMMUIdx_MSPriv = 5 | ARM_MMU_IDX_M, 2314 ARMMMUIdx_MSUserNegPri = 6 | ARM_MMU_IDX_M, 2315 ARMMMUIdx_MSPrivNegPri = 7 | ARM_MMU_IDX_M, 2316 /* Indexes below here don't have TLBs and are used only for AT system 2317 * instructions or for the first stage of an S12 page table walk. 2318 */ 2319 ARMMMUIdx_S1NSE0 = 0 | ARM_MMU_IDX_NOTLB, 2320 ARMMMUIdx_S1NSE1 = 1 | ARM_MMU_IDX_NOTLB, 2321 } ARMMMUIdx; 2322 2323 /* Bit macros for the core-mmu-index values for each index, 2324 * for use when calling tlb_flush_by_mmuidx() and friends. 2325 */ 2326 typedef enum ARMMMUIdxBit { 2327 ARMMMUIdxBit_S12NSE0 = 1 << 0, 2328 ARMMMUIdxBit_S12NSE1 = 1 << 1, 2329 ARMMMUIdxBit_S1E2 = 1 << 2, 2330 ARMMMUIdxBit_S1E3 = 1 << 3, 2331 ARMMMUIdxBit_S1SE0 = 1 << 4, 2332 ARMMMUIdxBit_S1SE1 = 1 << 5, 2333 ARMMMUIdxBit_S2NS = 1 << 6, 2334 ARMMMUIdxBit_MUser = 1 << 0, 2335 ARMMMUIdxBit_MPriv = 1 << 1, 2336 ARMMMUIdxBit_MUserNegPri = 1 << 2, 2337 ARMMMUIdxBit_MPrivNegPri = 1 << 3, 2338 ARMMMUIdxBit_MSUser = 1 << 4, 2339 ARMMMUIdxBit_MSPriv = 1 << 5, 2340 ARMMMUIdxBit_MSUserNegPri = 1 << 6, 2341 ARMMMUIdxBit_MSPrivNegPri = 1 << 7, 2342 } ARMMMUIdxBit; 2343 2344 #define MMU_USER_IDX 0 2345 2346 static inline int arm_to_core_mmu_idx(ARMMMUIdx mmu_idx) 2347 { 2348 return mmu_idx & ARM_MMU_IDX_COREIDX_MASK; 2349 } 2350 2351 static inline ARMMMUIdx core_to_arm_mmu_idx(CPUARMState *env, int mmu_idx) 2352 { 2353 if (arm_feature(env, ARM_FEATURE_M)) { 2354 return mmu_idx | ARM_MMU_IDX_M; 2355 } else { 2356 return mmu_idx | ARM_MMU_IDX_A; 2357 } 2358 } 2359 2360 /* Return the exception level we're running at if this is our mmu_idx */ 2361 static inline int arm_mmu_idx_to_el(ARMMMUIdx mmu_idx) 2362 { 2363 switch (mmu_idx & ARM_MMU_IDX_TYPE_MASK) { 2364 case ARM_MMU_IDX_A: 2365 return mmu_idx & 3; 2366 case ARM_MMU_IDX_M: 2367 return mmu_idx & ARM_MMU_IDX_M_PRIV; 2368 default: 2369 g_assert_not_reached(); 2370 } 2371 } 2372 2373 /* Return the MMU index for a v7M CPU in the specified security and 2374 * privilege state 2375 */ 2376 static inline ARMMMUIdx arm_v7m_mmu_idx_for_secstate_and_priv(CPUARMState *env, 2377 bool secstate, 2378 bool priv) 2379 { 2380 ARMMMUIdx mmu_idx = ARM_MMU_IDX_M; 2381 2382 if (priv) { 2383 mmu_idx |= ARM_MMU_IDX_M_PRIV; 2384 } 2385 2386 if (armv7m_nvic_neg_prio_requested(env->nvic, secstate)) { 2387 mmu_idx |= ARM_MMU_IDX_M_NEGPRI; 2388 } 2389 2390 if (secstate) { 2391 mmu_idx |= ARM_MMU_IDX_M_S; 2392 } 2393 2394 return mmu_idx; 2395 } 2396 2397 /* Return the MMU index for a v7M CPU in the specified security state */ 2398 static inline ARMMMUIdx arm_v7m_mmu_idx_for_secstate(CPUARMState *env, 2399 bool secstate) 2400 { 2401 bool priv = arm_current_el(env) != 0; 2402 2403 return arm_v7m_mmu_idx_for_secstate_and_priv(env, secstate, priv); 2404 } 2405 2406 /* Determine the current mmu_idx to use for normal loads/stores */ 2407 static inline int cpu_mmu_index(CPUARMState *env, bool ifetch) 2408 { 2409 int el = arm_current_el(env); 2410 2411 if (arm_feature(env, ARM_FEATURE_M)) { 2412 ARMMMUIdx mmu_idx = arm_v7m_mmu_idx_for_secstate(env, env->v7m.secure); 2413 2414 return arm_to_core_mmu_idx(mmu_idx); 2415 } 2416 2417 if (el < 2 && arm_is_secure_below_el3(env)) { 2418 return arm_to_core_mmu_idx(ARMMMUIdx_S1SE0 + el); 2419 } 2420 return el; 2421 } 2422 2423 /* Indexes used when registering address spaces with cpu_address_space_init */ 2424 typedef enum ARMASIdx { 2425 ARMASIdx_NS = 0, 2426 ARMASIdx_S = 1, 2427 } ARMASIdx; 2428 2429 /* Return the Exception Level targeted by debug exceptions. */ 2430 static inline int arm_debug_target_el(CPUARMState *env) 2431 { 2432 bool secure = arm_is_secure(env); 2433 bool route_to_el2 = false; 2434 2435 if (arm_feature(env, ARM_FEATURE_EL2) && !secure) { 2436 route_to_el2 = env->cp15.hcr_el2 & HCR_TGE || 2437 env->cp15.mdcr_el2 & (1 << 8); 2438 } 2439 2440 if (route_to_el2) { 2441 return 2; 2442 } else if (arm_feature(env, ARM_FEATURE_EL3) && 2443 !arm_el_is_aa64(env, 3) && secure) { 2444 return 3; 2445 } else { 2446 return 1; 2447 } 2448 } 2449 2450 static inline bool aa64_generate_debug_exceptions(CPUARMState *env) 2451 { 2452 if (arm_is_secure(env)) { 2453 /* MDCR_EL3.SDD disables debug events from Secure state */ 2454 if (extract32(env->cp15.mdcr_el3, 16, 1) != 0 2455 || arm_current_el(env) == 3) { 2456 return false; 2457 } 2458 } 2459 2460 if (arm_current_el(env) == arm_debug_target_el(env)) { 2461 if ((extract32(env->cp15.mdscr_el1, 13, 1) == 0) 2462 || (env->daif & PSTATE_D)) { 2463 return false; 2464 } 2465 } 2466 return true; 2467 } 2468 2469 static inline bool aa32_generate_debug_exceptions(CPUARMState *env) 2470 { 2471 int el = arm_current_el(env); 2472 2473 if (el == 0 && arm_el_is_aa64(env, 1)) { 2474 return aa64_generate_debug_exceptions(env); 2475 } 2476 2477 if (arm_is_secure(env)) { 2478 int spd; 2479 2480 if (el == 0 && (env->cp15.sder & 1)) { 2481 /* SDER.SUIDEN means debug exceptions from Secure EL0 2482 * are always enabled. Otherwise they are controlled by 2483 * SDCR.SPD like those from other Secure ELs. 2484 */ 2485 return true; 2486 } 2487 2488 spd = extract32(env->cp15.mdcr_el3, 14, 2); 2489 switch (spd) { 2490 case 1: 2491 /* SPD == 0b01 is reserved, but behaves as 0b00. */ 2492 case 0: 2493 /* For 0b00 we return true if external secure invasive debug 2494 * is enabled. On real hardware this is controlled by external 2495 * signals to the core. QEMU always permits debug, and behaves 2496 * as if DBGEN, SPIDEN, NIDEN and SPNIDEN are all tied high. 2497 */ 2498 return true; 2499 case 2: 2500 return false; 2501 case 3: 2502 return true; 2503 } 2504 } 2505 2506 return el != 2; 2507 } 2508 2509 /* Return true if debugging exceptions are currently enabled. 2510 * This corresponds to what in ARM ARM pseudocode would be 2511 * if UsingAArch32() then 2512 * return AArch32.GenerateDebugExceptions() 2513 * else 2514 * return AArch64.GenerateDebugExceptions() 2515 * We choose to push the if() down into this function for clarity, 2516 * since the pseudocode has it at all callsites except for the one in 2517 * CheckSoftwareStep(), where it is elided because both branches would 2518 * always return the same value. 2519 * 2520 * Parts of the pseudocode relating to EL2 and EL3 are omitted because we 2521 * don't yet implement those exception levels or their associated trap bits. 2522 */ 2523 static inline bool arm_generate_debug_exceptions(CPUARMState *env) 2524 { 2525 if (env->aarch64) { 2526 return aa64_generate_debug_exceptions(env); 2527 } else { 2528 return aa32_generate_debug_exceptions(env); 2529 } 2530 } 2531 2532 /* Is single-stepping active? (Note that the "is EL_D AArch64?" check 2533 * implicitly means this always returns false in pre-v8 CPUs.) 2534 */ 2535 static inline bool arm_singlestep_active(CPUARMState *env) 2536 { 2537 return extract32(env->cp15.mdscr_el1, 0, 1) 2538 && arm_el_is_aa64(env, arm_debug_target_el(env)) 2539 && arm_generate_debug_exceptions(env); 2540 } 2541 2542 static inline bool arm_sctlr_b(CPUARMState *env) 2543 { 2544 return 2545 /* We need not implement SCTLR.ITD in user-mode emulation, so 2546 * let linux-user ignore the fact that it conflicts with SCTLR_B. 2547 * This lets people run BE32 binaries with "-cpu any". 2548 */ 2549 #ifndef CONFIG_USER_ONLY 2550 !arm_feature(env, ARM_FEATURE_V7) && 2551 #endif 2552 (env->cp15.sctlr_el[1] & SCTLR_B) != 0; 2553 } 2554 2555 /* Return true if the processor is in big-endian mode. */ 2556 static inline bool arm_cpu_data_is_big_endian(CPUARMState *env) 2557 { 2558 int cur_el; 2559 2560 /* In 32bit endianness is determined by looking at CPSR's E bit */ 2561 if (!is_a64(env)) { 2562 return 2563 #ifdef CONFIG_USER_ONLY 2564 /* In system mode, BE32 is modelled in line with the 2565 * architecture (as word-invariant big-endianness), where loads 2566 * and stores are done little endian but from addresses which 2567 * are adjusted by XORing with the appropriate constant. So the 2568 * endianness to use for the raw data access is not affected by 2569 * SCTLR.B. 2570 * In user mode, however, we model BE32 as byte-invariant 2571 * big-endianness (because user-only code cannot tell the 2572 * difference), and so we need to use a data access endianness 2573 * that depends on SCTLR.B. 2574 */ 2575 arm_sctlr_b(env) || 2576 #endif 2577 ((env->uncached_cpsr & CPSR_E) ? 1 : 0); 2578 } 2579 2580 cur_el = arm_current_el(env); 2581 2582 if (cur_el == 0) { 2583 return (env->cp15.sctlr_el[1] & SCTLR_E0E) != 0; 2584 } 2585 2586 return (env->cp15.sctlr_el[cur_el] & SCTLR_EE) != 0; 2587 } 2588 2589 #include "exec/cpu-all.h" 2590 2591 /* Bit usage in the TB flags field: bit 31 indicates whether we are 2592 * in 32 or 64 bit mode. The meaning of the other bits depends on that. 2593 * We put flags which are shared between 32 and 64 bit mode at the top 2594 * of the word, and flags which apply to only one mode at the bottom. 2595 */ 2596 #define ARM_TBFLAG_AARCH64_STATE_SHIFT 31 2597 #define ARM_TBFLAG_AARCH64_STATE_MASK (1U << ARM_TBFLAG_AARCH64_STATE_SHIFT) 2598 #define ARM_TBFLAG_MMUIDX_SHIFT 28 2599 #define ARM_TBFLAG_MMUIDX_MASK (0x7 << ARM_TBFLAG_MMUIDX_SHIFT) 2600 #define ARM_TBFLAG_SS_ACTIVE_SHIFT 27 2601 #define ARM_TBFLAG_SS_ACTIVE_MASK (1 << ARM_TBFLAG_SS_ACTIVE_SHIFT) 2602 #define ARM_TBFLAG_PSTATE_SS_SHIFT 26 2603 #define ARM_TBFLAG_PSTATE_SS_MASK (1 << ARM_TBFLAG_PSTATE_SS_SHIFT) 2604 /* Target EL if we take a floating-point-disabled exception */ 2605 #define ARM_TBFLAG_FPEXC_EL_SHIFT 24 2606 #define ARM_TBFLAG_FPEXC_EL_MASK (0x3 << ARM_TBFLAG_FPEXC_EL_SHIFT) 2607 2608 /* Bit usage when in AArch32 state: */ 2609 #define ARM_TBFLAG_THUMB_SHIFT 0 2610 #define ARM_TBFLAG_THUMB_MASK (1 << ARM_TBFLAG_THUMB_SHIFT) 2611 #define ARM_TBFLAG_VECLEN_SHIFT 1 2612 #define ARM_TBFLAG_VECLEN_MASK (0x7 << ARM_TBFLAG_VECLEN_SHIFT) 2613 #define ARM_TBFLAG_VECSTRIDE_SHIFT 4 2614 #define ARM_TBFLAG_VECSTRIDE_MASK (0x3 << ARM_TBFLAG_VECSTRIDE_SHIFT) 2615 #define ARM_TBFLAG_VFPEN_SHIFT 7 2616 #define ARM_TBFLAG_VFPEN_MASK (1 << ARM_TBFLAG_VFPEN_SHIFT) 2617 #define ARM_TBFLAG_CONDEXEC_SHIFT 8 2618 #define ARM_TBFLAG_CONDEXEC_MASK (0xff << ARM_TBFLAG_CONDEXEC_SHIFT) 2619 #define ARM_TBFLAG_SCTLR_B_SHIFT 16 2620 #define ARM_TBFLAG_SCTLR_B_MASK (1 << ARM_TBFLAG_SCTLR_B_SHIFT) 2621 /* We store the bottom two bits of the CPAR as TB flags and handle 2622 * checks on the other bits at runtime 2623 */ 2624 #define ARM_TBFLAG_XSCALE_CPAR_SHIFT 17 2625 #define ARM_TBFLAG_XSCALE_CPAR_MASK (3 << ARM_TBFLAG_XSCALE_CPAR_SHIFT) 2626 /* Indicates whether cp register reads and writes by guest code should access 2627 * the secure or nonsecure bank of banked registers; note that this is not 2628 * the same thing as the current security state of the processor! 2629 */ 2630 #define ARM_TBFLAG_NS_SHIFT 19 2631 #define ARM_TBFLAG_NS_MASK (1 << ARM_TBFLAG_NS_SHIFT) 2632 #define ARM_TBFLAG_BE_DATA_SHIFT 20 2633 #define ARM_TBFLAG_BE_DATA_MASK (1 << ARM_TBFLAG_BE_DATA_SHIFT) 2634 /* For M profile only, Handler (ie not Thread) mode */ 2635 #define ARM_TBFLAG_HANDLER_SHIFT 21 2636 #define ARM_TBFLAG_HANDLER_MASK (1 << ARM_TBFLAG_HANDLER_SHIFT) 2637 2638 /* Bit usage when in AArch64 state */ 2639 #define ARM_TBFLAG_TBI0_SHIFT 0 /* TBI0 for EL0/1 or TBI for EL2/3 */ 2640 #define ARM_TBFLAG_TBI0_MASK (0x1ull << ARM_TBFLAG_TBI0_SHIFT) 2641 #define ARM_TBFLAG_TBI1_SHIFT 1 /* TBI1 for EL0/1 */ 2642 #define ARM_TBFLAG_TBI1_MASK (0x1ull << ARM_TBFLAG_TBI1_SHIFT) 2643 2644 /* some convenience accessor macros */ 2645 #define ARM_TBFLAG_AARCH64_STATE(F) \ 2646 (((F) & ARM_TBFLAG_AARCH64_STATE_MASK) >> ARM_TBFLAG_AARCH64_STATE_SHIFT) 2647 #define ARM_TBFLAG_MMUIDX(F) \ 2648 (((F) & ARM_TBFLAG_MMUIDX_MASK) >> ARM_TBFLAG_MMUIDX_SHIFT) 2649 #define ARM_TBFLAG_SS_ACTIVE(F) \ 2650 (((F) & ARM_TBFLAG_SS_ACTIVE_MASK) >> ARM_TBFLAG_SS_ACTIVE_SHIFT) 2651 #define ARM_TBFLAG_PSTATE_SS(F) \ 2652 (((F) & ARM_TBFLAG_PSTATE_SS_MASK) >> ARM_TBFLAG_PSTATE_SS_SHIFT) 2653 #define ARM_TBFLAG_FPEXC_EL(F) \ 2654 (((F) & ARM_TBFLAG_FPEXC_EL_MASK) >> ARM_TBFLAG_FPEXC_EL_SHIFT) 2655 #define ARM_TBFLAG_THUMB(F) \ 2656 (((F) & ARM_TBFLAG_THUMB_MASK) >> ARM_TBFLAG_THUMB_SHIFT) 2657 #define ARM_TBFLAG_VECLEN(F) \ 2658 (((F) & ARM_TBFLAG_VECLEN_MASK) >> ARM_TBFLAG_VECLEN_SHIFT) 2659 #define ARM_TBFLAG_VECSTRIDE(F) \ 2660 (((F) & ARM_TBFLAG_VECSTRIDE_MASK) >> ARM_TBFLAG_VECSTRIDE_SHIFT) 2661 #define ARM_TBFLAG_VFPEN(F) \ 2662 (((F) & ARM_TBFLAG_VFPEN_MASK) >> ARM_TBFLAG_VFPEN_SHIFT) 2663 #define ARM_TBFLAG_CONDEXEC(F) \ 2664 (((F) & ARM_TBFLAG_CONDEXEC_MASK) >> ARM_TBFLAG_CONDEXEC_SHIFT) 2665 #define ARM_TBFLAG_SCTLR_B(F) \ 2666 (((F) & ARM_TBFLAG_SCTLR_B_MASK) >> ARM_TBFLAG_SCTLR_B_SHIFT) 2667 #define ARM_TBFLAG_XSCALE_CPAR(F) \ 2668 (((F) & ARM_TBFLAG_XSCALE_CPAR_MASK) >> ARM_TBFLAG_XSCALE_CPAR_SHIFT) 2669 #define ARM_TBFLAG_NS(F) \ 2670 (((F) & ARM_TBFLAG_NS_MASK) >> ARM_TBFLAG_NS_SHIFT) 2671 #define ARM_TBFLAG_BE_DATA(F) \ 2672 (((F) & ARM_TBFLAG_BE_DATA_MASK) >> ARM_TBFLAG_BE_DATA_SHIFT) 2673 #define ARM_TBFLAG_HANDLER(F) \ 2674 (((F) & ARM_TBFLAG_HANDLER_MASK) >> ARM_TBFLAG_HANDLER_SHIFT) 2675 #define ARM_TBFLAG_TBI0(F) \ 2676 (((F) & ARM_TBFLAG_TBI0_MASK) >> ARM_TBFLAG_TBI0_SHIFT) 2677 #define ARM_TBFLAG_TBI1(F) \ 2678 (((F) & ARM_TBFLAG_TBI1_MASK) >> ARM_TBFLAG_TBI1_SHIFT) 2679 2680 static inline bool bswap_code(bool sctlr_b) 2681 { 2682 #ifdef CONFIG_USER_ONLY 2683 /* BE8 (SCTLR.B = 0, TARGET_WORDS_BIGENDIAN = 1) is mixed endian. 2684 * The invalid combination SCTLR.B=1/CPSR.E=1/TARGET_WORDS_BIGENDIAN=0 2685 * would also end up as a mixed-endian mode with BE code, LE data. 2686 */ 2687 return 2688 #ifdef TARGET_WORDS_BIGENDIAN 2689 1 ^ 2690 #endif 2691 sctlr_b; 2692 #else 2693 /* All code access in ARM is little endian, and there are no loaders 2694 * doing swaps that need to be reversed 2695 */ 2696 return 0; 2697 #endif 2698 } 2699 2700 #ifdef CONFIG_USER_ONLY 2701 static inline bool arm_cpu_bswap_data(CPUARMState *env) 2702 { 2703 return 2704 #ifdef TARGET_WORDS_BIGENDIAN 2705 1 ^ 2706 #endif 2707 arm_cpu_data_is_big_endian(env); 2708 } 2709 #endif 2710 2711 #ifndef CONFIG_USER_ONLY 2712 /** 2713 * arm_regime_tbi0: 2714 * @env: CPUARMState 2715 * @mmu_idx: MMU index indicating required translation regime 2716 * 2717 * Extracts the TBI0 value from the appropriate TCR for the current EL 2718 * 2719 * Returns: the TBI0 value. 2720 */ 2721 uint32_t arm_regime_tbi0(CPUARMState *env, ARMMMUIdx mmu_idx); 2722 2723 /** 2724 * arm_regime_tbi1: 2725 * @env: CPUARMState 2726 * @mmu_idx: MMU index indicating required translation regime 2727 * 2728 * Extracts the TBI1 value from the appropriate TCR for the current EL 2729 * 2730 * Returns: the TBI1 value. 2731 */ 2732 uint32_t arm_regime_tbi1(CPUARMState *env, ARMMMUIdx mmu_idx); 2733 #else 2734 /* We can't handle tagged addresses properly in user-only mode */ 2735 static inline uint32_t arm_regime_tbi0(CPUARMState *env, ARMMMUIdx mmu_idx) 2736 { 2737 return 0; 2738 } 2739 2740 static inline uint32_t arm_regime_tbi1(CPUARMState *env, ARMMMUIdx mmu_idx) 2741 { 2742 return 0; 2743 } 2744 #endif 2745 2746 void cpu_get_tb_cpu_state(CPUARMState *env, target_ulong *pc, 2747 target_ulong *cs_base, uint32_t *flags); 2748 2749 enum { 2750 QEMU_PSCI_CONDUIT_DISABLED = 0, 2751 QEMU_PSCI_CONDUIT_SMC = 1, 2752 QEMU_PSCI_CONDUIT_HVC = 2, 2753 }; 2754 2755 #ifndef CONFIG_USER_ONLY 2756 /* Return the address space index to use for a memory access */ 2757 static inline int arm_asidx_from_attrs(CPUState *cs, MemTxAttrs attrs) 2758 { 2759 return attrs.secure ? ARMASIdx_S : ARMASIdx_NS; 2760 } 2761 2762 /* Return the AddressSpace to use for a memory access 2763 * (which depends on whether the access is S or NS, and whether 2764 * the board gave us a separate AddressSpace for S accesses). 2765 */ 2766 static inline AddressSpace *arm_addressspace(CPUState *cs, MemTxAttrs attrs) 2767 { 2768 return cpu_get_address_space(cs, arm_asidx_from_attrs(cs, attrs)); 2769 } 2770 #endif 2771 2772 /** 2773 * arm_register_el_change_hook: 2774 * Register a hook function which will be called back whenever this 2775 * CPU changes exception level or mode. The hook function will be 2776 * passed a pointer to the ARMCPU and the opaque data pointer passed 2777 * to this function when the hook was registered. 2778 * 2779 * Note that we currently only support registering a single hook function, 2780 * and will assert if this function is called twice. 2781 * This facility is intended for the use of the GICv3 emulation. 2782 */ 2783 void arm_register_el_change_hook(ARMCPU *cpu, ARMELChangeHook *hook, 2784 void *opaque); 2785 2786 /** 2787 * arm_get_el_change_hook_opaque: 2788 * Return the opaque data that will be used by the el_change_hook 2789 * for this CPU. 2790 */ 2791 static inline void *arm_get_el_change_hook_opaque(ARMCPU *cpu) 2792 { 2793 return cpu->el_change_hook_opaque; 2794 } 2795 2796 /** 2797 * aa32_vfp_dreg: 2798 * Return a pointer to the Dn register within env in 32-bit mode. 2799 */ 2800 static inline uint64_t *aa32_vfp_dreg(CPUARMState *env, unsigned regno) 2801 { 2802 return &env->vfp.regs[regno]; 2803 } 2804 2805 /** 2806 * aa32_vfp_qreg: 2807 * Return a pointer to the Qn register within env in 32-bit mode. 2808 */ 2809 static inline uint64_t *aa32_vfp_qreg(CPUARMState *env, unsigned regno) 2810 { 2811 return &env->vfp.regs[2 * regno]; 2812 } 2813 2814 /** 2815 * aa64_vfp_qreg: 2816 * Return a pointer to the Qn register within env in 64-bit mode. 2817 */ 2818 static inline uint64_t *aa64_vfp_qreg(CPUARMState *env, unsigned regno) 2819 { 2820 return &env->vfp.regs[2 * regno]; 2821 } 2822 2823 #endif 2824