1 /* 2 * ARM virtual CPU header 3 * 4 * Copyright (c) 2003 Fabrice Bellard 5 * 6 * This library is free software; you can redistribute it and/or 7 * modify it under the terms of the GNU Lesser General Public 8 * License as published by the Free Software Foundation; either 9 * version 2 of the License, or (at your option) any later version. 10 * 11 * This library is distributed in the hope that it will be useful, 12 * but WITHOUT ANY WARRANTY; without even the implied warranty of 13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU 14 * Lesser General Public License for more details. 15 * 16 * You should have received a copy of the GNU Lesser General Public 17 * License along with this library; if not, see <http://www.gnu.org/licenses/>. 18 */ 19 20 #ifndef ARM_CPU_H 21 #define ARM_CPU_H 22 23 #include "kvm-consts.h" 24 #include "hw/registerfields.h" 25 26 #if defined(TARGET_AARCH64) 27 /* AArch64 definitions */ 28 # define TARGET_LONG_BITS 64 29 #else 30 # define TARGET_LONG_BITS 32 31 #endif 32 33 /* ARM processors have a weak memory model */ 34 #define TCG_GUEST_DEFAULT_MO (0) 35 36 #define CPUArchState struct CPUARMState 37 38 #include "qemu-common.h" 39 #include "cpu-qom.h" 40 #include "exec/cpu-defs.h" 41 42 #include "fpu/softfloat.h" 43 44 #define EXCP_UDEF 1 /* undefined instruction */ 45 #define EXCP_SWI 2 /* software interrupt */ 46 #define EXCP_PREFETCH_ABORT 3 47 #define EXCP_DATA_ABORT 4 48 #define EXCP_IRQ 5 49 #define EXCP_FIQ 6 50 #define EXCP_BKPT 7 51 #define EXCP_EXCEPTION_EXIT 8 /* Return from v7M exception. */ 52 #define EXCP_KERNEL_TRAP 9 /* Jumped to kernel code page. */ 53 #define EXCP_HVC 11 /* HyperVisor Call */ 54 #define EXCP_HYP_TRAP 12 55 #define EXCP_SMC 13 /* Secure Monitor Call */ 56 #define EXCP_VIRQ 14 57 #define EXCP_VFIQ 15 58 #define EXCP_SEMIHOST 16 /* semihosting call */ 59 #define EXCP_NOCP 17 /* v7M NOCP UsageFault */ 60 #define EXCP_INVSTATE 18 /* v7M INVSTATE UsageFault */ 61 /* NB: add new EXCP_ defines to the array in arm_log_exception() too */ 62 63 #define ARMV7M_EXCP_RESET 1 64 #define ARMV7M_EXCP_NMI 2 65 #define ARMV7M_EXCP_HARD 3 66 #define ARMV7M_EXCP_MEM 4 67 #define ARMV7M_EXCP_BUS 5 68 #define ARMV7M_EXCP_USAGE 6 69 #define ARMV7M_EXCP_SECURE 7 70 #define ARMV7M_EXCP_SVC 11 71 #define ARMV7M_EXCP_DEBUG 12 72 #define ARMV7M_EXCP_PENDSV 14 73 #define ARMV7M_EXCP_SYSTICK 15 74 75 /* For M profile, some registers are banked secure vs non-secure; 76 * these are represented as a 2-element array where the first element 77 * is the non-secure copy and the second is the secure copy. 78 * When the CPU does not have implement the security extension then 79 * only the first element is used. 80 * This means that the copy for the current security state can be 81 * accessed via env->registerfield[env->v7m.secure] (whether the security 82 * extension is implemented or not). 83 */ 84 enum { 85 M_REG_NS = 0, 86 M_REG_S = 1, 87 M_REG_NUM_BANKS = 2, 88 }; 89 90 /* ARM-specific interrupt pending bits. */ 91 #define CPU_INTERRUPT_FIQ CPU_INTERRUPT_TGT_EXT_1 92 #define CPU_INTERRUPT_VIRQ CPU_INTERRUPT_TGT_EXT_2 93 #define CPU_INTERRUPT_VFIQ CPU_INTERRUPT_TGT_EXT_3 94 95 /* The usual mapping for an AArch64 system register to its AArch32 96 * counterpart is for the 32 bit world to have access to the lower 97 * half only (with writes leaving the upper half untouched). It's 98 * therefore useful to be able to pass TCG the offset of the least 99 * significant half of a uint64_t struct member. 100 */ 101 #ifdef HOST_WORDS_BIGENDIAN 102 #define offsetoflow32(S, M) (offsetof(S, M) + sizeof(uint32_t)) 103 #define offsetofhigh32(S, M) offsetof(S, M) 104 #else 105 #define offsetoflow32(S, M) offsetof(S, M) 106 #define offsetofhigh32(S, M) (offsetof(S, M) + sizeof(uint32_t)) 107 #endif 108 109 /* Meanings of the ARMCPU object's four inbound GPIO lines */ 110 #define ARM_CPU_IRQ 0 111 #define ARM_CPU_FIQ 1 112 #define ARM_CPU_VIRQ 2 113 #define ARM_CPU_VFIQ 3 114 115 #define NB_MMU_MODES 8 116 /* ARM-specific extra insn start words: 117 * 1: Conditional execution bits 118 * 2: Partial exception syndrome for data aborts 119 */ 120 #define TARGET_INSN_START_EXTRA_WORDS 2 121 122 /* The 2nd extra word holding syndrome info for data aborts does not use 123 * the upper 6 bits nor the lower 14 bits. We mask and shift it down to 124 * help the sleb128 encoder do a better job. 125 * When restoring the CPU state, we shift it back up. 126 */ 127 #define ARM_INSN_START_WORD2_MASK ((1 << 26) - 1) 128 #define ARM_INSN_START_WORD2_SHIFT 14 129 130 /* We currently assume float and double are IEEE single and double 131 precision respectively. 132 Doing runtime conversions is tricky because VFP registers may contain 133 integer values (eg. as the result of a FTOSI instruction). 134 s<2n> maps to the least significant half of d<n> 135 s<2n+1> maps to the most significant half of d<n> 136 */ 137 138 /* CPU state for each instance of a generic timer (in cp15 c14) */ 139 typedef struct ARMGenericTimer { 140 uint64_t cval; /* Timer CompareValue register */ 141 uint64_t ctl; /* Timer Control register */ 142 } ARMGenericTimer; 143 144 #define GTIMER_PHYS 0 145 #define GTIMER_VIRT 1 146 #define GTIMER_HYP 2 147 #define GTIMER_SEC 3 148 #define NUM_GTIMERS 4 149 150 typedef struct { 151 uint64_t raw_tcr; 152 uint32_t mask; 153 uint32_t base_mask; 154 } TCR; 155 156 /* Define a maximum sized vector register. 157 * For 32-bit, this is a 128-bit NEON/AdvSIMD register. 158 * For 64-bit, this is a 2048-bit SVE register. 159 * 160 * Note that the mapping between S, D, and Q views of the register bank 161 * differs between AArch64 and AArch32. 162 * In AArch32: 163 * Qn = regs[n].d[1]:regs[n].d[0] 164 * Dn = regs[n / 2].d[n & 1] 165 * Sn = regs[n / 4].d[n % 4 / 2], 166 * bits 31..0 for even n, and bits 63..32 for odd n 167 * (and regs[16] to regs[31] are inaccessible) 168 * In AArch64: 169 * Zn = regs[n].d[*] 170 * Qn = regs[n].d[1]:regs[n].d[0] 171 * Dn = regs[n].d[0] 172 * Sn = regs[n].d[0] bits 31..0 173 * 174 * This corresponds to the architecturally defined mapping between 175 * the two execution states, and means we do not need to explicitly 176 * map these registers when changing states. 177 * 178 * Align the data for use with TCG host vector operations. 179 */ 180 181 #ifdef TARGET_AARCH64 182 # define ARM_MAX_VQ 16 183 #else 184 # define ARM_MAX_VQ 1 185 #endif 186 187 typedef struct ARMVectorReg { 188 uint64_t d[2 * ARM_MAX_VQ] QEMU_ALIGNED(16); 189 } ARMVectorReg; 190 191 /* In AArch32 mode, predicate registers do not exist at all. */ 192 #ifdef TARGET_AARCH64 193 typedef struct ARMPredicateReg { 194 uint64_t p[2 * ARM_MAX_VQ / 8] QEMU_ALIGNED(16); 195 } ARMPredicateReg; 196 #endif 197 198 199 typedef struct CPUARMState { 200 /* Regs for current mode. */ 201 uint32_t regs[16]; 202 203 /* 32/64 switch only happens when taking and returning from 204 * exceptions so the overlap semantics are taken care of then 205 * instead of having a complicated union. 206 */ 207 /* Regs for A64 mode. */ 208 uint64_t xregs[32]; 209 uint64_t pc; 210 /* PSTATE isn't an architectural register for ARMv8. However, it is 211 * convenient for us to assemble the underlying state into a 32 bit format 212 * identical to the architectural format used for the SPSR. (This is also 213 * what the Linux kernel's 'pstate' field in signal handlers and KVM's 214 * 'pstate' register are.) Of the PSTATE bits: 215 * NZCV are kept in the split out env->CF/VF/NF/ZF, (which have the same 216 * semantics as for AArch32, as described in the comments on each field) 217 * nRW (also known as M[4]) is kept, inverted, in env->aarch64 218 * DAIF (exception masks) are kept in env->daif 219 * all other bits are stored in their correct places in env->pstate 220 */ 221 uint32_t pstate; 222 uint32_t aarch64; /* 1 if CPU is in aarch64 state; inverse of PSTATE.nRW */ 223 224 /* Frequently accessed CPSR bits are stored separately for efficiency. 225 This contains all the other bits. Use cpsr_{read,write} to access 226 the whole CPSR. */ 227 uint32_t uncached_cpsr; 228 uint32_t spsr; 229 230 /* Banked registers. */ 231 uint64_t banked_spsr[8]; 232 uint32_t banked_r13[8]; 233 uint32_t banked_r14[8]; 234 235 /* These hold r8-r12. */ 236 uint32_t usr_regs[5]; 237 uint32_t fiq_regs[5]; 238 239 /* cpsr flag cache for faster execution */ 240 uint32_t CF; /* 0 or 1 */ 241 uint32_t VF; /* V is the bit 31. All other bits are undefined */ 242 uint32_t NF; /* N is bit 31. All other bits are undefined. */ 243 uint32_t ZF; /* Z set if zero. */ 244 uint32_t QF; /* 0 or 1 */ 245 uint32_t GE; /* cpsr[19:16] */ 246 uint32_t thumb; /* cpsr[5]. 0 = arm mode, 1 = thumb mode. */ 247 uint32_t condexec_bits; /* IT bits. cpsr[15:10,26:25]. */ 248 uint64_t daif; /* exception masks, in the bits they are in PSTATE */ 249 250 uint64_t elr_el[4]; /* AArch64 exception link regs */ 251 uint64_t sp_el[4]; /* AArch64 banked stack pointers */ 252 253 /* System control coprocessor (cp15) */ 254 struct { 255 uint32_t c0_cpuid; 256 union { /* Cache size selection */ 257 struct { 258 uint64_t _unused_csselr0; 259 uint64_t csselr_ns; 260 uint64_t _unused_csselr1; 261 uint64_t csselr_s; 262 }; 263 uint64_t csselr_el[4]; 264 }; 265 union { /* System control register. */ 266 struct { 267 uint64_t _unused_sctlr; 268 uint64_t sctlr_ns; 269 uint64_t hsctlr; 270 uint64_t sctlr_s; 271 }; 272 uint64_t sctlr_el[4]; 273 }; 274 uint64_t cpacr_el1; /* Architectural feature access control register */ 275 uint64_t cptr_el[4]; /* ARMv8 feature trap registers */ 276 uint32_t c1_xscaleauxcr; /* XScale auxiliary control register. */ 277 uint64_t sder; /* Secure debug enable register. */ 278 uint32_t nsacr; /* Non-secure access control register. */ 279 union { /* MMU translation table base 0. */ 280 struct { 281 uint64_t _unused_ttbr0_0; 282 uint64_t ttbr0_ns; 283 uint64_t _unused_ttbr0_1; 284 uint64_t ttbr0_s; 285 }; 286 uint64_t ttbr0_el[4]; 287 }; 288 union { /* MMU translation table base 1. */ 289 struct { 290 uint64_t _unused_ttbr1_0; 291 uint64_t ttbr1_ns; 292 uint64_t _unused_ttbr1_1; 293 uint64_t ttbr1_s; 294 }; 295 uint64_t ttbr1_el[4]; 296 }; 297 uint64_t vttbr_el2; /* Virtualization Translation Table Base. */ 298 /* MMU translation table base control. */ 299 TCR tcr_el[4]; 300 TCR vtcr_el2; /* Virtualization Translation Control. */ 301 uint32_t c2_data; /* MPU data cacheable bits. */ 302 uint32_t c2_insn; /* MPU instruction cacheable bits. */ 303 union { /* MMU domain access control register 304 * MPU write buffer control. 305 */ 306 struct { 307 uint64_t dacr_ns; 308 uint64_t dacr_s; 309 }; 310 struct { 311 uint64_t dacr32_el2; 312 }; 313 }; 314 uint32_t pmsav5_data_ap; /* PMSAv5 MPU data access permissions */ 315 uint32_t pmsav5_insn_ap; /* PMSAv5 MPU insn access permissions */ 316 uint64_t hcr_el2; /* Hypervisor configuration register */ 317 uint64_t scr_el3; /* Secure configuration register. */ 318 union { /* Fault status registers. */ 319 struct { 320 uint64_t ifsr_ns; 321 uint64_t ifsr_s; 322 }; 323 struct { 324 uint64_t ifsr32_el2; 325 }; 326 }; 327 union { 328 struct { 329 uint64_t _unused_dfsr; 330 uint64_t dfsr_ns; 331 uint64_t hsr; 332 uint64_t dfsr_s; 333 }; 334 uint64_t esr_el[4]; 335 }; 336 uint32_t c6_region[8]; /* MPU base/size registers. */ 337 union { /* Fault address registers. */ 338 struct { 339 uint64_t _unused_far0; 340 #ifdef HOST_WORDS_BIGENDIAN 341 uint32_t ifar_ns; 342 uint32_t dfar_ns; 343 uint32_t ifar_s; 344 uint32_t dfar_s; 345 #else 346 uint32_t dfar_ns; 347 uint32_t ifar_ns; 348 uint32_t dfar_s; 349 uint32_t ifar_s; 350 #endif 351 uint64_t _unused_far3; 352 }; 353 uint64_t far_el[4]; 354 }; 355 uint64_t hpfar_el2; 356 uint64_t hstr_el2; 357 union { /* Translation result. */ 358 struct { 359 uint64_t _unused_par_0; 360 uint64_t par_ns; 361 uint64_t _unused_par_1; 362 uint64_t par_s; 363 }; 364 uint64_t par_el[4]; 365 }; 366 367 uint32_t c9_insn; /* Cache lockdown registers. */ 368 uint32_t c9_data; 369 uint64_t c9_pmcr; /* performance monitor control register */ 370 uint64_t c9_pmcnten; /* perf monitor counter enables */ 371 uint32_t c9_pmovsr; /* perf monitor overflow status */ 372 uint32_t c9_pmuserenr; /* perf monitor user enable */ 373 uint64_t c9_pmselr; /* perf monitor counter selection register */ 374 uint64_t c9_pminten; /* perf monitor interrupt enables */ 375 union { /* Memory attribute redirection */ 376 struct { 377 #ifdef HOST_WORDS_BIGENDIAN 378 uint64_t _unused_mair_0; 379 uint32_t mair1_ns; 380 uint32_t mair0_ns; 381 uint64_t _unused_mair_1; 382 uint32_t mair1_s; 383 uint32_t mair0_s; 384 #else 385 uint64_t _unused_mair_0; 386 uint32_t mair0_ns; 387 uint32_t mair1_ns; 388 uint64_t _unused_mair_1; 389 uint32_t mair0_s; 390 uint32_t mair1_s; 391 #endif 392 }; 393 uint64_t mair_el[4]; 394 }; 395 union { /* vector base address register */ 396 struct { 397 uint64_t _unused_vbar; 398 uint64_t vbar_ns; 399 uint64_t hvbar; 400 uint64_t vbar_s; 401 }; 402 uint64_t vbar_el[4]; 403 }; 404 uint32_t mvbar; /* (monitor) vector base address register */ 405 struct { /* FCSE PID. */ 406 uint32_t fcseidr_ns; 407 uint32_t fcseidr_s; 408 }; 409 union { /* Context ID. */ 410 struct { 411 uint64_t _unused_contextidr_0; 412 uint64_t contextidr_ns; 413 uint64_t _unused_contextidr_1; 414 uint64_t contextidr_s; 415 }; 416 uint64_t contextidr_el[4]; 417 }; 418 union { /* User RW Thread register. */ 419 struct { 420 uint64_t tpidrurw_ns; 421 uint64_t tpidrprw_ns; 422 uint64_t htpidr; 423 uint64_t _tpidr_el3; 424 }; 425 uint64_t tpidr_el[4]; 426 }; 427 /* The secure banks of these registers don't map anywhere */ 428 uint64_t tpidrurw_s; 429 uint64_t tpidrprw_s; 430 uint64_t tpidruro_s; 431 432 union { /* User RO Thread register. */ 433 uint64_t tpidruro_ns; 434 uint64_t tpidrro_el[1]; 435 }; 436 uint64_t c14_cntfrq; /* Counter Frequency register */ 437 uint64_t c14_cntkctl; /* Timer Control register */ 438 uint32_t cnthctl_el2; /* Counter/Timer Hyp Control register */ 439 uint64_t cntvoff_el2; /* Counter Virtual Offset register */ 440 ARMGenericTimer c14_timer[NUM_GTIMERS]; 441 uint32_t c15_cpar; /* XScale Coprocessor Access Register */ 442 uint32_t c15_ticonfig; /* TI925T configuration byte. */ 443 uint32_t c15_i_max; /* Maximum D-cache dirty line index. */ 444 uint32_t c15_i_min; /* Minimum D-cache dirty line index. */ 445 uint32_t c15_threadid; /* TI debugger thread-ID. */ 446 uint32_t c15_config_base_address; /* SCU base address. */ 447 uint32_t c15_diagnostic; /* diagnostic register */ 448 uint32_t c15_power_diagnostic; 449 uint32_t c15_power_control; /* power control */ 450 uint64_t dbgbvr[16]; /* breakpoint value registers */ 451 uint64_t dbgbcr[16]; /* breakpoint control registers */ 452 uint64_t dbgwvr[16]; /* watchpoint value registers */ 453 uint64_t dbgwcr[16]; /* watchpoint control registers */ 454 uint64_t mdscr_el1; 455 uint64_t oslsr_el1; /* OS Lock Status */ 456 uint64_t mdcr_el2; 457 uint64_t mdcr_el3; 458 /* If the counter is enabled, this stores the last time the counter 459 * was reset. Otherwise it stores the counter value 460 */ 461 uint64_t c15_ccnt; 462 uint64_t pmccfiltr_el0; /* Performance Monitor Filter Register */ 463 uint64_t vpidr_el2; /* Virtualization Processor ID Register */ 464 uint64_t vmpidr_el2; /* Virtualization Multiprocessor ID Register */ 465 } cp15; 466 467 struct { 468 /* M profile has up to 4 stack pointers: 469 * a Main Stack Pointer and a Process Stack Pointer for each 470 * of the Secure and Non-Secure states. (If the CPU doesn't support 471 * the security extension then it has only two SPs.) 472 * In QEMU we always store the currently active SP in regs[13], 473 * and the non-active SP for the current security state in 474 * v7m.other_sp. The stack pointers for the inactive security state 475 * are stored in other_ss_msp and other_ss_psp. 476 * switch_v7m_security_state() is responsible for rearranging them 477 * when we change security state. 478 */ 479 uint32_t other_sp; 480 uint32_t other_ss_msp; 481 uint32_t other_ss_psp; 482 uint32_t vecbase[M_REG_NUM_BANKS]; 483 uint32_t basepri[M_REG_NUM_BANKS]; 484 uint32_t control[M_REG_NUM_BANKS]; 485 uint32_t ccr[M_REG_NUM_BANKS]; /* Configuration and Control */ 486 uint32_t cfsr[M_REG_NUM_BANKS]; /* Configurable Fault Status */ 487 uint32_t hfsr; /* HardFault Status */ 488 uint32_t dfsr; /* Debug Fault Status Register */ 489 uint32_t sfsr; /* Secure Fault Status Register */ 490 uint32_t mmfar[M_REG_NUM_BANKS]; /* MemManage Fault Address */ 491 uint32_t bfar; /* BusFault Address */ 492 uint32_t sfar; /* Secure Fault Address Register */ 493 unsigned mpu_ctrl[M_REG_NUM_BANKS]; /* MPU_CTRL */ 494 int exception; 495 uint32_t primask[M_REG_NUM_BANKS]; 496 uint32_t faultmask[M_REG_NUM_BANKS]; 497 uint32_t aircr; /* only holds r/w state if security extn implemented */ 498 uint32_t secure; /* Is CPU in Secure state? (not guest visible) */ 499 uint32_t csselr[M_REG_NUM_BANKS]; 500 uint32_t scr[M_REG_NUM_BANKS]; 501 uint32_t msplim[M_REG_NUM_BANKS]; 502 uint32_t psplim[M_REG_NUM_BANKS]; 503 } v7m; 504 505 /* Information associated with an exception about to be taken: 506 * code which raises an exception must set cs->exception_index and 507 * the relevant parts of this structure; the cpu_do_interrupt function 508 * will then set the guest-visible registers as part of the exception 509 * entry process. 510 */ 511 struct { 512 uint32_t syndrome; /* AArch64 format syndrome register */ 513 uint32_t fsr; /* AArch32 format fault status register info */ 514 uint64_t vaddress; /* virtual addr associated with exception, if any */ 515 uint32_t target_el; /* EL the exception should be targeted for */ 516 /* If we implement EL2 we will also need to store information 517 * about the intermediate physical address for stage 2 faults. 518 */ 519 } exception; 520 521 /* Thumb-2 EE state. */ 522 uint32_t teecr; 523 uint32_t teehbr; 524 525 /* VFP coprocessor state. */ 526 struct { 527 ARMVectorReg zregs[32]; 528 529 #ifdef TARGET_AARCH64 530 /* Store FFR as pregs[16] to make it easier to treat as any other. */ 531 ARMPredicateReg pregs[17]; 532 #endif 533 534 uint32_t xregs[16]; 535 /* We store these fpcsr fields separately for convenience. */ 536 int vec_len; 537 int vec_stride; 538 539 /* scratch space when Tn are not sufficient. */ 540 uint32_t scratch[8]; 541 542 /* fp_status is the "normal" fp status. standard_fp_status retains 543 * values corresponding to the ARM "Standard FPSCR Value", ie 544 * default-NaN, flush-to-zero, round-to-nearest and is used by 545 * any operations (generally Neon) which the architecture defines 546 * as controlled by the standard FPSCR value rather than the FPSCR. 547 * 548 * To avoid having to transfer exception bits around, we simply 549 * say that the FPSCR cumulative exception flags are the logical 550 * OR of the flags in the two fp statuses. This relies on the 551 * only thing which needs to read the exception flags being 552 * an explicit FPSCR read. 553 */ 554 float_status fp_status; 555 float_status standard_fp_status; 556 557 /* ZCR_EL[1-3] */ 558 uint64_t zcr_el[4]; 559 } vfp; 560 uint64_t exclusive_addr; 561 uint64_t exclusive_val; 562 uint64_t exclusive_high; 563 564 /* iwMMXt coprocessor state. */ 565 struct { 566 uint64_t regs[16]; 567 uint64_t val; 568 569 uint32_t cregs[16]; 570 } iwmmxt; 571 572 #if defined(CONFIG_USER_ONLY) 573 /* For usermode syscall translation. */ 574 int eabi; 575 #endif 576 577 struct CPUBreakpoint *cpu_breakpoint[16]; 578 struct CPUWatchpoint *cpu_watchpoint[16]; 579 580 /* Fields up to this point are cleared by a CPU reset */ 581 struct {} end_reset_fields; 582 583 CPU_COMMON 584 585 /* Fields after CPU_COMMON are preserved across CPU reset. */ 586 587 /* Internal CPU feature flags. */ 588 uint64_t features; 589 590 /* PMSAv7 MPU */ 591 struct { 592 uint32_t *drbar; 593 uint32_t *drsr; 594 uint32_t *dracr; 595 uint32_t rnr[M_REG_NUM_BANKS]; 596 } pmsav7; 597 598 /* PMSAv8 MPU */ 599 struct { 600 /* The PMSAv8 implementation also shares some PMSAv7 config 601 * and state: 602 * pmsav7.rnr (region number register) 603 * pmsav7_dregion (number of configured regions) 604 */ 605 uint32_t *rbar[M_REG_NUM_BANKS]; 606 uint32_t *rlar[M_REG_NUM_BANKS]; 607 uint32_t mair0[M_REG_NUM_BANKS]; 608 uint32_t mair1[M_REG_NUM_BANKS]; 609 } pmsav8; 610 611 /* v8M SAU */ 612 struct { 613 uint32_t *rbar; 614 uint32_t *rlar; 615 uint32_t rnr; 616 uint32_t ctrl; 617 } sau; 618 619 void *nvic; 620 const struct arm_boot_info *boot_info; 621 /* Store GICv3CPUState to access from this struct */ 622 void *gicv3state; 623 } CPUARMState; 624 625 /** 626 * ARMELChangeHook: 627 * type of a function which can be registered via arm_register_el_change_hook() 628 * to get callbacks when the CPU changes its exception level or mode. 629 */ 630 typedef void ARMELChangeHook(ARMCPU *cpu, void *opaque); 631 632 633 /* These values map onto the return values for 634 * QEMU_PSCI_0_2_FN_AFFINITY_INFO */ 635 typedef enum ARMPSCIState { 636 PSCI_ON = 0, 637 PSCI_OFF = 1, 638 PSCI_ON_PENDING = 2 639 } ARMPSCIState; 640 641 /** 642 * ARMCPU: 643 * @env: #CPUARMState 644 * 645 * An ARM CPU core. 646 */ 647 struct ARMCPU { 648 /*< private >*/ 649 CPUState parent_obj; 650 /*< public >*/ 651 652 CPUARMState env; 653 654 /* Coprocessor information */ 655 GHashTable *cp_regs; 656 /* For marshalling (mostly coprocessor) register state between the 657 * kernel and QEMU (for KVM) and between two QEMUs (for migration), 658 * we use these arrays. 659 */ 660 /* List of register indexes managed via these arrays; (full KVM style 661 * 64 bit indexes, not CPRegInfo 32 bit indexes) 662 */ 663 uint64_t *cpreg_indexes; 664 /* Values of the registers (cpreg_indexes[i]'s value is cpreg_values[i]) */ 665 uint64_t *cpreg_values; 666 /* Length of the indexes, values, reset_values arrays */ 667 int32_t cpreg_array_len; 668 /* These are used only for migration: incoming data arrives in 669 * these fields and is sanity checked in post_load before copying 670 * to the working data structures above. 671 */ 672 uint64_t *cpreg_vmstate_indexes; 673 uint64_t *cpreg_vmstate_values; 674 int32_t cpreg_vmstate_array_len; 675 676 /* Timers used by the generic (architected) timer */ 677 QEMUTimer *gt_timer[NUM_GTIMERS]; 678 /* GPIO outputs for generic timer */ 679 qemu_irq gt_timer_outputs[NUM_GTIMERS]; 680 /* GPIO output for GICv3 maintenance interrupt signal */ 681 qemu_irq gicv3_maintenance_interrupt; 682 /* GPIO output for the PMU interrupt */ 683 qemu_irq pmu_interrupt; 684 685 /* MemoryRegion to use for secure physical accesses */ 686 MemoryRegion *secure_memory; 687 688 /* 'compatible' string for this CPU for Linux device trees */ 689 const char *dtb_compatible; 690 691 /* PSCI version for this CPU 692 * Bits[31:16] = Major Version 693 * Bits[15:0] = Minor Version 694 */ 695 uint32_t psci_version; 696 697 /* Should CPU start in PSCI powered-off state? */ 698 bool start_powered_off; 699 700 /* Current power state, access guarded by BQL */ 701 ARMPSCIState power_state; 702 703 /* CPU has virtualization extension */ 704 bool has_el2; 705 /* CPU has security extension */ 706 bool has_el3; 707 /* CPU has PMU (Performance Monitor Unit) */ 708 bool has_pmu; 709 710 /* CPU has memory protection unit */ 711 bool has_mpu; 712 /* PMSAv7 MPU number of supported regions */ 713 uint32_t pmsav7_dregion; 714 /* v8M SAU number of supported regions */ 715 uint32_t sau_sregion; 716 717 /* PSCI conduit used to invoke PSCI methods 718 * 0 - disabled, 1 - smc, 2 - hvc 719 */ 720 uint32_t psci_conduit; 721 722 /* [QEMU_]KVM_ARM_TARGET_* constant for this CPU, or 723 * QEMU_KVM_ARM_TARGET_NONE if the kernel doesn't support this CPU type. 724 */ 725 uint32_t kvm_target; 726 727 /* KVM init features for this CPU */ 728 uint32_t kvm_init_features[7]; 729 730 /* Uniprocessor system with MP extensions */ 731 bool mp_is_up; 732 733 /* The instance init functions for implementation-specific subclasses 734 * set these fields to specify the implementation-dependent values of 735 * various constant registers and reset values of non-constant 736 * registers. 737 * Some of these might become QOM properties eventually. 738 * Field names match the official register names as defined in the 739 * ARMv7AR ARM Architecture Reference Manual. A reset_ prefix 740 * is used for reset values of non-constant registers; no reset_ 741 * prefix means a constant register. 742 */ 743 uint32_t midr; 744 uint32_t revidr; 745 uint32_t reset_fpsid; 746 uint32_t mvfr0; 747 uint32_t mvfr1; 748 uint32_t mvfr2; 749 uint32_t ctr; 750 uint32_t reset_sctlr; 751 uint32_t id_pfr0; 752 uint32_t id_pfr1; 753 uint32_t id_dfr0; 754 uint32_t pmceid0; 755 uint32_t pmceid1; 756 uint32_t id_afr0; 757 uint32_t id_mmfr0; 758 uint32_t id_mmfr1; 759 uint32_t id_mmfr2; 760 uint32_t id_mmfr3; 761 uint32_t id_mmfr4; 762 uint32_t id_isar0; 763 uint32_t id_isar1; 764 uint32_t id_isar2; 765 uint32_t id_isar3; 766 uint32_t id_isar4; 767 uint32_t id_isar5; 768 uint64_t id_aa64pfr0; 769 uint64_t id_aa64pfr1; 770 uint64_t id_aa64dfr0; 771 uint64_t id_aa64dfr1; 772 uint64_t id_aa64afr0; 773 uint64_t id_aa64afr1; 774 uint64_t id_aa64isar0; 775 uint64_t id_aa64isar1; 776 uint64_t id_aa64mmfr0; 777 uint64_t id_aa64mmfr1; 778 uint32_t dbgdidr; 779 uint32_t clidr; 780 uint64_t mp_affinity; /* MP ID without feature bits */ 781 /* The elements of this array are the CCSIDR values for each cache, 782 * in the order L1DCache, L1ICache, L2DCache, L2ICache, etc. 783 */ 784 uint32_t ccsidr[16]; 785 uint64_t reset_cbar; 786 uint32_t reset_auxcr; 787 bool reset_hivecs; 788 /* DCZ blocksize, in log_2(words), ie low 4 bits of DCZID_EL0 */ 789 uint32_t dcz_blocksize; 790 uint64_t rvbar; 791 792 /* Configurable aspects of GIC cpu interface (which is part of the CPU) */ 793 int gic_num_lrs; /* number of list registers */ 794 int gic_vpribits; /* number of virtual priority bits */ 795 int gic_vprebits; /* number of virtual preemption bits */ 796 797 /* Whether the cfgend input is high (i.e. this CPU should reset into 798 * big-endian mode). This setting isn't used directly: instead it modifies 799 * the reset_sctlr value to have SCTLR_B or SCTLR_EE set, depending on the 800 * architecture version. 801 */ 802 bool cfgend; 803 804 ARMELChangeHook *el_change_hook; 805 void *el_change_hook_opaque; 806 807 int32_t node_id; /* NUMA node this CPU belongs to */ 808 809 /* Used to synchronize KVM and QEMU in-kernel device levels */ 810 uint8_t device_irq_level; 811 }; 812 813 static inline ARMCPU *arm_env_get_cpu(CPUARMState *env) 814 { 815 return container_of(env, ARMCPU, env); 816 } 817 818 uint64_t arm_cpu_mp_affinity(int idx, uint8_t clustersz); 819 820 #define ENV_GET_CPU(e) CPU(arm_env_get_cpu(e)) 821 822 #define ENV_OFFSET offsetof(ARMCPU, env) 823 824 #ifndef CONFIG_USER_ONLY 825 extern const struct VMStateDescription vmstate_arm_cpu; 826 #endif 827 828 void arm_cpu_do_interrupt(CPUState *cpu); 829 void arm_v7m_cpu_do_interrupt(CPUState *cpu); 830 bool arm_cpu_exec_interrupt(CPUState *cpu, int int_req); 831 832 void arm_cpu_dump_state(CPUState *cs, FILE *f, fprintf_function cpu_fprintf, 833 int flags); 834 835 hwaddr arm_cpu_get_phys_page_attrs_debug(CPUState *cpu, vaddr addr, 836 MemTxAttrs *attrs); 837 838 int arm_cpu_gdb_read_register(CPUState *cpu, uint8_t *buf, int reg); 839 int arm_cpu_gdb_write_register(CPUState *cpu, uint8_t *buf, int reg); 840 841 int arm_cpu_write_elf64_note(WriteCoreDumpFunction f, CPUState *cs, 842 int cpuid, void *opaque); 843 int arm_cpu_write_elf32_note(WriteCoreDumpFunction f, CPUState *cs, 844 int cpuid, void *opaque); 845 846 #ifdef TARGET_AARCH64 847 int aarch64_cpu_gdb_read_register(CPUState *cpu, uint8_t *buf, int reg); 848 int aarch64_cpu_gdb_write_register(CPUState *cpu, uint8_t *buf, int reg); 849 #endif 850 851 target_ulong do_arm_semihosting(CPUARMState *env); 852 void aarch64_sync_32_to_64(CPUARMState *env); 853 void aarch64_sync_64_to_32(CPUARMState *env); 854 855 static inline bool is_a64(CPUARMState *env) 856 { 857 return env->aarch64; 858 } 859 860 /* you can call this signal handler from your SIGBUS and SIGSEGV 861 signal handlers to inform the virtual CPU of exceptions. non zero 862 is returned if the signal was handled by the virtual CPU. */ 863 int cpu_arm_signal_handler(int host_signum, void *pinfo, 864 void *puc); 865 866 /** 867 * pmccntr_sync 868 * @env: CPUARMState 869 * 870 * Synchronises the counter in the PMCCNTR. This must always be called twice, 871 * once before any action that might affect the timer and again afterwards. 872 * The function is used to swap the state of the register if required. 873 * This only happens when not in user mode (!CONFIG_USER_ONLY) 874 */ 875 void pmccntr_sync(CPUARMState *env); 876 877 /* SCTLR bit meanings. Several bits have been reused in newer 878 * versions of the architecture; in that case we define constants 879 * for both old and new bit meanings. Code which tests against those 880 * bits should probably check or otherwise arrange that the CPU 881 * is the architectural version it expects. 882 */ 883 #define SCTLR_M (1U << 0) 884 #define SCTLR_A (1U << 1) 885 #define SCTLR_C (1U << 2) 886 #define SCTLR_W (1U << 3) /* up to v6; RAO in v7 */ 887 #define SCTLR_SA (1U << 3) 888 #define SCTLR_P (1U << 4) /* up to v5; RAO in v6 and v7 */ 889 #define SCTLR_SA0 (1U << 4) /* v8 onward, AArch64 only */ 890 #define SCTLR_D (1U << 5) /* up to v5; RAO in v6 */ 891 #define SCTLR_CP15BEN (1U << 5) /* v7 onward */ 892 #define SCTLR_L (1U << 6) /* up to v5; RAO in v6 and v7; RAZ in v8 */ 893 #define SCTLR_B (1U << 7) /* up to v6; RAZ in v7 */ 894 #define SCTLR_ITD (1U << 7) /* v8 onward */ 895 #define SCTLR_S (1U << 8) /* up to v6; RAZ in v7 */ 896 #define SCTLR_SED (1U << 8) /* v8 onward */ 897 #define SCTLR_R (1U << 9) /* up to v6; RAZ in v7 */ 898 #define SCTLR_UMA (1U << 9) /* v8 onward, AArch64 only */ 899 #define SCTLR_F (1U << 10) /* up to v6 */ 900 #define SCTLR_SW (1U << 10) /* v7 onward */ 901 #define SCTLR_Z (1U << 11) 902 #define SCTLR_I (1U << 12) 903 #define SCTLR_V (1U << 13) 904 #define SCTLR_RR (1U << 14) /* up to v7 */ 905 #define SCTLR_DZE (1U << 14) /* v8 onward, AArch64 only */ 906 #define SCTLR_L4 (1U << 15) /* up to v6; RAZ in v7 */ 907 #define SCTLR_UCT (1U << 15) /* v8 onward, AArch64 only */ 908 #define SCTLR_DT (1U << 16) /* up to ??, RAO in v6 and v7 */ 909 #define SCTLR_nTWI (1U << 16) /* v8 onward */ 910 #define SCTLR_HA (1U << 17) 911 #define SCTLR_BR (1U << 17) /* PMSA only */ 912 #define SCTLR_IT (1U << 18) /* up to ??, RAO in v6 and v7 */ 913 #define SCTLR_nTWE (1U << 18) /* v8 onward */ 914 #define SCTLR_WXN (1U << 19) 915 #define SCTLR_ST (1U << 20) /* up to ??, RAZ in v6 */ 916 #define SCTLR_UWXN (1U << 20) /* v7 onward */ 917 #define SCTLR_FI (1U << 21) 918 #define SCTLR_U (1U << 22) 919 #define SCTLR_XP (1U << 23) /* up to v6; v7 onward RAO */ 920 #define SCTLR_VE (1U << 24) /* up to v7 */ 921 #define SCTLR_E0E (1U << 24) /* v8 onward, AArch64 only */ 922 #define SCTLR_EE (1U << 25) 923 #define SCTLR_L2 (1U << 26) /* up to v6, RAZ in v7 */ 924 #define SCTLR_UCI (1U << 26) /* v8 onward, AArch64 only */ 925 #define SCTLR_NMFI (1U << 27) 926 #define SCTLR_TRE (1U << 28) 927 #define SCTLR_AFE (1U << 29) 928 #define SCTLR_TE (1U << 30) 929 930 #define CPTR_TCPAC (1U << 31) 931 #define CPTR_TTA (1U << 20) 932 #define CPTR_TFP (1U << 10) 933 #define CPTR_TZ (1U << 8) /* CPTR_EL2 */ 934 #define CPTR_EZ (1U << 8) /* CPTR_EL3 */ 935 936 #define MDCR_EPMAD (1U << 21) 937 #define MDCR_EDAD (1U << 20) 938 #define MDCR_SPME (1U << 17) 939 #define MDCR_SDD (1U << 16) 940 #define MDCR_SPD (3U << 14) 941 #define MDCR_TDRA (1U << 11) 942 #define MDCR_TDOSA (1U << 10) 943 #define MDCR_TDA (1U << 9) 944 #define MDCR_TDE (1U << 8) 945 #define MDCR_HPME (1U << 7) 946 #define MDCR_TPM (1U << 6) 947 #define MDCR_TPMCR (1U << 5) 948 949 /* Not all of the MDCR_EL3 bits are present in the 32-bit SDCR */ 950 #define SDCR_VALID_MASK (MDCR_EPMAD | MDCR_EDAD | MDCR_SPME | MDCR_SPD) 951 952 #define CPSR_M (0x1fU) 953 #define CPSR_T (1U << 5) 954 #define CPSR_F (1U << 6) 955 #define CPSR_I (1U << 7) 956 #define CPSR_A (1U << 8) 957 #define CPSR_E (1U << 9) 958 #define CPSR_IT_2_7 (0xfc00U) 959 #define CPSR_GE (0xfU << 16) 960 #define CPSR_IL (1U << 20) 961 /* Note that the RESERVED bits include bit 21, which is PSTATE_SS in 962 * an AArch64 SPSR but RES0 in AArch32 SPSR and CPSR. In QEMU we use 963 * env->uncached_cpsr bit 21 to store PSTATE.SS when executing in AArch32, 964 * where it is live state but not accessible to the AArch32 code. 965 */ 966 #define CPSR_RESERVED (0x7U << 21) 967 #define CPSR_J (1U << 24) 968 #define CPSR_IT_0_1 (3U << 25) 969 #define CPSR_Q (1U << 27) 970 #define CPSR_V (1U << 28) 971 #define CPSR_C (1U << 29) 972 #define CPSR_Z (1U << 30) 973 #define CPSR_N (1U << 31) 974 #define CPSR_NZCV (CPSR_N | CPSR_Z | CPSR_C | CPSR_V) 975 #define CPSR_AIF (CPSR_A | CPSR_I | CPSR_F) 976 977 #define CPSR_IT (CPSR_IT_0_1 | CPSR_IT_2_7) 978 #define CACHED_CPSR_BITS (CPSR_T | CPSR_AIF | CPSR_GE | CPSR_IT | CPSR_Q \ 979 | CPSR_NZCV) 980 /* Bits writable in user mode. */ 981 #define CPSR_USER (CPSR_NZCV | CPSR_Q | CPSR_GE) 982 /* Execution state bits. MRS read as zero, MSR writes ignored. */ 983 #define CPSR_EXEC (CPSR_T | CPSR_IT | CPSR_J | CPSR_IL) 984 /* Mask of bits which may be set by exception return copying them from SPSR */ 985 #define CPSR_ERET_MASK (~CPSR_RESERVED) 986 987 /* Bit definitions for M profile XPSR. Most are the same as CPSR. */ 988 #define XPSR_EXCP 0x1ffU 989 #define XPSR_SPREALIGN (1U << 9) /* Only set in exception stack frames */ 990 #define XPSR_IT_2_7 CPSR_IT_2_7 991 #define XPSR_GE CPSR_GE 992 #define XPSR_SFPA (1U << 20) /* Only set in exception stack frames */ 993 #define XPSR_T (1U << 24) /* Not the same as CPSR_T ! */ 994 #define XPSR_IT_0_1 CPSR_IT_0_1 995 #define XPSR_Q CPSR_Q 996 #define XPSR_V CPSR_V 997 #define XPSR_C CPSR_C 998 #define XPSR_Z CPSR_Z 999 #define XPSR_N CPSR_N 1000 #define XPSR_NZCV CPSR_NZCV 1001 #define XPSR_IT CPSR_IT 1002 1003 #define TTBCR_N (7U << 0) /* TTBCR.EAE==0 */ 1004 #define TTBCR_T0SZ (7U << 0) /* TTBCR.EAE==1 */ 1005 #define TTBCR_PD0 (1U << 4) 1006 #define TTBCR_PD1 (1U << 5) 1007 #define TTBCR_EPD0 (1U << 7) 1008 #define TTBCR_IRGN0 (3U << 8) 1009 #define TTBCR_ORGN0 (3U << 10) 1010 #define TTBCR_SH0 (3U << 12) 1011 #define TTBCR_T1SZ (3U << 16) 1012 #define TTBCR_A1 (1U << 22) 1013 #define TTBCR_EPD1 (1U << 23) 1014 #define TTBCR_IRGN1 (3U << 24) 1015 #define TTBCR_ORGN1 (3U << 26) 1016 #define TTBCR_SH1 (1U << 28) 1017 #define TTBCR_EAE (1U << 31) 1018 1019 /* Bit definitions for ARMv8 SPSR (PSTATE) format. 1020 * Only these are valid when in AArch64 mode; in 1021 * AArch32 mode SPSRs are basically CPSR-format. 1022 */ 1023 #define PSTATE_SP (1U) 1024 #define PSTATE_M (0xFU) 1025 #define PSTATE_nRW (1U << 4) 1026 #define PSTATE_F (1U << 6) 1027 #define PSTATE_I (1U << 7) 1028 #define PSTATE_A (1U << 8) 1029 #define PSTATE_D (1U << 9) 1030 #define PSTATE_IL (1U << 20) 1031 #define PSTATE_SS (1U << 21) 1032 #define PSTATE_V (1U << 28) 1033 #define PSTATE_C (1U << 29) 1034 #define PSTATE_Z (1U << 30) 1035 #define PSTATE_N (1U << 31) 1036 #define PSTATE_NZCV (PSTATE_N | PSTATE_Z | PSTATE_C | PSTATE_V) 1037 #define PSTATE_DAIF (PSTATE_D | PSTATE_A | PSTATE_I | PSTATE_F) 1038 #define CACHED_PSTATE_BITS (PSTATE_NZCV | PSTATE_DAIF) 1039 /* Mode values for AArch64 */ 1040 #define PSTATE_MODE_EL3h 13 1041 #define PSTATE_MODE_EL3t 12 1042 #define PSTATE_MODE_EL2h 9 1043 #define PSTATE_MODE_EL2t 8 1044 #define PSTATE_MODE_EL1h 5 1045 #define PSTATE_MODE_EL1t 4 1046 #define PSTATE_MODE_EL0t 0 1047 1048 /* Write a new value to v7m.exception, thus transitioning into or out 1049 * of Handler mode; this may result in a change of active stack pointer. 1050 */ 1051 void write_v7m_exception(CPUARMState *env, uint32_t new_exc); 1052 1053 /* Map EL and handler into a PSTATE_MODE. */ 1054 static inline unsigned int aarch64_pstate_mode(unsigned int el, bool handler) 1055 { 1056 return (el << 2) | handler; 1057 } 1058 1059 /* Return the current PSTATE value. For the moment we don't support 32<->64 bit 1060 * interprocessing, so we don't attempt to sync with the cpsr state used by 1061 * the 32 bit decoder. 1062 */ 1063 static inline uint32_t pstate_read(CPUARMState *env) 1064 { 1065 int ZF; 1066 1067 ZF = (env->ZF == 0); 1068 return (env->NF & 0x80000000) | (ZF << 30) 1069 | (env->CF << 29) | ((env->VF & 0x80000000) >> 3) 1070 | env->pstate | env->daif; 1071 } 1072 1073 static inline void pstate_write(CPUARMState *env, uint32_t val) 1074 { 1075 env->ZF = (~val) & PSTATE_Z; 1076 env->NF = val; 1077 env->CF = (val >> 29) & 1; 1078 env->VF = (val << 3) & 0x80000000; 1079 env->daif = val & PSTATE_DAIF; 1080 env->pstate = val & ~CACHED_PSTATE_BITS; 1081 } 1082 1083 /* Return the current CPSR value. */ 1084 uint32_t cpsr_read(CPUARMState *env); 1085 1086 typedef enum CPSRWriteType { 1087 CPSRWriteByInstr = 0, /* from guest MSR or CPS */ 1088 CPSRWriteExceptionReturn = 1, /* from guest exception return insn */ 1089 CPSRWriteRaw = 2, /* trust values, do not switch reg banks */ 1090 CPSRWriteByGDBStub = 3, /* from the GDB stub */ 1091 } CPSRWriteType; 1092 1093 /* Set the CPSR. Note that some bits of mask must be all-set or all-clear.*/ 1094 void cpsr_write(CPUARMState *env, uint32_t val, uint32_t mask, 1095 CPSRWriteType write_type); 1096 1097 /* Return the current xPSR value. */ 1098 static inline uint32_t xpsr_read(CPUARMState *env) 1099 { 1100 int ZF; 1101 ZF = (env->ZF == 0); 1102 return (env->NF & 0x80000000) | (ZF << 30) 1103 | (env->CF << 29) | ((env->VF & 0x80000000) >> 3) | (env->QF << 27) 1104 | (env->thumb << 24) | ((env->condexec_bits & 3) << 25) 1105 | ((env->condexec_bits & 0xfc) << 8) 1106 | env->v7m.exception; 1107 } 1108 1109 /* Set the xPSR. Note that some bits of mask must be all-set or all-clear. */ 1110 static inline void xpsr_write(CPUARMState *env, uint32_t val, uint32_t mask) 1111 { 1112 if (mask & XPSR_NZCV) { 1113 env->ZF = (~val) & XPSR_Z; 1114 env->NF = val; 1115 env->CF = (val >> 29) & 1; 1116 env->VF = (val << 3) & 0x80000000; 1117 } 1118 if (mask & XPSR_Q) { 1119 env->QF = ((val & XPSR_Q) != 0); 1120 } 1121 if (mask & XPSR_T) { 1122 env->thumb = ((val & XPSR_T) != 0); 1123 } 1124 if (mask & XPSR_IT_0_1) { 1125 env->condexec_bits &= ~3; 1126 env->condexec_bits |= (val >> 25) & 3; 1127 } 1128 if (mask & XPSR_IT_2_7) { 1129 env->condexec_bits &= 3; 1130 env->condexec_bits |= (val >> 8) & 0xfc; 1131 } 1132 if (mask & XPSR_EXCP) { 1133 /* Note that this only happens on exception exit */ 1134 write_v7m_exception(env, val & XPSR_EXCP); 1135 } 1136 } 1137 1138 #define HCR_VM (1ULL << 0) 1139 #define HCR_SWIO (1ULL << 1) 1140 #define HCR_PTW (1ULL << 2) 1141 #define HCR_FMO (1ULL << 3) 1142 #define HCR_IMO (1ULL << 4) 1143 #define HCR_AMO (1ULL << 5) 1144 #define HCR_VF (1ULL << 6) 1145 #define HCR_VI (1ULL << 7) 1146 #define HCR_VSE (1ULL << 8) 1147 #define HCR_FB (1ULL << 9) 1148 #define HCR_BSU_MASK (3ULL << 10) 1149 #define HCR_DC (1ULL << 12) 1150 #define HCR_TWI (1ULL << 13) 1151 #define HCR_TWE (1ULL << 14) 1152 #define HCR_TID0 (1ULL << 15) 1153 #define HCR_TID1 (1ULL << 16) 1154 #define HCR_TID2 (1ULL << 17) 1155 #define HCR_TID3 (1ULL << 18) 1156 #define HCR_TSC (1ULL << 19) 1157 #define HCR_TIDCP (1ULL << 20) 1158 #define HCR_TACR (1ULL << 21) 1159 #define HCR_TSW (1ULL << 22) 1160 #define HCR_TPC (1ULL << 23) 1161 #define HCR_TPU (1ULL << 24) 1162 #define HCR_TTLB (1ULL << 25) 1163 #define HCR_TVM (1ULL << 26) 1164 #define HCR_TGE (1ULL << 27) 1165 #define HCR_TDZ (1ULL << 28) 1166 #define HCR_HCD (1ULL << 29) 1167 #define HCR_TRVM (1ULL << 30) 1168 #define HCR_RW (1ULL << 31) 1169 #define HCR_CD (1ULL << 32) 1170 #define HCR_ID (1ULL << 33) 1171 #define HCR_MASK ((1ULL << 34) - 1) 1172 1173 #define SCR_NS (1U << 0) 1174 #define SCR_IRQ (1U << 1) 1175 #define SCR_FIQ (1U << 2) 1176 #define SCR_EA (1U << 3) 1177 #define SCR_FW (1U << 4) 1178 #define SCR_AW (1U << 5) 1179 #define SCR_NET (1U << 6) 1180 #define SCR_SMD (1U << 7) 1181 #define SCR_HCE (1U << 8) 1182 #define SCR_SIF (1U << 9) 1183 #define SCR_RW (1U << 10) 1184 #define SCR_ST (1U << 11) 1185 #define SCR_TWI (1U << 12) 1186 #define SCR_TWE (1U << 13) 1187 #define SCR_AARCH32_MASK (0x3fff & ~(SCR_RW | SCR_ST)) 1188 #define SCR_AARCH64_MASK (0x3fff & ~SCR_NET) 1189 1190 /* Return the current FPSCR value. */ 1191 uint32_t vfp_get_fpscr(CPUARMState *env); 1192 void vfp_set_fpscr(CPUARMState *env, uint32_t val); 1193 1194 /* For A64 the FPSCR is split into two logically distinct registers, 1195 * FPCR and FPSR. However since they still use non-overlapping bits 1196 * we store the underlying state in fpscr and just mask on read/write. 1197 */ 1198 #define FPSR_MASK 0xf800009f 1199 #define FPCR_MASK 0x07f79f00 1200 static inline uint32_t vfp_get_fpsr(CPUARMState *env) 1201 { 1202 return vfp_get_fpscr(env) & FPSR_MASK; 1203 } 1204 1205 static inline void vfp_set_fpsr(CPUARMState *env, uint32_t val) 1206 { 1207 uint32_t new_fpscr = (vfp_get_fpscr(env) & ~FPSR_MASK) | (val & FPSR_MASK); 1208 vfp_set_fpscr(env, new_fpscr); 1209 } 1210 1211 static inline uint32_t vfp_get_fpcr(CPUARMState *env) 1212 { 1213 return vfp_get_fpscr(env) & FPCR_MASK; 1214 } 1215 1216 static inline void vfp_set_fpcr(CPUARMState *env, uint32_t val) 1217 { 1218 uint32_t new_fpscr = (vfp_get_fpscr(env) & ~FPCR_MASK) | (val & FPCR_MASK); 1219 vfp_set_fpscr(env, new_fpscr); 1220 } 1221 1222 enum arm_cpu_mode { 1223 ARM_CPU_MODE_USR = 0x10, 1224 ARM_CPU_MODE_FIQ = 0x11, 1225 ARM_CPU_MODE_IRQ = 0x12, 1226 ARM_CPU_MODE_SVC = 0x13, 1227 ARM_CPU_MODE_MON = 0x16, 1228 ARM_CPU_MODE_ABT = 0x17, 1229 ARM_CPU_MODE_HYP = 0x1a, 1230 ARM_CPU_MODE_UND = 0x1b, 1231 ARM_CPU_MODE_SYS = 0x1f 1232 }; 1233 1234 /* VFP system registers. */ 1235 #define ARM_VFP_FPSID 0 1236 #define ARM_VFP_FPSCR 1 1237 #define ARM_VFP_MVFR2 5 1238 #define ARM_VFP_MVFR1 6 1239 #define ARM_VFP_MVFR0 7 1240 #define ARM_VFP_FPEXC 8 1241 #define ARM_VFP_FPINST 9 1242 #define ARM_VFP_FPINST2 10 1243 1244 /* iwMMXt coprocessor control registers. */ 1245 #define ARM_IWMMXT_wCID 0 1246 #define ARM_IWMMXT_wCon 1 1247 #define ARM_IWMMXT_wCSSF 2 1248 #define ARM_IWMMXT_wCASF 3 1249 #define ARM_IWMMXT_wCGR0 8 1250 #define ARM_IWMMXT_wCGR1 9 1251 #define ARM_IWMMXT_wCGR2 10 1252 #define ARM_IWMMXT_wCGR3 11 1253 1254 /* V7M CCR bits */ 1255 FIELD(V7M_CCR, NONBASETHRDENA, 0, 1) 1256 FIELD(V7M_CCR, USERSETMPEND, 1, 1) 1257 FIELD(V7M_CCR, UNALIGN_TRP, 3, 1) 1258 FIELD(V7M_CCR, DIV_0_TRP, 4, 1) 1259 FIELD(V7M_CCR, BFHFNMIGN, 8, 1) 1260 FIELD(V7M_CCR, STKALIGN, 9, 1) 1261 FIELD(V7M_CCR, DC, 16, 1) 1262 FIELD(V7M_CCR, IC, 17, 1) 1263 1264 /* V7M SCR bits */ 1265 FIELD(V7M_SCR, SLEEPONEXIT, 1, 1) 1266 FIELD(V7M_SCR, SLEEPDEEP, 2, 1) 1267 FIELD(V7M_SCR, SLEEPDEEPS, 3, 1) 1268 FIELD(V7M_SCR, SEVONPEND, 4, 1) 1269 1270 /* V7M AIRCR bits */ 1271 FIELD(V7M_AIRCR, VECTRESET, 0, 1) 1272 FIELD(V7M_AIRCR, VECTCLRACTIVE, 1, 1) 1273 FIELD(V7M_AIRCR, SYSRESETREQ, 2, 1) 1274 FIELD(V7M_AIRCR, SYSRESETREQS, 3, 1) 1275 FIELD(V7M_AIRCR, PRIGROUP, 8, 3) 1276 FIELD(V7M_AIRCR, BFHFNMINS, 13, 1) 1277 FIELD(V7M_AIRCR, PRIS, 14, 1) 1278 FIELD(V7M_AIRCR, ENDIANNESS, 15, 1) 1279 FIELD(V7M_AIRCR, VECTKEY, 16, 16) 1280 1281 /* V7M CFSR bits for MMFSR */ 1282 FIELD(V7M_CFSR, IACCVIOL, 0, 1) 1283 FIELD(V7M_CFSR, DACCVIOL, 1, 1) 1284 FIELD(V7M_CFSR, MUNSTKERR, 3, 1) 1285 FIELD(V7M_CFSR, MSTKERR, 4, 1) 1286 FIELD(V7M_CFSR, MLSPERR, 5, 1) 1287 FIELD(V7M_CFSR, MMARVALID, 7, 1) 1288 1289 /* V7M CFSR bits for BFSR */ 1290 FIELD(V7M_CFSR, IBUSERR, 8 + 0, 1) 1291 FIELD(V7M_CFSR, PRECISERR, 8 + 1, 1) 1292 FIELD(V7M_CFSR, IMPRECISERR, 8 + 2, 1) 1293 FIELD(V7M_CFSR, UNSTKERR, 8 + 3, 1) 1294 FIELD(V7M_CFSR, STKERR, 8 + 4, 1) 1295 FIELD(V7M_CFSR, LSPERR, 8 + 5, 1) 1296 FIELD(V7M_CFSR, BFARVALID, 8 + 7, 1) 1297 1298 /* V7M CFSR bits for UFSR */ 1299 FIELD(V7M_CFSR, UNDEFINSTR, 16 + 0, 1) 1300 FIELD(V7M_CFSR, INVSTATE, 16 + 1, 1) 1301 FIELD(V7M_CFSR, INVPC, 16 + 2, 1) 1302 FIELD(V7M_CFSR, NOCP, 16 + 3, 1) 1303 FIELD(V7M_CFSR, UNALIGNED, 16 + 8, 1) 1304 FIELD(V7M_CFSR, DIVBYZERO, 16 + 9, 1) 1305 1306 /* V7M CFSR bit masks covering all of the subregister bits */ 1307 FIELD(V7M_CFSR, MMFSR, 0, 8) 1308 FIELD(V7M_CFSR, BFSR, 8, 8) 1309 FIELD(V7M_CFSR, UFSR, 16, 16) 1310 1311 /* V7M HFSR bits */ 1312 FIELD(V7M_HFSR, VECTTBL, 1, 1) 1313 FIELD(V7M_HFSR, FORCED, 30, 1) 1314 FIELD(V7M_HFSR, DEBUGEVT, 31, 1) 1315 1316 /* V7M DFSR bits */ 1317 FIELD(V7M_DFSR, HALTED, 0, 1) 1318 FIELD(V7M_DFSR, BKPT, 1, 1) 1319 FIELD(V7M_DFSR, DWTTRAP, 2, 1) 1320 FIELD(V7M_DFSR, VCATCH, 3, 1) 1321 FIELD(V7M_DFSR, EXTERNAL, 4, 1) 1322 1323 /* V7M SFSR bits */ 1324 FIELD(V7M_SFSR, INVEP, 0, 1) 1325 FIELD(V7M_SFSR, INVIS, 1, 1) 1326 FIELD(V7M_SFSR, INVER, 2, 1) 1327 FIELD(V7M_SFSR, AUVIOL, 3, 1) 1328 FIELD(V7M_SFSR, INVTRAN, 4, 1) 1329 FIELD(V7M_SFSR, LSPERR, 5, 1) 1330 FIELD(V7M_SFSR, SFARVALID, 6, 1) 1331 FIELD(V7M_SFSR, LSERR, 7, 1) 1332 1333 /* v7M MPU_CTRL bits */ 1334 FIELD(V7M_MPU_CTRL, ENABLE, 0, 1) 1335 FIELD(V7M_MPU_CTRL, HFNMIENA, 1, 1) 1336 FIELD(V7M_MPU_CTRL, PRIVDEFENA, 2, 1) 1337 1338 /* v7M CLIDR bits */ 1339 FIELD(V7M_CLIDR, CTYPE_ALL, 0, 21) 1340 FIELD(V7M_CLIDR, LOUIS, 21, 3) 1341 FIELD(V7M_CLIDR, LOC, 24, 3) 1342 FIELD(V7M_CLIDR, LOUU, 27, 3) 1343 FIELD(V7M_CLIDR, ICB, 30, 2) 1344 1345 FIELD(V7M_CSSELR, IND, 0, 1) 1346 FIELD(V7M_CSSELR, LEVEL, 1, 3) 1347 /* We use the combination of InD and Level to index into cpu->ccsidr[]; 1348 * define a mask for this and check that it doesn't permit running off 1349 * the end of the array. 1350 */ 1351 FIELD(V7M_CSSELR, INDEX, 0, 4) 1352 1353 QEMU_BUILD_BUG_ON(ARRAY_SIZE(((ARMCPU *)0)->ccsidr) <= R_V7M_CSSELR_INDEX_MASK); 1354 1355 /* If adding a feature bit which corresponds to a Linux ELF 1356 * HWCAP bit, remember to update the feature-bit-to-hwcap 1357 * mapping in linux-user/elfload.c:get_elf_hwcap(). 1358 */ 1359 enum arm_features { 1360 ARM_FEATURE_VFP, 1361 ARM_FEATURE_AUXCR, /* ARM1026 Auxiliary control register. */ 1362 ARM_FEATURE_XSCALE, /* Intel XScale extensions. */ 1363 ARM_FEATURE_IWMMXT, /* Intel iwMMXt extension. */ 1364 ARM_FEATURE_V6, 1365 ARM_FEATURE_V6K, 1366 ARM_FEATURE_V7, 1367 ARM_FEATURE_THUMB2, 1368 ARM_FEATURE_PMSA, /* no MMU; may have Memory Protection Unit */ 1369 ARM_FEATURE_VFP3, 1370 ARM_FEATURE_VFP_FP16, 1371 ARM_FEATURE_NEON, 1372 ARM_FEATURE_THUMB_DIV, /* divide supported in Thumb encoding */ 1373 ARM_FEATURE_M, /* Microcontroller profile. */ 1374 ARM_FEATURE_OMAPCP, /* OMAP specific CP15 ops handling. */ 1375 ARM_FEATURE_THUMB2EE, 1376 ARM_FEATURE_V7MP, /* v7 Multiprocessing Extensions */ 1377 ARM_FEATURE_V4T, 1378 ARM_FEATURE_V5, 1379 ARM_FEATURE_STRONGARM, 1380 ARM_FEATURE_VAPA, /* cp15 VA to PA lookups */ 1381 ARM_FEATURE_ARM_DIV, /* divide supported in ARM encoding */ 1382 ARM_FEATURE_VFP4, /* VFPv4 (implies that NEON is v2) */ 1383 ARM_FEATURE_GENERIC_TIMER, 1384 ARM_FEATURE_MVFR, /* Media and VFP Feature Registers 0 and 1 */ 1385 ARM_FEATURE_DUMMY_C15_REGS, /* RAZ/WI all of cp15 crn=15 */ 1386 ARM_FEATURE_CACHE_TEST_CLEAN, /* 926/1026 style test-and-clean ops */ 1387 ARM_FEATURE_CACHE_DIRTY_REG, /* 1136/1176 cache dirty status register */ 1388 ARM_FEATURE_CACHE_BLOCK_OPS, /* v6 optional cache block operations */ 1389 ARM_FEATURE_MPIDR, /* has cp15 MPIDR */ 1390 ARM_FEATURE_PXN, /* has Privileged Execute Never bit */ 1391 ARM_FEATURE_LPAE, /* has Large Physical Address Extension */ 1392 ARM_FEATURE_V8, 1393 ARM_FEATURE_AARCH64, /* supports 64 bit mode */ 1394 ARM_FEATURE_V8_AES, /* implements AES part of v8 Crypto Extensions */ 1395 ARM_FEATURE_CBAR, /* has cp15 CBAR */ 1396 ARM_FEATURE_CRC, /* ARMv8 CRC instructions */ 1397 ARM_FEATURE_CBAR_RO, /* has cp15 CBAR and it is read-only */ 1398 ARM_FEATURE_EL2, /* has EL2 Virtualization support */ 1399 ARM_FEATURE_EL3, /* has EL3 Secure monitor support */ 1400 ARM_FEATURE_V8_SHA1, /* implements SHA1 part of v8 Crypto Extensions */ 1401 ARM_FEATURE_V8_SHA256, /* implements SHA256 part of v8 Crypto Extensions */ 1402 ARM_FEATURE_V8_PMULL, /* implements PMULL part of v8 Crypto Extensions */ 1403 ARM_FEATURE_THUMB_DSP, /* DSP insns supported in the Thumb encodings */ 1404 ARM_FEATURE_PMU, /* has PMU support */ 1405 ARM_FEATURE_VBAR, /* has cp15 VBAR */ 1406 ARM_FEATURE_M_SECURITY, /* M profile Security Extension */ 1407 ARM_FEATURE_JAZELLE, /* has (trivial) Jazelle implementation */ 1408 ARM_FEATURE_SVE, /* has Scalable Vector Extension */ 1409 ARM_FEATURE_V8_SHA512, /* implements SHA512 part of v8 Crypto Extensions */ 1410 ARM_FEATURE_V8_SHA3, /* implements SHA3 part of v8 Crypto Extensions */ 1411 ARM_FEATURE_V8_SM3, /* implements SM3 part of v8 Crypto Extensions */ 1412 ARM_FEATURE_V8_SM4, /* implements SM4 part of v8 Crypto Extensions */ 1413 }; 1414 1415 static inline int arm_feature(CPUARMState *env, int feature) 1416 { 1417 return (env->features & (1ULL << feature)) != 0; 1418 } 1419 1420 #if !defined(CONFIG_USER_ONLY) 1421 /* Return true if exception levels below EL3 are in secure state, 1422 * or would be following an exception return to that level. 1423 * Unlike arm_is_secure() (which is always a question about the 1424 * _current_ state of the CPU) this doesn't care about the current 1425 * EL or mode. 1426 */ 1427 static inline bool arm_is_secure_below_el3(CPUARMState *env) 1428 { 1429 if (arm_feature(env, ARM_FEATURE_EL3)) { 1430 return !(env->cp15.scr_el3 & SCR_NS); 1431 } else { 1432 /* If EL3 is not supported then the secure state is implementation 1433 * defined, in which case QEMU defaults to non-secure. 1434 */ 1435 return false; 1436 } 1437 } 1438 1439 /* Return true if the CPU is AArch64 EL3 or AArch32 Mon */ 1440 static inline bool arm_is_el3_or_mon(CPUARMState *env) 1441 { 1442 if (arm_feature(env, ARM_FEATURE_EL3)) { 1443 if (is_a64(env) && extract32(env->pstate, 2, 2) == 3) { 1444 /* CPU currently in AArch64 state and EL3 */ 1445 return true; 1446 } else if (!is_a64(env) && 1447 (env->uncached_cpsr & CPSR_M) == ARM_CPU_MODE_MON) { 1448 /* CPU currently in AArch32 state and monitor mode */ 1449 return true; 1450 } 1451 } 1452 return false; 1453 } 1454 1455 /* Return true if the processor is in secure state */ 1456 static inline bool arm_is_secure(CPUARMState *env) 1457 { 1458 if (arm_is_el3_or_mon(env)) { 1459 return true; 1460 } 1461 return arm_is_secure_below_el3(env); 1462 } 1463 1464 #else 1465 static inline bool arm_is_secure_below_el3(CPUARMState *env) 1466 { 1467 return false; 1468 } 1469 1470 static inline bool arm_is_secure(CPUARMState *env) 1471 { 1472 return false; 1473 } 1474 #endif 1475 1476 /* Return true if the specified exception level is running in AArch64 state. */ 1477 static inline bool arm_el_is_aa64(CPUARMState *env, int el) 1478 { 1479 /* This isn't valid for EL0 (if we're in EL0, is_a64() is what you want, 1480 * and if we're not in EL0 then the state of EL0 isn't well defined.) 1481 */ 1482 assert(el >= 1 && el <= 3); 1483 bool aa64 = arm_feature(env, ARM_FEATURE_AARCH64); 1484 1485 /* The highest exception level is always at the maximum supported 1486 * register width, and then lower levels have a register width controlled 1487 * by bits in the SCR or HCR registers. 1488 */ 1489 if (el == 3) { 1490 return aa64; 1491 } 1492 1493 if (arm_feature(env, ARM_FEATURE_EL3)) { 1494 aa64 = aa64 && (env->cp15.scr_el3 & SCR_RW); 1495 } 1496 1497 if (el == 2) { 1498 return aa64; 1499 } 1500 1501 if (arm_feature(env, ARM_FEATURE_EL2) && !arm_is_secure_below_el3(env)) { 1502 aa64 = aa64 && (env->cp15.hcr_el2 & HCR_RW); 1503 } 1504 1505 return aa64; 1506 } 1507 1508 /* Function for determing whether guest cp register reads and writes should 1509 * access the secure or non-secure bank of a cp register. When EL3 is 1510 * operating in AArch32 state, the NS-bit determines whether the secure 1511 * instance of a cp register should be used. When EL3 is AArch64 (or if 1512 * it doesn't exist at all) then there is no register banking, and all 1513 * accesses are to the non-secure version. 1514 */ 1515 static inline bool access_secure_reg(CPUARMState *env) 1516 { 1517 bool ret = (arm_feature(env, ARM_FEATURE_EL3) && 1518 !arm_el_is_aa64(env, 3) && 1519 !(env->cp15.scr_el3 & SCR_NS)); 1520 1521 return ret; 1522 } 1523 1524 /* Macros for accessing a specified CP register bank */ 1525 #define A32_BANKED_REG_GET(_env, _regname, _secure) \ 1526 ((_secure) ? (_env)->cp15._regname##_s : (_env)->cp15._regname##_ns) 1527 1528 #define A32_BANKED_REG_SET(_env, _regname, _secure, _val) \ 1529 do { \ 1530 if (_secure) { \ 1531 (_env)->cp15._regname##_s = (_val); \ 1532 } else { \ 1533 (_env)->cp15._regname##_ns = (_val); \ 1534 } \ 1535 } while (0) 1536 1537 /* Macros for automatically accessing a specific CP register bank depending on 1538 * the current secure state of the system. These macros are not intended for 1539 * supporting instruction translation reads/writes as these are dependent 1540 * solely on the SCR.NS bit and not the mode. 1541 */ 1542 #define A32_BANKED_CURRENT_REG_GET(_env, _regname) \ 1543 A32_BANKED_REG_GET((_env), _regname, \ 1544 (arm_is_secure(_env) && !arm_el_is_aa64((_env), 3))) 1545 1546 #define A32_BANKED_CURRENT_REG_SET(_env, _regname, _val) \ 1547 A32_BANKED_REG_SET((_env), _regname, \ 1548 (arm_is_secure(_env) && !arm_el_is_aa64((_env), 3)), \ 1549 (_val)) 1550 1551 void arm_cpu_list(FILE *f, fprintf_function cpu_fprintf); 1552 uint32_t arm_phys_excp_target_el(CPUState *cs, uint32_t excp_idx, 1553 uint32_t cur_el, bool secure); 1554 1555 /* Interface between CPU and Interrupt controller. */ 1556 #ifndef CONFIG_USER_ONLY 1557 bool armv7m_nvic_can_take_pending_exception(void *opaque); 1558 #else 1559 static inline bool armv7m_nvic_can_take_pending_exception(void *opaque) 1560 { 1561 return true; 1562 } 1563 #endif 1564 /** 1565 * armv7m_nvic_set_pending: mark the specified exception as pending 1566 * @opaque: the NVIC 1567 * @irq: the exception number to mark pending 1568 * @secure: false for non-banked exceptions or for the nonsecure 1569 * version of a banked exception, true for the secure version of a banked 1570 * exception. 1571 * 1572 * Marks the specified exception as pending. Note that we will assert() 1573 * if @secure is true and @irq does not specify one of the fixed set 1574 * of architecturally banked exceptions. 1575 */ 1576 void armv7m_nvic_set_pending(void *opaque, int irq, bool secure); 1577 /** 1578 * armv7m_nvic_set_pending_derived: mark this derived exception as pending 1579 * @opaque: the NVIC 1580 * @irq: the exception number to mark pending 1581 * @secure: false for non-banked exceptions or for the nonsecure 1582 * version of a banked exception, true for the secure version of a banked 1583 * exception. 1584 * 1585 * Similar to armv7m_nvic_set_pending(), but specifically for derived 1586 * exceptions (exceptions generated in the course of trying to take 1587 * a different exception). 1588 */ 1589 void armv7m_nvic_set_pending_derived(void *opaque, int irq, bool secure); 1590 /** 1591 * armv7m_nvic_get_pending_irq_info: return highest priority pending 1592 * exception, and whether it targets Secure state 1593 * @opaque: the NVIC 1594 * @pirq: set to pending exception number 1595 * @ptargets_secure: set to whether pending exception targets Secure 1596 * 1597 * This function writes the number of the highest priority pending 1598 * exception (the one which would be made active by 1599 * armv7m_nvic_acknowledge_irq()) to @pirq, and sets @ptargets_secure 1600 * to true if the current highest priority pending exception should 1601 * be taken to Secure state, false for NS. 1602 */ 1603 void armv7m_nvic_get_pending_irq_info(void *opaque, int *pirq, 1604 bool *ptargets_secure); 1605 /** 1606 * armv7m_nvic_acknowledge_irq: make highest priority pending exception active 1607 * @opaque: the NVIC 1608 * 1609 * Move the current highest priority pending exception from the pending 1610 * state to the active state, and update v7m.exception to indicate that 1611 * it is the exception currently being handled. 1612 */ 1613 void armv7m_nvic_acknowledge_irq(void *opaque); 1614 /** 1615 * armv7m_nvic_complete_irq: complete specified interrupt or exception 1616 * @opaque: the NVIC 1617 * @irq: the exception number to complete 1618 * @secure: true if this exception was secure 1619 * 1620 * Returns: -1 if the irq was not active 1621 * 1 if completing this irq brought us back to base (no active irqs) 1622 * 0 if there is still an irq active after this one was completed 1623 * (Ignoring -1, this is the same as the RETTOBASE value before completion.) 1624 */ 1625 int armv7m_nvic_complete_irq(void *opaque, int irq, bool secure); 1626 /** 1627 * armv7m_nvic_raw_execution_priority: return the raw execution priority 1628 * @opaque: the NVIC 1629 * 1630 * Returns: the raw execution priority as defined by the v8M architecture. 1631 * This is the execution priority minus the effects of AIRCR.PRIS, 1632 * and minus any PRIMASK/FAULTMASK/BASEPRI priority boosting. 1633 * (v8M ARM ARM I_PKLD.) 1634 */ 1635 int armv7m_nvic_raw_execution_priority(void *opaque); 1636 /** 1637 * armv7m_nvic_neg_prio_requested: return true if the requested execution 1638 * priority is negative for the specified security state. 1639 * @opaque: the NVIC 1640 * @secure: the security state to test 1641 * This corresponds to the pseudocode IsReqExecPriNeg(). 1642 */ 1643 #ifndef CONFIG_USER_ONLY 1644 bool armv7m_nvic_neg_prio_requested(void *opaque, bool secure); 1645 #else 1646 static inline bool armv7m_nvic_neg_prio_requested(void *opaque, bool secure) 1647 { 1648 return false; 1649 } 1650 #endif 1651 1652 /* Interface for defining coprocessor registers. 1653 * Registers are defined in tables of arm_cp_reginfo structs 1654 * which are passed to define_arm_cp_regs(). 1655 */ 1656 1657 /* When looking up a coprocessor register we look for it 1658 * via an integer which encodes all of: 1659 * coprocessor number 1660 * Crn, Crm, opc1, opc2 fields 1661 * 32 or 64 bit register (ie is it accessed via MRC/MCR 1662 * or via MRRC/MCRR?) 1663 * non-secure/secure bank (AArch32 only) 1664 * We allow 4 bits for opc1 because MRRC/MCRR have a 4 bit field. 1665 * (In this case crn and opc2 should be zero.) 1666 * For AArch64, there is no 32/64 bit size distinction; 1667 * instead all registers have a 2 bit op0, 3 bit op1 and op2, 1668 * and 4 bit CRn and CRm. The encoding patterns are chosen 1669 * to be easy to convert to and from the KVM encodings, and also 1670 * so that the hashtable can contain both AArch32 and AArch64 1671 * registers (to allow for interprocessing where we might run 1672 * 32 bit code on a 64 bit core). 1673 */ 1674 /* This bit is private to our hashtable cpreg; in KVM register 1675 * IDs the AArch64/32 distinction is the KVM_REG_ARM/ARM64 1676 * in the upper bits of the 64 bit ID. 1677 */ 1678 #define CP_REG_AA64_SHIFT 28 1679 #define CP_REG_AA64_MASK (1 << CP_REG_AA64_SHIFT) 1680 1681 /* To enable banking of coprocessor registers depending on ns-bit we 1682 * add a bit to distinguish between secure and non-secure cpregs in the 1683 * hashtable. 1684 */ 1685 #define CP_REG_NS_SHIFT 29 1686 #define CP_REG_NS_MASK (1 << CP_REG_NS_SHIFT) 1687 1688 #define ENCODE_CP_REG(cp, is64, ns, crn, crm, opc1, opc2) \ 1689 ((ns) << CP_REG_NS_SHIFT | ((cp) << 16) | ((is64) << 15) | \ 1690 ((crn) << 11) | ((crm) << 7) | ((opc1) << 3) | (opc2)) 1691 1692 #define ENCODE_AA64_CP_REG(cp, crn, crm, op0, op1, op2) \ 1693 (CP_REG_AA64_MASK | \ 1694 ((cp) << CP_REG_ARM_COPROC_SHIFT) | \ 1695 ((op0) << CP_REG_ARM64_SYSREG_OP0_SHIFT) | \ 1696 ((op1) << CP_REG_ARM64_SYSREG_OP1_SHIFT) | \ 1697 ((crn) << CP_REG_ARM64_SYSREG_CRN_SHIFT) | \ 1698 ((crm) << CP_REG_ARM64_SYSREG_CRM_SHIFT) | \ 1699 ((op2) << CP_REG_ARM64_SYSREG_OP2_SHIFT)) 1700 1701 /* Convert a full 64 bit KVM register ID to the truncated 32 bit 1702 * version used as a key for the coprocessor register hashtable 1703 */ 1704 static inline uint32_t kvm_to_cpreg_id(uint64_t kvmid) 1705 { 1706 uint32_t cpregid = kvmid; 1707 if ((kvmid & CP_REG_ARCH_MASK) == CP_REG_ARM64) { 1708 cpregid |= CP_REG_AA64_MASK; 1709 } else { 1710 if ((kvmid & CP_REG_SIZE_MASK) == CP_REG_SIZE_U64) { 1711 cpregid |= (1 << 15); 1712 } 1713 1714 /* KVM is always non-secure so add the NS flag on AArch32 register 1715 * entries. 1716 */ 1717 cpregid |= 1 << CP_REG_NS_SHIFT; 1718 } 1719 return cpregid; 1720 } 1721 1722 /* Convert a truncated 32 bit hashtable key into the full 1723 * 64 bit KVM register ID. 1724 */ 1725 static inline uint64_t cpreg_to_kvm_id(uint32_t cpregid) 1726 { 1727 uint64_t kvmid; 1728 1729 if (cpregid & CP_REG_AA64_MASK) { 1730 kvmid = cpregid & ~CP_REG_AA64_MASK; 1731 kvmid |= CP_REG_SIZE_U64 | CP_REG_ARM64; 1732 } else { 1733 kvmid = cpregid & ~(1 << 15); 1734 if (cpregid & (1 << 15)) { 1735 kvmid |= CP_REG_SIZE_U64 | CP_REG_ARM; 1736 } else { 1737 kvmid |= CP_REG_SIZE_U32 | CP_REG_ARM; 1738 } 1739 } 1740 return kvmid; 1741 } 1742 1743 /* ARMCPRegInfo type field bits. If the SPECIAL bit is set this is a 1744 * special-behaviour cp reg and bits [11..8] indicate what behaviour 1745 * it has. Otherwise it is a simple cp reg, where CONST indicates that 1746 * TCG can assume the value to be constant (ie load at translate time) 1747 * and 64BIT indicates a 64 bit wide coprocessor register. SUPPRESS_TB_END 1748 * indicates that the TB should not be ended after a write to this register 1749 * (the default is that the TB ends after cp writes). OVERRIDE permits 1750 * a register definition to override a previous definition for the 1751 * same (cp, is64, crn, crm, opc1, opc2) tuple: either the new or the 1752 * old must have the OVERRIDE bit set. 1753 * ALIAS indicates that this register is an alias view of some underlying 1754 * state which is also visible via another register, and that the other 1755 * register is handling migration and reset; registers marked ALIAS will not be 1756 * migrated but may have their state set by syncing of register state from KVM. 1757 * NO_RAW indicates that this register has no underlying state and does not 1758 * support raw access for state saving/loading; it will not be used for either 1759 * migration or KVM state synchronization. (Typically this is for "registers" 1760 * which are actually used as instructions for cache maintenance and so on.) 1761 * IO indicates that this register does I/O and therefore its accesses 1762 * need to be surrounded by gen_io_start()/gen_io_end(). In particular, 1763 * registers which implement clocks or timers require this. 1764 */ 1765 #define ARM_CP_SPECIAL 0x0001 1766 #define ARM_CP_CONST 0x0002 1767 #define ARM_CP_64BIT 0x0004 1768 #define ARM_CP_SUPPRESS_TB_END 0x0008 1769 #define ARM_CP_OVERRIDE 0x0010 1770 #define ARM_CP_ALIAS 0x0020 1771 #define ARM_CP_IO 0x0040 1772 #define ARM_CP_NO_RAW 0x0080 1773 #define ARM_CP_NOP (ARM_CP_SPECIAL | 0x0100) 1774 #define ARM_CP_WFI (ARM_CP_SPECIAL | 0x0200) 1775 #define ARM_CP_NZCV (ARM_CP_SPECIAL | 0x0300) 1776 #define ARM_CP_CURRENTEL (ARM_CP_SPECIAL | 0x0400) 1777 #define ARM_CP_DC_ZVA (ARM_CP_SPECIAL | 0x0500) 1778 #define ARM_LAST_SPECIAL ARM_CP_DC_ZVA 1779 #define ARM_CP_FPU 0x1000 1780 #define ARM_CP_SVE 0x2000 1781 /* Used only as a terminator for ARMCPRegInfo lists */ 1782 #define ARM_CP_SENTINEL 0xffff 1783 /* Mask of only the flag bits in a type field */ 1784 #define ARM_CP_FLAG_MASK 0x30ff 1785 1786 /* Valid values for ARMCPRegInfo state field, indicating which of 1787 * the AArch32 and AArch64 execution states this register is visible in. 1788 * If the reginfo doesn't explicitly specify then it is AArch32 only. 1789 * If the reginfo is declared to be visible in both states then a second 1790 * reginfo is synthesised for the AArch32 view of the AArch64 register, 1791 * such that the AArch32 view is the lower 32 bits of the AArch64 one. 1792 * Note that we rely on the values of these enums as we iterate through 1793 * the various states in some places. 1794 */ 1795 enum { 1796 ARM_CP_STATE_AA32 = 0, 1797 ARM_CP_STATE_AA64 = 1, 1798 ARM_CP_STATE_BOTH = 2, 1799 }; 1800 1801 /* ARM CP register secure state flags. These flags identify security state 1802 * attributes for a given CP register entry. 1803 * The existence of both or neither secure and non-secure flags indicates that 1804 * the register has both a secure and non-secure hash entry. A single one of 1805 * these flags causes the register to only be hashed for the specified 1806 * security state. 1807 * Although definitions may have any combination of the S/NS bits, each 1808 * registered entry will only have one to identify whether the entry is secure 1809 * or non-secure. 1810 */ 1811 enum { 1812 ARM_CP_SECSTATE_S = (1 << 0), /* bit[0]: Secure state register */ 1813 ARM_CP_SECSTATE_NS = (1 << 1), /* bit[1]: Non-secure state register */ 1814 }; 1815 1816 /* Return true if cptype is a valid type field. This is used to try to 1817 * catch errors where the sentinel has been accidentally left off the end 1818 * of a list of registers. 1819 */ 1820 static inline bool cptype_valid(int cptype) 1821 { 1822 return ((cptype & ~ARM_CP_FLAG_MASK) == 0) 1823 || ((cptype & ARM_CP_SPECIAL) && 1824 ((cptype & ~ARM_CP_FLAG_MASK) <= ARM_LAST_SPECIAL)); 1825 } 1826 1827 /* Access rights: 1828 * We define bits for Read and Write access for what rev C of the v7-AR ARM ARM 1829 * defines as PL0 (user), PL1 (fiq/irq/svc/abt/und/sys, ie privileged), and 1830 * PL2 (hyp). The other level which has Read and Write bits is Secure PL1 1831 * (ie any of the privileged modes in Secure state, or Monitor mode). 1832 * If a register is accessible in one privilege level it's always accessible 1833 * in higher privilege levels too. Since "Secure PL1" also follows this rule 1834 * (ie anything visible in PL2 is visible in S-PL1, some things are only 1835 * visible in S-PL1) but "Secure PL1" is a bit of a mouthful, we bend the 1836 * terminology a little and call this PL3. 1837 * In AArch64 things are somewhat simpler as the PLx bits line up exactly 1838 * with the ELx exception levels. 1839 * 1840 * If access permissions for a register are more complex than can be 1841 * described with these bits, then use a laxer set of restrictions, and 1842 * do the more restrictive/complex check inside a helper function. 1843 */ 1844 #define PL3_R 0x80 1845 #define PL3_W 0x40 1846 #define PL2_R (0x20 | PL3_R) 1847 #define PL2_W (0x10 | PL3_W) 1848 #define PL1_R (0x08 | PL2_R) 1849 #define PL1_W (0x04 | PL2_W) 1850 #define PL0_R (0x02 | PL1_R) 1851 #define PL0_W (0x01 | PL1_W) 1852 1853 #define PL3_RW (PL3_R | PL3_W) 1854 #define PL2_RW (PL2_R | PL2_W) 1855 #define PL1_RW (PL1_R | PL1_W) 1856 #define PL0_RW (PL0_R | PL0_W) 1857 1858 /* Return the highest implemented Exception Level */ 1859 static inline int arm_highest_el(CPUARMState *env) 1860 { 1861 if (arm_feature(env, ARM_FEATURE_EL3)) { 1862 return 3; 1863 } 1864 if (arm_feature(env, ARM_FEATURE_EL2)) { 1865 return 2; 1866 } 1867 return 1; 1868 } 1869 1870 /* Return true if a v7M CPU is in Handler mode */ 1871 static inline bool arm_v7m_is_handler_mode(CPUARMState *env) 1872 { 1873 return env->v7m.exception != 0; 1874 } 1875 1876 /* Return the current Exception Level (as per ARMv8; note that this differs 1877 * from the ARMv7 Privilege Level). 1878 */ 1879 static inline int arm_current_el(CPUARMState *env) 1880 { 1881 if (arm_feature(env, ARM_FEATURE_M)) { 1882 return arm_v7m_is_handler_mode(env) || 1883 !(env->v7m.control[env->v7m.secure] & 1); 1884 } 1885 1886 if (is_a64(env)) { 1887 return extract32(env->pstate, 2, 2); 1888 } 1889 1890 switch (env->uncached_cpsr & 0x1f) { 1891 case ARM_CPU_MODE_USR: 1892 return 0; 1893 case ARM_CPU_MODE_HYP: 1894 return 2; 1895 case ARM_CPU_MODE_MON: 1896 return 3; 1897 default: 1898 if (arm_is_secure(env) && !arm_el_is_aa64(env, 3)) { 1899 /* If EL3 is 32-bit then all secure privileged modes run in 1900 * EL3 1901 */ 1902 return 3; 1903 } 1904 1905 return 1; 1906 } 1907 } 1908 1909 typedef struct ARMCPRegInfo ARMCPRegInfo; 1910 1911 typedef enum CPAccessResult { 1912 /* Access is permitted */ 1913 CP_ACCESS_OK = 0, 1914 /* Access fails due to a configurable trap or enable which would 1915 * result in a categorized exception syndrome giving information about 1916 * the failing instruction (ie syndrome category 0x3, 0x4, 0x5, 0x6, 1917 * 0xc or 0x18). The exception is taken to the usual target EL (EL1 or 1918 * PL1 if in EL0, otherwise to the current EL). 1919 */ 1920 CP_ACCESS_TRAP = 1, 1921 /* Access fails and results in an exception syndrome 0x0 ("uncategorized"). 1922 * Note that this is not a catch-all case -- the set of cases which may 1923 * result in this failure is specifically defined by the architecture. 1924 */ 1925 CP_ACCESS_TRAP_UNCATEGORIZED = 2, 1926 /* As CP_ACCESS_TRAP, but for traps directly to EL2 or EL3 */ 1927 CP_ACCESS_TRAP_EL2 = 3, 1928 CP_ACCESS_TRAP_EL3 = 4, 1929 /* As CP_ACCESS_UNCATEGORIZED, but for traps directly to EL2 or EL3 */ 1930 CP_ACCESS_TRAP_UNCATEGORIZED_EL2 = 5, 1931 CP_ACCESS_TRAP_UNCATEGORIZED_EL3 = 6, 1932 /* Access fails and results in an exception syndrome for an FP access, 1933 * trapped directly to EL2 or EL3 1934 */ 1935 CP_ACCESS_TRAP_FP_EL2 = 7, 1936 CP_ACCESS_TRAP_FP_EL3 = 8, 1937 } CPAccessResult; 1938 1939 /* Access functions for coprocessor registers. These cannot fail and 1940 * may not raise exceptions. 1941 */ 1942 typedef uint64_t CPReadFn(CPUARMState *env, const ARMCPRegInfo *opaque); 1943 typedef void CPWriteFn(CPUARMState *env, const ARMCPRegInfo *opaque, 1944 uint64_t value); 1945 /* Access permission check functions for coprocessor registers. */ 1946 typedef CPAccessResult CPAccessFn(CPUARMState *env, 1947 const ARMCPRegInfo *opaque, 1948 bool isread); 1949 /* Hook function for register reset */ 1950 typedef void CPResetFn(CPUARMState *env, const ARMCPRegInfo *opaque); 1951 1952 #define CP_ANY 0xff 1953 1954 /* Definition of an ARM coprocessor register */ 1955 struct ARMCPRegInfo { 1956 /* Name of register (useful mainly for debugging, need not be unique) */ 1957 const char *name; 1958 /* Location of register: coprocessor number and (crn,crm,opc1,opc2) 1959 * tuple. Any of crm, opc1 and opc2 may be CP_ANY to indicate a 1960 * 'wildcard' field -- any value of that field in the MRC/MCR insn 1961 * will be decoded to this register. The register read and write 1962 * callbacks will be passed an ARMCPRegInfo with the crn/crm/opc1/opc2 1963 * used by the program, so it is possible to register a wildcard and 1964 * then behave differently on read/write if necessary. 1965 * For 64 bit registers, only crm and opc1 are relevant; crn and opc2 1966 * must both be zero. 1967 * For AArch64-visible registers, opc0 is also used. 1968 * Since there are no "coprocessors" in AArch64, cp is purely used as a 1969 * way to distinguish (for KVM's benefit) guest-visible system registers 1970 * from demuxed ones provided to preserve the "no side effects on 1971 * KVM register read/write from QEMU" semantics. cp==0x13 is guest 1972 * visible (to match KVM's encoding); cp==0 will be converted to 1973 * cp==0x13 when the ARMCPRegInfo is registered, for convenience. 1974 */ 1975 uint8_t cp; 1976 uint8_t crn; 1977 uint8_t crm; 1978 uint8_t opc0; 1979 uint8_t opc1; 1980 uint8_t opc2; 1981 /* Execution state in which this register is visible: ARM_CP_STATE_* */ 1982 int state; 1983 /* Register type: ARM_CP_* bits/values */ 1984 int type; 1985 /* Access rights: PL*_[RW] */ 1986 int access; 1987 /* Security state: ARM_CP_SECSTATE_* bits/values */ 1988 int secure; 1989 /* The opaque pointer passed to define_arm_cp_regs_with_opaque() when 1990 * this register was defined: can be used to hand data through to the 1991 * register read/write functions, since they are passed the ARMCPRegInfo*. 1992 */ 1993 void *opaque; 1994 /* Value of this register, if it is ARM_CP_CONST. Otherwise, if 1995 * fieldoffset is non-zero, the reset value of the register. 1996 */ 1997 uint64_t resetvalue; 1998 /* Offset of the field in CPUARMState for this register. 1999 * 2000 * This is not needed if either: 2001 * 1. type is ARM_CP_CONST or one of the ARM_CP_SPECIALs 2002 * 2. both readfn and writefn are specified 2003 */ 2004 ptrdiff_t fieldoffset; /* offsetof(CPUARMState, field) */ 2005 2006 /* Offsets of the secure and non-secure fields in CPUARMState for the 2007 * register if it is banked. These fields are only used during the static 2008 * registration of a register. During hashing the bank associated 2009 * with a given security state is copied to fieldoffset which is used from 2010 * there on out. 2011 * 2012 * It is expected that register definitions use either fieldoffset or 2013 * bank_fieldoffsets in the definition but not both. It is also expected 2014 * that both bank offsets are set when defining a banked register. This 2015 * use indicates that a register is banked. 2016 */ 2017 ptrdiff_t bank_fieldoffsets[2]; 2018 2019 /* Function for making any access checks for this register in addition to 2020 * those specified by the 'access' permissions bits. If NULL, no extra 2021 * checks required. The access check is performed at runtime, not at 2022 * translate time. 2023 */ 2024 CPAccessFn *accessfn; 2025 /* Function for handling reads of this register. If NULL, then reads 2026 * will be done by loading from the offset into CPUARMState specified 2027 * by fieldoffset. 2028 */ 2029 CPReadFn *readfn; 2030 /* Function for handling writes of this register. If NULL, then writes 2031 * will be done by writing to the offset into CPUARMState specified 2032 * by fieldoffset. 2033 */ 2034 CPWriteFn *writefn; 2035 /* Function for doing a "raw" read; used when we need to copy 2036 * coprocessor state to the kernel for KVM or out for 2037 * migration. This only needs to be provided if there is also a 2038 * readfn and it has side effects (for instance clear-on-read bits). 2039 */ 2040 CPReadFn *raw_readfn; 2041 /* Function for doing a "raw" write; used when we need to copy KVM 2042 * kernel coprocessor state into userspace, or for inbound 2043 * migration. This only needs to be provided if there is also a 2044 * writefn and it masks out "unwritable" bits or has write-one-to-clear 2045 * or similar behaviour. 2046 */ 2047 CPWriteFn *raw_writefn; 2048 /* Function for resetting the register. If NULL, then reset will be done 2049 * by writing resetvalue to the field specified in fieldoffset. If 2050 * fieldoffset is 0 then no reset will be done. 2051 */ 2052 CPResetFn *resetfn; 2053 }; 2054 2055 /* Macros which are lvalues for the field in CPUARMState for the 2056 * ARMCPRegInfo *ri. 2057 */ 2058 #define CPREG_FIELD32(env, ri) \ 2059 (*(uint32_t *)((char *)(env) + (ri)->fieldoffset)) 2060 #define CPREG_FIELD64(env, ri) \ 2061 (*(uint64_t *)((char *)(env) + (ri)->fieldoffset)) 2062 2063 #define REGINFO_SENTINEL { .type = ARM_CP_SENTINEL } 2064 2065 void define_arm_cp_regs_with_opaque(ARMCPU *cpu, 2066 const ARMCPRegInfo *regs, void *opaque); 2067 void define_one_arm_cp_reg_with_opaque(ARMCPU *cpu, 2068 const ARMCPRegInfo *regs, void *opaque); 2069 static inline void define_arm_cp_regs(ARMCPU *cpu, const ARMCPRegInfo *regs) 2070 { 2071 define_arm_cp_regs_with_opaque(cpu, regs, 0); 2072 } 2073 static inline void define_one_arm_cp_reg(ARMCPU *cpu, const ARMCPRegInfo *regs) 2074 { 2075 define_one_arm_cp_reg_with_opaque(cpu, regs, 0); 2076 } 2077 const ARMCPRegInfo *get_arm_cp_reginfo(GHashTable *cpregs, uint32_t encoded_cp); 2078 2079 /* CPWriteFn that can be used to implement writes-ignored behaviour */ 2080 void arm_cp_write_ignore(CPUARMState *env, const ARMCPRegInfo *ri, 2081 uint64_t value); 2082 /* CPReadFn that can be used for read-as-zero behaviour */ 2083 uint64_t arm_cp_read_zero(CPUARMState *env, const ARMCPRegInfo *ri); 2084 2085 /* CPResetFn that does nothing, for use if no reset is required even 2086 * if fieldoffset is non zero. 2087 */ 2088 void arm_cp_reset_ignore(CPUARMState *env, const ARMCPRegInfo *opaque); 2089 2090 /* Return true if this reginfo struct's field in the cpu state struct 2091 * is 64 bits wide. 2092 */ 2093 static inline bool cpreg_field_is_64bit(const ARMCPRegInfo *ri) 2094 { 2095 return (ri->state == ARM_CP_STATE_AA64) || (ri->type & ARM_CP_64BIT); 2096 } 2097 2098 static inline bool cp_access_ok(int current_el, 2099 const ARMCPRegInfo *ri, int isread) 2100 { 2101 return (ri->access >> ((current_el * 2) + isread)) & 1; 2102 } 2103 2104 /* Raw read of a coprocessor register (as needed for migration, etc) */ 2105 uint64_t read_raw_cp_reg(CPUARMState *env, const ARMCPRegInfo *ri); 2106 2107 /** 2108 * write_list_to_cpustate 2109 * @cpu: ARMCPU 2110 * 2111 * For each register listed in the ARMCPU cpreg_indexes list, write 2112 * its value from the cpreg_values list into the ARMCPUState structure. 2113 * This updates TCG's working data structures from KVM data or 2114 * from incoming migration state. 2115 * 2116 * Returns: true if all register values were updated correctly, 2117 * false if some register was unknown or could not be written. 2118 * Note that we do not stop early on failure -- we will attempt 2119 * writing all registers in the list. 2120 */ 2121 bool write_list_to_cpustate(ARMCPU *cpu); 2122 2123 /** 2124 * write_cpustate_to_list: 2125 * @cpu: ARMCPU 2126 * 2127 * For each register listed in the ARMCPU cpreg_indexes list, write 2128 * its value from the ARMCPUState structure into the cpreg_values list. 2129 * This is used to copy info from TCG's working data structures into 2130 * KVM or for outbound migration. 2131 * 2132 * Returns: true if all register values were read correctly, 2133 * false if some register was unknown or could not be read. 2134 * Note that we do not stop early on failure -- we will attempt 2135 * reading all registers in the list. 2136 */ 2137 bool write_cpustate_to_list(ARMCPU *cpu); 2138 2139 #define ARM_CPUID_TI915T 0x54029152 2140 #define ARM_CPUID_TI925T 0x54029252 2141 2142 #if defined(CONFIG_USER_ONLY) 2143 #define TARGET_PAGE_BITS 12 2144 #else 2145 /* ARMv7 and later CPUs have 4K pages minimum, but ARMv5 and v6 2146 * have to support 1K tiny pages. 2147 */ 2148 #define TARGET_PAGE_BITS_VARY 2149 #define TARGET_PAGE_BITS_MIN 10 2150 #endif 2151 2152 #if defined(TARGET_AARCH64) 2153 # define TARGET_PHYS_ADDR_SPACE_BITS 48 2154 # define TARGET_VIRT_ADDR_SPACE_BITS 64 2155 #else 2156 # define TARGET_PHYS_ADDR_SPACE_BITS 40 2157 # define TARGET_VIRT_ADDR_SPACE_BITS 32 2158 #endif 2159 2160 static inline bool arm_excp_unmasked(CPUState *cs, unsigned int excp_idx, 2161 unsigned int target_el) 2162 { 2163 CPUARMState *env = cs->env_ptr; 2164 unsigned int cur_el = arm_current_el(env); 2165 bool secure = arm_is_secure(env); 2166 bool pstate_unmasked; 2167 int8_t unmasked = 0; 2168 2169 /* Don't take exceptions if they target a lower EL. 2170 * This check should catch any exceptions that would not be taken but left 2171 * pending. 2172 */ 2173 if (cur_el > target_el) { 2174 return false; 2175 } 2176 2177 switch (excp_idx) { 2178 case EXCP_FIQ: 2179 pstate_unmasked = !(env->daif & PSTATE_F); 2180 break; 2181 2182 case EXCP_IRQ: 2183 pstate_unmasked = !(env->daif & PSTATE_I); 2184 break; 2185 2186 case EXCP_VFIQ: 2187 if (secure || !(env->cp15.hcr_el2 & HCR_FMO)) { 2188 /* VFIQs are only taken when hypervized and non-secure. */ 2189 return false; 2190 } 2191 return !(env->daif & PSTATE_F); 2192 case EXCP_VIRQ: 2193 if (secure || !(env->cp15.hcr_el2 & HCR_IMO)) { 2194 /* VIRQs are only taken when hypervized and non-secure. */ 2195 return false; 2196 } 2197 return !(env->daif & PSTATE_I); 2198 default: 2199 g_assert_not_reached(); 2200 } 2201 2202 /* Use the target EL, current execution state and SCR/HCR settings to 2203 * determine whether the corresponding CPSR bit is used to mask the 2204 * interrupt. 2205 */ 2206 if ((target_el > cur_el) && (target_el != 1)) { 2207 /* Exceptions targeting a higher EL may not be maskable */ 2208 if (arm_feature(env, ARM_FEATURE_AARCH64)) { 2209 /* 64-bit masking rules are simple: exceptions to EL3 2210 * can't be masked, and exceptions to EL2 can only be 2211 * masked from Secure state. The HCR and SCR settings 2212 * don't affect the masking logic, only the interrupt routing. 2213 */ 2214 if (target_el == 3 || !secure) { 2215 unmasked = 1; 2216 } 2217 } else { 2218 /* The old 32-bit-only environment has a more complicated 2219 * masking setup. HCR and SCR bits not only affect interrupt 2220 * routing but also change the behaviour of masking. 2221 */ 2222 bool hcr, scr; 2223 2224 switch (excp_idx) { 2225 case EXCP_FIQ: 2226 /* If FIQs are routed to EL3 or EL2 then there are cases where 2227 * we override the CPSR.F in determining if the exception is 2228 * masked or not. If neither of these are set then we fall back 2229 * to the CPSR.F setting otherwise we further assess the state 2230 * below. 2231 */ 2232 hcr = (env->cp15.hcr_el2 & HCR_FMO); 2233 scr = (env->cp15.scr_el3 & SCR_FIQ); 2234 2235 /* When EL3 is 32-bit, the SCR.FW bit controls whether the 2236 * CPSR.F bit masks FIQ interrupts when taken in non-secure 2237 * state. If SCR.FW is set then FIQs can be masked by CPSR.F 2238 * when non-secure but only when FIQs are only routed to EL3. 2239 */ 2240 scr = scr && !((env->cp15.scr_el3 & SCR_FW) && !hcr); 2241 break; 2242 case EXCP_IRQ: 2243 /* When EL3 execution state is 32-bit, if HCR.IMO is set then 2244 * we may override the CPSR.I masking when in non-secure state. 2245 * The SCR.IRQ setting has already been taken into consideration 2246 * when setting the target EL, so it does not have a further 2247 * affect here. 2248 */ 2249 hcr = (env->cp15.hcr_el2 & HCR_IMO); 2250 scr = false; 2251 break; 2252 default: 2253 g_assert_not_reached(); 2254 } 2255 2256 if ((scr || hcr) && !secure) { 2257 unmasked = 1; 2258 } 2259 } 2260 } 2261 2262 /* The PSTATE bits only mask the interrupt if we have not overriden the 2263 * ability above. 2264 */ 2265 return unmasked || pstate_unmasked; 2266 } 2267 2268 #define cpu_init(cpu_model) cpu_generic_init(TYPE_ARM_CPU, cpu_model) 2269 2270 #define ARM_CPU_TYPE_SUFFIX "-" TYPE_ARM_CPU 2271 #define ARM_CPU_TYPE_NAME(name) (name ARM_CPU_TYPE_SUFFIX) 2272 2273 #define cpu_signal_handler cpu_arm_signal_handler 2274 #define cpu_list arm_cpu_list 2275 2276 /* ARM has the following "translation regimes" (as the ARM ARM calls them): 2277 * 2278 * If EL3 is 64-bit: 2279 * + NonSecure EL1 & 0 stage 1 2280 * + NonSecure EL1 & 0 stage 2 2281 * + NonSecure EL2 2282 * + Secure EL1 & EL0 2283 * + Secure EL3 2284 * If EL3 is 32-bit: 2285 * + NonSecure PL1 & 0 stage 1 2286 * + NonSecure PL1 & 0 stage 2 2287 * + NonSecure PL2 2288 * + Secure PL0 & PL1 2289 * (reminder: for 32 bit EL3, Secure PL1 is *EL3*, not EL1.) 2290 * 2291 * For QEMU, an mmu_idx is not quite the same as a translation regime because: 2292 * 1. we need to split the "EL1 & 0" regimes into two mmu_idxes, because they 2293 * may differ in access permissions even if the VA->PA map is the same 2294 * 2. we want to cache in our TLB the full VA->IPA->PA lookup for a stage 1+2 2295 * translation, which means that we have one mmu_idx that deals with two 2296 * concatenated translation regimes [this sort of combined s1+2 TLB is 2297 * architecturally permitted] 2298 * 3. we don't need to allocate an mmu_idx to translations that we won't be 2299 * handling via the TLB. The only way to do a stage 1 translation without 2300 * the immediate stage 2 translation is via the ATS or AT system insns, 2301 * which can be slow-pathed and always do a page table walk. 2302 * 4. we can also safely fold together the "32 bit EL3" and "64 bit EL3" 2303 * translation regimes, because they map reasonably well to each other 2304 * and they can't both be active at the same time. 2305 * This gives us the following list of mmu_idx values: 2306 * 2307 * NS EL0 (aka NS PL0) stage 1+2 2308 * NS EL1 (aka NS PL1) stage 1+2 2309 * NS EL2 (aka NS PL2) 2310 * S EL3 (aka S PL1) 2311 * S EL0 (aka S PL0) 2312 * S EL1 (not used if EL3 is 32 bit) 2313 * NS EL0+1 stage 2 2314 * 2315 * (The last of these is an mmu_idx because we want to be able to use the TLB 2316 * for the accesses done as part of a stage 1 page table walk, rather than 2317 * having to walk the stage 2 page table over and over.) 2318 * 2319 * R profile CPUs have an MPU, but can use the same set of MMU indexes 2320 * as A profile. They only need to distinguish NS EL0 and NS EL1 (and 2321 * NS EL2 if we ever model a Cortex-R52). 2322 * 2323 * M profile CPUs are rather different as they do not have a true MMU. 2324 * They have the following different MMU indexes: 2325 * User 2326 * Privileged 2327 * User, execution priority negative (ie the MPU HFNMIENA bit may apply) 2328 * Privileged, execution priority negative (ditto) 2329 * If the CPU supports the v8M Security Extension then there are also: 2330 * Secure User 2331 * Secure Privileged 2332 * Secure User, execution priority negative 2333 * Secure Privileged, execution priority negative 2334 * 2335 * The ARMMMUIdx and the mmu index value used by the core QEMU TLB code 2336 * are not quite the same -- different CPU types (most notably M profile 2337 * vs A/R profile) would like to use MMU indexes with different semantics, 2338 * but since we don't ever need to use all of those in a single CPU we 2339 * can avoid setting NB_MMU_MODES to more than 8. The lower bits of 2340 * ARMMMUIdx are the core TLB mmu index, and the higher bits are always 2341 * the same for any particular CPU. 2342 * Variables of type ARMMUIdx are always full values, and the core 2343 * index values are in variables of type 'int'. 2344 * 2345 * Our enumeration includes at the end some entries which are not "true" 2346 * mmu_idx values in that they don't have corresponding TLBs and are only 2347 * valid for doing slow path page table walks. 2348 * 2349 * The constant names here are patterned after the general style of the names 2350 * of the AT/ATS operations. 2351 * The values used are carefully arranged to make mmu_idx => EL lookup easy. 2352 * For M profile we arrange them to have a bit for priv, a bit for negpri 2353 * and a bit for secure. 2354 */ 2355 #define ARM_MMU_IDX_A 0x10 /* A profile */ 2356 #define ARM_MMU_IDX_NOTLB 0x20 /* does not have a TLB */ 2357 #define ARM_MMU_IDX_M 0x40 /* M profile */ 2358 2359 /* meanings of the bits for M profile mmu idx values */ 2360 #define ARM_MMU_IDX_M_PRIV 0x1 2361 #define ARM_MMU_IDX_M_NEGPRI 0x2 2362 #define ARM_MMU_IDX_M_S 0x4 2363 2364 #define ARM_MMU_IDX_TYPE_MASK (~0x7) 2365 #define ARM_MMU_IDX_COREIDX_MASK 0x7 2366 2367 typedef enum ARMMMUIdx { 2368 ARMMMUIdx_S12NSE0 = 0 | ARM_MMU_IDX_A, 2369 ARMMMUIdx_S12NSE1 = 1 | ARM_MMU_IDX_A, 2370 ARMMMUIdx_S1E2 = 2 | ARM_MMU_IDX_A, 2371 ARMMMUIdx_S1E3 = 3 | ARM_MMU_IDX_A, 2372 ARMMMUIdx_S1SE0 = 4 | ARM_MMU_IDX_A, 2373 ARMMMUIdx_S1SE1 = 5 | ARM_MMU_IDX_A, 2374 ARMMMUIdx_S2NS = 6 | ARM_MMU_IDX_A, 2375 ARMMMUIdx_MUser = 0 | ARM_MMU_IDX_M, 2376 ARMMMUIdx_MPriv = 1 | ARM_MMU_IDX_M, 2377 ARMMMUIdx_MUserNegPri = 2 | ARM_MMU_IDX_M, 2378 ARMMMUIdx_MPrivNegPri = 3 | ARM_MMU_IDX_M, 2379 ARMMMUIdx_MSUser = 4 | ARM_MMU_IDX_M, 2380 ARMMMUIdx_MSPriv = 5 | ARM_MMU_IDX_M, 2381 ARMMMUIdx_MSUserNegPri = 6 | ARM_MMU_IDX_M, 2382 ARMMMUIdx_MSPrivNegPri = 7 | ARM_MMU_IDX_M, 2383 /* Indexes below here don't have TLBs and are used only for AT system 2384 * instructions or for the first stage of an S12 page table walk. 2385 */ 2386 ARMMMUIdx_S1NSE0 = 0 | ARM_MMU_IDX_NOTLB, 2387 ARMMMUIdx_S1NSE1 = 1 | ARM_MMU_IDX_NOTLB, 2388 } ARMMMUIdx; 2389 2390 /* Bit macros for the core-mmu-index values for each index, 2391 * for use when calling tlb_flush_by_mmuidx() and friends. 2392 */ 2393 typedef enum ARMMMUIdxBit { 2394 ARMMMUIdxBit_S12NSE0 = 1 << 0, 2395 ARMMMUIdxBit_S12NSE1 = 1 << 1, 2396 ARMMMUIdxBit_S1E2 = 1 << 2, 2397 ARMMMUIdxBit_S1E3 = 1 << 3, 2398 ARMMMUIdxBit_S1SE0 = 1 << 4, 2399 ARMMMUIdxBit_S1SE1 = 1 << 5, 2400 ARMMMUIdxBit_S2NS = 1 << 6, 2401 ARMMMUIdxBit_MUser = 1 << 0, 2402 ARMMMUIdxBit_MPriv = 1 << 1, 2403 ARMMMUIdxBit_MUserNegPri = 1 << 2, 2404 ARMMMUIdxBit_MPrivNegPri = 1 << 3, 2405 ARMMMUIdxBit_MSUser = 1 << 4, 2406 ARMMMUIdxBit_MSPriv = 1 << 5, 2407 ARMMMUIdxBit_MSUserNegPri = 1 << 6, 2408 ARMMMUIdxBit_MSPrivNegPri = 1 << 7, 2409 } ARMMMUIdxBit; 2410 2411 #define MMU_USER_IDX 0 2412 2413 static inline int arm_to_core_mmu_idx(ARMMMUIdx mmu_idx) 2414 { 2415 return mmu_idx & ARM_MMU_IDX_COREIDX_MASK; 2416 } 2417 2418 static inline ARMMMUIdx core_to_arm_mmu_idx(CPUARMState *env, int mmu_idx) 2419 { 2420 if (arm_feature(env, ARM_FEATURE_M)) { 2421 return mmu_idx | ARM_MMU_IDX_M; 2422 } else { 2423 return mmu_idx | ARM_MMU_IDX_A; 2424 } 2425 } 2426 2427 /* Return the exception level we're running at if this is our mmu_idx */ 2428 static inline int arm_mmu_idx_to_el(ARMMMUIdx mmu_idx) 2429 { 2430 switch (mmu_idx & ARM_MMU_IDX_TYPE_MASK) { 2431 case ARM_MMU_IDX_A: 2432 return mmu_idx & 3; 2433 case ARM_MMU_IDX_M: 2434 return mmu_idx & ARM_MMU_IDX_M_PRIV; 2435 default: 2436 g_assert_not_reached(); 2437 } 2438 } 2439 2440 /* Return the MMU index for a v7M CPU in the specified security and 2441 * privilege state 2442 */ 2443 static inline ARMMMUIdx arm_v7m_mmu_idx_for_secstate_and_priv(CPUARMState *env, 2444 bool secstate, 2445 bool priv) 2446 { 2447 ARMMMUIdx mmu_idx = ARM_MMU_IDX_M; 2448 2449 if (priv) { 2450 mmu_idx |= ARM_MMU_IDX_M_PRIV; 2451 } 2452 2453 if (armv7m_nvic_neg_prio_requested(env->nvic, secstate)) { 2454 mmu_idx |= ARM_MMU_IDX_M_NEGPRI; 2455 } 2456 2457 if (secstate) { 2458 mmu_idx |= ARM_MMU_IDX_M_S; 2459 } 2460 2461 return mmu_idx; 2462 } 2463 2464 /* Return the MMU index for a v7M CPU in the specified security state */ 2465 static inline ARMMMUIdx arm_v7m_mmu_idx_for_secstate(CPUARMState *env, 2466 bool secstate) 2467 { 2468 bool priv = arm_current_el(env) != 0; 2469 2470 return arm_v7m_mmu_idx_for_secstate_and_priv(env, secstate, priv); 2471 } 2472 2473 /* Determine the current mmu_idx to use for normal loads/stores */ 2474 static inline int cpu_mmu_index(CPUARMState *env, bool ifetch) 2475 { 2476 int el = arm_current_el(env); 2477 2478 if (arm_feature(env, ARM_FEATURE_M)) { 2479 ARMMMUIdx mmu_idx = arm_v7m_mmu_idx_for_secstate(env, env->v7m.secure); 2480 2481 return arm_to_core_mmu_idx(mmu_idx); 2482 } 2483 2484 if (el < 2 && arm_is_secure_below_el3(env)) { 2485 return arm_to_core_mmu_idx(ARMMMUIdx_S1SE0 + el); 2486 } 2487 return el; 2488 } 2489 2490 /* Indexes used when registering address spaces with cpu_address_space_init */ 2491 typedef enum ARMASIdx { 2492 ARMASIdx_NS = 0, 2493 ARMASIdx_S = 1, 2494 } ARMASIdx; 2495 2496 /* Return the Exception Level targeted by debug exceptions. */ 2497 static inline int arm_debug_target_el(CPUARMState *env) 2498 { 2499 bool secure = arm_is_secure(env); 2500 bool route_to_el2 = false; 2501 2502 if (arm_feature(env, ARM_FEATURE_EL2) && !secure) { 2503 route_to_el2 = env->cp15.hcr_el2 & HCR_TGE || 2504 env->cp15.mdcr_el2 & (1 << 8); 2505 } 2506 2507 if (route_to_el2) { 2508 return 2; 2509 } else if (arm_feature(env, ARM_FEATURE_EL3) && 2510 !arm_el_is_aa64(env, 3) && secure) { 2511 return 3; 2512 } else { 2513 return 1; 2514 } 2515 } 2516 2517 static inline bool arm_v7m_csselr_razwi(ARMCPU *cpu) 2518 { 2519 /* If all the CLIDR.Ctypem bits are 0 there are no caches, and 2520 * CSSELR is RAZ/WI. 2521 */ 2522 return (cpu->clidr & R_V7M_CLIDR_CTYPE_ALL_MASK) != 0; 2523 } 2524 2525 static inline bool aa64_generate_debug_exceptions(CPUARMState *env) 2526 { 2527 if (arm_is_secure(env)) { 2528 /* MDCR_EL3.SDD disables debug events from Secure state */ 2529 if (extract32(env->cp15.mdcr_el3, 16, 1) != 0 2530 || arm_current_el(env) == 3) { 2531 return false; 2532 } 2533 } 2534 2535 if (arm_current_el(env) == arm_debug_target_el(env)) { 2536 if ((extract32(env->cp15.mdscr_el1, 13, 1) == 0) 2537 || (env->daif & PSTATE_D)) { 2538 return false; 2539 } 2540 } 2541 return true; 2542 } 2543 2544 static inline bool aa32_generate_debug_exceptions(CPUARMState *env) 2545 { 2546 int el = arm_current_el(env); 2547 2548 if (el == 0 && arm_el_is_aa64(env, 1)) { 2549 return aa64_generate_debug_exceptions(env); 2550 } 2551 2552 if (arm_is_secure(env)) { 2553 int spd; 2554 2555 if (el == 0 && (env->cp15.sder & 1)) { 2556 /* SDER.SUIDEN means debug exceptions from Secure EL0 2557 * are always enabled. Otherwise they are controlled by 2558 * SDCR.SPD like those from other Secure ELs. 2559 */ 2560 return true; 2561 } 2562 2563 spd = extract32(env->cp15.mdcr_el3, 14, 2); 2564 switch (spd) { 2565 case 1: 2566 /* SPD == 0b01 is reserved, but behaves as 0b00. */ 2567 case 0: 2568 /* For 0b00 we return true if external secure invasive debug 2569 * is enabled. On real hardware this is controlled by external 2570 * signals to the core. QEMU always permits debug, and behaves 2571 * as if DBGEN, SPIDEN, NIDEN and SPNIDEN are all tied high. 2572 */ 2573 return true; 2574 case 2: 2575 return false; 2576 case 3: 2577 return true; 2578 } 2579 } 2580 2581 return el != 2; 2582 } 2583 2584 /* Return true if debugging exceptions are currently enabled. 2585 * This corresponds to what in ARM ARM pseudocode would be 2586 * if UsingAArch32() then 2587 * return AArch32.GenerateDebugExceptions() 2588 * else 2589 * return AArch64.GenerateDebugExceptions() 2590 * We choose to push the if() down into this function for clarity, 2591 * since the pseudocode has it at all callsites except for the one in 2592 * CheckSoftwareStep(), where it is elided because both branches would 2593 * always return the same value. 2594 * 2595 * Parts of the pseudocode relating to EL2 and EL3 are omitted because we 2596 * don't yet implement those exception levels or their associated trap bits. 2597 */ 2598 static inline bool arm_generate_debug_exceptions(CPUARMState *env) 2599 { 2600 if (env->aarch64) { 2601 return aa64_generate_debug_exceptions(env); 2602 } else { 2603 return aa32_generate_debug_exceptions(env); 2604 } 2605 } 2606 2607 /* Is single-stepping active? (Note that the "is EL_D AArch64?" check 2608 * implicitly means this always returns false in pre-v8 CPUs.) 2609 */ 2610 static inline bool arm_singlestep_active(CPUARMState *env) 2611 { 2612 return extract32(env->cp15.mdscr_el1, 0, 1) 2613 && arm_el_is_aa64(env, arm_debug_target_el(env)) 2614 && arm_generate_debug_exceptions(env); 2615 } 2616 2617 static inline bool arm_sctlr_b(CPUARMState *env) 2618 { 2619 return 2620 /* We need not implement SCTLR.ITD in user-mode emulation, so 2621 * let linux-user ignore the fact that it conflicts with SCTLR_B. 2622 * This lets people run BE32 binaries with "-cpu any". 2623 */ 2624 #ifndef CONFIG_USER_ONLY 2625 !arm_feature(env, ARM_FEATURE_V7) && 2626 #endif 2627 (env->cp15.sctlr_el[1] & SCTLR_B) != 0; 2628 } 2629 2630 /* Return true if the processor is in big-endian mode. */ 2631 static inline bool arm_cpu_data_is_big_endian(CPUARMState *env) 2632 { 2633 int cur_el; 2634 2635 /* In 32bit endianness is determined by looking at CPSR's E bit */ 2636 if (!is_a64(env)) { 2637 return 2638 #ifdef CONFIG_USER_ONLY 2639 /* In system mode, BE32 is modelled in line with the 2640 * architecture (as word-invariant big-endianness), where loads 2641 * and stores are done little endian but from addresses which 2642 * are adjusted by XORing with the appropriate constant. So the 2643 * endianness to use for the raw data access is not affected by 2644 * SCTLR.B. 2645 * In user mode, however, we model BE32 as byte-invariant 2646 * big-endianness (because user-only code cannot tell the 2647 * difference), and so we need to use a data access endianness 2648 * that depends on SCTLR.B. 2649 */ 2650 arm_sctlr_b(env) || 2651 #endif 2652 ((env->uncached_cpsr & CPSR_E) ? 1 : 0); 2653 } 2654 2655 cur_el = arm_current_el(env); 2656 2657 if (cur_el == 0) { 2658 return (env->cp15.sctlr_el[1] & SCTLR_E0E) != 0; 2659 } 2660 2661 return (env->cp15.sctlr_el[cur_el] & SCTLR_EE) != 0; 2662 } 2663 2664 #include "exec/cpu-all.h" 2665 2666 /* Bit usage in the TB flags field: bit 31 indicates whether we are 2667 * in 32 or 64 bit mode. The meaning of the other bits depends on that. 2668 * We put flags which are shared between 32 and 64 bit mode at the top 2669 * of the word, and flags which apply to only one mode at the bottom. 2670 */ 2671 #define ARM_TBFLAG_AARCH64_STATE_SHIFT 31 2672 #define ARM_TBFLAG_AARCH64_STATE_MASK (1U << ARM_TBFLAG_AARCH64_STATE_SHIFT) 2673 #define ARM_TBFLAG_MMUIDX_SHIFT 28 2674 #define ARM_TBFLAG_MMUIDX_MASK (0x7 << ARM_TBFLAG_MMUIDX_SHIFT) 2675 #define ARM_TBFLAG_SS_ACTIVE_SHIFT 27 2676 #define ARM_TBFLAG_SS_ACTIVE_MASK (1 << ARM_TBFLAG_SS_ACTIVE_SHIFT) 2677 #define ARM_TBFLAG_PSTATE_SS_SHIFT 26 2678 #define ARM_TBFLAG_PSTATE_SS_MASK (1 << ARM_TBFLAG_PSTATE_SS_SHIFT) 2679 /* Target EL if we take a floating-point-disabled exception */ 2680 #define ARM_TBFLAG_FPEXC_EL_SHIFT 24 2681 #define ARM_TBFLAG_FPEXC_EL_MASK (0x3 << ARM_TBFLAG_FPEXC_EL_SHIFT) 2682 2683 /* Bit usage when in AArch32 state: */ 2684 #define ARM_TBFLAG_THUMB_SHIFT 0 2685 #define ARM_TBFLAG_THUMB_MASK (1 << ARM_TBFLAG_THUMB_SHIFT) 2686 #define ARM_TBFLAG_VECLEN_SHIFT 1 2687 #define ARM_TBFLAG_VECLEN_MASK (0x7 << ARM_TBFLAG_VECLEN_SHIFT) 2688 #define ARM_TBFLAG_VECSTRIDE_SHIFT 4 2689 #define ARM_TBFLAG_VECSTRIDE_MASK (0x3 << ARM_TBFLAG_VECSTRIDE_SHIFT) 2690 #define ARM_TBFLAG_VFPEN_SHIFT 7 2691 #define ARM_TBFLAG_VFPEN_MASK (1 << ARM_TBFLAG_VFPEN_SHIFT) 2692 #define ARM_TBFLAG_CONDEXEC_SHIFT 8 2693 #define ARM_TBFLAG_CONDEXEC_MASK (0xff << ARM_TBFLAG_CONDEXEC_SHIFT) 2694 #define ARM_TBFLAG_SCTLR_B_SHIFT 16 2695 #define ARM_TBFLAG_SCTLR_B_MASK (1 << ARM_TBFLAG_SCTLR_B_SHIFT) 2696 /* We store the bottom two bits of the CPAR as TB flags and handle 2697 * checks on the other bits at runtime 2698 */ 2699 #define ARM_TBFLAG_XSCALE_CPAR_SHIFT 17 2700 #define ARM_TBFLAG_XSCALE_CPAR_MASK (3 << ARM_TBFLAG_XSCALE_CPAR_SHIFT) 2701 /* Indicates whether cp register reads and writes by guest code should access 2702 * the secure or nonsecure bank of banked registers; note that this is not 2703 * the same thing as the current security state of the processor! 2704 */ 2705 #define ARM_TBFLAG_NS_SHIFT 19 2706 #define ARM_TBFLAG_NS_MASK (1 << ARM_TBFLAG_NS_SHIFT) 2707 #define ARM_TBFLAG_BE_DATA_SHIFT 20 2708 #define ARM_TBFLAG_BE_DATA_MASK (1 << ARM_TBFLAG_BE_DATA_SHIFT) 2709 /* For M profile only, Handler (ie not Thread) mode */ 2710 #define ARM_TBFLAG_HANDLER_SHIFT 21 2711 #define ARM_TBFLAG_HANDLER_MASK (1 << ARM_TBFLAG_HANDLER_SHIFT) 2712 2713 /* Bit usage when in AArch64 state */ 2714 #define ARM_TBFLAG_TBI0_SHIFT 0 /* TBI0 for EL0/1 or TBI for EL2/3 */ 2715 #define ARM_TBFLAG_TBI0_MASK (0x1ull << ARM_TBFLAG_TBI0_SHIFT) 2716 #define ARM_TBFLAG_TBI1_SHIFT 1 /* TBI1 for EL0/1 */ 2717 #define ARM_TBFLAG_TBI1_MASK (0x1ull << ARM_TBFLAG_TBI1_SHIFT) 2718 #define ARM_TBFLAG_SVEEXC_EL_SHIFT 2 2719 #define ARM_TBFLAG_SVEEXC_EL_MASK (0x3 << ARM_TBFLAG_SVEEXC_EL_SHIFT) 2720 #define ARM_TBFLAG_ZCR_LEN_SHIFT 4 2721 #define ARM_TBFLAG_ZCR_LEN_MASK (0xf << ARM_TBFLAG_ZCR_LEN_SHIFT) 2722 2723 /* some convenience accessor macros */ 2724 #define ARM_TBFLAG_AARCH64_STATE(F) \ 2725 (((F) & ARM_TBFLAG_AARCH64_STATE_MASK) >> ARM_TBFLAG_AARCH64_STATE_SHIFT) 2726 #define ARM_TBFLAG_MMUIDX(F) \ 2727 (((F) & ARM_TBFLAG_MMUIDX_MASK) >> ARM_TBFLAG_MMUIDX_SHIFT) 2728 #define ARM_TBFLAG_SS_ACTIVE(F) \ 2729 (((F) & ARM_TBFLAG_SS_ACTIVE_MASK) >> ARM_TBFLAG_SS_ACTIVE_SHIFT) 2730 #define ARM_TBFLAG_PSTATE_SS(F) \ 2731 (((F) & ARM_TBFLAG_PSTATE_SS_MASK) >> ARM_TBFLAG_PSTATE_SS_SHIFT) 2732 #define ARM_TBFLAG_FPEXC_EL(F) \ 2733 (((F) & ARM_TBFLAG_FPEXC_EL_MASK) >> ARM_TBFLAG_FPEXC_EL_SHIFT) 2734 #define ARM_TBFLAG_THUMB(F) \ 2735 (((F) & ARM_TBFLAG_THUMB_MASK) >> ARM_TBFLAG_THUMB_SHIFT) 2736 #define ARM_TBFLAG_VECLEN(F) \ 2737 (((F) & ARM_TBFLAG_VECLEN_MASK) >> ARM_TBFLAG_VECLEN_SHIFT) 2738 #define ARM_TBFLAG_VECSTRIDE(F) \ 2739 (((F) & ARM_TBFLAG_VECSTRIDE_MASK) >> ARM_TBFLAG_VECSTRIDE_SHIFT) 2740 #define ARM_TBFLAG_VFPEN(F) \ 2741 (((F) & ARM_TBFLAG_VFPEN_MASK) >> ARM_TBFLAG_VFPEN_SHIFT) 2742 #define ARM_TBFLAG_CONDEXEC(F) \ 2743 (((F) & ARM_TBFLAG_CONDEXEC_MASK) >> ARM_TBFLAG_CONDEXEC_SHIFT) 2744 #define ARM_TBFLAG_SCTLR_B(F) \ 2745 (((F) & ARM_TBFLAG_SCTLR_B_MASK) >> ARM_TBFLAG_SCTLR_B_SHIFT) 2746 #define ARM_TBFLAG_XSCALE_CPAR(F) \ 2747 (((F) & ARM_TBFLAG_XSCALE_CPAR_MASK) >> ARM_TBFLAG_XSCALE_CPAR_SHIFT) 2748 #define ARM_TBFLAG_NS(F) \ 2749 (((F) & ARM_TBFLAG_NS_MASK) >> ARM_TBFLAG_NS_SHIFT) 2750 #define ARM_TBFLAG_BE_DATA(F) \ 2751 (((F) & ARM_TBFLAG_BE_DATA_MASK) >> ARM_TBFLAG_BE_DATA_SHIFT) 2752 #define ARM_TBFLAG_HANDLER(F) \ 2753 (((F) & ARM_TBFLAG_HANDLER_MASK) >> ARM_TBFLAG_HANDLER_SHIFT) 2754 #define ARM_TBFLAG_TBI0(F) \ 2755 (((F) & ARM_TBFLAG_TBI0_MASK) >> ARM_TBFLAG_TBI0_SHIFT) 2756 #define ARM_TBFLAG_TBI1(F) \ 2757 (((F) & ARM_TBFLAG_TBI1_MASK) >> ARM_TBFLAG_TBI1_SHIFT) 2758 #define ARM_TBFLAG_SVEEXC_EL(F) \ 2759 (((F) & ARM_TBFLAG_SVEEXC_EL_MASK) >> ARM_TBFLAG_SVEEXC_EL_SHIFT) 2760 #define ARM_TBFLAG_ZCR_LEN(F) \ 2761 (((F) & ARM_TBFLAG_ZCR_LEN_MASK) >> ARM_TBFLAG_ZCR_LEN_SHIFT) 2762 2763 static inline bool bswap_code(bool sctlr_b) 2764 { 2765 #ifdef CONFIG_USER_ONLY 2766 /* BE8 (SCTLR.B = 0, TARGET_WORDS_BIGENDIAN = 1) is mixed endian. 2767 * The invalid combination SCTLR.B=1/CPSR.E=1/TARGET_WORDS_BIGENDIAN=0 2768 * would also end up as a mixed-endian mode with BE code, LE data. 2769 */ 2770 return 2771 #ifdef TARGET_WORDS_BIGENDIAN 2772 1 ^ 2773 #endif 2774 sctlr_b; 2775 #else 2776 /* All code access in ARM is little endian, and there are no loaders 2777 * doing swaps that need to be reversed 2778 */ 2779 return 0; 2780 #endif 2781 } 2782 2783 #ifdef CONFIG_USER_ONLY 2784 static inline bool arm_cpu_bswap_data(CPUARMState *env) 2785 { 2786 return 2787 #ifdef TARGET_WORDS_BIGENDIAN 2788 1 ^ 2789 #endif 2790 arm_cpu_data_is_big_endian(env); 2791 } 2792 #endif 2793 2794 #ifndef CONFIG_USER_ONLY 2795 /** 2796 * arm_regime_tbi0: 2797 * @env: CPUARMState 2798 * @mmu_idx: MMU index indicating required translation regime 2799 * 2800 * Extracts the TBI0 value from the appropriate TCR for the current EL 2801 * 2802 * Returns: the TBI0 value. 2803 */ 2804 uint32_t arm_regime_tbi0(CPUARMState *env, ARMMMUIdx mmu_idx); 2805 2806 /** 2807 * arm_regime_tbi1: 2808 * @env: CPUARMState 2809 * @mmu_idx: MMU index indicating required translation regime 2810 * 2811 * Extracts the TBI1 value from the appropriate TCR for the current EL 2812 * 2813 * Returns: the TBI1 value. 2814 */ 2815 uint32_t arm_regime_tbi1(CPUARMState *env, ARMMMUIdx mmu_idx); 2816 #else 2817 /* We can't handle tagged addresses properly in user-only mode */ 2818 static inline uint32_t arm_regime_tbi0(CPUARMState *env, ARMMMUIdx mmu_idx) 2819 { 2820 return 0; 2821 } 2822 2823 static inline uint32_t arm_regime_tbi1(CPUARMState *env, ARMMMUIdx mmu_idx) 2824 { 2825 return 0; 2826 } 2827 #endif 2828 2829 void cpu_get_tb_cpu_state(CPUARMState *env, target_ulong *pc, 2830 target_ulong *cs_base, uint32_t *flags); 2831 2832 enum { 2833 QEMU_PSCI_CONDUIT_DISABLED = 0, 2834 QEMU_PSCI_CONDUIT_SMC = 1, 2835 QEMU_PSCI_CONDUIT_HVC = 2, 2836 }; 2837 2838 #ifndef CONFIG_USER_ONLY 2839 /* Return the address space index to use for a memory access */ 2840 static inline int arm_asidx_from_attrs(CPUState *cs, MemTxAttrs attrs) 2841 { 2842 return attrs.secure ? ARMASIdx_S : ARMASIdx_NS; 2843 } 2844 2845 /* Return the AddressSpace to use for a memory access 2846 * (which depends on whether the access is S or NS, and whether 2847 * the board gave us a separate AddressSpace for S accesses). 2848 */ 2849 static inline AddressSpace *arm_addressspace(CPUState *cs, MemTxAttrs attrs) 2850 { 2851 return cpu_get_address_space(cs, arm_asidx_from_attrs(cs, attrs)); 2852 } 2853 #endif 2854 2855 /** 2856 * arm_register_el_change_hook: 2857 * Register a hook function which will be called back whenever this 2858 * CPU changes exception level or mode. The hook function will be 2859 * passed a pointer to the ARMCPU and the opaque data pointer passed 2860 * to this function when the hook was registered. 2861 * 2862 * Note that we currently only support registering a single hook function, 2863 * and will assert if this function is called twice. 2864 * This facility is intended for the use of the GICv3 emulation. 2865 */ 2866 void arm_register_el_change_hook(ARMCPU *cpu, ARMELChangeHook *hook, 2867 void *opaque); 2868 2869 /** 2870 * arm_get_el_change_hook_opaque: 2871 * Return the opaque data that will be used by the el_change_hook 2872 * for this CPU. 2873 */ 2874 static inline void *arm_get_el_change_hook_opaque(ARMCPU *cpu) 2875 { 2876 return cpu->el_change_hook_opaque; 2877 } 2878 2879 /** 2880 * aa32_vfp_dreg: 2881 * Return a pointer to the Dn register within env in 32-bit mode. 2882 */ 2883 static inline uint64_t *aa32_vfp_dreg(CPUARMState *env, unsigned regno) 2884 { 2885 return &env->vfp.zregs[regno >> 1].d[regno & 1]; 2886 } 2887 2888 /** 2889 * aa32_vfp_qreg: 2890 * Return a pointer to the Qn register within env in 32-bit mode. 2891 */ 2892 static inline uint64_t *aa32_vfp_qreg(CPUARMState *env, unsigned regno) 2893 { 2894 return &env->vfp.zregs[regno].d[0]; 2895 } 2896 2897 /** 2898 * aa64_vfp_qreg: 2899 * Return a pointer to the Qn register within env in 64-bit mode. 2900 */ 2901 static inline uint64_t *aa64_vfp_qreg(CPUARMState *env, unsigned regno) 2902 { 2903 return &env->vfp.zregs[regno].d[0]; 2904 } 2905 2906 #endif 2907