1 /* 2 * ARM virtual CPU header 3 * 4 * Copyright (c) 2003 Fabrice Bellard 5 * 6 * This library is free software; you can redistribute it and/or 7 * modify it under the terms of the GNU Lesser General Public 8 * License as published by the Free Software Foundation; either 9 * version 2 of the License, or (at your option) any later version. 10 * 11 * This library is distributed in the hope that it will be useful, 12 * but WITHOUT ANY WARRANTY; without even the implied warranty of 13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU 14 * Lesser General Public License for more details. 15 * 16 * You should have received a copy of the GNU Lesser General Public 17 * License along with this library; if not, see <http://www.gnu.org/licenses/>. 18 */ 19 20 #ifndef ARM_CPU_H 21 #define ARM_CPU_H 22 23 #include "kvm-consts.h" 24 #include "hw/registerfields.h" 25 26 #if defined(TARGET_AARCH64) 27 /* AArch64 definitions */ 28 # define TARGET_LONG_BITS 64 29 #else 30 # define TARGET_LONG_BITS 32 31 #endif 32 33 /* ARM processors have a weak memory model */ 34 #define TCG_GUEST_DEFAULT_MO (0) 35 36 #define CPUArchState struct CPUARMState 37 38 #include "qemu-common.h" 39 #include "cpu-qom.h" 40 #include "exec/cpu-defs.h" 41 42 #include "fpu/softfloat.h" 43 44 #define EXCP_UDEF 1 /* undefined instruction */ 45 #define EXCP_SWI 2 /* software interrupt */ 46 #define EXCP_PREFETCH_ABORT 3 47 #define EXCP_DATA_ABORT 4 48 #define EXCP_IRQ 5 49 #define EXCP_FIQ 6 50 #define EXCP_BKPT 7 51 #define EXCP_EXCEPTION_EXIT 8 /* Return from v7M exception. */ 52 #define EXCP_KERNEL_TRAP 9 /* Jumped to kernel code page. */ 53 #define EXCP_HVC 11 /* HyperVisor Call */ 54 #define EXCP_HYP_TRAP 12 55 #define EXCP_SMC 13 /* Secure Monitor Call */ 56 #define EXCP_VIRQ 14 57 #define EXCP_VFIQ 15 58 #define EXCP_SEMIHOST 16 /* semihosting call */ 59 #define EXCP_NOCP 17 /* v7M NOCP UsageFault */ 60 #define EXCP_INVSTATE 18 /* v7M INVSTATE UsageFault */ 61 /* NB: add new EXCP_ defines to the array in arm_log_exception() too */ 62 63 #define ARMV7M_EXCP_RESET 1 64 #define ARMV7M_EXCP_NMI 2 65 #define ARMV7M_EXCP_HARD 3 66 #define ARMV7M_EXCP_MEM 4 67 #define ARMV7M_EXCP_BUS 5 68 #define ARMV7M_EXCP_USAGE 6 69 #define ARMV7M_EXCP_SVC 11 70 #define ARMV7M_EXCP_DEBUG 12 71 #define ARMV7M_EXCP_PENDSV 14 72 #define ARMV7M_EXCP_SYSTICK 15 73 74 /* ARM-specific interrupt pending bits. */ 75 #define CPU_INTERRUPT_FIQ CPU_INTERRUPT_TGT_EXT_1 76 #define CPU_INTERRUPT_VIRQ CPU_INTERRUPT_TGT_EXT_2 77 #define CPU_INTERRUPT_VFIQ CPU_INTERRUPT_TGT_EXT_3 78 79 /* The usual mapping for an AArch64 system register to its AArch32 80 * counterpart is for the 32 bit world to have access to the lower 81 * half only (with writes leaving the upper half untouched). It's 82 * therefore useful to be able to pass TCG the offset of the least 83 * significant half of a uint64_t struct member. 84 */ 85 #ifdef HOST_WORDS_BIGENDIAN 86 #define offsetoflow32(S, M) (offsetof(S, M) + sizeof(uint32_t)) 87 #define offsetofhigh32(S, M) offsetof(S, M) 88 #else 89 #define offsetoflow32(S, M) offsetof(S, M) 90 #define offsetofhigh32(S, M) (offsetof(S, M) + sizeof(uint32_t)) 91 #endif 92 93 /* Meanings of the ARMCPU object's four inbound GPIO lines */ 94 #define ARM_CPU_IRQ 0 95 #define ARM_CPU_FIQ 1 96 #define ARM_CPU_VIRQ 2 97 #define ARM_CPU_VFIQ 3 98 99 #define NB_MMU_MODES 7 100 /* ARM-specific extra insn start words: 101 * 1: Conditional execution bits 102 * 2: Partial exception syndrome for data aborts 103 */ 104 #define TARGET_INSN_START_EXTRA_WORDS 2 105 106 /* The 2nd extra word holding syndrome info for data aborts does not use 107 * the upper 6 bits nor the lower 14 bits. We mask and shift it down to 108 * help the sleb128 encoder do a better job. 109 * When restoring the CPU state, we shift it back up. 110 */ 111 #define ARM_INSN_START_WORD2_MASK ((1 << 26) - 1) 112 #define ARM_INSN_START_WORD2_SHIFT 14 113 114 /* We currently assume float and double are IEEE single and double 115 precision respectively. 116 Doing runtime conversions is tricky because VFP registers may contain 117 integer values (eg. as the result of a FTOSI instruction). 118 s<2n> maps to the least significant half of d<n> 119 s<2n+1> maps to the most significant half of d<n> 120 */ 121 122 /* CPU state for each instance of a generic timer (in cp15 c14) */ 123 typedef struct ARMGenericTimer { 124 uint64_t cval; /* Timer CompareValue register */ 125 uint64_t ctl; /* Timer Control register */ 126 } ARMGenericTimer; 127 128 #define GTIMER_PHYS 0 129 #define GTIMER_VIRT 1 130 #define GTIMER_HYP 2 131 #define GTIMER_SEC 3 132 #define NUM_GTIMERS 4 133 134 typedef struct { 135 uint64_t raw_tcr; 136 uint32_t mask; 137 uint32_t base_mask; 138 } TCR; 139 140 typedef struct CPUARMState { 141 /* Regs for current mode. */ 142 uint32_t regs[16]; 143 144 /* 32/64 switch only happens when taking and returning from 145 * exceptions so the overlap semantics are taken care of then 146 * instead of having a complicated union. 147 */ 148 /* Regs for A64 mode. */ 149 uint64_t xregs[32]; 150 uint64_t pc; 151 /* PSTATE isn't an architectural register for ARMv8. However, it is 152 * convenient for us to assemble the underlying state into a 32 bit format 153 * identical to the architectural format used for the SPSR. (This is also 154 * what the Linux kernel's 'pstate' field in signal handlers and KVM's 155 * 'pstate' register are.) Of the PSTATE bits: 156 * NZCV are kept in the split out env->CF/VF/NF/ZF, (which have the same 157 * semantics as for AArch32, as described in the comments on each field) 158 * nRW (also known as M[4]) is kept, inverted, in env->aarch64 159 * DAIF (exception masks) are kept in env->daif 160 * all other bits are stored in their correct places in env->pstate 161 */ 162 uint32_t pstate; 163 uint32_t aarch64; /* 1 if CPU is in aarch64 state; inverse of PSTATE.nRW */ 164 165 /* Frequently accessed CPSR bits are stored separately for efficiency. 166 This contains all the other bits. Use cpsr_{read,write} to access 167 the whole CPSR. */ 168 uint32_t uncached_cpsr; 169 uint32_t spsr; 170 171 /* Banked registers. */ 172 uint64_t banked_spsr[8]; 173 uint32_t banked_r13[8]; 174 uint32_t banked_r14[8]; 175 176 /* These hold r8-r12. */ 177 uint32_t usr_regs[5]; 178 uint32_t fiq_regs[5]; 179 180 /* cpsr flag cache for faster execution */ 181 uint32_t CF; /* 0 or 1 */ 182 uint32_t VF; /* V is the bit 31. All other bits are undefined */ 183 uint32_t NF; /* N is bit 31. All other bits are undefined. */ 184 uint32_t ZF; /* Z set if zero. */ 185 uint32_t QF; /* 0 or 1 */ 186 uint32_t GE; /* cpsr[19:16] */ 187 uint32_t thumb; /* cpsr[5]. 0 = arm mode, 1 = thumb mode. */ 188 uint32_t condexec_bits; /* IT bits. cpsr[15:10,26:25]. */ 189 uint64_t daif; /* exception masks, in the bits they are in PSTATE */ 190 191 uint64_t elr_el[4]; /* AArch64 exception link regs */ 192 uint64_t sp_el[4]; /* AArch64 banked stack pointers */ 193 194 /* System control coprocessor (cp15) */ 195 struct { 196 uint32_t c0_cpuid; 197 union { /* Cache size selection */ 198 struct { 199 uint64_t _unused_csselr0; 200 uint64_t csselr_ns; 201 uint64_t _unused_csselr1; 202 uint64_t csselr_s; 203 }; 204 uint64_t csselr_el[4]; 205 }; 206 union { /* System control register. */ 207 struct { 208 uint64_t _unused_sctlr; 209 uint64_t sctlr_ns; 210 uint64_t hsctlr; 211 uint64_t sctlr_s; 212 }; 213 uint64_t sctlr_el[4]; 214 }; 215 uint64_t cpacr_el1; /* Architectural feature access control register */ 216 uint64_t cptr_el[4]; /* ARMv8 feature trap registers */ 217 uint32_t c1_xscaleauxcr; /* XScale auxiliary control register. */ 218 uint64_t sder; /* Secure debug enable register. */ 219 uint32_t nsacr; /* Non-secure access control register. */ 220 union { /* MMU translation table base 0. */ 221 struct { 222 uint64_t _unused_ttbr0_0; 223 uint64_t ttbr0_ns; 224 uint64_t _unused_ttbr0_1; 225 uint64_t ttbr0_s; 226 }; 227 uint64_t ttbr0_el[4]; 228 }; 229 union { /* MMU translation table base 1. */ 230 struct { 231 uint64_t _unused_ttbr1_0; 232 uint64_t ttbr1_ns; 233 uint64_t _unused_ttbr1_1; 234 uint64_t ttbr1_s; 235 }; 236 uint64_t ttbr1_el[4]; 237 }; 238 uint64_t vttbr_el2; /* Virtualization Translation Table Base. */ 239 /* MMU translation table base control. */ 240 TCR tcr_el[4]; 241 TCR vtcr_el2; /* Virtualization Translation Control. */ 242 uint32_t c2_data; /* MPU data cacheable bits. */ 243 uint32_t c2_insn; /* MPU instruction cacheable bits. */ 244 union { /* MMU domain access control register 245 * MPU write buffer control. 246 */ 247 struct { 248 uint64_t dacr_ns; 249 uint64_t dacr_s; 250 }; 251 struct { 252 uint64_t dacr32_el2; 253 }; 254 }; 255 uint32_t pmsav5_data_ap; /* PMSAv5 MPU data access permissions */ 256 uint32_t pmsav5_insn_ap; /* PMSAv5 MPU insn access permissions */ 257 uint64_t hcr_el2; /* Hypervisor configuration register */ 258 uint64_t scr_el3; /* Secure configuration register. */ 259 union { /* Fault status registers. */ 260 struct { 261 uint64_t ifsr_ns; 262 uint64_t ifsr_s; 263 }; 264 struct { 265 uint64_t ifsr32_el2; 266 }; 267 }; 268 union { 269 struct { 270 uint64_t _unused_dfsr; 271 uint64_t dfsr_ns; 272 uint64_t hsr; 273 uint64_t dfsr_s; 274 }; 275 uint64_t esr_el[4]; 276 }; 277 uint32_t c6_region[8]; /* MPU base/size registers. */ 278 union { /* Fault address registers. */ 279 struct { 280 uint64_t _unused_far0; 281 #ifdef HOST_WORDS_BIGENDIAN 282 uint32_t ifar_ns; 283 uint32_t dfar_ns; 284 uint32_t ifar_s; 285 uint32_t dfar_s; 286 #else 287 uint32_t dfar_ns; 288 uint32_t ifar_ns; 289 uint32_t dfar_s; 290 uint32_t ifar_s; 291 #endif 292 uint64_t _unused_far3; 293 }; 294 uint64_t far_el[4]; 295 }; 296 uint64_t hpfar_el2; 297 uint64_t hstr_el2; 298 union { /* Translation result. */ 299 struct { 300 uint64_t _unused_par_0; 301 uint64_t par_ns; 302 uint64_t _unused_par_1; 303 uint64_t par_s; 304 }; 305 uint64_t par_el[4]; 306 }; 307 308 uint32_t c9_insn; /* Cache lockdown registers. */ 309 uint32_t c9_data; 310 uint64_t c9_pmcr; /* performance monitor control register */ 311 uint64_t c9_pmcnten; /* perf monitor counter enables */ 312 uint32_t c9_pmovsr; /* perf monitor overflow status */ 313 uint32_t c9_pmuserenr; /* perf monitor user enable */ 314 uint64_t c9_pmselr; /* perf monitor counter selection register */ 315 uint64_t c9_pminten; /* perf monitor interrupt enables */ 316 union { /* Memory attribute redirection */ 317 struct { 318 #ifdef HOST_WORDS_BIGENDIAN 319 uint64_t _unused_mair_0; 320 uint32_t mair1_ns; 321 uint32_t mair0_ns; 322 uint64_t _unused_mair_1; 323 uint32_t mair1_s; 324 uint32_t mair0_s; 325 #else 326 uint64_t _unused_mair_0; 327 uint32_t mair0_ns; 328 uint32_t mair1_ns; 329 uint64_t _unused_mair_1; 330 uint32_t mair0_s; 331 uint32_t mair1_s; 332 #endif 333 }; 334 uint64_t mair_el[4]; 335 }; 336 union { /* vector base address register */ 337 struct { 338 uint64_t _unused_vbar; 339 uint64_t vbar_ns; 340 uint64_t hvbar; 341 uint64_t vbar_s; 342 }; 343 uint64_t vbar_el[4]; 344 }; 345 uint32_t mvbar; /* (monitor) vector base address register */ 346 struct { /* FCSE PID. */ 347 uint32_t fcseidr_ns; 348 uint32_t fcseidr_s; 349 }; 350 union { /* Context ID. */ 351 struct { 352 uint64_t _unused_contextidr_0; 353 uint64_t contextidr_ns; 354 uint64_t _unused_contextidr_1; 355 uint64_t contextidr_s; 356 }; 357 uint64_t contextidr_el[4]; 358 }; 359 union { /* User RW Thread register. */ 360 struct { 361 uint64_t tpidrurw_ns; 362 uint64_t tpidrprw_ns; 363 uint64_t htpidr; 364 uint64_t _tpidr_el3; 365 }; 366 uint64_t tpidr_el[4]; 367 }; 368 /* The secure banks of these registers don't map anywhere */ 369 uint64_t tpidrurw_s; 370 uint64_t tpidrprw_s; 371 uint64_t tpidruro_s; 372 373 union { /* User RO Thread register. */ 374 uint64_t tpidruro_ns; 375 uint64_t tpidrro_el[1]; 376 }; 377 uint64_t c14_cntfrq; /* Counter Frequency register */ 378 uint64_t c14_cntkctl; /* Timer Control register */ 379 uint32_t cnthctl_el2; /* Counter/Timer Hyp Control register */ 380 uint64_t cntvoff_el2; /* Counter Virtual Offset register */ 381 ARMGenericTimer c14_timer[NUM_GTIMERS]; 382 uint32_t c15_cpar; /* XScale Coprocessor Access Register */ 383 uint32_t c15_ticonfig; /* TI925T configuration byte. */ 384 uint32_t c15_i_max; /* Maximum D-cache dirty line index. */ 385 uint32_t c15_i_min; /* Minimum D-cache dirty line index. */ 386 uint32_t c15_threadid; /* TI debugger thread-ID. */ 387 uint32_t c15_config_base_address; /* SCU base address. */ 388 uint32_t c15_diagnostic; /* diagnostic register */ 389 uint32_t c15_power_diagnostic; 390 uint32_t c15_power_control; /* power control */ 391 uint64_t dbgbvr[16]; /* breakpoint value registers */ 392 uint64_t dbgbcr[16]; /* breakpoint control registers */ 393 uint64_t dbgwvr[16]; /* watchpoint value registers */ 394 uint64_t dbgwcr[16]; /* watchpoint control registers */ 395 uint64_t mdscr_el1; 396 uint64_t oslsr_el1; /* OS Lock Status */ 397 uint64_t mdcr_el2; 398 uint64_t mdcr_el3; 399 /* If the counter is enabled, this stores the last time the counter 400 * was reset. Otherwise it stores the counter value 401 */ 402 uint64_t c15_ccnt; 403 uint64_t pmccfiltr_el0; /* Performance Monitor Filter Register */ 404 uint64_t vpidr_el2; /* Virtualization Processor ID Register */ 405 uint64_t vmpidr_el2; /* Virtualization Multiprocessor ID Register */ 406 } cp15; 407 408 struct { 409 uint32_t other_sp; 410 uint32_t vecbase; 411 uint32_t basepri; 412 uint32_t control; 413 uint32_t ccr; /* Configuration and Control */ 414 uint32_t cfsr; /* Configurable Fault Status */ 415 uint32_t hfsr; /* HardFault Status */ 416 uint32_t dfsr; /* Debug Fault Status Register */ 417 uint32_t mmfar; /* MemManage Fault Address */ 418 uint32_t bfar; /* BusFault Address */ 419 unsigned mpu_ctrl; /* MPU_CTRL */ 420 int exception; 421 uint32_t primask; 422 uint32_t faultmask; 423 } v7m; 424 425 /* Information associated with an exception about to be taken: 426 * code which raises an exception must set cs->exception_index and 427 * the relevant parts of this structure; the cpu_do_interrupt function 428 * will then set the guest-visible registers as part of the exception 429 * entry process. 430 */ 431 struct { 432 uint32_t syndrome; /* AArch64 format syndrome register */ 433 uint32_t fsr; /* AArch32 format fault status register info */ 434 uint64_t vaddress; /* virtual addr associated with exception, if any */ 435 uint32_t target_el; /* EL the exception should be targeted for */ 436 /* If we implement EL2 we will also need to store information 437 * about the intermediate physical address for stage 2 faults. 438 */ 439 } exception; 440 441 /* Thumb-2 EE state. */ 442 uint32_t teecr; 443 uint32_t teehbr; 444 445 /* VFP coprocessor state. */ 446 struct { 447 /* VFP/Neon register state. Note that the mapping between S, D and Q 448 * views of the register bank differs between AArch64 and AArch32: 449 * In AArch32: 450 * Qn = regs[2n+1]:regs[2n] 451 * Dn = regs[n] 452 * Sn = regs[n/2] bits 31..0 for even n, and bits 63..32 for odd n 453 * (and regs[32] to regs[63] are inaccessible) 454 * In AArch64: 455 * Qn = regs[2n+1]:regs[2n] 456 * Dn = regs[2n] 457 * Sn = regs[2n] bits 31..0 458 * This corresponds to the architecturally defined mapping between 459 * the two execution states, and means we do not need to explicitly 460 * map these registers when changing states. 461 */ 462 float64 regs[64]; 463 464 uint32_t xregs[16]; 465 /* We store these fpcsr fields separately for convenience. */ 466 int vec_len; 467 int vec_stride; 468 469 /* scratch space when Tn are not sufficient. */ 470 uint32_t scratch[8]; 471 472 /* fp_status is the "normal" fp status. standard_fp_status retains 473 * values corresponding to the ARM "Standard FPSCR Value", ie 474 * default-NaN, flush-to-zero, round-to-nearest and is used by 475 * any operations (generally Neon) which the architecture defines 476 * as controlled by the standard FPSCR value rather than the FPSCR. 477 * 478 * To avoid having to transfer exception bits around, we simply 479 * say that the FPSCR cumulative exception flags are the logical 480 * OR of the flags in the two fp statuses. This relies on the 481 * only thing which needs to read the exception flags being 482 * an explicit FPSCR read. 483 */ 484 float_status fp_status; 485 float_status standard_fp_status; 486 } vfp; 487 uint64_t exclusive_addr; 488 uint64_t exclusive_val; 489 uint64_t exclusive_high; 490 491 /* iwMMXt coprocessor state. */ 492 struct { 493 uint64_t regs[16]; 494 uint64_t val; 495 496 uint32_t cregs[16]; 497 } iwmmxt; 498 499 #if defined(CONFIG_USER_ONLY) 500 /* For usermode syscall translation. */ 501 int eabi; 502 #endif 503 504 struct CPUBreakpoint *cpu_breakpoint[16]; 505 struct CPUWatchpoint *cpu_watchpoint[16]; 506 507 /* Fields up to this point are cleared by a CPU reset */ 508 struct {} end_reset_fields; 509 510 CPU_COMMON 511 512 /* Fields after CPU_COMMON are preserved across CPU reset. */ 513 514 /* Internal CPU feature flags. */ 515 uint64_t features; 516 517 /* PMSAv7 MPU */ 518 struct { 519 uint32_t *drbar; 520 uint32_t *drsr; 521 uint32_t *dracr; 522 uint32_t rnr; 523 } pmsav7; 524 525 void *nvic; 526 const struct arm_boot_info *boot_info; 527 /* Store GICv3CPUState to access from this struct */ 528 void *gicv3state; 529 } CPUARMState; 530 531 /** 532 * ARMELChangeHook: 533 * type of a function which can be registered via arm_register_el_change_hook() 534 * to get callbacks when the CPU changes its exception level or mode. 535 */ 536 typedef void ARMELChangeHook(ARMCPU *cpu, void *opaque); 537 538 539 /* These values map onto the return values for 540 * QEMU_PSCI_0_2_FN_AFFINITY_INFO */ 541 typedef enum ARMPSCIState { 542 PSCI_ON = 0, 543 PSCI_OFF = 1, 544 PSCI_ON_PENDING = 2 545 } ARMPSCIState; 546 547 /** 548 * ARMCPU: 549 * @env: #CPUARMState 550 * 551 * An ARM CPU core. 552 */ 553 struct ARMCPU { 554 /*< private >*/ 555 CPUState parent_obj; 556 /*< public >*/ 557 558 CPUARMState env; 559 560 /* Coprocessor information */ 561 GHashTable *cp_regs; 562 /* For marshalling (mostly coprocessor) register state between the 563 * kernel and QEMU (for KVM) and between two QEMUs (for migration), 564 * we use these arrays. 565 */ 566 /* List of register indexes managed via these arrays; (full KVM style 567 * 64 bit indexes, not CPRegInfo 32 bit indexes) 568 */ 569 uint64_t *cpreg_indexes; 570 /* Values of the registers (cpreg_indexes[i]'s value is cpreg_values[i]) */ 571 uint64_t *cpreg_values; 572 /* Length of the indexes, values, reset_values arrays */ 573 int32_t cpreg_array_len; 574 /* These are used only for migration: incoming data arrives in 575 * these fields and is sanity checked in post_load before copying 576 * to the working data structures above. 577 */ 578 uint64_t *cpreg_vmstate_indexes; 579 uint64_t *cpreg_vmstate_values; 580 int32_t cpreg_vmstate_array_len; 581 582 /* Timers used by the generic (architected) timer */ 583 QEMUTimer *gt_timer[NUM_GTIMERS]; 584 /* GPIO outputs for generic timer */ 585 qemu_irq gt_timer_outputs[NUM_GTIMERS]; 586 /* GPIO output for GICv3 maintenance interrupt signal */ 587 qemu_irq gicv3_maintenance_interrupt; 588 /* GPIO output for the PMU interrupt */ 589 qemu_irq pmu_interrupt; 590 591 /* MemoryRegion to use for secure physical accesses */ 592 MemoryRegion *secure_memory; 593 594 /* 'compatible' string for this CPU for Linux device trees */ 595 const char *dtb_compatible; 596 597 /* PSCI version for this CPU 598 * Bits[31:16] = Major Version 599 * Bits[15:0] = Minor Version 600 */ 601 uint32_t psci_version; 602 603 /* Should CPU start in PSCI powered-off state? */ 604 bool start_powered_off; 605 606 /* Current power state, access guarded by BQL */ 607 ARMPSCIState power_state; 608 609 /* CPU has virtualization extension */ 610 bool has_el2; 611 /* CPU has security extension */ 612 bool has_el3; 613 /* CPU has PMU (Performance Monitor Unit) */ 614 bool has_pmu; 615 616 /* CPU has memory protection unit */ 617 bool has_mpu; 618 /* PMSAv7 MPU number of supported regions */ 619 uint32_t pmsav7_dregion; 620 621 /* PSCI conduit used to invoke PSCI methods 622 * 0 - disabled, 1 - smc, 2 - hvc 623 */ 624 uint32_t psci_conduit; 625 626 /* [QEMU_]KVM_ARM_TARGET_* constant for this CPU, or 627 * QEMU_KVM_ARM_TARGET_NONE if the kernel doesn't support this CPU type. 628 */ 629 uint32_t kvm_target; 630 631 /* KVM init features for this CPU */ 632 uint32_t kvm_init_features[7]; 633 634 /* Uniprocessor system with MP extensions */ 635 bool mp_is_up; 636 637 /* The instance init functions for implementation-specific subclasses 638 * set these fields to specify the implementation-dependent values of 639 * various constant registers and reset values of non-constant 640 * registers. 641 * Some of these might become QOM properties eventually. 642 * Field names match the official register names as defined in the 643 * ARMv7AR ARM Architecture Reference Manual. A reset_ prefix 644 * is used for reset values of non-constant registers; no reset_ 645 * prefix means a constant register. 646 */ 647 uint32_t midr; 648 uint32_t revidr; 649 uint32_t reset_fpsid; 650 uint32_t mvfr0; 651 uint32_t mvfr1; 652 uint32_t mvfr2; 653 uint32_t ctr; 654 uint32_t reset_sctlr; 655 uint32_t id_pfr0; 656 uint32_t id_pfr1; 657 uint32_t id_dfr0; 658 uint32_t pmceid0; 659 uint32_t pmceid1; 660 uint32_t id_afr0; 661 uint32_t id_mmfr0; 662 uint32_t id_mmfr1; 663 uint32_t id_mmfr2; 664 uint32_t id_mmfr3; 665 uint32_t id_mmfr4; 666 uint32_t id_isar0; 667 uint32_t id_isar1; 668 uint32_t id_isar2; 669 uint32_t id_isar3; 670 uint32_t id_isar4; 671 uint32_t id_isar5; 672 uint64_t id_aa64pfr0; 673 uint64_t id_aa64pfr1; 674 uint64_t id_aa64dfr0; 675 uint64_t id_aa64dfr1; 676 uint64_t id_aa64afr0; 677 uint64_t id_aa64afr1; 678 uint64_t id_aa64isar0; 679 uint64_t id_aa64isar1; 680 uint64_t id_aa64mmfr0; 681 uint64_t id_aa64mmfr1; 682 uint32_t dbgdidr; 683 uint32_t clidr; 684 uint64_t mp_affinity; /* MP ID without feature bits */ 685 /* The elements of this array are the CCSIDR values for each cache, 686 * in the order L1DCache, L1ICache, L2DCache, L2ICache, etc. 687 */ 688 uint32_t ccsidr[16]; 689 uint64_t reset_cbar; 690 uint32_t reset_auxcr; 691 bool reset_hivecs; 692 /* DCZ blocksize, in log_2(words), ie low 4 bits of DCZID_EL0 */ 693 uint32_t dcz_blocksize; 694 uint64_t rvbar; 695 696 /* Configurable aspects of GIC cpu interface (which is part of the CPU) */ 697 int gic_num_lrs; /* number of list registers */ 698 int gic_vpribits; /* number of virtual priority bits */ 699 int gic_vprebits; /* number of virtual preemption bits */ 700 701 /* Whether the cfgend input is high (i.e. this CPU should reset into 702 * big-endian mode). This setting isn't used directly: instead it modifies 703 * the reset_sctlr value to have SCTLR_B or SCTLR_EE set, depending on the 704 * architecture version. 705 */ 706 bool cfgend; 707 708 ARMELChangeHook *el_change_hook; 709 void *el_change_hook_opaque; 710 711 int32_t node_id; /* NUMA node this CPU belongs to */ 712 713 /* Used to synchronize KVM and QEMU in-kernel device levels */ 714 uint8_t device_irq_level; 715 }; 716 717 static inline ARMCPU *arm_env_get_cpu(CPUARMState *env) 718 { 719 return container_of(env, ARMCPU, env); 720 } 721 722 uint64_t arm_cpu_mp_affinity(int idx, uint8_t clustersz); 723 724 #define ENV_GET_CPU(e) CPU(arm_env_get_cpu(e)) 725 726 #define ENV_OFFSET offsetof(ARMCPU, env) 727 728 #ifndef CONFIG_USER_ONLY 729 extern const struct VMStateDescription vmstate_arm_cpu; 730 #endif 731 732 void arm_cpu_do_interrupt(CPUState *cpu); 733 void arm_v7m_cpu_do_interrupt(CPUState *cpu); 734 bool arm_cpu_exec_interrupt(CPUState *cpu, int int_req); 735 736 void arm_cpu_dump_state(CPUState *cs, FILE *f, fprintf_function cpu_fprintf, 737 int flags); 738 739 hwaddr arm_cpu_get_phys_page_attrs_debug(CPUState *cpu, vaddr addr, 740 MemTxAttrs *attrs); 741 742 int arm_cpu_gdb_read_register(CPUState *cpu, uint8_t *buf, int reg); 743 int arm_cpu_gdb_write_register(CPUState *cpu, uint8_t *buf, int reg); 744 745 int arm_cpu_write_elf64_note(WriteCoreDumpFunction f, CPUState *cs, 746 int cpuid, void *opaque); 747 int arm_cpu_write_elf32_note(WriteCoreDumpFunction f, CPUState *cs, 748 int cpuid, void *opaque); 749 750 #ifdef TARGET_AARCH64 751 int aarch64_cpu_gdb_read_register(CPUState *cpu, uint8_t *buf, int reg); 752 int aarch64_cpu_gdb_write_register(CPUState *cpu, uint8_t *buf, int reg); 753 #endif 754 755 target_ulong do_arm_semihosting(CPUARMState *env); 756 void aarch64_sync_32_to_64(CPUARMState *env); 757 void aarch64_sync_64_to_32(CPUARMState *env); 758 759 static inline bool is_a64(CPUARMState *env) 760 { 761 return env->aarch64; 762 } 763 764 /* you can call this signal handler from your SIGBUS and SIGSEGV 765 signal handlers to inform the virtual CPU of exceptions. non zero 766 is returned if the signal was handled by the virtual CPU. */ 767 int cpu_arm_signal_handler(int host_signum, void *pinfo, 768 void *puc); 769 770 /** 771 * pmccntr_sync 772 * @env: CPUARMState 773 * 774 * Synchronises the counter in the PMCCNTR. This must always be called twice, 775 * once before any action that might affect the timer and again afterwards. 776 * The function is used to swap the state of the register if required. 777 * This only happens when not in user mode (!CONFIG_USER_ONLY) 778 */ 779 void pmccntr_sync(CPUARMState *env); 780 781 /* SCTLR bit meanings. Several bits have been reused in newer 782 * versions of the architecture; in that case we define constants 783 * for both old and new bit meanings. Code which tests against those 784 * bits should probably check or otherwise arrange that the CPU 785 * is the architectural version it expects. 786 */ 787 #define SCTLR_M (1U << 0) 788 #define SCTLR_A (1U << 1) 789 #define SCTLR_C (1U << 2) 790 #define SCTLR_W (1U << 3) /* up to v6; RAO in v7 */ 791 #define SCTLR_SA (1U << 3) 792 #define SCTLR_P (1U << 4) /* up to v5; RAO in v6 and v7 */ 793 #define SCTLR_SA0 (1U << 4) /* v8 onward, AArch64 only */ 794 #define SCTLR_D (1U << 5) /* up to v5; RAO in v6 */ 795 #define SCTLR_CP15BEN (1U << 5) /* v7 onward */ 796 #define SCTLR_L (1U << 6) /* up to v5; RAO in v6 and v7; RAZ in v8 */ 797 #define SCTLR_B (1U << 7) /* up to v6; RAZ in v7 */ 798 #define SCTLR_ITD (1U << 7) /* v8 onward */ 799 #define SCTLR_S (1U << 8) /* up to v6; RAZ in v7 */ 800 #define SCTLR_SED (1U << 8) /* v8 onward */ 801 #define SCTLR_R (1U << 9) /* up to v6; RAZ in v7 */ 802 #define SCTLR_UMA (1U << 9) /* v8 onward, AArch64 only */ 803 #define SCTLR_F (1U << 10) /* up to v6 */ 804 #define SCTLR_SW (1U << 10) /* v7 onward */ 805 #define SCTLR_Z (1U << 11) 806 #define SCTLR_I (1U << 12) 807 #define SCTLR_V (1U << 13) 808 #define SCTLR_RR (1U << 14) /* up to v7 */ 809 #define SCTLR_DZE (1U << 14) /* v8 onward, AArch64 only */ 810 #define SCTLR_L4 (1U << 15) /* up to v6; RAZ in v7 */ 811 #define SCTLR_UCT (1U << 15) /* v8 onward, AArch64 only */ 812 #define SCTLR_DT (1U << 16) /* up to ??, RAO in v6 and v7 */ 813 #define SCTLR_nTWI (1U << 16) /* v8 onward */ 814 #define SCTLR_HA (1U << 17) 815 #define SCTLR_BR (1U << 17) /* PMSA only */ 816 #define SCTLR_IT (1U << 18) /* up to ??, RAO in v6 and v7 */ 817 #define SCTLR_nTWE (1U << 18) /* v8 onward */ 818 #define SCTLR_WXN (1U << 19) 819 #define SCTLR_ST (1U << 20) /* up to ??, RAZ in v6 */ 820 #define SCTLR_UWXN (1U << 20) /* v7 onward */ 821 #define SCTLR_FI (1U << 21) 822 #define SCTLR_U (1U << 22) 823 #define SCTLR_XP (1U << 23) /* up to v6; v7 onward RAO */ 824 #define SCTLR_VE (1U << 24) /* up to v7 */ 825 #define SCTLR_E0E (1U << 24) /* v8 onward, AArch64 only */ 826 #define SCTLR_EE (1U << 25) 827 #define SCTLR_L2 (1U << 26) /* up to v6, RAZ in v7 */ 828 #define SCTLR_UCI (1U << 26) /* v8 onward, AArch64 only */ 829 #define SCTLR_NMFI (1U << 27) 830 #define SCTLR_TRE (1U << 28) 831 #define SCTLR_AFE (1U << 29) 832 #define SCTLR_TE (1U << 30) 833 834 #define CPTR_TCPAC (1U << 31) 835 #define CPTR_TTA (1U << 20) 836 #define CPTR_TFP (1U << 10) 837 838 #define MDCR_EPMAD (1U << 21) 839 #define MDCR_EDAD (1U << 20) 840 #define MDCR_SPME (1U << 17) 841 #define MDCR_SDD (1U << 16) 842 #define MDCR_SPD (3U << 14) 843 #define MDCR_TDRA (1U << 11) 844 #define MDCR_TDOSA (1U << 10) 845 #define MDCR_TDA (1U << 9) 846 #define MDCR_TDE (1U << 8) 847 #define MDCR_HPME (1U << 7) 848 #define MDCR_TPM (1U << 6) 849 #define MDCR_TPMCR (1U << 5) 850 851 /* Not all of the MDCR_EL3 bits are present in the 32-bit SDCR */ 852 #define SDCR_VALID_MASK (MDCR_EPMAD | MDCR_EDAD | MDCR_SPME | MDCR_SPD) 853 854 #define CPSR_M (0x1fU) 855 #define CPSR_T (1U << 5) 856 #define CPSR_F (1U << 6) 857 #define CPSR_I (1U << 7) 858 #define CPSR_A (1U << 8) 859 #define CPSR_E (1U << 9) 860 #define CPSR_IT_2_7 (0xfc00U) 861 #define CPSR_GE (0xfU << 16) 862 #define CPSR_IL (1U << 20) 863 /* Note that the RESERVED bits include bit 21, which is PSTATE_SS in 864 * an AArch64 SPSR but RES0 in AArch32 SPSR and CPSR. In QEMU we use 865 * env->uncached_cpsr bit 21 to store PSTATE.SS when executing in AArch32, 866 * where it is live state but not accessible to the AArch32 code. 867 */ 868 #define CPSR_RESERVED (0x7U << 21) 869 #define CPSR_J (1U << 24) 870 #define CPSR_IT_0_1 (3U << 25) 871 #define CPSR_Q (1U << 27) 872 #define CPSR_V (1U << 28) 873 #define CPSR_C (1U << 29) 874 #define CPSR_Z (1U << 30) 875 #define CPSR_N (1U << 31) 876 #define CPSR_NZCV (CPSR_N | CPSR_Z | CPSR_C | CPSR_V) 877 #define CPSR_AIF (CPSR_A | CPSR_I | CPSR_F) 878 879 #define CPSR_IT (CPSR_IT_0_1 | CPSR_IT_2_7) 880 #define CACHED_CPSR_BITS (CPSR_T | CPSR_AIF | CPSR_GE | CPSR_IT | CPSR_Q \ 881 | CPSR_NZCV) 882 /* Bits writable in user mode. */ 883 #define CPSR_USER (CPSR_NZCV | CPSR_Q | CPSR_GE) 884 /* Execution state bits. MRS read as zero, MSR writes ignored. */ 885 #define CPSR_EXEC (CPSR_T | CPSR_IT | CPSR_J | CPSR_IL) 886 /* Mask of bits which may be set by exception return copying them from SPSR */ 887 #define CPSR_ERET_MASK (~CPSR_RESERVED) 888 889 /* Bit definitions for M profile XPSR. Most are the same as CPSR. */ 890 #define XPSR_EXCP 0x1ffU 891 #define XPSR_SPREALIGN (1U << 9) /* Only set in exception stack frames */ 892 #define XPSR_IT_2_7 CPSR_IT_2_7 893 #define XPSR_GE CPSR_GE 894 #define XPSR_SFPA (1U << 20) /* Only set in exception stack frames */ 895 #define XPSR_T (1U << 24) /* Not the same as CPSR_T ! */ 896 #define XPSR_IT_0_1 CPSR_IT_0_1 897 #define XPSR_Q CPSR_Q 898 #define XPSR_V CPSR_V 899 #define XPSR_C CPSR_C 900 #define XPSR_Z CPSR_Z 901 #define XPSR_N CPSR_N 902 #define XPSR_NZCV CPSR_NZCV 903 #define XPSR_IT CPSR_IT 904 905 #define TTBCR_N (7U << 0) /* TTBCR.EAE==0 */ 906 #define TTBCR_T0SZ (7U << 0) /* TTBCR.EAE==1 */ 907 #define TTBCR_PD0 (1U << 4) 908 #define TTBCR_PD1 (1U << 5) 909 #define TTBCR_EPD0 (1U << 7) 910 #define TTBCR_IRGN0 (3U << 8) 911 #define TTBCR_ORGN0 (3U << 10) 912 #define TTBCR_SH0 (3U << 12) 913 #define TTBCR_T1SZ (3U << 16) 914 #define TTBCR_A1 (1U << 22) 915 #define TTBCR_EPD1 (1U << 23) 916 #define TTBCR_IRGN1 (3U << 24) 917 #define TTBCR_ORGN1 (3U << 26) 918 #define TTBCR_SH1 (1U << 28) 919 #define TTBCR_EAE (1U << 31) 920 921 /* Bit definitions for ARMv8 SPSR (PSTATE) format. 922 * Only these are valid when in AArch64 mode; in 923 * AArch32 mode SPSRs are basically CPSR-format. 924 */ 925 #define PSTATE_SP (1U) 926 #define PSTATE_M (0xFU) 927 #define PSTATE_nRW (1U << 4) 928 #define PSTATE_F (1U << 6) 929 #define PSTATE_I (1U << 7) 930 #define PSTATE_A (1U << 8) 931 #define PSTATE_D (1U << 9) 932 #define PSTATE_IL (1U << 20) 933 #define PSTATE_SS (1U << 21) 934 #define PSTATE_V (1U << 28) 935 #define PSTATE_C (1U << 29) 936 #define PSTATE_Z (1U << 30) 937 #define PSTATE_N (1U << 31) 938 #define PSTATE_NZCV (PSTATE_N | PSTATE_Z | PSTATE_C | PSTATE_V) 939 #define PSTATE_DAIF (PSTATE_D | PSTATE_A | PSTATE_I | PSTATE_F) 940 #define CACHED_PSTATE_BITS (PSTATE_NZCV | PSTATE_DAIF) 941 /* Mode values for AArch64 */ 942 #define PSTATE_MODE_EL3h 13 943 #define PSTATE_MODE_EL3t 12 944 #define PSTATE_MODE_EL2h 9 945 #define PSTATE_MODE_EL2t 8 946 #define PSTATE_MODE_EL1h 5 947 #define PSTATE_MODE_EL1t 4 948 #define PSTATE_MODE_EL0t 0 949 950 /* Map EL and handler into a PSTATE_MODE. */ 951 static inline unsigned int aarch64_pstate_mode(unsigned int el, bool handler) 952 { 953 return (el << 2) | handler; 954 } 955 956 /* Return the current PSTATE value. For the moment we don't support 32<->64 bit 957 * interprocessing, so we don't attempt to sync with the cpsr state used by 958 * the 32 bit decoder. 959 */ 960 static inline uint32_t pstate_read(CPUARMState *env) 961 { 962 int ZF; 963 964 ZF = (env->ZF == 0); 965 return (env->NF & 0x80000000) | (ZF << 30) 966 | (env->CF << 29) | ((env->VF & 0x80000000) >> 3) 967 | env->pstate | env->daif; 968 } 969 970 static inline void pstate_write(CPUARMState *env, uint32_t val) 971 { 972 env->ZF = (~val) & PSTATE_Z; 973 env->NF = val; 974 env->CF = (val >> 29) & 1; 975 env->VF = (val << 3) & 0x80000000; 976 env->daif = val & PSTATE_DAIF; 977 env->pstate = val & ~CACHED_PSTATE_BITS; 978 } 979 980 /* Return the current CPSR value. */ 981 uint32_t cpsr_read(CPUARMState *env); 982 983 typedef enum CPSRWriteType { 984 CPSRWriteByInstr = 0, /* from guest MSR or CPS */ 985 CPSRWriteExceptionReturn = 1, /* from guest exception return insn */ 986 CPSRWriteRaw = 2, /* trust values, do not switch reg banks */ 987 CPSRWriteByGDBStub = 3, /* from the GDB stub */ 988 } CPSRWriteType; 989 990 /* Set the CPSR. Note that some bits of mask must be all-set or all-clear.*/ 991 void cpsr_write(CPUARMState *env, uint32_t val, uint32_t mask, 992 CPSRWriteType write_type); 993 994 /* Return the current xPSR value. */ 995 static inline uint32_t xpsr_read(CPUARMState *env) 996 { 997 int ZF; 998 ZF = (env->ZF == 0); 999 return (env->NF & 0x80000000) | (ZF << 30) 1000 | (env->CF << 29) | ((env->VF & 0x80000000) >> 3) | (env->QF << 27) 1001 | (env->thumb << 24) | ((env->condexec_bits & 3) << 25) 1002 | ((env->condexec_bits & 0xfc) << 8) 1003 | env->v7m.exception; 1004 } 1005 1006 /* Set the xPSR. Note that some bits of mask must be all-set or all-clear. */ 1007 static inline void xpsr_write(CPUARMState *env, uint32_t val, uint32_t mask) 1008 { 1009 if (mask & XPSR_NZCV) { 1010 env->ZF = (~val) & XPSR_Z; 1011 env->NF = val; 1012 env->CF = (val >> 29) & 1; 1013 env->VF = (val << 3) & 0x80000000; 1014 } 1015 if (mask & XPSR_Q) { 1016 env->QF = ((val & XPSR_Q) != 0); 1017 } 1018 if (mask & XPSR_T) { 1019 env->thumb = ((val & XPSR_T) != 0); 1020 } 1021 if (mask & XPSR_IT_0_1) { 1022 env->condexec_bits &= ~3; 1023 env->condexec_bits |= (val >> 25) & 3; 1024 } 1025 if (mask & XPSR_IT_2_7) { 1026 env->condexec_bits &= 3; 1027 env->condexec_bits |= (val >> 8) & 0xfc; 1028 } 1029 if (mask & XPSR_EXCP) { 1030 env->v7m.exception = val & XPSR_EXCP; 1031 } 1032 } 1033 1034 #define HCR_VM (1ULL << 0) 1035 #define HCR_SWIO (1ULL << 1) 1036 #define HCR_PTW (1ULL << 2) 1037 #define HCR_FMO (1ULL << 3) 1038 #define HCR_IMO (1ULL << 4) 1039 #define HCR_AMO (1ULL << 5) 1040 #define HCR_VF (1ULL << 6) 1041 #define HCR_VI (1ULL << 7) 1042 #define HCR_VSE (1ULL << 8) 1043 #define HCR_FB (1ULL << 9) 1044 #define HCR_BSU_MASK (3ULL << 10) 1045 #define HCR_DC (1ULL << 12) 1046 #define HCR_TWI (1ULL << 13) 1047 #define HCR_TWE (1ULL << 14) 1048 #define HCR_TID0 (1ULL << 15) 1049 #define HCR_TID1 (1ULL << 16) 1050 #define HCR_TID2 (1ULL << 17) 1051 #define HCR_TID3 (1ULL << 18) 1052 #define HCR_TSC (1ULL << 19) 1053 #define HCR_TIDCP (1ULL << 20) 1054 #define HCR_TACR (1ULL << 21) 1055 #define HCR_TSW (1ULL << 22) 1056 #define HCR_TPC (1ULL << 23) 1057 #define HCR_TPU (1ULL << 24) 1058 #define HCR_TTLB (1ULL << 25) 1059 #define HCR_TVM (1ULL << 26) 1060 #define HCR_TGE (1ULL << 27) 1061 #define HCR_TDZ (1ULL << 28) 1062 #define HCR_HCD (1ULL << 29) 1063 #define HCR_TRVM (1ULL << 30) 1064 #define HCR_RW (1ULL << 31) 1065 #define HCR_CD (1ULL << 32) 1066 #define HCR_ID (1ULL << 33) 1067 #define HCR_MASK ((1ULL << 34) - 1) 1068 1069 #define SCR_NS (1U << 0) 1070 #define SCR_IRQ (1U << 1) 1071 #define SCR_FIQ (1U << 2) 1072 #define SCR_EA (1U << 3) 1073 #define SCR_FW (1U << 4) 1074 #define SCR_AW (1U << 5) 1075 #define SCR_NET (1U << 6) 1076 #define SCR_SMD (1U << 7) 1077 #define SCR_HCE (1U << 8) 1078 #define SCR_SIF (1U << 9) 1079 #define SCR_RW (1U << 10) 1080 #define SCR_ST (1U << 11) 1081 #define SCR_TWI (1U << 12) 1082 #define SCR_TWE (1U << 13) 1083 #define SCR_AARCH32_MASK (0x3fff & ~(SCR_RW | SCR_ST)) 1084 #define SCR_AARCH64_MASK (0x3fff & ~SCR_NET) 1085 1086 /* Return the current FPSCR value. */ 1087 uint32_t vfp_get_fpscr(CPUARMState *env); 1088 void vfp_set_fpscr(CPUARMState *env, uint32_t val); 1089 1090 /* For A64 the FPSCR is split into two logically distinct registers, 1091 * FPCR and FPSR. However since they still use non-overlapping bits 1092 * we store the underlying state in fpscr and just mask on read/write. 1093 */ 1094 #define FPSR_MASK 0xf800009f 1095 #define FPCR_MASK 0x07f79f00 1096 static inline uint32_t vfp_get_fpsr(CPUARMState *env) 1097 { 1098 return vfp_get_fpscr(env) & FPSR_MASK; 1099 } 1100 1101 static inline void vfp_set_fpsr(CPUARMState *env, uint32_t val) 1102 { 1103 uint32_t new_fpscr = (vfp_get_fpscr(env) & ~FPSR_MASK) | (val & FPSR_MASK); 1104 vfp_set_fpscr(env, new_fpscr); 1105 } 1106 1107 static inline uint32_t vfp_get_fpcr(CPUARMState *env) 1108 { 1109 return vfp_get_fpscr(env) & FPCR_MASK; 1110 } 1111 1112 static inline void vfp_set_fpcr(CPUARMState *env, uint32_t val) 1113 { 1114 uint32_t new_fpscr = (vfp_get_fpscr(env) & ~FPCR_MASK) | (val & FPCR_MASK); 1115 vfp_set_fpscr(env, new_fpscr); 1116 } 1117 1118 enum arm_cpu_mode { 1119 ARM_CPU_MODE_USR = 0x10, 1120 ARM_CPU_MODE_FIQ = 0x11, 1121 ARM_CPU_MODE_IRQ = 0x12, 1122 ARM_CPU_MODE_SVC = 0x13, 1123 ARM_CPU_MODE_MON = 0x16, 1124 ARM_CPU_MODE_ABT = 0x17, 1125 ARM_CPU_MODE_HYP = 0x1a, 1126 ARM_CPU_MODE_UND = 0x1b, 1127 ARM_CPU_MODE_SYS = 0x1f 1128 }; 1129 1130 /* VFP system registers. */ 1131 #define ARM_VFP_FPSID 0 1132 #define ARM_VFP_FPSCR 1 1133 #define ARM_VFP_MVFR2 5 1134 #define ARM_VFP_MVFR1 6 1135 #define ARM_VFP_MVFR0 7 1136 #define ARM_VFP_FPEXC 8 1137 #define ARM_VFP_FPINST 9 1138 #define ARM_VFP_FPINST2 10 1139 1140 /* iwMMXt coprocessor control registers. */ 1141 #define ARM_IWMMXT_wCID 0 1142 #define ARM_IWMMXT_wCon 1 1143 #define ARM_IWMMXT_wCSSF 2 1144 #define ARM_IWMMXT_wCASF 3 1145 #define ARM_IWMMXT_wCGR0 8 1146 #define ARM_IWMMXT_wCGR1 9 1147 #define ARM_IWMMXT_wCGR2 10 1148 #define ARM_IWMMXT_wCGR3 11 1149 1150 /* V7M CCR bits */ 1151 FIELD(V7M_CCR, NONBASETHRDENA, 0, 1) 1152 FIELD(V7M_CCR, USERSETMPEND, 1, 1) 1153 FIELD(V7M_CCR, UNALIGN_TRP, 3, 1) 1154 FIELD(V7M_CCR, DIV_0_TRP, 4, 1) 1155 FIELD(V7M_CCR, BFHFNMIGN, 8, 1) 1156 FIELD(V7M_CCR, STKALIGN, 9, 1) 1157 FIELD(V7M_CCR, DC, 16, 1) 1158 FIELD(V7M_CCR, IC, 17, 1) 1159 1160 /* V7M CFSR bits for MMFSR */ 1161 FIELD(V7M_CFSR, IACCVIOL, 0, 1) 1162 FIELD(V7M_CFSR, DACCVIOL, 1, 1) 1163 FIELD(V7M_CFSR, MUNSTKERR, 3, 1) 1164 FIELD(V7M_CFSR, MSTKERR, 4, 1) 1165 FIELD(V7M_CFSR, MLSPERR, 5, 1) 1166 FIELD(V7M_CFSR, MMARVALID, 7, 1) 1167 1168 /* V7M CFSR bits for BFSR */ 1169 FIELD(V7M_CFSR, IBUSERR, 8 + 0, 1) 1170 FIELD(V7M_CFSR, PRECISERR, 8 + 1, 1) 1171 FIELD(V7M_CFSR, IMPRECISERR, 8 + 2, 1) 1172 FIELD(V7M_CFSR, UNSTKERR, 8 + 3, 1) 1173 FIELD(V7M_CFSR, STKERR, 8 + 4, 1) 1174 FIELD(V7M_CFSR, LSPERR, 8 + 5, 1) 1175 FIELD(V7M_CFSR, BFARVALID, 8 + 7, 1) 1176 1177 /* V7M CFSR bits for UFSR */ 1178 FIELD(V7M_CFSR, UNDEFINSTR, 16 + 0, 1) 1179 FIELD(V7M_CFSR, INVSTATE, 16 + 1, 1) 1180 FIELD(V7M_CFSR, INVPC, 16 + 2, 1) 1181 FIELD(V7M_CFSR, NOCP, 16 + 3, 1) 1182 FIELD(V7M_CFSR, UNALIGNED, 16 + 8, 1) 1183 FIELD(V7M_CFSR, DIVBYZERO, 16 + 9, 1) 1184 1185 /* V7M HFSR bits */ 1186 FIELD(V7M_HFSR, VECTTBL, 1, 1) 1187 FIELD(V7M_HFSR, FORCED, 30, 1) 1188 FIELD(V7M_HFSR, DEBUGEVT, 31, 1) 1189 1190 /* V7M DFSR bits */ 1191 FIELD(V7M_DFSR, HALTED, 0, 1) 1192 FIELD(V7M_DFSR, BKPT, 1, 1) 1193 FIELD(V7M_DFSR, DWTTRAP, 2, 1) 1194 FIELD(V7M_DFSR, VCATCH, 3, 1) 1195 FIELD(V7M_DFSR, EXTERNAL, 4, 1) 1196 1197 /* v7M MPU_CTRL bits */ 1198 FIELD(V7M_MPU_CTRL, ENABLE, 0, 1) 1199 FIELD(V7M_MPU_CTRL, HFNMIENA, 1, 1) 1200 FIELD(V7M_MPU_CTRL, PRIVDEFENA, 2, 1) 1201 1202 /* If adding a feature bit which corresponds to a Linux ELF 1203 * HWCAP bit, remember to update the feature-bit-to-hwcap 1204 * mapping in linux-user/elfload.c:get_elf_hwcap(). 1205 */ 1206 enum arm_features { 1207 ARM_FEATURE_VFP, 1208 ARM_FEATURE_AUXCR, /* ARM1026 Auxiliary control register. */ 1209 ARM_FEATURE_XSCALE, /* Intel XScale extensions. */ 1210 ARM_FEATURE_IWMMXT, /* Intel iwMMXt extension. */ 1211 ARM_FEATURE_V6, 1212 ARM_FEATURE_V6K, 1213 ARM_FEATURE_V7, 1214 ARM_FEATURE_THUMB2, 1215 ARM_FEATURE_PMSA, /* no MMU; may have Memory Protection Unit */ 1216 ARM_FEATURE_VFP3, 1217 ARM_FEATURE_VFP_FP16, 1218 ARM_FEATURE_NEON, 1219 ARM_FEATURE_THUMB_DIV, /* divide supported in Thumb encoding */ 1220 ARM_FEATURE_M, /* Microcontroller profile. */ 1221 ARM_FEATURE_OMAPCP, /* OMAP specific CP15 ops handling. */ 1222 ARM_FEATURE_THUMB2EE, 1223 ARM_FEATURE_V7MP, /* v7 Multiprocessing Extensions */ 1224 ARM_FEATURE_V4T, 1225 ARM_FEATURE_V5, 1226 ARM_FEATURE_STRONGARM, 1227 ARM_FEATURE_VAPA, /* cp15 VA to PA lookups */ 1228 ARM_FEATURE_ARM_DIV, /* divide supported in ARM encoding */ 1229 ARM_FEATURE_VFP4, /* VFPv4 (implies that NEON is v2) */ 1230 ARM_FEATURE_GENERIC_TIMER, 1231 ARM_FEATURE_MVFR, /* Media and VFP Feature Registers 0 and 1 */ 1232 ARM_FEATURE_DUMMY_C15_REGS, /* RAZ/WI all of cp15 crn=15 */ 1233 ARM_FEATURE_CACHE_TEST_CLEAN, /* 926/1026 style test-and-clean ops */ 1234 ARM_FEATURE_CACHE_DIRTY_REG, /* 1136/1176 cache dirty status register */ 1235 ARM_FEATURE_CACHE_BLOCK_OPS, /* v6 optional cache block operations */ 1236 ARM_FEATURE_MPIDR, /* has cp15 MPIDR */ 1237 ARM_FEATURE_PXN, /* has Privileged Execute Never bit */ 1238 ARM_FEATURE_LPAE, /* has Large Physical Address Extension */ 1239 ARM_FEATURE_V8, 1240 ARM_FEATURE_AARCH64, /* supports 64 bit mode */ 1241 ARM_FEATURE_V8_AES, /* implements AES part of v8 Crypto Extensions */ 1242 ARM_FEATURE_CBAR, /* has cp15 CBAR */ 1243 ARM_FEATURE_CRC, /* ARMv8 CRC instructions */ 1244 ARM_FEATURE_CBAR_RO, /* has cp15 CBAR and it is read-only */ 1245 ARM_FEATURE_EL2, /* has EL2 Virtualization support */ 1246 ARM_FEATURE_EL3, /* has EL3 Secure monitor support */ 1247 ARM_FEATURE_V8_SHA1, /* implements SHA1 part of v8 Crypto Extensions */ 1248 ARM_FEATURE_V8_SHA256, /* implements SHA256 part of v8 Crypto Extensions */ 1249 ARM_FEATURE_V8_PMULL, /* implements PMULL part of v8 Crypto Extensions */ 1250 ARM_FEATURE_THUMB_DSP, /* DSP insns supported in the Thumb encodings */ 1251 ARM_FEATURE_PMU, /* has PMU support */ 1252 ARM_FEATURE_VBAR, /* has cp15 VBAR */ 1253 }; 1254 1255 static inline int arm_feature(CPUARMState *env, int feature) 1256 { 1257 return (env->features & (1ULL << feature)) != 0; 1258 } 1259 1260 #if !defined(CONFIG_USER_ONLY) 1261 /* Return true if exception levels below EL3 are in secure state, 1262 * or would be following an exception return to that level. 1263 * Unlike arm_is_secure() (which is always a question about the 1264 * _current_ state of the CPU) this doesn't care about the current 1265 * EL or mode. 1266 */ 1267 static inline bool arm_is_secure_below_el3(CPUARMState *env) 1268 { 1269 if (arm_feature(env, ARM_FEATURE_EL3)) { 1270 return !(env->cp15.scr_el3 & SCR_NS); 1271 } else { 1272 /* If EL3 is not supported then the secure state is implementation 1273 * defined, in which case QEMU defaults to non-secure. 1274 */ 1275 return false; 1276 } 1277 } 1278 1279 /* Return true if the CPU is AArch64 EL3 or AArch32 Mon */ 1280 static inline bool arm_is_el3_or_mon(CPUARMState *env) 1281 { 1282 if (arm_feature(env, ARM_FEATURE_EL3)) { 1283 if (is_a64(env) && extract32(env->pstate, 2, 2) == 3) { 1284 /* CPU currently in AArch64 state and EL3 */ 1285 return true; 1286 } else if (!is_a64(env) && 1287 (env->uncached_cpsr & CPSR_M) == ARM_CPU_MODE_MON) { 1288 /* CPU currently in AArch32 state and monitor mode */ 1289 return true; 1290 } 1291 } 1292 return false; 1293 } 1294 1295 /* Return true if the processor is in secure state */ 1296 static inline bool arm_is_secure(CPUARMState *env) 1297 { 1298 if (arm_is_el3_or_mon(env)) { 1299 return true; 1300 } 1301 return arm_is_secure_below_el3(env); 1302 } 1303 1304 #else 1305 static inline bool arm_is_secure_below_el3(CPUARMState *env) 1306 { 1307 return false; 1308 } 1309 1310 static inline bool arm_is_secure(CPUARMState *env) 1311 { 1312 return false; 1313 } 1314 #endif 1315 1316 /* Return true if the specified exception level is running in AArch64 state. */ 1317 static inline bool arm_el_is_aa64(CPUARMState *env, int el) 1318 { 1319 /* This isn't valid for EL0 (if we're in EL0, is_a64() is what you want, 1320 * and if we're not in EL0 then the state of EL0 isn't well defined.) 1321 */ 1322 assert(el >= 1 && el <= 3); 1323 bool aa64 = arm_feature(env, ARM_FEATURE_AARCH64); 1324 1325 /* The highest exception level is always at the maximum supported 1326 * register width, and then lower levels have a register width controlled 1327 * by bits in the SCR or HCR registers. 1328 */ 1329 if (el == 3) { 1330 return aa64; 1331 } 1332 1333 if (arm_feature(env, ARM_FEATURE_EL3)) { 1334 aa64 = aa64 && (env->cp15.scr_el3 & SCR_RW); 1335 } 1336 1337 if (el == 2) { 1338 return aa64; 1339 } 1340 1341 if (arm_feature(env, ARM_FEATURE_EL2) && !arm_is_secure_below_el3(env)) { 1342 aa64 = aa64 && (env->cp15.hcr_el2 & HCR_RW); 1343 } 1344 1345 return aa64; 1346 } 1347 1348 /* Function for determing whether guest cp register reads and writes should 1349 * access the secure or non-secure bank of a cp register. When EL3 is 1350 * operating in AArch32 state, the NS-bit determines whether the secure 1351 * instance of a cp register should be used. When EL3 is AArch64 (or if 1352 * it doesn't exist at all) then there is no register banking, and all 1353 * accesses are to the non-secure version. 1354 */ 1355 static inline bool access_secure_reg(CPUARMState *env) 1356 { 1357 bool ret = (arm_feature(env, ARM_FEATURE_EL3) && 1358 !arm_el_is_aa64(env, 3) && 1359 !(env->cp15.scr_el3 & SCR_NS)); 1360 1361 return ret; 1362 } 1363 1364 /* Macros for accessing a specified CP register bank */ 1365 #define A32_BANKED_REG_GET(_env, _regname, _secure) \ 1366 ((_secure) ? (_env)->cp15._regname##_s : (_env)->cp15._regname##_ns) 1367 1368 #define A32_BANKED_REG_SET(_env, _regname, _secure, _val) \ 1369 do { \ 1370 if (_secure) { \ 1371 (_env)->cp15._regname##_s = (_val); \ 1372 } else { \ 1373 (_env)->cp15._regname##_ns = (_val); \ 1374 } \ 1375 } while (0) 1376 1377 /* Macros for automatically accessing a specific CP register bank depending on 1378 * the current secure state of the system. These macros are not intended for 1379 * supporting instruction translation reads/writes as these are dependent 1380 * solely on the SCR.NS bit and not the mode. 1381 */ 1382 #define A32_BANKED_CURRENT_REG_GET(_env, _regname) \ 1383 A32_BANKED_REG_GET((_env), _regname, \ 1384 (arm_is_secure(_env) && !arm_el_is_aa64((_env), 3))) 1385 1386 #define A32_BANKED_CURRENT_REG_SET(_env, _regname, _val) \ 1387 A32_BANKED_REG_SET((_env), _regname, \ 1388 (arm_is_secure(_env) && !arm_el_is_aa64((_env), 3)), \ 1389 (_val)) 1390 1391 void arm_cpu_list(FILE *f, fprintf_function cpu_fprintf); 1392 uint32_t arm_phys_excp_target_el(CPUState *cs, uint32_t excp_idx, 1393 uint32_t cur_el, bool secure); 1394 1395 /* Interface between CPU and Interrupt controller. */ 1396 #ifndef CONFIG_USER_ONLY 1397 bool armv7m_nvic_can_take_pending_exception(void *opaque); 1398 #else 1399 static inline bool armv7m_nvic_can_take_pending_exception(void *opaque) 1400 { 1401 return true; 1402 } 1403 #endif 1404 void armv7m_nvic_set_pending(void *opaque, int irq); 1405 void armv7m_nvic_acknowledge_irq(void *opaque); 1406 /** 1407 * armv7m_nvic_complete_irq: complete specified interrupt or exception 1408 * @opaque: the NVIC 1409 * @irq: the exception number to complete 1410 * 1411 * Returns: -1 if the irq was not active 1412 * 1 if completing this irq brought us back to base (no active irqs) 1413 * 0 if there is still an irq active after this one was completed 1414 * (Ignoring -1, this is the same as the RETTOBASE value before completion.) 1415 */ 1416 int armv7m_nvic_complete_irq(void *opaque, int irq); 1417 1418 /* Interface for defining coprocessor registers. 1419 * Registers are defined in tables of arm_cp_reginfo structs 1420 * which are passed to define_arm_cp_regs(). 1421 */ 1422 1423 /* When looking up a coprocessor register we look for it 1424 * via an integer which encodes all of: 1425 * coprocessor number 1426 * Crn, Crm, opc1, opc2 fields 1427 * 32 or 64 bit register (ie is it accessed via MRC/MCR 1428 * or via MRRC/MCRR?) 1429 * non-secure/secure bank (AArch32 only) 1430 * We allow 4 bits for opc1 because MRRC/MCRR have a 4 bit field. 1431 * (In this case crn and opc2 should be zero.) 1432 * For AArch64, there is no 32/64 bit size distinction; 1433 * instead all registers have a 2 bit op0, 3 bit op1 and op2, 1434 * and 4 bit CRn and CRm. The encoding patterns are chosen 1435 * to be easy to convert to and from the KVM encodings, and also 1436 * so that the hashtable can contain both AArch32 and AArch64 1437 * registers (to allow for interprocessing where we might run 1438 * 32 bit code on a 64 bit core). 1439 */ 1440 /* This bit is private to our hashtable cpreg; in KVM register 1441 * IDs the AArch64/32 distinction is the KVM_REG_ARM/ARM64 1442 * in the upper bits of the 64 bit ID. 1443 */ 1444 #define CP_REG_AA64_SHIFT 28 1445 #define CP_REG_AA64_MASK (1 << CP_REG_AA64_SHIFT) 1446 1447 /* To enable banking of coprocessor registers depending on ns-bit we 1448 * add a bit to distinguish between secure and non-secure cpregs in the 1449 * hashtable. 1450 */ 1451 #define CP_REG_NS_SHIFT 29 1452 #define CP_REG_NS_MASK (1 << CP_REG_NS_SHIFT) 1453 1454 #define ENCODE_CP_REG(cp, is64, ns, crn, crm, opc1, opc2) \ 1455 ((ns) << CP_REG_NS_SHIFT | ((cp) << 16) | ((is64) << 15) | \ 1456 ((crn) << 11) | ((crm) << 7) | ((opc1) << 3) | (opc2)) 1457 1458 #define ENCODE_AA64_CP_REG(cp, crn, crm, op0, op1, op2) \ 1459 (CP_REG_AA64_MASK | \ 1460 ((cp) << CP_REG_ARM_COPROC_SHIFT) | \ 1461 ((op0) << CP_REG_ARM64_SYSREG_OP0_SHIFT) | \ 1462 ((op1) << CP_REG_ARM64_SYSREG_OP1_SHIFT) | \ 1463 ((crn) << CP_REG_ARM64_SYSREG_CRN_SHIFT) | \ 1464 ((crm) << CP_REG_ARM64_SYSREG_CRM_SHIFT) | \ 1465 ((op2) << CP_REG_ARM64_SYSREG_OP2_SHIFT)) 1466 1467 /* Convert a full 64 bit KVM register ID to the truncated 32 bit 1468 * version used as a key for the coprocessor register hashtable 1469 */ 1470 static inline uint32_t kvm_to_cpreg_id(uint64_t kvmid) 1471 { 1472 uint32_t cpregid = kvmid; 1473 if ((kvmid & CP_REG_ARCH_MASK) == CP_REG_ARM64) { 1474 cpregid |= CP_REG_AA64_MASK; 1475 } else { 1476 if ((kvmid & CP_REG_SIZE_MASK) == CP_REG_SIZE_U64) { 1477 cpregid |= (1 << 15); 1478 } 1479 1480 /* KVM is always non-secure so add the NS flag on AArch32 register 1481 * entries. 1482 */ 1483 cpregid |= 1 << CP_REG_NS_SHIFT; 1484 } 1485 return cpregid; 1486 } 1487 1488 /* Convert a truncated 32 bit hashtable key into the full 1489 * 64 bit KVM register ID. 1490 */ 1491 static inline uint64_t cpreg_to_kvm_id(uint32_t cpregid) 1492 { 1493 uint64_t kvmid; 1494 1495 if (cpregid & CP_REG_AA64_MASK) { 1496 kvmid = cpregid & ~CP_REG_AA64_MASK; 1497 kvmid |= CP_REG_SIZE_U64 | CP_REG_ARM64; 1498 } else { 1499 kvmid = cpregid & ~(1 << 15); 1500 if (cpregid & (1 << 15)) { 1501 kvmid |= CP_REG_SIZE_U64 | CP_REG_ARM; 1502 } else { 1503 kvmid |= CP_REG_SIZE_U32 | CP_REG_ARM; 1504 } 1505 } 1506 return kvmid; 1507 } 1508 1509 /* ARMCPRegInfo type field bits. If the SPECIAL bit is set this is a 1510 * special-behaviour cp reg and bits [15..8] indicate what behaviour 1511 * it has. Otherwise it is a simple cp reg, where CONST indicates that 1512 * TCG can assume the value to be constant (ie load at translate time) 1513 * and 64BIT indicates a 64 bit wide coprocessor register. SUPPRESS_TB_END 1514 * indicates that the TB should not be ended after a write to this register 1515 * (the default is that the TB ends after cp writes). OVERRIDE permits 1516 * a register definition to override a previous definition for the 1517 * same (cp, is64, crn, crm, opc1, opc2) tuple: either the new or the 1518 * old must have the OVERRIDE bit set. 1519 * ALIAS indicates that this register is an alias view of some underlying 1520 * state which is also visible via another register, and that the other 1521 * register is handling migration and reset; registers marked ALIAS will not be 1522 * migrated but may have their state set by syncing of register state from KVM. 1523 * NO_RAW indicates that this register has no underlying state and does not 1524 * support raw access for state saving/loading; it will not be used for either 1525 * migration or KVM state synchronization. (Typically this is for "registers" 1526 * which are actually used as instructions for cache maintenance and so on.) 1527 * IO indicates that this register does I/O and therefore its accesses 1528 * need to be surrounded by gen_io_start()/gen_io_end(). In particular, 1529 * registers which implement clocks or timers require this. 1530 */ 1531 #define ARM_CP_SPECIAL 1 1532 #define ARM_CP_CONST 2 1533 #define ARM_CP_64BIT 4 1534 #define ARM_CP_SUPPRESS_TB_END 8 1535 #define ARM_CP_OVERRIDE 16 1536 #define ARM_CP_ALIAS 32 1537 #define ARM_CP_IO 64 1538 #define ARM_CP_NO_RAW 128 1539 #define ARM_CP_NOP (ARM_CP_SPECIAL | (1 << 8)) 1540 #define ARM_CP_WFI (ARM_CP_SPECIAL | (2 << 8)) 1541 #define ARM_CP_NZCV (ARM_CP_SPECIAL | (3 << 8)) 1542 #define ARM_CP_CURRENTEL (ARM_CP_SPECIAL | (4 << 8)) 1543 #define ARM_CP_DC_ZVA (ARM_CP_SPECIAL | (5 << 8)) 1544 #define ARM_LAST_SPECIAL ARM_CP_DC_ZVA 1545 /* Used only as a terminator for ARMCPRegInfo lists */ 1546 #define ARM_CP_SENTINEL 0xffff 1547 /* Mask of only the flag bits in a type field */ 1548 #define ARM_CP_FLAG_MASK 0xff 1549 1550 /* Valid values for ARMCPRegInfo state field, indicating which of 1551 * the AArch32 and AArch64 execution states this register is visible in. 1552 * If the reginfo doesn't explicitly specify then it is AArch32 only. 1553 * If the reginfo is declared to be visible in both states then a second 1554 * reginfo is synthesised for the AArch32 view of the AArch64 register, 1555 * such that the AArch32 view is the lower 32 bits of the AArch64 one. 1556 * Note that we rely on the values of these enums as we iterate through 1557 * the various states in some places. 1558 */ 1559 enum { 1560 ARM_CP_STATE_AA32 = 0, 1561 ARM_CP_STATE_AA64 = 1, 1562 ARM_CP_STATE_BOTH = 2, 1563 }; 1564 1565 /* ARM CP register secure state flags. These flags identify security state 1566 * attributes for a given CP register entry. 1567 * The existence of both or neither secure and non-secure flags indicates that 1568 * the register has both a secure and non-secure hash entry. A single one of 1569 * these flags causes the register to only be hashed for the specified 1570 * security state. 1571 * Although definitions may have any combination of the S/NS bits, each 1572 * registered entry will only have one to identify whether the entry is secure 1573 * or non-secure. 1574 */ 1575 enum { 1576 ARM_CP_SECSTATE_S = (1 << 0), /* bit[0]: Secure state register */ 1577 ARM_CP_SECSTATE_NS = (1 << 1), /* bit[1]: Non-secure state register */ 1578 }; 1579 1580 /* Return true if cptype is a valid type field. This is used to try to 1581 * catch errors where the sentinel has been accidentally left off the end 1582 * of a list of registers. 1583 */ 1584 static inline bool cptype_valid(int cptype) 1585 { 1586 return ((cptype & ~ARM_CP_FLAG_MASK) == 0) 1587 || ((cptype & ARM_CP_SPECIAL) && 1588 ((cptype & ~ARM_CP_FLAG_MASK) <= ARM_LAST_SPECIAL)); 1589 } 1590 1591 /* Access rights: 1592 * We define bits for Read and Write access for what rev C of the v7-AR ARM ARM 1593 * defines as PL0 (user), PL1 (fiq/irq/svc/abt/und/sys, ie privileged), and 1594 * PL2 (hyp). The other level which has Read and Write bits is Secure PL1 1595 * (ie any of the privileged modes in Secure state, or Monitor mode). 1596 * If a register is accessible in one privilege level it's always accessible 1597 * in higher privilege levels too. Since "Secure PL1" also follows this rule 1598 * (ie anything visible in PL2 is visible in S-PL1, some things are only 1599 * visible in S-PL1) but "Secure PL1" is a bit of a mouthful, we bend the 1600 * terminology a little and call this PL3. 1601 * In AArch64 things are somewhat simpler as the PLx bits line up exactly 1602 * with the ELx exception levels. 1603 * 1604 * If access permissions for a register are more complex than can be 1605 * described with these bits, then use a laxer set of restrictions, and 1606 * do the more restrictive/complex check inside a helper function. 1607 */ 1608 #define PL3_R 0x80 1609 #define PL3_W 0x40 1610 #define PL2_R (0x20 | PL3_R) 1611 #define PL2_W (0x10 | PL3_W) 1612 #define PL1_R (0x08 | PL2_R) 1613 #define PL1_W (0x04 | PL2_W) 1614 #define PL0_R (0x02 | PL1_R) 1615 #define PL0_W (0x01 | PL1_W) 1616 1617 #define PL3_RW (PL3_R | PL3_W) 1618 #define PL2_RW (PL2_R | PL2_W) 1619 #define PL1_RW (PL1_R | PL1_W) 1620 #define PL0_RW (PL0_R | PL0_W) 1621 1622 /* Return the highest implemented Exception Level */ 1623 static inline int arm_highest_el(CPUARMState *env) 1624 { 1625 if (arm_feature(env, ARM_FEATURE_EL3)) { 1626 return 3; 1627 } 1628 if (arm_feature(env, ARM_FEATURE_EL2)) { 1629 return 2; 1630 } 1631 return 1; 1632 } 1633 1634 /* Return true if a v7M CPU is in Handler mode */ 1635 static inline bool arm_v7m_is_handler_mode(CPUARMState *env) 1636 { 1637 return env->v7m.exception != 0; 1638 } 1639 1640 /* Return the current Exception Level (as per ARMv8; note that this differs 1641 * from the ARMv7 Privilege Level). 1642 */ 1643 static inline int arm_current_el(CPUARMState *env) 1644 { 1645 if (arm_feature(env, ARM_FEATURE_M)) { 1646 return arm_v7m_is_handler_mode(env) || !(env->v7m.control & 1); 1647 } 1648 1649 if (is_a64(env)) { 1650 return extract32(env->pstate, 2, 2); 1651 } 1652 1653 switch (env->uncached_cpsr & 0x1f) { 1654 case ARM_CPU_MODE_USR: 1655 return 0; 1656 case ARM_CPU_MODE_HYP: 1657 return 2; 1658 case ARM_CPU_MODE_MON: 1659 return 3; 1660 default: 1661 if (arm_is_secure(env) && !arm_el_is_aa64(env, 3)) { 1662 /* If EL3 is 32-bit then all secure privileged modes run in 1663 * EL3 1664 */ 1665 return 3; 1666 } 1667 1668 return 1; 1669 } 1670 } 1671 1672 typedef struct ARMCPRegInfo ARMCPRegInfo; 1673 1674 typedef enum CPAccessResult { 1675 /* Access is permitted */ 1676 CP_ACCESS_OK = 0, 1677 /* Access fails due to a configurable trap or enable which would 1678 * result in a categorized exception syndrome giving information about 1679 * the failing instruction (ie syndrome category 0x3, 0x4, 0x5, 0x6, 1680 * 0xc or 0x18). The exception is taken to the usual target EL (EL1 or 1681 * PL1 if in EL0, otherwise to the current EL). 1682 */ 1683 CP_ACCESS_TRAP = 1, 1684 /* Access fails and results in an exception syndrome 0x0 ("uncategorized"). 1685 * Note that this is not a catch-all case -- the set of cases which may 1686 * result in this failure is specifically defined by the architecture. 1687 */ 1688 CP_ACCESS_TRAP_UNCATEGORIZED = 2, 1689 /* As CP_ACCESS_TRAP, but for traps directly to EL2 or EL3 */ 1690 CP_ACCESS_TRAP_EL2 = 3, 1691 CP_ACCESS_TRAP_EL3 = 4, 1692 /* As CP_ACCESS_UNCATEGORIZED, but for traps directly to EL2 or EL3 */ 1693 CP_ACCESS_TRAP_UNCATEGORIZED_EL2 = 5, 1694 CP_ACCESS_TRAP_UNCATEGORIZED_EL3 = 6, 1695 /* Access fails and results in an exception syndrome for an FP access, 1696 * trapped directly to EL2 or EL3 1697 */ 1698 CP_ACCESS_TRAP_FP_EL2 = 7, 1699 CP_ACCESS_TRAP_FP_EL3 = 8, 1700 } CPAccessResult; 1701 1702 /* Access functions for coprocessor registers. These cannot fail and 1703 * may not raise exceptions. 1704 */ 1705 typedef uint64_t CPReadFn(CPUARMState *env, const ARMCPRegInfo *opaque); 1706 typedef void CPWriteFn(CPUARMState *env, const ARMCPRegInfo *opaque, 1707 uint64_t value); 1708 /* Access permission check functions for coprocessor registers. */ 1709 typedef CPAccessResult CPAccessFn(CPUARMState *env, 1710 const ARMCPRegInfo *opaque, 1711 bool isread); 1712 /* Hook function for register reset */ 1713 typedef void CPResetFn(CPUARMState *env, const ARMCPRegInfo *opaque); 1714 1715 #define CP_ANY 0xff 1716 1717 /* Definition of an ARM coprocessor register */ 1718 struct ARMCPRegInfo { 1719 /* Name of register (useful mainly for debugging, need not be unique) */ 1720 const char *name; 1721 /* Location of register: coprocessor number and (crn,crm,opc1,opc2) 1722 * tuple. Any of crm, opc1 and opc2 may be CP_ANY to indicate a 1723 * 'wildcard' field -- any value of that field in the MRC/MCR insn 1724 * will be decoded to this register. The register read and write 1725 * callbacks will be passed an ARMCPRegInfo with the crn/crm/opc1/opc2 1726 * used by the program, so it is possible to register a wildcard and 1727 * then behave differently on read/write if necessary. 1728 * For 64 bit registers, only crm and opc1 are relevant; crn and opc2 1729 * must both be zero. 1730 * For AArch64-visible registers, opc0 is also used. 1731 * Since there are no "coprocessors" in AArch64, cp is purely used as a 1732 * way to distinguish (for KVM's benefit) guest-visible system registers 1733 * from demuxed ones provided to preserve the "no side effects on 1734 * KVM register read/write from QEMU" semantics. cp==0x13 is guest 1735 * visible (to match KVM's encoding); cp==0 will be converted to 1736 * cp==0x13 when the ARMCPRegInfo is registered, for convenience. 1737 */ 1738 uint8_t cp; 1739 uint8_t crn; 1740 uint8_t crm; 1741 uint8_t opc0; 1742 uint8_t opc1; 1743 uint8_t opc2; 1744 /* Execution state in which this register is visible: ARM_CP_STATE_* */ 1745 int state; 1746 /* Register type: ARM_CP_* bits/values */ 1747 int type; 1748 /* Access rights: PL*_[RW] */ 1749 int access; 1750 /* Security state: ARM_CP_SECSTATE_* bits/values */ 1751 int secure; 1752 /* The opaque pointer passed to define_arm_cp_regs_with_opaque() when 1753 * this register was defined: can be used to hand data through to the 1754 * register read/write functions, since they are passed the ARMCPRegInfo*. 1755 */ 1756 void *opaque; 1757 /* Value of this register, if it is ARM_CP_CONST. Otherwise, if 1758 * fieldoffset is non-zero, the reset value of the register. 1759 */ 1760 uint64_t resetvalue; 1761 /* Offset of the field in CPUARMState for this register. 1762 * 1763 * This is not needed if either: 1764 * 1. type is ARM_CP_CONST or one of the ARM_CP_SPECIALs 1765 * 2. both readfn and writefn are specified 1766 */ 1767 ptrdiff_t fieldoffset; /* offsetof(CPUARMState, field) */ 1768 1769 /* Offsets of the secure and non-secure fields in CPUARMState for the 1770 * register if it is banked. These fields are only used during the static 1771 * registration of a register. During hashing the bank associated 1772 * with a given security state is copied to fieldoffset which is used from 1773 * there on out. 1774 * 1775 * It is expected that register definitions use either fieldoffset or 1776 * bank_fieldoffsets in the definition but not both. It is also expected 1777 * that both bank offsets are set when defining a banked register. This 1778 * use indicates that a register is banked. 1779 */ 1780 ptrdiff_t bank_fieldoffsets[2]; 1781 1782 /* Function for making any access checks for this register in addition to 1783 * those specified by the 'access' permissions bits. If NULL, no extra 1784 * checks required. The access check is performed at runtime, not at 1785 * translate time. 1786 */ 1787 CPAccessFn *accessfn; 1788 /* Function for handling reads of this register. If NULL, then reads 1789 * will be done by loading from the offset into CPUARMState specified 1790 * by fieldoffset. 1791 */ 1792 CPReadFn *readfn; 1793 /* Function for handling writes of this register. If NULL, then writes 1794 * will be done by writing to the offset into CPUARMState specified 1795 * by fieldoffset. 1796 */ 1797 CPWriteFn *writefn; 1798 /* Function for doing a "raw" read; used when we need to copy 1799 * coprocessor state to the kernel for KVM or out for 1800 * migration. This only needs to be provided if there is also a 1801 * readfn and it has side effects (for instance clear-on-read bits). 1802 */ 1803 CPReadFn *raw_readfn; 1804 /* Function for doing a "raw" write; used when we need to copy KVM 1805 * kernel coprocessor state into userspace, or for inbound 1806 * migration. This only needs to be provided if there is also a 1807 * writefn and it masks out "unwritable" bits or has write-one-to-clear 1808 * or similar behaviour. 1809 */ 1810 CPWriteFn *raw_writefn; 1811 /* Function for resetting the register. If NULL, then reset will be done 1812 * by writing resetvalue to the field specified in fieldoffset. If 1813 * fieldoffset is 0 then no reset will be done. 1814 */ 1815 CPResetFn *resetfn; 1816 }; 1817 1818 /* Macros which are lvalues for the field in CPUARMState for the 1819 * ARMCPRegInfo *ri. 1820 */ 1821 #define CPREG_FIELD32(env, ri) \ 1822 (*(uint32_t *)((char *)(env) + (ri)->fieldoffset)) 1823 #define CPREG_FIELD64(env, ri) \ 1824 (*(uint64_t *)((char *)(env) + (ri)->fieldoffset)) 1825 1826 #define REGINFO_SENTINEL { .type = ARM_CP_SENTINEL } 1827 1828 void define_arm_cp_regs_with_opaque(ARMCPU *cpu, 1829 const ARMCPRegInfo *regs, void *opaque); 1830 void define_one_arm_cp_reg_with_opaque(ARMCPU *cpu, 1831 const ARMCPRegInfo *regs, void *opaque); 1832 static inline void define_arm_cp_regs(ARMCPU *cpu, const ARMCPRegInfo *regs) 1833 { 1834 define_arm_cp_regs_with_opaque(cpu, regs, 0); 1835 } 1836 static inline void define_one_arm_cp_reg(ARMCPU *cpu, const ARMCPRegInfo *regs) 1837 { 1838 define_one_arm_cp_reg_with_opaque(cpu, regs, 0); 1839 } 1840 const ARMCPRegInfo *get_arm_cp_reginfo(GHashTable *cpregs, uint32_t encoded_cp); 1841 1842 /* CPWriteFn that can be used to implement writes-ignored behaviour */ 1843 void arm_cp_write_ignore(CPUARMState *env, const ARMCPRegInfo *ri, 1844 uint64_t value); 1845 /* CPReadFn that can be used for read-as-zero behaviour */ 1846 uint64_t arm_cp_read_zero(CPUARMState *env, const ARMCPRegInfo *ri); 1847 1848 /* CPResetFn that does nothing, for use if no reset is required even 1849 * if fieldoffset is non zero. 1850 */ 1851 void arm_cp_reset_ignore(CPUARMState *env, const ARMCPRegInfo *opaque); 1852 1853 /* Return true if this reginfo struct's field in the cpu state struct 1854 * is 64 bits wide. 1855 */ 1856 static inline bool cpreg_field_is_64bit(const ARMCPRegInfo *ri) 1857 { 1858 return (ri->state == ARM_CP_STATE_AA64) || (ri->type & ARM_CP_64BIT); 1859 } 1860 1861 static inline bool cp_access_ok(int current_el, 1862 const ARMCPRegInfo *ri, int isread) 1863 { 1864 return (ri->access >> ((current_el * 2) + isread)) & 1; 1865 } 1866 1867 /* Raw read of a coprocessor register (as needed for migration, etc) */ 1868 uint64_t read_raw_cp_reg(CPUARMState *env, const ARMCPRegInfo *ri); 1869 1870 /** 1871 * write_list_to_cpustate 1872 * @cpu: ARMCPU 1873 * 1874 * For each register listed in the ARMCPU cpreg_indexes list, write 1875 * its value from the cpreg_values list into the ARMCPUState structure. 1876 * This updates TCG's working data structures from KVM data or 1877 * from incoming migration state. 1878 * 1879 * Returns: true if all register values were updated correctly, 1880 * false if some register was unknown or could not be written. 1881 * Note that we do not stop early on failure -- we will attempt 1882 * writing all registers in the list. 1883 */ 1884 bool write_list_to_cpustate(ARMCPU *cpu); 1885 1886 /** 1887 * write_cpustate_to_list: 1888 * @cpu: ARMCPU 1889 * 1890 * For each register listed in the ARMCPU cpreg_indexes list, write 1891 * its value from the ARMCPUState structure into the cpreg_values list. 1892 * This is used to copy info from TCG's working data structures into 1893 * KVM or for outbound migration. 1894 * 1895 * Returns: true if all register values were read correctly, 1896 * false if some register was unknown or could not be read. 1897 * Note that we do not stop early on failure -- we will attempt 1898 * reading all registers in the list. 1899 */ 1900 bool write_cpustate_to_list(ARMCPU *cpu); 1901 1902 #define ARM_CPUID_TI915T 0x54029152 1903 #define ARM_CPUID_TI925T 0x54029252 1904 1905 #if defined(CONFIG_USER_ONLY) 1906 #define TARGET_PAGE_BITS 12 1907 #else 1908 /* ARMv7 and later CPUs have 4K pages minimum, but ARMv5 and v6 1909 * have to support 1K tiny pages. 1910 */ 1911 #define TARGET_PAGE_BITS_VARY 1912 #define TARGET_PAGE_BITS_MIN 10 1913 #endif 1914 1915 #if defined(TARGET_AARCH64) 1916 # define TARGET_PHYS_ADDR_SPACE_BITS 48 1917 # define TARGET_VIRT_ADDR_SPACE_BITS 64 1918 #else 1919 # define TARGET_PHYS_ADDR_SPACE_BITS 40 1920 # define TARGET_VIRT_ADDR_SPACE_BITS 32 1921 #endif 1922 1923 static inline bool arm_excp_unmasked(CPUState *cs, unsigned int excp_idx, 1924 unsigned int target_el) 1925 { 1926 CPUARMState *env = cs->env_ptr; 1927 unsigned int cur_el = arm_current_el(env); 1928 bool secure = arm_is_secure(env); 1929 bool pstate_unmasked; 1930 int8_t unmasked = 0; 1931 1932 /* Don't take exceptions if they target a lower EL. 1933 * This check should catch any exceptions that would not be taken but left 1934 * pending. 1935 */ 1936 if (cur_el > target_el) { 1937 return false; 1938 } 1939 1940 switch (excp_idx) { 1941 case EXCP_FIQ: 1942 pstate_unmasked = !(env->daif & PSTATE_F); 1943 break; 1944 1945 case EXCP_IRQ: 1946 pstate_unmasked = !(env->daif & PSTATE_I); 1947 break; 1948 1949 case EXCP_VFIQ: 1950 if (secure || !(env->cp15.hcr_el2 & HCR_FMO)) { 1951 /* VFIQs are only taken when hypervized and non-secure. */ 1952 return false; 1953 } 1954 return !(env->daif & PSTATE_F); 1955 case EXCP_VIRQ: 1956 if (secure || !(env->cp15.hcr_el2 & HCR_IMO)) { 1957 /* VIRQs are only taken when hypervized and non-secure. */ 1958 return false; 1959 } 1960 return !(env->daif & PSTATE_I); 1961 default: 1962 g_assert_not_reached(); 1963 } 1964 1965 /* Use the target EL, current execution state and SCR/HCR settings to 1966 * determine whether the corresponding CPSR bit is used to mask the 1967 * interrupt. 1968 */ 1969 if ((target_el > cur_el) && (target_el != 1)) { 1970 /* Exceptions targeting a higher EL may not be maskable */ 1971 if (arm_feature(env, ARM_FEATURE_AARCH64)) { 1972 /* 64-bit masking rules are simple: exceptions to EL3 1973 * can't be masked, and exceptions to EL2 can only be 1974 * masked from Secure state. The HCR and SCR settings 1975 * don't affect the masking logic, only the interrupt routing. 1976 */ 1977 if (target_el == 3 || !secure) { 1978 unmasked = 1; 1979 } 1980 } else { 1981 /* The old 32-bit-only environment has a more complicated 1982 * masking setup. HCR and SCR bits not only affect interrupt 1983 * routing but also change the behaviour of masking. 1984 */ 1985 bool hcr, scr; 1986 1987 switch (excp_idx) { 1988 case EXCP_FIQ: 1989 /* If FIQs are routed to EL3 or EL2 then there are cases where 1990 * we override the CPSR.F in determining if the exception is 1991 * masked or not. If neither of these are set then we fall back 1992 * to the CPSR.F setting otherwise we further assess the state 1993 * below. 1994 */ 1995 hcr = (env->cp15.hcr_el2 & HCR_FMO); 1996 scr = (env->cp15.scr_el3 & SCR_FIQ); 1997 1998 /* When EL3 is 32-bit, the SCR.FW bit controls whether the 1999 * CPSR.F bit masks FIQ interrupts when taken in non-secure 2000 * state. If SCR.FW is set then FIQs can be masked by CPSR.F 2001 * when non-secure but only when FIQs are only routed to EL3. 2002 */ 2003 scr = scr && !((env->cp15.scr_el3 & SCR_FW) && !hcr); 2004 break; 2005 case EXCP_IRQ: 2006 /* When EL3 execution state is 32-bit, if HCR.IMO is set then 2007 * we may override the CPSR.I masking when in non-secure state. 2008 * The SCR.IRQ setting has already been taken into consideration 2009 * when setting the target EL, so it does not have a further 2010 * affect here. 2011 */ 2012 hcr = (env->cp15.hcr_el2 & HCR_IMO); 2013 scr = false; 2014 break; 2015 default: 2016 g_assert_not_reached(); 2017 } 2018 2019 if ((scr || hcr) && !secure) { 2020 unmasked = 1; 2021 } 2022 } 2023 } 2024 2025 /* The PSTATE bits only mask the interrupt if we have not overriden the 2026 * ability above. 2027 */ 2028 return unmasked || pstate_unmasked; 2029 } 2030 2031 #define cpu_init(cpu_model) cpu_generic_init(TYPE_ARM_CPU, cpu_model) 2032 2033 #define cpu_signal_handler cpu_arm_signal_handler 2034 #define cpu_list arm_cpu_list 2035 2036 /* ARM has the following "translation regimes" (as the ARM ARM calls them): 2037 * 2038 * If EL3 is 64-bit: 2039 * + NonSecure EL1 & 0 stage 1 2040 * + NonSecure EL1 & 0 stage 2 2041 * + NonSecure EL2 2042 * + Secure EL1 & EL0 2043 * + Secure EL3 2044 * If EL3 is 32-bit: 2045 * + NonSecure PL1 & 0 stage 1 2046 * + NonSecure PL1 & 0 stage 2 2047 * + NonSecure PL2 2048 * + Secure PL0 & PL1 2049 * (reminder: for 32 bit EL3, Secure PL1 is *EL3*, not EL1.) 2050 * 2051 * For QEMU, an mmu_idx is not quite the same as a translation regime because: 2052 * 1. we need to split the "EL1 & 0" regimes into two mmu_idxes, because they 2053 * may differ in access permissions even if the VA->PA map is the same 2054 * 2. we want to cache in our TLB the full VA->IPA->PA lookup for a stage 1+2 2055 * translation, which means that we have one mmu_idx that deals with two 2056 * concatenated translation regimes [this sort of combined s1+2 TLB is 2057 * architecturally permitted] 2058 * 3. we don't need to allocate an mmu_idx to translations that we won't be 2059 * handling via the TLB. The only way to do a stage 1 translation without 2060 * the immediate stage 2 translation is via the ATS or AT system insns, 2061 * which can be slow-pathed and always do a page table walk. 2062 * 4. we can also safely fold together the "32 bit EL3" and "64 bit EL3" 2063 * translation regimes, because they map reasonably well to each other 2064 * and they can't both be active at the same time. 2065 * This gives us the following list of mmu_idx values: 2066 * 2067 * NS EL0 (aka NS PL0) stage 1+2 2068 * NS EL1 (aka NS PL1) stage 1+2 2069 * NS EL2 (aka NS PL2) 2070 * S EL3 (aka S PL1) 2071 * S EL0 (aka S PL0) 2072 * S EL1 (not used if EL3 is 32 bit) 2073 * NS EL0+1 stage 2 2074 * 2075 * (The last of these is an mmu_idx because we want to be able to use the TLB 2076 * for the accesses done as part of a stage 1 page table walk, rather than 2077 * having to walk the stage 2 page table over and over.) 2078 * 2079 * R profile CPUs have an MPU, but can use the same set of MMU indexes 2080 * as A profile. They only need to distinguish NS EL0 and NS EL1 (and 2081 * NS EL2 if we ever model a Cortex-R52). 2082 * 2083 * M profile CPUs are rather different as they do not have a true MMU. 2084 * They have the following different MMU indexes: 2085 * User 2086 * Privileged 2087 * Execution priority negative (this is like privileged, but the 2088 * MPU HFNMIENA bit means that it may have different access permission 2089 * check results to normal privileged code, so can't share a TLB). 2090 * 2091 * The ARMMMUIdx and the mmu index value used by the core QEMU TLB code 2092 * are not quite the same -- different CPU types (most notably M profile 2093 * vs A/R profile) would like to use MMU indexes with different semantics, 2094 * but since we don't ever need to use all of those in a single CPU we 2095 * can avoid setting NB_MMU_MODES to more than 8. The lower bits of 2096 * ARMMMUIdx are the core TLB mmu index, and the higher bits are always 2097 * the same for any particular CPU. 2098 * Variables of type ARMMUIdx are always full values, and the core 2099 * index values are in variables of type 'int'. 2100 * 2101 * Our enumeration includes at the end some entries which are not "true" 2102 * mmu_idx values in that they don't have corresponding TLBs and are only 2103 * valid for doing slow path page table walks. 2104 * 2105 * The constant names here are patterned after the general style of the names 2106 * of the AT/ATS operations. 2107 * The values used are carefully arranged to make mmu_idx => EL lookup easy. 2108 */ 2109 #define ARM_MMU_IDX_A 0x10 /* A profile */ 2110 #define ARM_MMU_IDX_NOTLB 0x20 /* does not have a TLB */ 2111 #define ARM_MMU_IDX_M 0x40 /* M profile */ 2112 2113 #define ARM_MMU_IDX_TYPE_MASK (~0x7) 2114 #define ARM_MMU_IDX_COREIDX_MASK 0x7 2115 2116 typedef enum ARMMMUIdx { 2117 ARMMMUIdx_S12NSE0 = 0 | ARM_MMU_IDX_A, 2118 ARMMMUIdx_S12NSE1 = 1 | ARM_MMU_IDX_A, 2119 ARMMMUIdx_S1E2 = 2 | ARM_MMU_IDX_A, 2120 ARMMMUIdx_S1E3 = 3 | ARM_MMU_IDX_A, 2121 ARMMMUIdx_S1SE0 = 4 | ARM_MMU_IDX_A, 2122 ARMMMUIdx_S1SE1 = 5 | ARM_MMU_IDX_A, 2123 ARMMMUIdx_S2NS = 6 | ARM_MMU_IDX_A, 2124 ARMMMUIdx_MUser = 0 | ARM_MMU_IDX_M, 2125 ARMMMUIdx_MPriv = 1 | ARM_MMU_IDX_M, 2126 ARMMMUIdx_MNegPri = 2 | ARM_MMU_IDX_M, 2127 /* Indexes below here don't have TLBs and are used only for AT system 2128 * instructions or for the first stage of an S12 page table walk. 2129 */ 2130 ARMMMUIdx_S1NSE0 = 0 | ARM_MMU_IDX_NOTLB, 2131 ARMMMUIdx_S1NSE1 = 1 | ARM_MMU_IDX_NOTLB, 2132 } ARMMMUIdx; 2133 2134 /* Bit macros for the core-mmu-index values for each index, 2135 * for use when calling tlb_flush_by_mmuidx() and friends. 2136 */ 2137 typedef enum ARMMMUIdxBit { 2138 ARMMMUIdxBit_S12NSE0 = 1 << 0, 2139 ARMMMUIdxBit_S12NSE1 = 1 << 1, 2140 ARMMMUIdxBit_S1E2 = 1 << 2, 2141 ARMMMUIdxBit_S1E3 = 1 << 3, 2142 ARMMMUIdxBit_S1SE0 = 1 << 4, 2143 ARMMMUIdxBit_S1SE1 = 1 << 5, 2144 ARMMMUIdxBit_S2NS = 1 << 6, 2145 ARMMMUIdxBit_MUser = 1 << 0, 2146 ARMMMUIdxBit_MPriv = 1 << 1, 2147 ARMMMUIdxBit_MNegPri = 1 << 2, 2148 } ARMMMUIdxBit; 2149 2150 #define MMU_USER_IDX 0 2151 2152 static inline int arm_to_core_mmu_idx(ARMMMUIdx mmu_idx) 2153 { 2154 return mmu_idx & ARM_MMU_IDX_COREIDX_MASK; 2155 } 2156 2157 static inline ARMMMUIdx core_to_arm_mmu_idx(CPUARMState *env, int mmu_idx) 2158 { 2159 if (arm_feature(env, ARM_FEATURE_M)) { 2160 return mmu_idx | ARM_MMU_IDX_M; 2161 } else { 2162 return mmu_idx | ARM_MMU_IDX_A; 2163 } 2164 } 2165 2166 /* Return the exception level we're running at if this is our mmu_idx */ 2167 static inline int arm_mmu_idx_to_el(ARMMMUIdx mmu_idx) 2168 { 2169 switch (mmu_idx & ARM_MMU_IDX_TYPE_MASK) { 2170 case ARM_MMU_IDX_A: 2171 return mmu_idx & 3; 2172 case ARM_MMU_IDX_M: 2173 return mmu_idx == ARMMMUIdx_MUser ? 0 : 1; 2174 default: 2175 g_assert_not_reached(); 2176 } 2177 } 2178 2179 /* Determine the current mmu_idx to use for normal loads/stores */ 2180 static inline int cpu_mmu_index(CPUARMState *env, bool ifetch) 2181 { 2182 int el = arm_current_el(env); 2183 2184 if (arm_feature(env, ARM_FEATURE_M)) { 2185 ARMMMUIdx mmu_idx = el == 0 ? ARMMMUIdx_MUser : ARMMMUIdx_MPriv; 2186 2187 /* Execution priority is negative if FAULTMASK is set or 2188 * we're in a HardFault or NMI handler. 2189 */ 2190 if ((env->v7m.exception > 0 && env->v7m.exception <= 3) 2191 || env->v7m.faultmask) { 2192 return arm_to_core_mmu_idx(ARMMMUIdx_MNegPri); 2193 } 2194 2195 return arm_to_core_mmu_idx(mmu_idx); 2196 } 2197 2198 if (el < 2 && arm_is_secure_below_el3(env)) { 2199 return arm_to_core_mmu_idx(ARMMMUIdx_S1SE0 + el); 2200 } 2201 return el; 2202 } 2203 2204 /* Indexes used when registering address spaces with cpu_address_space_init */ 2205 typedef enum ARMASIdx { 2206 ARMASIdx_NS = 0, 2207 ARMASIdx_S = 1, 2208 } ARMASIdx; 2209 2210 /* Return the Exception Level targeted by debug exceptions. */ 2211 static inline int arm_debug_target_el(CPUARMState *env) 2212 { 2213 bool secure = arm_is_secure(env); 2214 bool route_to_el2 = false; 2215 2216 if (arm_feature(env, ARM_FEATURE_EL2) && !secure) { 2217 route_to_el2 = env->cp15.hcr_el2 & HCR_TGE || 2218 env->cp15.mdcr_el2 & (1 << 8); 2219 } 2220 2221 if (route_to_el2) { 2222 return 2; 2223 } else if (arm_feature(env, ARM_FEATURE_EL3) && 2224 !arm_el_is_aa64(env, 3) && secure) { 2225 return 3; 2226 } else { 2227 return 1; 2228 } 2229 } 2230 2231 static inline bool aa64_generate_debug_exceptions(CPUARMState *env) 2232 { 2233 if (arm_is_secure(env)) { 2234 /* MDCR_EL3.SDD disables debug events from Secure state */ 2235 if (extract32(env->cp15.mdcr_el3, 16, 1) != 0 2236 || arm_current_el(env) == 3) { 2237 return false; 2238 } 2239 } 2240 2241 if (arm_current_el(env) == arm_debug_target_el(env)) { 2242 if ((extract32(env->cp15.mdscr_el1, 13, 1) == 0) 2243 || (env->daif & PSTATE_D)) { 2244 return false; 2245 } 2246 } 2247 return true; 2248 } 2249 2250 static inline bool aa32_generate_debug_exceptions(CPUARMState *env) 2251 { 2252 int el = arm_current_el(env); 2253 2254 if (el == 0 && arm_el_is_aa64(env, 1)) { 2255 return aa64_generate_debug_exceptions(env); 2256 } 2257 2258 if (arm_is_secure(env)) { 2259 int spd; 2260 2261 if (el == 0 && (env->cp15.sder & 1)) { 2262 /* SDER.SUIDEN means debug exceptions from Secure EL0 2263 * are always enabled. Otherwise they are controlled by 2264 * SDCR.SPD like those from other Secure ELs. 2265 */ 2266 return true; 2267 } 2268 2269 spd = extract32(env->cp15.mdcr_el3, 14, 2); 2270 switch (spd) { 2271 case 1: 2272 /* SPD == 0b01 is reserved, but behaves as 0b00. */ 2273 case 0: 2274 /* For 0b00 we return true if external secure invasive debug 2275 * is enabled. On real hardware this is controlled by external 2276 * signals to the core. QEMU always permits debug, and behaves 2277 * as if DBGEN, SPIDEN, NIDEN and SPNIDEN are all tied high. 2278 */ 2279 return true; 2280 case 2: 2281 return false; 2282 case 3: 2283 return true; 2284 } 2285 } 2286 2287 return el != 2; 2288 } 2289 2290 /* Return true if debugging exceptions are currently enabled. 2291 * This corresponds to what in ARM ARM pseudocode would be 2292 * if UsingAArch32() then 2293 * return AArch32.GenerateDebugExceptions() 2294 * else 2295 * return AArch64.GenerateDebugExceptions() 2296 * We choose to push the if() down into this function for clarity, 2297 * since the pseudocode has it at all callsites except for the one in 2298 * CheckSoftwareStep(), where it is elided because both branches would 2299 * always return the same value. 2300 * 2301 * Parts of the pseudocode relating to EL2 and EL3 are omitted because we 2302 * don't yet implement those exception levels or their associated trap bits. 2303 */ 2304 static inline bool arm_generate_debug_exceptions(CPUARMState *env) 2305 { 2306 if (env->aarch64) { 2307 return aa64_generate_debug_exceptions(env); 2308 } else { 2309 return aa32_generate_debug_exceptions(env); 2310 } 2311 } 2312 2313 /* Is single-stepping active? (Note that the "is EL_D AArch64?" check 2314 * implicitly means this always returns false in pre-v8 CPUs.) 2315 */ 2316 static inline bool arm_singlestep_active(CPUARMState *env) 2317 { 2318 return extract32(env->cp15.mdscr_el1, 0, 1) 2319 && arm_el_is_aa64(env, arm_debug_target_el(env)) 2320 && arm_generate_debug_exceptions(env); 2321 } 2322 2323 static inline bool arm_sctlr_b(CPUARMState *env) 2324 { 2325 return 2326 /* We need not implement SCTLR.ITD in user-mode emulation, so 2327 * let linux-user ignore the fact that it conflicts with SCTLR_B. 2328 * This lets people run BE32 binaries with "-cpu any". 2329 */ 2330 #ifndef CONFIG_USER_ONLY 2331 !arm_feature(env, ARM_FEATURE_V7) && 2332 #endif 2333 (env->cp15.sctlr_el[1] & SCTLR_B) != 0; 2334 } 2335 2336 /* Return true if the processor is in big-endian mode. */ 2337 static inline bool arm_cpu_data_is_big_endian(CPUARMState *env) 2338 { 2339 int cur_el; 2340 2341 /* In 32bit endianness is determined by looking at CPSR's E bit */ 2342 if (!is_a64(env)) { 2343 return 2344 #ifdef CONFIG_USER_ONLY 2345 /* In system mode, BE32 is modelled in line with the 2346 * architecture (as word-invariant big-endianness), where loads 2347 * and stores are done little endian but from addresses which 2348 * are adjusted by XORing with the appropriate constant. So the 2349 * endianness to use for the raw data access is not affected by 2350 * SCTLR.B. 2351 * In user mode, however, we model BE32 as byte-invariant 2352 * big-endianness (because user-only code cannot tell the 2353 * difference), and so we need to use a data access endianness 2354 * that depends on SCTLR.B. 2355 */ 2356 arm_sctlr_b(env) || 2357 #endif 2358 ((env->uncached_cpsr & CPSR_E) ? 1 : 0); 2359 } 2360 2361 cur_el = arm_current_el(env); 2362 2363 if (cur_el == 0) { 2364 return (env->cp15.sctlr_el[1] & SCTLR_E0E) != 0; 2365 } 2366 2367 return (env->cp15.sctlr_el[cur_el] & SCTLR_EE) != 0; 2368 } 2369 2370 #include "exec/cpu-all.h" 2371 2372 /* Bit usage in the TB flags field: bit 31 indicates whether we are 2373 * in 32 or 64 bit mode. The meaning of the other bits depends on that. 2374 * We put flags which are shared between 32 and 64 bit mode at the top 2375 * of the word, and flags which apply to only one mode at the bottom. 2376 */ 2377 #define ARM_TBFLAG_AARCH64_STATE_SHIFT 31 2378 #define ARM_TBFLAG_AARCH64_STATE_MASK (1U << ARM_TBFLAG_AARCH64_STATE_SHIFT) 2379 #define ARM_TBFLAG_MMUIDX_SHIFT 28 2380 #define ARM_TBFLAG_MMUIDX_MASK (0x7 << ARM_TBFLAG_MMUIDX_SHIFT) 2381 #define ARM_TBFLAG_SS_ACTIVE_SHIFT 27 2382 #define ARM_TBFLAG_SS_ACTIVE_MASK (1 << ARM_TBFLAG_SS_ACTIVE_SHIFT) 2383 #define ARM_TBFLAG_PSTATE_SS_SHIFT 26 2384 #define ARM_TBFLAG_PSTATE_SS_MASK (1 << ARM_TBFLAG_PSTATE_SS_SHIFT) 2385 /* Target EL if we take a floating-point-disabled exception */ 2386 #define ARM_TBFLAG_FPEXC_EL_SHIFT 24 2387 #define ARM_TBFLAG_FPEXC_EL_MASK (0x3 << ARM_TBFLAG_FPEXC_EL_SHIFT) 2388 2389 /* Bit usage when in AArch32 state: */ 2390 #define ARM_TBFLAG_THUMB_SHIFT 0 2391 #define ARM_TBFLAG_THUMB_MASK (1 << ARM_TBFLAG_THUMB_SHIFT) 2392 #define ARM_TBFLAG_VECLEN_SHIFT 1 2393 #define ARM_TBFLAG_VECLEN_MASK (0x7 << ARM_TBFLAG_VECLEN_SHIFT) 2394 #define ARM_TBFLAG_VECSTRIDE_SHIFT 4 2395 #define ARM_TBFLAG_VECSTRIDE_MASK (0x3 << ARM_TBFLAG_VECSTRIDE_SHIFT) 2396 #define ARM_TBFLAG_VFPEN_SHIFT 7 2397 #define ARM_TBFLAG_VFPEN_MASK (1 << ARM_TBFLAG_VFPEN_SHIFT) 2398 #define ARM_TBFLAG_CONDEXEC_SHIFT 8 2399 #define ARM_TBFLAG_CONDEXEC_MASK (0xff << ARM_TBFLAG_CONDEXEC_SHIFT) 2400 #define ARM_TBFLAG_SCTLR_B_SHIFT 16 2401 #define ARM_TBFLAG_SCTLR_B_MASK (1 << ARM_TBFLAG_SCTLR_B_SHIFT) 2402 /* We store the bottom two bits of the CPAR as TB flags and handle 2403 * checks on the other bits at runtime 2404 */ 2405 #define ARM_TBFLAG_XSCALE_CPAR_SHIFT 17 2406 #define ARM_TBFLAG_XSCALE_CPAR_MASK (3 << ARM_TBFLAG_XSCALE_CPAR_SHIFT) 2407 /* Indicates whether cp register reads and writes by guest code should access 2408 * the secure or nonsecure bank of banked registers; note that this is not 2409 * the same thing as the current security state of the processor! 2410 */ 2411 #define ARM_TBFLAG_NS_SHIFT 19 2412 #define ARM_TBFLAG_NS_MASK (1 << ARM_TBFLAG_NS_SHIFT) 2413 #define ARM_TBFLAG_BE_DATA_SHIFT 20 2414 #define ARM_TBFLAG_BE_DATA_MASK (1 << ARM_TBFLAG_BE_DATA_SHIFT) 2415 /* For M profile only, Handler (ie not Thread) mode */ 2416 #define ARM_TBFLAG_HANDLER_SHIFT 21 2417 #define ARM_TBFLAG_HANDLER_MASK (1 << ARM_TBFLAG_HANDLER_SHIFT) 2418 2419 /* Bit usage when in AArch64 state */ 2420 #define ARM_TBFLAG_TBI0_SHIFT 0 /* TBI0 for EL0/1 or TBI for EL2/3 */ 2421 #define ARM_TBFLAG_TBI0_MASK (0x1ull << ARM_TBFLAG_TBI0_SHIFT) 2422 #define ARM_TBFLAG_TBI1_SHIFT 1 /* TBI1 for EL0/1 */ 2423 #define ARM_TBFLAG_TBI1_MASK (0x1ull << ARM_TBFLAG_TBI1_SHIFT) 2424 2425 /* some convenience accessor macros */ 2426 #define ARM_TBFLAG_AARCH64_STATE(F) \ 2427 (((F) & ARM_TBFLAG_AARCH64_STATE_MASK) >> ARM_TBFLAG_AARCH64_STATE_SHIFT) 2428 #define ARM_TBFLAG_MMUIDX(F) \ 2429 (((F) & ARM_TBFLAG_MMUIDX_MASK) >> ARM_TBFLAG_MMUIDX_SHIFT) 2430 #define ARM_TBFLAG_SS_ACTIVE(F) \ 2431 (((F) & ARM_TBFLAG_SS_ACTIVE_MASK) >> ARM_TBFLAG_SS_ACTIVE_SHIFT) 2432 #define ARM_TBFLAG_PSTATE_SS(F) \ 2433 (((F) & ARM_TBFLAG_PSTATE_SS_MASK) >> ARM_TBFLAG_PSTATE_SS_SHIFT) 2434 #define ARM_TBFLAG_FPEXC_EL(F) \ 2435 (((F) & ARM_TBFLAG_FPEXC_EL_MASK) >> ARM_TBFLAG_FPEXC_EL_SHIFT) 2436 #define ARM_TBFLAG_THUMB(F) \ 2437 (((F) & ARM_TBFLAG_THUMB_MASK) >> ARM_TBFLAG_THUMB_SHIFT) 2438 #define ARM_TBFLAG_VECLEN(F) \ 2439 (((F) & ARM_TBFLAG_VECLEN_MASK) >> ARM_TBFLAG_VECLEN_SHIFT) 2440 #define ARM_TBFLAG_VECSTRIDE(F) \ 2441 (((F) & ARM_TBFLAG_VECSTRIDE_MASK) >> ARM_TBFLAG_VECSTRIDE_SHIFT) 2442 #define ARM_TBFLAG_VFPEN(F) \ 2443 (((F) & ARM_TBFLAG_VFPEN_MASK) >> ARM_TBFLAG_VFPEN_SHIFT) 2444 #define ARM_TBFLAG_CONDEXEC(F) \ 2445 (((F) & ARM_TBFLAG_CONDEXEC_MASK) >> ARM_TBFLAG_CONDEXEC_SHIFT) 2446 #define ARM_TBFLAG_SCTLR_B(F) \ 2447 (((F) & ARM_TBFLAG_SCTLR_B_MASK) >> ARM_TBFLAG_SCTLR_B_SHIFT) 2448 #define ARM_TBFLAG_XSCALE_CPAR(F) \ 2449 (((F) & ARM_TBFLAG_XSCALE_CPAR_MASK) >> ARM_TBFLAG_XSCALE_CPAR_SHIFT) 2450 #define ARM_TBFLAG_NS(F) \ 2451 (((F) & ARM_TBFLAG_NS_MASK) >> ARM_TBFLAG_NS_SHIFT) 2452 #define ARM_TBFLAG_BE_DATA(F) \ 2453 (((F) & ARM_TBFLAG_BE_DATA_MASK) >> ARM_TBFLAG_BE_DATA_SHIFT) 2454 #define ARM_TBFLAG_HANDLER(F) \ 2455 (((F) & ARM_TBFLAG_HANDLER_MASK) >> ARM_TBFLAG_HANDLER_SHIFT) 2456 #define ARM_TBFLAG_TBI0(F) \ 2457 (((F) & ARM_TBFLAG_TBI0_MASK) >> ARM_TBFLAG_TBI0_SHIFT) 2458 #define ARM_TBFLAG_TBI1(F) \ 2459 (((F) & ARM_TBFLAG_TBI1_MASK) >> ARM_TBFLAG_TBI1_SHIFT) 2460 2461 static inline bool bswap_code(bool sctlr_b) 2462 { 2463 #ifdef CONFIG_USER_ONLY 2464 /* BE8 (SCTLR.B = 0, TARGET_WORDS_BIGENDIAN = 1) is mixed endian. 2465 * The invalid combination SCTLR.B=1/CPSR.E=1/TARGET_WORDS_BIGENDIAN=0 2466 * would also end up as a mixed-endian mode with BE code, LE data. 2467 */ 2468 return 2469 #ifdef TARGET_WORDS_BIGENDIAN 2470 1 ^ 2471 #endif 2472 sctlr_b; 2473 #else 2474 /* All code access in ARM is little endian, and there are no loaders 2475 * doing swaps that need to be reversed 2476 */ 2477 return 0; 2478 #endif 2479 } 2480 2481 /* Return the exception level to which FP-disabled exceptions should 2482 * be taken, or 0 if FP is enabled. 2483 */ 2484 static inline int fp_exception_el(CPUARMState *env) 2485 { 2486 int fpen; 2487 int cur_el = arm_current_el(env); 2488 2489 /* CPACR and the CPTR registers don't exist before v6, so FP is 2490 * always accessible 2491 */ 2492 if (!arm_feature(env, ARM_FEATURE_V6)) { 2493 return 0; 2494 } 2495 2496 /* The CPACR controls traps to EL1, or PL1 if we're 32 bit: 2497 * 0, 2 : trap EL0 and EL1/PL1 accesses 2498 * 1 : trap only EL0 accesses 2499 * 3 : trap no accesses 2500 */ 2501 fpen = extract32(env->cp15.cpacr_el1, 20, 2); 2502 switch (fpen) { 2503 case 0: 2504 case 2: 2505 if (cur_el == 0 || cur_el == 1) { 2506 /* Trap to PL1, which might be EL1 or EL3 */ 2507 if (arm_is_secure(env) && !arm_el_is_aa64(env, 3)) { 2508 return 3; 2509 } 2510 return 1; 2511 } 2512 if (cur_el == 3 && !is_a64(env)) { 2513 /* Secure PL1 running at EL3 */ 2514 return 3; 2515 } 2516 break; 2517 case 1: 2518 if (cur_el == 0) { 2519 return 1; 2520 } 2521 break; 2522 case 3: 2523 break; 2524 } 2525 2526 /* For the CPTR registers we don't need to guard with an ARM_FEATURE 2527 * check because zero bits in the registers mean "don't trap". 2528 */ 2529 2530 /* CPTR_EL2 : present in v7VE or v8 */ 2531 if (cur_el <= 2 && extract32(env->cp15.cptr_el[2], 10, 1) 2532 && !arm_is_secure_below_el3(env)) { 2533 /* Trap FP ops at EL2, NS-EL1 or NS-EL0 to EL2 */ 2534 return 2; 2535 } 2536 2537 /* CPTR_EL3 : present in v8 */ 2538 if (extract32(env->cp15.cptr_el[3], 10, 1)) { 2539 /* Trap all FP ops to EL3 */ 2540 return 3; 2541 } 2542 2543 return 0; 2544 } 2545 2546 #ifdef CONFIG_USER_ONLY 2547 static inline bool arm_cpu_bswap_data(CPUARMState *env) 2548 { 2549 return 2550 #ifdef TARGET_WORDS_BIGENDIAN 2551 1 ^ 2552 #endif 2553 arm_cpu_data_is_big_endian(env); 2554 } 2555 #endif 2556 2557 #ifndef CONFIG_USER_ONLY 2558 /** 2559 * arm_regime_tbi0: 2560 * @env: CPUARMState 2561 * @mmu_idx: MMU index indicating required translation regime 2562 * 2563 * Extracts the TBI0 value from the appropriate TCR for the current EL 2564 * 2565 * Returns: the TBI0 value. 2566 */ 2567 uint32_t arm_regime_tbi0(CPUARMState *env, ARMMMUIdx mmu_idx); 2568 2569 /** 2570 * arm_regime_tbi1: 2571 * @env: CPUARMState 2572 * @mmu_idx: MMU index indicating required translation regime 2573 * 2574 * Extracts the TBI1 value from the appropriate TCR for the current EL 2575 * 2576 * Returns: the TBI1 value. 2577 */ 2578 uint32_t arm_regime_tbi1(CPUARMState *env, ARMMMUIdx mmu_idx); 2579 #else 2580 /* We can't handle tagged addresses properly in user-only mode */ 2581 static inline uint32_t arm_regime_tbi0(CPUARMState *env, ARMMMUIdx mmu_idx) 2582 { 2583 return 0; 2584 } 2585 2586 static inline uint32_t arm_regime_tbi1(CPUARMState *env, ARMMMUIdx mmu_idx) 2587 { 2588 return 0; 2589 } 2590 #endif 2591 2592 static inline void cpu_get_tb_cpu_state(CPUARMState *env, target_ulong *pc, 2593 target_ulong *cs_base, uint32_t *flags) 2594 { 2595 ARMMMUIdx mmu_idx = core_to_arm_mmu_idx(env, cpu_mmu_index(env, false)); 2596 if (is_a64(env)) { 2597 *pc = env->pc; 2598 *flags = ARM_TBFLAG_AARCH64_STATE_MASK; 2599 /* Get control bits for tagged addresses */ 2600 *flags |= (arm_regime_tbi0(env, mmu_idx) << ARM_TBFLAG_TBI0_SHIFT); 2601 *flags |= (arm_regime_tbi1(env, mmu_idx) << ARM_TBFLAG_TBI1_SHIFT); 2602 } else { 2603 *pc = env->regs[15]; 2604 *flags = (env->thumb << ARM_TBFLAG_THUMB_SHIFT) 2605 | (env->vfp.vec_len << ARM_TBFLAG_VECLEN_SHIFT) 2606 | (env->vfp.vec_stride << ARM_TBFLAG_VECSTRIDE_SHIFT) 2607 | (env->condexec_bits << ARM_TBFLAG_CONDEXEC_SHIFT) 2608 | (arm_sctlr_b(env) << ARM_TBFLAG_SCTLR_B_SHIFT); 2609 if (!(access_secure_reg(env))) { 2610 *flags |= ARM_TBFLAG_NS_MASK; 2611 } 2612 if (env->vfp.xregs[ARM_VFP_FPEXC] & (1 << 30) 2613 || arm_el_is_aa64(env, 1)) { 2614 *flags |= ARM_TBFLAG_VFPEN_MASK; 2615 } 2616 *flags |= (extract32(env->cp15.c15_cpar, 0, 2) 2617 << ARM_TBFLAG_XSCALE_CPAR_SHIFT); 2618 } 2619 2620 *flags |= (arm_to_core_mmu_idx(mmu_idx) << ARM_TBFLAG_MMUIDX_SHIFT); 2621 2622 /* The SS_ACTIVE and PSTATE_SS bits correspond to the state machine 2623 * states defined in the ARM ARM for software singlestep: 2624 * SS_ACTIVE PSTATE.SS State 2625 * 0 x Inactive (the TB flag for SS is always 0) 2626 * 1 0 Active-pending 2627 * 1 1 Active-not-pending 2628 */ 2629 if (arm_singlestep_active(env)) { 2630 *flags |= ARM_TBFLAG_SS_ACTIVE_MASK; 2631 if (is_a64(env)) { 2632 if (env->pstate & PSTATE_SS) { 2633 *flags |= ARM_TBFLAG_PSTATE_SS_MASK; 2634 } 2635 } else { 2636 if (env->uncached_cpsr & PSTATE_SS) { 2637 *flags |= ARM_TBFLAG_PSTATE_SS_MASK; 2638 } 2639 } 2640 } 2641 if (arm_cpu_data_is_big_endian(env)) { 2642 *flags |= ARM_TBFLAG_BE_DATA_MASK; 2643 } 2644 *flags |= fp_exception_el(env) << ARM_TBFLAG_FPEXC_EL_SHIFT; 2645 2646 if (arm_v7m_is_handler_mode(env)) { 2647 *flags |= ARM_TBFLAG_HANDLER_MASK; 2648 } 2649 2650 *cs_base = 0; 2651 } 2652 2653 enum { 2654 QEMU_PSCI_CONDUIT_DISABLED = 0, 2655 QEMU_PSCI_CONDUIT_SMC = 1, 2656 QEMU_PSCI_CONDUIT_HVC = 2, 2657 }; 2658 2659 #ifndef CONFIG_USER_ONLY 2660 /* Return the address space index to use for a memory access */ 2661 static inline int arm_asidx_from_attrs(CPUState *cs, MemTxAttrs attrs) 2662 { 2663 return attrs.secure ? ARMASIdx_S : ARMASIdx_NS; 2664 } 2665 2666 /* Return the AddressSpace to use for a memory access 2667 * (which depends on whether the access is S or NS, and whether 2668 * the board gave us a separate AddressSpace for S accesses). 2669 */ 2670 static inline AddressSpace *arm_addressspace(CPUState *cs, MemTxAttrs attrs) 2671 { 2672 return cpu_get_address_space(cs, arm_asidx_from_attrs(cs, attrs)); 2673 } 2674 #endif 2675 2676 /** 2677 * arm_register_el_change_hook: 2678 * Register a hook function which will be called back whenever this 2679 * CPU changes exception level or mode. The hook function will be 2680 * passed a pointer to the ARMCPU and the opaque data pointer passed 2681 * to this function when the hook was registered. 2682 * 2683 * Note that we currently only support registering a single hook function, 2684 * and will assert if this function is called twice. 2685 * This facility is intended for the use of the GICv3 emulation. 2686 */ 2687 void arm_register_el_change_hook(ARMCPU *cpu, ARMELChangeHook *hook, 2688 void *opaque); 2689 2690 /** 2691 * arm_get_el_change_hook_opaque: 2692 * Return the opaque data that will be used by the el_change_hook 2693 * for this CPU. 2694 */ 2695 static inline void *arm_get_el_change_hook_opaque(ARMCPU *cpu) 2696 { 2697 return cpu->el_change_hook_opaque; 2698 } 2699 2700 #endif 2701