1 /* 2 * ARM virtual CPU header 3 * 4 * Copyright (c) 2003 Fabrice Bellard 5 * 6 * This library is free software; you can redistribute it and/or 7 * modify it under the terms of the GNU Lesser General Public 8 * License as published by the Free Software Foundation; either 9 * version 2 of the License, or (at your option) any later version. 10 * 11 * This library is distributed in the hope that it will be useful, 12 * but WITHOUT ANY WARRANTY; without even the implied warranty of 13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU 14 * Lesser General Public License for more details. 15 * 16 * You should have received a copy of the GNU Lesser General Public 17 * License along with this library; if not, see <http://www.gnu.org/licenses/>. 18 */ 19 20 #ifndef ARM_CPU_H 21 #define ARM_CPU_H 22 23 #include "kvm-consts.h" 24 #include "hw/registerfields.h" 25 26 #if defined(TARGET_AARCH64) 27 /* AArch64 definitions */ 28 # define TARGET_LONG_BITS 64 29 #else 30 # define TARGET_LONG_BITS 32 31 #endif 32 33 /* ARM processors have a weak memory model */ 34 #define TCG_GUEST_DEFAULT_MO (0) 35 36 #define CPUArchState struct CPUARMState 37 38 #include "qemu-common.h" 39 #include "cpu-qom.h" 40 #include "exec/cpu-defs.h" 41 42 #define EXCP_UDEF 1 /* undefined instruction */ 43 #define EXCP_SWI 2 /* software interrupt */ 44 #define EXCP_PREFETCH_ABORT 3 45 #define EXCP_DATA_ABORT 4 46 #define EXCP_IRQ 5 47 #define EXCP_FIQ 6 48 #define EXCP_BKPT 7 49 #define EXCP_EXCEPTION_EXIT 8 /* Return from v7M exception. */ 50 #define EXCP_KERNEL_TRAP 9 /* Jumped to kernel code page. */ 51 #define EXCP_HVC 11 /* HyperVisor Call */ 52 #define EXCP_HYP_TRAP 12 53 #define EXCP_SMC 13 /* Secure Monitor Call */ 54 #define EXCP_VIRQ 14 55 #define EXCP_VFIQ 15 56 #define EXCP_SEMIHOST 16 /* semihosting call */ 57 #define EXCP_NOCP 17 /* v7M NOCP UsageFault */ 58 #define EXCP_INVSTATE 18 /* v7M INVSTATE UsageFault */ 59 /* NB: add new EXCP_ defines to the array in arm_log_exception() too */ 60 61 #define ARMV7M_EXCP_RESET 1 62 #define ARMV7M_EXCP_NMI 2 63 #define ARMV7M_EXCP_HARD 3 64 #define ARMV7M_EXCP_MEM 4 65 #define ARMV7M_EXCP_BUS 5 66 #define ARMV7M_EXCP_USAGE 6 67 #define ARMV7M_EXCP_SECURE 7 68 #define ARMV7M_EXCP_SVC 11 69 #define ARMV7M_EXCP_DEBUG 12 70 #define ARMV7M_EXCP_PENDSV 14 71 #define ARMV7M_EXCP_SYSTICK 15 72 73 /* For M profile, some registers are banked secure vs non-secure; 74 * these are represented as a 2-element array where the first element 75 * is the non-secure copy and the second is the secure copy. 76 * When the CPU does not have implement the security extension then 77 * only the first element is used. 78 * This means that the copy for the current security state can be 79 * accessed via env->registerfield[env->v7m.secure] (whether the security 80 * extension is implemented or not). 81 */ 82 enum { 83 M_REG_NS = 0, 84 M_REG_S = 1, 85 M_REG_NUM_BANKS = 2, 86 }; 87 88 /* ARM-specific interrupt pending bits. */ 89 #define CPU_INTERRUPT_FIQ CPU_INTERRUPT_TGT_EXT_1 90 #define CPU_INTERRUPT_VIRQ CPU_INTERRUPT_TGT_EXT_2 91 #define CPU_INTERRUPT_VFIQ CPU_INTERRUPT_TGT_EXT_3 92 93 /* The usual mapping for an AArch64 system register to its AArch32 94 * counterpart is for the 32 bit world to have access to the lower 95 * half only (with writes leaving the upper half untouched). It's 96 * therefore useful to be able to pass TCG the offset of the least 97 * significant half of a uint64_t struct member. 98 */ 99 #ifdef HOST_WORDS_BIGENDIAN 100 #define offsetoflow32(S, M) (offsetof(S, M) + sizeof(uint32_t)) 101 #define offsetofhigh32(S, M) offsetof(S, M) 102 #else 103 #define offsetoflow32(S, M) offsetof(S, M) 104 #define offsetofhigh32(S, M) (offsetof(S, M) + sizeof(uint32_t)) 105 #endif 106 107 /* Meanings of the ARMCPU object's four inbound GPIO lines */ 108 #define ARM_CPU_IRQ 0 109 #define ARM_CPU_FIQ 1 110 #define ARM_CPU_VIRQ 2 111 #define ARM_CPU_VFIQ 3 112 113 #define NB_MMU_MODES 8 114 /* ARM-specific extra insn start words: 115 * 1: Conditional execution bits 116 * 2: Partial exception syndrome for data aborts 117 */ 118 #define TARGET_INSN_START_EXTRA_WORDS 2 119 120 /* The 2nd extra word holding syndrome info for data aborts does not use 121 * the upper 6 bits nor the lower 14 bits. We mask and shift it down to 122 * help the sleb128 encoder do a better job. 123 * When restoring the CPU state, we shift it back up. 124 */ 125 #define ARM_INSN_START_WORD2_MASK ((1 << 26) - 1) 126 #define ARM_INSN_START_WORD2_SHIFT 14 127 128 /* We currently assume float and double are IEEE single and double 129 precision respectively. 130 Doing runtime conversions is tricky because VFP registers may contain 131 integer values (eg. as the result of a FTOSI instruction). 132 s<2n> maps to the least significant half of d<n> 133 s<2n+1> maps to the most significant half of d<n> 134 */ 135 136 /* CPU state for each instance of a generic timer (in cp15 c14) */ 137 typedef struct ARMGenericTimer { 138 uint64_t cval; /* Timer CompareValue register */ 139 uint64_t ctl; /* Timer Control register */ 140 } ARMGenericTimer; 141 142 #define GTIMER_PHYS 0 143 #define GTIMER_VIRT 1 144 #define GTIMER_HYP 2 145 #define GTIMER_SEC 3 146 #define NUM_GTIMERS 4 147 148 typedef struct { 149 uint64_t raw_tcr; 150 uint32_t mask; 151 uint32_t base_mask; 152 } TCR; 153 154 /* Define a maximum sized vector register. 155 * For 32-bit, this is a 128-bit NEON/AdvSIMD register. 156 * For 64-bit, this is a 2048-bit SVE register. 157 * 158 * Note that the mapping between S, D, and Q views of the register bank 159 * differs between AArch64 and AArch32. 160 * In AArch32: 161 * Qn = regs[n].d[1]:regs[n].d[0] 162 * Dn = regs[n / 2].d[n & 1] 163 * Sn = regs[n / 4].d[n % 4 / 2], 164 * bits 31..0 for even n, and bits 63..32 for odd n 165 * (and regs[16] to regs[31] are inaccessible) 166 * In AArch64: 167 * Zn = regs[n].d[*] 168 * Qn = regs[n].d[1]:regs[n].d[0] 169 * Dn = regs[n].d[0] 170 * Sn = regs[n].d[0] bits 31..0 171 * 172 * This corresponds to the architecturally defined mapping between 173 * the two execution states, and means we do not need to explicitly 174 * map these registers when changing states. 175 * 176 * Align the data for use with TCG host vector operations. 177 */ 178 179 #ifdef TARGET_AARCH64 180 # define ARM_MAX_VQ 16 181 #else 182 # define ARM_MAX_VQ 1 183 #endif 184 185 typedef struct ARMVectorReg { 186 uint64_t d[2 * ARM_MAX_VQ] QEMU_ALIGNED(16); 187 } ARMVectorReg; 188 189 /* In AArch32 mode, predicate registers do not exist at all. */ 190 #ifdef TARGET_AARCH64 191 typedef struct ARMPredicateReg { 192 uint64_t p[2 * ARM_MAX_VQ / 8] QEMU_ALIGNED(16); 193 } ARMPredicateReg; 194 #endif 195 196 197 typedef struct CPUARMState { 198 /* Regs for current mode. */ 199 uint32_t regs[16]; 200 201 /* 32/64 switch only happens when taking and returning from 202 * exceptions so the overlap semantics are taken care of then 203 * instead of having a complicated union. 204 */ 205 /* Regs for A64 mode. */ 206 uint64_t xregs[32]; 207 uint64_t pc; 208 /* PSTATE isn't an architectural register for ARMv8. However, it is 209 * convenient for us to assemble the underlying state into a 32 bit format 210 * identical to the architectural format used for the SPSR. (This is also 211 * what the Linux kernel's 'pstate' field in signal handlers and KVM's 212 * 'pstate' register are.) Of the PSTATE bits: 213 * NZCV are kept in the split out env->CF/VF/NF/ZF, (which have the same 214 * semantics as for AArch32, as described in the comments on each field) 215 * nRW (also known as M[4]) is kept, inverted, in env->aarch64 216 * DAIF (exception masks) are kept in env->daif 217 * all other bits are stored in their correct places in env->pstate 218 */ 219 uint32_t pstate; 220 uint32_t aarch64; /* 1 if CPU is in aarch64 state; inverse of PSTATE.nRW */ 221 222 /* Frequently accessed CPSR bits are stored separately for efficiency. 223 This contains all the other bits. Use cpsr_{read,write} to access 224 the whole CPSR. */ 225 uint32_t uncached_cpsr; 226 uint32_t spsr; 227 228 /* Banked registers. */ 229 uint64_t banked_spsr[8]; 230 uint32_t banked_r13[8]; 231 uint32_t banked_r14[8]; 232 233 /* These hold r8-r12. */ 234 uint32_t usr_regs[5]; 235 uint32_t fiq_regs[5]; 236 237 /* cpsr flag cache for faster execution */ 238 uint32_t CF; /* 0 or 1 */ 239 uint32_t VF; /* V is the bit 31. All other bits are undefined */ 240 uint32_t NF; /* N is bit 31. All other bits are undefined. */ 241 uint32_t ZF; /* Z set if zero. */ 242 uint32_t QF; /* 0 or 1 */ 243 uint32_t GE; /* cpsr[19:16] */ 244 uint32_t thumb; /* cpsr[5]. 0 = arm mode, 1 = thumb mode. */ 245 uint32_t condexec_bits; /* IT bits. cpsr[15:10,26:25]. */ 246 uint64_t daif; /* exception masks, in the bits they are in PSTATE */ 247 248 uint64_t elr_el[4]; /* AArch64 exception link regs */ 249 uint64_t sp_el[4]; /* AArch64 banked stack pointers */ 250 251 /* System control coprocessor (cp15) */ 252 struct { 253 uint32_t c0_cpuid; 254 union { /* Cache size selection */ 255 struct { 256 uint64_t _unused_csselr0; 257 uint64_t csselr_ns; 258 uint64_t _unused_csselr1; 259 uint64_t csselr_s; 260 }; 261 uint64_t csselr_el[4]; 262 }; 263 union { /* System control register. */ 264 struct { 265 uint64_t _unused_sctlr; 266 uint64_t sctlr_ns; 267 uint64_t hsctlr; 268 uint64_t sctlr_s; 269 }; 270 uint64_t sctlr_el[4]; 271 }; 272 uint64_t cpacr_el1; /* Architectural feature access control register */ 273 uint64_t cptr_el[4]; /* ARMv8 feature trap registers */ 274 uint32_t c1_xscaleauxcr; /* XScale auxiliary control register. */ 275 uint64_t sder; /* Secure debug enable register. */ 276 uint32_t nsacr; /* Non-secure access control register. */ 277 union { /* MMU translation table base 0. */ 278 struct { 279 uint64_t _unused_ttbr0_0; 280 uint64_t ttbr0_ns; 281 uint64_t _unused_ttbr0_1; 282 uint64_t ttbr0_s; 283 }; 284 uint64_t ttbr0_el[4]; 285 }; 286 union { /* MMU translation table base 1. */ 287 struct { 288 uint64_t _unused_ttbr1_0; 289 uint64_t ttbr1_ns; 290 uint64_t _unused_ttbr1_1; 291 uint64_t ttbr1_s; 292 }; 293 uint64_t ttbr1_el[4]; 294 }; 295 uint64_t vttbr_el2; /* Virtualization Translation Table Base. */ 296 /* MMU translation table base control. */ 297 TCR tcr_el[4]; 298 TCR vtcr_el2; /* Virtualization Translation Control. */ 299 uint32_t c2_data; /* MPU data cacheable bits. */ 300 uint32_t c2_insn; /* MPU instruction cacheable bits. */ 301 union { /* MMU domain access control register 302 * MPU write buffer control. 303 */ 304 struct { 305 uint64_t dacr_ns; 306 uint64_t dacr_s; 307 }; 308 struct { 309 uint64_t dacr32_el2; 310 }; 311 }; 312 uint32_t pmsav5_data_ap; /* PMSAv5 MPU data access permissions */ 313 uint32_t pmsav5_insn_ap; /* PMSAv5 MPU insn access permissions */ 314 uint64_t hcr_el2; /* Hypervisor configuration register */ 315 uint64_t scr_el3; /* Secure configuration register. */ 316 union { /* Fault status registers. */ 317 struct { 318 uint64_t ifsr_ns; 319 uint64_t ifsr_s; 320 }; 321 struct { 322 uint64_t ifsr32_el2; 323 }; 324 }; 325 union { 326 struct { 327 uint64_t _unused_dfsr; 328 uint64_t dfsr_ns; 329 uint64_t hsr; 330 uint64_t dfsr_s; 331 }; 332 uint64_t esr_el[4]; 333 }; 334 uint32_t c6_region[8]; /* MPU base/size registers. */ 335 union { /* Fault address registers. */ 336 struct { 337 uint64_t _unused_far0; 338 #ifdef HOST_WORDS_BIGENDIAN 339 uint32_t ifar_ns; 340 uint32_t dfar_ns; 341 uint32_t ifar_s; 342 uint32_t dfar_s; 343 #else 344 uint32_t dfar_ns; 345 uint32_t ifar_ns; 346 uint32_t dfar_s; 347 uint32_t ifar_s; 348 #endif 349 uint64_t _unused_far3; 350 }; 351 uint64_t far_el[4]; 352 }; 353 uint64_t hpfar_el2; 354 uint64_t hstr_el2; 355 union { /* Translation result. */ 356 struct { 357 uint64_t _unused_par_0; 358 uint64_t par_ns; 359 uint64_t _unused_par_1; 360 uint64_t par_s; 361 }; 362 uint64_t par_el[4]; 363 }; 364 365 uint32_t c9_insn; /* Cache lockdown registers. */ 366 uint32_t c9_data; 367 uint64_t c9_pmcr; /* performance monitor control register */ 368 uint64_t c9_pmcnten; /* perf monitor counter enables */ 369 uint32_t c9_pmovsr; /* perf monitor overflow status */ 370 uint32_t c9_pmuserenr; /* perf monitor user enable */ 371 uint64_t c9_pmselr; /* perf monitor counter selection register */ 372 uint64_t c9_pminten; /* perf monitor interrupt enables */ 373 union { /* Memory attribute redirection */ 374 struct { 375 #ifdef HOST_WORDS_BIGENDIAN 376 uint64_t _unused_mair_0; 377 uint32_t mair1_ns; 378 uint32_t mair0_ns; 379 uint64_t _unused_mair_1; 380 uint32_t mair1_s; 381 uint32_t mair0_s; 382 #else 383 uint64_t _unused_mair_0; 384 uint32_t mair0_ns; 385 uint32_t mair1_ns; 386 uint64_t _unused_mair_1; 387 uint32_t mair0_s; 388 uint32_t mair1_s; 389 #endif 390 }; 391 uint64_t mair_el[4]; 392 }; 393 union { /* vector base address register */ 394 struct { 395 uint64_t _unused_vbar; 396 uint64_t vbar_ns; 397 uint64_t hvbar; 398 uint64_t vbar_s; 399 }; 400 uint64_t vbar_el[4]; 401 }; 402 uint32_t mvbar; /* (monitor) vector base address register */ 403 struct { /* FCSE PID. */ 404 uint32_t fcseidr_ns; 405 uint32_t fcseidr_s; 406 }; 407 union { /* Context ID. */ 408 struct { 409 uint64_t _unused_contextidr_0; 410 uint64_t contextidr_ns; 411 uint64_t _unused_contextidr_1; 412 uint64_t contextidr_s; 413 }; 414 uint64_t contextidr_el[4]; 415 }; 416 union { /* User RW Thread register. */ 417 struct { 418 uint64_t tpidrurw_ns; 419 uint64_t tpidrprw_ns; 420 uint64_t htpidr; 421 uint64_t _tpidr_el3; 422 }; 423 uint64_t tpidr_el[4]; 424 }; 425 /* The secure banks of these registers don't map anywhere */ 426 uint64_t tpidrurw_s; 427 uint64_t tpidrprw_s; 428 uint64_t tpidruro_s; 429 430 union { /* User RO Thread register. */ 431 uint64_t tpidruro_ns; 432 uint64_t tpidrro_el[1]; 433 }; 434 uint64_t c14_cntfrq; /* Counter Frequency register */ 435 uint64_t c14_cntkctl; /* Timer Control register */ 436 uint32_t cnthctl_el2; /* Counter/Timer Hyp Control register */ 437 uint64_t cntvoff_el2; /* Counter Virtual Offset register */ 438 ARMGenericTimer c14_timer[NUM_GTIMERS]; 439 uint32_t c15_cpar; /* XScale Coprocessor Access Register */ 440 uint32_t c15_ticonfig; /* TI925T configuration byte. */ 441 uint32_t c15_i_max; /* Maximum D-cache dirty line index. */ 442 uint32_t c15_i_min; /* Minimum D-cache dirty line index. */ 443 uint32_t c15_threadid; /* TI debugger thread-ID. */ 444 uint32_t c15_config_base_address; /* SCU base address. */ 445 uint32_t c15_diagnostic; /* diagnostic register */ 446 uint32_t c15_power_diagnostic; 447 uint32_t c15_power_control; /* power control */ 448 uint64_t dbgbvr[16]; /* breakpoint value registers */ 449 uint64_t dbgbcr[16]; /* breakpoint control registers */ 450 uint64_t dbgwvr[16]; /* watchpoint value registers */ 451 uint64_t dbgwcr[16]; /* watchpoint control registers */ 452 uint64_t mdscr_el1; 453 uint64_t oslsr_el1; /* OS Lock Status */ 454 uint64_t mdcr_el2; 455 uint64_t mdcr_el3; 456 /* If the counter is enabled, this stores the last time the counter 457 * was reset. Otherwise it stores the counter value 458 */ 459 uint64_t c15_ccnt; 460 uint64_t pmccfiltr_el0; /* Performance Monitor Filter Register */ 461 uint64_t vpidr_el2; /* Virtualization Processor ID Register */ 462 uint64_t vmpidr_el2; /* Virtualization Multiprocessor ID Register */ 463 } cp15; 464 465 struct { 466 /* M profile has up to 4 stack pointers: 467 * a Main Stack Pointer and a Process Stack Pointer for each 468 * of the Secure and Non-Secure states. (If the CPU doesn't support 469 * the security extension then it has only two SPs.) 470 * In QEMU we always store the currently active SP in regs[13], 471 * and the non-active SP for the current security state in 472 * v7m.other_sp. The stack pointers for the inactive security state 473 * are stored in other_ss_msp and other_ss_psp. 474 * switch_v7m_security_state() is responsible for rearranging them 475 * when we change security state. 476 */ 477 uint32_t other_sp; 478 uint32_t other_ss_msp; 479 uint32_t other_ss_psp; 480 uint32_t vecbase[M_REG_NUM_BANKS]; 481 uint32_t basepri[M_REG_NUM_BANKS]; 482 uint32_t control[M_REG_NUM_BANKS]; 483 uint32_t ccr[M_REG_NUM_BANKS]; /* Configuration and Control */ 484 uint32_t cfsr[M_REG_NUM_BANKS]; /* Configurable Fault Status */ 485 uint32_t hfsr; /* HardFault Status */ 486 uint32_t dfsr; /* Debug Fault Status Register */ 487 uint32_t sfsr; /* Secure Fault Status Register */ 488 uint32_t mmfar[M_REG_NUM_BANKS]; /* MemManage Fault Address */ 489 uint32_t bfar; /* BusFault Address */ 490 uint32_t sfar; /* Secure Fault Address Register */ 491 unsigned mpu_ctrl[M_REG_NUM_BANKS]; /* MPU_CTRL */ 492 int exception; 493 uint32_t primask[M_REG_NUM_BANKS]; 494 uint32_t faultmask[M_REG_NUM_BANKS]; 495 uint32_t aircr; /* only holds r/w state if security extn implemented */ 496 uint32_t secure; /* Is CPU in Secure state? (not guest visible) */ 497 uint32_t csselr[M_REG_NUM_BANKS]; 498 uint32_t scr[M_REG_NUM_BANKS]; 499 uint32_t msplim[M_REG_NUM_BANKS]; 500 uint32_t psplim[M_REG_NUM_BANKS]; 501 } v7m; 502 503 /* Information associated with an exception about to be taken: 504 * code which raises an exception must set cs->exception_index and 505 * the relevant parts of this structure; the cpu_do_interrupt function 506 * will then set the guest-visible registers as part of the exception 507 * entry process. 508 */ 509 struct { 510 uint32_t syndrome; /* AArch64 format syndrome register */ 511 uint32_t fsr; /* AArch32 format fault status register info */ 512 uint64_t vaddress; /* virtual addr associated with exception, if any */ 513 uint32_t target_el; /* EL the exception should be targeted for */ 514 /* If we implement EL2 we will also need to store information 515 * about the intermediate physical address for stage 2 faults. 516 */ 517 } exception; 518 519 /* Thumb-2 EE state. */ 520 uint32_t teecr; 521 uint32_t teehbr; 522 523 /* VFP coprocessor state. */ 524 struct { 525 ARMVectorReg zregs[32]; 526 527 #ifdef TARGET_AARCH64 528 /* Store FFR as pregs[16] to make it easier to treat as any other. */ 529 ARMPredicateReg pregs[17]; 530 #endif 531 532 uint32_t xregs[16]; 533 /* We store these fpcsr fields separately for convenience. */ 534 int vec_len; 535 int vec_stride; 536 537 /* scratch space when Tn are not sufficient. */ 538 uint32_t scratch[8]; 539 540 /* fp_status is the "normal" fp status. standard_fp_status retains 541 * values corresponding to the ARM "Standard FPSCR Value", ie 542 * default-NaN, flush-to-zero, round-to-nearest and is used by 543 * any operations (generally Neon) which the architecture defines 544 * as controlled by the standard FPSCR value rather than the FPSCR. 545 * 546 * To avoid having to transfer exception bits around, we simply 547 * say that the FPSCR cumulative exception flags are the logical 548 * OR of the flags in the two fp statuses. This relies on the 549 * only thing which needs to read the exception flags being 550 * an explicit FPSCR read. 551 */ 552 float_status fp_status; 553 float_status standard_fp_status; 554 555 /* ZCR_EL[1-3] */ 556 uint64_t zcr_el[4]; 557 } vfp; 558 uint64_t exclusive_addr; 559 uint64_t exclusive_val; 560 uint64_t exclusive_high; 561 562 /* iwMMXt coprocessor state. */ 563 struct { 564 uint64_t regs[16]; 565 uint64_t val; 566 567 uint32_t cregs[16]; 568 } iwmmxt; 569 570 #if defined(CONFIG_USER_ONLY) 571 /* For usermode syscall translation. */ 572 int eabi; 573 #endif 574 575 struct CPUBreakpoint *cpu_breakpoint[16]; 576 struct CPUWatchpoint *cpu_watchpoint[16]; 577 578 /* Fields up to this point are cleared by a CPU reset */ 579 struct {} end_reset_fields; 580 581 CPU_COMMON 582 583 /* Fields after CPU_COMMON are preserved across CPU reset. */ 584 585 /* Internal CPU feature flags. */ 586 uint64_t features; 587 588 /* PMSAv7 MPU */ 589 struct { 590 uint32_t *drbar; 591 uint32_t *drsr; 592 uint32_t *dracr; 593 uint32_t rnr[M_REG_NUM_BANKS]; 594 } pmsav7; 595 596 /* PMSAv8 MPU */ 597 struct { 598 /* The PMSAv8 implementation also shares some PMSAv7 config 599 * and state: 600 * pmsav7.rnr (region number register) 601 * pmsav7_dregion (number of configured regions) 602 */ 603 uint32_t *rbar[M_REG_NUM_BANKS]; 604 uint32_t *rlar[M_REG_NUM_BANKS]; 605 uint32_t mair0[M_REG_NUM_BANKS]; 606 uint32_t mair1[M_REG_NUM_BANKS]; 607 } pmsav8; 608 609 /* v8M SAU */ 610 struct { 611 uint32_t *rbar; 612 uint32_t *rlar; 613 uint32_t rnr; 614 uint32_t ctrl; 615 } sau; 616 617 void *nvic; 618 const struct arm_boot_info *boot_info; 619 /* Store GICv3CPUState to access from this struct */ 620 void *gicv3state; 621 } CPUARMState; 622 623 /** 624 * ARMELChangeHook: 625 * type of a function which can be registered via arm_register_el_change_hook() 626 * to get callbacks when the CPU changes its exception level or mode. 627 */ 628 typedef void ARMELChangeHook(ARMCPU *cpu, void *opaque); 629 630 631 /* These values map onto the return values for 632 * QEMU_PSCI_0_2_FN_AFFINITY_INFO */ 633 typedef enum ARMPSCIState { 634 PSCI_ON = 0, 635 PSCI_OFF = 1, 636 PSCI_ON_PENDING = 2 637 } ARMPSCIState; 638 639 /** 640 * ARMCPU: 641 * @env: #CPUARMState 642 * 643 * An ARM CPU core. 644 */ 645 struct ARMCPU { 646 /*< private >*/ 647 CPUState parent_obj; 648 /*< public >*/ 649 650 CPUARMState env; 651 652 /* Coprocessor information */ 653 GHashTable *cp_regs; 654 /* For marshalling (mostly coprocessor) register state between the 655 * kernel and QEMU (for KVM) and between two QEMUs (for migration), 656 * we use these arrays. 657 */ 658 /* List of register indexes managed via these arrays; (full KVM style 659 * 64 bit indexes, not CPRegInfo 32 bit indexes) 660 */ 661 uint64_t *cpreg_indexes; 662 /* Values of the registers (cpreg_indexes[i]'s value is cpreg_values[i]) */ 663 uint64_t *cpreg_values; 664 /* Length of the indexes, values, reset_values arrays */ 665 int32_t cpreg_array_len; 666 /* These are used only for migration: incoming data arrives in 667 * these fields and is sanity checked in post_load before copying 668 * to the working data structures above. 669 */ 670 uint64_t *cpreg_vmstate_indexes; 671 uint64_t *cpreg_vmstate_values; 672 int32_t cpreg_vmstate_array_len; 673 674 /* Timers used by the generic (architected) timer */ 675 QEMUTimer *gt_timer[NUM_GTIMERS]; 676 /* GPIO outputs for generic timer */ 677 qemu_irq gt_timer_outputs[NUM_GTIMERS]; 678 /* GPIO output for GICv3 maintenance interrupt signal */ 679 qemu_irq gicv3_maintenance_interrupt; 680 /* GPIO output for the PMU interrupt */ 681 qemu_irq pmu_interrupt; 682 683 /* MemoryRegion to use for secure physical accesses */ 684 MemoryRegion *secure_memory; 685 686 /* 'compatible' string for this CPU for Linux device trees */ 687 const char *dtb_compatible; 688 689 /* PSCI version for this CPU 690 * Bits[31:16] = Major Version 691 * Bits[15:0] = Minor Version 692 */ 693 uint32_t psci_version; 694 695 /* Should CPU start in PSCI powered-off state? */ 696 bool start_powered_off; 697 698 /* Current power state, access guarded by BQL */ 699 ARMPSCIState power_state; 700 701 /* CPU has virtualization extension */ 702 bool has_el2; 703 /* CPU has security extension */ 704 bool has_el3; 705 /* CPU has PMU (Performance Monitor Unit) */ 706 bool has_pmu; 707 708 /* CPU has memory protection unit */ 709 bool has_mpu; 710 /* PMSAv7 MPU number of supported regions */ 711 uint32_t pmsav7_dregion; 712 /* v8M SAU number of supported regions */ 713 uint32_t sau_sregion; 714 715 /* PSCI conduit used to invoke PSCI methods 716 * 0 - disabled, 1 - smc, 2 - hvc 717 */ 718 uint32_t psci_conduit; 719 720 /* [QEMU_]KVM_ARM_TARGET_* constant for this CPU, or 721 * QEMU_KVM_ARM_TARGET_NONE if the kernel doesn't support this CPU type. 722 */ 723 uint32_t kvm_target; 724 725 /* KVM init features for this CPU */ 726 uint32_t kvm_init_features[7]; 727 728 /* Uniprocessor system with MP extensions */ 729 bool mp_is_up; 730 731 /* The instance init functions for implementation-specific subclasses 732 * set these fields to specify the implementation-dependent values of 733 * various constant registers and reset values of non-constant 734 * registers. 735 * Some of these might become QOM properties eventually. 736 * Field names match the official register names as defined in the 737 * ARMv7AR ARM Architecture Reference Manual. A reset_ prefix 738 * is used for reset values of non-constant registers; no reset_ 739 * prefix means a constant register. 740 */ 741 uint32_t midr; 742 uint32_t revidr; 743 uint32_t reset_fpsid; 744 uint32_t mvfr0; 745 uint32_t mvfr1; 746 uint32_t mvfr2; 747 uint32_t ctr; 748 uint32_t reset_sctlr; 749 uint32_t id_pfr0; 750 uint32_t id_pfr1; 751 uint32_t id_dfr0; 752 uint32_t pmceid0; 753 uint32_t pmceid1; 754 uint32_t id_afr0; 755 uint32_t id_mmfr0; 756 uint32_t id_mmfr1; 757 uint32_t id_mmfr2; 758 uint32_t id_mmfr3; 759 uint32_t id_mmfr4; 760 uint32_t id_isar0; 761 uint32_t id_isar1; 762 uint32_t id_isar2; 763 uint32_t id_isar3; 764 uint32_t id_isar4; 765 uint32_t id_isar5; 766 uint64_t id_aa64pfr0; 767 uint64_t id_aa64pfr1; 768 uint64_t id_aa64dfr0; 769 uint64_t id_aa64dfr1; 770 uint64_t id_aa64afr0; 771 uint64_t id_aa64afr1; 772 uint64_t id_aa64isar0; 773 uint64_t id_aa64isar1; 774 uint64_t id_aa64mmfr0; 775 uint64_t id_aa64mmfr1; 776 uint32_t dbgdidr; 777 uint32_t clidr; 778 uint64_t mp_affinity; /* MP ID without feature bits */ 779 /* The elements of this array are the CCSIDR values for each cache, 780 * in the order L1DCache, L1ICache, L2DCache, L2ICache, etc. 781 */ 782 uint32_t ccsidr[16]; 783 uint64_t reset_cbar; 784 uint32_t reset_auxcr; 785 bool reset_hivecs; 786 /* DCZ blocksize, in log_2(words), ie low 4 bits of DCZID_EL0 */ 787 uint32_t dcz_blocksize; 788 uint64_t rvbar; 789 790 /* Configurable aspects of GIC cpu interface (which is part of the CPU) */ 791 int gic_num_lrs; /* number of list registers */ 792 int gic_vpribits; /* number of virtual priority bits */ 793 int gic_vprebits; /* number of virtual preemption bits */ 794 795 /* Whether the cfgend input is high (i.e. this CPU should reset into 796 * big-endian mode). This setting isn't used directly: instead it modifies 797 * the reset_sctlr value to have SCTLR_B or SCTLR_EE set, depending on the 798 * architecture version. 799 */ 800 bool cfgend; 801 802 ARMELChangeHook *el_change_hook; 803 void *el_change_hook_opaque; 804 805 int32_t node_id; /* NUMA node this CPU belongs to */ 806 807 /* Used to synchronize KVM and QEMU in-kernel device levels */ 808 uint8_t device_irq_level; 809 }; 810 811 static inline ARMCPU *arm_env_get_cpu(CPUARMState *env) 812 { 813 return container_of(env, ARMCPU, env); 814 } 815 816 uint64_t arm_cpu_mp_affinity(int idx, uint8_t clustersz); 817 818 #define ENV_GET_CPU(e) CPU(arm_env_get_cpu(e)) 819 820 #define ENV_OFFSET offsetof(ARMCPU, env) 821 822 #ifndef CONFIG_USER_ONLY 823 extern const struct VMStateDescription vmstate_arm_cpu; 824 #endif 825 826 void arm_cpu_do_interrupt(CPUState *cpu); 827 void arm_v7m_cpu_do_interrupt(CPUState *cpu); 828 bool arm_cpu_exec_interrupt(CPUState *cpu, int int_req); 829 830 void arm_cpu_dump_state(CPUState *cs, FILE *f, fprintf_function cpu_fprintf, 831 int flags); 832 833 hwaddr arm_cpu_get_phys_page_attrs_debug(CPUState *cpu, vaddr addr, 834 MemTxAttrs *attrs); 835 836 int arm_cpu_gdb_read_register(CPUState *cpu, uint8_t *buf, int reg); 837 int arm_cpu_gdb_write_register(CPUState *cpu, uint8_t *buf, int reg); 838 839 int arm_cpu_write_elf64_note(WriteCoreDumpFunction f, CPUState *cs, 840 int cpuid, void *opaque); 841 int arm_cpu_write_elf32_note(WriteCoreDumpFunction f, CPUState *cs, 842 int cpuid, void *opaque); 843 844 #ifdef TARGET_AARCH64 845 int aarch64_cpu_gdb_read_register(CPUState *cpu, uint8_t *buf, int reg); 846 int aarch64_cpu_gdb_write_register(CPUState *cpu, uint8_t *buf, int reg); 847 #endif 848 849 target_ulong do_arm_semihosting(CPUARMState *env); 850 void aarch64_sync_32_to_64(CPUARMState *env); 851 void aarch64_sync_64_to_32(CPUARMState *env); 852 853 static inline bool is_a64(CPUARMState *env) 854 { 855 return env->aarch64; 856 } 857 858 /* you can call this signal handler from your SIGBUS and SIGSEGV 859 signal handlers to inform the virtual CPU of exceptions. non zero 860 is returned if the signal was handled by the virtual CPU. */ 861 int cpu_arm_signal_handler(int host_signum, void *pinfo, 862 void *puc); 863 864 /** 865 * pmccntr_sync 866 * @env: CPUARMState 867 * 868 * Synchronises the counter in the PMCCNTR. This must always be called twice, 869 * once before any action that might affect the timer and again afterwards. 870 * The function is used to swap the state of the register if required. 871 * This only happens when not in user mode (!CONFIG_USER_ONLY) 872 */ 873 void pmccntr_sync(CPUARMState *env); 874 875 /* SCTLR bit meanings. Several bits have been reused in newer 876 * versions of the architecture; in that case we define constants 877 * for both old and new bit meanings. Code which tests against those 878 * bits should probably check or otherwise arrange that the CPU 879 * is the architectural version it expects. 880 */ 881 #define SCTLR_M (1U << 0) 882 #define SCTLR_A (1U << 1) 883 #define SCTLR_C (1U << 2) 884 #define SCTLR_W (1U << 3) /* up to v6; RAO in v7 */ 885 #define SCTLR_SA (1U << 3) 886 #define SCTLR_P (1U << 4) /* up to v5; RAO in v6 and v7 */ 887 #define SCTLR_SA0 (1U << 4) /* v8 onward, AArch64 only */ 888 #define SCTLR_D (1U << 5) /* up to v5; RAO in v6 */ 889 #define SCTLR_CP15BEN (1U << 5) /* v7 onward */ 890 #define SCTLR_L (1U << 6) /* up to v5; RAO in v6 and v7; RAZ in v8 */ 891 #define SCTLR_B (1U << 7) /* up to v6; RAZ in v7 */ 892 #define SCTLR_ITD (1U << 7) /* v8 onward */ 893 #define SCTLR_S (1U << 8) /* up to v6; RAZ in v7 */ 894 #define SCTLR_SED (1U << 8) /* v8 onward */ 895 #define SCTLR_R (1U << 9) /* up to v6; RAZ in v7 */ 896 #define SCTLR_UMA (1U << 9) /* v8 onward, AArch64 only */ 897 #define SCTLR_F (1U << 10) /* up to v6 */ 898 #define SCTLR_SW (1U << 10) /* v7 onward */ 899 #define SCTLR_Z (1U << 11) 900 #define SCTLR_I (1U << 12) 901 #define SCTLR_V (1U << 13) 902 #define SCTLR_RR (1U << 14) /* up to v7 */ 903 #define SCTLR_DZE (1U << 14) /* v8 onward, AArch64 only */ 904 #define SCTLR_L4 (1U << 15) /* up to v6; RAZ in v7 */ 905 #define SCTLR_UCT (1U << 15) /* v8 onward, AArch64 only */ 906 #define SCTLR_DT (1U << 16) /* up to ??, RAO in v6 and v7 */ 907 #define SCTLR_nTWI (1U << 16) /* v8 onward */ 908 #define SCTLR_HA (1U << 17) 909 #define SCTLR_BR (1U << 17) /* PMSA only */ 910 #define SCTLR_IT (1U << 18) /* up to ??, RAO in v6 and v7 */ 911 #define SCTLR_nTWE (1U << 18) /* v8 onward */ 912 #define SCTLR_WXN (1U << 19) 913 #define SCTLR_ST (1U << 20) /* up to ??, RAZ in v6 */ 914 #define SCTLR_UWXN (1U << 20) /* v7 onward */ 915 #define SCTLR_FI (1U << 21) 916 #define SCTLR_U (1U << 22) 917 #define SCTLR_XP (1U << 23) /* up to v6; v7 onward RAO */ 918 #define SCTLR_VE (1U << 24) /* up to v7 */ 919 #define SCTLR_E0E (1U << 24) /* v8 onward, AArch64 only */ 920 #define SCTLR_EE (1U << 25) 921 #define SCTLR_L2 (1U << 26) /* up to v6, RAZ in v7 */ 922 #define SCTLR_UCI (1U << 26) /* v8 onward, AArch64 only */ 923 #define SCTLR_NMFI (1U << 27) 924 #define SCTLR_TRE (1U << 28) 925 #define SCTLR_AFE (1U << 29) 926 #define SCTLR_TE (1U << 30) 927 928 #define CPTR_TCPAC (1U << 31) 929 #define CPTR_TTA (1U << 20) 930 #define CPTR_TFP (1U << 10) 931 #define CPTR_TZ (1U << 8) /* CPTR_EL2 */ 932 #define CPTR_EZ (1U << 8) /* CPTR_EL3 */ 933 934 #define MDCR_EPMAD (1U << 21) 935 #define MDCR_EDAD (1U << 20) 936 #define MDCR_SPME (1U << 17) 937 #define MDCR_SDD (1U << 16) 938 #define MDCR_SPD (3U << 14) 939 #define MDCR_TDRA (1U << 11) 940 #define MDCR_TDOSA (1U << 10) 941 #define MDCR_TDA (1U << 9) 942 #define MDCR_TDE (1U << 8) 943 #define MDCR_HPME (1U << 7) 944 #define MDCR_TPM (1U << 6) 945 #define MDCR_TPMCR (1U << 5) 946 947 /* Not all of the MDCR_EL3 bits are present in the 32-bit SDCR */ 948 #define SDCR_VALID_MASK (MDCR_EPMAD | MDCR_EDAD | MDCR_SPME | MDCR_SPD) 949 950 #define CPSR_M (0x1fU) 951 #define CPSR_T (1U << 5) 952 #define CPSR_F (1U << 6) 953 #define CPSR_I (1U << 7) 954 #define CPSR_A (1U << 8) 955 #define CPSR_E (1U << 9) 956 #define CPSR_IT_2_7 (0xfc00U) 957 #define CPSR_GE (0xfU << 16) 958 #define CPSR_IL (1U << 20) 959 /* Note that the RESERVED bits include bit 21, which is PSTATE_SS in 960 * an AArch64 SPSR but RES0 in AArch32 SPSR and CPSR. In QEMU we use 961 * env->uncached_cpsr bit 21 to store PSTATE.SS when executing in AArch32, 962 * where it is live state but not accessible to the AArch32 code. 963 */ 964 #define CPSR_RESERVED (0x7U << 21) 965 #define CPSR_J (1U << 24) 966 #define CPSR_IT_0_1 (3U << 25) 967 #define CPSR_Q (1U << 27) 968 #define CPSR_V (1U << 28) 969 #define CPSR_C (1U << 29) 970 #define CPSR_Z (1U << 30) 971 #define CPSR_N (1U << 31) 972 #define CPSR_NZCV (CPSR_N | CPSR_Z | CPSR_C | CPSR_V) 973 #define CPSR_AIF (CPSR_A | CPSR_I | CPSR_F) 974 975 #define CPSR_IT (CPSR_IT_0_1 | CPSR_IT_2_7) 976 #define CACHED_CPSR_BITS (CPSR_T | CPSR_AIF | CPSR_GE | CPSR_IT | CPSR_Q \ 977 | CPSR_NZCV) 978 /* Bits writable in user mode. */ 979 #define CPSR_USER (CPSR_NZCV | CPSR_Q | CPSR_GE) 980 /* Execution state bits. MRS read as zero, MSR writes ignored. */ 981 #define CPSR_EXEC (CPSR_T | CPSR_IT | CPSR_J | CPSR_IL) 982 /* Mask of bits which may be set by exception return copying them from SPSR */ 983 #define CPSR_ERET_MASK (~CPSR_RESERVED) 984 985 /* Bit definitions for M profile XPSR. Most are the same as CPSR. */ 986 #define XPSR_EXCP 0x1ffU 987 #define XPSR_SPREALIGN (1U << 9) /* Only set in exception stack frames */ 988 #define XPSR_IT_2_7 CPSR_IT_2_7 989 #define XPSR_GE CPSR_GE 990 #define XPSR_SFPA (1U << 20) /* Only set in exception stack frames */ 991 #define XPSR_T (1U << 24) /* Not the same as CPSR_T ! */ 992 #define XPSR_IT_0_1 CPSR_IT_0_1 993 #define XPSR_Q CPSR_Q 994 #define XPSR_V CPSR_V 995 #define XPSR_C CPSR_C 996 #define XPSR_Z CPSR_Z 997 #define XPSR_N CPSR_N 998 #define XPSR_NZCV CPSR_NZCV 999 #define XPSR_IT CPSR_IT 1000 1001 #define TTBCR_N (7U << 0) /* TTBCR.EAE==0 */ 1002 #define TTBCR_T0SZ (7U << 0) /* TTBCR.EAE==1 */ 1003 #define TTBCR_PD0 (1U << 4) 1004 #define TTBCR_PD1 (1U << 5) 1005 #define TTBCR_EPD0 (1U << 7) 1006 #define TTBCR_IRGN0 (3U << 8) 1007 #define TTBCR_ORGN0 (3U << 10) 1008 #define TTBCR_SH0 (3U << 12) 1009 #define TTBCR_T1SZ (3U << 16) 1010 #define TTBCR_A1 (1U << 22) 1011 #define TTBCR_EPD1 (1U << 23) 1012 #define TTBCR_IRGN1 (3U << 24) 1013 #define TTBCR_ORGN1 (3U << 26) 1014 #define TTBCR_SH1 (1U << 28) 1015 #define TTBCR_EAE (1U << 31) 1016 1017 /* Bit definitions for ARMv8 SPSR (PSTATE) format. 1018 * Only these are valid when in AArch64 mode; in 1019 * AArch32 mode SPSRs are basically CPSR-format. 1020 */ 1021 #define PSTATE_SP (1U) 1022 #define PSTATE_M (0xFU) 1023 #define PSTATE_nRW (1U << 4) 1024 #define PSTATE_F (1U << 6) 1025 #define PSTATE_I (1U << 7) 1026 #define PSTATE_A (1U << 8) 1027 #define PSTATE_D (1U << 9) 1028 #define PSTATE_IL (1U << 20) 1029 #define PSTATE_SS (1U << 21) 1030 #define PSTATE_V (1U << 28) 1031 #define PSTATE_C (1U << 29) 1032 #define PSTATE_Z (1U << 30) 1033 #define PSTATE_N (1U << 31) 1034 #define PSTATE_NZCV (PSTATE_N | PSTATE_Z | PSTATE_C | PSTATE_V) 1035 #define PSTATE_DAIF (PSTATE_D | PSTATE_A | PSTATE_I | PSTATE_F) 1036 #define CACHED_PSTATE_BITS (PSTATE_NZCV | PSTATE_DAIF) 1037 /* Mode values for AArch64 */ 1038 #define PSTATE_MODE_EL3h 13 1039 #define PSTATE_MODE_EL3t 12 1040 #define PSTATE_MODE_EL2h 9 1041 #define PSTATE_MODE_EL2t 8 1042 #define PSTATE_MODE_EL1h 5 1043 #define PSTATE_MODE_EL1t 4 1044 #define PSTATE_MODE_EL0t 0 1045 1046 /* Write a new value to v7m.exception, thus transitioning into or out 1047 * of Handler mode; this may result in a change of active stack pointer. 1048 */ 1049 void write_v7m_exception(CPUARMState *env, uint32_t new_exc); 1050 1051 /* Map EL and handler into a PSTATE_MODE. */ 1052 static inline unsigned int aarch64_pstate_mode(unsigned int el, bool handler) 1053 { 1054 return (el << 2) | handler; 1055 } 1056 1057 /* Return the current PSTATE value. For the moment we don't support 32<->64 bit 1058 * interprocessing, so we don't attempt to sync with the cpsr state used by 1059 * the 32 bit decoder. 1060 */ 1061 static inline uint32_t pstate_read(CPUARMState *env) 1062 { 1063 int ZF; 1064 1065 ZF = (env->ZF == 0); 1066 return (env->NF & 0x80000000) | (ZF << 30) 1067 | (env->CF << 29) | ((env->VF & 0x80000000) >> 3) 1068 | env->pstate | env->daif; 1069 } 1070 1071 static inline void pstate_write(CPUARMState *env, uint32_t val) 1072 { 1073 env->ZF = (~val) & PSTATE_Z; 1074 env->NF = val; 1075 env->CF = (val >> 29) & 1; 1076 env->VF = (val << 3) & 0x80000000; 1077 env->daif = val & PSTATE_DAIF; 1078 env->pstate = val & ~CACHED_PSTATE_BITS; 1079 } 1080 1081 /* Return the current CPSR value. */ 1082 uint32_t cpsr_read(CPUARMState *env); 1083 1084 typedef enum CPSRWriteType { 1085 CPSRWriteByInstr = 0, /* from guest MSR or CPS */ 1086 CPSRWriteExceptionReturn = 1, /* from guest exception return insn */ 1087 CPSRWriteRaw = 2, /* trust values, do not switch reg banks */ 1088 CPSRWriteByGDBStub = 3, /* from the GDB stub */ 1089 } CPSRWriteType; 1090 1091 /* Set the CPSR. Note that some bits of mask must be all-set or all-clear.*/ 1092 void cpsr_write(CPUARMState *env, uint32_t val, uint32_t mask, 1093 CPSRWriteType write_type); 1094 1095 /* Return the current xPSR value. */ 1096 static inline uint32_t xpsr_read(CPUARMState *env) 1097 { 1098 int ZF; 1099 ZF = (env->ZF == 0); 1100 return (env->NF & 0x80000000) | (ZF << 30) 1101 | (env->CF << 29) | ((env->VF & 0x80000000) >> 3) | (env->QF << 27) 1102 | (env->thumb << 24) | ((env->condexec_bits & 3) << 25) 1103 | ((env->condexec_bits & 0xfc) << 8) 1104 | env->v7m.exception; 1105 } 1106 1107 /* Set the xPSR. Note that some bits of mask must be all-set or all-clear. */ 1108 static inline void xpsr_write(CPUARMState *env, uint32_t val, uint32_t mask) 1109 { 1110 if (mask & XPSR_NZCV) { 1111 env->ZF = (~val) & XPSR_Z; 1112 env->NF = val; 1113 env->CF = (val >> 29) & 1; 1114 env->VF = (val << 3) & 0x80000000; 1115 } 1116 if (mask & XPSR_Q) { 1117 env->QF = ((val & XPSR_Q) != 0); 1118 } 1119 if (mask & XPSR_T) { 1120 env->thumb = ((val & XPSR_T) != 0); 1121 } 1122 if (mask & XPSR_IT_0_1) { 1123 env->condexec_bits &= ~3; 1124 env->condexec_bits |= (val >> 25) & 3; 1125 } 1126 if (mask & XPSR_IT_2_7) { 1127 env->condexec_bits &= 3; 1128 env->condexec_bits |= (val >> 8) & 0xfc; 1129 } 1130 if (mask & XPSR_EXCP) { 1131 /* Note that this only happens on exception exit */ 1132 write_v7m_exception(env, val & XPSR_EXCP); 1133 } 1134 } 1135 1136 #define HCR_VM (1ULL << 0) 1137 #define HCR_SWIO (1ULL << 1) 1138 #define HCR_PTW (1ULL << 2) 1139 #define HCR_FMO (1ULL << 3) 1140 #define HCR_IMO (1ULL << 4) 1141 #define HCR_AMO (1ULL << 5) 1142 #define HCR_VF (1ULL << 6) 1143 #define HCR_VI (1ULL << 7) 1144 #define HCR_VSE (1ULL << 8) 1145 #define HCR_FB (1ULL << 9) 1146 #define HCR_BSU_MASK (3ULL << 10) 1147 #define HCR_DC (1ULL << 12) 1148 #define HCR_TWI (1ULL << 13) 1149 #define HCR_TWE (1ULL << 14) 1150 #define HCR_TID0 (1ULL << 15) 1151 #define HCR_TID1 (1ULL << 16) 1152 #define HCR_TID2 (1ULL << 17) 1153 #define HCR_TID3 (1ULL << 18) 1154 #define HCR_TSC (1ULL << 19) 1155 #define HCR_TIDCP (1ULL << 20) 1156 #define HCR_TACR (1ULL << 21) 1157 #define HCR_TSW (1ULL << 22) 1158 #define HCR_TPC (1ULL << 23) 1159 #define HCR_TPU (1ULL << 24) 1160 #define HCR_TTLB (1ULL << 25) 1161 #define HCR_TVM (1ULL << 26) 1162 #define HCR_TGE (1ULL << 27) 1163 #define HCR_TDZ (1ULL << 28) 1164 #define HCR_HCD (1ULL << 29) 1165 #define HCR_TRVM (1ULL << 30) 1166 #define HCR_RW (1ULL << 31) 1167 #define HCR_CD (1ULL << 32) 1168 #define HCR_ID (1ULL << 33) 1169 #define HCR_MASK ((1ULL << 34) - 1) 1170 1171 #define SCR_NS (1U << 0) 1172 #define SCR_IRQ (1U << 1) 1173 #define SCR_FIQ (1U << 2) 1174 #define SCR_EA (1U << 3) 1175 #define SCR_FW (1U << 4) 1176 #define SCR_AW (1U << 5) 1177 #define SCR_NET (1U << 6) 1178 #define SCR_SMD (1U << 7) 1179 #define SCR_HCE (1U << 8) 1180 #define SCR_SIF (1U << 9) 1181 #define SCR_RW (1U << 10) 1182 #define SCR_ST (1U << 11) 1183 #define SCR_TWI (1U << 12) 1184 #define SCR_TWE (1U << 13) 1185 #define SCR_AARCH32_MASK (0x3fff & ~(SCR_RW | SCR_ST)) 1186 #define SCR_AARCH64_MASK (0x3fff & ~SCR_NET) 1187 1188 /* Return the current FPSCR value. */ 1189 uint32_t vfp_get_fpscr(CPUARMState *env); 1190 void vfp_set_fpscr(CPUARMState *env, uint32_t val); 1191 1192 /* For A64 the FPSCR is split into two logically distinct registers, 1193 * FPCR and FPSR. However since they still use non-overlapping bits 1194 * we store the underlying state in fpscr and just mask on read/write. 1195 */ 1196 #define FPSR_MASK 0xf800009f 1197 #define FPCR_MASK 0x07f79f00 1198 static inline uint32_t vfp_get_fpsr(CPUARMState *env) 1199 { 1200 return vfp_get_fpscr(env) & FPSR_MASK; 1201 } 1202 1203 static inline void vfp_set_fpsr(CPUARMState *env, uint32_t val) 1204 { 1205 uint32_t new_fpscr = (vfp_get_fpscr(env) & ~FPSR_MASK) | (val & FPSR_MASK); 1206 vfp_set_fpscr(env, new_fpscr); 1207 } 1208 1209 static inline uint32_t vfp_get_fpcr(CPUARMState *env) 1210 { 1211 return vfp_get_fpscr(env) & FPCR_MASK; 1212 } 1213 1214 static inline void vfp_set_fpcr(CPUARMState *env, uint32_t val) 1215 { 1216 uint32_t new_fpscr = (vfp_get_fpscr(env) & ~FPCR_MASK) | (val & FPCR_MASK); 1217 vfp_set_fpscr(env, new_fpscr); 1218 } 1219 1220 enum arm_cpu_mode { 1221 ARM_CPU_MODE_USR = 0x10, 1222 ARM_CPU_MODE_FIQ = 0x11, 1223 ARM_CPU_MODE_IRQ = 0x12, 1224 ARM_CPU_MODE_SVC = 0x13, 1225 ARM_CPU_MODE_MON = 0x16, 1226 ARM_CPU_MODE_ABT = 0x17, 1227 ARM_CPU_MODE_HYP = 0x1a, 1228 ARM_CPU_MODE_UND = 0x1b, 1229 ARM_CPU_MODE_SYS = 0x1f 1230 }; 1231 1232 /* VFP system registers. */ 1233 #define ARM_VFP_FPSID 0 1234 #define ARM_VFP_FPSCR 1 1235 #define ARM_VFP_MVFR2 5 1236 #define ARM_VFP_MVFR1 6 1237 #define ARM_VFP_MVFR0 7 1238 #define ARM_VFP_FPEXC 8 1239 #define ARM_VFP_FPINST 9 1240 #define ARM_VFP_FPINST2 10 1241 1242 /* iwMMXt coprocessor control registers. */ 1243 #define ARM_IWMMXT_wCID 0 1244 #define ARM_IWMMXT_wCon 1 1245 #define ARM_IWMMXT_wCSSF 2 1246 #define ARM_IWMMXT_wCASF 3 1247 #define ARM_IWMMXT_wCGR0 8 1248 #define ARM_IWMMXT_wCGR1 9 1249 #define ARM_IWMMXT_wCGR2 10 1250 #define ARM_IWMMXT_wCGR3 11 1251 1252 /* V7M CCR bits */ 1253 FIELD(V7M_CCR, NONBASETHRDENA, 0, 1) 1254 FIELD(V7M_CCR, USERSETMPEND, 1, 1) 1255 FIELD(V7M_CCR, UNALIGN_TRP, 3, 1) 1256 FIELD(V7M_CCR, DIV_0_TRP, 4, 1) 1257 FIELD(V7M_CCR, BFHFNMIGN, 8, 1) 1258 FIELD(V7M_CCR, STKALIGN, 9, 1) 1259 FIELD(V7M_CCR, DC, 16, 1) 1260 FIELD(V7M_CCR, IC, 17, 1) 1261 1262 /* V7M SCR bits */ 1263 FIELD(V7M_SCR, SLEEPONEXIT, 1, 1) 1264 FIELD(V7M_SCR, SLEEPDEEP, 2, 1) 1265 FIELD(V7M_SCR, SLEEPDEEPS, 3, 1) 1266 FIELD(V7M_SCR, SEVONPEND, 4, 1) 1267 1268 /* V7M AIRCR bits */ 1269 FIELD(V7M_AIRCR, VECTRESET, 0, 1) 1270 FIELD(V7M_AIRCR, VECTCLRACTIVE, 1, 1) 1271 FIELD(V7M_AIRCR, SYSRESETREQ, 2, 1) 1272 FIELD(V7M_AIRCR, SYSRESETREQS, 3, 1) 1273 FIELD(V7M_AIRCR, PRIGROUP, 8, 3) 1274 FIELD(V7M_AIRCR, BFHFNMINS, 13, 1) 1275 FIELD(V7M_AIRCR, PRIS, 14, 1) 1276 FIELD(V7M_AIRCR, ENDIANNESS, 15, 1) 1277 FIELD(V7M_AIRCR, VECTKEY, 16, 16) 1278 1279 /* V7M CFSR bits for MMFSR */ 1280 FIELD(V7M_CFSR, IACCVIOL, 0, 1) 1281 FIELD(V7M_CFSR, DACCVIOL, 1, 1) 1282 FIELD(V7M_CFSR, MUNSTKERR, 3, 1) 1283 FIELD(V7M_CFSR, MSTKERR, 4, 1) 1284 FIELD(V7M_CFSR, MLSPERR, 5, 1) 1285 FIELD(V7M_CFSR, MMARVALID, 7, 1) 1286 1287 /* V7M CFSR bits for BFSR */ 1288 FIELD(V7M_CFSR, IBUSERR, 8 + 0, 1) 1289 FIELD(V7M_CFSR, PRECISERR, 8 + 1, 1) 1290 FIELD(V7M_CFSR, IMPRECISERR, 8 + 2, 1) 1291 FIELD(V7M_CFSR, UNSTKERR, 8 + 3, 1) 1292 FIELD(V7M_CFSR, STKERR, 8 + 4, 1) 1293 FIELD(V7M_CFSR, LSPERR, 8 + 5, 1) 1294 FIELD(V7M_CFSR, BFARVALID, 8 + 7, 1) 1295 1296 /* V7M CFSR bits for UFSR */ 1297 FIELD(V7M_CFSR, UNDEFINSTR, 16 + 0, 1) 1298 FIELD(V7M_CFSR, INVSTATE, 16 + 1, 1) 1299 FIELD(V7M_CFSR, INVPC, 16 + 2, 1) 1300 FIELD(V7M_CFSR, NOCP, 16 + 3, 1) 1301 FIELD(V7M_CFSR, UNALIGNED, 16 + 8, 1) 1302 FIELD(V7M_CFSR, DIVBYZERO, 16 + 9, 1) 1303 1304 /* V7M CFSR bit masks covering all of the subregister bits */ 1305 FIELD(V7M_CFSR, MMFSR, 0, 8) 1306 FIELD(V7M_CFSR, BFSR, 8, 8) 1307 FIELD(V7M_CFSR, UFSR, 16, 16) 1308 1309 /* V7M HFSR bits */ 1310 FIELD(V7M_HFSR, VECTTBL, 1, 1) 1311 FIELD(V7M_HFSR, FORCED, 30, 1) 1312 FIELD(V7M_HFSR, DEBUGEVT, 31, 1) 1313 1314 /* V7M DFSR bits */ 1315 FIELD(V7M_DFSR, HALTED, 0, 1) 1316 FIELD(V7M_DFSR, BKPT, 1, 1) 1317 FIELD(V7M_DFSR, DWTTRAP, 2, 1) 1318 FIELD(V7M_DFSR, VCATCH, 3, 1) 1319 FIELD(V7M_DFSR, EXTERNAL, 4, 1) 1320 1321 /* V7M SFSR bits */ 1322 FIELD(V7M_SFSR, INVEP, 0, 1) 1323 FIELD(V7M_SFSR, INVIS, 1, 1) 1324 FIELD(V7M_SFSR, INVER, 2, 1) 1325 FIELD(V7M_SFSR, AUVIOL, 3, 1) 1326 FIELD(V7M_SFSR, INVTRAN, 4, 1) 1327 FIELD(V7M_SFSR, LSPERR, 5, 1) 1328 FIELD(V7M_SFSR, SFARVALID, 6, 1) 1329 FIELD(V7M_SFSR, LSERR, 7, 1) 1330 1331 /* v7M MPU_CTRL bits */ 1332 FIELD(V7M_MPU_CTRL, ENABLE, 0, 1) 1333 FIELD(V7M_MPU_CTRL, HFNMIENA, 1, 1) 1334 FIELD(V7M_MPU_CTRL, PRIVDEFENA, 2, 1) 1335 1336 /* v7M CLIDR bits */ 1337 FIELD(V7M_CLIDR, CTYPE_ALL, 0, 21) 1338 FIELD(V7M_CLIDR, LOUIS, 21, 3) 1339 FIELD(V7M_CLIDR, LOC, 24, 3) 1340 FIELD(V7M_CLIDR, LOUU, 27, 3) 1341 FIELD(V7M_CLIDR, ICB, 30, 2) 1342 1343 FIELD(V7M_CSSELR, IND, 0, 1) 1344 FIELD(V7M_CSSELR, LEVEL, 1, 3) 1345 /* We use the combination of InD and Level to index into cpu->ccsidr[]; 1346 * define a mask for this and check that it doesn't permit running off 1347 * the end of the array. 1348 */ 1349 FIELD(V7M_CSSELR, INDEX, 0, 4) 1350 1351 QEMU_BUILD_BUG_ON(ARRAY_SIZE(((ARMCPU *)0)->ccsidr) <= R_V7M_CSSELR_INDEX_MASK); 1352 1353 /* If adding a feature bit which corresponds to a Linux ELF 1354 * HWCAP bit, remember to update the feature-bit-to-hwcap 1355 * mapping in linux-user/elfload.c:get_elf_hwcap(). 1356 */ 1357 enum arm_features { 1358 ARM_FEATURE_VFP, 1359 ARM_FEATURE_AUXCR, /* ARM1026 Auxiliary control register. */ 1360 ARM_FEATURE_XSCALE, /* Intel XScale extensions. */ 1361 ARM_FEATURE_IWMMXT, /* Intel iwMMXt extension. */ 1362 ARM_FEATURE_V6, 1363 ARM_FEATURE_V6K, 1364 ARM_FEATURE_V7, 1365 ARM_FEATURE_THUMB2, 1366 ARM_FEATURE_PMSA, /* no MMU; may have Memory Protection Unit */ 1367 ARM_FEATURE_VFP3, 1368 ARM_FEATURE_VFP_FP16, 1369 ARM_FEATURE_NEON, 1370 ARM_FEATURE_THUMB_DIV, /* divide supported in Thumb encoding */ 1371 ARM_FEATURE_M, /* Microcontroller profile. */ 1372 ARM_FEATURE_OMAPCP, /* OMAP specific CP15 ops handling. */ 1373 ARM_FEATURE_THUMB2EE, 1374 ARM_FEATURE_V7MP, /* v7 Multiprocessing Extensions */ 1375 ARM_FEATURE_V4T, 1376 ARM_FEATURE_V5, 1377 ARM_FEATURE_STRONGARM, 1378 ARM_FEATURE_VAPA, /* cp15 VA to PA lookups */ 1379 ARM_FEATURE_ARM_DIV, /* divide supported in ARM encoding */ 1380 ARM_FEATURE_VFP4, /* VFPv4 (implies that NEON is v2) */ 1381 ARM_FEATURE_GENERIC_TIMER, 1382 ARM_FEATURE_MVFR, /* Media and VFP Feature Registers 0 and 1 */ 1383 ARM_FEATURE_DUMMY_C15_REGS, /* RAZ/WI all of cp15 crn=15 */ 1384 ARM_FEATURE_CACHE_TEST_CLEAN, /* 926/1026 style test-and-clean ops */ 1385 ARM_FEATURE_CACHE_DIRTY_REG, /* 1136/1176 cache dirty status register */ 1386 ARM_FEATURE_CACHE_BLOCK_OPS, /* v6 optional cache block operations */ 1387 ARM_FEATURE_MPIDR, /* has cp15 MPIDR */ 1388 ARM_FEATURE_PXN, /* has Privileged Execute Never bit */ 1389 ARM_FEATURE_LPAE, /* has Large Physical Address Extension */ 1390 ARM_FEATURE_V8, 1391 ARM_FEATURE_AARCH64, /* supports 64 bit mode */ 1392 ARM_FEATURE_V8_AES, /* implements AES part of v8 Crypto Extensions */ 1393 ARM_FEATURE_CBAR, /* has cp15 CBAR */ 1394 ARM_FEATURE_CRC, /* ARMv8 CRC instructions */ 1395 ARM_FEATURE_CBAR_RO, /* has cp15 CBAR and it is read-only */ 1396 ARM_FEATURE_EL2, /* has EL2 Virtualization support */ 1397 ARM_FEATURE_EL3, /* has EL3 Secure monitor support */ 1398 ARM_FEATURE_V8_SHA1, /* implements SHA1 part of v8 Crypto Extensions */ 1399 ARM_FEATURE_V8_SHA256, /* implements SHA256 part of v8 Crypto Extensions */ 1400 ARM_FEATURE_V8_PMULL, /* implements PMULL part of v8 Crypto Extensions */ 1401 ARM_FEATURE_THUMB_DSP, /* DSP insns supported in the Thumb encodings */ 1402 ARM_FEATURE_PMU, /* has PMU support */ 1403 ARM_FEATURE_VBAR, /* has cp15 VBAR */ 1404 ARM_FEATURE_M_SECURITY, /* M profile Security Extension */ 1405 ARM_FEATURE_JAZELLE, /* has (trivial) Jazelle implementation */ 1406 ARM_FEATURE_SVE, /* has Scalable Vector Extension */ 1407 ARM_FEATURE_V8_SHA512, /* implements SHA512 part of v8 Crypto Extensions */ 1408 ARM_FEATURE_V8_SHA3, /* implements SHA3 part of v8 Crypto Extensions */ 1409 ARM_FEATURE_V8_SM3, /* implements SM3 part of v8 Crypto Extensions */ 1410 ARM_FEATURE_V8_SM4, /* implements SM4 part of v8 Crypto Extensions */ 1411 }; 1412 1413 static inline int arm_feature(CPUARMState *env, int feature) 1414 { 1415 return (env->features & (1ULL << feature)) != 0; 1416 } 1417 1418 #if !defined(CONFIG_USER_ONLY) 1419 /* Return true if exception levels below EL3 are in secure state, 1420 * or would be following an exception return to that level. 1421 * Unlike arm_is_secure() (which is always a question about the 1422 * _current_ state of the CPU) this doesn't care about the current 1423 * EL or mode. 1424 */ 1425 static inline bool arm_is_secure_below_el3(CPUARMState *env) 1426 { 1427 if (arm_feature(env, ARM_FEATURE_EL3)) { 1428 return !(env->cp15.scr_el3 & SCR_NS); 1429 } else { 1430 /* If EL3 is not supported then the secure state is implementation 1431 * defined, in which case QEMU defaults to non-secure. 1432 */ 1433 return false; 1434 } 1435 } 1436 1437 /* Return true if the CPU is AArch64 EL3 or AArch32 Mon */ 1438 static inline bool arm_is_el3_or_mon(CPUARMState *env) 1439 { 1440 if (arm_feature(env, ARM_FEATURE_EL3)) { 1441 if (is_a64(env) && extract32(env->pstate, 2, 2) == 3) { 1442 /* CPU currently in AArch64 state and EL3 */ 1443 return true; 1444 } else if (!is_a64(env) && 1445 (env->uncached_cpsr & CPSR_M) == ARM_CPU_MODE_MON) { 1446 /* CPU currently in AArch32 state and monitor mode */ 1447 return true; 1448 } 1449 } 1450 return false; 1451 } 1452 1453 /* Return true if the processor is in secure state */ 1454 static inline bool arm_is_secure(CPUARMState *env) 1455 { 1456 if (arm_is_el3_or_mon(env)) { 1457 return true; 1458 } 1459 return arm_is_secure_below_el3(env); 1460 } 1461 1462 #else 1463 static inline bool arm_is_secure_below_el3(CPUARMState *env) 1464 { 1465 return false; 1466 } 1467 1468 static inline bool arm_is_secure(CPUARMState *env) 1469 { 1470 return false; 1471 } 1472 #endif 1473 1474 /* Return true if the specified exception level is running in AArch64 state. */ 1475 static inline bool arm_el_is_aa64(CPUARMState *env, int el) 1476 { 1477 /* This isn't valid for EL0 (if we're in EL0, is_a64() is what you want, 1478 * and if we're not in EL0 then the state of EL0 isn't well defined.) 1479 */ 1480 assert(el >= 1 && el <= 3); 1481 bool aa64 = arm_feature(env, ARM_FEATURE_AARCH64); 1482 1483 /* The highest exception level is always at the maximum supported 1484 * register width, and then lower levels have a register width controlled 1485 * by bits in the SCR or HCR registers. 1486 */ 1487 if (el == 3) { 1488 return aa64; 1489 } 1490 1491 if (arm_feature(env, ARM_FEATURE_EL3)) { 1492 aa64 = aa64 && (env->cp15.scr_el3 & SCR_RW); 1493 } 1494 1495 if (el == 2) { 1496 return aa64; 1497 } 1498 1499 if (arm_feature(env, ARM_FEATURE_EL2) && !arm_is_secure_below_el3(env)) { 1500 aa64 = aa64 && (env->cp15.hcr_el2 & HCR_RW); 1501 } 1502 1503 return aa64; 1504 } 1505 1506 /* Function for determing whether guest cp register reads and writes should 1507 * access the secure or non-secure bank of a cp register. When EL3 is 1508 * operating in AArch32 state, the NS-bit determines whether the secure 1509 * instance of a cp register should be used. When EL3 is AArch64 (or if 1510 * it doesn't exist at all) then there is no register banking, and all 1511 * accesses are to the non-secure version. 1512 */ 1513 static inline bool access_secure_reg(CPUARMState *env) 1514 { 1515 bool ret = (arm_feature(env, ARM_FEATURE_EL3) && 1516 !arm_el_is_aa64(env, 3) && 1517 !(env->cp15.scr_el3 & SCR_NS)); 1518 1519 return ret; 1520 } 1521 1522 /* Macros for accessing a specified CP register bank */ 1523 #define A32_BANKED_REG_GET(_env, _regname, _secure) \ 1524 ((_secure) ? (_env)->cp15._regname##_s : (_env)->cp15._regname##_ns) 1525 1526 #define A32_BANKED_REG_SET(_env, _regname, _secure, _val) \ 1527 do { \ 1528 if (_secure) { \ 1529 (_env)->cp15._regname##_s = (_val); \ 1530 } else { \ 1531 (_env)->cp15._regname##_ns = (_val); \ 1532 } \ 1533 } while (0) 1534 1535 /* Macros for automatically accessing a specific CP register bank depending on 1536 * the current secure state of the system. These macros are not intended for 1537 * supporting instruction translation reads/writes as these are dependent 1538 * solely on the SCR.NS bit and not the mode. 1539 */ 1540 #define A32_BANKED_CURRENT_REG_GET(_env, _regname) \ 1541 A32_BANKED_REG_GET((_env), _regname, \ 1542 (arm_is_secure(_env) && !arm_el_is_aa64((_env), 3))) 1543 1544 #define A32_BANKED_CURRENT_REG_SET(_env, _regname, _val) \ 1545 A32_BANKED_REG_SET((_env), _regname, \ 1546 (arm_is_secure(_env) && !arm_el_is_aa64((_env), 3)), \ 1547 (_val)) 1548 1549 void arm_cpu_list(FILE *f, fprintf_function cpu_fprintf); 1550 uint32_t arm_phys_excp_target_el(CPUState *cs, uint32_t excp_idx, 1551 uint32_t cur_el, bool secure); 1552 1553 /* Interface between CPU and Interrupt controller. */ 1554 #ifndef CONFIG_USER_ONLY 1555 bool armv7m_nvic_can_take_pending_exception(void *opaque); 1556 #else 1557 static inline bool armv7m_nvic_can_take_pending_exception(void *opaque) 1558 { 1559 return true; 1560 } 1561 #endif 1562 /** 1563 * armv7m_nvic_set_pending: mark the specified exception as pending 1564 * @opaque: the NVIC 1565 * @irq: the exception number to mark pending 1566 * @secure: false for non-banked exceptions or for the nonsecure 1567 * version of a banked exception, true for the secure version of a banked 1568 * exception. 1569 * 1570 * Marks the specified exception as pending. Note that we will assert() 1571 * if @secure is true and @irq does not specify one of the fixed set 1572 * of architecturally banked exceptions. 1573 */ 1574 void armv7m_nvic_set_pending(void *opaque, int irq, bool secure); 1575 /** 1576 * armv7m_nvic_set_pending_derived: mark this derived exception as pending 1577 * @opaque: the NVIC 1578 * @irq: the exception number to mark pending 1579 * @secure: false for non-banked exceptions or for the nonsecure 1580 * version of a banked exception, true for the secure version of a banked 1581 * exception. 1582 * 1583 * Similar to armv7m_nvic_set_pending(), but specifically for derived 1584 * exceptions (exceptions generated in the course of trying to take 1585 * a different exception). 1586 */ 1587 void armv7m_nvic_set_pending_derived(void *opaque, int irq, bool secure); 1588 /** 1589 * armv7m_nvic_get_pending_irq_info: return highest priority pending 1590 * exception, and whether it targets Secure state 1591 * @opaque: the NVIC 1592 * @pirq: set to pending exception number 1593 * @ptargets_secure: set to whether pending exception targets Secure 1594 * 1595 * This function writes the number of the highest priority pending 1596 * exception (the one which would be made active by 1597 * armv7m_nvic_acknowledge_irq()) to @pirq, and sets @ptargets_secure 1598 * to true if the current highest priority pending exception should 1599 * be taken to Secure state, false for NS. 1600 */ 1601 void armv7m_nvic_get_pending_irq_info(void *opaque, int *pirq, 1602 bool *ptargets_secure); 1603 /** 1604 * armv7m_nvic_acknowledge_irq: make highest priority pending exception active 1605 * @opaque: the NVIC 1606 * 1607 * Move the current highest priority pending exception from the pending 1608 * state to the active state, and update v7m.exception to indicate that 1609 * it is the exception currently being handled. 1610 */ 1611 void armv7m_nvic_acknowledge_irq(void *opaque); 1612 /** 1613 * armv7m_nvic_complete_irq: complete specified interrupt or exception 1614 * @opaque: the NVIC 1615 * @irq: the exception number to complete 1616 * @secure: true if this exception was secure 1617 * 1618 * Returns: -1 if the irq was not active 1619 * 1 if completing this irq brought us back to base (no active irqs) 1620 * 0 if there is still an irq active after this one was completed 1621 * (Ignoring -1, this is the same as the RETTOBASE value before completion.) 1622 */ 1623 int armv7m_nvic_complete_irq(void *opaque, int irq, bool secure); 1624 /** 1625 * armv7m_nvic_raw_execution_priority: return the raw execution priority 1626 * @opaque: the NVIC 1627 * 1628 * Returns: the raw execution priority as defined by the v8M architecture. 1629 * This is the execution priority minus the effects of AIRCR.PRIS, 1630 * and minus any PRIMASK/FAULTMASK/BASEPRI priority boosting. 1631 * (v8M ARM ARM I_PKLD.) 1632 */ 1633 int armv7m_nvic_raw_execution_priority(void *opaque); 1634 /** 1635 * armv7m_nvic_neg_prio_requested: return true if the requested execution 1636 * priority is negative for the specified security state. 1637 * @opaque: the NVIC 1638 * @secure: the security state to test 1639 * This corresponds to the pseudocode IsReqExecPriNeg(). 1640 */ 1641 #ifndef CONFIG_USER_ONLY 1642 bool armv7m_nvic_neg_prio_requested(void *opaque, bool secure); 1643 #else 1644 static inline bool armv7m_nvic_neg_prio_requested(void *opaque, bool secure) 1645 { 1646 return false; 1647 } 1648 #endif 1649 1650 /* Interface for defining coprocessor registers. 1651 * Registers are defined in tables of arm_cp_reginfo structs 1652 * which are passed to define_arm_cp_regs(). 1653 */ 1654 1655 /* When looking up a coprocessor register we look for it 1656 * via an integer which encodes all of: 1657 * coprocessor number 1658 * Crn, Crm, opc1, opc2 fields 1659 * 32 or 64 bit register (ie is it accessed via MRC/MCR 1660 * or via MRRC/MCRR?) 1661 * non-secure/secure bank (AArch32 only) 1662 * We allow 4 bits for opc1 because MRRC/MCRR have a 4 bit field. 1663 * (In this case crn and opc2 should be zero.) 1664 * For AArch64, there is no 32/64 bit size distinction; 1665 * instead all registers have a 2 bit op0, 3 bit op1 and op2, 1666 * and 4 bit CRn and CRm. The encoding patterns are chosen 1667 * to be easy to convert to and from the KVM encodings, and also 1668 * so that the hashtable can contain both AArch32 and AArch64 1669 * registers (to allow for interprocessing where we might run 1670 * 32 bit code on a 64 bit core). 1671 */ 1672 /* This bit is private to our hashtable cpreg; in KVM register 1673 * IDs the AArch64/32 distinction is the KVM_REG_ARM/ARM64 1674 * in the upper bits of the 64 bit ID. 1675 */ 1676 #define CP_REG_AA64_SHIFT 28 1677 #define CP_REG_AA64_MASK (1 << CP_REG_AA64_SHIFT) 1678 1679 /* To enable banking of coprocessor registers depending on ns-bit we 1680 * add a bit to distinguish between secure and non-secure cpregs in the 1681 * hashtable. 1682 */ 1683 #define CP_REG_NS_SHIFT 29 1684 #define CP_REG_NS_MASK (1 << CP_REG_NS_SHIFT) 1685 1686 #define ENCODE_CP_REG(cp, is64, ns, crn, crm, opc1, opc2) \ 1687 ((ns) << CP_REG_NS_SHIFT | ((cp) << 16) | ((is64) << 15) | \ 1688 ((crn) << 11) | ((crm) << 7) | ((opc1) << 3) | (opc2)) 1689 1690 #define ENCODE_AA64_CP_REG(cp, crn, crm, op0, op1, op2) \ 1691 (CP_REG_AA64_MASK | \ 1692 ((cp) << CP_REG_ARM_COPROC_SHIFT) | \ 1693 ((op0) << CP_REG_ARM64_SYSREG_OP0_SHIFT) | \ 1694 ((op1) << CP_REG_ARM64_SYSREG_OP1_SHIFT) | \ 1695 ((crn) << CP_REG_ARM64_SYSREG_CRN_SHIFT) | \ 1696 ((crm) << CP_REG_ARM64_SYSREG_CRM_SHIFT) | \ 1697 ((op2) << CP_REG_ARM64_SYSREG_OP2_SHIFT)) 1698 1699 /* Convert a full 64 bit KVM register ID to the truncated 32 bit 1700 * version used as a key for the coprocessor register hashtable 1701 */ 1702 static inline uint32_t kvm_to_cpreg_id(uint64_t kvmid) 1703 { 1704 uint32_t cpregid = kvmid; 1705 if ((kvmid & CP_REG_ARCH_MASK) == CP_REG_ARM64) { 1706 cpregid |= CP_REG_AA64_MASK; 1707 } else { 1708 if ((kvmid & CP_REG_SIZE_MASK) == CP_REG_SIZE_U64) { 1709 cpregid |= (1 << 15); 1710 } 1711 1712 /* KVM is always non-secure so add the NS flag on AArch32 register 1713 * entries. 1714 */ 1715 cpregid |= 1 << CP_REG_NS_SHIFT; 1716 } 1717 return cpregid; 1718 } 1719 1720 /* Convert a truncated 32 bit hashtable key into the full 1721 * 64 bit KVM register ID. 1722 */ 1723 static inline uint64_t cpreg_to_kvm_id(uint32_t cpregid) 1724 { 1725 uint64_t kvmid; 1726 1727 if (cpregid & CP_REG_AA64_MASK) { 1728 kvmid = cpregid & ~CP_REG_AA64_MASK; 1729 kvmid |= CP_REG_SIZE_U64 | CP_REG_ARM64; 1730 } else { 1731 kvmid = cpregid & ~(1 << 15); 1732 if (cpregid & (1 << 15)) { 1733 kvmid |= CP_REG_SIZE_U64 | CP_REG_ARM; 1734 } else { 1735 kvmid |= CP_REG_SIZE_U32 | CP_REG_ARM; 1736 } 1737 } 1738 return kvmid; 1739 } 1740 1741 /* ARMCPRegInfo type field bits. If the SPECIAL bit is set this is a 1742 * special-behaviour cp reg and bits [11..8] indicate what behaviour 1743 * it has. Otherwise it is a simple cp reg, where CONST indicates that 1744 * TCG can assume the value to be constant (ie load at translate time) 1745 * and 64BIT indicates a 64 bit wide coprocessor register. SUPPRESS_TB_END 1746 * indicates that the TB should not be ended after a write to this register 1747 * (the default is that the TB ends after cp writes). OVERRIDE permits 1748 * a register definition to override a previous definition for the 1749 * same (cp, is64, crn, crm, opc1, opc2) tuple: either the new or the 1750 * old must have the OVERRIDE bit set. 1751 * ALIAS indicates that this register is an alias view of some underlying 1752 * state which is also visible via another register, and that the other 1753 * register is handling migration and reset; registers marked ALIAS will not be 1754 * migrated but may have their state set by syncing of register state from KVM. 1755 * NO_RAW indicates that this register has no underlying state and does not 1756 * support raw access for state saving/loading; it will not be used for either 1757 * migration or KVM state synchronization. (Typically this is for "registers" 1758 * which are actually used as instructions for cache maintenance and so on.) 1759 * IO indicates that this register does I/O and therefore its accesses 1760 * need to be surrounded by gen_io_start()/gen_io_end(). In particular, 1761 * registers which implement clocks or timers require this. 1762 */ 1763 #define ARM_CP_SPECIAL 0x0001 1764 #define ARM_CP_CONST 0x0002 1765 #define ARM_CP_64BIT 0x0004 1766 #define ARM_CP_SUPPRESS_TB_END 0x0008 1767 #define ARM_CP_OVERRIDE 0x0010 1768 #define ARM_CP_ALIAS 0x0020 1769 #define ARM_CP_IO 0x0040 1770 #define ARM_CP_NO_RAW 0x0080 1771 #define ARM_CP_NOP (ARM_CP_SPECIAL | 0x0100) 1772 #define ARM_CP_WFI (ARM_CP_SPECIAL | 0x0200) 1773 #define ARM_CP_NZCV (ARM_CP_SPECIAL | 0x0300) 1774 #define ARM_CP_CURRENTEL (ARM_CP_SPECIAL | 0x0400) 1775 #define ARM_CP_DC_ZVA (ARM_CP_SPECIAL | 0x0500) 1776 #define ARM_LAST_SPECIAL ARM_CP_DC_ZVA 1777 #define ARM_CP_FPU 0x1000 1778 #define ARM_CP_SVE 0x2000 1779 /* Used only as a terminator for ARMCPRegInfo lists */ 1780 #define ARM_CP_SENTINEL 0xffff 1781 /* Mask of only the flag bits in a type field */ 1782 #define ARM_CP_FLAG_MASK 0x30ff 1783 1784 /* Valid values for ARMCPRegInfo state field, indicating which of 1785 * the AArch32 and AArch64 execution states this register is visible in. 1786 * If the reginfo doesn't explicitly specify then it is AArch32 only. 1787 * If the reginfo is declared to be visible in both states then a second 1788 * reginfo is synthesised for the AArch32 view of the AArch64 register, 1789 * such that the AArch32 view is the lower 32 bits of the AArch64 one. 1790 * Note that we rely on the values of these enums as we iterate through 1791 * the various states in some places. 1792 */ 1793 enum { 1794 ARM_CP_STATE_AA32 = 0, 1795 ARM_CP_STATE_AA64 = 1, 1796 ARM_CP_STATE_BOTH = 2, 1797 }; 1798 1799 /* ARM CP register secure state flags. These flags identify security state 1800 * attributes for a given CP register entry. 1801 * The existence of both or neither secure and non-secure flags indicates that 1802 * the register has both a secure and non-secure hash entry. A single one of 1803 * these flags causes the register to only be hashed for the specified 1804 * security state. 1805 * Although definitions may have any combination of the S/NS bits, each 1806 * registered entry will only have one to identify whether the entry is secure 1807 * or non-secure. 1808 */ 1809 enum { 1810 ARM_CP_SECSTATE_S = (1 << 0), /* bit[0]: Secure state register */ 1811 ARM_CP_SECSTATE_NS = (1 << 1), /* bit[1]: Non-secure state register */ 1812 }; 1813 1814 /* Return true if cptype is a valid type field. This is used to try to 1815 * catch errors where the sentinel has been accidentally left off the end 1816 * of a list of registers. 1817 */ 1818 static inline bool cptype_valid(int cptype) 1819 { 1820 return ((cptype & ~ARM_CP_FLAG_MASK) == 0) 1821 || ((cptype & ARM_CP_SPECIAL) && 1822 ((cptype & ~ARM_CP_FLAG_MASK) <= ARM_LAST_SPECIAL)); 1823 } 1824 1825 /* Access rights: 1826 * We define bits for Read and Write access for what rev C of the v7-AR ARM ARM 1827 * defines as PL0 (user), PL1 (fiq/irq/svc/abt/und/sys, ie privileged), and 1828 * PL2 (hyp). The other level which has Read and Write bits is Secure PL1 1829 * (ie any of the privileged modes in Secure state, or Monitor mode). 1830 * If a register is accessible in one privilege level it's always accessible 1831 * in higher privilege levels too. Since "Secure PL1" also follows this rule 1832 * (ie anything visible in PL2 is visible in S-PL1, some things are only 1833 * visible in S-PL1) but "Secure PL1" is a bit of a mouthful, we bend the 1834 * terminology a little and call this PL3. 1835 * In AArch64 things are somewhat simpler as the PLx bits line up exactly 1836 * with the ELx exception levels. 1837 * 1838 * If access permissions for a register are more complex than can be 1839 * described with these bits, then use a laxer set of restrictions, and 1840 * do the more restrictive/complex check inside a helper function. 1841 */ 1842 #define PL3_R 0x80 1843 #define PL3_W 0x40 1844 #define PL2_R (0x20 | PL3_R) 1845 #define PL2_W (0x10 | PL3_W) 1846 #define PL1_R (0x08 | PL2_R) 1847 #define PL1_W (0x04 | PL2_W) 1848 #define PL0_R (0x02 | PL1_R) 1849 #define PL0_W (0x01 | PL1_W) 1850 1851 #define PL3_RW (PL3_R | PL3_W) 1852 #define PL2_RW (PL2_R | PL2_W) 1853 #define PL1_RW (PL1_R | PL1_W) 1854 #define PL0_RW (PL0_R | PL0_W) 1855 1856 /* Return the highest implemented Exception Level */ 1857 static inline int arm_highest_el(CPUARMState *env) 1858 { 1859 if (arm_feature(env, ARM_FEATURE_EL3)) { 1860 return 3; 1861 } 1862 if (arm_feature(env, ARM_FEATURE_EL2)) { 1863 return 2; 1864 } 1865 return 1; 1866 } 1867 1868 /* Return true if a v7M CPU is in Handler mode */ 1869 static inline bool arm_v7m_is_handler_mode(CPUARMState *env) 1870 { 1871 return env->v7m.exception != 0; 1872 } 1873 1874 /* Return the current Exception Level (as per ARMv8; note that this differs 1875 * from the ARMv7 Privilege Level). 1876 */ 1877 static inline int arm_current_el(CPUARMState *env) 1878 { 1879 if (arm_feature(env, ARM_FEATURE_M)) { 1880 return arm_v7m_is_handler_mode(env) || 1881 !(env->v7m.control[env->v7m.secure] & 1); 1882 } 1883 1884 if (is_a64(env)) { 1885 return extract32(env->pstate, 2, 2); 1886 } 1887 1888 switch (env->uncached_cpsr & 0x1f) { 1889 case ARM_CPU_MODE_USR: 1890 return 0; 1891 case ARM_CPU_MODE_HYP: 1892 return 2; 1893 case ARM_CPU_MODE_MON: 1894 return 3; 1895 default: 1896 if (arm_is_secure(env) && !arm_el_is_aa64(env, 3)) { 1897 /* If EL3 is 32-bit then all secure privileged modes run in 1898 * EL3 1899 */ 1900 return 3; 1901 } 1902 1903 return 1; 1904 } 1905 } 1906 1907 typedef struct ARMCPRegInfo ARMCPRegInfo; 1908 1909 typedef enum CPAccessResult { 1910 /* Access is permitted */ 1911 CP_ACCESS_OK = 0, 1912 /* Access fails due to a configurable trap or enable which would 1913 * result in a categorized exception syndrome giving information about 1914 * the failing instruction (ie syndrome category 0x3, 0x4, 0x5, 0x6, 1915 * 0xc or 0x18). The exception is taken to the usual target EL (EL1 or 1916 * PL1 if in EL0, otherwise to the current EL). 1917 */ 1918 CP_ACCESS_TRAP = 1, 1919 /* Access fails and results in an exception syndrome 0x0 ("uncategorized"). 1920 * Note that this is not a catch-all case -- the set of cases which may 1921 * result in this failure is specifically defined by the architecture. 1922 */ 1923 CP_ACCESS_TRAP_UNCATEGORIZED = 2, 1924 /* As CP_ACCESS_TRAP, but for traps directly to EL2 or EL3 */ 1925 CP_ACCESS_TRAP_EL2 = 3, 1926 CP_ACCESS_TRAP_EL3 = 4, 1927 /* As CP_ACCESS_UNCATEGORIZED, but for traps directly to EL2 or EL3 */ 1928 CP_ACCESS_TRAP_UNCATEGORIZED_EL2 = 5, 1929 CP_ACCESS_TRAP_UNCATEGORIZED_EL3 = 6, 1930 /* Access fails and results in an exception syndrome for an FP access, 1931 * trapped directly to EL2 or EL3 1932 */ 1933 CP_ACCESS_TRAP_FP_EL2 = 7, 1934 CP_ACCESS_TRAP_FP_EL3 = 8, 1935 } CPAccessResult; 1936 1937 /* Access functions for coprocessor registers. These cannot fail and 1938 * may not raise exceptions. 1939 */ 1940 typedef uint64_t CPReadFn(CPUARMState *env, const ARMCPRegInfo *opaque); 1941 typedef void CPWriteFn(CPUARMState *env, const ARMCPRegInfo *opaque, 1942 uint64_t value); 1943 /* Access permission check functions for coprocessor registers. */ 1944 typedef CPAccessResult CPAccessFn(CPUARMState *env, 1945 const ARMCPRegInfo *opaque, 1946 bool isread); 1947 /* Hook function for register reset */ 1948 typedef void CPResetFn(CPUARMState *env, const ARMCPRegInfo *opaque); 1949 1950 #define CP_ANY 0xff 1951 1952 /* Definition of an ARM coprocessor register */ 1953 struct ARMCPRegInfo { 1954 /* Name of register (useful mainly for debugging, need not be unique) */ 1955 const char *name; 1956 /* Location of register: coprocessor number and (crn,crm,opc1,opc2) 1957 * tuple. Any of crm, opc1 and opc2 may be CP_ANY to indicate a 1958 * 'wildcard' field -- any value of that field in the MRC/MCR insn 1959 * will be decoded to this register. The register read and write 1960 * callbacks will be passed an ARMCPRegInfo with the crn/crm/opc1/opc2 1961 * used by the program, so it is possible to register a wildcard and 1962 * then behave differently on read/write if necessary. 1963 * For 64 bit registers, only crm and opc1 are relevant; crn and opc2 1964 * must both be zero. 1965 * For AArch64-visible registers, opc0 is also used. 1966 * Since there are no "coprocessors" in AArch64, cp is purely used as a 1967 * way to distinguish (for KVM's benefit) guest-visible system registers 1968 * from demuxed ones provided to preserve the "no side effects on 1969 * KVM register read/write from QEMU" semantics. cp==0x13 is guest 1970 * visible (to match KVM's encoding); cp==0 will be converted to 1971 * cp==0x13 when the ARMCPRegInfo is registered, for convenience. 1972 */ 1973 uint8_t cp; 1974 uint8_t crn; 1975 uint8_t crm; 1976 uint8_t opc0; 1977 uint8_t opc1; 1978 uint8_t opc2; 1979 /* Execution state in which this register is visible: ARM_CP_STATE_* */ 1980 int state; 1981 /* Register type: ARM_CP_* bits/values */ 1982 int type; 1983 /* Access rights: PL*_[RW] */ 1984 int access; 1985 /* Security state: ARM_CP_SECSTATE_* bits/values */ 1986 int secure; 1987 /* The opaque pointer passed to define_arm_cp_regs_with_opaque() when 1988 * this register was defined: can be used to hand data through to the 1989 * register read/write functions, since they are passed the ARMCPRegInfo*. 1990 */ 1991 void *opaque; 1992 /* Value of this register, if it is ARM_CP_CONST. Otherwise, if 1993 * fieldoffset is non-zero, the reset value of the register. 1994 */ 1995 uint64_t resetvalue; 1996 /* Offset of the field in CPUARMState for this register. 1997 * 1998 * This is not needed if either: 1999 * 1. type is ARM_CP_CONST or one of the ARM_CP_SPECIALs 2000 * 2. both readfn and writefn are specified 2001 */ 2002 ptrdiff_t fieldoffset; /* offsetof(CPUARMState, field) */ 2003 2004 /* Offsets of the secure and non-secure fields in CPUARMState for the 2005 * register if it is banked. These fields are only used during the static 2006 * registration of a register. During hashing the bank associated 2007 * with a given security state is copied to fieldoffset which is used from 2008 * there on out. 2009 * 2010 * It is expected that register definitions use either fieldoffset or 2011 * bank_fieldoffsets in the definition but not both. It is also expected 2012 * that both bank offsets are set when defining a banked register. This 2013 * use indicates that a register is banked. 2014 */ 2015 ptrdiff_t bank_fieldoffsets[2]; 2016 2017 /* Function for making any access checks for this register in addition to 2018 * those specified by the 'access' permissions bits. If NULL, no extra 2019 * checks required. The access check is performed at runtime, not at 2020 * translate time. 2021 */ 2022 CPAccessFn *accessfn; 2023 /* Function for handling reads of this register. If NULL, then reads 2024 * will be done by loading from the offset into CPUARMState specified 2025 * by fieldoffset. 2026 */ 2027 CPReadFn *readfn; 2028 /* Function for handling writes of this register. If NULL, then writes 2029 * will be done by writing to the offset into CPUARMState specified 2030 * by fieldoffset. 2031 */ 2032 CPWriteFn *writefn; 2033 /* Function for doing a "raw" read; used when we need to copy 2034 * coprocessor state to the kernel for KVM or out for 2035 * migration. This only needs to be provided if there is also a 2036 * readfn and it has side effects (for instance clear-on-read bits). 2037 */ 2038 CPReadFn *raw_readfn; 2039 /* Function for doing a "raw" write; used when we need to copy KVM 2040 * kernel coprocessor state into userspace, or for inbound 2041 * migration. This only needs to be provided if there is also a 2042 * writefn and it masks out "unwritable" bits or has write-one-to-clear 2043 * or similar behaviour. 2044 */ 2045 CPWriteFn *raw_writefn; 2046 /* Function for resetting the register. If NULL, then reset will be done 2047 * by writing resetvalue to the field specified in fieldoffset. If 2048 * fieldoffset is 0 then no reset will be done. 2049 */ 2050 CPResetFn *resetfn; 2051 }; 2052 2053 /* Macros which are lvalues for the field in CPUARMState for the 2054 * ARMCPRegInfo *ri. 2055 */ 2056 #define CPREG_FIELD32(env, ri) \ 2057 (*(uint32_t *)((char *)(env) + (ri)->fieldoffset)) 2058 #define CPREG_FIELD64(env, ri) \ 2059 (*(uint64_t *)((char *)(env) + (ri)->fieldoffset)) 2060 2061 #define REGINFO_SENTINEL { .type = ARM_CP_SENTINEL } 2062 2063 void define_arm_cp_regs_with_opaque(ARMCPU *cpu, 2064 const ARMCPRegInfo *regs, void *opaque); 2065 void define_one_arm_cp_reg_with_opaque(ARMCPU *cpu, 2066 const ARMCPRegInfo *regs, void *opaque); 2067 static inline void define_arm_cp_regs(ARMCPU *cpu, const ARMCPRegInfo *regs) 2068 { 2069 define_arm_cp_regs_with_opaque(cpu, regs, 0); 2070 } 2071 static inline void define_one_arm_cp_reg(ARMCPU *cpu, const ARMCPRegInfo *regs) 2072 { 2073 define_one_arm_cp_reg_with_opaque(cpu, regs, 0); 2074 } 2075 const ARMCPRegInfo *get_arm_cp_reginfo(GHashTable *cpregs, uint32_t encoded_cp); 2076 2077 /* CPWriteFn that can be used to implement writes-ignored behaviour */ 2078 void arm_cp_write_ignore(CPUARMState *env, const ARMCPRegInfo *ri, 2079 uint64_t value); 2080 /* CPReadFn that can be used for read-as-zero behaviour */ 2081 uint64_t arm_cp_read_zero(CPUARMState *env, const ARMCPRegInfo *ri); 2082 2083 /* CPResetFn that does nothing, for use if no reset is required even 2084 * if fieldoffset is non zero. 2085 */ 2086 void arm_cp_reset_ignore(CPUARMState *env, const ARMCPRegInfo *opaque); 2087 2088 /* Return true if this reginfo struct's field in the cpu state struct 2089 * is 64 bits wide. 2090 */ 2091 static inline bool cpreg_field_is_64bit(const ARMCPRegInfo *ri) 2092 { 2093 return (ri->state == ARM_CP_STATE_AA64) || (ri->type & ARM_CP_64BIT); 2094 } 2095 2096 static inline bool cp_access_ok(int current_el, 2097 const ARMCPRegInfo *ri, int isread) 2098 { 2099 return (ri->access >> ((current_el * 2) + isread)) & 1; 2100 } 2101 2102 /* Raw read of a coprocessor register (as needed for migration, etc) */ 2103 uint64_t read_raw_cp_reg(CPUARMState *env, const ARMCPRegInfo *ri); 2104 2105 /** 2106 * write_list_to_cpustate 2107 * @cpu: ARMCPU 2108 * 2109 * For each register listed in the ARMCPU cpreg_indexes list, write 2110 * its value from the cpreg_values list into the ARMCPUState structure. 2111 * This updates TCG's working data structures from KVM data or 2112 * from incoming migration state. 2113 * 2114 * Returns: true if all register values were updated correctly, 2115 * false if some register was unknown or could not be written. 2116 * Note that we do not stop early on failure -- we will attempt 2117 * writing all registers in the list. 2118 */ 2119 bool write_list_to_cpustate(ARMCPU *cpu); 2120 2121 /** 2122 * write_cpustate_to_list: 2123 * @cpu: ARMCPU 2124 * 2125 * For each register listed in the ARMCPU cpreg_indexes list, write 2126 * its value from the ARMCPUState structure into the cpreg_values list. 2127 * This is used to copy info from TCG's working data structures into 2128 * KVM or for outbound migration. 2129 * 2130 * Returns: true if all register values were read correctly, 2131 * false if some register was unknown or could not be read. 2132 * Note that we do not stop early on failure -- we will attempt 2133 * reading all registers in the list. 2134 */ 2135 bool write_cpustate_to_list(ARMCPU *cpu); 2136 2137 #define ARM_CPUID_TI915T 0x54029152 2138 #define ARM_CPUID_TI925T 0x54029252 2139 2140 #if defined(CONFIG_USER_ONLY) 2141 #define TARGET_PAGE_BITS 12 2142 #else 2143 /* ARMv7 and later CPUs have 4K pages minimum, but ARMv5 and v6 2144 * have to support 1K tiny pages. 2145 */ 2146 #define TARGET_PAGE_BITS_VARY 2147 #define TARGET_PAGE_BITS_MIN 10 2148 #endif 2149 2150 #if defined(TARGET_AARCH64) 2151 # define TARGET_PHYS_ADDR_SPACE_BITS 48 2152 # define TARGET_VIRT_ADDR_SPACE_BITS 64 2153 #else 2154 # define TARGET_PHYS_ADDR_SPACE_BITS 40 2155 # define TARGET_VIRT_ADDR_SPACE_BITS 32 2156 #endif 2157 2158 static inline bool arm_excp_unmasked(CPUState *cs, unsigned int excp_idx, 2159 unsigned int target_el) 2160 { 2161 CPUARMState *env = cs->env_ptr; 2162 unsigned int cur_el = arm_current_el(env); 2163 bool secure = arm_is_secure(env); 2164 bool pstate_unmasked; 2165 int8_t unmasked = 0; 2166 2167 /* Don't take exceptions if they target a lower EL. 2168 * This check should catch any exceptions that would not be taken but left 2169 * pending. 2170 */ 2171 if (cur_el > target_el) { 2172 return false; 2173 } 2174 2175 switch (excp_idx) { 2176 case EXCP_FIQ: 2177 pstate_unmasked = !(env->daif & PSTATE_F); 2178 break; 2179 2180 case EXCP_IRQ: 2181 pstate_unmasked = !(env->daif & PSTATE_I); 2182 break; 2183 2184 case EXCP_VFIQ: 2185 if (secure || !(env->cp15.hcr_el2 & HCR_FMO)) { 2186 /* VFIQs are only taken when hypervized and non-secure. */ 2187 return false; 2188 } 2189 return !(env->daif & PSTATE_F); 2190 case EXCP_VIRQ: 2191 if (secure || !(env->cp15.hcr_el2 & HCR_IMO)) { 2192 /* VIRQs are only taken when hypervized and non-secure. */ 2193 return false; 2194 } 2195 return !(env->daif & PSTATE_I); 2196 default: 2197 g_assert_not_reached(); 2198 } 2199 2200 /* Use the target EL, current execution state and SCR/HCR settings to 2201 * determine whether the corresponding CPSR bit is used to mask the 2202 * interrupt. 2203 */ 2204 if ((target_el > cur_el) && (target_el != 1)) { 2205 /* Exceptions targeting a higher EL may not be maskable */ 2206 if (arm_feature(env, ARM_FEATURE_AARCH64)) { 2207 /* 64-bit masking rules are simple: exceptions to EL3 2208 * can't be masked, and exceptions to EL2 can only be 2209 * masked from Secure state. The HCR and SCR settings 2210 * don't affect the masking logic, only the interrupt routing. 2211 */ 2212 if (target_el == 3 || !secure) { 2213 unmasked = 1; 2214 } 2215 } else { 2216 /* The old 32-bit-only environment has a more complicated 2217 * masking setup. HCR and SCR bits not only affect interrupt 2218 * routing but also change the behaviour of masking. 2219 */ 2220 bool hcr, scr; 2221 2222 switch (excp_idx) { 2223 case EXCP_FIQ: 2224 /* If FIQs are routed to EL3 or EL2 then there are cases where 2225 * we override the CPSR.F in determining if the exception is 2226 * masked or not. If neither of these are set then we fall back 2227 * to the CPSR.F setting otherwise we further assess the state 2228 * below. 2229 */ 2230 hcr = (env->cp15.hcr_el2 & HCR_FMO); 2231 scr = (env->cp15.scr_el3 & SCR_FIQ); 2232 2233 /* When EL3 is 32-bit, the SCR.FW bit controls whether the 2234 * CPSR.F bit masks FIQ interrupts when taken in non-secure 2235 * state. If SCR.FW is set then FIQs can be masked by CPSR.F 2236 * when non-secure but only when FIQs are only routed to EL3. 2237 */ 2238 scr = scr && !((env->cp15.scr_el3 & SCR_FW) && !hcr); 2239 break; 2240 case EXCP_IRQ: 2241 /* When EL3 execution state is 32-bit, if HCR.IMO is set then 2242 * we may override the CPSR.I masking when in non-secure state. 2243 * The SCR.IRQ setting has already been taken into consideration 2244 * when setting the target EL, so it does not have a further 2245 * affect here. 2246 */ 2247 hcr = (env->cp15.hcr_el2 & HCR_IMO); 2248 scr = false; 2249 break; 2250 default: 2251 g_assert_not_reached(); 2252 } 2253 2254 if ((scr || hcr) && !secure) { 2255 unmasked = 1; 2256 } 2257 } 2258 } 2259 2260 /* The PSTATE bits only mask the interrupt if we have not overriden the 2261 * ability above. 2262 */ 2263 return unmasked || pstate_unmasked; 2264 } 2265 2266 #define cpu_init(cpu_model) cpu_generic_init(TYPE_ARM_CPU, cpu_model) 2267 2268 #define ARM_CPU_TYPE_SUFFIX "-" TYPE_ARM_CPU 2269 #define ARM_CPU_TYPE_NAME(name) (name ARM_CPU_TYPE_SUFFIX) 2270 2271 #define cpu_signal_handler cpu_arm_signal_handler 2272 #define cpu_list arm_cpu_list 2273 2274 /* ARM has the following "translation regimes" (as the ARM ARM calls them): 2275 * 2276 * If EL3 is 64-bit: 2277 * + NonSecure EL1 & 0 stage 1 2278 * + NonSecure EL1 & 0 stage 2 2279 * + NonSecure EL2 2280 * + Secure EL1 & EL0 2281 * + Secure EL3 2282 * If EL3 is 32-bit: 2283 * + NonSecure PL1 & 0 stage 1 2284 * + NonSecure PL1 & 0 stage 2 2285 * + NonSecure PL2 2286 * + Secure PL0 & PL1 2287 * (reminder: for 32 bit EL3, Secure PL1 is *EL3*, not EL1.) 2288 * 2289 * For QEMU, an mmu_idx is not quite the same as a translation regime because: 2290 * 1. we need to split the "EL1 & 0" regimes into two mmu_idxes, because they 2291 * may differ in access permissions even if the VA->PA map is the same 2292 * 2. we want to cache in our TLB the full VA->IPA->PA lookup for a stage 1+2 2293 * translation, which means that we have one mmu_idx that deals with two 2294 * concatenated translation regimes [this sort of combined s1+2 TLB is 2295 * architecturally permitted] 2296 * 3. we don't need to allocate an mmu_idx to translations that we won't be 2297 * handling via the TLB. The only way to do a stage 1 translation without 2298 * the immediate stage 2 translation is via the ATS or AT system insns, 2299 * which can be slow-pathed and always do a page table walk. 2300 * 4. we can also safely fold together the "32 bit EL3" and "64 bit EL3" 2301 * translation regimes, because they map reasonably well to each other 2302 * and they can't both be active at the same time. 2303 * This gives us the following list of mmu_idx values: 2304 * 2305 * NS EL0 (aka NS PL0) stage 1+2 2306 * NS EL1 (aka NS PL1) stage 1+2 2307 * NS EL2 (aka NS PL2) 2308 * S EL3 (aka S PL1) 2309 * S EL0 (aka S PL0) 2310 * S EL1 (not used if EL3 is 32 bit) 2311 * NS EL0+1 stage 2 2312 * 2313 * (The last of these is an mmu_idx because we want to be able to use the TLB 2314 * for the accesses done as part of a stage 1 page table walk, rather than 2315 * having to walk the stage 2 page table over and over.) 2316 * 2317 * R profile CPUs have an MPU, but can use the same set of MMU indexes 2318 * as A profile. They only need to distinguish NS EL0 and NS EL1 (and 2319 * NS EL2 if we ever model a Cortex-R52). 2320 * 2321 * M profile CPUs are rather different as they do not have a true MMU. 2322 * They have the following different MMU indexes: 2323 * User 2324 * Privileged 2325 * User, execution priority negative (ie the MPU HFNMIENA bit may apply) 2326 * Privileged, execution priority negative (ditto) 2327 * If the CPU supports the v8M Security Extension then there are also: 2328 * Secure User 2329 * Secure Privileged 2330 * Secure User, execution priority negative 2331 * Secure Privileged, execution priority negative 2332 * 2333 * The ARMMMUIdx and the mmu index value used by the core QEMU TLB code 2334 * are not quite the same -- different CPU types (most notably M profile 2335 * vs A/R profile) would like to use MMU indexes with different semantics, 2336 * but since we don't ever need to use all of those in a single CPU we 2337 * can avoid setting NB_MMU_MODES to more than 8. The lower bits of 2338 * ARMMMUIdx are the core TLB mmu index, and the higher bits are always 2339 * the same for any particular CPU. 2340 * Variables of type ARMMUIdx are always full values, and the core 2341 * index values are in variables of type 'int'. 2342 * 2343 * Our enumeration includes at the end some entries which are not "true" 2344 * mmu_idx values in that they don't have corresponding TLBs and are only 2345 * valid for doing slow path page table walks. 2346 * 2347 * The constant names here are patterned after the general style of the names 2348 * of the AT/ATS operations. 2349 * The values used are carefully arranged to make mmu_idx => EL lookup easy. 2350 * For M profile we arrange them to have a bit for priv, a bit for negpri 2351 * and a bit for secure. 2352 */ 2353 #define ARM_MMU_IDX_A 0x10 /* A profile */ 2354 #define ARM_MMU_IDX_NOTLB 0x20 /* does not have a TLB */ 2355 #define ARM_MMU_IDX_M 0x40 /* M profile */ 2356 2357 /* meanings of the bits for M profile mmu idx values */ 2358 #define ARM_MMU_IDX_M_PRIV 0x1 2359 #define ARM_MMU_IDX_M_NEGPRI 0x2 2360 #define ARM_MMU_IDX_M_S 0x4 2361 2362 #define ARM_MMU_IDX_TYPE_MASK (~0x7) 2363 #define ARM_MMU_IDX_COREIDX_MASK 0x7 2364 2365 typedef enum ARMMMUIdx { 2366 ARMMMUIdx_S12NSE0 = 0 | ARM_MMU_IDX_A, 2367 ARMMMUIdx_S12NSE1 = 1 | ARM_MMU_IDX_A, 2368 ARMMMUIdx_S1E2 = 2 | ARM_MMU_IDX_A, 2369 ARMMMUIdx_S1E3 = 3 | ARM_MMU_IDX_A, 2370 ARMMMUIdx_S1SE0 = 4 | ARM_MMU_IDX_A, 2371 ARMMMUIdx_S1SE1 = 5 | ARM_MMU_IDX_A, 2372 ARMMMUIdx_S2NS = 6 | ARM_MMU_IDX_A, 2373 ARMMMUIdx_MUser = 0 | ARM_MMU_IDX_M, 2374 ARMMMUIdx_MPriv = 1 | ARM_MMU_IDX_M, 2375 ARMMMUIdx_MUserNegPri = 2 | ARM_MMU_IDX_M, 2376 ARMMMUIdx_MPrivNegPri = 3 | ARM_MMU_IDX_M, 2377 ARMMMUIdx_MSUser = 4 | ARM_MMU_IDX_M, 2378 ARMMMUIdx_MSPriv = 5 | ARM_MMU_IDX_M, 2379 ARMMMUIdx_MSUserNegPri = 6 | ARM_MMU_IDX_M, 2380 ARMMMUIdx_MSPrivNegPri = 7 | ARM_MMU_IDX_M, 2381 /* Indexes below here don't have TLBs and are used only for AT system 2382 * instructions or for the first stage of an S12 page table walk. 2383 */ 2384 ARMMMUIdx_S1NSE0 = 0 | ARM_MMU_IDX_NOTLB, 2385 ARMMMUIdx_S1NSE1 = 1 | ARM_MMU_IDX_NOTLB, 2386 } ARMMMUIdx; 2387 2388 /* Bit macros for the core-mmu-index values for each index, 2389 * for use when calling tlb_flush_by_mmuidx() and friends. 2390 */ 2391 typedef enum ARMMMUIdxBit { 2392 ARMMMUIdxBit_S12NSE0 = 1 << 0, 2393 ARMMMUIdxBit_S12NSE1 = 1 << 1, 2394 ARMMMUIdxBit_S1E2 = 1 << 2, 2395 ARMMMUIdxBit_S1E3 = 1 << 3, 2396 ARMMMUIdxBit_S1SE0 = 1 << 4, 2397 ARMMMUIdxBit_S1SE1 = 1 << 5, 2398 ARMMMUIdxBit_S2NS = 1 << 6, 2399 ARMMMUIdxBit_MUser = 1 << 0, 2400 ARMMMUIdxBit_MPriv = 1 << 1, 2401 ARMMMUIdxBit_MUserNegPri = 1 << 2, 2402 ARMMMUIdxBit_MPrivNegPri = 1 << 3, 2403 ARMMMUIdxBit_MSUser = 1 << 4, 2404 ARMMMUIdxBit_MSPriv = 1 << 5, 2405 ARMMMUIdxBit_MSUserNegPri = 1 << 6, 2406 ARMMMUIdxBit_MSPrivNegPri = 1 << 7, 2407 } ARMMMUIdxBit; 2408 2409 #define MMU_USER_IDX 0 2410 2411 static inline int arm_to_core_mmu_idx(ARMMMUIdx mmu_idx) 2412 { 2413 return mmu_idx & ARM_MMU_IDX_COREIDX_MASK; 2414 } 2415 2416 static inline ARMMMUIdx core_to_arm_mmu_idx(CPUARMState *env, int mmu_idx) 2417 { 2418 if (arm_feature(env, ARM_FEATURE_M)) { 2419 return mmu_idx | ARM_MMU_IDX_M; 2420 } else { 2421 return mmu_idx | ARM_MMU_IDX_A; 2422 } 2423 } 2424 2425 /* Return the exception level we're running at if this is our mmu_idx */ 2426 static inline int arm_mmu_idx_to_el(ARMMMUIdx mmu_idx) 2427 { 2428 switch (mmu_idx & ARM_MMU_IDX_TYPE_MASK) { 2429 case ARM_MMU_IDX_A: 2430 return mmu_idx & 3; 2431 case ARM_MMU_IDX_M: 2432 return mmu_idx & ARM_MMU_IDX_M_PRIV; 2433 default: 2434 g_assert_not_reached(); 2435 } 2436 } 2437 2438 /* Return the MMU index for a v7M CPU in the specified security and 2439 * privilege state 2440 */ 2441 static inline ARMMMUIdx arm_v7m_mmu_idx_for_secstate_and_priv(CPUARMState *env, 2442 bool secstate, 2443 bool priv) 2444 { 2445 ARMMMUIdx mmu_idx = ARM_MMU_IDX_M; 2446 2447 if (priv) { 2448 mmu_idx |= ARM_MMU_IDX_M_PRIV; 2449 } 2450 2451 if (armv7m_nvic_neg_prio_requested(env->nvic, secstate)) { 2452 mmu_idx |= ARM_MMU_IDX_M_NEGPRI; 2453 } 2454 2455 if (secstate) { 2456 mmu_idx |= ARM_MMU_IDX_M_S; 2457 } 2458 2459 return mmu_idx; 2460 } 2461 2462 /* Return the MMU index for a v7M CPU in the specified security state */ 2463 static inline ARMMMUIdx arm_v7m_mmu_idx_for_secstate(CPUARMState *env, 2464 bool secstate) 2465 { 2466 bool priv = arm_current_el(env) != 0; 2467 2468 return arm_v7m_mmu_idx_for_secstate_and_priv(env, secstate, priv); 2469 } 2470 2471 /* Determine the current mmu_idx to use for normal loads/stores */ 2472 static inline int cpu_mmu_index(CPUARMState *env, bool ifetch) 2473 { 2474 int el = arm_current_el(env); 2475 2476 if (arm_feature(env, ARM_FEATURE_M)) { 2477 ARMMMUIdx mmu_idx = arm_v7m_mmu_idx_for_secstate(env, env->v7m.secure); 2478 2479 return arm_to_core_mmu_idx(mmu_idx); 2480 } 2481 2482 if (el < 2 && arm_is_secure_below_el3(env)) { 2483 return arm_to_core_mmu_idx(ARMMMUIdx_S1SE0 + el); 2484 } 2485 return el; 2486 } 2487 2488 /* Indexes used when registering address spaces with cpu_address_space_init */ 2489 typedef enum ARMASIdx { 2490 ARMASIdx_NS = 0, 2491 ARMASIdx_S = 1, 2492 } ARMASIdx; 2493 2494 /* Return the Exception Level targeted by debug exceptions. */ 2495 static inline int arm_debug_target_el(CPUARMState *env) 2496 { 2497 bool secure = arm_is_secure(env); 2498 bool route_to_el2 = false; 2499 2500 if (arm_feature(env, ARM_FEATURE_EL2) && !secure) { 2501 route_to_el2 = env->cp15.hcr_el2 & HCR_TGE || 2502 env->cp15.mdcr_el2 & (1 << 8); 2503 } 2504 2505 if (route_to_el2) { 2506 return 2; 2507 } else if (arm_feature(env, ARM_FEATURE_EL3) && 2508 !arm_el_is_aa64(env, 3) && secure) { 2509 return 3; 2510 } else { 2511 return 1; 2512 } 2513 } 2514 2515 static inline bool arm_v7m_csselr_razwi(ARMCPU *cpu) 2516 { 2517 /* If all the CLIDR.Ctypem bits are 0 there are no caches, and 2518 * CSSELR is RAZ/WI. 2519 */ 2520 return (cpu->clidr & R_V7M_CLIDR_CTYPE_ALL_MASK) != 0; 2521 } 2522 2523 static inline bool aa64_generate_debug_exceptions(CPUARMState *env) 2524 { 2525 if (arm_is_secure(env)) { 2526 /* MDCR_EL3.SDD disables debug events from Secure state */ 2527 if (extract32(env->cp15.mdcr_el3, 16, 1) != 0 2528 || arm_current_el(env) == 3) { 2529 return false; 2530 } 2531 } 2532 2533 if (arm_current_el(env) == arm_debug_target_el(env)) { 2534 if ((extract32(env->cp15.mdscr_el1, 13, 1) == 0) 2535 || (env->daif & PSTATE_D)) { 2536 return false; 2537 } 2538 } 2539 return true; 2540 } 2541 2542 static inline bool aa32_generate_debug_exceptions(CPUARMState *env) 2543 { 2544 int el = arm_current_el(env); 2545 2546 if (el == 0 && arm_el_is_aa64(env, 1)) { 2547 return aa64_generate_debug_exceptions(env); 2548 } 2549 2550 if (arm_is_secure(env)) { 2551 int spd; 2552 2553 if (el == 0 && (env->cp15.sder & 1)) { 2554 /* SDER.SUIDEN means debug exceptions from Secure EL0 2555 * are always enabled. Otherwise they are controlled by 2556 * SDCR.SPD like those from other Secure ELs. 2557 */ 2558 return true; 2559 } 2560 2561 spd = extract32(env->cp15.mdcr_el3, 14, 2); 2562 switch (spd) { 2563 case 1: 2564 /* SPD == 0b01 is reserved, but behaves as 0b00. */ 2565 case 0: 2566 /* For 0b00 we return true if external secure invasive debug 2567 * is enabled. On real hardware this is controlled by external 2568 * signals to the core. QEMU always permits debug, and behaves 2569 * as if DBGEN, SPIDEN, NIDEN and SPNIDEN are all tied high. 2570 */ 2571 return true; 2572 case 2: 2573 return false; 2574 case 3: 2575 return true; 2576 } 2577 } 2578 2579 return el != 2; 2580 } 2581 2582 /* Return true if debugging exceptions are currently enabled. 2583 * This corresponds to what in ARM ARM pseudocode would be 2584 * if UsingAArch32() then 2585 * return AArch32.GenerateDebugExceptions() 2586 * else 2587 * return AArch64.GenerateDebugExceptions() 2588 * We choose to push the if() down into this function for clarity, 2589 * since the pseudocode has it at all callsites except for the one in 2590 * CheckSoftwareStep(), where it is elided because both branches would 2591 * always return the same value. 2592 * 2593 * Parts of the pseudocode relating to EL2 and EL3 are omitted because we 2594 * don't yet implement those exception levels or their associated trap bits. 2595 */ 2596 static inline bool arm_generate_debug_exceptions(CPUARMState *env) 2597 { 2598 if (env->aarch64) { 2599 return aa64_generate_debug_exceptions(env); 2600 } else { 2601 return aa32_generate_debug_exceptions(env); 2602 } 2603 } 2604 2605 /* Is single-stepping active? (Note that the "is EL_D AArch64?" check 2606 * implicitly means this always returns false in pre-v8 CPUs.) 2607 */ 2608 static inline bool arm_singlestep_active(CPUARMState *env) 2609 { 2610 return extract32(env->cp15.mdscr_el1, 0, 1) 2611 && arm_el_is_aa64(env, arm_debug_target_el(env)) 2612 && arm_generate_debug_exceptions(env); 2613 } 2614 2615 static inline bool arm_sctlr_b(CPUARMState *env) 2616 { 2617 return 2618 /* We need not implement SCTLR.ITD in user-mode emulation, so 2619 * let linux-user ignore the fact that it conflicts with SCTLR_B. 2620 * This lets people run BE32 binaries with "-cpu any". 2621 */ 2622 #ifndef CONFIG_USER_ONLY 2623 !arm_feature(env, ARM_FEATURE_V7) && 2624 #endif 2625 (env->cp15.sctlr_el[1] & SCTLR_B) != 0; 2626 } 2627 2628 /* Return true if the processor is in big-endian mode. */ 2629 static inline bool arm_cpu_data_is_big_endian(CPUARMState *env) 2630 { 2631 int cur_el; 2632 2633 /* In 32bit endianness is determined by looking at CPSR's E bit */ 2634 if (!is_a64(env)) { 2635 return 2636 #ifdef CONFIG_USER_ONLY 2637 /* In system mode, BE32 is modelled in line with the 2638 * architecture (as word-invariant big-endianness), where loads 2639 * and stores are done little endian but from addresses which 2640 * are adjusted by XORing with the appropriate constant. So the 2641 * endianness to use for the raw data access is not affected by 2642 * SCTLR.B. 2643 * In user mode, however, we model BE32 as byte-invariant 2644 * big-endianness (because user-only code cannot tell the 2645 * difference), and so we need to use a data access endianness 2646 * that depends on SCTLR.B. 2647 */ 2648 arm_sctlr_b(env) || 2649 #endif 2650 ((env->uncached_cpsr & CPSR_E) ? 1 : 0); 2651 } 2652 2653 cur_el = arm_current_el(env); 2654 2655 if (cur_el == 0) { 2656 return (env->cp15.sctlr_el[1] & SCTLR_E0E) != 0; 2657 } 2658 2659 return (env->cp15.sctlr_el[cur_el] & SCTLR_EE) != 0; 2660 } 2661 2662 #include "exec/cpu-all.h" 2663 2664 /* Bit usage in the TB flags field: bit 31 indicates whether we are 2665 * in 32 or 64 bit mode. The meaning of the other bits depends on that. 2666 * We put flags which are shared between 32 and 64 bit mode at the top 2667 * of the word, and flags which apply to only one mode at the bottom. 2668 */ 2669 #define ARM_TBFLAG_AARCH64_STATE_SHIFT 31 2670 #define ARM_TBFLAG_AARCH64_STATE_MASK (1U << ARM_TBFLAG_AARCH64_STATE_SHIFT) 2671 #define ARM_TBFLAG_MMUIDX_SHIFT 28 2672 #define ARM_TBFLAG_MMUIDX_MASK (0x7 << ARM_TBFLAG_MMUIDX_SHIFT) 2673 #define ARM_TBFLAG_SS_ACTIVE_SHIFT 27 2674 #define ARM_TBFLAG_SS_ACTIVE_MASK (1 << ARM_TBFLAG_SS_ACTIVE_SHIFT) 2675 #define ARM_TBFLAG_PSTATE_SS_SHIFT 26 2676 #define ARM_TBFLAG_PSTATE_SS_MASK (1 << ARM_TBFLAG_PSTATE_SS_SHIFT) 2677 /* Target EL if we take a floating-point-disabled exception */ 2678 #define ARM_TBFLAG_FPEXC_EL_SHIFT 24 2679 #define ARM_TBFLAG_FPEXC_EL_MASK (0x3 << ARM_TBFLAG_FPEXC_EL_SHIFT) 2680 2681 /* Bit usage when in AArch32 state: */ 2682 #define ARM_TBFLAG_THUMB_SHIFT 0 2683 #define ARM_TBFLAG_THUMB_MASK (1 << ARM_TBFLAG_THUMB_SHIFT) 2684 #define ARM_TBFLAG_VECLEN_SHIFT 1 2685 #define ARM_TBFLAG_VECLEN_MASK (0x7 << ARM_TBFLAG_VECLEN_SHIFT) 2686 #define ARM_TBFLAG_VECSTRIDE_SHIFT 4 2687 #define ARM_TBFLAG_VECSTRIDE_MASK (0x3 << ARM_TBFLAG_VECSTRIDE_SHIFT) 2688 #define ARM_TBFLAG_VFPEN_SHIFT 7 2689 #define ARM_TBFLAG_VFPEN_MASK (1 << ARM_TBFLAG_VFPEN_SHIFT) 2690 #define ARM_TBFLAG_CONDEXEC_SHIFT 8 2691 #define ARM_TBFLAG_CONDEXEC_MASK (0xff << ARM_TBFLAG_CONDEXEC_SHIFT) 2692 #define ARM_TBFLAG_SCTLR_B_SHIFT 16 2693 #define ARM_TBFLAG_SCTLR_B_MASK (1 << ARM_TBFLAG_SCTLR_B_SHIFT) 2694 /* We store the bottom two bits of the CPAR as TB flags and handle 2695 * checks on the other bits at runtime 2696 */ 2697 #define ARM_TBFLAG_XSCALE_CPAR_SHIFT 17 2698 #define ARM_TBFLAG_XSCALE_CPAR_MASK (3 << ARM_TBFLAG_XSCALE_CPAR_SHIFT) 2699 /* Indicates whether cp register reads and writes by guest code should access 2700 * the secure or nonsecure bank of banked registers; note that this is not 2701 * the same thing as the current security state of the processor! 2702 */ 2703 #define ARM_TBFLAG_NS_SHIFT 19 2704 #define ARM_TBFLAG_NS_MASK (1 << ARM_TBFLAG_NS_SHIFT) 2705 #define ARM_TBFLAG_BE_DATA_SHIFT 20 2706 #define ARM_TBFLAG_BE_DATA_MASK (1 << ARM_TBFLAG_BE_DATA_SHIFT) 2707 /* For M profile only, Handler (ie not Thread) mode */ 2708 #define ARM_TBFLAG_HANDLER_SHIFT 21 2709 #define ARM_TBFLAG_HANDLER_MASK (1 << ARM_TBFLAG_HANDLER_SHIFT) 2710 2711 /* Bit usage when in AArch64 state */ 2712 #define ARM_TBFLAG_TBI0_SHIFT 0 /* TBI0 for EL0/1 or TBI for EL2/3 */ 2713 #define ARM_TBFLAG_TBI0_MASK (0x1ull << ARM_TBFLAG_TBI0_SHIFT) 2714 #define ARM_TBFLAG_TBI1_SHIFT 1 /* TBI1 for EL0/1 */ 2715 #define ARM_TBFLAG_TBI1_MASK (0x1ull << ARM_TBFLAG_TBI1_SHIFT) 2716 #define ARM_TBFLAG_SVEEXC_EL_SHIFT 2 2717 #define ARM_TBFLAG_SVEEXC_EL_MASK (0x3 << ARM_TBFLAG_SVEEXC_EL_SHIFT) 2718 #define ARM_TBFLAG_ZCR_LEN_SHIFT 4 2719 #define ARM_TBFLAG_ZCR_LEN_MASK (0xf << ARM_TBFLAG_ZCR_LEN_SHIFT) 2720 2721 /* some convenience accessor macros */ 2722 #define ARM_TBFLAG_AARCH64_STATE(F) \ 2723 (((F) & ARM_TBFLAG_AARCH64_STATE_MASK) >> ARM_TBFLAG_AARCH64_STATE_SHIFT) 2724 #define ARM_TBFLAG_MMUIDX(F) \ 2725 (((F) & ARM_TBFLAG_MMUIDX_MASK) >> ARM_TBFLAG_MMUIDX_SHIFT) 2726 #define ARM_TBFLAG_SS_ACTIVE(F) \ 2727 (((F) & ARM_TBFLAG_SS_ACTIVE_MASK) >> ARM_TBFLAG_SS_ACTIVE_SHIFT) 2728 #define ARM_TBFLAG_PSTATE_SS(F) \ 2729 (((F) & ARM_TBFLAG_PSTATE_SS_MASK) >> ARM_TBFLAG_PSTATE_SS_SHIFT) 2730 #define ARM_TBFLAG_FPEXC_EL(F) \ 2731 (((F) & ARM_TBFLAG_FPEXC_EL_MASK) >> ARM_TBFLAG_FPEXC_EL_SHIFT) 2732 #define ARM_TBFLAG_THUMB(F) \ 2733 (((F) & ARM_TBFLAG_THUMB_MASK) >> ARM_TBFLAG_THUMB_SHIFT) 2734 #define ARM_TBFLAG_VECLEN(F) \ 2735 (((F) & ARM_TBFLAG_VECLEN_MASK) >> ARM_TBFLAG_VECLEN_SHIFT) 2736 #define ARM_TBFLAG_VECSTRIDE(F) \ 2737 (((F) & ARM_TBFLAG_VECSTRIDE_MASK) >> ARM_TBFLAG_VECSTRIDE_SHIFT) 2738 #define ARM_TBFLAG_VFPEN(F) \ 2739 (((F) & ARM_TBFLAG_VFPEN_MASK) >> ARM_TBFLAG_VFPEN_SHIFT) 2740 #define ARM_TBFLAG_CONDEXEC(F) \ 2741 (((F) & ARM_TBFLAG_CONDEXEC_MASK) >> ARM_TBFLAG_CONDEXEC_SHIFT) 2742 #define ARM_TBFLAG_SCTLR_B(F) \ 2743 (((F) & ARM_TBFLAG_SCTLR_B_MASK) >> ARM_TBFLAG_SCTLR_B_SHIFT) 2744 #define ARM_TBFLAG_XSCALE_CPAR(F) \ 2745 (((F) & ARM_TBFLAG_XSCALE_CPAR_MASK) >> ARM_TBFLAG_XSCALE_CPAR_SHIFT) 2746 #define ARM_TBFLAG_NS(F) \ 2747 (((F) & ARM_TBFLAG_NS_MASK) >> ARM_TBFLAG_NS_SHIFT) 2748 #define ARM_TBFLAG_BE_DATA(F) \ 2749 (((F) & ARM_TBFLAG_BE_DATA_MASK) >> ARM_TBFLAG_BE_DATA_SHIFT) 2750 #define ARM_TBFLAG_HANDLER(F) \ 2751 (((F) & ARM_TBFLAG_HANDLER_MASK) >> ARM_TBFLAG_HANDLER_SHIFT) 2752 #define ARM_TBFLAG_TBI0(F) \ 2753 (((F) & ARM_TBFLAG_TBI0_MASK) >> ARM_TBFLAG_TBI0_SHIFT) 2754 #define ARM_TBFLAG_TBI1(F) \ 2755 (((F) & ARM_TBFLAG_TBI1_MASK) >> ARM_TBFLAG_TBI1_SHIFT) 2756 #define ARM_TBFLAG_SVEEXC_EL(F) \ 2757 (((F) & ARM_TBFLAG_SVEEXC_EL_MASK) >> ARM_TBFLAG_SVEEXC_EL_SHIFT) 2758 #define ARM_TBFLAG_ZCR_LEN(F) \ 2759 (((F) & ARM_TBFLAG_ZCR_LEN_MASK) >> ARM_TBFLAG_ZCR_LEN_SHIFT) 2760 2761 static inline bool bswap_code(bool sctlr_b) 2762 { 2763 #ifdef CONFIG_USER_ONLY 2764 /* BE8 (SCTLR.B = 0, TARGET_WORDS_BIGENDIAN = 1) is mixed endian. 2765 * The invalid combination SCTLR.B=1/CPSR.E=1/TARGET_WORDS_BIGENDIAN=0 2766 * would also end up as a mixed-endian mode with BE code, LE data. 2767 */ 2768 return 2769 #ifdef TARGET_WORDS_BIGENDIAN 2770 1 ^ 2771 #endif 2772 sctlr_b; 2773 #else 2774 /* All code access in ARM is little endian, and there are no loaders 2775 * doing swaps that need to be reversed 2776 */ 2777 return 0; 2778 #endif 2779 } 2780 2781 #ifdef CONFIG_USER_ONLY 2782 static inline bool arm_cpu_bswap_data(CPUARMState *env) 2783 { 2784 return 2785 #ifdef TARGET_WORDS_BIGENDIAN 2786 1 ^ 2787 #endif 2788 arm_cpu_data_is_big_endian(env); 2789 } 2790 #endif 2791 2792 #ifndef CONFIG_USER_ONLY 2793 /** 2794 * arm_regime_tbi0: 2795 * @env: CPUARMState 2796 * @mmu_idx: MMU index indicating required translation regime 2797 * 2798 * Extracts the TBI0 value from the appropriate TCR for the current EL 2799 * 2800 * Returns: the TBI0 value. 2801 */ 2802 uint32_t arm_regime_tbi0(CPUARMState *env, ARMMMUIdx mmu_idx); 2803 2804 /** 2805 * arm_regime_tbi1: 2806 * @env: CPUARMState 2807 * @mmu_idx: MMU index indicating required translation regime 2808 * 2809 * Extracts the TBI1 value from the appropriate TCR for the current EL 2810 * 2811 * Returns: the TBI1 value. 2812 */ 2813 uint32_t arm_regime_tbi1(CPUARMState *env, ARMMMUIdx mmu_idx); 2814 #else 2815 /* We can't handle tagged addresses properly in user-only mode */ 2816 static inline uint32_t arm_regime_tbi0(CPUARMState *env, ARMMMUIdx mmu_idx) 2817 { 2818 return 0; 2819 } 2820 2821 static inline uint32_t arm_regime_tbi1(CPUARMState *env, ARMMMUIdx mmu_idx) 2822 { 2823 return 0; 2824 } 2825 #endif 2826 2827 void cpu_get_tb_cpu_state(CPUARMState *env, target_ulong *pc, 2828 target_ulong *cs_base, uint32_t *flags); 2829 2830 enum { 2831 QEMU_PSCI_CONDUIT_DISABLED = 0, 2832 QEMU_PSCI_CONDUIT_SMC = 1, 2833 QEMU_PSCI_CONDUIT_HVC = 2, 2834 }; 2835 2836 #ifndef CONFIG_USER_ONLY 2837 /* Return the address space index to use for a memory access */ 2838 static inline int arm_asidx_from_attrs(CPUState *cs, MemTxAttrs attrs) 2839 { 2840 return attrs.secure ? ARMASIdx_S : ARMASIdx_NS; 2841 } 2842 2843 /* Return the AddressSpace to use for a memory access 2844 * (which depends on whether the access is S or NS, and whether 2845 * the board gave us a separate AddressSpace for S accesses). 2846 */ 2847 static inline AddressSpace *arm_addressspace(CPUState *cs, MemTxAttrs attrs) 2848 { 2849 return cpu_get_address_space(cs, arm_asidx_from_attrs(cs, attrs)); 2850 } 2851 #endif 2852 2853 /** 2854 * arm_register_el_change_hook: 2855 * Register a hook function which will be called back whenever this 2856 * CPU changes exception level or mode. The hook function will be 2857 * passed a pointer to the ARMCPU and the opaque data pointer passed 2858 * to this function when the hook was registered. 2859 * 2860 * Note that we currently only support registering a single hook function, 2861 * and will assert if this function is called twice. 2862 * This facility is intended for the use of the GICv3 emulation. 2863 */ 2864 void arm_register_el_change_hook(ARMCPU *cpu, ARMELChangeHook *hook, 2865 void *opaque); 2866 2867 /** 2868 * arm_get_el_change_hook_opaque: 2869 * Return the opaque data that will be used by the el_change_hook 2870 * for this CPU. 2871 */ 2872 static inline void *arm_get_el_change_hook_opaque(ARMCPU *cpu) 2873 { 2874 return cpu->el_change_hook_opaque; 2875 } 2876 2877 /** 2878 * aa32_vfp_dreg: 2879 * Return a pointer to the Dn register within env in 32-bit mode. 2880 */ 2881 static inline uint64_t *aa32_vfp_dreg(CPUARMState *env, unsigned regno) 2882 { 2883 return &env->vfp.zregs[regno >> 1].d[regno & 1]; 2884 } 2885 2886 /** 2887 * aa32_vfp_qreg: 2888 * Return a pointer to the Qn register within env in 32-bit mode. 2889 */ 2890 static inline uint64_t *aa32_vfp_qreg(CPUARMState *env, unsigned regno) 2891 { 2892 return &env->vfp.zregs[regno].d[0]; 2893 } 2894 2895 /** 2896 * aa64_vfp_qreg: 2897 * Return a pointer to the Qn register within env in 64-bit mode. 2898 */ 2899 static inline uint64_t *aa64_vfp_qreg(CPUARMState *env, unsigned regno) 2900 { 2901 return &env->vfp.zregs[regno].d[0]; 2902 } 2903 2904 #endif 2905