1 /* 2 * QEMU ARM CPU 3 * 4 * Copyright (c) 2012 SUSE LINUX Products GmbH 5 * 6 * This program is free software; you can redistribute it and/or 7 * modify it under the terms of the GNU General Public License 8 * as published by the Free Software Foundation; either version 2 9 * of the License, or (at your option) any later version. 10 * 11 * This program is distributed in the hope that it will be useful, 12 * but WITHOUT ANY WARRANTY; without even the implied warranty of 13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 14 * GNU General Public License for more details. 15 * 16 * You should have received a copy of the GNU General Public License 17 * along with this program; if not, see 18 * <http://www.gnu.org/licenses/gpl-2.0.html> 19 */ 20 21 #include "qemu/osdep.h" 22 #include "qemu/qemu-print.h" 23 #include "qemu-common.h" 24 #include "target/arm/idau.h" 25 #include "qemu/module.h" 26 #include "qapi/error.h" 27 #include "qapi/visitor.h" 28 #include "cpu.h" 29 #include "internals.h" 30 #include "exec/exec-all.h" 31 #include "hw/qdev-properties.h" 32 #if !defined(CONFIG_USER_ONLY) 33 #include "hw/loader.h" 34 #include "hw/boards.h" 35 #endif 36 #include "sysemu/sysemu.h" 37 #include "sysemu/tcg.h" 38 #include "sysemu/hw_accel.h" 39 #include "kvm_arm.h" 40 #include "disas/capstone.h" 41 #include "fpu/softfloat.h" 42 43 static void arm_cpu_set_pc(CPUState *cs, vaddr value) 44 { 45 ARMCPU *cpu = ARM_CPU(cs); 46 CPUARMState *env = &cpu->env; 47 48 if (is_a64(env)) { 49 env->pc = value; 50 env->thumb = 0; 51 } else { 52 env->regs[15] = value & ~1; 53 env->thumb = value & 1; 54 } 55 } 56 57 static void arm_cpu_synchronize_from_tb(CPUState *cs, TranslationBlock *tb) 58 { 59 ARMCPU *cpu = ARM_CPU(cs); 60 CPUARMState *env = &cpu->env; 61 62 /* 63 * It's OK to look at env for the current mode here, because it's 64 * never possible for an AArch64 TB to chain to an AArch32 TB. 65 */ 66 if (is_a64(env)) { 67 env->pc = tb->pc; 68 } else { 69 env->regs[15] = tb->pc; 70 } 71 } 72 73 static bool arm_cpu_has_work(CPUState *cs) 74 { 75 ARMCPU *cpu = ARM_CPU(cs); 76 77 return (cpu->power_state != PSCI_OFF) 78 && cs->interrupt_request & 79 (CPU_INTERRUPT_FIQ | CPU_INTERRUPT_HARD 80 | CPU_INTERRUPT_VFIQ | CPU_INTERRUPT_VIRQ 81 | CPU_INTERRUPT_EXITTB); 82 } 83 84 void arm_register_pre_el_change_hook(ARMCPU *cpu, ARMELChangeHookFn *hook, 85 void *opaque) 86 { 87 ARMELChangeHook *entry = g_new0(ARMELChangeHook, 1); 88 89 entry->hook = hook; 90 entry->opaque = opaque; 91 92 QLIST_INSERT_HEAD(&cpu->pre_el_change_hooks, entry, node); 93 } 94 95 void arm_register_el_change_hook(ARMCPU *cpu, ARMELChangeHookFn *hook, 96 void *opaque) 97 { 98 ARMELChangeHook *entry = g_new0(ARMELChangeHook, 1); 99 100 entry->hook = hook; 101 entry->opaque = opaque; 102 103 QLIST_INSERT_HEAD(&cpu->el_change_hooks, entry, node); 104 } 105 106 static void cp_reg_reset(gpointer key, gpointer value, gpointer opaque) 107 { 108 /* Reset a single ARMCPRegInfo register */ 109 ARMCPRegInfo *ri = value; 110 ARMCPU *cpu = opaque; 111 112 if (ri->type & (ARM_CP_SPECIAL | ARM_CP_ALIAS)) { 113 return; 114 } 115 116 if (ri->resetfn) { 117 ri->resetfn(&cpu->env, ri); 118 return; 119 } 120 121 /* A zero offset is never possible as it would be regs[0] 122 * so we use it to indicate that reset is being handled elsewhere. 123 * This is basically only used for fields in non-core coprocessors 124 * (like the pxa2xx ones). 125 */ 126 if (!ri->fieldoffset) { 127 return; 128 } 129 130 if (cpreg_field_is_64bit(ri)) { 131 CPREG_FIELD64(&cpu->env, ri) = ri->resetvalue; 132 } else { 133 CPREG_FIELD32(&cpu->env, ri) = ri->resetvalue; 134 } 135 } 136 137 static void cp_reg_check_reset(gpointer key, gpointer value, gpointer opaque) 138 { 139 /* Purely an assertion check: we've already done reset once, 140 * so now check that running the reset for the cpreg doesn't 141 * change its value. This traps bugs where two different cpregs 142 * both try to reset the same state field but to different values. 143 */ 144 ARMCPRegInfo *ri = value; 145 ARMCPU *cpu = opaque; 146 uint64_t oldvalue, newvalue; 147 148 if (ri->type & (ARM_CP_SPECIAL | ARM_CP_ALIAS | ARM_CP_NO_RAW)) { 149 return; 150 } 151 152 oldvalue = read_raw_cp_reg(&cpu->env, ri); 153 cp_reg_reset(key, value, opaque); 154 newvalue = read_raw_cp_reg(&cpu->env, ri); 155 assert(oldvalue == newvalue); 156 } 157 158 /* CPUClass::reset() */ 159 static void arm_cpu_reset(CPUState *s) 160 { 161 ARMCPU *cpu = ARM_CPU(s); 162 ARMCPUClass *acc = ARM_CPU_GET_CLASS(cpu); 163 CPUARMState *env = &cpu->env; 164 165 acc->parent_reset(s); 166 167 memset(env, 0, offsetof(CPUARMState, end_reset_fields)); 168 169 g_hash_table_foreach(cpu->cp_regs, cp_reg_reset, cpu); 170 g_hash_table_foreach(cpu->cp_regs, cp_reg_check_reset, cpu); 171 172 env->vfp.xregs[ARM_VFP_FPSID] = cpu->reset_fpsid; 173 env->vfp.xregs[ARM_VFP_MVFR0] = cpu->isar.mvfr0; 174 env->vfp.xregs[ARM_VFP_MVFR1] = cpu->isar.mvfr1; 175 env->vfp.xregs[ARM_VFP_MVFR2] = cpu->isar.mvfr2; 176 177 cpu->power_state = cpu->start_powered_off ? PSCI_OFF : PSCI_ON; 178 s->halted = cpu->start_powered_off; 179 180 if (arm_feature(env, ARM_FEATURE_IWMMXT)) { 181 env->iwmmxt.cregs[ARM_IWMMXT_wCID] = 0x69051000 | 'Q'; 182 } 183 184 if (arm_feature(env, ARM_FEATURE_AARCH64)) { 185 /* 64 bit CPUs always start in 64 bit mode */ 186 env->aarch64 = 1; 187 #if defined(CONFIG_USER_ONLY) 188 env->pstate = PSTATE_MODE_EL0t; 189 /* Userspace expects access to DC ZVA, CTL_EL0 and the cache ops */ 190 env->cp15.sctlr_el[1] |= SCTLR_UCT | SCTLR_UCI | SCTLR_DZE; 191 /* Enable all PAC keys. */ 192 env->cp15.sctlr_el[1] |= (SCTLR_EnIA | SCTLR_EnIB | 193 SCTLR_EnDA | SCTLR_EnDB); 194 /* Enable all PAC instructions */ 195 env->cp15.hcr_el2 |= HCR_API; 196 env->cp15.scr_el3 |= SCR_API; 197 /* and to the FP/Neon instructions */ 198 env->cp15.cpacr_el1 = deposit64(env->cp15.cpacr_el1, 20, 2, 3); 199 /* and to the SVE instructions */ 200 env->cp15.cpacr_el1 = deposit64(env->cp15.cpacr_el1, 16, 2, 3); 201 env->cp15.cptr_el[3] |= CPTR_EZ; 202 /* with maximum vector length */ 203 env->vfp.zcr_el[1] = cpu_isar_feature(aa64_sve, cpu) ? 204 cpu->sve_max_vq - 1 : 0; 205 env->vfp.zcr_el[2] = env->vfp.zcr_el[1]; 206 env->vfp.zcr_el[3] = env->vfp.zcr_el[1]; 207 /* 208 * Enable TBI0 and TBI1. While the real kernel only enables TBI0, 209 * turning on both here will produce smaller code and otherwise 210 * make no difference to the user-level emulation. 211 */ 212 env->cp15.tcr_el[1].raw_tcr = (3ULL << 37); 213 #else 214 /* Reset into the highest available EL */ 215 if (arm_feature(env, ARM_FEATURE_EL3)) { 216 env->pstate = PSTATE_MODE_EL3h; 217 } else if (arm_feature(env, ARM_FEATURE_EL2)) { 218 env->pstate = PSTATE_MODE_EL2h; 219 } else { 220 env->pstate = PSTATE_MODE_EL1h; 221 } 222 env->pc = cpu->rvbar; 223 #endif 224 } else { 225 #if defined(CONFIG_USER_ONLY) 226 /* Userspace expects access to cp10 and cp11 for FP/Neon */ 227 env->cp15.cpacr_el1 = deposit64(env->cp15.cpacr_el1, 20, 4, 0xf); 228 #endif 229 } 230 231 #if defined(CONFIG_USER_ONLY) 232 env->uncached_cpsr = ARM_CPU_MODE_USR; 233 /* For user mode we must enable access to coprocessors */ 234 env->vfp.xregs[ARM_VFP_FPEXC] = 1 << 30; 235 if (arm_feature(env, ARM_FEATURE_IWMMXT)) { 236 env->cp15.c15_cpar = 3; 237 } else if (arm_feature(env, ARM_FEATURE_XSCALE)) { 238 env->cp15.c15_cpar = 1; 239 } 240 #else 241 242 /* 243 * If the highest available EL is EL2, AArch32 will start in Hyp 244 * mode; otherwise it starts in SVC. Note that if we start in 245 * AArch64 then these values in the uncached_cpsr will be ignored. 246 */ 247 if (arm_feature(env, ARM_FEATURE_EL2) && 248 !arm_feature(env, ARM_FEATURE_EL3)) { 249 env->uncached_cpsr = ARM_CPU_MODE_HYP; 250 } else { 251 env->uncached_cpsr = ARM_CPU_MODE_SVC; 252 } 253 env->daif = PSTATE_D | PSTATE_A | PSTATE_I | PSTATE_F; 254 255 if (arm_feature(env, ARM_FEATURE_M)) { 256 uint32_t initial_msp; /* Loaded from 0x0 */ 257 uint32_t initial_pc; /* Loaded from 0x4 */ 258 uint8_t *rom; 259 uint32_t vecbase; 260 261 if (arm_feature(env, ARM_FEATURE_M_SECURITY)) { 262 env->v7m.secure = true; 263 } else { 264 /* This bit resets to 0 if security is supported, but 1 if 265 * it is not. The bit is not present in v7M, but we set it 266 * here so we can avoid having to make checks on it conditional 267 * on ARM_FEATURE_V8 (we don't let the guest see the bit). 268 */ 269 env->v7m.aircr = R_V7M_AIRCR_BFHFNMINS_MASK; 270 /* 271 * Set NSACR to indicate "NS access permitted to everything"; 272 * this avoids having to have all the tests of it being 273 * conditional on ARM_FEATURE_M_SECURITY. Note also that from 274 * v8.1M the guest-visible value of NSACR in a CPU without the 275 * Security Extension is 0xcff. 276 */ 277 env->v7m.nsacr = 0xcff; 278 } 279 280 /* In v7M the reset value of this bit is IMPDEF, but ARM recommends 281 * that it resets to 1, so QEMU always does that rather than making 282 * it dependent on CPU model. In v8M it is RES1. 283 */ 284 env->v7m.ccr[M_REG_NS] = R_V7M_CCR_STKALIGN_MASK; 285 env->v7m.ccr[M_REG_S] = R_V7M_CCR_STKALIGN_MASK; 286 if (arm_feature(env, ARM_FEATURE_V8)) { 287 /* in v8M the NONBASETHRDENA bit [0] is RES1 */ 288 env->v7m.ccr[M_REG_NS] |= R_V7M_CCR_NONBASETHRDENA_MASK; 289 env->v7m.ccr[M_REG_S] |= R_V7M_CCR_NONBASETHRDENA_MASK; 290 } 291 if (!arm_feature(env, ARM_FEATURE_M_MAIN)) { 292 env->v7m.ccr[M_REG_NS] |= R_V7M_CCR_UNALIGN_TRP_MASK; 293 env->v7m.ccr[M_REG_S] |= R_V7M_CCR_UNALIGN_TRP_MASK; 294 } 295 296 if (arm_feature(env, ARM_FEATURE_VFP)) { 297 env->v7m.fpccr[M_REG_NS] = R_V7M_FPCCR_ASPEN_MASK; 298 env->v7m.fpccr[M_REG_S] = R_V7M_FPCCR_ASPEN_MASK | 299 R_V7M_FPCCR_LSPEN_MASK | R_V7M_FPCCR_S_MASK; 300 } 301 /* Unlike A/R profile, M profile defines the reset LR value */ 302 env->regs[14] = 0xffffffff; 303 304 env->v7m.vecbase[M_REG_S] = cpu->init_svtor & 0xffffff80; 305 306 /* Load the initial SP and PC from offset 0 and 4 in the vector table */ 307 vecbase = env->v7m.vecbase[env->v7m.secure]; 308 rom = rom_ptr(vecbase, 8); 309 if (rom) { 310 /* Address zero is covered by ROM which hasn't yet been 311 * copied into physical memory. 312 */ 313 initial_msp = ldl_p(rom); 314 initial_pc = ldl_p(rom + 4); 315 } else { 316 /* Address zero not covered by a ROM blob, or the ROM blob 317 * is in non-modifiable memory and this is a second reset after 318 * it got copied into memory. In the latter case, rom_ptr 319 * will return a NULL pointer and we should use ldl_phys instead. 320 */ 321 initial_msp = ldl_phys(s->as, vecbase); 322 initial_pc = ldl_phys(s->as, vecbase + 4); 323 } 324 325 env->regs[13] = initial_msp & 0xFFFFFFFC; 326 env->regs[15] = initial_pc & ~1; 327 env->thumb = initial_pc & 1; 328 } 329 330 /* AArch32 has a hard highvec setting of 0xFFFF0000. If we are currently 331 * executing as AArch32 then check if highvecs are enabled and 332 * adjust the PC accordingly. 333 */ 334 if (A32_BANKED_CURRENT_REG_GET(env, sctlr) & SCTLR_V) { 335 env->regs[15] = 0xFFFF0000; 336 } 337 338 /* M profile requires that reset clears the exclusive monitor; 339 * A profile does not, but clearing it makes more sense than having it 340 * set with an exclusive access on address zero. 341 */ 342 arm_clear_exclusive(env); 343 344 env->vfp.xregs[ARM_VFP_FPEXC] = 0; 345 #endif 346 347 if (arm_feature(env, ARM_FEATURE_PMSA)) { 348 if (cpu->pmsav7_dregion > 0) { 349 if (arm_feature(env, ARM_FEATURE_V8)) { 350 memset(env->pmsav8.rbar[M_REG_NS], 0, 351 sizeof(*env->pmsav8.rbar[M_REG_NS]) 352 * cpu->pmsav7_dregion); 353 memset(env->pmsav8.rlar[M_REG_NS], 0, 354 sizeof(*env->pmsav8.rlar[M_REG_NS]) 355 * cpu->pmsav7_dregion); 356 if (arm_feature(env, ARM_FEATURE_M_SECURITY)) { 357 memset(env->pmsav8.rbar[M_REG_S], 0, 358 sizeof(*env->pmsav8.rbar[M_REG_S]) 359 * cpu->pmsav7_dregion); 360 memset(env->pmsav8.rlar[M_REG_S], 0, 361 sizeof(*env->pmsav8.rlar[M_REG_S]) 362 * cpu->pmsav7_dregion); 363 } 364 } else if (arm_feature(env, ARM_FEATURE_V7)) { 365 memset(env->pmsav7.drbar, 0, 366 sizeof(*env->pmsav7.drbar) * cpu->pmsav7_dregion); 367 memset(env->pmsav7.drsr, 0, 368 sizeof(*env->pmsav7.drsr) * cpu->pmsav7_dregion); 369 memset(env->pmsav7.dracr, 0, 370 sizeof(*env->pmsav7.dracr) * cpu->pmsav7_dregion); 371 } 372 } 373 env->pmsav7.rnr[M_REG_NS] = 0; 374 env->pmsav7.rnr[M_REG_S] = 0; 375 env->pmsav8.mair0[M_REG_NS] = 0; 376 env->pmsav8.mair0[M_REG_S] = 0; 377 env->pmsav8.mair1[M_REG_NS] = 0; 378 env->pmsav8.mair1[M_REG_S] = 0; 379 } 380 381 if (arm_feature(env, ARM_FEATURE_M_SECURITY)) { 382 if (cpu->sau_sregion > 0) { 383 memset(env->sau.rbar, 0, sizeof(*env->sau.rbar) * cpu->sau_sregion); 384 memset(env->sau.rlar, 0, sizeof(*env->sau.rlar) * cpu->sau_sregion); 385 } 386 env->sau.rnr = 0; 387 /* SAU_CTRL reset value is IMPDEF; we choose 0, which is what 388 * the Cortex-M33 does. 389 */ 390 env->sau.ctrl = 0; 391 } 392 393 set_flush_to_zero(1, &env->vfp.standard_fp_status); 394 set_flush_inputs_to_zero(1, &env->vfp.standard_fp_status); 395 set_default_nan_mode(1, &env->vfp.standard_fp_status); 396 set_float_detect_tininess(float_tininess_before_rounding, 397 &env->vfp.fp_status); 398 set_float_detect_tininess(float_tininess_before_rounding, 399 &env->vfp.standard_fp_status); 400 set_float_detect_tininess(float_tininess_before_rounding, 401 &env->vfp.fp_status_f16); 402 #ifndef CONFIG_USER_ONLY 403 if (kvm_enabled()) { 404 kvm_arm_reset_vcpu(cpu); 405 } 406 #endif 407 408 hw_breakpoint_update_all(cpu); 409 hw_watchpoint_update_all(cpu); 410 arm_rebuild_hflags(env); 411 } 412 413 bool arm_cpu_exec_interrupt(CPUState *cs, int interrupt_request) 414 { 415 CPUClass *cc = CPU_GET_CLASS(cs); 416 CPUARMState *env = cs->env_ptr; 417 uint32_t cur_el = arm_current_el(env); 418 bool secure = arm_is_secure(env); 419 uint32_t target_el; 420 uint32_t excp_idx; 421 bool ret = false; 422 423 if (interrupt_request & CPU_INTERRUPT_FIQ) { 424 excp_idx = EXCP_FIQ; 425 target_el = arm_phys_excp_target_el(cs, excp_idx, cur_el, secure); 426 if (arm_excp_unmasked(cs, excp_idx, target_el)) { 427 cs->exception_index = excp_idx; 428 env->exception.target_el = target_el; 429 cc->do_interrupt(cs); 430 ret = true; 431 } 432 } 433 if (interrupt_request & CPU_INTERRUPT_HARD) { 434 excp_idx = EXCP_IRQ; 435 target_el = arm_phys_excp_target_el(cs, excp_idx, cur_el, secure); 436 if (arm_excp_unmasked(cs, excp_idx, target_el)) { 437 cs->exception_index = excp_idx; 438 env->exception.target_el = target_el; 439 cc->do_interrupt(cs); 440 ret = true; 441 } 442 } 443 if (interrupt_request & CPU_INTERRUPT_VIRQ) { 444 excp_idx = EXCP_VIRQ; 445 target_el = 1; 446 if (arm_excp_unmasked(cs, excp_idx, target_el)) { 447 cs->exception_index = excp_idx; 448 env->exception.target_el = target_el; 449 cc->do_interrupt(cs); 450 ret = true; 451 } 452 } 453 if (interrupt_request & CPU_INTERRUPT_VFIQ) { 454 excp_idx = EXCP_VFIQ; 455 target_el = 1; 456 if (arm_excp_unmasked(cs, excp_idx, target_el)) { 457 cs->exception_index = excp_idx; 458 env->exception.target_el = target_el; 459 cc->do_interrupt(cs); 460 ret = true; 461 } 462 } 463 464 return ret; 465 } 466 467 #if !defined(CONFIG_USER_ONLY) || !defined(TARGET_AARCH64) 468 static bool arm_v7m_cpu_exec_interrupt(CPUState *cs, int interrupt_request) 469 { 470 CPUClass *cc = CPU_GET_CLASS(cs); 471 ARMCPU *cpu = ARM_CPU(cs); 472 CPUARMState *env = &cpu->env; 473 bool ret = false; 474 475 /* ARMv7-M interrupt masking works differently than -A or -R. 476 * There is no FIQ/IRQ distinction. Instead of I and F bits 477 * masking FIQ and IRQ interrupts, an exception is taken only 478 * if it is higher priority than the current execution priority 479 * (which depends on state like BASEPRI, FAULTMASK and the 480 * currently active exception). 481 */ 482 if (interrupt_request & CPU_INTERRUPT_HARD 483 && (armv7m_nvic_can_take_pending_exception(env->nvic))) { 484 cs->exception_index = EXCP_IRQ; 485 cc->do_interrupt(cs); 486 ret = true; 487 } 488 return ret; 489 } 490 #endif 491 492 void arm_cpu_update_virq(ARMCPU *cpu) 493 { 494 /* 495 * Update the interrupt level for VIRQ, which is the logical OR of 496 * the HCR_EL2.VI bit and the input line level from the GIC. 497 */ 498 CPUARMState *env = &cpu->env; 499 CPUState *cs = CPU(cpu); 500 501 bool new_state = (env->cp15.hcr_el2 & HCR_VI) || 502 (env->irq_line_state & CPU_INTERRUPT_VIRQ); 503 504 if (new_state != ((cs->interrupt_request & CPU_INTERRUPT_VIRQ) != 0)) { 505 if (new_state) { 506 cpu_interrupt(cs, CPU_INTERRUPT_VIRQ); 507 } else { 508 cpu_reset_interrupt(cs, CPU_INTERRUPT_VIRQ); 509 } 510 } 511 } 512 513 void arm_cpu_update_vfiq(ARMCPU *cpu) 514 { 515 /* 516 * Update the interrupt level for VFIQ, which is the logical OR of 517 * the HCR_EL2.VF bit and the input line level from the GIC. 518 */ 519 CPUARMState *env = &cpu->env; 520 CPUState *cs = CPU(cpu); 521 522 bool new_state = (env->cp15.hcr_el2 & HCR_VF) || 523 (env->irq_line_state & CPU_INTERRUPT_VFIQ); 524 525 if (new_state != ((cs->interrupt_request & CPU_INTERRUPT_VFIQ) != 0)) { 526 if (new_state) { 527 cpu_interrupt(cs, CPU_INTERRUPT_VFIQ); 528 } else { 529 cpu_reset_interrupt(cs, CPU_INTERRUPT_VFIQ); 530 } 531 } 532 } 533 534 #ifndef CONFIG_USER_ONLY 535 static void arm_cpu_set_irq(void *opaque, int irq, int level) 536 { 537 ARMCPU *cpu = opaque; 538 CPUARMState *env = &cpu->env; 539 CPUState *cs = CPU(cpu); 540 static const int mask[] = { 541 [ARM_CPU_IRQ] = CPU_INTERRUPT_HARD, 542 [ARM_CPU_FIQ] = CPU_INTERRUPT_FIQ, 543 [ARM_CPU_VIRQ] = CPU_INTERRUPT_VIRQ, 544 [ARM_CPU_VFIQ] = CPU_INTERRUPT_VFIQ 545 }; 546 547 if (level) { 548 env->irq_line_state |= mask[irq]; 549 } else { 550 env->irq_line_state &= ~mask[irq]; 551 } 552 553 switch (irq) { 554 case ARM_CPU_VIRQ: 555 assert(arm_feature(env, ARM_FEATURE_EL2)); 556 arm_cpu_update_virq(cpu); 557 break; 558 case ARM_CPU_VFIQ: 559 assert(arm_feature(env, ARM_FEATURE_EL2)); 560 arm_cpu_update_vfiq(cpu); 561 break; 562 case ARM_CPU_IRQ: 563 case ARM_CPU_FIQ: 564 if (level) { 565 cpu_interrupt(cs, mask[irq]); 566 } else { 567 cpu_reset_interrupt(cs, mask[irq]); 568 } 569 break; 570 default: 571 g_assert_not_reached(); 572 } 573 } 574 575 static void arm_cpu_kvm_set_irq(void *opaque, int irq, int level) 576 { 577 #ifdef CONFIG_KVM 578 ARMCPU *cpu = opaque; 579 CPUARMState *env = &cpu->env; 580 CPUState *cs = CPU(cpu); 581 uint32_t linestate_bit; 582 int irq_id; 583 584 switch (irq) { 585 case ARM_CPU_IRQ: 586 irq_id = KVM_ARM_IRQ_CPU_IRQ; 587 linestate_bit = CPU_INTERRUPT_HARD; 588 break; 589 case ARM_CPU_FIQ: 590 irq_id = KVM_ARM_IRQ_CPU_FIQ; 591 linestate_bit = CPU_INTERRUPT_FIQ; 592 break; 593 default: 594 g_assert_not_reached(); 595 } 596 597 if (level) { 598 env->irq_line_state |= linestate_bit; 599 } else { 600 env->irq_line_state &= ~linestate_bit; 601 } 602 kvm_arm_set_irq(cs->cpu_index, KVM_ARM_IRQ_TYPE_CPU, irq_id, !!level); 603 #endif 604 } 605 606 static bool arm_cpu_virtio_is_big_endian(CPUState *cs) 607 { 608 ARMCPU *cpu = ARM_CPU(cs); 609 CPUARMState *env = &cpu->env; 610 611 cpu_synchronize_state(cs); 612 return arm_cpu_data_is_big_endian(env); 613 } 614 615 #endif 616 617 static inline void set_feature(CPUARMState *env, int feature) 618 { 619 env->features |= 1ULL << feature; 620 } 621 622 static inline void unset_feature(CPUARMState *env, int feature) 623 { 624 env->features &= ~(1ULL << feature); 625 } 626 627 static int 628 print_insn_thumb1(bfd_vma pc, disassemble_info *info) 629 { 630 return print_insn_arm(pc | 1, info); 631 } 632 633 static void arm_disas_set_info(CPUState *cpu, disassemble_info *info) 634 { 635 ARMCPU *ac = ARM_CPU(cpu); 636 CPUARMState *env = &ac->env; 637 bool sctlr_b; 638 639 if (is_a64(env)) { 640 /* We might not be compiled with the A64 disassembler 641 * because it needs a C++ compiler. Leave print_insn 642 * unset in this case to use the caller default behaviour. 643 */ 644 #if defined(CONFIG_ARM_A64_DIS) 645 info->print_insn = print_insn_arm_a64; 646 #endif 647 info->cap_arch = CS_ARCH_ARM64; 648 info->cap_insn_unit = 4; 649 info->cap_insn_split = 4; 650 } else { 651 int cap_mode; 652 if (env->thumb) { 653 info->print_insn = print_insn_thumb1; 654 info->cap_insn_unit = 2; 655 info->cap_insn_split = 4; 656 cap_mode = CS_MODE_THUMB; 657 } else { 658 info->print_insn = print_insn_arm; 659 info->cap_insn_unit = 4; 660 info->cap_insn_split = 4; 661 cap_mode = CS_MODE_ARM; 662 } 663 if (arm_feature(env, ARM_FEATURE_V8)) { 664 cap_mode |= CS_MODE_V8; 665 } 666 if (arm_feature(env, ARM_FEATURE_M)) { 667 cap_mode |= CS_MODE_MCLASS; 668 } 669 info->cap_arch = CS_ARCH_ARM; 670 info->cap_mode = cap_mode; 671 } 672 673 sctlr_b = arm_sctlr_b(env); 674 if (bswap_code(sctlr_b)) { 675 #ifdef TARGET_WORDS_BIGENDIAN 676 info->endian = BFD_ENDIAN_LITTLE; 677 #else 678 info->endian = BFD_ENDIAN_BIG; 679 #endif 680 } 681 info->flags &= ~INSN_ARM_BE32; 682 #ifndef CONFIG_USER_ONLY 683 if (sctlr_b) { 684 info->flags |= INSN_ARM_BE32; 685 } 686 #endif 687 } 688 689 #ifdef TARGET_AARCH64 690 691 static void aarch64_cpu_dump_state(CPUState *cs, FILE *f, int flags) 692 { 693 ARMCPU *cpu = ARM_CPU(cs); 694 CPUARMState *env = &cpu->env; 695 uint32_t psr = pstate_read(env); 696 int i; 697 int el = arm_current_el(env); 698 const char *ns_status; 699 700 qemu_fprintf(f, " PC=%016" PRIx64 " ", env->pc); 701 for (i = 0; i < 32; i++) { 702 if (i == 31) { 703 qemu_fprintf(f, " SP=%016" PRIx64 "\n", env->xregs[i]); 704 } else { 705 qemu_fprintf(f, "X%02d=%016" PRIx64 "%s", i, env->xregs[i], 706 (i + 2) % 3 ? " " : "\n"); 707 } 708 } 709 710 if (arm_feature(env, ARM_FEATURE_EL3) && el != 3) { 711 ns_status = env->cp15.scr_el3 & SCR_NS ? "NS " : "S "; 712 } else { 713 ns_status = ""; 714 } 715 qemu_fprintf(f, "PSTATE=%08x %c%c%c%c %sEL%d%c", 716 psr, 717 psr & PSTATE_N ? 'N' : '-', 718 psr & PSTATE_Z ? 'Z' : '-', 719 psr & PSTATE_C ? 'C' : '-', 720 psr & PSTATE_V ? 'V' : '-', 721 ns_status, 722 el, 723 psr & PSTATE_SP ? 'h' : 't'); 724 725 if (cpu_isar_feature(aa64_bti, cpu)) { 726 qemu_fprintf(f, " BTYPE=%d", (psr & PSTATE_BTYPE) >> 10); 727 } 728 if (!(flags & CPU_DUMP_FPU)) { 729 qemu_fprintf(f, "\n"); 730 return; 731 } 732 if (fp_exception_el(env, el) != 0) { 733 qemu_fprintf(f, " FPU disabled\n"); 734 return; 735 } 736 qemu_fprintf(f, " FPCR=%08x FPSR=%08x\n", 737 vfp_get_fpcr(env), vfp_get_fpsr(env)); 738 739 if (cpu_isar_feature(aa64_sve, cpu) && sve_exception_el(env, el) == 0) { 740 int j, zcr_len = sve_zcr_len_for_el(env, el); 741 742 for (i = 0; i <= FFR_PRED_NUM; i++) { 743 bool eol; 744 if (i == FFR_PRED_NUM) { 745 qemu_fprintf(f, "FFR="); 746 /* It's last, so end the line. */ 747 eol = true; 748 } else { 749 qemu_fprintf(f, "P%02d=", i); 750 switch (zcr_len) { 751 case 0: 752 eol = i % 8 == 7; 753 break; 754 case 1: 755 eol = i % 6 == 5; 756 break; 757 case 2: 758 case 3: 759 eol = i % 3 == 2; 760 break; 761 default: 762 /* More than one quadword per predicate. */ 763 eol = true; 764 break; 765 } 766 } 767 for (j = zcr_len / 4; j >= 0; j--) { 768 int digits; 769 if (j * 4 + 4 <= zcr_len + 1) { 770 digits = 16; 771 } else { 772 digits = (zcr_len % 4 + 1) * 4; 773 } 774 qemu_fprintf(f, "%0*" PRIx64 "%s", digits, 775 env->vfp.pregs[i].p[j], 776 j ? ":" : eol ? "\n" : " "); 777 } 778 } 779 780 for (i = 0; i < 32; i++) { 781 if (zcr_len == 0) { 782 qemu_fprintf(f, "Z%02d=%016" PRIx64 ":%016" PRIx64 "%s", 783 i, env->vfp.zregs[i].d[1], 784 env->vfp.zregs[i].d[0], i & 1 ? "\n" : " "); 785 } else if (zcr_len == 1) { 786 qemu_fprintf(f, "Z%02d=%016" PRIx64 ":%016" PRIx64 787 ":%016" PRIx64 ":%016" PRIx64 "\n", 788 i, env->vfp.zregs[i].d[3], env->vfp.zregs[i].d[2], 789 env->vfp.zregs[i].d[1], env->vfp.zregs[i].d[0]); 790 } else { 791 for (j = zcr_len; j >= 0; j--) { 792 bool odd = (zcr_len - j) % 2 != 0; 793 if (j == zcr_len) { 794 qemu_fprintf(f, "Z%02d[%x-%x]=", i, j, j - 1); 795 } else if (!odd) { 796 if (j > 0) { 797 qemu_fprintf(f, " [%x-%x]=", j, j - 1); 798 } else { 799 qemu_fprintf(f, " [%x]=", j); 800 } 801 } 802 qemu_fprintf(f, "%016" PRIx64 ":%016" PRIx64 "%s", 803 env->vfp.zregs[i].d[j * 2 + 1], 804 env->vfp.zregs[i].d[j * 2], 805 odd || j == 0 ? "\n" : ":"); 806 } 807 } 808 } 809 } else { 810 for (i = 0; i < 32; i++) { 811 uint64_t *q = aa64_vfp_qreg(env, i); 812 qemu_fprintf(f, "Q%02d=%016" PRIx64 ":%016" PRIx64 "%s", 813 i, q[1], q[0], (i & 1 ? "\n" : " ")); 814 } 815 } 816 } 817 818 #else 819 820 static inline void aarch64_cpu_dump_state(CPUState *cs, FILE *f, int flags) 821 { 822 g_assert_not_reached(); 823 } 824 825 #endif 826 827 static void arm_cpu_dump_state(CPUState *cs, FILE *f, int flags) 828 { 829 ARMCPU *cpu = ARM_CPU(cs); 830 CPUARMState *env = &cpu->env; 831 int i; 832 833 if (is_a64(env)) { 834 aarch64_cpu_dump_state(cs, f, flags); 835 return; 836 } 837 838 for (i = 0; i < 16; i++) { 839 qemu_fprintf(f, "R%02d=%08x", i, env->regs[i]); 840 if ((i % 4) == 3) { 841 qemu_fprintf(f, "\n"); 842 } else { 843 qemu_fprintf(f, " "); 844 } 845 } 846 847 if (arm_feature(env, ARM_FEATURE_M)) { 848 uint32_t xpsr = xpsr_read(env); 849 const char *mode; 850 const char *ns_status = ""; 851 852 if (arm_feature(env, ARM_FEATURE_M_SECURITY)) { 853 ns_status = env->v7m.secure ? "S " : "NS "; 854 } 855 856 if (xpsr & XPSR_EXCP) { 857 mode = "handler"; 858 } else { 859 if (env->v7m.control[env->v7m.secure] & R_V7M_CONTROL_NPRIV_MASK) { 860 mode = "unpriv-thread"; 861 } else { 862 mode = "priv-thread"; 863 } 864 } 865 866 qemu_fprintf(f, "XPSR=%08x %c%c%c%c %c %s%s\n", 867 xpsr, 868 xpsr & XPSR_N ? 'N' : '-', 869 xpsr & XPSR_Z ? 'Z' : '-', 870 xpsr & XPSR_C ? 'C' : '-', 871 xpsr & XPSR_V ? 'V' : '-', 872 xpsr & XPSR_T ? 'T' : 'A', 873 ns_status, 874 mode); 875 } else { 876 uint32_t psr = cpsr_read(env); 877 const char *ns_status = ""; 878 879 if (arm_feature(env, ARM_FEATURE_EL3) && 880 (psr & CPSR_M) != ARM_CPU_MODE_MON) { 881 ns_status = env->cp15.scr_el3 & SCR_NS ? "NS " : "S "; 882 } 883 884 qemu_fprintf(f, "PSR=%08x %c%c%c%c %c %s%s%d\n", 885 psr, 886 psr & CPSR_N ? 'N' : '-', 887 psr & CPSR_Z ? 'Z' : '-', 888 psr & CPSR_C ? 'C' : '-', 889 psr & CPSR_V ? 'V' : '-', 890 psr & CPSR_T ? 'T' : 'A', 891 ns_status, 892 aarch32_mode_name(psr), (psr & 0x10) ? 32 : 26); 893 } 894 895 if (flags & CPU_DUMP_FPU) { 896 int numvfpregs = 0; 897 if (arm_feature(env, ARM_FEATURE_VFP)) { 898 numvfpregs += 16; 899 } 900 if (arm_feature(env, ARM_FEATURE_VFP3)) { 901 numvfpregs += 16; 902 } 903 for (i = 0; i < numvfpregs; i++) { 904 uint64_t v = *aa32_vfp_dreg(env, i); 905 qemu_fprintf(f, "s%02d=%08x s%02d=%08x d%02d=%016" PRIx64 "\n", 906 i * 2, (uint32_t)v, 907 i * 2 + 1, (uint32_t)(v >> 32), 908 i, v); 909 } 910 qemu_fprintf(f, "FPSCR: %08x\n", vfp_get_fpscr(env)); 911 } 912 } 913 914 uint64_t arm_cpu_mp_affinity(int idx, uint8_t clustersz) 915 { 916 uint32_t Aff1 = idx / clustersz; 917 uint32_t Aff0 = idx % clustersz; 918 return (Aff1 << ARM_AFF1_SHIFT) | Aff0; 919 } 920 921 static void cpreg_hashtable_data_destroy(gpointer data) 922 { 923 /* 924 * Destroy function for cpu->cp_regs hashtable data entries. 925 * We must free the name string because it was g_strdup()ed in 926 * add_cpreg_to_hashtable(). It's OK to cast away the 'const' 927 * from r->name because we know we definitely allocated it. 928 */ 929 ARMCPRegInfo *r = data; 930 931 g_free((void *)r->name); 932 g_free(r); 933 } 934 935 static void arm_cpu_initfn(Object *obj) 936 { 937 ARMCPU *cpu = ARM_CPU(obj); 938 939 cpu_set_cpustate_pointers(cpu); 940 cpu->cp_regs = g_hash_table_new_full(g_int_hash, g_int_equal, 941 g_free, cpreg_hashtable_data_destroy); 942 943 QLIST_INIT(&cpu->pre_el_change_hooks); 944 QLIST_INIT(&cpu->el_change_hooks); 945 946 #ifndef CONFIG_USER_ONLY 947 /* Our inbound IRQ and FIQ lines */ 948 if (kvm_enabled()) { 949 /* VIRQ and VFIQ are unused with KVM but we add them to maintain 950 * the same interface as non-KVM CPUs. 951 */ 952 qdev_init_gpio_in(DEVICE(cpu), arm_cpu_kvm_set_irq, 4); 953 } else { 954 qdev_init_gpio_in(DEVICE(cpu), arm_cpu_set_irq, 4); 955 } 956 957 qdev_init_gpio_out(DEVICE(cpu), cpu->gt_timer_outputs, 958 ARRAY_SIZE(cpu->gt_timer_outputs)); 959 960 qdev_init_gpio_out_named(DEVICE(cpu), &cpu->gicv3_maintenance_interrupt, 961 "gicv3-maintenance-interrupt", 1); 962 qdev_init_gpio_out_named(DEVICE(cpu), &cpu->pmu_interrupt, 963 "pmu-interrupt", 1); 964 #endif 965 966 /* DTB consumers generally don't in fact care what the 'compatible' 967 * string is, so always provide some string and trust that a hypothetical 968 * picky DTB consumer will also provide a helpful error message. 969 */ 970 cpu->dtb_compatible = "qemu,unknown"; 971 cpu->psci_version = 1; /* By default assume PSCI v0.1 */ 972 cpu->kvm_target = QEMU_KVM_ARM_TARGET_NONE; 973 974 if (tcg_enabled()) { 975 cpu->psci_version = 2; /* TCG implements PSCI 0.2 */ 976 } 977 } 978 979 static Property arm_cpu_reset_cbar_property = 980 DEFINE_PROP_UINT64("reset-cbar", ARMCPU, reset_cbar, 0); 981 982 static Property arm_cpu_reset_hivecs_property = 983 DEFINE_PROP_BOOL("reset-hivecs", ARMCPU, reset_hivecs, false); 984 985 static Property arm_cpu_rvbar_property = 986 DEFINE_PROP_UINT64("rvbar", ARMCPU, rvbar, 0); 987 988 static Property arm_cpu_has_el2_property = 989 DEFINE_PROP_BOOL("has_el2", ARMCPU, has_el2, true); 990 991 static Property arm_cpu_has_el3_property = 992 DEFINE_PROP_BOOL("has_el3", ARMCPU, has_el3, true); 993 994 static Property arm_cpu_cfgend_property = 995 DEFINE_PROP_BOOL("cfgend", ARMCPU, cfgend, false); 996 997 static Property arm_cpu_has_vfp_property = 998 DEFINE_PROP_BOOL("vfp", ARMCPU, has_vfp, true); 999 1000 static Property arm_cpu_has_neon_property = 1001 DEFINE_PROP_BOOL("neon", ARMCPU, has_neon, true); 1002 1003 static Property arm_cpu_has_dsp_property = 1004 DEFINE_PROP_BOOL("dsp", ARMCPU, has_dsp, true); 1005 1006 static Property arm_cpu_has_mpu_property = 1007 DEFINE_PROP_BOOL("has-mpu", ARMCPU, has_mpu, true); 1008 1009 /* This is like DEFINE_PROP_UINT32 but it doesn't set the default value, 1010 * because the CPU initfn will have already set cpu->pmsav7_dregion to 1011 * the right value for that particular CPU type, and we don't want 1012 * to override that with an incorrect constant value. 1013 */ 1014 static Property arm_cpu_pmsav7_dregion_property = 1015 DEFINE_PROP_UNSIGNED_NODEFAULT("pmsav7-dregion", ARMCPU, 1016 pmsav7_dregion, 1017 qdev_prop_uint32, uint32_t); 1018 1019 static bool arm_get_pmu(Object *obj, Error **errp) 1020 { 1021 ARMCPU *cpu = ARM_CPU(obj); 1022 1023 return cpu->has_pmu; 1024 } 1025 1026 static void arm_set_pmu(Object *obj, bool value, Error **errp) 1027 { 1028 ARMCPU *cpu = ARM_CPU(obj); 1029 1030 if (value) { 1031 if (kvm_enabled() && !kvm_arm_pmu_supported(CPU(cpu))) { 1032 error_setg(errp, "'pmu' feature not supported by KVM on this host"); 1033 return; 1034 } 1035 set_feature(&cpu->env, ARM_FEATURE_PMU); 1036 } else { 1037 unset_feature(&cpu->env, ARM_FEATURE_PMU); 1038 } 1039 cpu->has_pmu = value; 1040 } 1041 1042 static void arm_get_init_svtor(Object *obj, Visitor *v, const char *name, 1043 void *opaque, Error **errp) 1044 { 1045 ARMCPU *cpu = ARM_CPU(obj); 1046 1047 visit_type_uint32(v, name, &cpu->init_svtor, errp); 1048 } 1049 1050 static void arm_set_init_svtor(Object *obj, Visitor *v, const char *name, 1051 void *opaque, Error **errp) 1052 { 1053 ARMCPU *cpu = ARM_CPU(obj); 1054 1055 visit_type_uint32(v, name, &cpu->init_svtor, errp); 1056 } 1057 1058 void arm_cpu_post_init(Object *obj) 1059 { 1060 ARMCPU *cpu = ARM_CPU(obj); 1061 1062 /* M profile implies PMSA. We have to do this here rather than 1063 * in realize with the other feature-implication checks because 1064 * we look at the PMSA bit to see if we should add some properties. 1065 */ 1066 if (arm_feature(&cpu->env, ARM_FEATURE_M)) { 1067 set_feature(&cpu->env, ARM_FEATURE_PMSA); 1068 } 1069 /* Similarly for the VFP feature bits */ 1070 if (arm_feature(&cpu->env, ARM_FEATURE_VFP4)) { 1071 set_feature(&cpu->env, ARM_FEATURE_VFP3); 1072 } 1073 if (arm_feature(&cpu->env, ARM_FEATURE_VFP3)) { 1074 set_feature(&cpu->env, ARM_FEATURE_VFP); 1075 } 1076 1077 if (arm_feature(&cpu->env, ARM_FEATURE_CBAR) || 1078 arm_feature(&cpu->env, ARM_FEATURE_CBAR_RO)) { 1079 qdev_property_add_static(DEVICE(obj), &arm_cpu_reset_cbar_property, 1080 &error_abort); 1081 } 1082 1083 if (!arm_feature(&cpu->env, ARM_FEATURE_M)) { 1084 qdev_property_add_static(DEVICE(obj), &arm_cpu_reset_hivecs_property, 1085 &error_abort); 1086 } 1087 1088 if (arm_feature(&cpu->env, ARM_FEATURE_AARCH64)) { 1089 qdev_property_add_static(DEVICE(obj), &arm_cpu_rvbar_property, 1090 &error_abort); 1091 } 1092 1093 if (arm_feature(&cpu->env, ARM_FEATURE_EL3)) { 1094 /* Add the has_el3 state CPU property only if EL3 is allowed. This will 1095 * prevent "has_el3" from existing on CPUs which cannot support EL3. 1096 */ 1097 qdev_property_add_static(DEVICE(obj), &arm_cpu_has_el3_property, 1098 &error_abort); 1099 1100 #ifndef CONFIG_USER_ONLY 1101 object_property_add_link(obj, "secure-memory", 1102 TYPE_MEMORY_REGION, 1103 (Object **)&cpu->secure_memory, 1104 qdev_prop_allow_set_link_before_realize, 1105 OBJ_PROP_LINK_STRONG, 1106 &error_abort); 1107 #endif 1108 } 1109 1110 if (arm_feature(&cpu->env, ARM_FEATURE_EL2)) { 1111 qdev_property_add_static(DEVICE(obj), &arm_cpu_has_el2_property, 1112 &error_abort); 1113 } 1114 1115 if (arm_feature(&cpu->env, ARM_FEATURE_PMU)) { 1116 cpu->has_pmu = true; 1117 object_property_add_bool(obj, "pmu", arm_get_pmu, arm_set_pmu, 1118 &error_abort); 1119 } 1120 1121 /* 1122 * Allow user to turn off VFP and Neon support, but only for TCG -- 1123 * KVM does not currently allow us to lie to the guest about its 1124 * ID/feature registers, so the guest always sees what the host has. 1125 */ 1126 if (arm_feature(&cpu->env, ARM_FEATURE_VFP)) { 1127 cpu->has_vfp = true; 1128 if (!kvm_enabled()) { 1129 qdev_property_add_static(DEVICE(obj), &arm_cpu_has_vfp_property, 1130 &error_abort); 1131 } 1132 } 1133 1134 if (arm_feature(&cpu->env, ARM_FEATURE_NEON)) { 1135 cpu->has_neon = true; 1136 if (!kvm_enabled()) { 1137 qdev_property_add_static(DEVICE(obj), &arm_cpu_has_neon_property, 1138 &error_abort); 1139 } 1140 } 1141 1142 if (arm_feature(&cpu->env, ARM_FEATURE_M) && 1143 arm_feature(&cpu->env, ARM_FEATURE_THUMB_DSP)) { 1144 qdev_property_add_static(DEVICE(obj), &arm_cpu_has_dsp_property, 1145 &error_abort); 1146 } 1147 1148 if (arm_feature(&cpu->env, ARM_FEATURE_PMSA)) { 1149 qdev_property_add_static(DEVICE(obj), &arm_cpu_has_mpu_property, 1150 &error_abort); 1151 if (arm_feature(&cpu->env, ARM_FEATURE_V7)) { 1152 qdev_property_add_static(DEVICE(obj), 1153 &arm_cpu_pmsav7_dregion_property, 1154 &error_abort); 1155 } 1156 } 1157 1158 if (arm_feature(&cpu->env, ARM_FEATURE_M_SECURITY)) { 1159 object_property_add_link(obj, "idau", TYPE_IDAU_INTERFACE, &cpu->idau, 1160 qdev_prop_allow_set_link_before_realize, 1161 OBJ_PROP_LINK_STRONG, 1162 &error_abort); 1163 /* 1164 * M profile: initial value of the Secure VTOR. We can't just use 1165 * a simple DEFINE_PROP_UINT32 for this because we want to permit 1166 * the property to be set after realize. 1167 */ 1168 object_property_add(obj, "init-svtor", "uint32", 1169 arm_get_init_svtor, arm_set_init_svtor, 1170 NULL, NULL, &error_abort); 1171 } 1172 1173 qdev_property_add_static(DEVICE(obj), &arm_cpu_cfgend_property, 1174 &error_abort); 1175 } 1176 1177 static void arm_cpu_finalizefn(Object *obj) 1178 { 1179 ARMCPU *cpu = ARM_CPU(obj); 1180 ARMELChangeHook *hook, *next; 1181 1182 g_hash_table_destroy(cpu->cp_regs); 1183 1184 QLIST_FOREACH_SAFE(hook, &cpu->pre_el_change_hooks, node, next) { 1185 QLIST_REMOVE(hook, node); 1186 g_free(hook); 1187 } 1188 QLIST_FOREACH_SAFE(hook, &cpu->el_change_hooks, node, next) { 1189 QLIST_REMOVE(hook, node); 1190 g_free(hook); 1191 } 1192 #ifndef CONFIG_USER_ONLY 1193 if (cpu->pmu_timer) { 1194 timer_del(cpu->pmu_timer); 1195 timer_deinit(cpu->pmu_timer); 1196 timer_free(cpu->pmu_timer); 1197 } 1198 #endif 1199 } 1200 1201 void arm_cpu_finalize_features(ARMCPU *cpu, Error **errp) 1202 { 1203 Error *local_err = NULL; 1204 1205 if (arm_feature(&cpu->env, ARM_FEATURE_AARCH64)) { 1206 arm_cpu_sve_finalize(cpu, &local_err); 1207 if (local_err != NULL) { 1208 error_propagate(errp, local_err); 1209 return; 1210 } 1211 } 1212 } 1213 1214 static void arm_cpu_realizefn(DeviceState *dev, Error **errp) 1215 { 1216 CPUState *cs = CPU(dev); 1217 ARMCPU *cpu = ARM_CPU(dev); 1218 ARMCPUClass *acc = ARM_CPU_GET_CLASS(dev); 1219 CPUARMState *env = &cpu->env; 1220 int pagebits; 1221 Error *local_err = NULL; 1222 bool no_aa32 = false; 1223 1224 /* If we needed to query the host kernel for the CPU features 1225 * then it's possible that might have failed in the initfn, but 1226 * this is the first point where we can report it. 1227 */ 1228 if (cpu->host_cpu_probe_failed) { 1229 if (!kvm_enabled()) { 1230 error_setg(errp, "The 'host' CPU type can only be used with KVM"); 1231 } else { 1232 error_setg(errp, "Failed to retrieve host CPU features"); 1233 } 1234 return; 1235 } 1236 1237 #ifndef CONFIG_USER_ONLY 1238 /* The NVIC and M-profile CPU are two halves of a single piece of 1239 * hardware; trying to use one without the other is a command line 1240 * error and will result in segfaults if not caught here. 1241 */ 1242 if (arm_feature(env, ARM_FEATURE_M)) { 1243 if (!env->nvic) { 1244 error_setg(errp, "This board cannot be used with Cortex-M CPUs"); 1245 return; 1246 } 1247 } else { 1248 if (env->nvic) { 1249 error_setg(errp, "This board can only be used with Cortex-M CPUs"); 1250 return; 1251 } 1252 } 1253 1254 cpu->gt_timer[GTIMER_PHYS] = timer_new(QEMU_CLOCK_VIRTUAL, GTIMER_SCALE, 1255 arm_gt_ptimer_cb, cpu); 1256 cpu->gt_timer[GTIMER_VIRT] = timer_new(QEMU_CLOCK_VIRTUAL, GTIMER_SCALE, 1257 arm_gt_vtimer_cb, cpu); 1258 cpu->gt_timer[GTIMER_HYP] = timer_new(QEMU_CLOCK_VIRTUAL, GTIMER_SCALE, 1259 arm_gt_htimer_cb, cpu); 1260 cpu->gt_timer[GTIMER_SEC] = timer_new(QEMU_CLOCK_VIRTUAL, GTIMER_SCALE, 1261 arm_gt_stimer_cb, cpu); 1262 #endif 1263 1264 cpu_exec_realizefn(cs, &local_err); 1265 if (local_err != NULL) { 1266 error_propagate(errp, local_err); 1267 return; 1268 } 1269 1270 arm_cpu_finalize_features(cpu, &local_err); 1271 if (local_err != NULL) { 1272 error_propagate(errp, local_err); 1273 return; 1274 } 1275 1276 if (arm_feature(env, ARM_FEATURE_AARCH64) && 1277 cpu->has_vfp != cpu->has_neon) { 1278 /* 1279 * This is an architectural requirement for AArch64; AArch32 is 1280 * more flexible and permits VFP-no-Neon and Neon-no-VFP. 1281 */ 1282 error_setg(errp, 1283 "AArch64 CPUs must have both VFP and Neon or neither"); 1284 return; 1285 } 1286 1287 if (!cpu->has_vfp) { 1288 uint64_t t; 1289 uint32_t u; 1290 1291 unset_feature(env, ARM_FEATURE_VFP); 1292 unset_feature(env, ARM_FEATURE_VFP3); 1293 unset_feature(env, ARM_FEATURE_VFP4); 1294 1295 t = cpu->isar.id_aa64isar1; 1296 t = FIELD_DP64(t, ID_AA64ISAR1, JSCVT, 0); 1297 cpu->isar.id_aa64isar1 = t; 1298 1299 t = cpu->isar.id_aa64pfr0; 1300 t = FIELD_DP64(t, ID_AA64PFR0, FP, 0xf); 1301 cpu->isar.id_aa64pfr0 = t; 1302 1303 u = cpu->isar.id_isar6; 1304 u = FIELD_DP32(u, ID_ISAR6, JSCVT, 0); 1305 cpu->isar.id_isar6 = u; 1306 1307 u = cpu->isar.mvfr0; 1308 u = FIELD_DP32(u, MVFR0, FPSP, 0); 1309 u = FIELD_DP32(u, MVFR0, FPDP, 0); 1310 u = FIELD_DP32(u, MVFR0, FPTRAP, 0); 1311 u = FIELD_DP32(u, MVFR0, FPDIVIDE, 0); 1312 u = FIELD_DP32(u, MVFR0, FPSQRT, 0); 1313 u = FIELD_DP32(u, MVFR0, FPSHVEC, 0); 1314 u = FIELD_DP32(u, MVFR0, FPROUND, 0); 1315 cpu->isar.mvfr0 = u; 1316 1317 u = cpu->isar.mvfr1; 1318 u = FIELD_DP32(u, MVFR1, FPFTZ, 0); 1319 u = FIELD_DP32(u, MVFR1, FPDNAN, 0); 1320 u = FIELD_DP32(u, MVFR1, FPHP, 0); 1321 cpu->isar.mvfr1 = u; 1322 1323 u = cpu->isar.mvfr2; 1324 u = FIELD_DP32(u, MVFR2, FPMISC, 0); 1325 cpu->isar.mvfr2 = u; 1326 } 1327 1328 if (!cpu->has_neon) { 1329 uint64_t t; 1330 uint32_t u; 1331 1332 unset_feature(env, ARM_FEATURE_NEON); 1333 1334 t = cpu->isar.id_aa64isar0; 1335 t = FIELD_DP64(t, ID_AA64ISAR0, DP, 0); 1336 cpu->isar.id_aa64isar0 = t; 1337 1338 t = cpu->isar.id_aa64isar1; 1339 t = FIELD_DP64(t, ID_AA64ISAR1, FCMA, 0); 1340 cpu->isar.id_aa64isar1 = t; 1341 1342 t = cpu->isar.id_aa64pfr0; 1343 t = FIELD_DP64(t, ID_AA64PFR0, ADVSIMD, 0xf); 1344 cpu->isar.id_aa64pfr0 = t; 1345 1346 u = cpu->isar.id_isar5; 1347 u = FIELD_DP32(u, ID_ISAR5, RDM, 0); 1348 u = FIELD_DP32(u, ID_ISAR5, VCMA, 0); 1349 cpu->isar.id_isar5 = u; 1350 1351 u = cpu->isar.id_isar6; 1352 u = FIELD_DP32(u, ID_ISAR6, DP, 0); 1353 u = FIELD_DP32(u, ID_ISAR6, FHM, 0); 1354 cpu->isar.id_isar6 = u; 1355 1356 u = cpu->isar.mvfr1; 1357 u = FIELD_DP32(u, MVFR1, SIMDLS, 0); 1358 u = FIELD_DP32(u, MVFR1, SIMDINT, 0); 1359 u = FIELD_DP32(u, MVFR1, SIMDSP, 0); 1360 u = FIELD_DP32(u, MVFR1, SIMDHP, 0); 1361 u = FIELD_DP32(u, MVFR1, SIMDFMAC, 0); 1362 cpu->isar.mvfr1 = u; 1363 1364 u = cpu->isar.mvfr2; 1365 u = FIELD_DP32(u, MVFR2, SIMDMISC, 0); 1366 cpu->isar.mvfr2 = u; 1367 } 1368 1369 if (!cpu->has_neon && !cpu->has_vfp) { 1370 uint64_t t; 1371 uint32_t u; 1372 1373 t = cpu->isar.id_aa64isar0; 1374 t = FIELD_DP64(t, ID_AA64ISAR0, FHM, 0); 1375 cpu->isar.id_aa64isar0 = t; 1376 1377 t = cpu->isar.id_aa64isar1; 1378 t = FIELD_DP64(t, ID_AA64ISAR1, FRINTTS, 0); 1379 cpu->isar.id_aa64isar1 = t; 1380 1381 u = cpu->isar.mvfr0; 1382 u = FIELD_DP32(u, MVFR0, SIMDREG, 0); 1383 cpu->isar.mvfr0 = u; 1384 } 1385 1386 if (arm_feature(env, ARM_FEATURE_M) && !cpu->has_dsp) { 1387 uint32_t u; 1388 1389 unset_feature(env, ARM_FEATURE_THUMB_DSP); 1390 1391 u = cpu->isar.id_isar1; 1392 u = FIELD_DP32(u, ID_ISAR1, EXTEND, 1); 1393 cpu->isar.id_isar1 = u; 1394 1395 u = cpu->isar.id_isar2; 1396 u = FIELD_DP32(u, ID_ISAR2, MULTU, 1); 1397 u = FIELD_DP32(u, ID_ISAR2, MULTS, 1); 1398 cpu->isar.id_isar2 = u; 1399 1400 u = cpu->isar.id_isar3; 1401 u = FIELD_DP32(u, ID_ISAR3, SIMD, 1); 1402 u = FIELD_DP32(u, ID_ISAR3, SATURATE, 0); 1403 cpu->isar.id_isar3 = u; 1404 } 1405 1406 /* Some features automatically imply others: */ 1407 if (arm_feature(env, ARM_FEATURE_V8)) { 1408 if (arm_feature(env, ARM_FEATURE_M)) { 1409 set_feature(env, ARM_FEATURE_V7); 1410 } else { 1411 set_feature(env, ARM_FEATURE_V7VE); 1412 } 1413 } 1414 1415 /* 1416 * There exist AArch64 cpus without AArch32 support. When KVM 1417 * queries ID_ISAR0_EL1 on such a host, the value is UNKNOWN. 1418 * Similarly, we cannot check ID_AA64PFR0 without AArch64 support. 1419 * As a general principle, we also do not make ID register 1420 * consistency checks anywhere unless using TCG, because only 1421 * for TCG would a consistency-check failure be a QEMU bug. 1422 */ 1423 if (arm_feature(&cpu->env, ARM_FEATURE_AARCH64)) { 1424 no_aa32 = !cpu_isar_feature(aa64_aa32, cpu); 1425 } 1426 1427 if (arm_feature(env, ARM_FEATURE_V7VE)) { 1428 /* v7 Virtualization Extensions. In real hardware this implies 1429 * EL2 and also the presence of the Security Extensions. 1430 * For QEMU, for backwards-compatibility we implement some 1431 * CPUs or CPU configs which have no actual EL2 or EL3 but do 1432 * include the various other features that V7VE implies. 1433 * Presence of EL2 itself is ARM_FEATURE_EL2, and of the 1434 * Security Extensions is ARM_FEATURE_EL3. 1435 */ 1436 assert(!tcg_enabled() || no_aa32 || cpu_isar_feature(arm_div, cpu)); 1437 set_feature(env, ARM_FEATURE_LPAE); 1438 set_feature(env, ARM_FEATURE_V7); 1439 } 1440 if (arm_feature(env, ARM_FEATURE_V7)) { 1441 set_feature(env, ARM_FEATURE_VAPA); 1442 set_feature(env, ARM_FEATURE_THUMB2); 1443 set_feature(env, ARM_FEATURE_MPIDR); 1444 if (!arm_feature(env, ARM_FEATURE_M)) { 1445 set_feature(env, ARM_FEATURE_V6K); 1446 } else { 1447 set_feature(env, ARM_FEATURE_V6); 1448 } 1449 1450 /* Always define VBAR for V7 CPUs even if it doesn't exist in 1451 * non-EL3 configs. This is needed by some legacy boards. 1452 */ 1453 set_feature(env, ARM_FEATURE_VBAR); 1454 } 1455 if (arm_feature(env, ARM_FEATURE_V6K)) { 1456 set_feature(env, ARM_FEATURE_V6); 1457 set_feature(env, ARM_FEATURE_MVFR); 1458 } 1459 if (arm_feature(env, ARM_FEATURE_V6)) { 1460 set_feature(env, ARM_FEATURE_V5); 1461 if (!arm_feature(env, ARM_FEATURE_M)) { 1462 assert(!tcg_enabled() || no_aa32 || cpu_isar_feature(jazelle, cpu)); 1463 set_feature(env, ARM_FEATURE_AUXCR); 1464 } 1465 } 1466 if (arm_feature(env, ARM_FEATURE_V5)) { 1467 set_feature(env, ARM_FEATURE_V4T); 1468 } 1469 if (arm_feature(env, ARM_FEATURE_LPAE)) { 1470 set_feature(env, ARM_FEATURE_V7MP); 1471 set_feature(env, ARM_FEATURE_PXN); 1472 } 1473 if (arm_feature(env, ARM_FEATURE_CBAR_RO)) { 1474 set_feature(env, ARM_FEATURE_CBAR); 1475 } 1476 if (arm_feature(env, ARM_FEATURE_THUMB2) && 1477 !arm_feature(env, ARM_FEATURE_M)) { 1478 set_feature(env, ARM_FEATURE_THUMB_DSP); 1479 } 1480 1481 /* 1482 * We rely on no XScale CPU having VFP so we can use the same bits in the 1483 * TB flags field for VECSTRIDE and XSCALE_CPAR. 1484 */ 1485 assert(!(arm_feature(env, ARM_FEATURE_VFP) && 1486 arm_feature(env, ARM_FEATURE_XSCALE))); 1487 1488 if (arm_feature(env, ARM_FEATURE_V7) && 1489 !arm_feature(env, ARM_FEATURE_M) && 1490 !arm_feature(env, ARM_FEATURE_PMSA)) { 1491 /* v7VMSA drops support for the old ARMv5 tiny pages, so we 1492 * can use 4K pages. 1493 */ 1494 pagebits = 12; 1495 } else { 1496 /* For CPUs which might have tiny 1K pages, or which have an 1497 * MPU and might have small region sizes, stick with 1K pages. 1498 */ 1499 pagebits = 10; 1500 } 1501 if (!set_preferred_target_page_bits(pagebits)) { 1502 /* This can only ever happen for hotplugging a CPU, or if 1503 * the board code incorrectly creates a CPU which it has 1504 * promised via minimum_page_size that it will not. 1505 */ 1506 error_setg(errp, "This CPU requires a smaller page size than the " 1507 "system is using"); 1508 return; 1509 } 1510 1511 /* This cpu-id-to-MPIDR affinity is used only for TCG; KVM will override it. 1512 * We don't support setting cluster ID ([16..23]) (known as Aff2 1513 * in later ARM ARM versions), or any of the higher affinity level fields, 1514 * so these bits always RAZ. 1515 */ 1516 if (cpu->mp_affinity == ARM64_AFFINITY_INVALID) { 1517 cpu->mp_affinity = arm_cpu_mp_affinity(cs->cpu_index, 1518 ARM_DEFAULT_CPUS_PER_CLUSTER); 1519 } 1520 1521 if (cpu->reset_hivecs) { 1522 cpu->reset_sctlr |= (1 << 13); 1523 } 1524 1525 if (cpu->cfgend) { 1526 if (arm_feature(&cpu->env, ARM_FEATURE_V7)) { 1527 cpu->reset_sctlr |= SCTLR_EE; 1528 } else { 1529 cpu->reset_sctlr |= SCTLR_B; 1530 } 1531 } 1532 1533 if (!cpu->has_el3) { 1534 /* If the has_el3 CPU property is disabled then we need to disable the 1535 * feature. 1536 */ 1537 unset_feature(env, ARM_FEATURE_EL3); 1538 1539 /* Disable the security extension feature bits in the processor feature 1540 * registers as well. These are id_pfr1[7:4] and id_aa64pfr0[15:12]. 1541 */ 1542 cpu->id_pfr1 &= ~0xf0; 1543 cpu->isar.id_aa64pfr0 &= ~0xf000; 1544 } 1545 1546 if (!cpu->has_el2) { 1547 unset_feature(env, ARM_FEATURE_EL2); 1548 } 1549 1550 if (!cpu->has_pmu) { 1551 unset_feature(env, ARM_FEATURE_PMU); 1552 } 1553 if (arm_feature(env, ARM_FEATURE_PMU)) { 1554 pmu_init(cpu); 1555 1556 if (!kvm_enabled()) { 1557 arm_register_pre_el_change_hook(cpu, &pmu_pre_el_change, 0); 1558 arm_register_el_change_hook(cpu, &pmu_post_el_change, 0); 1559 } 1560 1561 #ifndef CONFIG_USER_ONLY 1562 cpu->pmu_timer = timer_new_ns(QEMU_CLOCK_VIRTUAL, arm_pmu_timer_cb, 1563 cpu); 1564 #endif 1565 } else { 1566 cpu->id_aa64dfr0 &= ~0xf00; 1567 cpu->id_dfr0 &= ~(0xf << 24); 1568 cpu->pmceid0 = 0; 1569 cpu->pmceid1 = 0; 1570 } 1571 1572 if (!arm_feature(env, ARM_FEATURE_EL2)) { 1573 /* Disable the hypervisor feature bits in the processor feature 1574 * registers if we don't have EL2. These are id_pfr1[15:12] and 1575 * id_aa64pfr0_el1[11:8]. 1576 */ 1577 cpu->isar.id_aa64pfr0 &= ~0xf00; 1578 cpu->id_pfr1 &= ~0xf000; 1579 } 1580 1581 /* MPU can be configured out of a PMSA CPU either by setting has-mpu 1582 * to false or by setting pmsav7-dregion to 0. 1583 */ 1584 if (!cpu->has_mpu) { 1585 cpu->pmsav7_dregion = 0; 1586 } 1587 if (cpu->pmsav7_dregion == 0) { 1588 cpu->has_mpu = false; 1589 } 1590 1591 if (arm_feature(env, ARM_FEATURE_PMSA) && 1592 arm_feature(env, ARM_FEATURE_V7)) { 1593 uint32_t nr = cpu->pmsav7_dregion; 1594 1595 if (nr > 0xff) { 1596 error_setg(errp, "PMSAv7 MPU #regions invalid %" PRIu32, nr); 1597 return; 1598 } 1599 1600 if (nr) { 1601 if (arm_feature(env, ARM_FEATURE_V8)) { 1602 /* PMSAv8 */ 1603 env->pmsav8.rbar[M_REG_NS] = g_new0(uint32_t, nr); 1604 env->pmsav8.rlar[M_REG_NS] = g_new0(uint32_t, nr); 1605 if (arm_feature(env, ARM_FEATURE_M_SECURITY)) { 1606 env->pmsav8.rbar[M_REG_S] = g_new0(uint32_t, nr); 1607 env->pmsav8.rlar[M_REG_S] = g_new0(uint32_t, nr); 1608 } 1609 } else { 1610 env->pmsav7.drbar = g_new0(uint32_t, nr); 1611 env->pmsav7.drsr = g_new0(uint32_t, nr); 1612 env->pmsav7.dracr = g_new0(uint32_t, nr); 1613 } 1614 } 1615 } 1616 1617 if (arm_feature(env, ARM_FEATURE_M_SECURITY)) { 1618 uint32_t nr = cpu->sau_sregion; 1619 1620 if (nr > 0xff) { 1621 error_setg(errp, "v8M SAU #regions invalid %" PRIu32, nr); 1622 return; 1623 } 1624 1625 if (nr) { 1626 env->sau.rbar = g_new0(uint32_t, nr); 1627 env->sau.rlar = g_new0(uint32_t, nr); 1628 } 1629 } 1630 1631 if (arm_feature(env, ARM_FEATURE_EL3)) { 1632 set_feature(env, ARM_FEATURE_VBAR); 1633 } 1634 1635 register_cp_regs_for_features(cpu); 1636 arm_cpu_register_gdb_regs_for_features(cpu); 1637 1638 init_cpreg_list(cpu); 1639 1640 #ifndef CONFIG_USER_ONLY 1641 MachineState *ms = MACHINE(qdev_get_machine()); 1642 unsigned int smp_cpus = ms->smp.cpus; 1643 1644 if (cpu->has_el3 || arm_feature(env, ARM_FEATURE_M_SECURITY)) { 1645 cs->num_ases = 2; 1646 1647 if (!cpu->secure_memory) { 1648 cpu->secure_memory = cs->memory; 1649 } 1650 cpu_address_space_init(cs, ARMASIdx_S, "cpu-secure-memory", 1651 cpu->secure_memory); 1652 } else { 1653 cs->num_ases = 1; 1654 } 1655 cpu_address_space_init(cs, ARMASIdx_NS, "cpu-memory", cs->memory); 1656 1657 /* No core_count specified, default to smp_cpus. */ 1658 if (cpu->core_count == -1) { 1659 cpu->core_count = smp_cpus; 1660 } 1661 #endif 1662 1663 qemu_init_vcpu(cs); 1664 cpu_reset(cs); 1665 1666 acc->parent_realize(dev, errp); 1667 } 1668 1669 static ObjectClass *arm_cpu_class_by_name(const char *cpu_model) 1670 { 1671 ObjectClass *oc; 1672 char *typename; 1673 char **cpuname; 1674 const char *cpunamestr; 1675 1676 cpuname = g_strsplit(cpu_model, ",", 1); 1677 cpunamestr = cpuname[0]; 1678 #ifdef CONFIG_USER_ONLY 1679 /* For backwards compatibility usermode emulation allows "-cpu any", 1680 * which has the same semantics as "-cpu max". 1681 */ 1682 if (!strcmp(cpunamestr, "any")) { 1683 cpunamestr = "max"; 1684 } 1685 #endif 1686 typename = g_strdup_printf(ARM_CPU_TYPE_NAME("%s"), cpunamestr); 1687 oc = object_class_by_name(typename); 1688 g_strfreev(cpuname); 1689 g_free(typename); 1690 if (!oc || !object_class_dynamic_cast(oc, TYPE_ARM_CPU) || 1691 object_class_is_abstract(oc)) { 1692 return NULL; 1693 } 1694 return oc; 1695 } 1696 1697 /* CPU models. These are not needed for the AArch64 linux-user build. */ 1698 #if !defined(CONFIG_USER_ONLY) || !defined(TARGET_AARCH64) 1699 1700 static void arm926_initfn(Object *obj) 1701 { 1702 ARMCPU *cpu = ARM_CPU(obj); 1703 1704 cpu->dtb_compatible = "arm,arm926"; 1705 set_feature(&cpu->env, ARM_FEATURE_V5); 1706 set_feature(&cpu->env, ARM_FEATURE_VFP); 1707 set_feature(&cpu->env, ARM_FEATURE_DUMMY_C15_REGS); 1708 set_feature(&cpu->env, ARM_FEATURE_CACHE_TEST_CLEAN); 1709 cpu->midr = 0x41069265; 1710 cpu->reset_fpsid = 0x41011090; 1711 cpu->ctr = 0x1dd20d2; 1712 cpu->reset_sctlr = 0x00090078; 1713 1714 /* 1715 * ARMv5 does not have the ID_ISAR registers, but we can still 1716 * set the field to indicate Jazelle support within QEMU. 1717 */ 1718 cpu->isar.id_isar1 = FIELD_DP32(cpu->isar.id_isar1, ID_ISAR1, JAZELLE, 1); 1719 /* 1720 * Similarly, we need to set MVFR0 fields to enable double precision 1721 * and short vector support even though ARMv5 doesn't have this register. 1722 */ 1723 cpu->isar.mvfr0 = FIELD_DP32(cpu->isar.mvfr0, MVFR0, FPSHVEC, 1); 1724 cpu->isar.mvfr0 = FIELD_DP32(cpu->isar.mvfr0, MVFR0, FPDP, 1); 1725 } 1726 1727 static void arm946_initfn(Object *obj) 1728 { 1729 ARMCPU *cpu = ARM_CPU(obj); 1730 1731 cpu->dtb_compatible = "arm,arm946"; 1732 set_feature(&cpu->env, ARM_FEATURE_V5); 1733 set_feature(&cpu->env, ARM_FEATURE_PMSA); 1734 set_feature(&cpu->env, ARM_FEATURE_DUMMY_C15_REGS); 1735 cpu->midr = 0x41059461; 1736 cpu->ctr = 0x0f004006; 1737 cpu->reset_sctlr = 0x00000078; 1738 } 1739 1740 static void arm1026_initfn(Object *obj) 1741 { 1742 ARMCPU *cpu = ARM_CPU(obj); 1743 1744 cpu->dtb_compatible = "arm,arm1026"; 1745 set_feature(&cpu->env, ARM_FEATURE_V5); 1746 set_feature(&cpu->env, ARM_FEATURE_VFP); 1747 set_feature(&cpu->env, ARM_FEATURE_AUXCR); 1748 set_feature(&cpu->env, ARM_FEATURE_DUMMY_C15_REGS); 1749 set_feature(&cpu->env, ARM_FEATURE_CACHE_TEST_CLEAN); 1750 cpu->midr = 0x4106a262; 1751 cpu->reset_fpsid = 0x410110a0; 1752 cpu->ctr = 0x1dd20d2; 1753 cpu->reset_sctlr = 0x00090078; 1754 cpu->reset_auxcr = 1; 1755 1756 /* 1757 * ARMv5 does not have the ID_ISAR registers, but we can still 1758 * set the field to indicate Jazelle support within QEMU. 1759 */ 1760 cpu->isar.id_isar1 = FIELD_DP32(cpu->isar.id_isar1, ID_ISAR1, JAZELLE, 1); 1761 /* 1762 * Similarly, we need to set MVFR0 fields to enable double precision 1763 * and short vector support even though ARMv5 doesn't have this register. 1764 */ 1765 cpu->isar.mvfr0 = FIELD_DP32(cpu->isar.mvfr0, MVFR0, FPSHVEC, 1); 1766 cpu->isar.mvfr0 = FIELD_DP32(cpu->isar.mvfr0, MVFR0, FPDP, 1); 1767 1768 { 1769 /* The 1026 had an IFAR at c6,c0,0,1 rather than the ARMv6 c6,c0,0,2 */ 1770 ARMCPRegInfo ifar = { 1771 .name = "IFAR", .cp = 15, .crn = 6, .crm = 0, .opc1 = 0, .opc2 = 1, 1772 .access = PL1_RW, 1773 .fieldoffset = offsetof(CPUARMState, cp15.ifar_ns), 1774 .resetvalue = 0 1775 }; 1776 define_one_arm_cp_reg(cpu, &ifar); 1777 } 1778 } 1779 1780 static void arm1136_r2_initfn(Object *obj) 1781 { 1782 ARMCPU *cpu = ARM_CPU(obj); 1783 /* What qemu calls "arm1136_r2" is actually the 1136 r0p2, ie an 1784 * older core than plain "arm1136". In particular this does not 1785 * have the v6K features. 1786 * These ID register values are correct for 1136 but may be wrong 1787 * for 1136_r2 (in particular r0p2 does not actually implement most 1788 * of the ID registers). 1789 */ 1790 1791 cpu->dtb_compatible = "arm,arm1136"; 1792 set_feature(&cpu->env, ARM_FEATURE_V6); 1793 set_feature(&cpu->env, ARM_FEATURE_VFP); 1794 set_feature(&cpu->env, ARM_FEATURE_DUMMY_C15_REGS); 1795 set_feature(&cpu->env, ARM_FEATURE_CACHE_DIRTY_REG); 1796 set_feature(&cpu->env, ARM_FEATURE_CACHE_BLOCK_OPS); 1797 cpu->midr = 0x4107b362; 1798 cpu->reset_fpsid = 0x410120b4; 1799 cpu->isar.mvfr0 = 0x11111111; 1800 cpu->isar.mvfr1 = 0x00000000; 1801 cpu->ctr = 0x1dd20d2; 1802 cpu->reset_sctlr = 0x00050078; 1803 cpu->id_pfr0 = 0x111; 1804 cpu->id_pfr1 = 0x1; 1805 cpu->id_dfr0 = 0x2; 1806 cpu->id_afr0 = 0x3; 1807 cpu->id_mmfr0 = 0x01130003; 1808 cpu->id_mmfr1 = 0x10030302; 1809 cpu->id_mmfr2 = 0x01222110; 1810 cpu->isar.id_isar0 = 0x00140011; 1811 cpu->isar.id_isar1 = 0x12002111; 1812 cpu->isar.id_isar2 = 0x11231111; 1813 cpu->isar.id_isar3 = 0x01102131; 1814 cpu->isar.id_isar4 = 0x141; 1815 cpu->reset_auxcr = 7; 1816 } 1817 1818 static void arm1136_initfn(Object *obj) 1819 { 1820 ARMCPU *cpu = ARM_CPU(obj); 1821 1822 cpu->dtb_compatible = "arm,arm1136"; 1823 set_feature(&cpu->env, ARM_FEATURE_V6K); 1824 set_feature(&cpu->env, ARM_FEATURE_V6); 1825 set_feature(&cpu->env, ARM_FEATURE_VFP); 1826 set_feature(&cpu->env, ARM_FEATURE_DUMMY_C15_REGS); 1827 set_feature(&cpu->env, ARM_FEATURE_CACHE_DIRTY_REG); 1828 set_feature(&cpu->env, ARM_FEATURE_CACHE_BLOCK_OPS); 1829 cpu->midr = 0x4117b363; 1830 cpu->reset_fpsid = 0x410120b4; 1831 cpu->isar.mvfr0 = 0x11111111; 1832 cpu->isar.mvfr1 = 0x00000000; 1833 cpu->ctr = 0x1dd20d2; 1834 cpu->reset_sctlr = 0x00050078; 1835 cpu->id_pfr0 = 0x111; 1836 cpu->id_pfr1 = 0x1; 1837 cpu->id_dfr0 = 0x2; 1838 cpu->id_afr0 = 0x3; 1839 cpu->id_mmfr0 = 0x01130003; 1840 cpu->id_mmfr1 = 0x10030302; 1841 cpu->id_mmfr2 = 0x01222110; 1842 cpu->isar.id_isar0 = 0x00140011; 1843 cpu->isar.id_isar1 = 0x12002111; 1844 cpu->isar.id_isar2 = 0x11231111; 1845 cpu->isar.id_isar3 = 0x01102131; 1846 cpu->isar.id_isar4 = 0x141; 1847 cpu->reset_auxcr = 7; 1848 } 1849 1850 static void arm1176_initfn(Object *obj) 1851 { 1852 ARMCPU *cpu = ARM_CPU(obj); 1853 1854 cpu->dtb_compatible = "arm,arm1176"; 1855 set_feature(&cpu->env, ARM_FEATURE_V6K); 1856 set_feature(&cpu->env, ARM_FEATURE_VFP); 1857 set_feature(&cpu->env, ARM_FEATURE_VAPA); 1858 set_feature(&cpu->env, ARM_FEATURE_DUMMY_C15_REGS); 1859 set_feature(&cpu->env, ARM_FEATURE_CACHE_DIRTY_REG); 1860 set_feature(&cpu->env, ARM_FEATURE_CACHE_BLOCK_OPS); 1861 set_feature(&cpu->env, ARM_FEATURE_EL3); 1862 cpu->midr = 0x410fb767; 1863 cpu->reset_fpsid = 0x410120b5; 1864 cpu->isar.mvfr0 = 0x11111111; 1865 cpu->isar.mvfr1 = 0x00000000; 1866 cpu->ctr = 0x1dd20d2; 1867 cpu->reset_sctlr = 0x00050078; 1868 cpu->id_pfr0 = 0x111; 1869 cpu->id_pfr1 = 0x11; 1870 cpu->id_dfr0 = 0x33; 1871 cpu->id_afr0 = 0; 1872 cpu->id_mmfr0 = 0x01130003; 1873 cpu->id_mmfr1 = 0x10030302; 1874 cpu->id_mmfr2 = 0x01222100; 1875 cpu->isar.id_isar0 = 0x0140011; 1876 cpu->isar.id_isar1 = 0x12002111; 1877 cpu->isar.id_isar2 = 0x11231121; 1878 cpu->isar.id_isar3 = 0x01102131; 1879 cpu->isar.id_isar4 = 0x01141; 1880 cpu->reset_auxcr = 7; 1881 } 1882 1883 static void arm11mpcore_initfn(Object *obj) 1884 { 1885 ARMCPU *cpu = ARM_CPU(obj); 1886 1887 cpu->dtb_compatible = "arm,arm11mpcore"; 1888 set_feature(&cpu->env, ARM_FEATURE_V6K); 1889 set_feature(&cpu->env, ARM_FEATURE_VFP); 1890 set_feature(&cpu->env, ARM_FEATURE_VAPA); 1891 set_feature(&cpu->env, ARM_FEATURE_MPIDR); 1892 set_feature(&cpu->env, ARM_FEATURE_DUMMY_C15_REGS); 1893 cpu->midr = 0x410fb022; 1894 cpu->reset_fpsid = 0x410120b4; 1895 cpu->isar.mvfr0 = 0x11111111; 1896 cpu->isar.mvfr1 = 0x00000000; 1897 cpu->ctr = 0x1d192992; /* 32K icache 32K dcache */ 1898 cpu->id_pfr0 = 0x111; 1899 cpu->id_pfr1 = 0x1; 1900 cpu->id_dfr0 = 0; 1901 cpu->id_afr0 = 0x2; 1902 cpu->id_mmfr0 = 0x01100103; 1903 cpu->id_mmfr1 = 0x10020302; 1904 cpu->id_mmfr2 = 0x01222000; 1905 cpu->isar.id_isar0 = 0x00100011; 1906 cpu->isar.id_isar1 = 0x12002111; 1907 cpu->isar.id_isar2 = 0x11221011; 1908 cpu->isar.id_isar3 = 0x01102131; 1909 cpu->isar.id_isar4 = 0x141; 1910 cpu->reset_auxcr = 1; 1911 } 1912 1913 static void cortex_m0_initfn(Object *obj) 1914 { 1915 ARMCPU *cpu = ARM_CPU(obj); 1916 set_feature(&cpu->env, ARM_FEATURE_V6); 1917 set_feature(&cpu->env, ARM_FEATURE_M); 1918 1919 cpu->midr = 0x410cc200; 1920 } 1921 1922 static void cortex_m3_initfn(Object *obj) 1923 { 1924 ARMCPU *cpu = ARM_CPU(obj); 1925 set_feature(&cpu->env, ARM_FEATURE_V7); 1926 set_feature(&cpu->env, ARM_FEATURE_M); 1927 set_feature(&cpu->env, ARM_FEATURE_M_MAIN); 1928 cpu->midr = 0x410fc231; 1929 cpu->pmsav7_dregion = 8; 1930 cpu->id_pfr0 = 0x00000030; 1931 cpu->id_pfr1 = 0x00000200; 1932 cpu->id_dfr0 = 0x00100000; 1933 cpu->id_afr0 = 0x00000000; 1934 cpu->id_mmfr0 = 0x00000030; 1935 cpu->id_mmfr1 = 0x00000000; 1936 cpu->id_mmfr2 = 0x00000000; 1937 cpu->id_mmfr3 = 0x00000000; 1938 cpu->isar.id_isar0 = 0x01141110; 1939 cpu->isar.id_isar1 = 0x02111000; 1940 cpu->isar.id_isar2 = 0x21112231; 1941 cpu->isar.id_isar3 = 0x01111110; 1942 cpu->isar.id_isar4 = 0x01310102; 1943 cpu->isar.id_isar5 = 0x00000000; 1944 cpu->isar.id_isar6 = 0x00000000; 1945 } 1946 1947 static void cortex_m4_initfn(Object *obj) 1948 { 1949 ARMCPU *cpu = ARM_CPU(obj); 1950 1951 set_feature(&cpu->env, ARM_FEATURE_V7); 1952 set_feature(&cpu->env, ARM_FEATURE_M); 1953 set_feature(&cpu->env, ARM_FEATURE_M_MAIN); 1954 set_feature(&cpu->env, ARM_FEATURE_THUMB_DSP); 1955 set_feature(&cpu->env, ARM_FEATURE_VFP4); 1956 cpu->midr = 0x410fc240; /* r0p0 */ 1957 cpu->pmsav7_dregion = 8; 1958 cpu->isar.mvfr0 = 0x10110021; 1959 cpu->isar.mvfr1 = 0x11000011; 1960 cpu->isar.mvfr2 = 0x00000000; 1961 cpu->id_pfr0 = 0x00000030; 1962 cpu->id_pfr1 = 0x00000200; 1963 cpu->id_dfr0 = 0x00100000; 1964 cpu->id_afr0 = 0x00000000; 1965 cpu->id_mmfr0 = 0x00000030; 1966 cpu->id_mmfr1 = 0x00000000; 1967 cpu->id_mmfr2 = 0x00000000; 1968 cpu->id_mmfr3 = 0x00000000; 1969 cpu->isar.id_isar0 = 0x01141110; 1970 cpu->isar.id_isar1 = 0x02111000; 1971 cpu->isar.id_isar2 = 0x21112231; 1972 cpu->isar.id_isar3 = 0x01111110; 1973 cpu->isar.id_isar4 = 0x01310102; 1974 cpu->isar.id_isar5 = 0x00000000; 1975 cpu->isar.id_isar6 = 0x00000000; 1976 } 1977 1978 static void cortex_m7_initfn(Object *obj) 1979 { 1980 ARMCPU *cpu = ARM_CPU(obj); 1981 1982 set_feature(&cpu->env, ARM_FEATURE_V7); 1983 set_feature(&cpu->env, ARM_FEATURE_M); 1984 set_feature(&cpu->env, ARM_FEATURE_M_MAIN); 1985 set_feature(&cpu->env, ARM_FEATURE_THUMB_DSP); 1986 set_feature(&cpu->env, ARM_FEATURE_VFP4); 1987 cpu->midr = 0x411fc272; /* r1p2 */ 1988 cpu->pmsav7_dregion = 8; 1989 cpu->isar.mvfr0 = 0x10110221; 1990 cpu->isar.mvfr1 = 0x12000011; 1991 cpu->isar.mvfr2 = 0x00000040; 1992 cpu->id_pfr0 = 0x00000030; 1993 cpu->id_pfr1 = 0x00000200; 1994 cpu->id_dfr0 = 0x00100000; 1995 cpu->id_afr0 = 0x00000000; 1996 cpu->id_mmfr0 = 0x00100030; 1997 cpu->id_mmfr1 = 0x00000000; 1998 cpu->id_mmfr2 = 0x01000000; 1999 cpu->id_mmfr3 = 0x00000000; 2000 cpu->isar.id_isar0 = 0x01101110; 2001 cpu->isar.id_isar1 = 0x02112000; 2002 cpu->isar.id_isar2 = 0x20232231; 2003 cpu->isar.id_isar3 = 0x01111131; 2004 cpu->isar.id_isar4 = 0x01310132; 2005 cpu->isar.id_isar5 = 0x00000000; 2006 cpu->isar.id_isar6 = 0x00000000; 2007 } 2008 2009 static void cortex_m33_initfn(Object *obj) 2010 { 2011 ARMCPU *cpu = ARM_CPU(obj); 2012 2013 set_feature(&cpu->env, ARM_FEATURE_V8); 2014 set_feature(&cpu->env, ARM_FEATURE_M); 2015 set_feature(&cpu->env, ARM_FEATURE_M_MAIN); 2016 set_feature(&cpu->env, ARM_FEATURE_M_SECURITY); 2017 set_feature(&cpu->env, ARM_FEATURE_THUMB_DSP); 2018 set_feature(&cpu->env, ARM_FEATURE_VFP4); 2019 cpu->midr = 0x410fd213; /* r0p3 */ 2020 cpu->pmsav7_dregion = 16; 2021 cpu->sau_sregion = 8; 2022 cpu->isar.mvfr0 = 0x10110021; 2023 cpu->isar.mvfr1 = 0x11000011; 2024 cpu->isar.mvfr2 = 0x00000040; 2025 cpu->id_pfr0 = 0x00000030; 2026 cpu->id_pfr1 = 0x00000210; 2027 cpu->id_dfr0 = 0x00200000; 2028 cpu->id_afr0 = 0x00000000; 2029 cpu->id_mmfr0 = 0x00101F40; 2030 cpu->id_mmfr1 = 0x00000000; 2031 cpu->id_mmfr2 = 0x01000000; 2032 cpu->id_mmfr3 = 0x00000000; 2033 cpu->isar.id_isar0 = 0x01101110; 2034 cpu->isar.id_isar1 = 0x02212000; 2035 cpu->isar.id_isar2 = 0x20232232; 2036 cpu->isar.id_isar3 = 0x01111131; 2037 cpu->isar.id_isar4 = 0x01310132; 2038 cpu->isar.id_isar5 = 0x00000000; 2039 cpu->isar.id_isar6 = 0x00000000; 2040 cpu->clidr = 0x00000000; 2041 cpu->ctr = 0x8000c000; 2042 } 2043 2044 static void arm_v7m_class_init(ObjectClass *oc, void *data) 2045 { 2046 ARMCPUClass *acc = ARM_CPU_CLASS(oc); 2047 CPUClass *cc = CPU_CLASS(oc); 2048 2049 acc->info = data; 2050 #ifndef CONFIG_USER_ONLY 2051 cc->do_interrupt = arm_v7m_cpu_do_interrupt; 2052 #endif 2053 2054 cc->cpu_exec_interrupt = arm_v7m_cpu_exec_interrupt; 2055 } 2056 2057 static const ARMCPRegInfo cortexr5_cp_reginfo[] = { 2058 /* Dummy the TCM region regs for the moment */ 2059 { .name = "ATCM", .cp = 15, .opc1 = 0, .crn = 9, .crm = 1, .opc2 = 0, 2060 .access = PL1_RW, .type = ARM_CP_CONST }, 2061 { .name = "BTCM", .cp = 15, .opc1 = 0, .crn = 9, .crm = 1, .opc2 = 1, 2062 .access = PL1_RW, .type = ARM_CP_CONST }, 2063 { .name = "DCACHE_INVAL", .cp = 15, .opc1 = 0, .crn = 15, .crm = 5, 2064 .opc2 = 0, .access = PL1_W, .type = ARM_CP_NOP }, 2065 REGINFO_SENTINEL 2066 }; 2067 2068 static void cortex_r5_initfn(Object *obj) 2069 { 2070 ARMCPU *cpu = ARM_CPU(obj); 2071 2072 set_feature(&cpu->env, ARM_FEATURE_V7); 2073 set_feature(&cpu->env, ARM_FEATURE_V7MP); 2074 set_feature(&cpu->env, ARM_FEATURE_PMSA); 2075 cpu->midr = 0x411fc153; /* r1p3 */ 2076 cpu->id_pfr0 = 0x0131; 2077 cpu->id_pfr1 = 0x001; 2078 cpu->id_dfr0 = 0x010400; 2079 cpu->id_afr0 = 0x0; 2080 cpu->id_mmfr0 = 0x0210030; 2081 cpu->id_mmfr1 = 0x00000000; 2082 cpu->id_mmfr2 = 0x01200000; 2083 cpu->id_mmfr3 = 0x0211; 2084 cpu->isar.id_isar0 = 0x02101111; 2085 cpu->isar.id_isar1 = 0x13112111; 2086 cpu->isar.id_isar2 = 0x21232141; 2087 cpu->isar.id_isar3 = 0x01112131; 2088 cpu->isar.id_isar4 = 0x0010142; 2089 cpu->isar.id_isar5 = 0x0; 2090 cpu->isar.id_isar6 = 0x0; 2091 cpu->mp_is_up = true; 2092 cpu->pmsav7_dregion = 16; 2093 define_arm_cp_regs(cpu, cortexr5_cp_reginfo); 2094 } 2095 2096 static void cortex_r5f_initfn(Object *obj) 2097 { 2098 ARMCPU *cpu = ARM_CPU(obj); 2099 2100 cortex_r5_initfn(obj); 2101 set_feature(&cpu->env, ARM_FEATURE_VFP3); 2102 cpu->isar.mvfr0 = 0x10110221; 2103 cpu->isar.mvfr1 = 0x00000011; 2104 } 2105 2106 static const ARMCPRegInfo cortexa8_cp_reginfo[] = { 2107 { .name = "L2LOCKDOWN", .cp = 15, .crn = 9, .crm = 0, .opc1 = 1, .opc2 = 0, 2108 .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0 }, 2109 { .name = "L2AUXCR", .cp = 15, .crn = 9, .crm = 0, .opc1 = 1, .opc2 = 2, 2110 .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0 }, 2111 REGINFO_SENTINEL 2112 }; 2113 2114 static void cortex_a8_initfn(Object *obj) 2115 { 2116 ARMCPU *cpu = ARM_CPU(obj); 2117 2118 cpu->dtb_compatible = "arm,cortex-a8"; 2119 set_feature(&cpu->env, ARM_FEATURE_V7); 2120 set_feature(&cpu->env, ARM_FEATURE_VFP3); 2121 set_feature(&cpu->env, ARM_FEATURE_NEON); 2122 set_feature(&cpu->env, ARM_FEATURE_THUMB2EE); 2123 set_feature(&cpu->env, ARM_FEATURE_DUMMY_C15_REGS); 2124 set_feature(&cpu->env, ARM_FEATURE_EL3); 2125 cpu->midr = 0x410fc080; 2126 cpu->reset_fpsid = 0x410330c0; 2127 cpu->isar.mvfr0 = 0x11110222; 2128 cpu->isar.mvfr1 = 0x00011111; 2129 cpu->ctr = 0x82048004; 2130 cpu->reset_sctlr = 0x00c50078; 2131 cpu->id_pfr0 = 0x1031; 2132 cpu->id_pfr1 = 0x11; 2133 cpu->id_dfr0 = 0x400; 2134 cpu->id_afr0 = 0; 2135 cpu->id_mmfr0 = 0x31100003; 2136 cpu->id_mmfr1 = 0x20000000; 2137 cpu->id_mmfr2 = 0x01202000; 2138 cpu->id_mmfr3 = 0x11; 2139 cpu->isar.id_isar0 = 0x00101111; 2140 cpu->isar.id_isar1 = 0x12112111; 2141 cpu->isar.id_isar2 = 0x21232031; 2142 cpu->isar.id_isar3 = 0x11112131; 2143 cpu->isar.id_isar4 = 0x00111142; 2144 cpu->dbgdidr = 0x15141000; 2145 cpu->clidr = (1 << 27) | (2 << 24) | 3; 2146 cpu->ccsidr[0] = 0xe007e01a; /* 16k L1 dcache. */ 2147 cpu->ccsidr[1] = 0x2007e01a; /* 16k L1 icache. */ 2148 cpu->ccsidr[2] = 0xf0000000; /* No L2 icache. */ 2149 cpu->reset_auxcr = 2; 2150 define_arm_cp_regs(cpu, cortexa8_cp_reginfo); 2151 } 2152 2153 static const ARMCPRegInfo cortexa9_cp_reginfo[] = { 2154 /* power_control should be set to maximum latency. Again, 2155 * default to 0 and set by private hook 2156 */ 2157 { .name = "A9_PWRCTL", .cp = 15, .crn = 15, .crm = 0, .opc1 = 0, .opc2 = 0, 2158 .access = PL1_RW, .resetvalue = 0, 2159 .fieldoffset = offsetof(CPUARMState, cp15.c15_power_control) }, 2160 { .name = "A9_DIAG", .cp = 15, .crn = 15, .crm = 0, .opc1 = 0, .opc2 = 1, 2161 .access = PL1_RW, .resetvalue = 0, 2162 .fieldoffset = offsetof(CPUARMState, cp15.c15_diagnostic) }, 2163 { .name = "A9_PWRDIAG", .cp = 15, .crn = 15, .crm = 0, .opc1 = 0, .opc2 = 2, 2164 .access = PL1_RW, .resetvalue = 0, 2165 .fieldoffset = offsetof(CPUARMState, cp15.c15_power_diagnostic) }, 2166 { .name = "NEONBUSY", .cp = 15, .crn = 15, .crm = 1, .opc1 = 0, .opc2 = 0, 2167 .access = PL1_RW, .resetvalue = 0, .type = ARM_CP_CONST }, 2168 /* TLB lockdown control */ 2169 { .name = "TLB_LOCKR", .cp = 15, .crn = 15, .crm = 4, .opc1 = 5, .opc2 = 2, 2170 .access = PL1_W, .resetvalue = 0, .type = ARM_CP_NOP }, 2171 { .name = "TLB_LOCKW", .cp = 15, .crn = 15, .crm = 4, .opc1 = 5, .opc2 = 4, 2172 .access = PL1_W, .resetvalue = 0, .type = ARM_CP_NOP }, 2173 { .name = "TLB_VA", .cp = 15, .crn = 15, .crm = 5, .opc1 = 5, .opc2 = 2, 2174 .access = PL1_RW, .resetvalue = 0, .type = ARM_CP_CONST }, 2175 { .name = "TLB_PA", .cp = 15, .crn = 15, .crm = 6, .opc1 = 5, .opc2 = 2, 2176 .access = PL1_RW, .resetvalue = 0, .type = ARM_CP_CONST }, 2177 { .name = "TLB_ATTR", .cp = 15, .crn = 15, .crm = 7, .opc1 = 5, .opc2 = 2, 2178 .access = PL1_RW, .resetvalue = 0, .type = ARM_CP_CONST }, 2179 REGINFO_SENTINEL 2180 }; 2181 2182 static void cortex_a9_initfn(Object *obj) 2183 { 2184 ARMCPU *cpu = ARM_CPU(obj); 2185 2186 cpu->dtb_compatible = "arm,cortex-a9"; 2187 set_feature(&cpu->env, ARM_FEATURE_V7); 2188 set_feature(&cpu->env, ARM_FEATURE_VFP3); 2189 set_feature(&cpu->env, ARM_FEATURE_NEON); 2190 set_feature(&cpu->env, ARM_FEATURE_THUMB2EE); 2191 set_feature(&cpu->env, ARM_FEATURE_EL3); 2192 /* Note that A9 supports the MP extensions even for 2193 * A9UP and single-core A9MP (which are both different 2194 * and valid configurations; we don't model A9UP). 2195 */ 2196 set_feature(&cpu->env, ARM_FEATURE_V7MP); 2197 set_feature(&cpu->env, ARM_FEATURE_CBAR); 2198 cpu->midr = 0x410fc090; 2199 cpu->reset_fpsid = 0x41033090; 2200 cpu->isar.mvfr0 = 0x11110222; 2201 cpu->isar.mvfr1 = 0x01111111; 2202 cpu->ctr = 0x80038003; 2203 cpu->reset_sctlr = 0x00c50078; 2204 cpu->id_pfr0 = 0x1031; 2205 cpu->id_pfr1 = 0x11; 2206 cpu->id_dfr0 = 0x000; 2207 cpu->id_afr0 = 0; 2208 cpu->id_mmfr0 = 0x00100103; 2209 cpu->id_mmfr1 = 0x20000000; 2210 cpu->id_mmfr2 = 0x01230000; 2211 cpu->id_mmfr3 = 0x00002111; 2212 cpu->isar.id_isar0 = 0x00101111; 2213 cpu->isar.id_isar1 = 0x13112111; 2214 cpu->isar.id_isar2 = 0x21232041; 2215 cpu->isar.id_isar3 = 0x11112131; 2216 cpu->isar.id_isar4 = 0x00111142; 2217 cpu->dbgdidr = 0x35141000; 2218 cpu->clidr = (1 << 27) | (1 << 24) | 3; 2219 cpu->ccsidr[0] = 0xe00fe019; /* 16k L1 dcache. */ 2220 cpu->ccsidr[1] = 0x200fe019; /* 16k L1 icache. */ 2221 define_arm_cp_regs(cpu, cortexa9_cp_reginfo); 2222 } 2223 2224 #ifndef CONFIG_USER_ONLY 2225 static uint64_t a15_l2ctlr_read(CPUARMState *env, const ARMCPRegInfo *ri) 2226 { 2227 MachineState *ms = MACHINE(qdev_get_machine()); 2228 2229 /* Linux wants the number of processors from here. 2230 * Might as well set the interrupt-controller bit too. 2231 */ 2232 return ((ms->smp.cpus - 1) << 24) | (1 << 23); 2233 } 2234 #endif 2235 2236 static const ARMCPRegInfo cortexa15_cp_reginfo[] = { 2237 #ifndef CONFIG_USER_ONLY 2238 { .name = "L2CTLR", .cp = 15, .crn = 9, .crm = 0, .opc1 = 1, .opc2 = 2, 2239 .access = PL1_RW, .resetvalue = 0, .readfn = a15_l2ctlr_read, 2240 .writefn = arm_cp_write_ignore, }, 2241 #endif 2242 { .name = "L2ECTLR", .cp = 15, .crn = 9, .crm = 0, .opc1 = 1, .opc2 = 3, 2243 .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0 }, 2244 REGINFO_SENTINEL 2245 }; 2246 2247 static void cortex_a7_initfn(Object *obj) 2248 { 2249 ARMCPU *cpu = ARM_CPU(obj); 2250 2251 cpu->dtb_compatible = "arm,cortex-a7"; 2252 set_feature(&cpu->env, ARM_FEATURE_V7VE); 2253 set_feature(&cpu->env, ARM_FEATURE_VFP4); 2254 set_feature(&cpu->env, ARM_FEATURE_NEON); 2255 set_feature(&cpu->env, ARM_FEATURE_THUMB2EE); 2256 set_feature(&cpu->env, ARM_FEATURE_GENERIC_TIMER); 2257 set_feature(&cpu->env, ARM_FEATURE_DUMMY_C15_REGS); 2258 set_feature(&cpu->env, ARM_FEATURE_CBAR_RO); 2259 set_feature(&cpu->env, ARM_FEATURE_EL2); 2260 set_feature(&cpu->env, ARM_FEATURE_EL3); 2261 set_feature(&cpu->env, ARM_FEATURE_PMU); 2262 cpu->kvm_target = QEMU_KVM_ARM_TARGET_CORTEX_A7; 2263 cpu->midr = 0x410fc075; 2264 cpu->reset_fpsid = 0x41023075; 2265 cpu->isar.mvfr0 = 0x10110222; 2266 cpu->isar.mvfr1 = 0x11111111; 2267 cpu->ctr = 0x84448003; 2268 cpu->reset_sctlr = 0x00c50078; 2269 cpu->id_pfr0 = 0x00001131; 2270 cpu->id_pfr1 = 0x00011011; 2271 cpu->id_dfr0 = 0x02010555; 2272 cpu->id_afr0 = 0x00000000; 2273 cpu->id_mmfr0 = 0x10101105; 2274 cpu->id_mmfr1 = 0x40000000; 2275 cpu->id_mmfr2 = 0x01240000; 2276 cpu->id_mmfr3 = 0x02102211; 2277 /* a7_mpcore_r0p5_trm, page 4-4 gives 0x01101110; but 2278 * table 4-41 gives 0x02101110, which includes the arm div insns. 2279 */ 2280 cpu->isar.id_isar0 = 0x02101110; 2281 cpu->isar.id_isar1 = 0x13112111; 2282 cpu->isar.id_isar2 = 0x21232041; 2283 cpu->isar.id_isar3 = 0x11112131; 2284 cpu->isar.id_isar4 = 0x10011142; 2285 cpu->dbgdidr = 0x3515f005; 2286 cpu->clidr = 0x0a200023; 2287 cpu->ccsidr[0] = 0x701fe00a; /* 32K L1 dcache */ 2288 cpu->ccsidr[1] = 0x201fe00a; /* 32K L1 icache */ 2289 cpu->ccsidr[2] = 0x711fe07a; /* 4096K L2 unified cache */ 2290 define_arm_cp_regs(cpu, cortexa15_cp_reginfo); /* Same as A15 */ 2291 } 2292 2293 static void cortex_a15_initfn(Object *obj) 2294 { 2295 ARMCPU *cpu = ARM_CPU(obj); 2296 2297 cpu->dtb_compatible = "arm,cortex-a15"; 2298 set_feature(&cpu->env, ARM_FEATURE_V7VE); 2299 set_feature(&cpu->env, ARM_FEATURE_VFP4); 2300 set_feature(&cpu->env, ARM_FEATURE_NEON); 2301 set_feature(&cpu->env, ARM_FEATURE_THUMB2EE); 2302 set_feature(&cpu->env, ARM_FEATURE_GENERIC_TIMER); 2303 set_feature(&cpu->env, ARM_FEATURE_DUMMY_C15_REGS); 2304 set_feature(&cpu->env, ARM_FEATURE_CBAR_RO); 2305 set_feature(&cpu->env, ARM_FEATURE_EL2); 2306 set_feature(&cpu->env, ARM_FEATURE_EL3); 2307 set_feature(&cpu->env, ARM_FEATURE_PMU); 2308 cpu->kvm_target = QEMU_KVM_ARM_TARGET_CORTEX_A15; 2309 cpu->midr = 0x412fc0f1; 2310 cpu->reset_fpsid = 0x410430f0; 2311 cpu->isar.mvfr0 = 0x10110222; 2312 cpu->isar.mvfr1 = 0x11111111; 2313 cpu->ctr = 0x8444c004; 2314 cpu->reset_sctlr = 0x00c50078; 2315 cpu->id_pfr0 = 0x00001131; 2316 cpu->id_pfr1 = 0x00011011; 2317 cpu->id_dfr0 = 0x02010555; 2318 cpu->id_afr0 = 0x00000000; 2319 cpu->id_mmfr0 = 0x10201105; 2320 cpu->id_mmfr1 = 0x20000000; 2321 cpu->id_mmfr2 = 0x01240000; 2322 cpu->id_mmfr3 = 0x02102211; 2323 cpu->isar.id_isar0 = 0x02101110; 2324 cpu->isar.id_isar1 = 0x13112111; 2325 cpu->isar.id_isar2 = 0x21232041; 2326 cpu->isar.id_isar3 = 0x11112131; 2327 cpu->isar.id_isar4 = 0x10011142; 2328 cpu->dbgdidr = 0x3515f021; 2329 cpu->clidr = 0x0a200023; 2330 cpu->ccsidr[0] = 0x701fe00a; /* 32K L1 dcache */ 2331 cpu->ccsidr[1] = 0x201fe00a; /* 32K L1 icache */ 2332 cpu->ccsidr[2] = 0x711fe07a; /* 4096K L2 unified cache */ 2333 define_arm_cp_regs(cpu, cortexa15_cp_reginfo); 2334 } 2335 2336 static void ti925t_initfn(Object *obj) 2337 { 2338 ARMCPU *cpu = ARM_CPU(obj); 2339 set_feature(&cpu->env, ARM_FEATURE_V4T); 2340 set_feature(&cpu->env, ARM_FEATURE_OMAPCP); 2341 cpu->midr = ARM_CPUID_TI925T; 2342 cpu->ctr = 0x5109149; 2343 cpu->reset_sctlr = 0x00000070; 2344 } 2345 2346 static void sa1100_initfn(Object *obj) 2347 { 2348 ARMCPU *cpu = ARM_CPU(obj); 2349 2350 cpu->dtb_compatible = "intel,sa1100"; 2351 set_feature(&cpu->env, ARM_FEATURE_STRONGARM); 2352 set_feature(&cpu->env, ARM_FEATURE_DUMMY_C15_REGS); 2353 cpu->midr = 0x4401A11B; 2354 cpu->reset_sctlr = 0x00000070; 2355 } 2356 2357 static void sa1110_initfn(Object *obj) 2358 { 2359 ARMCPU *cpu = ARM_CPU(obj); 2360 set_feature(&cpu->env, ARM_FEATURE_STRONGARM); 2361 set_feature(&cpu->env, ARM_FEATURE_DUMMY_C15_REGS); 2362 cpu->midr = 0x6901B119; 2363 cpu->reset_sctlr = 0x00000070; 2364 } 2365 2366 static void pxa250_initfn(Object *obj) 2367 { 2368 ARMCPU *cpu = ARM_CPU(obj); 2369 2370 cpu->dtb_compatible = "marvell,xscale"; 2371 set_feature(&cpu->env, ARM_FEATURE_V5); 2372 set_feature(&cpu->env, ARM_FEATURE_XSCALE); 2373 cpu->midr = 0x69052100; 2374 cpu->ctr = 0xd172172; 2375 cpu->reset_sctlr = 0x00000078; 2376 } 2377 2378 static void pxa255_initfn(Object *obj) 2379 { 2380 ARMCPU *cpu = ARM_CPU(obj); 2381 2382 cpu->dtb_compatible = "marvell,xscale"; 2383 set_feature(&cpu->env, ARM_FEATURE_V5); 2384 set_feature(&cpu->env, ARM_FEATURE_XSCALE); 2385 cpu->midr = 0x69052d00; 2386 cpu->ctr = 0xd172172; 2387 cpu->reset_sctlr = 0x00000078; 2388 } 2389 2390 static void pxa260_initfn(Object *obj) 2391 { 2392 ARMCPU *cpu = ARM_CPU(obj); 2393 2394 cpu->dtb_compatible = "marvell,xscale"; 2395 set_feature(&cpu->env, ARM_FEATURE_V5); 2396 set_feature(&cpu->env, ARM_FEATURE_XSCALE); 2397 cpu->midr = 0x69052903; 2398 cpu->ctr = 0xd172172; 2399 cpu->reset_sctlr = 0x00000078; 2400 } 2401 2402 static void pxa261_initfn(Object *obj) 2403 { 2404 ARMCPU *cpu = ARM_CPU(obj); 2405 2406 cpu->dtb_compatible = "marvell,xscale"; 2407 set_feature(&cpu->env, ARM_FEATURE_V5); 2408 set_feature(&cpu->env, ARM_FEATURE_XSCALE); 2409 cpu->midr = 0x69052d05; 2410 cpu->ctr = 0xd172172; 2411 cpu->reset_sctlr = 0x00000078; 2412 } 2413 2414 static void pxa262_initfn(Object *obj) 2415 { 2416 ARMCPU *cpu = ARM_CPU(obj); 2417 2418 cpu->dtb_compatible = "marvell,xscale"; 2419 set_feature(&cpu->env, ARM_FEATURE_V5); 2420 set_feature(&cpu->env, ARM_FEATURE_XSCALE); 2421 cpu->midr = 0x69052d06; 2422 cpu->ctr = 0xd172172; 2423 cpu->reset_sctlr = 0x00000078; 2424 } 2425 2426 static void pxa270a0_initfn(Object *obj) 2427 { 2428 ARMCPU *cpu = ARM_CPU(obj); 2429 2430 cpu->dtb_compatible = "marvell,xscale"; 2431 set_feature(&cpu->env, ARM_FEATURE_V5); 2432 set_feature(&cpu->env, ARM_FEATURE_XSCALE); 2433 set_feature(&cpu->env, ARM_FEATURE_IWMMXT); 2434 cpu->midr = 0x69054110; 2435 cpu->ctr = 0xd172172; 2436 cpu->reset_sctlr = 0x00000078; 2437 } 2438 2439 static void pxa270a1_initfn(Object *obj) 2440 { 2441 ARMCPU *cpu = ARM_CPU(obj); 2442 2443 cpu->dtb_compatible = "marvell,xscale"; 2444 set_feature(&cpu->env, ARM_FEATURE_V5); 2445 set_feature(&cpu->env, ARM_FEATURE_XSCALE); 2446 set_feature(&cpu->env, ARM_FEATURE_IWMMXT); 2447 cpu->midr = 0x69054111; 2448 cpu->ctr = 0xd172172; 2449 cpu->reset_sctlr = 0x00000078; 2450 } 2451 2452 static void pxa270b0_initfn(Object *obj) 2453 { 2454 ARMCPU *cpu = ARM_CPU(obj); 2455 2456 cpu->dtb_compatible = "marvell,xscale"; 2457 set_feature(&cpu->env, ARM_FEATURE_V5); 2458 set_feature(&cpu->env, ARM_FEATURE_XSCALE); 2459 set_feature(&cpu->env, ARM_FEATURE_IWMMXT); 2460 cpu->midr = 0x69054112; 2461 cpu->ctr = 0xd172172; 2462 cpu->reset_sctlr = 0x00000078; 2463 } 2464 2465 static void pxa270b1_initfn(Object *obj) 2466 { 2467 ARMCPU *cpu = ARM_CPU(obj); 2468 2469 cpu->dtb_compatible = "marvell,xscale"; 2470 set_feature(&cpu->env, ARM_FEATURE_V5); 2471 set_feature(&cpu->env, ARM_FEATURE_XSCALE); 2472 set_feature(&cpu->env, ARM_FEATURE_IWMMXT); 2473 cpu->midr = 0x69054113; 2474 cpu->ctr = 0xd172172; 2475 cpu->reset_sctlr = 0x00000078; 2476 } 2477 2478 static void pxa270c0_initfn(Object *obj) 2479 { 2480 ARMCPU *cpu = ARM_CPU(obj); 2481 2482 cpu->dtb_compatible = "marvell,xscale"; 2483 set_feature(&cpu->env, ARM_FEATURE_V5); 2484 set_feature(&cpu->env, ARM_FEATURE_XSCALE); 2485 set_feature(&cpu->env, ARM_FEATURE_IWMMXT); 2486 cpu->midr = 0x69054114; 2487 cpu->ctr = 0xd172172; 2488 cpu->reset_sctlr = 0x00000078; 2489 } 2490 2491 static void pxa270c5_initfn(Object *obj) 2492 { 2493 ARMCPU *cpu = ARM_CPU(obj); 2494 2495 cpu->dtb_compatible = "marvell,xscale"; 2496 set_feature(&cpu->env, ARM_FEATURE_V5); 2497 set_feature(&cpu->env, ARM_FEATURE_XSCALE); 2498 set_feature(&cpu->env, ARM_FEATURE_IWMMXT); 2499 cpu->midr = 0x69054117; 2500 cpu->ctr = 0xd172172; 2501 cpu->reset_sctlr = 0x00000078; 2502 } 2503 2504 #ifndef TARGET_AARCH64 2505 /* -cpu max: if KVM is enabled, like -cpu host (best possible with this host); 2506 * otherwise, a CPU with as many features enabled as our emulation supports. 2507 * The version of '-cpu max' for qemu-system-aarch64 is defined in cpu64.c; 2508 * this only needs to handle 32 bits. 2509 */ 2510 static void arm_max_initfn(Object *obj) 2511 { 2512 ARMCPU *cpu = ARM_CPU(obj); 2513 2514 if (kvm_enabled()) { 2515 kvm_arm_set_cpu_features_from_host(cpu); 2516 } else { 2517 cortex_a15_initfn(obj); 2518 2519 /* old-style VFP short-vector support */ 2520 cpu->isar.mvfr0 = FIELD_DP32(cpu->isar.mvfr0, MVFR0, FPSHVEC, 1); 2521 2522 #ifdef CONFIG_USER_ONLY 2523 /* We don't set these in system emulation mode for the moment, 2524 * since we don't correctly set (all of) the ID registers to 2525 * advertise them. 2526 */ 2527 set_feature(&cpu->env, ARM_FEATURE_V8); 2528 { 2529 uint32_t t; 2530 2531 t = cpu->isar.id_isar5; 2532 t = FIELD_DP32(t, ID_ISAR5, AES, 2); 2533 t = FIELD_DP32(t, ID_ISAR5, SHA1, 1); 2534 t = FIELD_DP32(t, ID_ISAR5, SHA2, 1); 2535 t = FIELD_DP32(t, ID_ISAR5, CRC32, 1); 2536 t = FIELD_DP32(t, ID_ISAR5, RDM, 1); 2537 t = FIELD_DP32(t, ID_ISAR5, VCMA, 1); 2538 cpu->isar.id_isar5 = t; 2539 2540 t = cpu->isar.id_isar6; 2541 t = FIELD_DP32(t, ID_ISAR6, JSCVT, 1); 2542 t = FIELD_DP32(t, ID_ISAR6, DP, 1); 2543 t = FIELD_DP32(t, ID_ISAR6, FHM, 1); 2544 t = FIELD_DP32(t, ID_ISAR6, SB, 1); 2545 t = FIELD_DP32(t, ID_ISAR6, SPECRES, 1); 2546 cpu->isar.id_isar6 = t; 2547 2548 t = cpu->isar.mvfr1; 2549 t = FIELD_DP32(t, MVFR1, FPHP, 2); /* v8.0 FP support */ 2550 cpu->isar.mvfr1 = t; 2551 2552 t = cpu->isar.mvfr2; 2553 t = FIELD_DP32(t, MVFR2, SIMDMISC, 3); /* SIMD MaxNum */ 2554 t = FIELD_DP32(t, MVFR2, FPMISC, 4); /* FP MaxNum */ 2555 cpu->isar.mvfr2 = t; 2556 2557 t = cpu->id_mmfr4; 2558 t = FIELD_DP32(t, ID_MMFR4, HPDS, 1); /* AA32HPD */ 2559 cpu->id_mmfr4 = t; 2560 } 2561 #endif 2562 } 2563 } 2564 #endif 2565 2566 #endif /* !defined(CONFIG_USER_ONLY) || !defined(TARGET_AARCH64) */ 2567 2568 struct ARMCPUInfo { 2569 const char *name; 2570 void (*initfn)(Object *obj); 2571 void (*class_init)(ObjectClass *oc, void *data); 2572 }; 2573 2574 static const ARMCPUInfo arm_cpus[] = { 2575 #if !defined(CONFIG_USER_ONLY) || !defined(TARGET_AARCH64) 2576 { .name = "arm926", .initfn = arm926_initfn }, 2577 { .name = "arm946", .initfn = arm946_initfn }, 2578 { .name = "arm1026", .initfn = arm1026_initfn }, 2579 /* What QEMU calls "arm1136-r2" is actually the 1136 r0p2, i.e. an 2580 * older core than plain "arm1136". In particular this does not 2581 * have the v6K features. 2582 */ 2583 { .name = "arm1136-r2", .initfn = arm1136_r2_initfn }, 2584 { .name = "arm1136", .initfn = arm1136_initfn }, 2585 { .name = "arm1176", .initfn = arm1176_initfn }, 2586 { .name = "arm11mpcore", .initfn = arm11mpcore_initfn }, 2587 { .name = "cortex-m0", .initfn = cortex_m0_initfn, 2588 .class_init = arm_v7m_class_init }, 2589 { .name = "cortex-m3", .initfn = cortex_m3_initfn, 2590 .class_init = arm_v7m_class_init }, 2591 { .name = "cortex-m4", .initfn = cortex_m4_initfn, 2592 .class_init = arm_v7m_class_init }, 2593 { .name = "cortex-m7", .initfn = cortex_m7_initfn, 2594 .class_init = arm_v7m_class_init }, 2595 { .name = "cortex-m33", .initfn = cortex_m33_initfn, 2596 .class_init = arm_v7m_class_init }, 2597 { .name = "cortex-r5", .initfn = cortex_r5_initfn }, 2598 { .name = "cortex-r5f", .initfn = cortex_r5f_initfn }, 2599 { .name = "cortex-a7", .initfn = cortex_a7_initfn }, 2600 { .name = "cortex-a8", .initfn = cortex_a8_initfn }, 2601 { .name = "cortex-a9", .initfn = cortex_a9_initfn }, 2602 { .name = "cortex-a15", .initfn = cortex_a15_initfn }, 2603 { .name = "ti925t", .initfn = ti925t_initfn }, 2604 { .name = "sa1100", .initfn = sa1100_initfn }, 2605 { .name = "sa1110", .initfn = sa1110_initfn }, 2606 { .name = "pxa250", .initfn = pxa250_initfn }, 2607 { .name = "pxa255", .initfn = pxa255_initfn }, 2608 { .name = "pxa260", .initfn = pxa260_initfn }, 2609 { .name = "pxa261", .initfn = pxa261_initfn }, 2610 { .name = "pxa262", .initfn = pxa262_initfn }, 2611 /* "pxa270" is an alias for "pxa270-a0" */ 2612 { .name = "pxa270", .initfn = pxa270a0_initfn }, 2613 { .name = "pxa270-a0", .initfn = pxa270a0_initfn }, 2614 { .name = "pxa270-a1", .initfn = pxa270a1_initfn }, 2615 { .name = "pxa270-b0", .initfn = pxa270b0_initfn }, 2616 { .name = "pxa270-b1", .initfn = pxa270b1_initfn }, 2617 { .name = "pxa270-c0", .initfn = pxa270c0_initfn }, 2618 { .name = "pxa270-c5", .initfn = pxa270c5_initfn }, 2619 #ifndef TARGET_AARCH64 2620 { .name = "max", .initfn = arm_max_initfn }, 2621 #endif 2622 #ifdef CONFIG_USER_ONLY 2623 { .name = "any", .initfn = arm_max_initfn }, 2624 #endif 2625 #endif 2626 { .name = NULL } 2627 }; 2628 2629 static Property arm_cpu_properties[] = { 2630 DEFINE_PROP_BOOL("start-powered-off", ARMCPU, start_powered_off, false), 2631 DEFINE_PROP_UINT32("psci-conduit", ARMCPU, psci_conduit, 0), 2632 DEFINE_PROP_UINT32("midr", ARMCPU, midr, 0), 2633 DEFINE_PROP_UINT64("mp-affinity", ARMCPU, 2634 mp_affinity, ARM64_AFFINITY_INVALID), 2635 DEFINE_PROP_INT32("node-id", ARMCPU, node_id, CPU_UNSET_NUMA_NODE_ID), 2636 DEFINE_PROP_INT32("core-count", ARMCPU, core_count, -1), 2637 DEFINE_PROP_END_OF_LIST() 2638 }; 2639 2640 static gchar *arm_gdb_arch_name(CPUState *cs) 2641 { 2642 ARMCPU *cpu = ARM_CPU(cs); 2643 CPUARMState *env = &cpu->env; 2644 2645 if (arm_feature(env, ARM_FEATURE_IWMMXT)) { 2646 return g_strdup("iwmmxt"); 2647 } 2648 return g_strdup("arm"); 2649 } 2650 2651 static void arm_cpu_class_init(ObjectClass *oc, void *data) 2652 { 2653 ARMCPUClass *acc = ARM_CPU_CLASS(oc); 2654 CPUClass *cc = CPU_CLASS(acc); 2655 DeviceClass *dc = DEVICE_CLASS(oc); 2656 2657 device_class_set_parent_realize(dc, arm_cpu_realizefn, 2658 &acc->parent_realize); 2659 dc->props = arm_cpu_properties; 2660 2661 acc->parent_reset = cc->reset; 2662 cc->reset = arm_cpu_reset; 2663 2664 cc->class_by_name = arm_cpu_class_by_name; 2665 cc->has_work = arm_cpu_has_work; 2666 cc->cpu_exec_interrupt = arm_cpu_exec_interrupt; 2667 cc->dump_state = arm_cpu_dump_state; 2668 cc->set_pc = arm_cpu_set_pc; 2669 cc->synchronize_from_tb = arm_cpu_synchronize_from_tb; 2670 cc->gdb_read_register = arm_cpu_gdb_read_register; 2671 cc->gdb_write_register = arm_cpu_gdb_write_register; 2672 #ifndef CONFIG_USER_ONLY 2673 cc->do_interrupt = arm_cpu_do_interrupt; 2674 cc->get_phys_page_attrs_debug = arm_cpu_get_phys_page_attrs_debug; 2675 cc->asidx_from_attrs = arm_asidx_from_attrs; 2676 cc->vmsd = &vmstate_arm_cpu; 2677 cc->virtio_is_big_endian = arm_cpu_virtio_is_big_endian; 2678 cc->write_elf64_note = arm_cpu_write_elf64_note; 2679 cc->write_elf32_note = arm_cpu_write_elf32_note; 2680 #endif 2681 cc->gdb_num_core_regs = 26; 2682 cc->gdb_core_xml_file = "arm-core.xml"; 2683 cc->gdb_arch_name = arm_gdb_arch_name; 2684 cc->gdb_get_dynamic_xml = arm_gdb_get_dynamic_xml; 2685 cc->gdb_stop_before_watchpoint = true; 2686 cc->disas_set_info = arm_disas_set_info; 2687 #ifdef CONFIG_TCG 2688 cc->tcg_initialize = arm_translate_init; 2689 cc->tlb_fill = arm_cpu_tlb_fill; 2690 cc->debug_excp_handler = arm_debug_excp_handler; 2691 cc->debug_check_watchpoint = arm_debug_check_watchpoint; 2692 #if !defined(CONFIG_USER_ONLY) 2693 cc->do_unaligned_access = arm_cpu_do_unaligned_access; 2694 cc->do_transaction_failed = arm_cpu_do_transaction_failed; 2695 cc->adjust_watchpoint_address = arm_adjust_watchpoint_address; 2696 #endif /* CONFIG_TCG && !CONFIG_USER_ONLY */ 2697 #endif 2698 } 2699 2700 #ifdef CONFIG_KVM 2701 static void arm_host_initfn(Object *obj) 2702 { 2703 ARMCPU *cpu = ARM_CPU(obj); 2704 2705 kvm_arm_set_cpu_features_from_host(cpu); 2706 if (arm_feature(&cpu->env, ARM_FEATURE_AARCH64)) { 2707 aarch64_add_sve_properties(obj); 2708 } 2709 arm_cpu_post_init(obj); 2710 } 2711 2712 static const TypeInfo host_arm_cpu_type_info = { 2713 .name = TYPE_ARM_HOST_CPU, 2714 #ifdef TARGET_AARCH64 2715 .parent = TYPE_AARCH64_CPU, 2716 #else 2717 .parent = TYPE_ARM_CPU, 2718 #endif 2719 .instance_init = arm_host_initfn, 2720 }; 2721 2722 #endif 2723 2724 static void arm_cpu_instance_init(Object *obj) 2725 { 2726 ARMCPUClass *acc = ARM_CPU_GET_CLASS(obj); 2727 2728 acc->info->initfn(obj); 2729 arm_cpu_post_init(obj); 2730 } 2731 2732 static void cpu_register_class_init(ObjectClass *oc, void *data) 2733 { 2734 ARMCPUClass *acc = ARM_CPU_CLASS(oc); 2735 2736 acc->info = data; 2737 } 2738 2739 static void cpu_register(const ARMCPUInfo *info) 2740 { 2741 TypeInfo type_info = { 2742 .parent = TYPE_ARM_CPU, 2743 .instance_size = sizeof(ARMCPU), 2744 .instance_init = arm_cpu_instance_init, 2745 .class_size = sizeof(ARMCPUClass), 2746 .class_init = info->class_init ?: cpu_register_class_init, 2747 .class_data = (void *)info, 2748 }; 2749 2750 type_info.name = g_strdup_printf("%s-" TYPE_ARM_CPU, info->name); 2751 type_register(&type_info); 2752 g_free((void *)type_info.name); 2753 } 2754 2755 static const TypeInfo arm_cpu_type_info = { 2756 .name = TYPE_ARM_CPU, 2757 .parent = TYPE_CPU, 2758 .instance_size = sizeof(ARMCPU), 2759 .instance_init = arm_cpu_initfn, 2760 .instance_finalize = arm_cpu_finalizefn, 2761 .abstract = true, 2762 .class_size = sizeof(ARMCPUClass), 2763 .class_init = arm_cpu_class_init, 2764 }; 2765 2766 static const TypeInfo idau_interface_type_info = { 2767 .name = TYPE_IDAU_INTERFACE, 2768 .parent = TYPE_INTERFACE, 2769 .class_size = sizeof(IDAUInterfaceClass), 2770 }; 2771 2772 static void arm_cpu_register_types(void) 2773 { 2774 const ARMCPUInfo *info = arm_cpus; 2775 2776 type_register_static(&arm_cpu_type_info); 2777 type_register_static(&idau_interface_type_info); 2778 2779 while (info->name) { 2780 cpu_register(info); 2781 info++; 2782 } 2783 2784 #ifdef CONFIG_KVM 2785 type_register_static(&host_arm_cpu_type_info); 2786 #endif 2787 } 2788 2789 type_init(arm_cpu_register_types) 2790