1 /* 2 * QEMU ARM CPU 3 * 4 * Copyright (c) 2012 SUSE LINUX Products GmbH 5 * 6 * This program is free software; you can redistribute it and/or 7 * modify it under the terms of the GNU General Public License 8 * as published by the Free Software Foundation; either version 2 9 * of the License, or (at your option) any later version. 10 * 11 * This program is distributed in the hope that it will be useful, 12 * but WITHOUT ANY WARRANTY; without even the implied warranty of 13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 14 * GNU General Public License for more details. 15 * 16 * You should have received a copy of the GNU General Public License 17 * along with this program; if not, see 18 * <http://www.gnu.org/licenses/gpl-2.0.html> 19 */ 20 21 #include "qemu/osdep.h" 22 #include "qemu/qemu-print.h" 23 #include "qemu/timer.h" 24 #include "qemu/log.h" 25 #include "exec/page-vary.h" 26 #include "target/arm/idau.h" 27 #include "qemu/module.h" 28 #include "qapi/error.h" 29 #include "qapi/visitor.h" 30 #include "cpu.h" 31 #ifdef CONFIG_TCG 32 #include "hw/core/tcg-cpu-ops.h" 33 #endif /* CONFIG_TCG */ 34 #include "internals.h" 35 #include "exec/exec-all.h" 36 #include "hw/qdev-properties.h" 37 #if !defined(CONFIG_USER_ONLY) 38 #include "hw/loader.h" 39 #include "hw/boards.h" 40 #endif 41 #include "sysemu/tcg.h" 42 #include "sysemu/hw_accel.h" 43 #include "kvm_arm.h" 44 #include "disas/capstone.h" 45 #include "fpu/softfloat.h" 46 #include "cpregs.h" 47 48 static void arm_cpu_set_pc(CPUState *cs, vaddr value) 49 { 50 ARMCPU *cpu = ARM_CPU(cs); 51 CPUARMState *env = &cpu->env; 52 53 if (is_a64(env)) { 54 env->pc = value; 55 env->thumb = false; 56 } else { 57 env->regs[15] = value & ~1; 58 env->thumb = value & 1; 59 } 60 } 61 62 #ifdef CONFIG_TCG 63 void arm_cpu_synchronize_from_tb(CPUState *cs, 64 const TranslationBlock *tb) 65 { 66 ARMCPU *cpu = ARM_CPU(cs); 67 CPUARMState *env = &cpu->env; 68 69 /* 70 * It's OK to look at env for the current mode here, because it's 71 * never possible for an AArch64 TB to chain to an AArch32 TB. 72 */ 73 if (is_a64(env)) { 74 env->pc = tb->pc; 75 } else { 76 env->regs[15] = tb->pc; 77 } 78 } 79 #endif /* CONFIG_TCG */ 80 81 static bool arm_cpu_has_work(CPUState *cs) 82 { 83 ARMCPU *cpu = ARM_CPU(cs); 84 85 return (cpu->power_state != PSCI_OFF) 86 && cs->interrupt_request & 87 (CPU_INTERRUPT_FIQ | CPU_INTERRUPT_HARD 88 | CPU_INTERRUPT_VFIQ | CPU_INTERRUPT_VIRQ 89 | CPU_INTERRUPT_EXITTB); 90 } 91 92 void arm_register_pre_el_change_hook(ARMCPU *cpu, ARMELChangeHookFn *hook, 93 void *opaque) 94 { 95 ARMELChangeHook *entry = g_new0(ARMELChangeHook, 1); 96 97 entry->hook = hook; 98 entry->opaque = opaque; 99 100 QLIST_INSERT_HEAD(&cpu->pre_el_change_hooks, entry, node); 101 } 102 103 void arm_register_el_change_hook(ARMCPU *cpu, ARMELChangeHookFn *hook, 104 void *opaque) 105 { 106 ARMELChangeHook *entry = g_new0(ARMELChangeHook, 1); 107 108 entry->hook = hook; 109 entry->opaque = opaque; 110 111 QLIST_INSERT_HEAD(&cpu->el_change_hooks, entry, node); 112 } 113 114 static void cp_reg_reset(gpointer key, gpointer value, gpointer opaque) 115 { 116 /* Reset a single ARMCPRegInfo register */ 117 ARMCPRegInfo *ri = value; 118 ARMCPU *cpu = opaque; 119 120 if (ri->type & (ARM_CP_SPECIAL_MASK | ARM_CP_ALIAS)) { 121 return; 122 } 123 124 if (ri->resetfn) { 125 ri->resetfn(&cpu->env, ri); 126 return; 127 } 128 129 /* A zero offset is never possible as it would be regs[0] 130 * so we use it to indicate that reset is being handled elsewhere. 131 * This is basically only used for fields in non-core coprocessors 132 * (like the pxa2xx ones). 133 */ 134 if (!ri->fieldoffset) { 135 return; 136 } 137 138 if (cpreg_field_is_64bit(ri)) { 139 CPREG_FIELD64(&cpu->env, ri) = ri->resetvalue; 140 } else { 141 CPREG_FIELD32(&cpu->env, ri) = ri->resetvalue; 142 } 143 } 144 145 static void cp_reg_check_reset(gpointer key, gpointer value, gpointer opaque) 146 { 147 /* Purely an assertion check: we've already done reset once, 148 * so now check that running the reset for the cpreg doesn't 149 * change its value. This traps bugs where two different cpregs 150 * both try to reset the same state field but to different values. 151 */ 152 ARMCPRegInfo *ri = value; 153 ARMCPU *cpu = opaque; 154 uint64_t oldvalue, newvalue; 155 156 if (ri->type & (ARM_CP_SPECIAL_MASK | ARM_CP_ALIAS | ARM_CP_NO_RAW)) { 157 return; 158 } 159 160 oldvalue = read_raw_cp_reg(&cpu->env, ri); 161 cp_reg_reset(key, value, opaque); 162 newvalue = read_raw_cp_reg(&cpu->env, ri); 163 assert(oldvalue == newvalue); 164 } 165 166 static void arm_cpu_reset(DeviceState *dev) 167 { 168 CPUState *s = CPU(dev); 169 ARMCPU *cpu = ARM_CPU(s); 170 ARMCPUClass *acc = ARM_CPU_GET_CLASS(cpu); 171 CPUARMState *env = &cpu->env; 172 173 acc->parent_reset(dev); 174 175 memset(env, 0, offsetof(CPUARMState, end_reset_fields)); 176 177 g_hash_table_foreach(cpu->cp_regs, cp_reg_reset, cpu); 178 g_hash_table_foreach(cpu->cp_regs, cp_reg_check_reset, cpu); 179 180 env->vfp.xregs[ARM_VFP_FPSID] = cpu->reset_fpsid; 181 env->vfp.xregs[ARM_VFP_MVFR0] = cpu->isar.mvfr0; 182 env->vfp.xregs[ARM_VFP_MVFR1] = cpu->isar.mvfr1; 183 env->vfp.xregs[ARM_VFP_MVFR2] = cpu->isar.mvfr2; 184 185 cpu->power_state = s->start_powered_off ? PSCI_OFF : PSCI_ON; 186 187 if (arm_feature(env, ARM_FEATURE_IWMMXT)) { 188 env->iwmmxt.cregs[ARM_IWMMXT_wCID] = 0x69051000 | 'Q'; 189 } 190 191 if (arm_feature(env, ARM_FEATURE_AARCH64)) { 192 /* 64 bit CPUs always start in 64 bit mode */ 193 env->aarch64 = true; 194 #if defined(CONFIG_USER_ONLY) 195 env->pstate = PSTATE_MODE_EL0t; 196 /* Userspace expects access to DC ZVA, CTL_EL0 and the cache ops */ 197 env->cp15.sctlr_el[1] |= SCTLR_UCT | SCTLR_UCI | SCTLR_DZE; 198 /* Enable all PAC keys. */ 199 env->cp15.sctlr_el[1] |= (SCTLR_EnIA | SCTLR_EnIB | 200 SCTLR_EnDA | SCTLR_EnDB); 201 /* Trap on btype=3 for PACIxSP. */ 202 env->cp15.sctlr_el[1] |= SCTLR_BT0; 203 /* and to the FP/Neon instructions */ 204 env->cp15.cpacr_el1 = deposit64(env->cp15.cpacr_el1, 20, 2, 3); 205 /* and to the SVE instructions */ 206 env->cp15.cpacr_el1 = deposit64(env->cp15.cpacr_el1, 16, 2, 3); 207 /* with reasonable vector length */ 208 if (cpu_isar_feature(aa64_sve, cpu)) { 209 env->vfp.zcr_el[1] = 210 aarch64_sve_zcr_get_valid_len(cpu, cpu->sve_default_vq - 1); 211 } 212 /* 213 * Enable 48-bit address space (TODO: take reserved_va into account). 214 * Enable TBI0 but not TBI1. 215 * Note that this must match useronly_clean_ptr. 216 */ 217 env->cp15.tcr_el[1].raw_tcr = 5 | (1ULL << 37); 218 219 /* Enable MTE */ 220 if (cpu_isar_feature(aa64_mte, cpu)) { 221 /* Enable tag access, but leave TCF0 as No Effect (0). */ 222 env->cp15.sctlr_el[1] |= SCTLR_ATA0; 223 /* 224 * Exclude all tags, so that tag 0 is always used. 225 * This corresponds to Linux current->thread.gcr_incl = 0. 226 * 227 * Set RRND, so that helper_irg() will generate a seed later. 228 * Here in cpu_reset(), the crypto subsystem has not yet been 229 * initialized. 230 */ 231 env->cp15.gcr_el1 = 0x1ffff; 232 } 233 #else 234 /* Reset into the highest available EL */ 235 if (arm_feature(env, ARM_FEATURE_EL3)) { 236 env->pstate = PSTATE_MODE_EL3h; 237 } else if (arm_feature(env, ARM_FEATURE_EL2)) { 238 env->pstate = PSTATE_MODE_EL2h; 239 } else { 240 env->pstate = PSTATE_MODE_EL1h; 241 } 242 243 /* Sample rvbar at reset. */ 244 env->cp15.rvbar = cpu->rvbar_prop; 245 env->pc = env->cp15.rvbar; 246 #endif 247 } else { 248 #if defined(CONFIG_USER_ONLY) 249 /* Userspace expects access to cp10 and cp11 for FP/Neon */ 250 env->cp15.cpacr_el1 = deposit64(env->cp15.cpacr_el1, 20, 4, 0xf); 251 #endif 252 } 253 254 #if defined(CONFIG_USER_ONLY) 255 env->uncached_cpsr = ARM_CPU_MODE_USR; 256 /* For user mode we must enable access to coprocessors */ 257 env->vfp.xregs[ARM_VFP_FPEXC] = 1 << 30; 258 if (arm_feature(env, ARM_FEATURE_IWMMXT)) { 259 env->cp15.c15_cpar = 3; 260 } else if (arm_feature(env, ARM_FEATURE_XSCALE)) { 261 env->cp15.c15_cpar = 1; 262 } 263 #else 264 265 /* 266 * If the highest available EL is EL2, AArch32 will start in Hyp 267 * mode; otherwise it starts in SVC. Note that if we start in 268 * AArch64 then these values in the uncached_cpsr will be ignored. 269 */ 270 if (arm_feature(env, ARM_FEATURE_EL2) && 271 !arm_feature(env, ARM_FEATURE_EL3)) { 272 env->uncached_cpsr = ARM_CPU_MODE_HYP; 273 } else { 274 env->uncached_cpsr = ARM_CPU_MODE_SVC; 275 } 276 env->daif = PSTATE_D | PSTATE_A | PSTATE_I | PSTATE_F; 277 278 /* AArch32 has a hard highvec setting of 0xFFFF0000. If we are currently 279 * executing as AArch32 then check if highvecs are enabled and 280 * adjust the PC accordingly. 281 */ 282 if (A32_BANKED_CURRENT_REG_GET(env, sctlr) & SCTLR_V) { 283 env->regs[15] = 0xFFFF0000; 284 } 285 286 env->vfp.xregs[ARM_VFP_FPEXC] = 0; 287 #endif 288 289 if (arm_feature(env, ARM_FEATURE_M)) { 290 #ifndef CONFIG_USER_ONLY 291 uint32_t initial_msp; /* Loaded from 0x0 */ 292 uint32_t initial_pc; /* Loaded from 0x4 */ 293 uint8_t *rom; 294 uint32_t vecbase; 295 #endif 296 297 if (cpu_isar_feature(aa32_lob, cpu)) { 298 /* 299 * LTPSIZE is constant 4 if MVE not implemented, and resets 300 * to an UNKNOWN value if MVE is implemented. We choose to 301 * always reset to 4. 302 */ 303 env->v7m.ltpsize = 4; 304 /* The LTPSIZE field in FPDSCR is constant and reads as 4. */ 305 env->v7m.fpdscr[M_REG_NS] = 4 << FPCR_LTPSIZE_SHIFT; 306 env->v7m.fpdscr[M_REG_S] = 4 << FPCR_LTPSIZE_SHIFT; 307 } 308 309 if (arm_feature(env, ARM_FEATURE_M_SECURITY)) { 310 env->v7m.secure = true; 311 } else { 312 /* This bit resets to 0 if security is supported, but 1 if 313 * it is not. The bit is not present in v7M, but we set it 314 * here so we can avoid having to make checks on it conditional 315 * on ARM_FEATURE_V8 (we don't let the guest see the bit). 316 */ 317 env->v7m.aircr = R_V7M_AIRCR_BFHFNMINS_MASK; 318 /* 319 * Set NSACR to indicate "NS access permitted to everything"; 320 * this avoids having to have all the tests of it being 321 * conditional on ARM_FEATURE_M_SECURITY. Note also that from 322 * v8.1M the guest-visible value of NSACR in a CPU without the 323 * Security Extension is 0xcff. 324 */ 325 env->v7m.nsacr = 0xcff; 326 } 327 328 /* In v7M the reset value of this bit is IMPDEF, but ARM recommends 329 * that it resets to 1, so QEMU always does that rather than making 330 * it dependent on CPU model. In v8M it is RES1. 331 */ 332 env->v7m.ccr[M_REG_NS] = R_V7M_CCR_STKALIGN_MASK; 333 env->v7m.ccr[M_REG_S] = R_V7M_CCR_STKALIGN_MASK; 334 if (arm_feature(env, ARM_FEATURE_V8)) { 335 /* in v8M the NONBASETHRDENA bit [0] is RES1 */ 336 env->v7m.ccr[M_REG_NS] |= R_V7M_CCR_NONBASETHRDENA_MASK; 337 env->v7m.ccr[M_REG_S] |= R_V7M_CCR_NONBASETHRDENA_MASK; 338 } 339 if (!arm_feature(env, ARM_FEATURE_M_MAIN)) { 340 env->v7m.ccr[M_REG_NS] |= R_V7M_CCR_UNALIGN_TRP_MASK; 341 env->v7m.ccr[M_REG_S] |= R_V7M_CCR_UNALIGN_TRP_MASK; 342 } 343 344 if (cpu_isar_feature(aa32_vfp_simd, cpu)) { 345 env->v7m.fpccr[M_REG_NS] = R_V7M_FPCCR_ASPEN_MASK; 346 env->v7m.fpccr[M_REG_S] = R_V7M_FPCCR_ASPEN_MASK | 347 R_V7M_FPCCR_LSPEN_MASK | R_V7M_FPCCR_S_MASK; 348 } 349 350 #ifndef CONFIG_USER_ONLY 351 /* Unlike A/R profile, M profile defines the reset LR value */ 352 env->regs[14] = 0xffffffff; 353 354 env->v7m.vecbase[M_REG_S] = cpu->init_svtor & 0xffffff80; 355 env->v7m.vecbase[M_REG_NS] = cpu->init_nsvtor & 0xffffff80; 356 357 /* Load the initial SP and PC from offset 0 and 4 in the vector table */ 358 vecbase = env->v7m.vecbase[env->v7m.secure]; 359 rom = rom_ptr_for_as(s->as, vecbase, 8); 360 if (rom) { 361 /* Address zero is covered by ROM which hasn't yet been 362 * copied into physical memory. 363 */ 364 initial_msp = ldl_p(rom); 365 initial_pc = ldl_p(rom + 4); 366 } else { 367 /* Address zero not covered by a ROM blob, or the ROM blob 368 * is in non-modifiable memory and this is a second reset after 369 * it got copied into memory. In the latter case, rom_ptr 370 * will return a NULL pointer and we should use ldl_phys instead. 371 */ 372 initial_msp = ldl_phys(s->as, vecbase); 373 initial_pc = ldl_phys(s->as, vecbase + 4); 374 } 375 376 qemu_log_mask(CPU_LOG_INT, 377 "Loaded reset SP 0x%x PC 0x%x from vector table\n", 378 initial_msp, initial_pc); 379 380 env->regs[13] = initial_msp & 0xFFFFFFFC; 381 env->regs[15] = initial_pc & ~1; 382 env->thumb = initial_pc & 1; 383 #else 384 /* 385 * For user mode we run non-secure and with access to the FPU. 386 * The FPU context is active (ie does not need further setup) 387 * and is owned by non-secure. 388 */ 389 env->v7m.secure = false; 390 env->v7m.nsacr = 0xcff; 391 env->v7m.cpacr[M_REG_NS] = 0xf0ffff; 392 env->v7m.fpccr[M_REG_S] &= 393 ~(R_V7M_FPCCR_LSPEN_MASK | R_V7M_FPCCR_S_MASK); 394 env->v7m.control[M_REG_S] |= R_V7M_CONTROL_FPCA_MASK; 395 #endif 396 } 397 398 /* M profile requires that reset clears the exclusive monitor; 399 * A profile does not, but clearing it makes more sense than having it 400 * set with an exclusive access on address zero. 401 */ 402 arm_clear_exclusive(env); 403 404 if (arm_feature(env, ARM_FEATURE_PMSA)) { 405 if (cpu->pmsav7_dregion > 0) { 406 if (arm_feature(env, ARM_FEATURE_V8)) { 407 memset(env->pmsav8.rbar[M_REG_NS], 0, 408 sizeof(*env->pmsav8.rbar[M_REG_NS]) 409 * cpu->pmsav7_dregion); 410 memset(env->pmsav8.rlar[M_REG_NS], 0, 411 sizeof(*env->pmsav8.rlar[M_REG_NS]) 412 * cpu->pmsav7_dregion); 413 if (arm_feature(env, ARM_FEATURE_M_SECURITY)) { 414 memset(env->pmsav8.rbar[M_REG_S], 0, 415 sizeof(*env->pmsav8.rbar[M_REG_S]) 416 * cpu->pmsav7_dregion); 417 memset(env->pmsav8.rlar[M_REG_S], 0, 418 sizeof(*env->pmsav8.rlar[M_REG_S]) 419 * cpu->pmsav7_dregion); 420 } 421 } else if (arm_feature(env, ARM_FEATURE_V7)) { 422 memset(env->pmsav7.drbar, 0, 423 sizeof(*env->pmsav7.drbar) * cpu->pmsav7_dregion); 424 memset(env->pmsav7.drsr, 0, 425 sizeof(*env->pmsav7.drsr) * cpu->pmsav7_dregion); 426 memset(env->pmsav7.dracr, 0, 427 sizeof(*env->pmsav7.dracr) * cpu->pmsav7_dregion); 428 } 429 } 430 env->pmsav7.rnr[M_REG_NS] = 0; 431 env->pmsav7.rnr[M_REG_S] = 0; 432 env->pmsav8.mair0[M_REG_NS] = 0; 433 env->pmsav8.mair0[M_REG_S] = 0; 434 env->pmsav8.mair1[M_REG_NS] = 0; 435 env->pmsav8.mair1[M_REG_S] = 0; 436 } 437 438 if (arm_feature(env, ARM_FEATURE_M_SECURITY)) { 439 if (cpu->sau_sregion > 0) { 440 memset(env->sau.rbar, 0, sizeof(*env->sau.rbar) * cpu->sau_sregion); 441 memset(env->sau.rlar, 0, sizeof(*env->sau.rlar) * cpu->sau_sregion); 442 } 443 env->sau.rnr = 0; 444 /* SAU_CTRL reset value is IMPDEF; we choose 0, which is what 445 * the Cortex-M33 does. 446 */ 447 env->sau.ctrl = 0; 448 } 449 450 set_flush_to_zero(1, &env->vfp.standard_fp_status); 451 set_flush_inputs_to_zero(1, &env->vfp.standard_fp_status); 452 set_default_nan_mode(1, &env->vfp.standard_fp_status); 453 set_default_nan_mode(1, &env->vfp.standard_fp_status_f16); 454 set_float_detect_tininess(float_tininess_before_rounding, 455 &env->vfp.fp_status); 456 set_float_detect_tininess(float_tininess_before_rounding, 457 &env->vfp.standard_fp_status); 458 set_float_detect_tininess(float_tininess_before_rounding, 459 &env->vfp.fp_status_f16); 460 set_float_detect_tininess(float_tininess_before_rounding, 461 &env->vfp.standard_fp_status_f16); 462 #ifndef CONFIG_USER_ONLY 463 if (kvm_enabled()) { 464 kvm_arm_reset_vcpu(cpu); 465 } 466 #endif 467 468 hw_breakpoint_update_all(cpu); 469 hw_watchpoint_update_all(cpu); 470 arm_rebuild_hflags(env); 471 } 472 473 #ifndef CONFIG_USER_ONLY 474 475 static inline bool arm_excp_unmasked(CPUState *cs, unsigned int excp_idx, 476 unsigned int target_el, 477 unsigned int cur_el, bool secure, 478 uint64_t hcr_el2) 479 { 480 CPUARMState *env = cs->env_ptr; 481 bool pstate_unmasked; 482 bool unmasked = false; 483 484 /* 485 * Don't take exceptions if they target a lower EL. 486 * This check should catch any exceptions that would not be taken 487 * but left pending. 488 */ 489 if (cur_el > target_el) { 490 return false; 491 } 492 493 switch (excp_idx) { 494 case EXCP_FIQ: 495 pstate_unmasked = !(env->daif & PSTATE_F); 496 break; 497 498 case EXCP_IRQ: 499 pstate_unmasked = !(env->daif & PSTATE_I); 500 break; 501 502 case EXCP_VFIQ: 503 if (!(hcr_el2 & HCR_FMO) || (hcr_el2 & HCR_TGE)) { 504 /* VFIQs are only taken when hypervized. */ 505 return false; 506 } 507 return !(env->daif & PSTATE_F); 508 case EXCP_VIRQ: 509 if (!(hcr_el2 & HCR_IMO) || (hcr_el2 & HCR_TGE)) { 510 /* VIRQs are only taken when hypervized. */ 511 return false; 512 } 513 return !(env->daif & PSTATE_I); 514 default: 515 g_assert_not_reached(); 516 } 517 518 /* 519 * Use the target EL, current execution state and SCR/HCR settings to 520 * determine whether the corresponding CPSR bit is used to mask the 521 * interrupt. 522 */ 523 if ((target_el > cur_el) && (target_el != 1)) { 524 /* Exceptions targeting a higher EL may not be maskable */ 525 if (arm_feature(env, ARM_FEATURE_AARCH64)) { 526 /* 527 * 64-bit masking rules are simple: exceptions to EL3 528 * can't be masked, and exceptions to EL2 can only be 529 * masked from Secure state. The HCR and SCR settings 530 * don't affect the masking logic, only the interrupt routing. 531 */ 532 if (target_el == 3 || !secure || (env->cp15.scr_el3 & SCR_EEL2)) { 533 unmasked = true; 534 } 535 } else { 536 /* 537 * The old 32-bit-only environment has a more complicated 538 * masking setup. HCR and SCR bits not only affect interrupt 539 * routing but also change the behaviour of masking. 540 */ 541 bool hcr, scr; 542 543 switch (excp_idx) { 544 case EXCP_FIQ: 545 /* 546 * If FIQs are routed to EL3 or EL2 then there are cases where 547 * we override the CPSR.F in determining if the exception is 548 * masked or not. If neither of these are set then we fall back 549 * to the CPSR.F setting otherwise we further assess the state 550 * below. 551 */ 552 hcr = hcr_el2 & HCR_FMO; 553 scr = (env->cp15.scr_el3 & SCR_FIQ); 554 555 /* 556 * When EL3 is 32-bit, the SCR.FW bit controls whether the 557 * CPSR.F bit masks FIQ interrupts when taken in non-secure 558 * state. If SCR.FW is set then FIQs can be masked by CPSR.F 559 * when non-secure but only when FIQs are only routed to EL3. 560 */ 561 scr = scr && !((env->cp15.scr_el3 & SCR_FW) && !hcr); 562 break; 563 case EXCP_IRQ: 564 /* 565 * When EL3 execution state is 32-bit, if HCR.IMO is set then 566 * we may override the CPSR.I masking when in non-secure state. 567 * The SCR.IRQ setting has already been taken into consideration 568 * when setting the target EL, so it does not have a further 569 * affect here. 570 */ 571 hcr = hcr_el2 & HCR_IMO; 572 scr = false; 573 break; 574 default: 575 g_assert_not_reached(); 576 } 577 578 if ((scr || hcr) && !secure) { 579 unmasked = true; 580 } 581 } 582 } 583 584 /* 585 * The PSTATE bits only mask the interrupt if we have not overriden the 586 * ability above. 587 */ 588 return unmasked || pstate_unmasked; 589 } 590 591 static bool arm_cpu_exec_interrupt(CPUState *cs, int interrupt_request) 592 { 593 CPUClass *cc = CPU_GET_CLASS(cs); 594 CPUARMState *env = cs->env_ptr; 595 uint32_t cur_el = arm_current_el(env); 596 bool secure = arm_is_secure(env); 597 uint64_t hcr_el2 = arm_hcr_el2_eff(env); 598 uint32_t target_el; 599 uint32_t excp_idx; 600 601 /* The prioritization of interrupts is IMPLEMENTATION DEFINED. */ 602 603 if (interrupt_request & CPU_INTERRUPT_FIQ) { 604 excp_idx = EXCP_FIQ; 605 target_el = arm_phys_excp_target_el(cs, excp_idx, cur_el, secure); 606 if (arm_excp_unmasked(cs, excp_idx, target_el, 607 cur_el, secure, hcr_el2)) { 608 goto found; 609 } 610 } 611 if (interrupt_request & CPU_INTERRUPT_HARD) { 612 excp_idx = EXCP_IRQ; 613 target_el = arm_phys_excp_target_el(cs, excp_idx, cur_el, secure); 614 if (arm_excp_unmasked(cs, excp_idx, target_el, 615 cur_el, secure, hcr_el2)) { 616 goto found; 617 } 618 } 619 if (interrupt_request & CPU_INTERRUPT_VIRQ) { 620 excp_idx = EXCP_VIRQ; 621 target_el = 1; 622 if (arm_excp_unmasked(cs, excp_idx, target_el, 623 cur_el, secure, hcr_el2)) { 624 goto found; 625 } 626 } 627 if (interrupt_request & CPU_INTERRUPT_VFIQ) { 628 excp_idx = EXCP_VFIQ; 629 target_el = 1; 630 if (arm_excp_unmasked(cs, excp_idx, target_el, 631 cur_el, secure, hcr_el2)) { 632 goto found; 633 } 634 } 635 return false; 636 637 found: 638 cs->exception_index = excp_idx; 639 env->exception.target_el = target_el; 640 cc->tcg_ops->do_interrupt(cs); 641 return true; 642 } 643 #endif /* !CONFIG_USER_ONLY */ 644 645 void arm_cpu_update_virq(ARMCPU *cpu) 646 { 647 /* 648 * Update the interrupt level for VIRQ, which is the logical OR of 649 * the HCR_EL2.VI bit and the input line level from the GIC. 650 */ 651 CPUARMState *env = &cpu->env; 652 CPUState *cs = CPU(cpu); 653 654 bool new_state = (env->cp15.hcr_el2 & HCR_VI) || 655 (env->irq_line_state & CPU_INTERRUPT_VIRQ); 656 657 if (new_state != ((cs->interrupt_request & CPU_INTERRUPT_VIRQ) != 0)) { 658 if (new_state) { 659 cpu_interrupt(cs, CPU_INTERRUPT_VIRQ); 660 } else { 661 cpu_reset_interrupt(cs, CPU_INTERRUPT_VIRQ); 662 } 663 } 664 } 665 666 void arm_cpu_update_vfiq(ARMCPU *cpu) 667 { 668 /* 669 * Update the interrupt level for VFIQ, which is the logical OR of 670 * the HCR_EL2.VF bit and the input line level from the GIC. 671 */ 672 CPUARMState *env = &cpu->env; 673 CPUState *cs = CPU(cpu); 674 675 bool new_state = (env->cp15.hcr_el2 & HCR_VF) || 676 (env->irq_line_state & CPU_INTERRUPT_VFIQ); 677 678 if (new_state != ((cs->interrupt_request & CPU_INTERRUPT_VFIQ) != 0)) { 679 if (new_state) { 680 cpu_interrupt(cs, CPU_INTERRUPT_VFIQ); 681 } else { 682 cpu_reset_interrupt(cs, CPU_INTERRUPT_VFIQ); 683 } 684 } 685 } 686 687 #ifndef CONFIG_USER_ONLY 688 static void arm_cpu_set_irq(void *opaque, int irq, int level) 689 { 690 ARMCPU *cpu = opaque; 691 CPUARMState *env = &cpu->env; 692 CPUState *cs = CPU(cpu); 693 static const int mask[] = { 694 [ARM_CPU_IRQ] = CPU_INTERRUPT_HARD, 695 [ARM_CPU_FIQ] = CPU_INTERRUPT_FIQ, 696 [ARM_CPU_VIRQ] = CPU_INTERRUPT_VIRQ, 697 [ARM_CPU_VFIQ] = CPU_INTERRUPT_VFIQ 698 }; 699 700 if (!arm_feature(env, ARM_FEATURE_EL2) && 701 (irq == ARM_CPU_VIRQ || irq == ARM_CPU_VFIQ)) { 702 /* 703 * The GIC might tell us about VIRQ and VFIQ state, but if we don't 704 * have EL2 support we don't care. (Unless the guest is doing something 705 * silly this will only be calls saying "level is still 0".) 706 */ 707 return; 708 } 709 710 if (level) { 711 env->irq_line_state |= mask[irq]; 712 } else { 713 env->irq_line_state &= ~mask[irq]; 714 } 715 716 switch (irq) { 717 case ARM_CPU_VIRQ: 718 arm_cpu_update_virq(cpu); 719 break; 720 case ARM_CPU_VFIQ: 721 arm_cpu_update_vfiq(cpu); 722 break; 723 case ARM_CPU_IRQ: 724 case ARM_CPU_FIQ: 725 if (level) { 726 cpu_interrupt(cs, mask[irq]); 727 } else { 728 cpu_reset_interrupt(cs, mask[irq]); 729 } 730 break; 731 default: 732 g_assert_not_reached(); 733 } 734 } 735 736 static void arm_cpu_kvm_set_irq(void *opaque, int irq, int level) 737 { 738 #ifdef CONFIG_KVM 739 ARMCPU *cpu = opaque; 740 CPUARMState *env = &cpu->env; 741 CPUState *cs = CPU(cpu); 742 uint32_t linestate_bit; 743 int irq_id; 744 745 switch (irq) { 746 case ARM_CPU_IRQ: 747 irq_id = KVM_ARM_IRQ_CPU_IRQ; 748 linestate_bit = CPU_INTERRUPT_HARD; 749 break; 750 case ARM_CPU_FIQ: 751 irq_id = KVM_ARM_IRQ_CPU_FIQ; 752 linestate_bit = CPU_INTERRUPT_FIQ; 753 break; 754 default: 755 g_assert_not_reached(); 756 } 757 758 if (level) { 759 env->irq_line_state |= linestate_bit; 760 } else { 761 env->irq_line_state &= ~linestate_bit; 762 } 763 kvm_arm_set_irq(cs->cpu_index, KVM_ARM_IRQ_TYPE_CPU, irq_id, !!level); 764 #endif 765 } 766 767 static bool arm_cpu_virtio_is_big_endian(CPUState *cs) 768 { 769 ARMCPU *cpu = ARM_CPU(cs); 770 CPUARMState *env = &cpu->env; 771 772 cpu_synchronize_state(cs); 773 return arm_cpu_data_is_big_endian(env); 774 } 775 776 #endif 777 778 static void arm_disas_set_info(CPUState *cpu, disassemble_info *info) 779 { 780 ARMCPU *ac = ARM_CPU(cpu); 781 CPUARMState *env = &ac->env; 782 bool sctlr_b; 783 784 if (is_a64(env)) { 785 /* We might not be compiled with the A64 disassembler 786 * because it needs a C++ compiler. Leave print_insn 787 * unset in this case to use the caller default behaviour. 788 */ 789 #if defined(CONFIG_ARM_A64_DIS) 790 info->print_insn = print_insn_arm_a64; 791 #endif 792 info->cap_arch = CS_ARCH_ARM64; 793 info->cap_insn_unit = 4; 794 info->cap_insn_split = 4; 795 } else { 796 int cap_mode; 797 if (env->thumb) { 798 info->cap_insn_unit = 2; 799 info->cap_insn_split = 4; 800 cap_mode = CS_MODE_THUMB; 801 } else { 802 info->cap_insn_unit = 4; 803 info->cap_insn_split = 4; 804 cap_mode = CS_MODE_ARM; 805 } 806 if (arm_feature(env, ARM_FEATURE_V8)) { 807 cap_mode |= CS_MODE_V8; 808 } 809 if (arm_feature(env, ARM_FEATURE_M)) { 810 cap_mode |= CS_MODE_MCLASS; 811 } 812 info->cap_arch = CS_ARCH_ARM; 813 info->cap_mode = cap_mode; 814 } 815 816 sctlr_b = arm_sctlr_b(env); 817 if (bswap_code(sctlr_b)) { 818 #if TARGET_BIG_ENDIAN 819 info->endian = BFD_ENDIAN_LITTLE; 820 #else 821 info->endian = BFD_ENDIAN_BIG; 822 #endif 823 } 824 info->flags &= ~INSN_ARM_BE32; 825 #ifndef CONFIG_USER_ONLY 826 if (sctlr_b) { 827 info->flags |= INSN_ARM_BE32; 828 } 829 #endif 830 } 831 832 #ifdef TARGET_AARCH64 833 834 static void aarch64_cpu_dump_state(CPUState *cs, FILE *f, int flags) 835 { 836 ARMCPU *cpu = ARM_CPU(cs); 837 CPUARMState *env = &cpu->env; 838 uint32_t psr = pstate_read(env); 839 int i; 840 int el = arm_current_el(env); 841 const char *ns_status; 842 843 qemu_fprintf(f, " PC=%016" PRIx64 " ", env->pc); 844 for (i = 0; i < 32; i++) { 845 if (i == 31) { 846 qemu_fprintf(f, " SP=%016" PRIx64 "\n", env->xregs[i]); 847 } else { 848 qemu_fprintf(f, "X%02d=%016" PRIx64 "%s", i, env->xregs[i], 849 (i + 2) % 3 ? " " : "\n"); 850 } 851 } 852 853 if (arm_feature(env, ARM_FEATURE_EL3) && el != 3) { 854 ns_status = env->cp15.scr_el3 & SCR_NS ? "NS " : "S "; 855 } else { 856 ns_status = ""; 857 } 858 qemu_fprintf(f, "PSTATE=%08x %c%c%c%c %sEL%d%c", 859 psr, 860 psr & PSTATE_N ? 'N' : '-', 861 psr & PSTATE_Z ? 'Z' : '-', 862 psr & PSTATE_C ? 'C' : '-', 863 psr & PSTATE_V ? 'V' : '-', 864 ns_status, 865 el, 866 psr & PSTATE_SP ? 'h' : 't'); 867 868 if (cpu_isar_feature(aa64_bti, cpu)) { 869 qemu_fprintf(f, " BTYPE=%d", (psr & PSTATE_BTYPE) >> 10); 870 } 871 if (!(flags & CPU_DUMP_FPU)) { 872 qemu_fprintf(f, "\n"); 873 return; 874 } 875 if (fp_exception_el(env, el) != 0) { 876 qemu_fprintf(f, " FPU disabled\n"); 877 return; 878 } 879 qemu_fprintf(f, " FPCR=%08x FPSR=%08x\n", 880 vfp_get_fpcr(env), vfp_get_fpsr(env)); 881 882 if (cpu_isar_feature(aa64_sve, cpu) && sve_exception_el(env, el) == 0) { 883 int j, zcr_len = sve_zcr_len_for_el(env, el); 884 885 for (i = 0; i <= FFR_PRED_NUM; i++) { 886 bool eol; 887 if (i == FFR_PRED_NUM) { 888 qemu_fprintf(f, "FFR="); 889 /* It's last, so end the line. */ 890 eol = true; 891 } else { 892 qemu_fprintf(f, "P%02d=", i); 893 switch (zcr_len) { 894 case 0: 895 eol = i % 8 == 7; 896 break; 897 case 1: 898 eol = i % 6 == 5; 899 break; 900 case 2: 901 case 3: 902 eol = i % 3 == 2; 903 break; 904 default: 905 /* More than one quadword per predicate. */ 906 eol = true; 907 break; 908 } 909 } 910 for (j = zcr_len / 4; j >= 0; j--) { 911 int digits; 912 if (j * 4 + 4 <= zcr_len + 1) { 913 digits = 16; 914 } else { 915 digits = (zcr_len % 4 + 1) * 4; 916 } 917 qemu_fprintf(f, "%0*" PRIx64 "%s", digits, 918 env->vfp.pregs[i].p[j], 919 j ? ":" : eol ? "\n" : " "); 920 } 921 } 922 923 for (i = 0; i < 32; i++) { 924 if (zcr_len == 0) { 925 qemu_fprintf(f, "Z%02d=%016" PRIx64 ":%016" PRIx64 "%s", 926 i, env->vfp.zregs[i].d[1], 927 env->vfp.zregs[i].d[0], i & 1 ? "\n" : " "); 928 } else if (zcr_len == 1) { 929 qemu_fprintf(f, "Z%02d=%016" PRIx64 ":%016" PRIx64 930 ":%016" PRIx64 ":%016" PRIx64 "\n", 931 i, env->vfp.zregs[i].d[3], env->vfp.zregs[i].d[2], 932 env->vfp.zregs[i].d[1], env->vfp.zregs[i].d[0]); 933 } else { 934 for (j = zcr_len; j >= 0; j--) { 935 bool odd = (zcr_len - j) % 2 != 0; 936 if (j == zcr_len) { 937 qemu_fprintf(f, "Z%02d[%x-%x]=", i, j, j - 1); 938 } else if (!odd) { 939 if (j > 0) { 940 qemu_fprintf(f, " [%x-%x]=", j, j - 1); 941 } else { 942 qemu_fprintf(f, " [%x]=", j); 943 } 944 } 945 qemu_fprintf(f, "%016" PRIx64 ":%016" PRIx64 "%s", 946 env->vfp.zregs[i].d[j * 2 + 1], 947 env->vfp.zregs[i].d[j * 2], 948 odd || j == 0 ? "\n" : ":"); 949 } 950 } 951 } 952 } else { 953 for (i = 0; i < 32; i++) { 954 uint64_t *q = aa64_vfp_qreg(env, i); 955 qemu_fprintf(f, "Q%02d=%016" PRIx64 ":%016" PRIx64 "%s", 956 i, q[1], q[0], (i & 1 ? "\n" : " ")); 957 } 958 } 959 } 960 961 #else 962 963 static inline void aarch64_cpu_dump_state(CPUState *cs, FILE *f, int flags) 964 { 965 g_assert_not_reached(); 966 } 967 968 #endif 969 970 static void arm_cpu_dump_state(CPUState *cs, FILE *f, int flags) 971 { 972 ARMCPU *cpu = ARM_CPU(cs); 973 CPUARMState *env = &cpu->env; 974 int i; 975 976 if (is_a64(env)) { 977 aarch64_cpu_dump_state(cs, f, flags); 978 return; 979 } 980 981 for (i = 0; i < 16; i++) { 982 qemu_fprintf(f, "R%02d=%08x", i, env->regs[i]); 983 if ((i % 4) == 3) { 984 qemu_fprintf(f, "\n"); 985 } else { 986 qemu_fprintf(f, " "); 987 } 988 } 989 990 if (arm_feature(env, ARM_FEATURE_M)) { 991 uint32_t xpsr = xpsr_read(env); 992 const char *mode; 993 const char *ns_status = ""; 994 995 if (arm_feature(env, ARM_FEATURE_M_SECURITY)) { 996 ns_status = env->v7m.secure ? "S " : "NS "; 997 } 998 999 if (xpsr & XPSR_EXCP) { 1000 mode = "handler"; 1001 } else { 1002 if (env->v7m.control[env->v7m.secure] & R_V7M_CONTROL_NPRIV_MASK) { 1003 mode = "unpriv-thread"; 1004 } else { 1005 mode = "priv-thread"; 1006 } 1007 } 1008 1009 qemu_fprintf(f, "XPSR=%08x %c%c%c%c %c %s%s\n", 1010 xpsr, 1011 xpsr & XPSR_N ? 'N' : '-', 1012 xpsr & XPSR_Z ? 'Z' : '-', 1013 xpsr & XPSR_C ? 'C' : '-', 1014 xpsr & XPSR_V ? 'V' : '-', 1015 xpsr & XPSR_T ? 'T' : 'A', 1016 ns_status, 1017 mode); 1018 } else { 1019 uint32_t psr = cpsr_read(env); 1020 const char *ns_status = ""; 1021 1022 if (arm_feature(env, ARM_FEATURE_EL3) && 1023 (psr & CPSR_M) != ARM_CPU_MODE_MON) { 1024 ns_status = env->cp15.scr_el3 & SCR_NS ? "NS " : "S "; 1025 } 1026 1027 qemu_fprintf(f, "PSR=%08x %c%c%c%c %c %s%s%d\n", 1028 psr, 1029 psr & CPSR_N ? 'N' : '-', 1030 psr & CPSR_Z ? 'Z' : '-', 1031 psr & CPSR_C ? 'C' : '-', 1032 psr & CPSR_V ? 'V' : '-', 1033 psr & CPSR_T ? 'T' : 'A', 1034 ns_status, 1035 aarch32_mode_name(psr), (psr & 0x10) ? 32 : 26); 1036 } 1037 1038 if (flags & CPU_DUMP_FPU) { 1039 int numvfpregs = 0; 1040 if (cpu_isar_feature(aa32_simd_r32, cpu)) { 1041 numvfpregs = 32; 1042 } else if (cpu_isar_feature(aa32_vfp_simd, cpu)) { 1043 numvfpregs = 16; 1044 } 1045 for (i = 0; i < numvfpregs; i++) { 1046 uint64_t v = *aa32_vfp_dreg(env, i); 1047 qemu_fprintf(f, "s%02d=%08x s%02d=%08x d%02d=%016" PRIx64 "\n", 1048 i * 2, (uint32_t)v, 1049 i * 2 + 1, (uint32_t)(v >> 32), 1050 i, v); 1051 } 1052 qemu_fprintf(f, "FPSCR: %08x\n", vfp_get_fpscr(env)); 1053 if (cpu_isar_feature(aa32_mve, cpu)) { 1054 qemu_fprintf(f, "VPR: %08x\n", env->v7m.vpr); 1055 } 1056 } 1057 } 1058 1059 uint64_t arm_cpu_mp_affinity(int idx, uint8_t clustersz) 1060 { 1061 uint32_t Aff1 = idx / clustersz; 1062 uint32_t Aff0 = idx % clustersz; 1063 return (Aff1 << ARM_AFF1_SHIFT) | Aff0; 1064 } 1065 1066 static void arm_cpu_initfn(Object *obj) 1067 { 1068 ARMCPU *cpu = ARM_CPU(obj); 1069 1070 cpu_set_cpustate_pointers(cpu); 1071 cpu->cp_regs = g_hash_table_new_full(g_direct_hash, g_direct_equal, 1072 NULL, g_free); 1073 1074 QLIST_INIT(&cpu->pre_el_change_hooks); 1075 QLIST_INIT(&cpu->el_change_hooks); 1076 1077 #ifdef CONFIG_USER_ONLY 1078 # ifdef TARGET_AARCH64 1079 /* 1080 * The linux kernel defaults to 512-bit vectors, when sve is supported. 1081 * See documentation for /proc/sys/abi/sve_default_vector_length, and 1082 * our corresponding sve-default-vector-length cpu property. 1083 */ 1084 cpu->sve_default_vq = 4; 1085 # endif 1086 #else 1087 /* Our inbound IRQ and FIQ lines */ 1088 if (kvm_enabled()) { 1089 /* VIRQ and VFIQ are unused with KVM but we add them to maintain 1090 * the same interface as non-KVM CPUs. 1091 */ 1092 qdev_init_gpio_in(DEVICE(cpu), arm_cpu_kvm_set_irq, 4); 1093 } else { 1094 qdev_init_gpio_in(DEVICE(cpu), arm_cpu_set_irq, 4); 1095 } 1096 1097 qdev_init_gpio_out(DEVICE(cpu), cpu->gt_timer_outputs, 1098 ARRAY_SIZE(cpu->gt_timer_outputs)); 1099 1100 qdev_init_gpio_out_named(DEVICE(cpu), &cpu->gicv3_maintenance_interrupt, 1101 "gicv3-maintenance-interrupt", 1); 1102 qdev_init_gpio_out_named(DEVICE(cpu), &cpu->pmu_interrupt, 1103 "pmu-interrupt", 1); 1104 #endif 1105 1106 /* DTB consumers generally don't in fact care what the 'compatible' 1107 * string is, so always provide some string and trust that a hypothetical 1108 * picky DTB consumer will also provide a helpful error message. 1109 */ 1110 cpu->dtb_compatible = "qemu,unknown"; 1111 cpu->psci_version = QEMU_PSCI_VERSION_0_1; /* By default assume PSCI v0.1 */ 1112 cpu->kvm_target = QEMU_KVM_ARM_TARGET_NONE; 1113 1114 if (tcg_enabled() || hvf_enabled()) { 1115 /* TCG and HVF implement PSCI 1.1 */ 1116 cpu->psci_version = QEMU_PSCI_VERSION_1_1; 1117 } 1118 } 1119 1120 static Property arm_cpu_gt_cntfrq_property = 1121 DEFINE_PROP_UINT64("cntfrq", ARMCPU, gt_cntfrq_hz, 1122 NANOSECONDS_PER_SECOND / GTIMER_SCALE); 1123 1124 static Property arm_cpu_reset_cbar_property = 1125 DEFINE_PROP_UINT64("reset-cbar", ARMCPU, reset_cbar, 0); 1126 1127 static Property arm_cpu_reset_hivecs_property = 1128 DEFINE_PROP_BOOL("reset-hivecs", ARMCPU, reset_hivecs, false); 1129 1130 #ifndef CONFIG_USER_ONLY 1131 static Property arm_cpu_has_el2_property = 1132 DEFINE_PROP_BOOL("has_el2", ARMCPU, has_el2, true); 1133 1134 static Property arm_cpu_has_el3_property = 1135 DEFINE_PROP_BOOL("has_el3", ARMCPU, has_el3, true); 1136 #endif 1137 1138 static Property arm_cpu_cfgend_property = 1139 DEFINE_PROP_BOOL("cfgend", ARMCPU, cfgend, false); 1140 1141 static Property arm_cpu_has_vfp_property = 1142 DEFINE_PROP_BOOL("vfp", ARMCPU, has_vfp, true); 1143 1144 static Property arm_cpu_has_neon_property = 1145 DEFINE_PROP_BOOL("neon", ARMCPU, has_neon, true); 1146 1147 static Property arm_cpu_has_dsp_property = 1148 DEFINE_PROP_BOOL("dsp", ARMCPU, has_dsp, true); 1149 1150 static Property arm_cpu_has_mpu_property = 1151 DEFINE_PROP_BOOL("has-mpu", ARMCPU, has_mpu, true); 1152 1153 /* This is like DEFINE_PROP_UINT32 but it doesn't set the default value, 1154 * because the CPU initfn will have already set cpu->pmsav7_dregion to 1155 * the right value for that particular CPU type, and we don't want 1156 * to override that with an incorrect constant value. 1157 */ 1158 static Property arm_cpu_pmsav7_dregion_property = 1159 DEFINE_PROP_UNSIGNED_NODEFAULT("pmsav7-dregion", ARMCPU, 1160 pmsav7_dregion, 1161 qdev_prop_uint32, uint32_t); 1162 1163 static bool arm_get_pmu(Object *obj, Error **errp) 1164 { 1165 ARMCPU *cpu = ARM_CPU(obj); 1166 1167 return cpu->has_pmu; 1168 } 1169 1170 static void arm_set_pmu(Object *obj, bool value, Error **errp) 1171 { 1172 ARMCPU *cpu = ARM_CPU(obj); 1173 1174 if (value) { 1175 if (kvm_enabled() && !kvm_arm_pmu_supported()) { 1176 error_setg(errp, "'pmu' feature not supported by KVM on this host"); 1177 return; 1178 } 1179 set_feature(&cpu->env, ARM_FEATURE_PMU); 1180 } else { 1181 unset_feature(&cpu->env, ARM_FEATURE_PMU); 1182 } 1183 cpu->has_pmu = value; 1184 } 1185 1186 unsigned int gt_cntfrq_period_ns(ARMCPU *cpu) 1187 { 1188 /* 1189 * The exact approach to calculating guest ticks is: 1190 * 1191 * muldiv64(qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL), cpu->gt_cntfrq_hz, 1192 * NANOSECONDS_PER_SECOND); 1193 * 1194 * We don't do that. Rather we intentionally use integer division 1195 * truncation below and in the caller for the conversion of host monotonic 1196 * time to guest ticks to provide the exact inverse for the semantics of 1197 * the QEMUTimer scale factor. QEMUTimer's scale facter is an integer, so 1198 * it loses precision when representing frequencies where 1199 * `(NANOSECONDS_PER_SECOND % cpu->gt_cntfrq) > 0` holds. Failing to 1200 * provide an exact inverse leads to scheduling timers with negative 1201 * periods, which in turn leads to sticky behaviour in the guest. 1202 * 1203 * Finally, CNTFRQ is effectively capped at 1GHz to ensure our scale factor 1204 * cannot become zero. 1205 */ 1206 return NANOSECONDS_PER_SECOND > cpu->gt_cntfrq_hz ? 1207 NANOSECONDS_PER_SECOND / cpu->gt_cntfrq_hz : 1; 1208 } 1209 1210 void arm_cpu_post_init(Object *obj) 1211 { 1212 ARMCPU *cpu = ARM_CPU(obj); 1213 1214 /* M profile implies PMSA. We have to do this here rather than 1215 * in realize with the other feature-implication checks because 1216 * we look at the PMSA bit to see if we should add some properties. 1217 */ 1218 if (arm_feature(&cpu->env, ARM_FEATURE_M)) { 1219 set_feature(&cpu->env, ARM_FEATURE_PMSA); 1220 } 1221 1222 if (arm_feature(&cpu->env, ARM_FEATURE_CBAR) || 1223 arm_feature(&cpu->env, ARM_FEATURE_CBAR_RO)) { 1224 qdev_property_add_static(DEVICE(obj), &arm_cpu_reset_cbar_property); 1225 } 1226 1227 if (!arm_feature(&cpu->env, ARM_FEATURE_M)) { 1228 qdev_property_add_static(DEVICE(obj), &arm_cpu_reset_hivecs_property); 1229 } 1230 1231 if (arm_feature(&cpu->env, ARM_FEATURE_AARCH64)) { 1232 object_property_add_uint64_ptr(obj, "rvbar", 1233 &cpu->rvbar_prop, 1234 OBJ_PROP_FLAG_READWRITE); 1235 } 1236 1237 #ifndef CONFIG_USER_ONLY 1238 if (arm_feature(&cpu->env, ARM_FEATURE_EL3)) { 1239 /* Add the has_el3 state CPU property only if EL3 is allowed. This will 1240 * prevent "has_el3" from existing on CPUs which cannot support EL3. 1241 */ 1242 qdev_property_add_static(DEVICE(obj), &arm_cpu_has_el3_property); 1243 1244 object_property_add_link(obj, "secure-memory", 1245 TYPE_MEMORY_REGION, 1246 (Object **)&cpu->secure_memory, 1247 qdev_prop_allow_set_link_before_realize, 1248 OBJ_PROP_LINK_STRONG); 1249 } 1250 1251 if (arm_feature(&cpu->env, ARM_FEATURE_EL2)) { 1252 qdev_property_add_static(DEVICE(obj), &arm_cpu_has_el2_property); 1253 } 1254 #endif 1255 1256 if (arm_feature(&cpu->env, ARM_FEATURE_PMU)) { 1257 cpu->has_pmu = true; 1258 object_property_add_bool(obj, "pmu", arm_get_pmu, arm_set_pmu); 1259 } 1260 1261 /* 1262 * Allow user to turn off VFP and Neon support, but only for TCG -- 1263 * KVM does not currently allow us to lie to the guest about its 1264 * ID/feature registers, so the guest always sees what the host has. 1265 */ 1266 if (arm_feature(&cpu->env, ARM_FEATURE_AARCH64) 1267 ? cpu_isar_feature(aa64_fp_simd, cpu) 1268 : cpu_isar_feature(aa32_vfp, cpu)) { 1269 cpu->has_vfp = true; 1270 if (!kvm_enabled()) { 1271 qdev_property_add_static(DEVICE(obj), &arm_cpu_has_vfp_property); 1272 } 1273 } 1274 1275 if (arm_feature(&cpu->env, ARM_FEATURE_NEON)) { 1276 cpu->has_neon = true; 1277 if (!kvm_enabled()) { 1278 qdev_property_add_static(DEVICE(obj), &arm_cpu_has_neon_property); 1279 } 1280 } 1281 1282 if (arm_feature(&cpu->env, ARM_FEATURE_M) && 1283 arm_feature(&cpu->env, ARM_FEATURE_THUMB_DSP)) { 1284 qdev_property_add_static(DEVICE(obj), &arm_cpu_has_dsp_property); 1285 } 1286 1287 if (arm_feature(&cpu->env, ARM_FEATURE_PMSA)) { 1288 qdev_property_add_static(DEVICE(obj), &arm_cpu_has_mpu_property); 1289 if (arm_feature(&cpu->env, ARM_FEATURE_V7)) { 1290 qdev_property_add_static(DEVICE(obj), 1291 &arm_cpu_pmsav7_dregion_property); 1292 } 1293 } 1294 1295 if (arm_feature(&cpu->env, ARM_FEATURE_M_SECURITY)) { 1296 object_property_add_link(obj, "idau", TYPE_IDAU_INTERFACE, &cpu->idau, 1297 qdev_prop_allow_set_link_before_realize, 1298 OBJ_PROP_LINK_STRONG); 1299 /* 1300 * M profile: initial value of the Secure VTOR. We can't just use 1301 * a simple DEFINE_PROP_UINT32 for this because we want to permit 1302 * the property to be set after realize. 1303 */ 1304 object_property_add_uint32_ptr(obj, "init-svtor", 1305 &cpu->init_svtor, 1306 OBJ_PROP_FLAG_READWRITE); 1307 } 1308 if (arm_feature(&cpu->env, ARM_FEATURE_M)) { 1309 /* 1310 * Initial value of the NS VTOR (for cores without the Security 1311 * extension, this is the only VTOR) 1312 */ 1313 object_property_add_uint32_ptr(obj, "init-nsvtor", 1314 &cpu->init_nsvtor, 1315 OBJ_PROP_FLAG_READWRITE); 1316 } 1317 1318 /* Not DEFINE_PROP_UINT32: we want this to be settable after realize */ 1319 object_property_add_uint32_ptr(obj, "psci-conduit", 1320 &cpu->psci_conduit, 1321 OBJ_PROP_FLAG_READWRITE); 1322 1323 qdev_property_add_static(DEVICE(obj), &arm_cpu_cfgend_property); 1324 1325 if (arm_feature(&cpu->env, ARM_FEATURE_GENERIC_TIMER)) { 1326 qdev_property_add_static(DEVICE(cpu), &arm_cpu_gt_cntfrq_property); 1327 } 1328 1329 if (kvm_enabled()) { 1330 kvm_arm_add_vcpu_properties(obj); 1331 } 1332 1333 #ifndef CONFIG_USER_ONLY 1334 if (arm_feature(&cpu->env, ARM_FEATURE_AARCH64) && 1335 cpu_isar_feature(aa64_mte, cpu)) { 1336 object_property_add_link(obj, "tag-memory", 1337 TYPE_MEMORY_REGION, 1338 (Object **)&cpu->tag_memory, 1339 qdev_prop_allow_set_link_before_realize, 1340 OBJ_PROP_LINK_STRONG); 1341 1342 if (arm_feature(&cpu->env, ARM_FEATURE_EL3)) { 1343 object_property_add_link(obj, "secure-tag-memory", 1344 TYPE_MEMORY_REGION, 1345 (Object **)&cpu->secure_tag_memory, 1346 qdev_prop_allow_set_link_before_realize, 1347 OBJ_PROP_LINK_STRONG); 1348 } 1349 } 1350 #endif 1351 } 1352 1353 static void arm_cpu_finalizefn(Object *obj) 1354 { 1355 ARMCPU *cpu = ARM_CPU(obj); 1356 ARMELChangeHook *hook, *next; 1357 1358 g_hash_table_destroy(cpu->cp_regs); 1359 1360 QLIST_FOREACH_SAFE(hook, &cpu->pre_el_change_hooks, node, next) { 1361 QLIST_REMOVE(hook, node); 1362 g_free(hook); 1363 } 1364 QLIST_FOREACH_SAFE(hook, &cpu->el_change_hooks, node, next) { 1365 QLIST_REMOVE(hook, node); 1366 g_free(hook); 1367 } 1368 #ifndef CONFIG_USER_ONLY 1369 if (cpu->pmu_timer) { 1370 timer_free(cpu->pmu_timer); 1371 } 1372 #endif 1373 } 1374 1375 void arm_cpu_finalize_features(ARMCPU *cpu, Error **errp) 1376 { 1377 Error *local_err = NULL; 1378 1379 if (arm_feature(&cpu->env, ARM_FEATURE_AARCH64)) { 1380 arm_cpu_sve_finalize(cpu, &local_err); 1381 if (local_err != NULL) { 1382 error_propagate(errp, local_err); 1383 return; 1384 } 1385 1386 arm_cpu_pauth_finalize(cpu, &local_err); 1387 if (local_err != NULL) { 1388 error_propagate(errp, local_err); 1389 return; 1390 } 1391 1392 arm_cpu_lpa2_finalize(cpu, &local_err); 1393 if (local_err != NULL) { 1394 error_propagate(errp, local_err); 1395 return; 1396 } 1397 } 1398 1399 if (kvm_enabled()) { 1400 kvm_arm_steal_time_finalize(cpu, &local_err); 1401 if (local_err != NULL) { 1402 error_propagate(errp, local_err); 1403 return; 1404 } 1405 } 1406 } 1407 1408 static void arm_cpu_realizefn(DeviceState *dev, Error **errp) 1409 { 1410 CPUState *cs = CPU(dev); 1411 ARMCPU *cpu = ARM_CPU(dev); 1412 ARMCPUClass *acc = ARM_CPU_GET_CLASS(dev); 1413 CPUARMState *env = &cpu->env; 1414 int pagebits; 1415 Error *local_err = NULL; 1416 bool no_aa32 = false; 1417 1418 /* If we needed to query the host kernel for the CPU features 1419 * then it's possible that might have failed in the initfn, but 1420 * this is the first point where we can report it. 1421 */ 1422 if (cpu->host_cpu_probe_failed) { 1423 if (!kvm_enabled() && !hvf_enabled()) { 1424 error_setg(errp, "The 'host' CPU type can only be used with KVM or HVF"); 1425 } else { 1426 error_setg(errp, "Failed to retrieve host CPU features"); 1427 } 1428 return; 1429 } 1430 1431 #ifndef CONFIG_USER_ONLY 1432 /* The NVIC and M-profile CPU are two halves of a single piece of 1433 * hardware; trying to use one without the other is a command line 1434 * error and will result in segfaults if not caught here. 1435 */ 1436 if (arm_feature(env, ARM_FEATURE_M)) { 1437 if (!env->nvic) { 1438 error_setg(errp, "This board cannot be used with Cortex-M CPUs"); 1439 return; 1440 } 1441 } else { 1442 if (env->nvic) { 1443 error_setg(errp, "This board can only be used with Cortex-M CPUs"); 1444 return; 1445 } 1446 } 1447 1448 if (kvm_enabled()) { 1449 /* 1450 * Catch all the cases which might cause us to create more than one 1451 * address space for the CPU (otherwise we will assert() later in 1452 * cpu_address_space_init()). 1453 */ 1454 if (arm_feature(env, ARM_FEATURE_M)) { 1455 error_setg(errp, 1456 "Cannot enable KVM when using an M-profile guest CPU"); 1457 return; 1458 } 1459 if (cpu->has_el3) { 1460 error_setg(errp, 1461 "Cannot enable KVM when guest CPU has EL3 enabled"); 1462 return; 1463 } 1464 if (cpu->tag_memory) { 1465 error_setg(errp, 1466 "Cannot enable KVM when guest CPUs has MTE enabled"); 1467 return; 1468 } 1469 } 1470 1471 { 1472 uint64_t scale; 1473 1474 if (arm_feature(env, ARM_FEATURE_GENERIC_TIMER)) { 1475 if (!cpu->gt_cntfrq_hz) { 1476 error_setg(errp, "Invalid CNTFRQ: %"PRId64"Hz", 1477 cpu->gt_cntfrq_hz); 1478 return; 1479 } 1480 scale = gt_cntfrq_period_ns(cpu); 1481 } else { 1482 scale = GTIMER_SCALE; 1483 } 1484 1485 cpu->gt_timer[GTIMER_PHYS] = timer_new(QEMU_CLOCK_VIRTUAL, scale, 1486 arm_gt_ptimer_cb, cpu); 1487 cpu->gt_timer[GTIMER_VIRT] = timer_new(QEMU_CLOCK_VIRTUAL, scale, 1488 arm_gt_vtimer_cb, cpu); 1489 cpu->gt_timer[GTIMER_HYP] = timer_new(QEMU_CLOCK_VIRTUAL, scale, 1490 arm_gt_htimer_cb, cpu); 1491 cpu->gt_timer[GTIMER_SEC] = timer_new(QEMU_CLOCK_VIRTUAL, scale, 1492 arm_gt_stimer_cb, cpu); 1493 cpu->gt_timer[GTIMER_HYPVIRT] = timer_new(QEMU_CLOCK_VIRTUAL, scale, 1494 arm_gt_hvtimer_cb, cpu); 1495 } 1496 #endif 1497 1498 cpu_exec_realizefn(cs, &local_err); 1499 if (local_err != NULL) { 1500 error_propagate(errp, local_err); 1501 return; 1502 } 1503 1504 arm_cpu_finalize_features(cpu, &local_err); 1505 if (local_err != NULL) { 1506 error_propagate(errp, local_err); 1507 return; 1508 } 1509 1510 if (arm_feature(env, ARM_FEATURE_AARCH64) && 1511 cpu->has_vfp != cpu->has_neon) { 1512 /* 1513 * This is an architectural requirement for AArch64; AArch32 is 1514 * more flexible and permits VFP-no-Neon and Neon-no-VFP. 1515 */ 1516 error_setg(errp, 1517 "AArch64 CPUs must have both VFP and Neon or neither"); 1518 return; 1519 } 1520 1521 if (!cpu->has_vfp) { 1522 uint64_t t; 1523 uint32_t u; 1524 1525 t = cpu->isar.id_aa64isar1; 1526 t = FIELD_DP64(t, ID_AA64ISAR1, JSCVT, 0); 1527 cpu->isar.id_aa64isar1 = t; 1528 1529 t = cpu->isar.id_aa64pfr0; 1530 t = FIELD_DP64(t, ID_AA64PFR0, FP, 0xf); 1531 cpu->isar.id_aa64pfr0 = t; 1532 1533 u = cpu->isar.id_isar6; 1534 u = FIELD_DP32(u, ID_ISAR6, JSCVT, 0); 1535 u = FIELD_DP32(u, ID_ISAR6, BF16, 0); 1536 cpu->isar.id_isar6 = u; 1537 1538 u = cpu->isar.mvfr0; 1539 u = FIELD_DP32(u, MVFR0, FPSP, 0); 1540 u = FIELD_DP32(u, MVFR0, FPDP, 0); 1541 u = FIELD_DP32(u, MVFR0, FPDIVIDE, 0); 1542 u = FIELD_DP32(u, MVFR0, FPSQRT, 0); 1543 u = FIELD_DP32(u, MVFR0, FPROUND, 0); 1544 if (!arm_feature(env, ARM_FEATURE_M)) { 1545 u = FIELD_DP32(u, MVFR0, FPTRAP, 0); 1546 u = FIELD_DP32(u, MVFR0, FPSHVEC, 0); 1547 } 1548 cpu->isar.mvfr0 = u; 1549 1550 u = cpu->isar.mvfr1; 1551 u = FIELD_DP32(u, MVFR1, FPFTZ, 0); 1552 u = FIELD_DP32(u, MVFR1, FPDNAN, 0); 1553 u = FIELD_DP32(u, MVFR1, FPHP, 0); 1554 if (arm_feature(env, ARM_FEATURE_M)) { 1555 u = FIELD_DP32(u, MVFR1, FP16, 0); 1556 } 1557 cpu->isar.mvfr1 = u; 1558 1559 u = cpu->isar.mvfr2; 1560 u = FIELD_DP32(u, MVFR2, FPMISC, 0); 1561 cpu->isar.mvfr2 = u; 1562 } 1563 1564 if (!cpu->has_neon) { 1565 uint64_t t; 1566 uint32_t u; 1567 1568 unset_feature(env, ARM_FEATURE_NEON); 1569 1570 t = cpu->isar.id_aa64isar0; 1571 t = FIELD_DP64(t, ID_AA64ISAR0, AES, 0); 1572 t = FIELD_DP64(t, ID_AA64ISAR0, SHA1, 0); 1573 t = FIELD_DP64(t, ID_AA64ISAR0, SHA2, 0); 1574 t = FIELD_DP64(t, ID_AA64ISAR0, SHA3, 0); 1575 t = FIELD_DP64(t, ID_AA64ISAR0, SM3, 0); 1576 t = FIELD_DP64(t, ID_AA64ISAR0, SM4, 0); 1577 t = FIELD_DP64(t, ID_AA64ISAR0, DP, 0); 1578 cpu->isar.id_aa64isar0 = t; 1579 1580 t = cpu->isar.id_aa64isar1; 1581 t = FIELD_DP64(t, ID_AA64ISAR1, FCMA, 0); 1582 t = FIELD_DP64(t, ID_AA64ISAR1, BF16, 0); 1583 t = FIELD_DP64(t, ID_AA64ISAR1, I8MM, 0); 1584 cpu->isar.id_aa64isar1 = t; 1585 1586 t = cpu->isar.id_aa64pfr0; 1587 t = FIELD_DP64(t, ID_AA64PFR0, ADVSIMD, 0xf); 1588 cpu->isar.id_aa64pfr0 = t; 1589 1590 u = cpu->isar.id_isar5; 1591 u = FIELD_DP32(u, ID_ISAR5, AES, 0); 1592 u = FIELD_DP32(u, ID_ISAR5, SHA1, 0); 1593 u = FIELD_DP32(u, ID_ISAR5, SHA2, 0); 1594 u = FIELD_DP32(u, ID_ISAR5, RDM, 0); 1595 u = FIELD_DP32(u, ID_ISAR5, VCMA, 0); 1596 cpu->isar.id_isar5 = u; 1597 1598 u = cpu->isar.id_isar6; 1599 u = FIELD_DP32(u, ID_ISAR6, DP, 0); 1600 u = FIELD_DP32(u, ID_ISAR6, FHM, 0); 1601 u = FIELD_DP32(u, ID_ISAR6, BF16, 0); 1602 u = FIELD_DP32(u, ID_ISAR6, I8MM, 0); 1603 cpu->isar.id_isar6 = u; 1604 1605 if (!arm_feature(env, ARM_FEATURE_M)) { 1606 u = cpu->isar.mvfr1; 1607 u = FIELD_DP32(u, MVFR1, SIMDLS, 0); 1608 u = FIELD_DP32(u, MVFR1, SIMDINT, 0); 1609 u = FIELD_DP32(u, MVFR1, SIMDSP, 0); 1610 u = FIELD_DP32(u, MVFR1, SIMDHP, 0); 1611 cpu->isar.mvfr1 = u; 1612 1613 u = cpu->isar.mvfr2; 1614 u = FIELD_DP32(u, MVFR2, SIMDMISC, 0); 1615 cpu->isar.mvfr2 = u; 1616 } 1617 } 1618 1619 if (!cpu->has_neon && !cpu->has_vfp) { 1620 uint64_t t; 1621 uint32_t u; 1622 1623 t = cpu->isar.id_aa64isar0; 1624 t = FIELD_DP64(t, ID_AA64ISAR0, FHM, 0); 1625 cpu->isar.id_aa64isar0 = t; 1626 1627 t = cpu->isar.id_aa64isar1; 1628 t = FIELD_DP64(t, ID_AA64ISAR1, FRINTTS, 0); 1629 cpu->isar.id_aa64isar1 = t; 1630 1631 u = cpu->isar.mvfr0; 1632 u = FIELD_DP32(u, MVFR0, SIMDREG, 0); 1633 cpu->isar.mvfr0 = u; 1634 1635 /* Despite the name, this field covers both VFP and Neon */ 1636 u = cpu->isar.mvfr1; 1637 u = FIELD_DP32(u, MVFR1, SIMDFMAC, 0); 1638 cpu->isar.mvfr1 = u; 1639 } 1640 1641 if (arm_feature(env, ARM_FEATURE_M) && !cpu->has_dsp) { 1642 uint32_t u; 1643 1644 unset_feature(env, ARM_FEATURE_THUMB_DSP); 1645 1646 u = cpu->isar.id_isar1; 1647 u = FIELD_DP32(u, ID_ISAR1, EXTEND, 1); 1648 cpu->isar.id_isar1 = u; 1649 1650 u = cpu->isar.id_isar2; 1651 u = FIELD_DP32(u, ID_ISAR2, MULTU, 1); 1652 u = FIELD_DP32(u, ID_ISAR2, MULTS, 1); 1653 cpu->isar.id_isar2 = u; 1654 1655 u = cpu->isar.id_isar3; 1656 u = FIELD_DP32(u, ID_ISAR3, SIMD, 1); 1657 u = FIELD_DP32(u, ID_ISAR3, SATURATE, 0); 1658 cpu->isar.id_isar3 = u; 1659 } 1660 1661 /* Some features automatically imply others: */ 1662 if (arm_feature(env, ARM_FEATURE_V8)) { 1663 if (arm_feature(env, ARM_FEATURE_M)) { 1664 set_feature(env, ARM_FEATURE_V7); 1665 } else { 1666 set_feature(env, ARM_FEATURE_V7VE); 1667 } 1668 } 1669 1670 /* 1671 * There exist AArch64 cpus without AArch32 support. When KVM 1672 * queries ID_ISAR0_EL1 on such a host, the value is UNKNOWN. 1673 * Similarly, we cannot check ID_AA64PFR0 without AArch64 support. 1674 * As a general principle, we also do not make ID register 1675 * consistency checks anywhere unless using TCG, because only 1676 * for TCG would a consistency-check failure be a QEMU bug. 1677 */ 1678 if (arm_feature(&cpu->env, ARM_FEATURE_AARCH64)) { 1679 no_aa32 = !cpu_isar_feature(aa64_aa32, cpu); 1680 } 1681 1682 if (arm_feature(env, ARM_FEATURE_V7VE)) { 1683 /* v7 Virtualization Extensions. In real hardware this implies 1684 * EL2 and also the presence of the Security Extensions. 1685 * For QEMU, for backwards-compatibility we implement some 1686 * CPUs or CPU configs which have no actual EL2 or EL3 but do 1687 * include the various other features that V7VE implies. 1688 * Presence of EL2 itself is ARM_FEATURE_EL2, and of the 1689 * Security Extensions is ARM_FEATURE_EL3. 1690 */ 1691 assert(!tcg_enabled() || no_aa32 || 1692 cpu_isar_feature(aa32_arm_div, cpu)); 1693 set_feature(env, ARM_FEATURE_LPAE); 1694 set_feature(env, ARM_FEATURE_V7); 1695 } 1696 if (arm_feature(env, ARM_FEATURE_V7)) { 1697 set_feature(env, ARM_FEATURE_VAPA); 1698 set_feature(env, ARM_FEATURE_THUMB2); 1699 set_feature(env, ARM_FEATURE_MPIDR); 1700 if (!arm_feature(env, ARM_FEATURE_M)) { 1701 set_feature(env, ARM_FEATURE_V6K); 1702 } else { 1703 set_feature(env, ARM_FEATURE_V6); 1704 } 1705 1706 /* Always define VBAR for V7 CPUs even if it doesn't exist in 1707 * non-EL3 configs. This is needed by some legacy boards. 1708 */ 1709 set_feature(env, ARM_FEATURE_VBAR); 1710 } 1711 if (arm_feature(env, ARM_FEATURE_V6K)) { 1712 set_feature(env, ARM_FEATURE_V6); 1713 set_feature(env, ARM_FEATURE_MVFR); 1714 } 1715 if (arm_feature(env, ARM_FEATURE_V6)) { 1716 set_feature(env, ARM_FEATURE_V5); 1717 if (!arm_feature(env, ARM_FEATURE_M)) { 1718 assert(!tcg_enabled() || no_aa32 || 1719 cpu_isar_feature(aa32_jazelle, cpu)); 1720 set_feature(env, ARM_FEATURE_AUXCR); 1721 } 1722 } 1723 if (arm_feature(env, ARM_FEATURE_V5)) { 1724 set_feature(env, ARM_FEATURE_V4T); 1725 } 1726 if (arm_feature(env, ARM_FEATURE_LPAE)) { 1727 set_feature(env, ARM_FEATURE_V7MP); 1728 } 1729 if (arm_feature(env, ARM_FEATURE_CBAR_RO)) { 1730 set_feature(env, ARM_FEATURE_CBAR); 1731 } 1732 if (arm_feature(env, ARM_FEATURE_THUMB2) && 1733 !arm_feature(env, ARM_FEATURE_M)) { 1734 set_feature(env, ARM_FEATURE_THUMB_DSP); 1735 } 1736 1737 /* 1738 * We rely on no XScale CPU having VFP so we can use the same bits in the 1739 * TB flags field for VECSTRIDE and XSCALE_CPAR. 1740 */ 1741 assert(arm_feature(&cpu->env, ARM_FEATURE_AARCH64) || 1742 !cpu_isar_feature(aa32_vfp_simd, cpu) || 1743 !arm_feature(env, ARM_FEATURE_XSCALE)); 1744 1745 if (arm_feature(env, ARM_FEATURE_V7) && 1746 !arm_feature(env, ARM_FEATURE_M) && 1747 !arm_feature(env, ARM_FEATURE_PMSA)) { 1748 /* v7VMSA drops support for the old ARMv5 tiny pages, so we 1749 * can use 4K pages. 1750 */ 1751 pagebits = 12; 1752 } else { 1753 /* For CPUs which might have tiny 1K pages, or which have an 1754 * MPU and might have small region sizes, stick with 1K pages. 1755 */ 1756 pagebits = 10; 1757 } 1758 if (!set_preferred_target_page_bits(pagebits)) { 1759 /* This can only ever happen for hotplugging a CPU, or if 1760 * the board code incorrectly creates a CPU which it has 1761 * promised via minimum_page_size that it will not. 1762 */ 1763 error_setg(errp, "This CPU requires a smaller page size than the " 1764 "system is using"); 1765 return; 1766 } 1767 1768 /* This cpu-id-to-MPIDR affinity is used only for TCG; KVM will override it. 1769 * We don't support setting cluster ID ([16..23]) (known as Aff2 1770 * in later ARM ARM versions), or any of the higher affinity level fields, 1771 * so these bits always RAZ. 1772 */ 1773 if (cpu->mp_affinity == ARM64_AFFINITY_INVALID) { 1774 cpu->mp_affinity = arm_cpu_mp_affinity(cs->cpu_index, 1775 ARM_DEFAULT_CPUS_PER_CLUSTER); 1776 } 1777 1778 if (cpu->reset_hivecs) { 1779 cpu->reset_sctlr |= (1 << 13); 1780 } 1781 1782 if (cpu->cfgend) { 1783 if (arm_feature(&cpu->env, ARM_FEATURE_V7)) { 1784 cpu->reset_sctlr |= SCTLR_EE; 1785 } else { 1786 cpu->reset_sctlr |= SCTLR_B; 1787 } 1788 } 1789 1790 if (!arm_feature(env, ARM_FEATURE_M) && !cpu->has_el3) { 1791 /* If the has_el3 CPU property is disabled then we need to disable the 1792 * feature. 1793 */ 1794 unset_feature(env, ARM_FEATURE_EL3); 1795 1796 /* Disable the security extension feature bits in the processor feature 1797 * registers as well. These are id_pfr1[7:4] and id_aa64pfr0[15:12]. 1798 */ 1799 cpu->isar.id_pfr1 &= ~0xf0; 1800 cpu->isar.id_aa64pfr0 &= ~0xf000; 1801 } 1802 1803 if (!cpu->has_el2) { 1804 unset_feature(env, ARM_FEATURE_EL2); 1805 } 1806 1807 if (!cpu->has_pmu) { 1808 unset_feature(env, ARM_FEATURE_PMU); 1809 } 1810 if (arm_feature(env, ARM_FEATURE_PMU)) { 1811 pmu_init(cpu); 1812 1813 if (!kvm_enabled()) { 1814 arm_register_pre_el_change_hook(cpu, &pmu_pre_el_change, 0); 1815 arm_register_el_change_hook(cpu, &pmu_post_el_change, 0); 1816 } 1817 1818 #ifndef CONFIG_USER_ONLY 1819 cpu->pmu_timer = timer_new_ns(QEMU_CLOCK_VIRTUAL, arm_pmu_timer_cb, 1820 cpu); 1821 #endif 1822 } else { 1823 cpu->isar.id_aa64dfr0 = 1824 FIELD_DP64(cpu->isar.id_aa64dfr0, ID_AA64DFR0, PMUVER, 0); 1825 cpu->isar.id_dfr0 = FIELD_DP32(cpu->isar.id_dfr0, ID_DFR0, PERFMON, 0); 1826 cpu->pmceid0 = 0; 1827 cpu->pmceid1 = 0; 1828 } 1829 1830 if (!arm_feature(env, ARM_FEATURE_EL2)) { 1831 /* Disable the hypervisor feature bits in the processor feature 1832 * registers if we don't have EL2. These are id_pfr1[15:12] and 1833 * id_aa64pfr0_el1[11:8]. 1834 */ 1835 cpu->isar.id_aa64pfr0 &= ~0xf00; 1836 cpu->isar.id_pfr1 &= ~0xf000; 1837 } 1838 1839 #ifndef CONFIG_USER_ONLY 1840 if (cpu->tag_memory == NULL && cpu_isar_feature(aa64_mte, cpu)) { 1841 /* 1842 * Disable the MTE feature bits if we do not have tag-memory 1843 * provided by the machine. 1844 */ 1845 cpu->isar.id_aa64pfr1 = 1846 FIELD_DP64(cpu->isar.id_aa64pfr1, ID_AA64PFR1, MTE, 0); 1847 } 1848 #endif 1849 1850 /* MPU can be configured out of a PMSA CPU either by setting has-mpu 1851 * to false or by setting pmsav7-dregion to 0. 1852 */ 1853 if (!cpu->has_mpu) { 1854 cpu->pmsav7_dregion = 0; 1855 } 1856 if (cpu->pmsav7_dregion == 0) { 1857 cpu->has_mpu = false; 1858 } 1859 1860 if (arm_feature(env, ARM_FEATURE_PMSA) && 1861 arm_feature(env, ARM_FEATURE_V7)) { 1862 uint32_t nr = cpu->pmsav7_dregion; 1863 1864 if (nr > 0xff) { 1865 error_setg(errp, "PMSAv7 MPU #regions invalid %" PRIu32, nr); 1866 return; 1867 } 1868 1869 if (nr) { 1870 if (arm_feature(env, ARM_FEATURE_V8)) { 1871 /* PMSAv8 */ 1872 env->pmsav8.rbar[M_REG_NS] = g_new0(uint32_t, nr); 1873 env->pmsav8.rlar[M_REG_NS] = g_new0(uint32_t, nr); 1874 if (arm_feature(env, ARM_FEATURE_M_SECURITY)) { 1875 env->pmsav8.rbar[M_REG_S] = g_new0(uint32_t, nr); 1876 env->pmsav8.rlar[M_REG_S] = g_new0(uint32_t, nr); 1877 } 1878 } else { 1879 env->pmsav7.drbar = g_new0(uint32_t, nr); 1880 env->pmsav7.drsr = g_new0(uint32_t, nr); 1881 env->pmsav7.dracr = g_new0(uint32_t, nr); 1882 } 1883 } 1884 } 1885 1886 if (arm_feature(env, ARM_FEATURE_M_SECURITY)) { 1887 uint32_t nr = cpu->sau_sregion; 1888 1889 if (nr > 0xff) { 1890 error_setg(errp, "v8M SAU #regions invalid %" PRIu32, nr); 1891 return; 1892 } 1893 1894 if (nr) { 1895 env->sau.rbar = g_new0(uint32_t, nr); 1896 env->sau.rlar = g_new0(uint32_t, nr); 1897 } 1898 } 1899 1900 if (arm_feature(env, ARM_FEATURE_EL3)) { 1901 set_feature(env, ARM_FEATURE_VBAR); 1902 } 1903 1904 register_cp_regs_for_features(cpu); 1905 arm_cpu_register_gdb_regs_for_features(cpu); 1906 1907 init_cpreg_list(cpu); 1908 1909 #ifndef CONFIG_USER_ONLY 1910 MachineState *ms = MACHINE(qdev_get_machine()); 1911 unsigned int smp_cpus = ms->smp.cpus; 1912 bool has_secure = cpu->has_el3 || arm_feature(env, ARM_FEATURE_M_SECURITY); 1913 1914 /* 1915 * We must set cs->num_ases to the final value before 1916 * the first call to cpu_address_space_init. 1917 */ 1918 if (cpu->tag_memory != NULL) { 1919 cs->num_ases = 3 + has_secure; 1920 } else { 1921 cs->num_ases = 1 + has_secure; 1922 } 1923 1924 if (has_secure) { 1925 if (!cpu->secure_memory) { 1926 cpu->secure_memory = cs->memory; 1927 } 1928 cpu_address_space_init(cs, ARMASIdx_S, "cpu-secure-memory", 1929 cpu->secure_memory); 1930 } 1931 1932 if (cpu->tag_memory != NULL) { 1933 cpu_address_space_init(cs, ARMASIdx_TagNS, "cpu-tag-memory", 1934 cpu->tag_memory); 1935 if (has_secure) { 1936 cpu_address_space_init(cs, ARMASIdx_TagS, "cpu-tag-memory", 1937 cpu->secure_tag_memory); 1938 } 1939 } 1940 1941 cpu_address_space_init(cs, ARMASIdx_NS, "cpu-memory", cs->memory); 1942 1943 /* No core_count specified, default to smp_cpus. */ 1944 if (cpu->core_count == -1) { 1945 cpu->core_count = smp_cpus; 1946 } 1947 #endif 1948 1949 if (tcg_enabled()) { 1950 int dcz_blocklen = 4 << cpu->dcz_blocksize; 1951 1952 /* 1953 * We only support DCZ blocklen that fits on one page. 1954 * 1955 * Architectually this is always true. However TARGET_PAGE_SIZE 1956 * is variable and, for compatibility with -machine virt-2.7, 1957 * is only 1KiB, as an artifact of legacy ARMv5 subpage support. 1958 * But even then, while the largest architectural DCZ blocklen 1959 * is 2KiB, no cpu actually uses such a large blocklen. 1960 */ 1961 assert(dcz_blocklen <= TARGET_PAGE_SIZE); 1962 1963 /* 1964 * We only support DCZ blocksize >= 2*TAG_GRANULE, which is to say 1965 * both nibbles of each byte storing tag data may be written at once. 1966 * Since TAG_GRANULE is 16, this means that blocklen must be >= 32. 1967 */ 1968 if (cpu_isar_feature(aa64_mte, cpu)) { 1969 assert(dcz_blocklen >= 2 * TAG_GRANULE); 1970 } 1971 } 1972 1973 qemu_init_vcpu(cs); 1974 cpu_reset(cs); 1975 1976 acc->parent_realize(dev, errp); 1977 } 1978 1979 static ObjectClass *arm_cpu_class_by_name(const char *cpu_model) 1980 { 1981 ObjectClass *oc; 1982 char *typename; 1983 char **cpuname; 1984 const char *cpunamestr; 1985 1986 cpuname = g_strsplit(cpu_model, ",", 1); 1987 cpunamestr = cpuname[0]; 1988 #ifdef CONFIG_USER_ONLY 1989 /* For backwards compatibility usermode emulation allows "-cpu any", 1990 * which has the same semantics as "-cpu max". 1991 */ 1992 if (!strcmp(cpunamestr, "any")) { 1993 cpunamestr = "max"; 1994 } 1995 #endif 1996 typename = g_strdup_printf(ARM_CPU_TYPE_NAME("%s"), cpunamestr); 1997 oc = object_class_by_name(typename); 1998 g_strfreev(cpuname); 1999 g_free(typename); 2000 if (!oc || !object_class_dynamic_cast(oc, TYPE_ARM_CPU) || 2001 object_class_is_abstract(oc)) { 2002 return NULL; 2003 } 2004 return oc; 2005 } 2006 2007 static Property arm_cpu_properties[] = { 2008 DEFINE_PROP_UINT64("midr", ARMCPU, midr, 0), 2009 DEFINE_PROP_UINT64("mp-affinity", ARMCPU, 2010 mp_affinity, ARM64_AFFINITY_INVALID), 2011 DEFINE_PROP_INT32("node-id", ARMCPU, node_id, CPU_UNSET_NUMA_NODE_ID), 2012 DEFINE_PROP_INT32("core-count", ARMCPU, core_count, -1), 2013 DEFINE_PROP_END_OF_LIST() 2014 }; 2015 2016 static gchar *arm_gdb_arch_name(CPUState *cs) 2017 { 2018 ARMCPU *cpu = ARM_CPU(cs); 2019 CPUARMState *env = &cpu->env; 2020 2021 if (arm_feature(env, ARM_FEATURE_IWMMXT)) { 2022 return g_strdup("iwmmxt"); 2023 } 2024 return g_strdup("arm"); 2025 } 2026 2027 #ifndef CONFIG_USER_ONLY 2028 #include "hw/core/sysemu-cpu-ops.h" 2029 2030 static const struct SysemuCPUOps arm_sysemu_ops = { 2031 .get_phys_page_attrs_debug = arm_cpu_get_phys_page_attrs_debug, 2032 .asidx_from_attrs = arm_asidx_from_attrs, 2033 .write_elf32_note = arm_cpu_write_elf32_note, 2034 .write_elf64_note = arm_cpu_write_elf64_note, 2035 .virtio_is_big_endian = arm_cpu_virtio_is_big_endian, 2036 .legacy_vmsd = &vmstate_arm_cpu, 2037 }; 2038 #endif 2039 2040 #ifdef CONFIG_TCG 2041 static const struct TCGCPUOps arm_tcg_ops = { 2042 .initialize = arm_translate_init, 2043 .synchronize_from_tb = arm_cpu_synchronize_from_tb, 2044 .debug_excp_handler = arm_debug_excp_handler, 2045 2046 #ifdef CONFIG_USER_ONLY 2047 .record_sigsegv = arm_cpu_record_sigsegv, 2048 .record_sigbus = arm_cpu_record_sigbus, 2049 #else 2050 .tlb_fill = arm_cpu_tlb_fill, 2051 .cpu_exec_interrupt = arm_cpu_exec_interrupt, 2052 .do_interrupt = arm_cpu_do_interrupt, 2053 .do_transaction_failed = arm_cpu_do_transaction_failed, 2054 .do_unaligned_access = arm_cpu_do_unaligned_access, 2055 .adjust_watchpoint_address = arm_adjust_watchpoint_address, 2056 .debug_check_watchpoint = arm_debug_check_watchpoint, 2057 .debug_check_breakpoint = arm_debug_check_breakpoint, 2058 #endif /* !CONFIG_USER_ONLY */ 2059 }; 2060 #endif /* CONFIG_TCG */ 2061 2062 static void arm_cpu_class_init(ObjectClass *oc, void *data) 2063 { 2064 ARMCPUClass *acc = ARM_CPU_CLASS(oc); 2065 CPUClass *cc = CPU_CLASS(acc); 2066 DeviceClass *dc = DEVICE_CLASS(oc); 2067 2068 device_class_set_parent_realize(dc, arm_cpu_realizefn, 2069 &acc->parent_realize); 2070 2071 device_class_set_props(dc, arm_cpu_properties); 2072 device_class_set_parent_reset(dc, arm_cpu_reset, &acc->parent_reset); 2073 2074 cc->class_by_name = arm_cpu_class_by_name; 2075 cc->has_work = arm_cpu_has_work; 2076 cc->dump_state = arm_cpu_dump_state; 2077 cc->set_pc = arm_cpu_set_pc; 2078 cc->gdb_read_register = arm_cpu_gdb_read_register; 2079 cc->gdb_write_register = arm_cpu_gdb_write_register; 2080 #ifndef CONFIG_USER_ONLY 2081 cc->sysemu_ops = &arm_sysemu_ops; 2082 #endif 2083 cc->gdb_num_core_regs = 26; 2084 cc->gdb_core_xml_file = "arm-core.xml"; 2085 cc->gdb_arch_name = arm_gdb_arch_name; 2086 cc->gdb_get_dynamic_xml = arm_gdb_get_dynamic_xml; 2087 cc->gdb_stop_before_watchpoint = true; 2088 cc->disas_set_info = arm_disas_set_info; 2089 2090 #ifdef CONFIG_TCG 2091 cc->tcg_ops = &arm_tcg_ops; 2092 #endif /* CONFIG_TCG */ 2093 } 2094 2095 static void arm_cpu_instance_init(Object *obj) 2096 { 2097 ARMCPUClass *acc = ARM_CPU_GET_CLASS(obj); 2098 2099 acc->info->initfn(obj); 2100 arm_cpu_post_init(obj); 2101 } 2102 2103 static void cpu_register_class_init(ObjectClass *oc, void *data) 2104 { 2105 ARMCPUClass *acc = ARM_CPU_CLASS(oc); 2106 2107 acc->info = data; 2108 } 2109 2110 void arm_cpu_register(const ARMCPUInfo *info) 2111 { 2112 TypeInfo type_info = { 2113 .parent = TYPE_ARM_CPU, 2114 .instance_size = sizeof(ARMCPU), 2115 .instance_align = __alignof__(ARMCPU), 2116 .instance_init = arm_cpu_instance_init, 2117 .class_size = sizeof(ARMCPUClass), 2118 .class_init = info->class_init ?: cpu_register_class_init, 2119 .class_data = (void *)info, 2120 }; 2121 2122 type_info.name = g_strdup_printf("%s-" TYPE_ARM_CPU, info->name); 2123 type_register(&type_info); 2124 g_free((void *)type_info.name); 2125 } 2126 2127 static const TypeInfo arm_cpu_type_info = { 2128 .name = TYPE_ARM_CPU, 2129 .parent = TYPE_CPU, 2130 .instance_size = sizeof(ARMCPU), 2131 .instance_align = __alignof__(ARMCPU), 2132 .instance_init = arm_cpu_initfn, 2133 .instance_finalize = arm_cpu_finalizefn, 2134 .abstract = true, 2135 .class_size = sizeof(ARMCPUClass), 2136 .class_init = arm_cpu_class_init, 2137 }; 2138 2139 static void arm_cpu_register_types(void) 2140 { 2141 type_register_static(&arm_cpu_type_info); 2142 } 2143 2144 type_init(arm_cpu_register_types) 2145