1 /* 2 * QEMU ARM CPU 3 * 4 * Copyright (c) 2012 SUSE LINUX Products GmbH 5 * 6 * This program is free software; you can redistribute it and/or 7 * modify it under the terms of the GNU General Public License 8 * as published by the Free Software Foundation; either version 2 9 * of the License, or (at your option) any later version. 10 * 11 * This program is distributed in the hope that it will be useful, 12 * but WITHOUT ANY WARRANTY; without even the implied warranty of 13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 14 * GNU General Public License for more details. 15 * 16 * You should have received a copy of the GNU General Public License 17 * along with this program; if not, see 18 * <http://www.gnu.org/licenses/gpl-2.0.html> 19 */ 20 21 #include "qemu/osdep.h" 22 #include "target/arm/idau.h" 23 #include "qemu/error-report.h" 24 #include "qapi/error.h" 25 #include "cpu.h" 26 #include "internals.h" 27 #include "qemu-common.h" 28 #include "exec/exec-all.h" 29 #include "hw/qdev-properties.h" 30 #if !defined(CONFIG_USER_ONLY) 31 #include "hw/loader.h" 32 #endif 33 #include "hw/arm/arm.h" 34 #include "sysemu/sysemu.h" 35 #include "sysemu/hw_accel.h" 36 #include "kvm_arm.h" 37 #include "disas/capstone.h" 38 #include "fpu/softfloat.h" 39 40 static void arm_cpu_set_pc(CPUState *cs, vaddr value) 41 { 42 ARMCPU *cpu = ARM_CPU(cs); 43 44 cpu->env.regs[15] = value; 45 } 46 47 static bool arm_cpu_has_work(CPUState *cs) 48 { 49 ARMCPU *cpu = ARM_CPU(cs); 50 51 return (cpu->power_state != PSCI_OFF) 52 && cs->interrupt_request & 53 (CPU_INTERRUPT_FIQ | CPU_INTERRUPT_HARD 54 | CPU_INTERRUPT_VFIQ | CPU_INTERRUPT_VIRQ 55 | CPU_INTERRUPT_EXITTB); 56 } 57 58 void arm_register_pre_el_change_hook(ARMCPU *cpu, ARMELChangeHookFn *hook, 59 void *opaque) 60 { 61 ARMELChangeHook *entry = g_new0(ARMELChangeHook, 1); 62 63 entry->hook = hook; 64 entry->opaque = opaque; 65 66 QLIST_INSERT_HEAD(&cpu->pre_el_change_hooks, entry, node); 67 } 68 69 void arm_register_el_change_hook(ARMCPU *cpu, ARMELChangeHookFn *hook, 70 void *opaque) 71 { 72 ARMELChangeHook *entry = g_new0(ARMELChangeHook, 1); 73 74 entry->hook = hook; 75 entry->opaque = opaque; 76 77 QLIST_INSERT_HEAD(&cpu->el_change_hooks, entry, node); 78 } 79 80 static void cp_reg_reset(gpointer key, gpointer value, gpointer opaque) 81 { 82 /* Reset a single ARMCPRegInfo register */ 83 ARMCPRegInfo *ri = value; 84 ARMCPU *cpu = opaque; 85 86 if (ri->type & (ARM_CP_SPECIAL | ARM_CP_ALIAS)) { 87 return; 88 } 89 90 if (ri->resetfn) { 91 ri->resetfn(&cpu->env, ri); 92 return; 93 } 94 95 /* A zero offset is never possible as it would be regs[0] 96 * so we use it to indicate that reset is being handled elsewhere. 97 * This is basically only used for fields in non-core coprocessors 98 * (like the pxa2xx ones). 99 */ 100 if (!ri->fieldoffset) { 101 return; 102 } 103 104 if (cpreg_field_is_64bit(ri)) { 105 CPREG_FIELD64(&cpu->env, ri) = ri->resetvalue; 106 } else { 107 CPREG_FIELD32(&cpu->env, ri) = ri->resetvalue; 108 } 109 } 110 111 static void cp_reg_check_reset(gpointer key, gpointer value, gpointer opaque) 112 { 113 /* Purely an assertion check: we've already done reset once, 114 * so now check that running the reset for the cpreg doesn't 115 * change its value. This traps bugs where two different cpregs 116 * both try to reset the same state field but to different values. 117 */ 118 ARMCPRegInfo *ri = value; 119 ARMCPU *cpu = opaque; 120 uint64_t oldvalue, newvalue; 121 122 if (ri->type & (ARM_CP_SPECIAL | ARM_CP_ALIAS | ARM_CP_NO_RAW)) { 123 return; 124 } 125 126 oldvalue = read_raw_cp_reg(&cpu->env, ri); 127 cp_reg_reset(key, value, opaque); 128 newvalue = read_raw_cp_reg(&cpu->env, ri); 129 assert(oldvalue == newvalue); 130 } 131 132 /* CPUClass::reset() */ 133 static void arm_cpu_reset(CPUState *s) 134 { 135 ARMCPU *cpu = ARM_CPU(s); 136 ARMCPUClass *acc = ARM_CPU_GET_CLASS(cpu); 137 CPUARMState *env = &cpu->env; 138 139 acc->parent_reset(s); 140 141 memset(env, 0, offsetof(CPUARMState, end_reset_fields)); 142 143 g_hash_table_foreach(cpu->cp_regs, cp_reg_reset, cpu); 144 g_hash_table_foreach(cpu->cp_regs, cp_reg_check_reset, cpu); 145 146 env->vfp.xregs[ARM_VFP_FPSID] = cpu->reset_fpsid; 147 env->vfp.xregs[ARM_VFP_MVFR0] = cpu->mvfr0; 148 env->vfp.xregs[ARM_VFP_MVFR1] = cpu->mvfr1; 149 env->vfp.xregs[ARM_VFP_MVFR2] = cpu->mvfr2; 150 151 cpu->power_state = cpu->start_powered_off ? PSCI_OFF : PSCI_ON; 152 s->halted = cpu->start_powered_off; 153 154 if (arm_feature(env, ARM_FEATURE_IWMMXT)) { 155 env->iwmmxt.cregs[ARM_IWMMXT_wCID] = 0x69051000 | 'Q'; 156 } 157 158 if (arm_feature(env, ARM_FEATURE_AARCH64)) { 159 /* 64 bit CPUs always start in 64 bit mode */ 160 env->aarch64 = 1; 161 #if defined(CONFIG_USER_ONLY) 162 env->pstate = PSTATE_MODE_EL0t; 163 /* Userspace expects access to DC ZVA, CTL_EL0 and the cache ops */ 164 env->cp15.sctlr_el[1] |= SCTLR_UCT | SCTLR_UCI | SCTLR_DZE; 165 /* and to the FP/Neon instructions */ 166 env->cp15.cpacr_el1 = deposit64(env->cp15.cpacr_el1, 20, 2, 3); 167 #else 168 /* Reset into the highest available EL */ 169 if (arm_feature(env, ARM_FEATURE_EL3)) { 170 env->pstate = PSTATE_MODE_EL3h; 171 } else if (arm_feature(env, ARM_FEATURE_EL2)) { 172 env->pstate = PSTATE_MODE_EL2h; 173 } else { 174 env->pstate = PSTATE_MODE_EL1h; 175 } 176 env->pc = cpu->rvbar; 177 #endif 178 } else { 179 #if defined(CONFIG_USER_ONLY) 180 /* Userspace expects access to cp10 and cp11 for FP/Neon */ 181 env->cp15.cpacr_el1 = deposit64(env->cp15.cpacr_el1, 20, 4, 0xf); 182 #endif 183 } 184 185 #if defined(CONFIG_USER_ONLY) 186 env->uncached_cpsr = ARM_CPU_MODE_USR; 187 /* For user mode we must enable access to coprocessors */ 188 env->vfp.xregs[ARM_VFP_FPEXC] = 1 << 30; 189 if (arm_feature(env, ARM_FEATURE_IWMMXT)) { 190 env->cp15.c15_cpar = 3; 191 } else if (arm_feature(env, ARM_FEATURE_XSCALE)) { 192 env->cp15.c15_cpar = 1; 193 } 194 #else 195 /* SVC mode with interrupts disabled. */ 196 env->uncached_cpsr = ARM_CPU_MODE_SVC; 197 env->daif = PSTATE_D | PSTATE_A | PSTATE_I | PSTATE_F; 198 199 if (arm_feature(env, ARM_FEATURE_M)) { 200 uint32_t initial_msp; /* Loaded from 0x0 */ 201 uint32_t initial_pc; /* Loaded from 0x4 */ 202 uint8_t *rom; 203 uint32_t vecbase; 204 205 if (arm_feature(env, ARM_FEATURE_M_SECURITY)) { 206 env->v7m.secure = true; 207 } else { 208 /* This bit resets to 0 if security is supported, but 1 if 209 * it is not. The bit is not present in v7M, but we set it 210 * here so we can avoid having to make checks on it conditional 211 * on ARM_FEATURE_V8 (we don't let the guest see the bit). 212 */ 213 env->v7m.aircr = R_V7M_AIRCR_BFHFNMINS_MASK; 214 } 215 216 /* In v7M the reset value of this bit is IMPDEF, but ARM recommends 217 * that it resets to 1, so QEMU always does that rather than making 218 * it dependent on CPU model. In v8M it is RES1. 219 */ 220 env->v7m.ccr[M_REG_NS] = R_V7M_CCR_STKALIGN_MASK; 221 env->v7m.ccr[M_REG_S] = R_V7M_CCR_STKALIGN_MASK; 222 if (arm_feature(env, ARM_FEATURE_V8)) { 223 /* in v8M the NONBASETHRDENA bit [0] is RES1 */ 224 env->v7m.ccr[M_REG_NS] |= R_V7M_CCR_NONBASETHRDENA_MASK; 225 env->v7m.ccr[M_REG_S] |= R_V7M_CCR_NONBASETHRDENA_MASK; 226 } 227 228 /* Unlike A/R profile, M profile defines the reset LR value */ 229 env->regs[14] = 0xffffffff; 230 231 env->v7m.vecbase[M_REG_S] = cpu->init_svtor & 0xffffff80; 232 233 /* Load the initial SP and PC from offset 0 and 4 in the vector table */ 234 vecbase = env->v7m.vecbase[env->v7m.secure]; 235 rom = rom_ptr(vecbase); 236 if (rom) { 237 /* Address zero is covered by ROM which hasn't yet been 238 * copied into physical memory. 239 */ 240 initial_msp = ldl_p(rom); 241 initial_pc = ldl_p(rom + 4); 242 } else { 243 /* Address zero not covered by a ROM blob, or the ROM blob 244 * is in non-modifiable memory and this is a second reset after 245 * it got copied into memory. In the latter case, rom_ptr 246 * will return a NULL pointer and we should use ldl_phys instead. 247 */ 248 initial_msp = ldl_phys(s->as, vecbase); 249 initial_pc = ldl_phys(s->as, vecbase + 4); 250 } 251 252 env->regs[13] = initial_msp & 0xFFFFFFFC; 253 env->regs[15] = initial_pc & ~1; 254 env->thumb = initial_pc & 1; 255 } 256 257 /* AArch32 has a hard highvec setting of 0xFFFF0000. If we are currently 258 * executing as AArch32 then check if highvecs are enabled and 259 * adjust the PC accordingly. 260 */ 261 if (A32_BANKED_CURRENT_REG_GET(env, sctlr) & SCTLR_V) { 262 env->regs[15] = 0xFFFF0000; 263 } 264 265 /* M profile requires that reset clears the exclusive monitor; 266 * A profile does not, but clearing it makes more sense than having it 267 * set with an exclusive access on address zero. 268 */ 269 arm_clear_exclusive(env); 270 271 env->vfp.xregs[ARM_VFP_FPEXC] = 0; 272 #endif 273 274 if (arm_feature(env, ARM_FEATURE_PMSA)) { 275 if (cpu->pmsav7_dregion > 0) { 276 if (arm_feature(env, ARM_FEATURE_V8)) { 277 memset(env->pmsav8.rbar[M_REG_NS], 0, 278 sizeof(*env->pmsav8.rbar[M_REG_NS]) 279 * cpu->pmsav7_dregion); 280 memset(env->pmsav8.rlar[M_REG_NS], 0, 281 sizeof(*env->pmsav8.rlar[M_REG_NS]) 282 * cpu->pmsav7_dregion); 283 if (arm_feature(env, ARM_FEATURE_M_SECURITY)) { 284 memset(env->pmsav8.rbar[M_REG_S], 0, 285 sizeof(*env->pmsav8.rbar[M_REG_S]) 286 * cpu->pmsav7_dregion); 287 memset(env->pmsav8.rlar[M_REG_S], 0, 288 sizeof(*env->pmsav8.rlar[M_REG_S]) 289 * cpu->pmsav7_dregion); 290 } 291 } else if (arm_feature(env, ARM_FEATURE_V7)) { 292 memset(env->pmsav7.drbar, 0, 293 sizeof(*env->pmsav7.drbar) * cpu->pmsav7_dregion); 294 memset(env->pmsav7.drsr, 0, 295 sizeof(*env->pmsav7.drsr) * cpu->pmsav7_dregion); 296 memset(env->pmsav7.dracr, 0, 297 sizeof(*env->pmsav7.dracr) * cpu->pmsav7_dregion); 298 } 299 } 300 env->pmsav7.rnr[M_REG_NS] = 0; 301 env->pmsav7.rnr[M_REG_S] = 0; 302 env->pmsav8.mair0[M_REG_NS] = 0; 303 env->pmsav8.mair0[M_REG_S] = 0; 304 env->pmsav8.mair1[M_REG_NS] = 0; 305 env->pmsav8.mair1[M_REG_S] = 0; 306 } 307 308 if (arm_feature(env, ARM_FEATURE_M_SECURITY)) { 309 if (cpu->sau_sregion > 0) { 310 memset(env->sau.rbar, 0, sizeof(*env->sau.rbar) * cpu->sau_sregion); 311 memset(env->sau.rlar, 0, sizeof(*env->sau.rlar) * cpu->sau_sregion); 312 } 313 env->sau.rnr = 0; 314 /* SAU_CTRL reset value is IMPDEF; we choose 0, which is what 315 * the Cortex-M33 does. 316 */ 317 env->sau.ctrl = 0; 318 } 319 320 set_flush_to_zero(1, &env->vfp.standard_fp_status); 321 set_flush_inputs_to_zero(1, &env->vfp.standard_fp_status); 322 set_default_nan_mode(1, &env->vfp.standard_fp_status); 323 set_float_detect_tininess(float_tininess_before_rounding, 324 &env->vfp.fp_status); 325 set_float_detect_tininess(float_tininess_before_rounding, 326 &env->vfp.standard_fp_status); 327 set_float_detect_tininess(float_tininess_before_rounding, 328 &env->vfp.fp_status_f16); 329 #ifndef CONFIG_USER_ONLY 330 if (kvm_enabled()) { 331 kvm_arm_reset_vcpu(cpu); 332 } 333 #endif 334 335 hw_breakpoint_update_all(cpu); 336 hw_watchpoint_update_all(cpu); 337 } 338 339 bool arm_cpu_exec_interrupt(CPUState *cs, int interrupt_request) 340 { 341 CPUClass *cc = CPU_GET_CLASS(cs); 342 CPUARMState *env = cs->env_ptr; 343 uint32_t cur_el = arm_current_el(env); 344 bool secure = arm_is_secure(env); 345 uint32_t target_el; 346 uint32_t excp_idx; 347 bool ret = false; 348 349 if (interrupt_request & CPU_INTERRUPT_FIQ) { 350 excp_idx = EXCP_FIQ; 351 target_el = arm_phys_excp_target_el(cs, excp_idx, cur_el, secure); 352 if (arm_excp_unmasked(cs, excp_idx, target_el)) { 353 cs->exception_index = excp_idx; 354 env->exception.target_el = target_el; 355 cc->do_interrupt(cs); 356 ret = true; 357 } 358 } 359 if (interrupt_request & CPU_INTERRUPT_HARD) { 360 excp_idx = EXCP_IRQ; 361 target_el = arm_phys_excp_target_el(cs, excp_idx, cur_el, secure); 362 if (arm_excp_unmasked(cs, excp_idx, target_el)) { 363 cs->exception_index = excp_idx; 364 env->exception.target_el = target_el; 365 cc->do_interrupt(cs); 366 ret = true; 367 } 368 } 369 if (interrupt_request & CPU_INTERRUPT_VIRQ) { 370 excp_idx = EXCP_VIRQ; 371 target_el = 1; 372 if (arm_excp_unmasked(cs, excp_idx, target_el)) { 373 cs->exception_index = excp_idx; 374 env->exception.target_el = target_el; 375 cc->do_interrupt(cs); 376 ret = true; 377 } 378 } 379 if (interrupt_request & CPU_INTERRUPT_VFIQ) { 380 excp_idx = EXCP_VFIQ; 381 target_el = 1; 382 if (arm_excp_unmasked(cs, excp_idx, target_el)) { 383 cs->exception_index = excp_idx; 384 env->exception.target_el = target_el; 385 cc->do_interrupt(cs); 386 ret = true; 387 } 388 } 389 390 return ret; 391 } 392 393 #if !defined(CONFIG_USER_ONLY) || !defined(TARGET_AARCH64) 394 static bool arm_v7m_cpu_exec_interrupt(CPUState *cs, int interrupt_request) 395 { 396 CPUClass *cc = CPU_GET_CLASS(cs); 397 ARMCPU *cpu = ARM_CPU(cs); 398 CPUARMState *env = &cpu->env; 399 bool ret = false; 400 401 /* ARMv7-M interrupt masking works differently than -A or -R. 402 * There is no FIQ/IRQ distinction. Instead of I and F bits 403 * masking FIQ and IRQ interrupts, an exception is taken only 404 * if it is higher priority than the current execution priority 405 * (which depends on state like BASEPRI, FAULTMASK and the 406 * currently active exception). 407 */ 408 if (interrupt_request & CPU_INTERRUPT_HARD 409 && (armv7m_nvic_can_take_pending_exception(env->nvic))) { 410 cs->exception_index = EXCP_IRQ; 411 cc->do_interrupt(cs); 412 ret = true; 413 } 414 return ret; 415 } 416 #endif 417 418 #ifndef CONFIG_USER_ONLY 419 static void arm_cpu_set_irq(void *opaque, int irq, int level) 420 { 421 ARMCPU *cpu = opaque; 422 CPUARMState *env = &cpu->env; 423 CPUState *cs = CPU(cpu); 424 static const int mask[] = { 425 [ARM_CPU_IRQ] = CPU_INTERRUPT_HARD, 426 [ARM_CPU_FIQ] = CPU_INTERRUPT_FIQ, 427 [ARM_CPU_VIRQ] = CPU_INTERRUPT_VIRQ, 428 [ARM_CPU_VFIQ] = CPU_INTERRUPT_VFIQ 429 }; 430 431 switch (irq) { 432 case ARM_CPU_VIRQ: 433 case ARM_CPU_VFIQ: 434 assert(arm_feature(env, ARM_FEATURE_EL2)); 435 /* fall through */ 436 case ARM_CPU_IRQ: 437 case ARM_CPU_FIQ: 438 if (level) { 439 cpu_interrupt(cs, mask[irq]); 440 } else { 441 cpu_reset_interrupt(cs, mask[irq]); 442 } 443 break; 444 default: 445 g_assert_not_reached(); 446 } 447 } 448 449 static void arm_cpu_kvm_set_irq(void *opaque, int irq, int level) 450 { 451 #ifdef CONFIG_KVM 452 ARMCPU *cpu = opaque; 453 CPUState *cs = CPU(cpu); 454 int kvm_irq = KVM_ARM_IRQ_TYPE_CPU << KVM_ARM_IRQ_TYPE_SHIFT; 455 456 switch (irq) { 457 case ARM_CPU_IRQ: 458 kvm_irq |= KVM_ARM_IRQ_CPU_IRQ; 459 break; 460 case ARM_CPU_FIQ: 461 kvm_irq |= KVM_ARM_IRQ_CPU_FIQ; 462 break; 463 default: 464 g_assert_not_reached(); 465 } 466 kvm_irq |= cs->cpu_index << KVM_ARM_IRQ_VCPU_SHIFT; 467 kvm_set_irq(kvm_state, kvm_irq, level ? 1 : 0); 468 #endif 469 } 470 471 static bool arm_cpu_virtio_is_big_endian(CPUState *cs) 472 { 473 ARMCPU *cpu = ARM_CPU(cs); 474 CPUARMState *env = &cpu->env; 475 476 cpu_synchronize_state(cs); 477 return arm_cpu_data_is_big_endian(env); 478 } 479 480 #endif 481 482 static inline void set_feature(CPUARMState *env, int feature) 483 { 484 env->features |= 1ULL << feature; 485 } 486 487 static inline void unset_feature(CPUARMState *env, int feature) 488 { 489 env->features &= ~(1ULL << feature); 490 } 491 492 static int 493 print_insn_thumb1(bfd_vma pc, disassemble_info *info) 494 { 495 return print_insn_arm(pc | 1, info); 496 } 497 498 static void arm_disas_set_info(CPUState *cpu, disassemble_info *info) 499 { 500 ARMCPU *ac = ARM_CPU(cpu); 501 CPUARMState *env = &ac->env; 502 bool sctlr_b; 503 504 if (is_a64(env)) { 505 /* We might not be compiled with the A64 disassembler 506 * because it needs a C++ compiler. Leave print_insn 507 * unset in this case to use the caller default behaviour. 508 */ 509 #if defined(CONFIG_ARM_A64_DIS) 510 info->print_insn = print_insn_arm_a64; 511 #endif 512 info->cap_arch = CS_ARCH_ARM64; 513 info->cap_insn_unit = 4; 514 info->cap_insn_split = 4; 515 } else { 516 int cap_mode; 517 if (env->thumb) { 518 info->print_insn = print_insn_thumb1; 519 info->cap_insn_unit = 2; 520 info->cap_insn_split = 4; 521 cap_mode = CS_MODE_THUMB; 522 } else { 523 info->print_insn = print_insn_arm; 524 info->cap_insn_unit = 4; 525 info->cap_insn_split = 4; 526 cap_mode = CS_MODE_ARM; 527 } 528 if (arm_feature(env, ARM_FEATURE_V8)) { 529 cap_mode |= CS_MODE_V8; 530 } 531 if (arm_feature(env, ARM_FEATURE_M)) { 532 cap_mode |= CS_MODE_MCLASS; 533 } 534 info->cap_arch = CS_ARCH_ARM; 535 info->cap_mode = cap_mode; 536 } 537 538 sctlr_b = arm_sctlr_b(env); 539 if (bswap_code(sctlr_b)) { 540 #ifdef TARGET_WORDS_BIGENDIAN 541 info->endian = BFD_ENDIAN_LITTLE; 542 #else 543 info->endian = BFD_ENDIAN_BIG; 544 #endif 545 } 546 info->flags &= ~INSN_ARM_BE32; 547 #ifndef CONFIG_USER_ONLY 548 if (sctlr_b) { 549 info->flags |= INSN_ARM_BE32; 550 } 551 #endif 552 } 553 554 uint64_t arm_cpu_mp_affinity(int idx, uint8_t clustersz) 555 { 556 uint32_t Aff1 = idx / clustersz; 557 uint32_t Aff0 = idx % clustersz; 558 return (Aff1 << ARM_AFF1_SHIFT) | Aff0; 559 } 560 561 static void arm_cpu_initfn(Object *obj) 562 { 563 CPUState *cs = CPU(obj); 564 ARMCPU *cpu = ARM_CPU(obj); 565 566 cs->env_ptr = &cpu->env; 567 cpu->cp_regs = g_hash_table_new_full(g_int_hash, g_int_equal, 568 g_free, g_free); 569 570 QLIST_INIT(&cpu->pre_el_change_hooks); 571 QLIST_INIT(&cpu->el_change_hooks); 572 573 #ifndef CONFIG_USER_ONLY 574 /* Our inbound IRQ and FIQ lines */ 575 if (kvm_enabled()) { 576 /* VIRQ and VFIQ are unused with KVM but we add them to maintain 577 * the same interface as non-KVM CPUs. 578 */ 579 qdev_init_gpio_in(DEVICE(cpu), arm_cpu_kvm_set_irq, 4); 580 } else { 581 qdev_init_gpio_in(DEVICE(cpu), arm_cpu_set_irq, 4); 582 } 583 584 cpu->gt_timer[GTIMER_PHYS] = timer_new(QEMU_CLOCK_VIRTUAL, GTIMER_SCALE, 585 arm_gt_ptimer_cb, cpu); 586 cpu->gt_timer[GTIMER_VIRT] = timer_new(QEMU_CLOCK_VIRTUAL, GTIMER_SCALE, 587 arm_gt_vtimer_cb, cpu); 588 cpu->gt_timer[GTIMER_HYP] = timer_new(QEMU_CLOCK_VIRTUAL, GTIMER_SCALE, 589 arm_gt_htimer_cb, cpu); 590 cpu->gt_timer[GTIMER_SEC] = timer_new(QEMU_CLOCK_VIRTUAL, GTIMER_SCALE, 591 arm_gt_stimer_cb, cpu); 592 qdev_init_gpio_out(DEVICE(cpu), cpu->gt_timer_outputs, 593 ARRAY_SIZE(cpu->gt_timer_outputs)); 594 595 qdev_init_gpio_out_named(DEVICE(cpu), &cpu->gicv3_maintenance_interrupt, 596 "gicv3-maintenance-interrupt", 1); 597 qdev_init_gpio_out_named(DEVICE(cpu), &cpu->pmu_interrupt, 598 "pmu-interrupt", 1); 599 #endif 600 601 /* DTB consumers generally don't in fact care what the 'compatible' 602 * string is, so always provide some string and trust that a hypothetical 603 * picky DTB consumer will also provide a helpful error message. 604 */ 605 cpu->dtb_compatible = "qemu,unknown"; 606 cpu->psci_version = 1; /* By default assume PSCI v0.1 */ 607 cpu->kvm_target = QEMU_KVM_ARM_TARGET_NONE; 608 609 if (tcg_enabled()) { 610 cpu->psci_version = 2; /* TCG implements PSCI 0.2 */ 611 } 612 } 613 614 static Property arm_cpu_reset_cbar_property = 615 DEFINE_PROP_UINT64("reset-cbar", ARMCPU, reset_cbar, 0); 616 617 static Property arm_cpu_reset_hivecs_property = 618 DEFINE_PROP_BOOL("reset-hivecs", ARMCPU, reset_hivecs, false); 619 620 static Property arm_cpu_rvbar_property = 621 DEFINE_PROP_UINT64("rvbar", ARMCPU, rvbar, 0); 622 623 static Property arm_cpu_has_el2_property = 624 DEFINE_PROP_BOOL("has_el2", ARMCPU, has_el2, true); 625 626 static Property arm_cpu_has_el3_property = 627 DEFINE_PROP_BOOL("has_el3", ARMCPU, has_el3, true); 628 629 static Property arm_cpu_cfgend_property = 630 DEFINE_PROP_BOOL("cfgend", ARMCPU, cfgend, false); 631 632 /* use property name "pmu" to match other archs and virt tools */ 633 static Property arm_cpu_has_pmu_property = 634 DEFINE_PROP_BOOL("pmu", ARMCPU, has_pmu, true); 635 636 static Property arm_cpu_has_mpu_property = 637 DEFINE_PROP_BOOL("has-mpu", ARMCPU, has_mpu, true); 638 639 /* This is like DEFINE_PROP_UINT32 but it doesn't set the default value, 640 * because the CPU initfn will have already set cpu->pmsav7_dregion to 641 * the right value for that particular CPU type, and we don't want 642 * to override that with an incorrect constant value. 643 */ 644 static Property arm_cpu_pmsav7_dregion_property = 645 DEFINE_PROP_UNSIGNED_NODEFAULT("pmsav7-dregion", ARMCPU, 646 pmsav7_dregion, 647 qdev_prop_uint32, uint32_t); 648 649 /* M profile: initial value of the Secure VTOR */ 650 static Property arm_cpu_initsvtor_property = 651 DEFINE_PROP_UINT32("init-svtor", ARMCPU, init_svtor, 0); 652 653 static void arm_cpu_post_init(Object *obj) 654 { 655 ARMCPU *cpu = ARM_CPU(obj); 656 657 /* M profile implies PMSA. We have to do this here rather than 658 * in realize with the other feature-implication checks because 659 * we look at the PMSA bit to see if we should add some properties. 660 */ 661 if (arm_feature(&cpu->env, ARM_FEATURE_M)) { 662 set_feature(&cpu->env, ARM_FEATURE_PMSA); 663 } 664 665 if (arm_feature(&cpu->env, ARM_FEATURE_CBAR) || 666 arm_feature(&cpu->env, ARM_FEATURE_CBAR_RO)) { 667 qdev_property_add_static(DEVICE(obj), &arm_cpu_reset_cbar_property, 668 &error_abort); 669 } 670 671 if (!arm_feature(&cpu->env, ARM_FEATURE_M)) { 672 qdev_property_add_static(DEVICE(obj), &arm_cpu_reset_hivecs_property, 673 &error_abort); 674 } 675 676 if (arm_feature(&cpu->env, ARM_FEATURE_AARCH64)) { 677 qdev_property_add_static(DEVICE(obj), &arm_cpu_rvbar_property, 678 &error_abort); 679 } 680 681 if (arm_feature(&cpu->env, ARM_FEATURE_EL3)) { 682 /* Add the has_el3 state CPU property only if EL3 is allowed. This will 683 * prevent "has_el3" from existing on CPUs which cannot support EL3. 684 */ 685 qdev_property_add_static(DEVICE(obj), &arm_cpu_has_el3_property, 686 &error_abort); 687 688 #ifndef CONFIG_USER_ONLY 689 object_property_add_link(obj, "secure-memory", 690 TYPE_MEMORY_REGION, 691 (Object **)&cpu->secure_memory, 692 qdev_prop_allow_set_link_before_realize, 693 OBJ_PROP_LINK_STRONG, 694 &error_abort); 695 #endif 696 } 697 698 if (arm_feature(&cpu->env, ARM_FEATURE_EL2)) { 699 qdev_property_add_static(DEVICE(obj), &arm_cpu_has_el2_property, 700 &error_abort); 701 } 702 703 if (arm_feature(&cpu->env, ARM_FEATURE_PMU)) { 704 qdev_property_add_static(DEVICE(obj), &arm_cpu_has_pmu_property, 705 &error_abort); 706 } 707 708 if (arm_feature(&cpu->env, ARM_FEATURE_PMSA)) { 709 qdev_property_add_static(DEVICE(obj), &arm_cpu_has_mpu_property, 710 &error_abort); 711 if (arm_feature(&cpu->env, ARM_FEATURE_V7)) { 712 qdev_property_add_static(DEVICE(obj), 713 &arm_cpu_pmsav7_dregion_property, 714 &error_abort); 715 } 716 } 717 718 if (arm_feature(&cpu->env, ARM_FEATURE_M_SECURITY)) { 719 object_property_add_link(obj, "idau", TYPE_IDAU_INTERFACE, &cpu->idau, 720 qdev_prop_allow_set_link_before_realize, 721 OBJ_PROP_LINK_STRONG, 722 &error_abort); 723 qdev_property_add_static(DEVICE(obj), &arm_cpu_initsvtor_property, 724 &error_abort); 725 } 726 727 qdev_property_add_static(DEVICE(obj), &arm_cpu_cfgend_property, 728 &error_abort); 729 } 730 731 static void arm_cpu_finalizefn(Object *obj) 732 { 733 ARMCPU *cpu = ARM_CPU(obj); 734 ARMELChangeHook *hook, *next; 735 736 g_hash_table_destroy(cpu->cp_regs); 737 738 QLIST_FOREACH_SAFE(hook, &cpu->pre_el_change_hooks, node, next) { 739 QLIST_REMOVE(hook, node); 740 g_free(hook); 741 } 742 QLIST_FOREACH_SAFE(hook, &cpu->el_change_hooks, node, next) { 743 QLIST_REMOVE(hook, node); 744 g_free(hook); 745 } 746 } 747 748 static void arm_cpu_realizefn(DeviceState *dev, Error **errp) 749 { 750 CPUState *cs = CPU(dev); 751 ARMCPU *cpu = ARM_CPU(dev); 752 ARMCPUClass *acc = ARM_CPU_GET_CLASS(dev); 753 CPUARMState *env = &cpu->env; 754 int pagebits; 755 Error *local_err = NULL; 756 757 /* If we needed to query the host kernel for the CPU features 758 * then it's possible that might have failed in the initfn, but 759 * this is the first point where we can report it. 760 */ 761 if (cpu->host_cpu_probe_failed) { 762 if (!kvm_enabled()) { 763 error_setg(errp, "The 'host' CPU type can only be used with KVM"); 764 } else { 765 error_setg(errp, "Failed to retrieve host CPU features"); 766 } 767 return; 768 } 769 770 #ifndef CONFIG_USER_ONLY 771 /* The NVIC and M-profile CPU are two halves of a single piece of 772 * hardware; trying to use one without the other is a command line 773 * error and will result in segfaults if not caught here. 774 */ 775 if (arm_feature(env, ARM_FEATURE_M)) { 776 if (!env->nvic) { 777 error_setg(errp, "This board cannot be used with Cortex-M CPUs"); 778 return; 779 } 780 } else { 781 if (env->nvic) { 782 error_setg(errp, "This board can only be used with Cortex-M CPUs"); 783 return; 784 } 785 } 786 #endif 787 788 cpu_exec_realizefn(cs, &local_err); 789 if (local_err != NULL) { 790 error_propagate(errp, local_err); 791 return; 792 } 793 794 /* Some features automatically imply others: */ 795 if (arm_feature(env, ARM_FEATURE_V8)) { 796 set_feature(env, ARM_FEATURE_V7); 797 set_feature(env, ARM_FEATURE_ARM_DIV); 798 set_feature(env, ARM_FEATURE_LPAE); 799 } 800 if (arm_feature(env, ARM_FEATURE_V7)) { 801 set_feature(env, ARM_FEATURE_VAPA); 802 set_feature(env, ARM_FEATURE_THUMB2); 803 set_feature(env, ARM_FEATURE_MPIDR); 804 if (!arm_feature(env, ARM_FEATURE_M)) { 805 set_feature(env, ARM_FEATURE_V6K); 806 } else { 807 set_feature(env, ARM_FEATURE_V6); 808 } 809 810 /* Always define VBAR for V7 CPUs even if it doesn't exist in 811 * non-EL3 configs. This is needed by some legacy boards. 812 */ 813 set_feature(env, ARM_FEATURE_VBAR); 814 } 815 if (arm_feature(env, ARM_FEATURE_V6K)) { 816 set_feature(env, ARM_FEATURE_V6); 817 set_feature(env, ARM_FEATURE_MVFR); 818 } 819 if (arm_feature(env, ARM_FEATURE_V6)) { 820 set_feature(env, ARM_FEATURE_V5); 821 set_feature(env, ARM_FEATURE_JAZELLE); 822 if (!arm_feature(env, ARM_FEATURE_M)) { 823 set_feature(env, ARM_FEATURE_AUXCR); 824 } 825 } 826 if (arm_feature(env, ARM_FEATURE_V5)) { 827 set_feature(env, ARM_FEATURE_V4T); 828 } 829 if (arm_feature(env, ARM_FEATURE_M)) { 830 set_feature(env, ARM_FEATURE_THUMB_DIV); 831 } 832 if (arm_feature(env, ARM_FEATURE_ARM_DIV)) { 833 set_feature(env, ARM_FEATURE_THUMB_DIV); 834 } 835 if (arm_feature(env, ARM_FEATURE_VFP4)) { 836 set_feature(env, ARM_FEATURE_VFP3); 837 set_feature(env, ARM_FEATURE_VFP_FP16); 838 } 839 if (arm_feature(env, ARM_FEATURE_VFP3)) { 840 set_feature(env, ARM_FEATURE_VFP); 841 } 842 if (arm_feature(env, ARM_FEATURE_LPAE)) { 843 set_feature(env, ARM_FEATURE_V7MP); 844 set_feature(env, ARM_FEATURE_PXN); 845 } 846 if (arm_feature(env, ARM_FEATURE_CBAR_RO)) { 847 set_feature(env, ARM_FEATURE_CBAR); 848 } 849 if (arm_feature(env, ARM_FEATURE_THUMB2) && 850 !arm_feature(env, ARM_FEATURE_M)) { 851 set_feature(env, ARM_FEATURE_THUMB_DSP); 852 } 853 854 if (arm_feature(env, ARM_FEATURE_V7) && 855 !arm_feature(env, ARM_FEATURE_M) && 856 !arm_feature(env, ARM_FEATURE_PMSA)) { 857 /* v7VMSA drops support for the old ARMv5 tiny pages, so we 858 * can use 4K pages. 859 */ 860 pagebits = 12; 861 } else { 862 /* For CPUs which might have tiny 1K pages, or which have an 863 * MPU and might have small region sizes, stick with 1K pages. 864 */ 865 pagebits = 10; 866 } 867 if (!set_preferred_target_page_bits(pagebits)) { 868 /* This can only ever happen for hotplugging a CPU, or if 869 * the board code incorrectly creates a CPU which it has 870 * promised via minimum_page_size that it will not. 871 */ 872 error_setg(errp, "This CPU requires a smaller page size than the " 873 "system is using"); 874 return; 875 } 876 877 /* This cpu-id-to-MPIDR affinity is used only for TCG; KVM will override it. 878 * We don't support setting cluster ID ([16..23]) (known as Aff2 879 * in later ARM ARM versions), or any of the higher affinity level fields, 880 * so these bits always RAZ. 881 */ 882 if (cpu->mp_affinity == ARM64_AFFINITY_INVALID) { 883 cpu->mp_affinity = arm_cpu_mp_affinity(cs->cpu_index, 884 ARM_DEFAULT_CPUS_PER_CLUSTER); 885 } 886 887 if (cpu->reset_hivecs) { 888 cpu->reset_sctlr |= (1 << 13); 889 } 890 891 if (cpu->cfgend) { 892 if (arm_feature(&cpu->env, ARM_FEATURE_V7)) { 893 cpu->reset_sctlr |= SCTLR_EE; 894 } else { 895 cpu->reset_sctlr |= SCTLR_B; 896 } 897 } 898 899 if (!cpu->has_el3) { 900 /* If the has_el3 CPU property is disabled then we need to disable the 901 * feature. 902 */ 903 unset_feature(env, ARM_FEATURE_EL3); 904 905 /* Disable the security extension feature bits in the processor feature 906 * registers as well. These are id_pfr1[7:4] and id_aa64pfr0[15:12]. 907 */ 908 cpu->id_pfr1 &= ~0xf0; 909 cpu->id_aa64pfr0 &= ~0xf000; 910 } 911 912 if (!cpu->has_el2) { 913 unset_feature(env, ARM_FEATURE_EL2); 914 } 915 916 if (!cpu->has_pmu) { 917 unset_feature(env, ARM_FEATURE_PMU); 918 cpu->id_aa64dfr0 &= ~0xf00; 919 } 920 921 if (!arm_feature(env, ARM_FEATURE_EL2)) { 922 /* Disable the hypervisor feature bits in the processor feature 923 * registers if we don't have EL2. These are id_pfr1[15:12] and 924 * id_aa64pfr0_el1[11:8]. 925 */ 926 cpu->id_aa64pfr0 &= ~0xf00; 927 cpu->id_pfr1 &= ~0xf000; 928 } 929 930 /* MPU can be configured out of a PMSA CPU either by setting has-mpu 931 * to false or by setting pmsav7-dregion to 0. 932 */ 933 if (!cpu->has_mpu) { 934 cpu->pmsav7_dregion = 0; 935 } 936 if (cpu->pmsav7_dregion == 0) { 937 cpu->has_mpu = false; 938 } 939 940 if (arm_feature(env, ARM_FEATURE_PMSA) && 941 arm_feature(env, ARM_FEATURE_V7)) { 942 uint32_t nr = cpu->pmsav7_dregion; 943 944 if (nr > 0xff) { 945 error_setg(errp, "PMSAv7 MPU #regions invalid %" PRIu32, nr); 946 return; 947 } 948 949 if (nr) { 950 if (arm_feature(env, ARM_FEATURE_V8)) { 951 /* PMSAv8 */ 952 env->pmsav8.rbar[M_REG_NS] = g_new0(uint32_t, nr); 953 env->pmsav8.rlar[M_REG_NS] = g_new0(uint32_t, nr); 954 if (arm_feature(env, ARM_FEATURE_M_SECURITY)) { 955 env->pmsav8.rbar[M_REG_S] = g_new0(uint32_t, nr); 956 env->pmsav8.rlar[M_REG_S] = g_new0(uint32_t, nr); 957 } 958 } else { 959 env->pmsav7.drbar = g_new0(uint32_t, nr); 960 env->pmsav7.drsr = g_new0(uint32_t, nr); 961 env->pmsav7.dracr = g_new0(uint32_t, nr); 962 } 963 } 964 } 965 966 if (arm_feature(env, ARM_FEATURE_M_SECURITY)) { 967 uint32_t nr = cpu->sau_sregion; 968 969 if (nr > 0xff) { 970 error_setg(errp, "v8M SAU #regions invalid %" PRIu32, nr); 971 return; 972 } 973 974 if (nr) { 975 env->sau.rbar = g_new0(uint32_t, nr); 976 env->sau.rlar = g_new0(uint32_t, nr); 977 } 978 } 979 980 if (arm_feature(env, ARM_FEATURE_EL3)) { 981 set_feature(env, ARM_FEATURE_VBAR); 982 } 983 984 register_cp_regs_for_features(cpu); 985 arm_cpu_register_gdb_regs_for_features(cpu); 986 987 init_cpreg_list(cpu); 988 989 #ifndef CONFIG_USER_ONLY 990 if (cpu->has_el3 || arm_feature(env, ARM_FEATURE_M_SECURITY)) { 991 cs->num_ases = 2; 992 993 if (!cpu->secure_memory) { 994 cpu->secure_memory = cs->memory; 995 } 996 cpu_address_space_init(cs, ARMASIdx_S, "cpu-secure-memory", 997 cpu->secure_memory); 998 } else { 999 cs->num_ases = 1; 1000 } 1001 cpu_address_space_init(cs, ARMASIdx_NS, "cpu-memory", cs->memory); 1002 1003 /* No core_count specified, default to smp_cpus. */ 1004 if (cpu->core_count == -1) { 1005 cpu->core_count = smp_cpus; 1006 } 1007 #endif 1008 1009 qemu_init_vcpu(cs); 1010 cpu_reset(cs); 1011 1012 acc->parent_realize(dev, errp); 1013 } 1014 1015 static ObjectClass *arm_cpu_class_by_name(const char *cpu_model) 1016 { 1017 ObjectClass *oc; 1018 char *typename; 1019 char **cpuname; 1020 const char *cpunamestr; 1021 1022 cpuname = g_strsplit(cpu_model, ",", 1); 1023 cpunamestr = cpuname[0]; 1024 #ifdef CONFIG_USER_ONLY 1025 /* For backwards compatibility usermode emulation allows "-cpu any", 1026 * which has the same semantics as "-cpu max". 1027 */ 1028 if (!strcmp(cpunamestr, "any")) { 1029 cpunamestr = "max"; 1030 } 1031 #endif 1032 typename = g_strdup_printf(ARM_CPU_TYPE_NAME("%s"), cpunamestr); 1033 oc = object_class_by_name(typename); 1034 g_strfreev(cpuname); 1035 g_free(typename); 1036 if (!oc || !object_class_dynamic_cast(oc, TYPE_ARM_CPU) || 1037 object_class_is_abstract(oc)) { 1038 return NULL; 1039 } 1040 return oc; 1041 } 1042 1043 /* CPU models. These are not needed for the AArch64 linux-user build. */ 1044 #if !defined(CONFIG_USER_ONLY) || !defined(TARGET_AARCH64) 1045 1046 static void arm926_initfn(Object *obj) 1047 { 1048 ARMCPU *cpu = ARM_CPU(obj); 1049 1050 cpu->dtb_compatible = "arm,arm926"; 1051 set_feature(&cpu->env, ARM_FEATURE_V5); 1052 set_feature(&cpu->env, ARM_FEATURE_VFP); 1053 set_feature(&cpu->env, ARM_FEATURE_DUMMY_C15_REGS); 1054 set_feature(&cpu->env, ARM_FEATURE_CACHE_TEST_CLEAN); 1055 set_feature(&cpu->env, ARM_FEATURE_JAZELLE); 1056 cpu->midr = 0x41069265; 1057 cpu->reset_fpsid = 0x41011090; 1058 cpu->ctr = 0x1dd20d2; 1059 cpu->reset_sctlr = 0x00090078; 1060 } 1061 1062 static void arm946_initfn(Object *obj) 1063 { 1064 ARMCPU *cpu = ARM_CPU(obj); 1065 1066 cpu->dtb_compatible = "arm,arm946"; 1067 set_feature(&cpu->env, ARM_FEATURE_V5); 1068 set_feature(&cpu->env, ARM_FEATURE_PMSA); 1069 set_feature(&cpu->env, ARM_FEATURE_DUMMY_C15_REGS); 1070 cpu->midr = 0x41059461; 1071 cpu->ctr = 0x0f004006; 1072 cpu->reset_sctlr = 0x00000078; 1073 } 1074 1075 static void arm1026_initfn(Object *obj) 1076 { 1077 ARMCPU *cpu = ARM_CPU(obj); 1078 1079 cpu->dtb_compatible = "arm,arm1026"; 1080 set_feature(&cpu->env, ARM_FEATURE_V5); 1081 set_feature(&cpu->env, ARM_FEATURE_VFP); 1082 set_feature(&cpu->env, ARM_FEATURE_AUXCR); 1083 set_feature(&cpu->env, ARM_FEATURE_DUMMY_C15_REGS); 1084 set_feature(&cpu->env, ARM_FEATURE_CACHE_TEST_CLEAN); 1085 set_feature(&cpu->env, ARM_FEATURE_JAZELLE); 1086 cpu->midr = 0x4106a262; 1087 cpu->reset_fpsid = 0x410110a0; 1088 cpu->ctr = 0x1dd20d2; 1089 cpu->reset_sctlr = 0x00090078; 1090 cpu->reset_auxcr = 1; 1091 { 1092 /* The 1026 had an IFAR at c6,c0,0,1 rather than the ARMv6 c6,c0,0,2 */ 1093 ARMCPRegInfo ifar = { 1094 .name = "IFAR", .cp = 15, .crn = 6, .crm = 0, .opc1 = 0, .opc2 = 1, 1095 .access = PL1_RW, 1096 .fieldoffset = offsetof(CPUARMState, cp15.ifar_ns), 1097 .resetvalue = 0 1098 }; 1099 define_one_arm_cp_reg(cpu, &ifar); 1100 } 1101 } 1102 1103 static void arm1136_r2_initfn(Object *obj) 1104 { 1105 ARMCPU *cpu = ARM_CPU(obj); 1106 /* What qemu calls "arm1136_r2" is actually the 1136 r0p2, ie an 1107 * older core than plain "arm1136". In particular this does not 1108 * have the v6K features. 1109 * These ID register values are correct for 1136 but may be wrong 1110 * for 1136_r2 (in particular r0p2 does not actually implement most 1111 * of the ID registers). 1112 */ 1113 1114 cpu->dtb_compatible = "arm,arm1136"; 1115 set_feature(&cpu->env, ARM_FEATURE_V6); 1116 set_feature(&cpu->env, ARM_FEATURE_VFP); 1117 set_feature(&cpu->env, ARM_FEATURE_DUMMY_C15_REGS); 1118 set_feature(&cpu->env, ARM_FEATURE_CACHE_DIRTY_REG); 1119 set_feature(&cpu->env, ARM_FEATURE_CACHE_BLOCK_OPS); 1120 cpu->midr = 0x4107b362; 1121 cpu->reset_fpsid = 0x410120b4; 1122 cpu->mvfr0 = 0x11111111; 1123 cpu->mvfr1 = 0x00000000; 1124 cpu->ctr = 0x1dd20d2; 1125 cpu->reset_sctlr = 0x00050078; 1126 cpu->id_pfr0 = 0x111; 1127 cpu->id_pfr1 = 0x1; 1128 cpu->id_dfr0 = 0x2; 1129 cpu->id_afr0 = 0x3; 1130 cpu->id_mmfr0 = 0x01130003; 1131 cpu->id_mmfr1 = 0x10030302; 1132 cpu->id_mmfr2 = 0x01222110; 1133 cpu->id_isar0 = 0x00140011; 1134 cpu->id_isar1 = 0x12002111; 1135 cpu->id_isar2 = 0x11231111; 1136 cpu->id_isar3 = 0x01102131; 1137 cpu->id_isar4 = 0x141; 1138 cpu->reset_auxcr = 7; 1139 } 1140 1141 static void arm1136_initfn(Object *obj) 1142 { 1143 ARMCPU *cpu = ARM_CPU(obj); 1144 1145 cpu->dtb_compatible = "arm,arm1136"; 1146 set_feature(&cpu->env, ARM_FEATURE_V6K); 1147 set_feature(&cpu->env, ARM_FEATURE_V6); 1148 set_feature(&cpu->env, ARM_FEATURE_VFP); 1149 set_feature(&cpu->env, ARM_FEATURE_DUMMY_C15_REGS); 1150 set_feature(&cpu->env, ARM_FEATURE_CACHE_DIRTY_REG); 1151 set_feature(&cpu->env, ARM_FEATURE_CACHE_BLOCK_OPS); 1152 cpu->midr = 0x4117b363; 1153 cpu->reset_fpsid = 0x410120b4; 1154 cpu->mvfr0 = 0x11111111; 1155 cpu->mvfr1 = 0x00000000; 1156 cpu->ctr = 0x1dd20d2; 1157 cpu->reset_sctlr = 0x00050078; 1158 cpu->id_pfr0 = 0x111; 1159 cpu->id_pfr1 = 0x1; 1160 cpu->id_dfr0 = 0x2; 1161 cpu->id_afr0 = 0x3; 1162 cpu->id_mmfr0 = 0x01130003; 1163 cpu->id_mmfr1 = 0x10030302; 1164 cpu->id_mmfr2 = 0x01222110; 1165 cpu->id_isar0 = 0x00140011; 1166 cpu->id_isar1 = 0x12002111; 1167 cpu->id_isar2 = 0x11231111; 1168 cpu->id_isar3 = 0x01102131; 1169 cpu->id_isar4 = 0x141; 1170 cpu->reset_auxcr = 7; 1171 } 1172 1173 static void arm1176_initfn(Object *obj) 1174 { 1175 ARMCPU *cpu = ARM_CPU(obj); 1176 1177 cpu->dtb_compatible = "arm,arm1176"; 1178 set_feature(&cpu->env, ARM_FEATURE_V6K); 1179 set_feature(&cpu->env, ARM_FEATURE_VFP); 1180 set_feature(&cpu->env, ARM_FEATURE_VAPA); 1181 set_feature(&cpu->env, ARM_FEATURE_DUMMY_C15_REGS); 1182 set_feature(&cpu->env, ARM_FEATURE_CACHE_DIRTY_REG); 1183 set_feature(&cpu->env, ARM_FEATURE_CACHE_BLOCK_OPS); 1184 set_feature(&cpu->env, ARM_FEATURE_EL3); 1185 cpu->midr = 0x410fb767; 1186 cpu->reset_fpsid = 0x410120b5; 1187 cpu->mvfr0 = 0x11111111; 1188 cpu->mvfr1 = 0x00000000; 1189 cpu->ctr = 0x1dd20d2; 1190 cpu->reset_sctlr = 0x00050078; 1191 cpu->id_pfr0 = 0x111; 1192 cpu->id_pfr1 = 0x11; 1193 cpu->id_dfr0 = 0x33; 1194 cpu->id_afr0 = 0; 1195 cpu->id_mmfr0 = 0x01130003; 1196 cpu->id_mmfr1 = 0x10030302; 1197 cpu->id_mmfr2 = 0x01222100; 1198 cpu->id_isar0 = 0x0140011; 1199 cpu->id_isar1 = 0x12002111; 1200 cpu->id_isar2 = 0x11231121; 1201 cpu->id_isar3 = 0x01102131; 1202 cpu->id_isar4 = 0x01141; 1203 cpu->reset_auxcr = 7; 1204 } 1205 1206 static void arm11mpcore_initfn(Object *obj) 1207 { 1208 ARMCPU *cpu = ARM_CPU(obj); 1209 1210 cpu->dtb_compatible = "arm,arm11mpcore"; 1211 set_feature(&cpu->env, ARM_FEATURE_V6K); 1212 set_feature(&cpu->env, ARM_FEATURE_VFP); 1213 set_feature(&cpu->env, ARM_FEATURE_VAPA); 1214 set_feature(&cpu->env, ARM_FEATURE_MPIDR); 1215 set_feature(&cpu->env, ARM_FEATURE_DUMMY_C15_REGS); 1216 cpu->midr = 0x410fb022; 1217 cpu->reset_fpsid = 0x410120b4; 1218 cpu->mvfr0 = 0x11111111; 1219 cpu->mvfr1 = 0x00000000; 1220 cpu->ctr = 0x1d192992; /* 32K icache 32K dcache */ 1221 cpu->id_pfr0 = 0x111; 1222 cpu->id_pfr1 = 0x1; 1223 cpu->id_dfr0 = 0; 1224 cpu->id_afr0 = 0x2; 1225 cpu->id_mmfr0 = 0x01100103; 1226 cpu->id_mmfr1 = 0x10020302; 1227 cpu->id_mmfr2 = 0x01222000; 1228 cpu->id_isar0 = 0x00100011; 1229 cpu->id_isar1 = 0x12002111; 1230 cpu->id_isar2 = 0x11221011; 1231 cpu->id_isar3 = 0x01102131; 1232 cpu->id_isar4 = 0x141; 1233 cpu->reset_auxcr = 1; 1234 } 1235 1236 static void cortex_m3_initfn(Object *obj) 1237 { 1238 ARMCPU *cpu = ARM_CPU(obj); 1239 set_feature(&cpu->env, ARM_FEATURE_V7); 1240 set_feature(&cpu->env, ARM_FEATURE_M); 1241 set_feature(&cpu->env, ARM_FEATURE_M_MAIN); 1242 cpu->midr = 0x410fc231; 1243 cpu->pmsav7_dregion = 8; 1244 cpu->id_pfr0 = 0x00000030; 1245 cpu->id_pfr1 = 0x00000200; 1246 cpu->id_dfr0 = 0x00100000; 1247 cpu->id_afr0 = 0x00000000; 1248 cpu->id_mmfr0 = 0x00000030; 1249 cpu->id_mmfr1 = 0x00000000; 1250 cpu->id_mmfr2 = 0x00000000; 1251 cpu->id_mmfr3 = 0x00000000; 1252 cpu->id_isar0 = 0x01141110; 1253 cpu->id_isar1 = 0x02111000; 1254 cpu->id_isar2 = 0x21112231; 1255 cpu->id_isar3 = 0x01111110; 1256 cpu->id_isar4 = 0x01310102; 1257 cpu->id_isar5 = 0x00000000; 1258 } 1259 1260 static void cortex_m4_initfn(Object *obj) 1261 { 1262 ARMCPU *cpu = ARM_CPU(obj); 1263 1264 set_feature(&cpu->env, ARM_FEATURE_V7); 1265 set_feature(&cpu->env, ARM_FEATURE_M); 1266 set_feature(&cpu->env, ARM_FEATURE_M_MAIN); 1267 set_feature(&cpu->env, ARM_FEATURE_THUMB_DSP); 1268 cpu->midr = 0x410fc240; /* r0p0 */ 1269 cpu->pmsav7_dregion = 8; 1270 cpu->id_pfr0 = 0x00000030; 1271 cpu->id_pfr1 = 0x00000200; 1272 cpu->id_dfr0 = 0x00100000; 1273 cpu->id_afr0 = 0x00000000; 1274 cpu->id_mmfr0 = 0x00000030; 1275 cpu->id_mmfr1 = 0x00000000; 1276 cpu->id_mmfr2 = 0x00000000; 1277 cpu->id_mmfr3 = 0x00000000; 1278 cpu->id_isar0 = 0x01141110; 1279 cpu->id_isar1 = 0x02111000; 1280 cpu->id_isar2 = 0x21112231; 1281 cpu->id_isar3 = 0x01111110; 1282 cpu->id_isar4 = 0x01310102; 1283 cpu->id_isar5 = 0x00000000; 1284 } 1285 1286 static void cortex_m33_initfn(Object *obj) 1287 { 1288 ARMCPU *cpu = ARM_CPU(obj); 1289 1290 set_feature(&cpu->env, ARM_FEATURE_V8); 1291 set_feature(&cpu->env, ARM_FEATURE_M); 1292 set_feature(&cpu->env, ARM_FEATURE_M_MAIN); 1293 set_feature(&cpu->env, ARM_FEATURE_M_SECURITY); 1294 set_feature(&cpu->env, ARM_FEATURE_THUMB_DSP); 1295 cpu->midr = 0x410fd213; /* r0p3 */ 1296 cpu->pmsav7_dregion = 16; 1297 cpu->sau_sregion = 8; 1298 cpu->id_pfr0 = 0x00000030; 1299 cpu->id_pfr1 = 0x00000210; 1300 cpu->id_dfr0 = 0x00200000; 1301 cpu->id_afr0 = 0x00000000; 1302 cpu->id_mmfr0 = 0x00101F40; 1303 cpu->id_mmfr1 = 0x00000000; 1304 cpu->id_mmfr2 = 0x01000000; 1305 cpu->id_mmfr3 = 0x00000000; 1306 cpu->id_isar0 = 0x01101110; 1307 cpu->id_isar1 = 0x02212000; 1308 cpu->id_isar2 = 0x20232232; 1309 cpu->id_isar3 = 0x01111131; 1310 cpu->id_isar4 = 0x01310132; 1311 cpu->id_isar5 = 0x00000000; 1312 cpu->clidr = 0x00000000; 1313 cpu->ctr = 0x8000c000; 1314 } 1315 1316 static void arm_v7m_class_init(ObjectClass *oc, void *data) 1317 { 1318 CPUClass *cc = CPU_CLASS(oc); 1319 1320 #ifndef CONFIG_USER_ONLY 1321 cc->do_interrupt = arm_v7m_cpu_do_interrupt; 1322 #endif 1323 1324 cc->cpu_exec_interrupt = arm_v7m_cpu_exec_interrupt; 1325 } 1326 1327 static const ARMCPRegInfo cortexr5_cp_reginfo[] = { 1328 /* Dummy the TCM region regs for the moment */ 1329 { .name = "ATCM", .cp = 15, .opc1 = 0, .crn = 9, .crm = 1, .opc2 = 0, 1330 .access = PL1_RW, .type = ARM_CP_CONST }, 1331 { .name = "BTCM", .cp = 15, .opc1 = 0, .crn = 9, .crm = 1, .opc2 = 1, 1332 .access = PL1_RW, .type = ARM_CP_CONST }, 1333 { .name = "DCACHE_INVAL", .cp = 15, .opc1 = 0, .crn = 15, .crm = 5, 1334 .opc2 = 0, .access = PL1_W, .type = ARM_CP_NOP }, 1335 REGINFO_SENTINEL 1336 }; 1337 1338 static void cortex_r5_initfn(Object *obj) 1339 { 1340 ARMCPU *cpu = ARM_CPU(obj); 1341 1342 set_feature(&cpu->env, ARM_FEATURE_V7); 1343 set_feature(&cpu->env, ARM_FEATURE_THUMB_DIV); 1344 set_feature(&cpu->env, ARM_FEATURE_ARM_DIV); 1345 set_feature(&cpu->env, ARM_FEATURE_V7MP); 1346 set_feature(&cpu->env, ARM_FEATURE_PMSA); 1347 cpu->midr = 0x411fc153; /* r1p3 */ 1348 cpu->id_pfr0 = 0x0131; 1349 cpu->id_pfr1 = 0x001; 1350 cpu->id_dfr0 = 0x010400; 1351 cpu->id_afr0 = 0x0; 1352 cpu->id_mmfr0 = 0x0210030; 1353 cpu->id_mmfr1 = 0x00000000; 1354 cpu->id_mmfr2 = 0x01200000; 1355 cpu->id_mmfr3 = 0x0211; 1356 cpu->id_isar0 = 0x2101111; 1357 cpu->id_isar1 = 0x13112111; 1358 cpu->id_isar2 = 0x21232141; 1359 cpu->id_isar3 = 0x01112131; 1360 cpu->id_isar4 = 0x0010142; 1361 cpu->id_isar5 = 0x0; 1362 cpu->mp_is_up = true; 1363 cpu->pmsav7_dregion = 16; 1364 define_arm_cp_regs(cpu, cortexr5_cp_reginfo); 1365 } 1366 1367 static void cortex_r5f_initfn(Object *obj) 1368 { 1369 ARMCPU *cpu = ARM_CPU(obj); 1370 1371 cortex_r5_initfn(obj); 1372 set_feature(&cpu->env, ARM_FEATURE_VFP3); 1373 } 1374 1375 static const ARMCPRegInfo cortexa8_cp_reginfo[] = { 1376 { .name = "L2LOCKDOWN", .cp = 15, .crn = 9, .crm = 0, .opc1 = 1, .opc2 = 0, 1377 .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0 }, 1378 { .name = "L2AUXCR", .cp = 15, .crn = 9, .crm = 0, .opc1 = 1, .opc2 = 2, 1379 .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0 }, 1380 REGINFO_SENTINEL 1381 }; 1382 1383 static void cortex_a8_initfn(Object *obj) 1384 { 1385 ARMCPU *cpu = ARM_CPU(obj); 1386 1387 cpu->dtb_compatible = "arm,cortex-a8"; 1388 set_feature(&cpu->env, ARM_FEATURE_V7); 1389 set_feature(&cpu->env, ARM_FEATURE_VFP3); 1390 set_feature(&cpu->env, ARM_FEATURE_NEON); 1391 set_feature(&cpu->env, ARM_FEATURE_THUMB2EE); 1392 set_feature(&cpu->env, ARM_FEATURE_DUMMY_C15_REGS); 1393 set_feature(&cpu->env, ARM_FEATURE_EL3); 1394 cpu->midr = 0x410fc080; 1395 cpu->reset_fpsid = 0x410330c0; 1396 cpu->mvfr0 = 0x11110222; 1397 cpu->mvfr1 = 0x00011111; 1398 cpu->ctr = 0x82048004; 1399 cpu->reset_sctlr = 0x00c50078; 1400 cpu->id_pfr0 = 0x1031; 1401 cpu->id_pfr1 = 0x11; 1402 cpu->id_dfr0 = 0x400; 1403 cpu->id_afr0 = 0; 1404 cpu->id_mmfr0 = 0x31100003; 1405 cpu->id_mmfr1 = 0x20000000; 1406 cpu->id_mmfr2 = 0x01202000; 1407 cpu->id_mmfr3 = 0x11; 1408 cpu->id_isar0 = 0x00101111; 1409 cpu->id_isar1 = 0x12112111; 1410 cpu->id_isar2 = 0x21232031; 1411 cpu->id_isar3 = 0x11112131; 1412 cpu->id_isar4 = 0x00111142; 1413 cpu->dbgdidr = 0x15141000; 1414 cpu->clidr = (1 << 27) | (2 << 24) | 3; 1415 cpu->ccsidr[0] = 0xe007e01a; /* 16k L1 dcache. */ 1416 cpu->ccsidr[1] = 0x2007e01a; /* 16k L1 icache. */ 1417 cpu->ccsidr[2] = 0xf0000000; /* No L2 icache. */ 1418 cpu->reset_auxcr = 2; 1419 define_arm_cp_regs(cpu, cortexa8_cp_reginfo); 1420 } 1421 1422 static const ARMCPRegInfo cortexa9_cp_reginfo[] = { 1423 /* power_control should be set to maximum latency. Again, 1424 * default to 0 and set by private hook 1425 */ 1426 { .name = "A9_PWRCTL", .cp = 15, .crn = 15, .crm = 0, .opc1 = 0, .opc2 = 0, 1427 .access = PL1_RW, .resetvalue = 0, 1428 .fieldoffset = offsetof(CPUARMState, cp15.c15_power_control) }, 1429 { .name = "A9_DIAG", .cp = 15, .crn = 15, .crm = 0, .opc1 = 0, .opc2 = 1, 1430 .access = PL1_RW, .resetvalue = 0, 1431 .fieldoffset = offsetof(CPUARMState, cp15.c15_diagnostic) }, 1432 { .name = "A9_PWRDIAG", .cp = 15, .crn = 15, .crm = 0, .opc1 = 0, .opc2 = 2, 1433 .access = PL1_RW, .resetvalue = 0, 1434 .fieldoffset = offsetof(CPUARMState, cp15.c15_power_diagnostic) }, 1435 { .name = "NEONBUSY", .cp = 15, .crn = 15, .crm = 1, .opc1 = 0, .opc2 = 0, 1436 .access = PL1_RW, .resetvalue = 0, .type = ARM_CP_CONST }, 1437 /* TLB lockdown control */ 1438 { .name = "TLB_LOCKR", .cp = 15, .crn = 15, .crm = 4, .opc1 = 5, .opc2 = 2, 1439 .access = PL1_W, .resetvalue = 0, .type = ARM_CP_NOP }, 1440 { .name = "TLB_LOCKW", .cp = 15, .crn = 15, .crm = 4, .opc1 = 5, .opc2 = 4, 1441 .access = PL1_W, .resetvalue = 0, .type = ARM_CP_NOP }, 1442 { .name = "TLB_VA", .cp = 15, .crn = 15, .crm = 5, .opc1 = 5, .opc2 = 2, 1443 .access = PL1_RW, .resetvalue = 0, .type = ARM_CP_CONST }, 1444 { .name = "TLB_PA", .cp = 15, .crn = 15, .crm = 6, .opc1 = 5, .opc2 = 2, 1445 .access = PL1_RW, .resetvalue = 0, .type = ARM_CP_CONST }, 1446 { .name = "TLB_ATTR", .cp = 15, .crn = 15, .crm = 7, .opc1 = 5, .opc2 = 2, 1447 .access = PL1_RW, .resetvalue = 0, .type = ARM_CP_CONST }, 1448 REGINFO_SENTINEL 1449 }; 1450 1451 static void cortex_a9_initfn(Object *obj) 1452 { 1453 ARMCPU *cpu = ARM_CPU(obj); 1454 1455 cpu->dtb_compatible = "arm,cortex-a9"; 1456 set_feature(&cpu->env, ARM_FEATURE_V7); 1457 set_feature(&cpu->env, ARM_FEATURE_VFP3); 1458 set_feature(&cpu->env, ARM_FEATURE_VFP_FP16); 1459 set_feature(&cpu->env, ARM_FEATURE_NEON); 1460 set_feature(&cpu->env, ARM_FEATURE_THUMB2EE); 1461 set_feature(&cpu->env, ARM_FEATURE_EL3); 1462 /* Note that A9 supports the MP extensions even for 1463 * A9UP and single-core A9MP (which are both different 1464 * and valid configurations; we don't model A9UP). 1465 */ 1466 set_feature(&cpu->env, ARM_FEATURE_V7MP); 1467 set_feature(&cpu->env, ARM_FEATURE_CBAR); 1468 cpu->midr = 0x410fc090; 1469 cpu->reset_fpsid = 0x41033090; 1470 cpu->mvfr0 = 0x11110222; 1471 cpu->mvfr1 = 0x01111111; 1472 cpu->ctr = 0x80038003; 1473 cpu->reset_sctlr = 0x00c50078; 1474 cpu->id_pfr0 = 0x1031; 1475 cpu->id_pfr1 = 0x11; 1476 cpu->id_dfr0 = 0x000; 1477 cpu->id_afr0 = 0; 1478 cpu->id_mmfr0 = 0x00100103; 1479 cpu->id_mmfr1 = 0x20000000; 1480 cpu->id_mmfr2 = 0x01230000; 1481 cpu->id_mmfr3 = 0x00002111; 1482 cpu->id_isar0 = 0x00101111; 1483 cpu->id_isar1 = 0x13112111; 1484 cpu->id_isar2 = 0x21232041; 1485 cpu->id_isar3 = 0x11112131; 1486 cpu->id_isar4 = 0x00111142; 1487 cpu->dbgdidr = 0x35141000; 1488 cpu->clidr = (1 << 27) | (1 << 24) | 3; 1489 cpu->ccsidr[0] = 0xe00fe019; /* 16k L1 dcache. */ 1490 cpu->ccsidr[1] = 0x200fe019; /* 16k L1 icache. */ 1491 define_arm_cp_regs(cpu, cortexa9_cp_reginfo); 1492 } 1493 1494 #ifndef CONFIG_USER_ONLY 1495 static uint64_t a15_l2ctlr_read(CPUARMState *env, const ARMCPRegInfo *ri) 1496 { 1497 /* Linux wants the number of processors from here. 1498 * Might as well set the interrupt-controller bit too. 1499 */ 1500 return ((smp_cpus - 1) << 24) | (1 << 23); 1501 } 1502 #endif 1503 1504 static const ARMCPRegInfo cortexa15_cp_reginfo[] = { 1505 #ifndef CONFIG_USER_ONLY 1506 { .name = "L2CTLR", .cp = 15, .crn = 9, .crm = 0, .opc1 = 1, .opc2 = 2, 1507 .access = PL1_RW, .resetvalue = 0, .readfn = a15_l2ctlr_read, 1508 .writefn = arm_cp_write_ignore, }, 1509 #endif 1510 { .name = "L2ECTLR", .cp = 15, .crn = 9, .crm = 0, .opc1 = 1, .opc2 = 3, 1511 .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0 }, 1512 REGINFO_SENTINEL 1513 }; 1514 1515 static void cortex_a7_initfn(Object *obj) 1516 { 1517 ARMCPU *cpu = ARM_CPU(obj); 1518 1519 cpu->dtb_compatible = "arm,cortex-a7"; 1520 set_feature(&cpu->env, ARM_FEATURE_V7); 1521 set_feature(&cpu->env, ARM_FEATURE_VFP4); 1522 set_feature(&cpu->env, ARM_FEATURE_NEON); 1523 set_feature(&cpu->env, ARM_FEATURE_THUMB2EE); 1524 set_feature(&cpu->env, ARM_FEATURE_ARM_DIV); 1525 set_feature(&cpu->env, ARM_FEATURE_GENERIC_TIMER); 1526 set_feature(&cpu->env, ARM_FEATURE_DUMMY_C15_REGS); 1527 set_feature(&cpu->env, ARM_FEATURE_CBAR_RO); 1528 set_feature(&cpu->env, ARM_FEATURE_LPAE); 1529 set_feature(&cpu->env, ARM_FEATURE_EL3); 1530 cpu->kvm_target = QEMU_KVM_ARM_TARGET_CORTEX_A7; 1531 cpu->midr = 0x410fc075; 1532 cpu->reset_fpsid = 0x41023075; 1533 cpu->mvfr0 = 0x10110222; 1534 cpu->mvfr1 = 0x11111111; 1535 cpu->ctr = 0x84448003; 1536 cpu->reset_sctlr = 0x00c50078; 1537 cpu->id_pfr0 = 0x00001131; 1538 cpu->id_pfr1 = 0x00011011; 1539 cpu->id_dfr0 = 0x02010555; 1540 cpu->pmceid0 = 0x00000000; 1541 cpu->pmceid1 = 0x00000000; 1542 cpu->id_afr0 = 0x00000000; 1543 cpu->id_mmfr0 = 0x10101105; 1544 cpu->id_mmfr1 = 0x40000000; 1545 cpu->id_mmfr2 = 0x01240000; 1546 cpu->id_mmfr3 = 0x02102211; 1547 cpu->id_isar0 = 0x01101110; 1548 cpu->id_isar1 = 0x13112111; 1549 cpu->id_isar2 = 0x21232041; 1550 cpu->id_isar3 = 0x11112131; 1551 cpu->id_isar4 = 0x10011142; 1552 cpu->dbgdidr = 0x3515f005; 1553 cpu->clidr = 0x0a200023; 1554 cpu->ccsidr[0] = 0x701fe00a; /* 32K L1 dcache */ 1555 cpu->ccsidr[1] = 0x201fe00a; /* 32K L1 icache */ 1556 cpu->ccsidr[2] = 0x711fe07a; /* 4096K L2 unified cache */ 1557 define_arm_cp_regs(cpu, cortexa15_cp_reginfo); /* Same as A15 */ 1558 } 1559 1560 static void cortex_a15_initfn(Object *obj) 1561 { 1562 ARMCPU *cpu = ARM_CPU(obj); 1563 1564 cpu->dtb_compatible = "arm,cortex-a15"; 1565 set_feature(&cpu->env, ARM_FEATURE_V7); 1566 set_feature(&cpu->env, ARM_FEATURE_VFP4); 1567 set_feature(&cpu->env, ARM_FEATURE_NEON); 1568 set_feature(&cpu->env, ARM_FEATURE_THUMB2EE); 1569 set_feature(&cpu->env, ARM_FEATURE_ARM_DIV); 1570 set_feature(&cpu->env, ARM_FEATURE_GENERIC_TIMER); 1571 set_feature(&cpu->env, ARM_FEATURE_DUMMY_C15_REGS); 1572 set_feature(&cpu->env, ARM_FEATURE_CBAR_RO); 1573 set_feature(&cpu->env, ARM_FEATURE_LPAE); 1574 set_feature(&cpu->env, ARM_FEATURE_EL3); 1575 cpu->kvm_target = QEMU_KVM_ARM_TARGET_CORTEX_A15; 1576 cpu->midr = 0x412fc0f1; 1577 cpu->reset_fpsid = 0x410430f0; 1578 cpu->mvfr0 = 0x10110222; 1579 cpu->mvfr1 = 0x11111111; 1580 cpu->ctr = 0x8444c004; 1581 cpu->reset_sctlr = 0x00c50078; 1582 cpu->id_pfr0 = 0x00001131; 1583 cpu->id_pfr1 = 0x00011011; 1584 cpu->id_dfr0 = 0x02010555; 1585 cpu->pmceid0 = 0x0000000; 1586 cpu->pmceid1 = 0x00000000; 1587 cpu->id_afr0 = 0x00000000; 1588 cpu->id_mmfr0 = 0x10201105; 1589 cpu->id_mmfr1 = 0x20000000; 1590 cpu->id_mmfr2 = 0x01240000; 1591 cpu->id_mmfr3 = 0x02102211; 1592 cpu->id_isar0 = 0x02101110; 1593 cpu->id_isar1 = 0x13112111; 1594 cpu->id_isar2 = 0x21232041; 1595 cpu->id_isar3 = 0x11112131; 1596 cpu->id_isar4 = 0x10011142; 1597 cpu->dbgdidr = 0x3515f021; 1598 cpu->clidr = 0x0a200023; 1599 cpu->ccsidr[0] = 0x701fe00a; /* 32K L1 dcache */ 1600 cpu->ccsidr[1] = 0x201fe00a; /* 32K L1 icache */ 1601 cpu->ccsidr[2] = 0x711fe07a; /* 4096K L2 unified cache */ 1602 define_arm_cp_regs(cpu, cortexa15_cp_reginfo); 1603 } 1604 1605 static void ti925t_initfn(Object *obj) 1606 { 1607 ARMCPU *cpu = ARM_CPU(obj); 1608 set_feature(&cpu->env, ARM_FEATURE_V4T); 1609 set_feature(&cpu->env, ARM_FEATURE_OMAPCP); 1610 cpu->midr = ARM_CPUID_TI925T; 1611 cpu->ctr = 0x5109149; 1612 cpu->reset_sctlr = 0x00000070; 1613 } 1614 1615 static void sa1100_initfn(Object *obj) 1616 { 1617 ARMCPU *cpu = ARM_CPU(obj); 1618 1619 cpu->dtb_compatible = "intel,sa1100"; 1620 set_feature(&cpu->env, ARM_FEATURE_STRONGARM); 1621 set_feature(&cpu->env, ARM_FEATURE_DUMMY_C15_REGS); 1622 cpu->midr = 0x4401A11B; 1623 cpu->reset_sctlr = 0x00000070; 1624 } 1625 1626 static void sa1110_initfn(Object *obj) 1627 { 1628 ARMCPU *cpu = ARM_CPU(obj); 1629 set_feature(&cpu->env, ARM_FEATURE_STRONGARM); 1630 set_feature(&cpu->env, ARM_FEATURE_DUMMY_C15_REGS); 1631 cpu->midr = 0x6901B119; 1632 cpu->reset_sctlr = 0x00000070; 1633 } 1634 1635 static void pxa250_initfn(Object *obj) 1636 { 1637 ARMCPU *cpu = ARM_CPU(obj); 1638 1639 cpu->dtb_compatible = "marvell,xscale"; 1640 set_feature(&cpu->env, ARM_FEATURE_V5); 1641 set_feature(&cpu->env, ARM_FEATURE_XSCALE); 1642 cpu->midr = 0x69052100; 1643 cpu->ctr = 0xd172172; 1644 cpu->reset_sctlr = 0x00000078; 1645 } 1646 1647 static void pxa255_initfn(Object *obj) 1648 { 1649 ARMCPU *cpu = ARM_CPU(obj); 1650 1651 cpu->dtb_compatible = "marvell,xscale"; 1652 set_feature(&cpu->env, ARM_FEATURE_V5); 1653 set_feature(&cpu->env, ARM_FEATURE_XSCALE); 1654 cpu->midr = 0x69052d00; 1655 cpu->ctr = 0xd172172; 1656 cpu->reset_sctlr = 0x00000078; 1657 } 1658 1659 static void pxa260_initfn(Object *obj) 1660 { 1661 ARMCPU *cpu = ARM_CPU(obj); 1662 1663 cpu->dtb_compatible = "marvell,xscale"; 1664 set_feature(&cpu->env, ARM_FEATURE_V5); 1665 set_feature(&cpu->env, ARM_FEATURE_XSCALE); 1666 cpu->midr = 0x69052903; 1667 cpu->ctr = 0xd172172; 1668 cpu->reset_sctlr = 0x00000078; 1669 } 1670 1671 static void pxa261_initfn(Object *obj) 1672 { 1673 ARMCPU *cpu = ARM_CPU(obj); 1674 1675 cpu->dtb_compatible = "marvell,xscale"; 1676 set_feature(&cpu->env, ARM_FEATURE_V5); 1677 set_feature(&cpu->env, ARM_FEATURE_XSCALE); 1678 cpu->midr = 0x69052d05; 1679 cpu->ctr = 0xd172172; 1680 cpu->reset_sctlr = 0x00000078; 1681 } 1682 1683 static void pxa262_initfn(Object *obj) 1684 { 1685 ARMCPU *cpu = ARM_CPU(obj); 1686 1687 cpu->dtb_compatible = "marvell,xscale"; 1688 set_feature(&cpu->env, ARM_FEATURE_V5); 1689 set_feature(&cpu->env, ARM_FEATURE_XSCALE); 1690 cpu->midr = 0x69052d06; 1691 cpu->ctr = 0xd172172; 1692 cpu->reset_sctlr = 0x00000078; 1693 } 1694 1695 static void pxa270a0_initfn(Object *obj) 1696 { 1697 ARMCPU *cpu = ARM_CPU(obj); 1698 1699 cpu->dtb_compatible = "marvell,xscale"; 1700 set_feature(&cpu->env, ARM_FEATURE_V5); 1701 set_feature(&cpu->env, ARM_FEATURE_XSCALE); 1702 set_feature(&cpu->env, ARM_FEATURE_IWMMXT); 1703 cpu->midr = 0x69054110; 1704 cpu->ctr = 0xd172172; 1705 cpu->reset_sctlr = 0x00000078; 1706 } 1707 1708 static void pxa270a1_initfn(Object *obj) 1709 { 1710 ARMCPU *cpu = ARM_CPU(obj); 1711 1712 cpu->dtb_compatible = "marvell,xscale"; 1713 set_feature(&cpu->env, ARM_FEATURE_V5); 1714 set_feature(&cpu->env, ARM_FEATURE_XSCALE); 1715 set_feature(&cpu->env, ARM_FEATURE_IWMMXT); 1716 cpu->midr = 0x69054111; 1717 cpu->ctr = 0xd172172; 1718 cpu->reset_sctlr = 0x00000078; 1719 } 1720 1721 static void pxa270b0_initfn(Object *obj) 1722 { 1723 ARMCPU *cpu = ARM_CPU(obj); 1724 1725 cpu->dtb_compatible = "marvell,xscale"; 1726 set_feature(&cpu->env, ARM_FEATURE_V5); 1727 set_feature(&cpu->env, ARM_FEATURE_XSCALE); 1728 set_feature(&cpu->env, ARM_FEATURE_IWMMXT); 1729 cpu->midr = 0x69054112; 1730 cpu->ctr = 0xd172172; 1731 cpu->reset_sctlr = 0x00000078; 1732 } 1733 1734 static void pxa270b1_initfn(Object *obj) 1735 { 1736 ARMCPU *cpu = ARM_CPU(obj); 1737 1738 cpu->dtb_compatible = "marvell,xscale"; 1739 set_feature(&cpu->env, ARM_FEATURE_V5); 1740 set_feature(&cpu->env, ARM_FEATURE_XSCALE); 1741 set_feature(&cpu->env, ARM_FEATURE_IWMMXT); 1742 cpu->midr = 0x69054113; 1743 cpu->ctr = 0xd172172; 1744 cpu->reset_sctlr = 0x00000078; 1745 } 1746 1747 static void pxa270c0_initfn(Object *obj) 1748 { 1749 ARMCPU *cpu = ARM_CPU(obj); 1750 1751 cpu->dtb_compatible = "marvell,xscale"; 1752 set_feature(&cpu->env, ARM_FEATURE_V5); 1753 set_feature(&cpu->env, ARM_FEATURE_XSCALE); 1754 set_feature(&cpu->env, ARM_FEATURE_IWMMXT); 1755 cpu->midr = 0x69054114; 1756 cpu->ctr = 0xd172172; 1757 cpu->reset_sctlr = 0x00000078; 1758 } 1759 1760 static void pxa270c5_initfn(Object *obj) 1761 { 1762 ARMCPU *cpu = ARM_CPU(obj); 1763 1764 cpu->dtb_compatible = "marvell,xscale"; 1765 set_feature(&cpu->env, ARM_FEATURE_V5); 1766 set_feature(&cpu->env, ARM_FEATURE_XSCALE); 1767 set_feature(&cpu->env, ARM_FEATURE_IWMMXT); 1768 cpu->midr = 0x69054117; 1769 cpu->ctr = 0xd172172; 1770 cpu->reset_sctlr = 0x00000078; 1771 } 1772 1773 #ifndef TARGET_AARCH64 1774 /* -cpu max: if KVM is enabled, like -cpu host (best possible with this host); 1775 * otherwise, a CPU with as many features enabled as our emulation supports. 1776 * The version of '-cpu max' for qemu-system-aarch64 is defined in cpu64.c; 1777 * this only needs to handle 32 bits. 1778 */ 1779 static void arm_max_initfn(Object *obj) 1780 { 1781 ARMCPU *cpu = ARM_CPU(obj); 1782 1783 if (kvm_enabled()) { 1784 kvm_arm_set_cpu_features_from_host(cpu); 1785 } else { 1786 cortex_a15_initfn(obj); 1787 #ifdef CONFIG_USER_ONLY 1788 /* We don't set these in system emulation mode for the moment, 1789 * since we don't correctly set the ID registers to advertise them, 1790 */ 1791 set_feature(&cpu->env, ARM_FEATURE_V8); 1792 set_feature(&cpu->env, ARM_FEATURE_VFP4); 1793 set_feature(&cpu->env, ARM_FEATURE_NEON); 1794 set_feature(&cpu->env, ARM_FEATURE_THUMB2EE); 1795 set_feature(&cpu->env, ARM_FEATURE_V8_AES); 1796 set_feature(&cpu->env, ARM_FEATURE_V8_SHA1); 1797 set_feature(&cpu->env, ARM_FEATURE_V8_SHA256); 1798 set_feature(&cpu->env, ARM_FEATURE_V8_PMULL); 1799 set_feature(&cpu->env, ARM_FEATURE_CRC); 1800 set_feature(&cpu->env, ARM_FEATURE_V8_RDM); 1801 set_feature(&cpu->env, ARM_FEATURE_V8_FCMA); 1802 #endif 1803 } 1804 } 1805 #endif 1806 1807 #endif /* !defined(CONFIG_USER_ONLY) || !defined(TARGET_AARCH64) */ 1808 1809 typedef struct ARMCPUInfo { 1810 const char *name; 1811 void (*initfn)(Object *obj); 1812 void (*class_init)(ObjectClass *oc, void *data); 1813 } ARMCPUInfo; 1814 1815 static const ARMCPUInfo arm_cpus[] = { 1816 #if !defined(CONFIG_USER_ONLY) || !defined(TARGET_AARCH64) 1817 { .name = "arm926", .initfn = arm926_initfn }, 1818 { .name = "arm946", .initfn = arm946_initfn }, 1819 { .name = "arm1026", .initfn = arm1026_initfn }, 1820 /* What QEMU calls "arm1136-r2" is actually the 1136 r0p2, i.e. an 1821 * older core than plain "arm1136". In particular this does not 1822 * have the v6K features. 1823 */ 1824 { .name = "arm1136-r2", .initfn = arm1136_r2_initfn }, 1825 { .name = "arm1136", .initfn = arm1136_initfn }, 1826 { .name = "arm1176", .initfn = arm1176_initfn }, 1827 { .name = "arm11mpcore", .initfn = arm11mpcore_initfn }, 1828 { .name = "cortex-m3", .initfn = cortex_m3_initfn, 1829 .class_init = arm_v7m_class_init }, 1830 { .name = "cortex-m4", .initfn = cortex_m4_initfn, 1831 .class_init = arm_v7m_class_init }, 1832 { .name = "cortex-m33", .initfn = cortex_m33_initfn, 1833 .class_init = arm_v7m_class_init }, 1834 { .name = "cortex-r5", .initfn = cortex_r5_initfn }, 1835 { .name = "cortex-r5f", .initfn = cortex_r5f_initfn }, 1836 { .name = "cortex-a7", .initfn = cortex_a7_initfn }, 1837 { .name = "cortex-a8", .initfn = cortex_a8_initfn }, 1838 { .name = "cortex-a9", .initfn = cortex_a9_initfn }, 1839 { .name = "cortex-a15", .initfn = cortex_a15_initfn }, 1840 { .name = "ti925t", .initfn = ti925t_initfn }, 1841 { .name = "sa1100", .initfn = sa1100_initfn }, 1842 { .name = "sa1110", .initfn = sa1110_initfn }, 1843 { .name = "pxa250", .initfn = pxa250_initfn }, 1844 { .name = "pxa255", .initfn = pxa255_initfn }, 1845 { .name = "pxa260", .initfn = pxa260_initfn }, 1846 { .name = "pxa261", .initfn = pxa261_initfn }, 1847 { .name = "pxa262", .initfn = pxa262_initfn }, 1848 /* "pxa270" is an alias for "pxa270-a0" */ 1849 { .name = "pxa270", .initfn = pxa270a0_initfn }, 1850 { .name = "pxa270-a0", .initfn = pxa270a0_initfn }, 1851 { .name = "pxa270-a1", .initfn = pxa270a1_initfn }, 1852 { .name = "pxa270-b0", .initfn = pxa270b0_initfn }, 1853 { .name = "pxa270-b1", .initfn = pxa270b1_initfn }, 1854 { .name = "pxa270-c0", .initfn = pxa270c0_initfn }, 1855 { .name = "pxa270-c5", .initfn = pxa270c5_initfn }, 1856 #ifndef TARGET_AARCH64 1857 { .name = "max", .initfn = arm_max_initfn }, 1858 #endif 1859 #ifdef CONFIG_USER_ONLY 1860 { .name = "any", .initfn = arm_max_initfn }, 1861 #endif 1862 #endif 1863 { .name = NULL } 1864 }; 1865 1866 static Property arm_cpu_properties[] = { 1867 DEFINE_PROP_BOOL("start-powered-off", ARMCPU, start_powered_off, false), 1868 DEFINE_PROP_UINT32("psci-conduit", ARMCPU, psci_conduit, 0), 1869 DEFINE_PROP_UINT32("midr", ARMCPU, midr, 0), 1870 DEFINE_PROP_UINT64("mp-affinity", ARMCPU, 1871 mp_affinity, ARM64_AFFINITY_INVALID), 1872 DEFINE_PROP_INT32("node-id", ARMCPU, node_id, CPU_UNSET_NUMA_NODE_ID), 1873 DEFINE_PROP_INT32("core-count", ARMCPU, core_count, -1), 1874 DEFINE_PROP_END_OF_LIST() 1875 }; 1876 1877 #ifdef CONFIG_USER_ONLY 1878 static int arm_cpu_handle_mmu_fault(CPUState *cs, vaddr address, int size, 1879 int rw, int mmu_idx) 1880 { 1881 ARMCPU *cpu = ARM_CPU(cs); 1882 CPUARMState *env = &cpu->env; 1883 1884 env->exception.vaddress = address; 1885 if (rw == 2) { 1886 cs->exception_index = EXCP_PREFETCH_ABORT; 1887 } else { 1888 cs->exception_index = EXCP_DATA_ABORT; 1889 } 1890 return 1; 1891 } 1892 #endif 1893 1894 static gchar *arm_gdb_arch_name(CPUState *cs) 1895 { 1896 ARMCPU *cpu = ARM_CPU(cs); 1897 CPUARMState *env = &cpu->env; 1898 1899 if (arm_feature(env, ARM_FEATURE_IWMMXT)) { 1900 return g_strdup("iwmmxt"); 1901 } 1902 return g_strdup("arm"); 1903 } 1904 1905 static void arm_cpu_class_init(ObjectClass *oc, void *data) 1906 { 1907 ARMCPUClass *acc = ARM_CPU_CLASS(oc); 1908 CPUClass *cc = CPU_CLASS(acc); 1909 DeviceClass *dc = DEVICE_CLASS(oc); 1910 1911 device_class_set_parent_realize(dc, arm_cpu_realizefn, 1912 &acc->parent_realize); 1913 dc->props = arm_cpu_properties; 1914 1915 acc->parent_reset = cc->reset; 1916 cc->reset = arm_cpu_reset; 1917 1918 cc->class_by_name = arm_cpu_class_by_name; 1919 cc->has_work = arm_cpu_has_work; 1920 cc->cpu_exec_interrupt = arm_cpu_exec_interrupt; 1921 cc->dump_state = arm_cpu_dump_state; 1922 cc->set_pc = arm_cpu_set_pc; 1923 cc->gdb_read_register = arm_cpu_gdb_read_register; 1924 cc->gdb_write_register = arm_cpu_gdb_write_register; 1925 #ifdef CONFIG_USER_ONLY 1926 cc->handle_mmu_fault = arm_cpu_handle_mmu_fault; 1927 #else 1928 cc->do_interrupt = arm_cpu_do_interrupt; 1929 cc->do_unaligned_access = arm_cpu_do_unaligned_access; 1930 cc->do_transaction_failed = arm_cpu_do_transaction_failed; 1931 cc->get_phys_page_attrs_debug = arm_cpu_get_phys_page_attrs_debug; 1932 cc->asidx_from_attrs = arm_asidx_from_attrs; 1933 cc->vmsd = &vmstate_arm_cpu; 1934 cc->virtio_is_big_endian = arm_cpu_virtio_is_big_endian; 1935 cc->write_elf64_note = arm_cpu_write_elf64_note; 1936 cc->write_elf32_note = arm_cpu_write_elf32_note; 1937 #endif 1938 cc->gdb_num_core_regs = 26; 1939 cc->gdb_core_xml_file = "arm-core.xml"; 1940 cc->gdb_arch_name = arm_gdb_arch_name; 1941 cc->gdb_get_dynamic_xml = arm_gdb_get_dynamic_xml; 1942 cc->gdb_stop_before_watchpoint = true; 1943 cc->debug_excp_handler = arm_debug_excp_handler; 1944 cc->debug_check_watchpoint = arm_debug_check_watchpoint; 1945 #if !defined(CONFIG_USER_ONLY) 1946 cc->adjust_watchpoint_address = arm_adjust_watchpoint_address; 1947 #endif 1948 1949 cc->disas_set_info = arm_disas_set_info; 1950 #ifdef CONFIG_TCG 1951 cc->tcg_initialize = arm_translate_init; 1952 #endif 1953 } 1954 1955 #ifdef CONFIG_KVM 1956 static void arm_host_initfn(Object *obj) 1957 { 1958 ARMCPU *cpu = ARM_CPU(obj); 1959 1960 kvm_arm_set_cpu_features_from_host(cpu); 1961 } 1962 1963 static const TypeInfo host_arm_cpu_type_info = { 1964 .name = TYPE_ARM_HOST_CPU, 1965 #ifdef TARGET_AARCH64 1966 .parent = TYPE_AARCH64_CPU, 1967 #else 1968 .parent = TYPE_ARM_CPU, 1969 #endif 1970 .instance_init = arm_host_initfn, 1971 }; 1972 1973 #endif 1974 1975 static void cpu_register(const ARMCPUInfo *info) 1976 { 1977 TypeInfo type_info = { 1978 .parent = TYPE_ARM_CPU, 1979 .instance_size = sizeof(ARMCPU), 1980 .instance_init = info->initfn, 1981 .class_size = sizeof(ARMCPUClass), 1982 .class_init = info->class_init, 1983 }; 1984 1985 type_info.name = g_strdup_printf("%s-" TYPE_ARM_CPU, info->name); 1986 type_register(&type_info); 1987 g_free((void *)type_info.name); 1988 } 1989 1990 static const TypeInfo arm_cpu_type_info = { 1991 .name = TYPE_ARM_CPU, 1992 .parent = TYPE_CPU, 1993 .instance_size = sizeof(ARMCPU), 1994 .instance_init = arm_cpu_initfn, 1995 .instance_post_init = arm_cpu_post_init, 1996 .instance_finalize = arm_cpu_finalizefn, 1997 .abstract = true, 1998 .class_size = sizeof(ARMCPUClass), 1999 .class_init = arm_cpu_class_init, 2000 }; 2001 2002 static const TypeInfo idau_interface_type_info = { 2003 .name = TYPE_IDAU_INTERFACE, 2004 .parent = TYPE_INTERFACE, 2005 .class_size = sizeof(IDAUInterfaceClass), 2006 }; 2007 2008 static void arm_cpu_register_types(void) 2009 { 2010 const ARMCPUInfo *info = arm_cpus; 2011 2012 type_register_static(&arm_cpu_type_info); 2013 type_register_static(&idau_interface_type_info); 2014 2015 while (info->name) { 2016 cpu_register(info); 2017 info++; 2018 } 2019 2020 #ifdef CONFIG_KVM 2021 type_register_static(&host_arm_cpu_type_info); 2022 #endif 2023 } 2024 2025 type_init(arm_cpu_register_types) 2026