1 /* 2 * QEMU ARM CPU 3 * 4 * Copyright (c) 2012 SUSE LINUX Products GmbH 5 * 6 * This program is free software; you can redistribute it and/or 7 * modify it under the terms of the GNU General Public License 8 * as published by the Free Software Foundation; either version 2 9 * of the License, or (at your option) any later version. 10 * 11 * This program is distributed in the hope that it will be useful, 12 * but WITHOUT ANY WARRANTY; without even the implied warranty of 13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 14 * GNU General Public License for more details. 15 * 16 * You should have received a copy of the GNU General Public License 17 * along with this program; if not, see 18 * <http://www.gnu.org/licenses/gpl-2.0.html> 19 */ 20 21 #include "qemu/osdep.h" 22 #include "qemu/error-report.h" 23 #include "qapi/error.h" 24 #include "cpu.h" 25 #include "internals.h" 26 #include "qemu-common.h" 27 #include "exec/exec-all.h" 28 #include "hw/qdev-properties.h" 29 #if !defined(CONFIG_USER_ONLY) 30 #include "hw/loader.h" 31 #endif 32 #include "hw/arm/arm.h" 33 #include "sysemu/sysemu.h" 34 #include "sysemu/hw_accel.h" 35 #include "kvm_arm.h" 36 37 static void arm_cpu_set_pc(CPUState *cs, vaddr value) 38 { 39 ARMCPU *cpu = ARM_CPU(cs); 40 41 cpu->env.regs[15] = value; 42 } 43 44 static bool arm_cpu_has_work(CPUState *cs) 45 { 46 ARMCPU *cpu = ARM_CPU(cs); 47 48 return (cpu->power_state != PSCI_OFF) 49 && cs->interrupt_request & 50 (CPU_INTERRUPT_FIQ | CPU_INTERRUPT_HARD 51 | CPU_INTERRUPT_VFIQ | CPU_INTERRUPT_VIRQ 52 | CPU_INTERRUPT_EXITTB); 53 } 54 55 void arm_register_el_change_hook(ARMCPU *cpu, ARMELChangeHook *hook, 56 void *opaque) 57 { 58 /* We currently only support registering a single hook function */ 59 assert(!cpu->el_change_hook); 60 cpu->el_change_hook = hook; 61 cpu->el_change_hook_opaque = opaque; 62 } 63 64 static void cp_reg_reset(gpointer key, gpointer value, gpointer opaque) 65 { 66 /* Reset a single ARMCPRegInfo register */ 67 ARMCPRegInfo *ri = value; 68 ARMCPU *cpu = opaque; 69 70 if (ri->type & (ARM_CP_SPECIAL | ARM_CP_ALIAS)) { 71 return; 72 } 73 74 if (ri->resetfn) { 75 ri->resetfn(&cpu->env, ri); 76 return; 77 } 78 79 /* A zero offset is never possible as it would be regs[0] 80 * so we use it to indicate that reset is being handled elsewhere. 81 * This is basically only used for fields in non-core coprocessors 82 * (like the pxa2xx ones). 83 */ 84 if (!ri->fieldoffset) { 85 return; 86 } 87 88 if (cpreg_field_is_64bit(ri)) { 89 CPREG_FIELD64(&cpu->env, ri) = ri->resetvalue; 90 } else { 91 CPREG_FIELD32(&cpu->env, ri) = ri->resetvalue; 92 } 93 } 94 95 static void cp_reg_check_reset(gpointer key, gpointer value, gpointer opaque) 96 { 97 /* Purely an assertion check: we've already done reset once, 98 * so now check that running the reset for the cpreg doesn't 99 * change its value. This traps bugs where two different cpregs 100 * both try to reset the same state field but to different values. 101 */ 102 ARMCPRegInfo *ri = value; 103 ARMCPU *cpu = opaque; 104 uint64_t oldvalue, newvalue; 105 106 if (ri->type & (ARM_CP_SPECIAL | ARM_CP_ALIAS | ARM_CP_NO_RAW)) { 107 return; 108 } 109 110 oldvalue = read_raw_cp_reg(&cpu->env, ri); 111 cp_reg_reset(key, value, opaque); 112 newvalue = read_raw_cp_reg(&cpu->env, ri); 113 assert(oldvalue == newvalue); 114 } 115 116 /* CPUClass::reset() */ 117 static void arm_cpu_reset(CPUState *s) 118 { 119 ARMCPU *cpu = ARM_CPU(s); 120 ARMCPUClass *acc = ARM_CPU_GET_CLASS(cpu); 121 CPUARMState *env = &cpu->env; 122 123 acc->parent_reset(s); 124 125 memset(env, 0, offsetof(CPUARMState, end_reset_fields)); 126 127 g_hash_table_foreach(cpu->cp_regs, cp_reg_reset, cpu); 128 g_hash_table_foreach(cpu->cp_regs, cp_reg_check_reset, cpu); 129 130 env->vfp.xregs[ARM_VFP_FPSID] = cpu->reset_fpsid; 131 env->vfp.xregs[ARM_VFP_MVFR0] = cpu->mvfr0; 132 env->vfp.xregs[ARM_VFP_MVFR1] = cpu->mvfr1; 133 env->vfp.xregs[ARM_VFP_MVFR2] = cpu->mvfr2; 134 135 cpu->power_state = cpu->start_powered_off ? PSCI_OFF : PSCI_ON; 136 s->halted = cpu->start_powered_off; 137 138 if (arm_feature(env, ARM_FEATURE_IWMMXT)) { 139 env->iwmmxt.cregs[ARM_IWMMXT_wCID] = 0x69051000 | 'Q'; 140 } 141 142 if (arm_feature(env, ARM_FEATURE_AARCH64)) { 143 /* 64 bit CPUs always start in 64 bit mode */ 144 env->aarch64 = 1; 145 #if defined(CONFIG_USER_ONLY) 146 env->pstate = PSTATE_MODE_EL0t; 147 /* Userspace expects access to DC ZVA, CTL_EL0 and the cache ops */ 148 env->cp15.sctlr_el[1] |= SCTLR_UCT | SCTLR_UCI | SCTLR_DZE; 149 /* and to the FP/Neon instructions */ 150 env->cp15.cpacr_el1 = deposit64(env->cp15.cpacr_el1, 20, 2, 3); 151 #else 152 /* Reset into the highest available EL */ 153 if (arm_feature(env, ARM_FEATURE_EL3)) { 154 env->pstate = PSTATE_MODE_EL3h; 155 } else if (arm_feature(env, ARM_FEATURE_EL2)) { 156 env->pstate = PSTATE_MODE_EL2h; 157 } else { 158 env->pstate = PSTATE_MODE_EL1h; 159 } 160 env->pc = cpu->rvbar; 161 #endif 162 } else { 163 #if defined(CONFIG_USER_ONLY) 164 /* Userspace expects access to cp10 and cp11 for FP/Neon */ 165 env->cp15.cpacr_el1 = deposit64(env->cp15.cpacr_el1, 20, 4, 0xf); 166 #endif 167 } 168 169 #if defined(CONFIG_USER_ONLY) 170 env->uncached_cpsr = ARM_CPU_MODE_USR; 171 /* For user mode we must enable access to coprocessors */ 172 env->vfp.xregs[ARM_VFP_FPEXC] = 1 << 30; 173 if (arm_feature(env, ARM_FEATURE_IWMMXT)) { 174 env->cp15.c15_cpar = 3; 175 } else if (arm_feature(env, ARM_FEATURE_XSCALE)) { 176 env->cp15.c15_cpar = 1; 177 } 178 #else 179 /* SVC mode with interrupts disabled. */ 180 env->uncached_cpsr = ARM_CPU_MODE_SVC; 181 env->daif = PSTATE_D | PSTATE_A | PSTATE_I | PSTATE_F; 182 183 if (arm_feature(env, ARM_FEATURE_M)) { 184 uint32_t initial_msp; /* Loaded from 0x0 */ 185 uint32_t initial_pc; /* Loaded from 0x4 */ 186 uint8_t *rom; 187 188 if (arm_feature(env, ARM_FEATURE_M_SECURITY)) { 189 env->v7m.secure = true; 190 } 191 192 /* The reset value of this bit is IMPDEF, but ARM recommends 193 * that it resets to 1, so QEMU always does that rather than making 194 * it dependent on CPU model. 195 */ 196 env->v7m.ccr = R_V7M_CCR_STKALIGN_MASK; 197 198 /* Unlike A/R profile, M profile defines the reset LR value */ 199 env->regs[14] = 0xffffffff; 200 201 /* Load the initial SP and PC from the vector table at address 0 */ 202 rom = rom_ptr(0); 203 if (rom) { 204 /* Address zero is covered by ROM which hasn't yet been 205 * copied into physical memory. 206 */ 207 initial_msp = ldl_p(rom); 208 initial_pc = ldl_p(rom + 4); 209 } else { 210 /* Address zero not covered by a ROM blob, or the ROM blob 211 * is in non-modifiable memory and this is a second reset after 212 * it got copied into memory. In the latter case, rom_ptr 213 * will return a NULL pointer and we should use ldl_phys instead. 214 */ 215 initial_msp = ldl_phys(s->as, 0); 216 initial_pc = ldl_phys(s->as, 4); 217 } 218 219 env->regs[13] = initial_msp & 0xFFFFFFFC; 220 env->regs[15] = initial_pc & ~1; 221 env->thumb = initial_pc & 1; 222 } 223 224 /* AArch32 has a hard highvec setting of 0xFFFF0000. If we are currently 225 * executing as AArch32 then check if highvecs are enabled and 226 * adjust the PC accordingly. 227 */ 228 if (A32_BANKED_CURRENT_REG_GET(env, sctlr) & SCTLR_V) { 229 env->regs[15] = 0xFFFF0000; 230 } 231 232 env->vfp.xregs[ARM_VFP_FPEXC] = 0; 233 #endif 234 235 if (arm_feature(env, ARM_FEATURE_PMSA)) { 236 if (cpu->pmsav7_dregion > 0) { 237 if (arm_feature(env, ARM_FEATURE_V8)) { 238 memset(env->pmsav8.rbar, 0, 239 sizeof(*env->pmsav8.rbar) * cpu->pmsav7_dregion); 240 memset(env->pmsav8.rlar, 0, 241 sizeof(*env->pmsav8.rlar) * cpu->pmsav7_dregion); 242 } else if (arm_feature(env, ARM_FEATURE_V7)) { 243 memset(env->pmsav7.drbar, 0, 244 sizeof(*env->pmsav7.drbar) * cpu->pmsav7_dregion); 245 memset(env->pmsav7.drsr, 0, 246 sizeof(*env->pmsav7.drsr) * cpu->pmsav7_dregion); 247 memset(env->pmsav7.dracr, 0, 248 sizeof(*env->pmsav7.dracr) * cpu->pmsav7_dregion); 249 } 250 } 251 env->pmsav7.rnr = 0; 252 env->pmsav8.mair0 = 0; 253 env->pmsav8.mair1 = 0; 254 } 255 256 set_flush_to_zero(1, &env->vfp.standard_fp_status); 257 set_flush_inputs_to_zero(1, &env->vfp.standard_fp_status); 258 set_default_nan_mode(1, &env->vfp.standard_fp_status); 259 set_float_detect_tininess(float_tininess_before_rounding, 260 &env->vfp.fp_status); 261 set_float_detect_tininess(float_tininess_before_rounding, 262 &env->vfp.standard_fp_status); 263 #ifndef CONFIG_USER_ONLY 264 if (kvm_enabled()) { 265 kvm_arm_reset_vcpu(cpu); 266 } 267 #endif 268 269 hw_breakpoint_update_all(cpu); 270 hw_watchpoint_update_all(cpu); 271 } 272 273 bool arm_cpu_exec_interrupt(CPUState *cs, int interrupt_request) 274 { 275 CPUClass *cc = CPU_GET_CLASS(cs); 276 CPUARMState *env = cs->env_ptr; 277 uint32_t cur_el = arm_current_el(env); 278 bool secure = arm_is_secure(env); 279 uint32_t target_el; 280 uint32_t excp_idx; 281 bool ret = false; 282 283 if (interrupt_request & CPU_INTERRUPT_FIQ) { 284 excp_idx = EXCP_FIQ; 285 target_el = arm_phys_excp_target_el(cs, excp_idx, cur_el, secure); 286 if (arm_excp_unmasked(cs, excp_idx, target_el)) { 287 cs->exception_index = excp_idx; 288 env->exception.target_el = target_el; 289 cc->do_interrupt(cs); 290 ret = true; 291 } 292 } 293 if (interrupt_request & CPU_INTERRUPT_HARD) { 294 excp_idx = EXCP_IRQ; 295 target_el = arm_phys_excp_target_el(cs, excp_idx, cur_el, secure); 296 if (arm_excp_unmasked(cs, excp_idx, target_el)) { 297 cs->exception_index = excp_idx; 298 env->exception.target_el = target_el; 299 cc->do_interrupt(cs); 300 ret = true; 301 } 302 } 303 if (interrupt_request & CPU_INTERRUPT_VIRQ) { 304 excp_idx = EXCP_VIRQ; 305 target_el = 1; 306 if (arm_excp_unmasked(cs, excp_idx, target_el)) { 307 cs->exception_index = excp_idx; 308 env->exception.target_el = target_el; 309 cc->do_interrupt(cs); 310 ret = true; 311 } 312 } 313 if (interrupt_request & CPU_INTERRUPT_VFIQ) { 314 excp_idx = EXCP_VFIQ; 315 target_el = 1; 316 if (arm_excp_unmasked(cs, excp_idx, target_el)) { 317 cs->exception_index = excp_idx; 318 env->exception.target_el = target_el; 319 cc->do_interrupt(cs); 320 ret = true; 321 } 322 } 323 324 return ret; 325 } 326 327 #if !defined(CONFIG_USER_ONLY) || !defined(TARGET_AARCH64) 328 static bool arm_v7m_cpu_exec_interrupt(CPUState *cs, int interrupt_request) 329 { 330 CPUClass *cc = CPU_GET_CLASS(cs); 331 ARMCPU *cpu = ARM_CPU(cs); 332 CPUARMState *env = &cpu->env; 333 bool ret = false; 334 335 /* ARMv7-M interrupt masking works differently than -A or -R. 336 * There is no FIQ/IRQ distinction. Instead of I and F bits 337 * masking FIQ and IRQ interrupts, an exception is taken only 338 * if it is higher priority than the current execution priority 339 * (which depends on state like BASEPRI, FAULTMASK and the 340 * currently active exception). 341 */ 342 if (interrupt_request & CPU_INTERRUPT_HARD 343 && (armv7m_nvic_can_take_pending_exception(env->nvic))) { 344 cs->exception_index = EXCP_IRQ; 345 cc->do_interrupt(cs); 346 ret = true; 347 } 348 return ret; 349 } 350 #endif 351 352 #ifndef CONFIG_USER_ONLY 353 static void arm_cpu_set_irq(void *opaque, int irq, int level) 354 { 355 ARMCPU *cpu = opaque; 356 CPUARMState *env = &cpu->env; 357 CPUState *cs = CPU(cpu); 358 static const int mask[] = { 359 [ARM_CPU_IRQ] = CPU_INTERRUPT_HARD, 360 [ARM_CPU_FIQ] = CPU_INTERRUPT_FIQ, 361 [ARM_CPU_VIRQ] = CPU_INTERRUPT_VIRQ, 362 [ARM_CPU_VFIQ] = CPU_INTERRUPT_VFIQ 363 }; 364 365 switch (irq) { 366 case ARM_CPU_VIRQ: 367 case ARM_CPU_VFIQ: 368 assert(arm_feature(env, ARM_FEATURE_EL2)); 369 /* fall through */ 370 case ARM_CPU_IRQ: 371 case ARM_CPU_FIQ: 372 if (level) { 373 cpu_interrupt(cs, mask[irq]); 374 } else { 375 cpu_reset_interrupt(cs, mask[irq]); 376 } 377 break; 378 default: 379 g_assert_not_reached(); 380 } 381 } 382 383 static void arm_cpu_kvm_set_irq(void *opaque, int irq, int level) 384 { 385 #ifdef CONFIG_KVM 386 ARMCPU *cpu = opaque; 387 CPUState *cs = CPU(cpu); 388 int kvm_irq = KVM_ARM_IRQ_TYPE_CPU << KVM_ARM_IRQ_TYPE_SHIFT; 389 390 switch (irq) { 391 case ARM_CPU_IRQ: 392 kvm_irq |= KVM_ARM_IRQ_CPU_IRQ; 393 break; 394 case ARM_CPU_FIQ: 395 kvm_irq |= KVM_ARM_IRQ_CPU_FIQ; 396 break; 397 default: 398 g_assert_not_reached(); 399 } 400 kvm_irq |= cs->cpu_index << KVM_ARM_IRQ_VCPU_SHIFT; 401 kvm_set_irq(kvm_state, kvm_irq, level ? 1 : 0); 402 #endif 403 } 404 405 static bool arm_cpu_virtio_is_big_endian(CPUState *cs) 406 { 407 ARMCPU *cpu = ARM_CPU(cs); 408 CPUARMState *env = &cpu->env; 409 410 cpu_synchronize_state(cs); 411 return arm_cpu_data_is_big_endian(env); 412 } 413 414 #endif 415 416 static inline void set_feature(CPUARMState *env, int feature) 417 { 418 env->features |= 1ULL << feature; 419 } 420 421 static inline void unset_feature(CPUARMState *env, int feature) 422 { 423 env->features &= ~(1ULL << feature); 424 } 425 426 static int 427 print_insn_thumb1(bfd_vma pc, disassemble_info *info) 428 { 429 return print_insn_arm(pc | 1, info); 430 } 431 432 static int arm_read_memory_func(bfd_vma memaddr, bfd_byte *b, 433 int length, struct disassemble_info *info) 434 { 435 assert(info->read_memory_inner_func); 436 assert((info->flags & INSN_ARM_BE32) == 0 || length == 2 || length == 4); 437 438 if ((info->flags & INSN_ARM_BE32) != 0 && length == 2) { 439 assert(info->endian == BFD_ENDIAN_LITTLE); 440 return info->read_memory_inner_func(memaddr ^ 2, (bfd_byte *)b, 2, 441 info); 442 } else { 443 return info->read_memory_inner_func(memaddr, b, length, info); 444 } 445 } 446 447 static void arm_disas_set_info(CPUState *cpu, disassemble_info *info) 448 { 449 ARMCPU *ac = ARM_CPU(cpu); 450 CPUARMState *env = &ac->env; 451 452 if (is_a64(env)) { 453 /* We might not be compiled with the A64 disassembler 454 * because it needs a C++ compiler. Leave print_insn 455 * unset in this case to use the caller default behaviour. 456 */ 457 #if defined(CONFIG_ARM_A64_DIS) 458 info->print_insn = print_insn_arm_a64; 459 #endif 460 } else if (env->thumb) { 461 info->print_insn = print_insn_thumb1; 462 } else { 463 info->print_insn = print_insn_arm; 464 } 465 if (bswap_code(arm_sctlr_b(env))) { 466 #ifdef TARGET_WORDS_BIGENDIAN 467 info->endian = BFD_ENDIAN_LITTLE; 468 #else 469 info->endian = BFD_ENDIAN_BIG; 470 #endif 471 } 472 if (info->read_memory_inner_func == NULL) { 473 info->read_memory_inner_func = info->read_memory_func; 474 info->read_memory_func = arm_read_memory_func; 475 } 476 info->flags &= ~INSN_ARM_BE32; 477 if (arm_sctlr_b(env)) { 478 info->flags |= INSN_ARM_BE32; 479 } 480 } 481 482 uint64_t arm_cpu_mp_affinity(int idx, uint8_t clustersz) 483 { 484 uint32_t Aff1 = idx / clustersz; 485 uint32_t Aff0 = idx % clustersz; 486 return (Aff1 << ARM_AFF1_SHIFT) | Aff0; 487 } 488 489 static void arm_cpu_initfn(Object *obj) 490 { 491 CPUState *cs = CPU(obj); 492 ARMCPU *cpu = ARM_CPU(obj); 493 static bool inited; 494 495 cs->env_ptr = &cpu->env; 496 cpu->cp_regs = g_hash_table_new_full(g_int_hash, g_int_equal, 497 g_free, g_free); 498 499 #ifndef CONFIG_USER_ONLY 500 /* Our inbound IRQ and FIQ lines */ 501 if (kvm_enabled()) { 502 /* VIRQ and VFIQ are unused with KVM but we add them to maintain 503 * the same interface as non-KVM CPUs. 504 */ 505 qdev_init_gpio_in(DEVICE(cpu), arm_cpu_kvm_set_irq, 4); 506 } else { 507 qdev_init_gpio_in(DEVICE(cpu), arm_cpu_set_irq, 4); 508 } 509 510 cpu->gt_timer[GTIMER_PHYS] = timer_new(QEMU_CLOCK_VIRTUAL, GTIMER_SCALE, 511 arm_gt_ptimer_cb, cpu); 512 cpu->gt_timer[GTIMER_VIRT] = timer_new(QEMU_CLOCK_VIRTUAL, GTIMER_SCALE, 513 arm_gt_vtimer_cb, cpu); 514 cpu->gt_timer[GTIMER_HYP] = timer_new(QEMU_CLOCK_VIRTUAL, GTIMER_SCALE, 515 arm_gt_htimer_cb, cpu); 516 cpu->gt_timer[GTIMER_SEC] = timer_new(QEMU_CLOCK_VIRTUAL, GTIMER_SCALE, 517 arm_gt_stimer_cb, cpu); 518 qdev_init_gpio_out(DEVICE(cpu), cpu->gt_timer_outputs, 519 ARRAY_SIZE(cpu->gt_timer_outputs)); 520 521 qdev_init_gpio_out_named(DEVICE(cpu), &cpu->gicv3_maintenance_interrupt, 522 "gicv3-maintenance-interrupt", 1); 523 qdev_init_gpio_out_named(DEVICE(cpu), &cpu->pmu_interrupt, 524 "pmu-interrupt", 1); 525 #endif 526 527 /* DTB consumers generally don't in fact care what the 'compatible' 528 * string is, so always provide some string and trust that a hypothetical 529 * picky DTB consumer will also provide a helpful error message. 530 */ 531 cpu->dtb_compatible = "qemu,unknown"; 532 cpu->psci_version = 1; /* By default assume PSCI v0.1 */ 533 cpu->kvm_target = QEMU_KVM_ARM_TARGET_NONE; 534 535 if (tcg_enabled()) { 536 cpu->psci_version = 2; /* TCG implements PSCI 0.2 */ 537 if (!inited) { 538 inited = true; 539 arm_translate_init(); 540 } 541 } 542 } 543 544 static Property arm_cpu_reset_cbar_property = 545 DEFINE_PROP_UINT64("reset-cbar", ARMCPU, reset_cbar, 0); 546 547 static Property arm_cpu_reset_hivecs_property = 548 DEFINE_PROP_BOOL("reset-hivecs", ARMCPU, reset_hivecs, false); 549 550 static Property arm_cpu_rvbar_property = 551 DEFINE_PROP_UINT64("rvbar", ARMCPU, rvbar, 0); 552 553 static Property arm_cpu_has_el2_property = 554 DEFINE_PROP_BOOL("has_el2", ARMCPU, has_el2, true); 555 556 static Property arm_cpu_has_el3_property = 557 DEFINE_PROP_BOOL("has_el3", ARMCPU, has_el3, true); 558 559 static Property arm_cpu_cfgend_property = 560 DEFINE_PROP_BOOL("cfgend", ARMCPU, cfgend, false); 561 562 /* use property name "pmu" to match other archs and virt tools */ 563 static Property arm_cpu_has_pmu_property = 564 DEFINE_PROP_BOOL("pmu", ARMCPU, has_pmu, true); 565 566 static Property arm_cpu_has_mpu_property = 567 DEFINE_PROP_BOOL("has-mpu", ARMCPU, has_mpu, true); 568 569 /* This is like DEFINE_PROP_UINT32 but it doesn't set the default value, 570 * because the CPU initfn will have already set cpu->pmsav7_dregion to 571 * the right value for that particular CPU type, and we don't want 572 * to override that with an incorrect constant value. 573 */ 574 static Property arm_cpu_pmsav7_dregion_property = 575 DEFINE_PROP_UNSIGNED_NODEFAULT("pmsav7-dregion", ARMCPU, 576 pmsav7_dregion, 577 qdev_prop_uint32, uint32_t); 578 579 static void arm_cpu_post_init(Object *obj) 580 { 581 ARMCPU *cpu = ARM_CPU(obj); 582 583 /* M profile implies PMSA. We have to do this here rather than 584 * in realize with the other feature-implication checks because 585 * we look at the PMSA bit to see if we should add some properties. 586 */ 587 if (arm_feature(&cpu->env, ARM_FEATURE_M)) { 588 set_feature(&cpu->env, ARM_FEATURE_PMSA); 589 } 590 591 if (arm_feature(&cpu->env, ARM_FEATURE_CBAR) || 592 arm_feature(&cpu->env, ARM_FEATURE_CBAR_RO)) { 593 qdev_property_add_static(DEVICE(obj), &arm_cpu_reset_cbar_property, 594 &error_abort); 595 } 596 597 if (!arm_feature(&cpu->env, ARM_FEATURE_M)) { 598 qdev_property_add_static(DEVICE(obj), &arm_cpu_reset_hivecs_property, 599 &error_abort); 600 } 601 602 if (arm_feature(&cpu->env, ARM_FEATURE_AARCH64)) { 603 qdev_property_add_static(DEVICE(obj), &arm_cpu_rvbar_property, 604 &error_abort); 605 } 606 607 if (arm_feature(&cpu->env, ARM_FEATURE_EL3)) { 608 /* Add the has_el3 state CPU property only if EL3 is allowed. This will 609 * prevent "has_el3" from existing on CPUs which cannot support EL3. 610 */ 611 qdev_property_add_static(DEVICE(obj), &arm_cpu_has_el3_property, 612 &error_abort); 613 614 #ifndef CONFIG_USER_ONLY 615 object_property_add_link(obj, "secure-memory", 616 TYPE_MEMORY_REGION, 617 (Object **)&cpu->secure_memory, 618 qdev_prop_allow_set_link_before_realize, 619 OBJ_PROP_LINK_UNREF_ON_RELEASE, 620 &error_abort); 621 #endif 622 } 623 624 if (arm_feature(&cpu->env, ARM_FEATURE_EL2)) { 625 qdev_property_add_static(DEVICE(obj), &arm_cpu_has_el2_property, 626 &error_abort); 627 } 628 629 if (arm_feature(&cpu->env, ARM_FEATURE_PMU)) { 630 qdev_property_add_static(DEVICE(obj), &arm_cpu_has_pmu_property, 631 &error_abort); 632 } 633 634 if (arm_feature(&cpu->env, ARM_FEATURE_PMSA)) { 635 qdev_property_add_static(DEVICE(obj), &arm_cpu_has_mpu_property, 636 &error_abort); 637 if (arm_feature(&cpu->env, ARM_FEATURE_V7)) { 638 qdev_property_add_static(DEVICE(obj), 639 &arm_cpu_pmsav7_dregion_property, 640 &error_abort); 641 } 642 } 643 644 qdev_property_add_static(DEVICE(obj), &arm_cpu_cfgend_property, 645 &error_abort); 646 } 647 648 static void arm_cpu_finalizefn(Object *obj) 649 { 650 ARMCPU *cpu = ARM_CPU(obj); 651 g_hash_table_destroy(cpu->cp_regs); 652 } 653 654 static void arm_cpu_realizefn(DeviceState *dev, Error **errp) 655 { 656 CPUState *cs = CPU(dev); 657 ARMCPU *cpu = ARM_CPU(dev); 658 ARMCPUClass *acc = ARM_CPU_GET_CLASS(dev); 659 CPUARMState *env = &cpu->env; 660 int pagebits; 661 Error *local_err = NULL; 662 663 cpu_exec_realizefn(cs, &local_err); 664 if (local_err != NULL) { 665 error_propagate(errp, local_err); 666 return; 667 } 668 669 /* Some features automatically imply others: */ 670 if (arm_feature(env, ARM_FEATURE_V8)) { 671 set_feature(env, ARM_FEATURE_V7); 672 set_feature(env, ARM_FEATURE_ARM_DIV); 673 set_feature(env, ARM_FEATURE_LPAE); 674 } 675 if (arm_feature(env, ARM_FEATURE_V7)) { 676 set_feature(env, ARM_FEATURE_VAPA); 677 set_feature(env, ARM_FEATURE_THUMB2); 678 set_feature(env, ARM_FEATURE_MPIDR); 679 if (!arm_feature(env, ARM_FEATURE_M)) { 680 set_feature(env, ARM_FEATURE_V6K); 681 } else { 682 set_feature(env, ARM_FEATURE_V6); 683 } 684 685 /* Always define VBAR for V7 CPUs even if it doesn't exist in 686 * non-EL3 configs. This is needed by some legacy boards. 687 */ 688 set_feature(env, ARM_FEATURE_VBAR); 689 } 690 if (arm_feature(env, ARM_FEATURE_V6K)) { 691 set_feature(env, ARM_FEATURE_V6); 692 set_feature(env, ARM_FEATURE_MVFR); 693 } 694 if (arm_feature(env, ARM_FEATURE_V6)) { 695 set_feature(env, ARM_FEATURE_V5); 696 if (!arm_feature(env, ARM_FEATURE_M)) { 697 set_feature(env, ARM_FEATURE_AUXCR); 698 } 699 } 700 if (arm_feature(env, ARM_FEATURE_V5)) { 701 set_feature(env, ARM_FEATURE_V4T); 702 } 703 if (arm_feature(env, ARM_FEATURE_M)) { 704 set_feature(env, ARM_FEATURE_THUMB_DIV); 705 } 706 if (arm_feature(env, ARM_FEATURE_ARM_DIV)) { 707 set_feature(env, ARM_FEATURE_THUMB_DIV); 708 } 709 if (arm_feature(env, ARM_FEATURE_VFP4)) { 710 set_feature(env, ARM_FEATURE_VFP3); 711 set_feature(env, ARM_FEATURE_VFP_FP16); 712 } 713 if (arm_feature(env, ARM_FEATURE_VFP3)) { 714 set_feature(env, ARM_FEATURE_VFP); 715 } 716 if (arm_feature(env, ARM_FEATURE_LPAE)) { 717 set_feature(env, ARM_FEATURE_V7MP); 718 set_feature(env, ARM_FEATURE_PXN); 719 } 720 if (arm_feature(env, ARM_FEATURE_CBAR_RO)) { 721 set_feature(env, ARM_FEATURE_CBAR); 722 } 723 if (arm_feature(env, ARM_FEATURE_THUMB2) && 724 !arm_feature(env, ARM_FEATURE_M)) { 725 set_feature(env, ARM_FEATURE_THUMB_DSP); 726 } 727 728 if (arm_feature(env, ARM_FEATURE_V7) && 729 !arm_feature(env, ARM_FEATURE_M) && 730 !arm_feature(env, ARM_FEATURE_PMSA)) { 731 /* v7VMSA drops support for the old ARMv5 tiny pages, so we 732 * can use 4K pages. 733 */ 734 pagebits = 12; 735 } else { 736 /* For CPUs which might have tiny 1K pages, or which have an 737 * MPU and might have small region sizes, stick with 1K pages. 738 */ 739 pagebits = 10; 740 } 741 if (!set_preferred_target_page_bits(pagebits)) { 742 /* This can only ever happen for hotplugging a CPU, or if 743 * the board code incorrectly creates a CPU which it has 744 * promised via minimum_page_size that it will not. 745 */ 746 error_setg(errp, "This CPU requires a smaller page size than the " 747 "system is using"); 748 return; 749 } 750 751 /* This cpu-id-to-MPIDR affinity is used only for TCG; KVM will override it. 752 * We don't support setting cluster ID ([16..23]) (known as Aff2 753 * in later ARM ARM versions), or any of the higher affinity level fields, 754 * so these bits always RAZ. 755 */ 756 if (cpu->mp_affinity == ARM64_AFFINITY_INVALID) { 757 cpu->mp_affinity = arm_cpu_mp_affinity(cs->cpu_index, 758 ARM_DEFAULT_CPUS_PER_CLUSTER); 759 } 760 761 if (cpu->reset_hivecs) { 762 cpu->reset_sctlr |= (1 << 13); 763 } 764 765 if (cpu->cfgend) { 766 if (arm_feature(&cpu->env, ARM_FEATURE_V7)) { 767 cpu->reset_sctlr |= SCTLR_EE; 768 } else { 769 cpu->reset_sctlr |= SCTLR_B; 770 } 771 } 772 773 if (!cpu->has_el3) { 774 /* If the has_el3 CPU property is disabled then we need to disable the 775 * feature. 776 */ 777 unset_feature(env, ARM_FEATURE_EL3); 778 779 /* Disable the security extension feature bits in the processor feature 780 * registers as well. These are id_pfr1[7:4] and id_aa64pfr0[15:12]. 781 */ 782 cpu->id_pfr1 &= ~0xf0; 783 cpu->id_aa64pfr0 &= ~0xf000; 784 } 785 786 if (!cpu->has_el2) { 787 unset_feature(env, ARM_FEATURE_EL2); 788 } 789 790 if (!cpu->has_pmu) { 791 unset_feature(env, ARM_FEATURE_PMU); 792 cpu->id_aa64dfr0 &= ~0xf00; 793 } 794 795 if (!arm_feature(env, ARM_FEATURE_EL2)) { 796 /* Disable the hypervisor feature bits in the processor feature 797 * registers if we don't have EL2. These are id_pfr1[15:12] and 798 * id_aa64pfr0_el1[11:8]. 799 */ 800 cpu->id_aa64pfr0 &= ~0xf00; 801 cpu->id_pfr1 &= ~0xf000; 802 } 803 804 /* MPU can be configured out of a PMSA CPU either by setting has-mpu 805 * to false or by setting pmsav7-dregion to 0. 806 */ 807 if (!cpu->has_mpu) { 808 cpu->pmsav7_dregion = 0; 809 } 810 if (cpu->pmsav7_dregion == 0) { 811 cpu->has_mpu = false; 812 } 813 814 if (arm_feature(env, ARM_FEATURE_PMSA) && 815 arm_feature(env, ARM_FEATURE_V7)) { 816 uint32_t nr = cpu->pmsav7_dregion; 817 818 if (nr > 0xff) { 819 error_setg(errp, "PMSAv7 MPU #regions invalid %" PRIu32, nr); 820 return; 821 } 822 823 if (nr) { 824 if (arm_feature(env, ARM_FEATURE_V8)) { 825 /* PMSAv8 */ 826 env->pmsav8.rbar = g_new0(uint32_t, nr); 827 env->pmsav8.rlar = g_new0(uint32_t, nr); 828 } else { 829 env->pmsav7.drbar = g_new0(uint32_t, nr); 830 env->pmsav7.drsr = g_new0(uint32_t, nr); 831 env->pmsav7.dracr = g_new0(uint32_t, nr); 832 } 833 } 834 } 835 836 if (arm_feature(env, ARM_FEATURE_EL3)) { 837 set_feature(env, ARM_FEATURE_VBAR); 838 } 839 840 register_cp_regs_for_features(cpu); 841 arm_cpu_register_gdb_regs_for_features(cpu); 842 843 init_cpreg_list(cpu); 844 845 #ifndef CONFIG_USER_ONLY 846 if (cpu->has_el3 || arm_feature(env, ARM_FEATURE_M_SECURITY)) { 847 AddressSpace *as; 848 849 cs->num_ases = 2; 850 851 if (!cpu->secure_memory) { 852 cpu->secure_memory = cs->memory; 853 } 854 as = address_space_init_shareable(cpu->secure_memory, 855 "cpu-secure-memory"); 856 cpu_address_space_init(cs, as, ARMASIdx_S); 857 } else { 858 cs->num_ases = 1; 859 } 860 861 cpu_address_space_init(cs, 862 address_space_init_shareable(cs->memory, 863 "cpu-memory"), 864 ARMASIdx_NS); 865 #endif 866 867 qemu_init_vcpu(cs); 868 cpu_reset(cs); 869 870 acc->parent_realize(dev, errp); 871 } 872 873 static ObjectClass *arm_cpu_class_by_name(const char *cpu_model) 874 { 875 ObjectClass *oc; 876 char *typename; 877 char **cpuname; 878 879 if (!cpu_model) { 880 return NULL; 881 } 882 883 cpuname = g_strsplit(cpu_model, ",", 1); 884 typename = g_strdup_printf("%s-" TYPE_ARM_CPU, cpuname[0]); 885 oc = object_class_by_name(typename); 886 g_strfreev(cpuname); 887 g_free(typename); 888 if (!oc || !object_class_dynamic_cast(oc, TYPE_ARM_CPU) || 889 object_class_is_abstract(oc)) { 890 return NULL; 891 } 892 return oc; 893 } 894 895 /* CPU models. These are not needed for the AArch64 linux-user build. */ 896 #if !defined(CONFIG_USER_ONLY) || !defined(TARGET_AARCH64) 897 898 static void arm926_initfn(Object *obj) 899 { 900 ARMCPU *cpu = ARM_CPU(obj); 901 902 cpu->dtb_compatible = "arm,arm926"; 903 set_feature(&cpu->env, ARM_FEATURE_V5); 904 set_feature(&cpu->env, ARM_FEATURE_VFP); 905 set_feature(&cpu->env, ARM_FEATURE_DUMMY_C15_REGS); 906 set_feature(&cpu->env, ARM_FEATURE_CACHE_TEST_CLEAN); 907 cpu->midr = 0x41069265; 908 cpu->reset_fpsid = 0x41011090; 909 cpu->ctr = 0x1dd20d2; 910 cpu->reset_sctlr = 0x00090078; 911 } 912 913 static void arm946_initfn(Object *obj) 914 { 915 ARMCPU *cpu = ARM_CPU(obj); 916 917 cpu->dtb_compatible = "arm,arm946"; 918 set_feature(&cpu->env, ARM_FEATURE_V5); 919 set_feature(&cpu->env, ARM_FEATURE_PMSA); 920 set_feature(&cpu->env, ARM_FEATURE_DUMMY_C15_REGS); 921 cpu->midr = 0x41059461; 922 cpu->ctr = 0x0f004006; 923 cpu->reset_sctlr = 0x00000078; 924 } 925 926 static void arm1026_initfn(Object *obj) 927 { 928 ARMCPU *cpu = ARM_CPU(obj); 929 930 cpu->dtb_compatible = "arm,arm1026"; 931 set_feature(&cpu->env, ARM_FEATURE_V5); 932 set_feature(&cpu->env, ARM_FEATURE_VFP); 933 set_feature(&cpu->env, ARM_FEATURE_AUXCR); 934 set_feature(&cpu->env, ARM_FEATURE_DUMMY_C15_REGS); 935 set_feature(&cpu->env, ARM_FEATURE_CACHE_TEST_CLEAN); 936 cpu->midr = 0x4106a262; 937 cpu->reset_fpsid = 0x410110a0; 938 cpu->ctr = 0x1dd20d2; 939 cpu->reset_sctlr = 0x00090078; 940 cpu->reset_auxcr = 1; 941 { 942 /* The 1026 had an IFAR at c6,c0,0,1 rather than the ARMv6 c6,c0,0,2 */ 943 ARMCPRegInfo ifar = { 944 .name = "IFAR", .cp = 15, .crn = 6, .crm = 0, .opc1 = 0, .opc2 = 1, 945 .access = PL1_RW, 946 .fieldoffset = offsetof(CPUARMState, cp15.ifar_ns), 947 .resetvalue = 0 948 }; 949 define_one_arm_cp_reg(cpu, &ifar); 950 } 951 } 952 953 static void arm1136_r2_initfn(Object *obj) 954 { 955 ARMCPU *cpu = ARM_CPU(obj); 956 /* What qemu calls "arm1136_r2" is actually the 1136 r0p2, ie an 957 * older core than plain "arm1136". In particular this does not 958 * have the v6K features. 959 * These ID register values are correct for 1136 but may be wrong 960 * for 1136_r2 (in particular r0p2 does not actually implement most 961 * of the ID registers). 962 */ 963 964 cpu->dtb_compatible = "arm,arm1136"; 965 set_feature(&cpu->env, ARM_FEATURE_V6); 966 set_feature(&cpu->env, ARM_FEATURE_VFP); 967 set_feature(&cpu->env, ARM_FEATURE_DUMMY_C15_REGS); 968 set_feature(&cpu->env, ARM_FEATURE_CACHE_DIRTY_REG); 969 set_feature(&cpu->env, ARM_FEATURE_CACHE_BLOCK_OPS); 970 cpu->midr = 0x4107b362; 971 cpu->reset_fpsid = 0x410120b4; 972 cpu->mvfr0 = 0x11111111; 973 cpu->mvfr1 = 0x00000000; 974 cpu->ctr = 0x1dd20d2; 975 cpu->reset_sctlr = 0x00050078; 976 cpu->id_pfr0 = 0x111; 977 cpu->id_pfr1 = 0x1; 978 cpu->id_dfr0 = 0x2; 979 cpu->id_afr0 = 0x3; 980 cpu->id_mmfr0 = 0x01130003; 981 cpu->id_mmfr1 = 0x10030302; 982 cpu->id_mmfr2 = 0x01222110; 983 cpu->id_isar0 = 0x00140011; 984 cpu->id_isar1 = 0x12002111; 985 cpu->id_isar2 = 0x11231111; 986 cpu->id_isar3 = 0x01102131; 987 cpu->id_isar4 = 0x141; 988 cpu->reset_auxcr = 7; 989 } 990 991 static void arm1136_initfn(Object *obj) 992 { 993 ARMCPU *cpu = ARM_CPU(obj); 994 995 cpu->dtb_compatible = "arm,arm1136"; 996 set_feature(&cpu->env, ARM_FEATURE_V6K); 997 set_feature(&cpu->env, ARM_FEATURE_V6); 998 set_feature(&cpu->env, ARM_FEATURE_VFP); 999 set_feature(&cpu->env, ARM_FEATURE_DUMMY_C15_REGS); 1000 set_feature(&cpu->env, ARM_FEATURE_CACHE_DIRTY_REG); 1001 set_feature(&cpu->env, ARM_FEATURE_CACHE_BLOCK_OPS); 1002 cpu->midr = 0x4117b363; 1003 cpu->reset_fpsid = 0x410120b4; 1004 cpu->mvfr0 = 0x11111111; 1005 cpu->mvfr1 = 0x00000000; 1006 cpu->ctr = 0x1dd20d2; 1007 cpu->reset_sctlr = 0x00050078; 1008 cpu->id_pfr0 = 0x111; 1009 cpu->id_pfr1 = 0x1; 1010 cpu->id_dfr0 = 0x2; 1011 cpu->id_afr0 = 0x3; 1012 cpu->id_mmfr0 = 0x01130003; 1013 cpu->id_mmfr1 = 0x10030302; 1014 cpu->id_mmfr2 = 0x01222110; 1015 cpu->id_isar0 = 0x00140011; 1016 cpu->id_isar1 = 0x12002111; 1017 cpu->id_isar2 = 0x11231111; 1018 cpu->id_isar3 = 0x01102131; 1019 cpu->id_isar4 = 0x141; 1020 cpu->reset_auxcr = 7; 1021 } 1022 1023 static void arm1176_initfn(Object *obj) 1024 { 1025 ARMCPU *cpu = ARM_CPU(obj); 1026 1027 cpu->dtb_compatible = "arm,arm1176"; 1028 set_feature(&cpu->env, ARM_FEATURE_V6K); 1029 set_feature(&cpu->env, ARM_FEATURE_VFP); 1030 set_feature(&cpu->env, ARM_FEATURE_VAPA); 1031 set_feature(&cpu->env, ARM_FEATURE_DUMMY_C15_REGS); 1032 set_feature(&cpu->env, ARM_FEATURE_CACHE_DIRTY_REG); 1033 set_feature(&cpu->env, ARM_FEATURE_CACHE_BLOCK_OPS); 1034 set_feature(&cpu->env, ARM_FEATURE_EL3); 1035 cpu->midr = 0x410fb767; 1036 cpu->reset_fpsid = 0x410120b5; 1037 cpu->mvfr0 = 0x11111111; 1038 cpu->mvfr1 = 0x00000000; 1039 cpu->ctr = 0x1dd20d2; 1040 cpu->reset_sctlr = 0x00050078; 1041 cpu->id_pfr0 = 0x111; 1042 cpu->id_pfr1 = 0x11; 1043 cpu->id_dfr0 = 0x33; 1044 cpu->id_afr0 = 0; 1045 cpu->id_mmfr0 = 0x01130003; 1046 cpu->id_mmfr1 = 0x10030302; 1047 cpu->id_mmfr2 = 0x01222100; 1048 cpu->id_isar0 = 0x0140011; 1049 cpu->id_isar1 = 0x12002111; 1050 cpu->id_isar2 = 0x11231121; 1051 cpu->id_isar3 = 0x01102131; 1052 cpu->id_isar4 = 0x01141; 1053 cpu->reset_auxcr = 7; 1054 } 1055 1056 static void arm11mpcore_initfn(Object *obj) 1057 { 1058 ARMCPU *cpu = ARM_CPU(obj); 1059 1060 cpu->dtb_compatible = "arm,arm11mpcore"; 1061 set_feature(&cpu->env, ARM_FEATURE_V6K); 1062 set_feature(&cpu->env, ARM_FEATURE_VFP); 1063 set_feature(&cpu->env, ARM_FEATURE_VAPA); 1064 set_feature(&cpu->env, ARM_FEATURE_MPIDR); 1065 set_feature(&cpu->env, ARM_FEATURE_DUMMY_C15_REGS); 1066 cpu->midr = 0x410fb022; 1067 cpu->reset_fpsid = 0x410120b4; 1068 cpu->mvfr0 = 0x11111111; 1069 cpu->mvfr1 = 0x00000000; 1070 cpu->ctr = 0x1d192992; /* 32K icache 32K dcache */ 1071 cpu->id_pfr0 = 0x111; 1072 cpu->id_pfr1 = 0x1; 1073 cpu->id_dfr0 = 0; 1074 cpu->id_afr0 = 0x2; 1075 cpu->id_mmfr0 = 0x01100103; 1076 cpu->id_mmfr1 = 0x10020302; 1077 cpu->id_mmfr2 = 0x01222000; 1078 cpu->id_isar0 = 0x00100011; 1079 cpu->id_isar1 = 0x12002111; 1080 cpu->id_isar2 = 0x11221011; 1081 cpu->id_isar3 = 0x01102131; 1082 cpu->id_isar4 = 0x141; 1083 cpu->reset_auxcr = 1; 1084 } 1085 1086 static void cortex_m3_initfn(Object *obj) 1087 { 1088 ARMCPU *cpu = ARM_CPU(obj); 1089 set_feature(&cpu->env, ARM_FEATURE_V7); 1090 set_feature(&cpu->env, ARM_FEATURE_M); 1091 cpu->midr = 0x410fc231; 1092 cpu->pmsav7_dregion = 8; 1093 } 1094 1095 static void cortex_m4_initfn(Object *obj) 1096 { 1097 ARMCPU *cpu = ARM_CPU(obj); 1098 1099 set_feature(&cpu->env, ARM_FEATURE_V7); 1100 set_feature(&cpu->env, ARM_FEATURE_M); 1101 set_feature(&cpu->env, ARM_FEATURE_THUMB_DSP); 1102 cpu->midr = 0x410fc240; /* r0p0 */ 1103 cpu->pmsav7_dregion = 8; 1104 } 1105 static void arm_v7m_class_init(ObjectClass *oc, void *data) 1106 { 1107 CPUClass *cc = CPU_CLASS(oc); 1108 1109 #ifndef CONFIG_USER_ONLY 1110 cc->do_interrupt = arm_v7m_cpu_do_interrupt; 1111 #endif 1112 1113 cc->cpu_exec_interrupt = arm_v7m_cpu_exec_interrupt; 1114 } 1115 1116 static const ARMCPRegInfo cortexr5_cp_reginfo[] = { 1117 /* Dummy the TCM region regs for the moment */ 1118 { .name = "ATCM", .cp = 15, .opc1 = 0, .crn = 9, .crm = 1, .opc2 = 0, 1119 .access = PL1_RW, .type = ARM_CP_CONST }, 1120 { .name = "BTCM", .cp = 15, .opc1 = 0, .crn = 9, .crm = 1, .opc2 = 1, 1121 .access = PL1_RW, .type = ARM_CP_CONST }, 1122 { .name = "DCACHE_INVAL", .cp = 15, .opc1 = 0, .crn = 15, .crm = 5, 1123 .opc2 = 0, .access = PL1_W, .type = ARM_CP_NOP }, 1124 REGINFO_SENTINEL 1125 }; 1126 1127 static void cortex_r5_initfn(Object *obj) 1128 { 1129 ARMCPU *cpu = ARM_CPU(obj); 1130 1131 set_feature(&cpu->env, ARM_FEATURE_V7); 1132 set_feature(&cpu->env, ARM_FEATURE_THUMB_DIV); 1133 set_feature(&cpu->env, ARM_FEATURE_ARM_DIV); 1134 set_feature(&cpu->env, ARM_FEATURE_V7MP); 1135 set_feature(&cpu->env, ARM_FEATURE_PMSA); 1136 cpu->midr = 0x411fc153; /* r1p3 */ 1137 cpu->id_pfr0 = 0x0131; 1138 cpu->id_pfr1 = 0x001; 1139 cpu->id_dfr0 = 0x010400; 1140 cpu->id_afr0 = 0x0; 1141 cpu->id_mmfr0 = 0x0210030; 1142 cpu->id_mmfr1 = 0x00000000; 1143 cpu->id_mmfr2 = 0x01200000; 1144 cpu->id_mmfr3 = 0x0211; 1145 cpu->id_isar0 = 0x2101111; 1146 cpu->id_isar1 = 0x13112111; 1147 cpu->id_isar2 = 0x21232141; 1148 cpu->id_isar3 = 0x01112131; 1149 cpu->id_isar4 = 0x0010142; 1150 cpu->id_isar5 = 0x0; 1151 cpu->mp_is_up = true; 1152 cpu->pmsav7_dregion = 16; 1153 define_arm_cp_regs(cpu, cortexr5_cp_reginfo); 1154 } 1155 1156 static const ARMCPRegInfo cortexa8_cp_reginfo[] = { 1157 { .name = "L2LOCKDOWN", .cp = 15, .crn = 9, .crm = 0, .opc1 = 1, .opc2 = 0, 1158 .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0 }, 1159 { .name = "L2AUXCR", .cp = 15, .crn = 9, .crm = 0, .opc1 = 1, .opc2 = 2, 1160 .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0 }, 1161 REGINFO_SENTINEL 1162 }; 1163 1164 static void cortex_a8_initfn(Object *obj) 1165 { 1166 ARMCPU *cpu = ARM_CPU(obj); 1167 1168 cpu->dtb_compatible = "arm,cortex-a8"; 1169 set_feature(&cpu->env, ARM_FEATURE_V7); 1170 set_feature(&cpu->env, ARM_FEATURE_VFP3); 1171 set_feature(&cpu->env, ARM_FEATURE_NEON); 1172 set_feature(&cpu->env, ARM_FEATURE_THUMB2EE); 1173 set_feature(&cpu->env, ARM_FEATURE_DUMMY_C15_REGS); 1174 set_feature(&cpu->env, ARM_FEATURE_EL3); 1175 cpu->midr = 0x410fc080; 1176 cpu->reset_fpsid = 0x410330c0; 1177 cpu->mvfr0 = 0x11110222; 1178 cpu->mvfr1 = 0x00011111; 1179 cpu->ctr = 0x82048004; 1180 cpu->reset_sctlr = 0x00c50078; 1181 cpu->id_pfr0 = 0x1031; 1182 cpu->id_pfr1 = 0x11; 1183 cpu->id_dfr0 = 0x400; 1184 cpu->id_afr0 = 0; 1185 cpu->id_mmfr0 = 0x31100003; 1186 cpu->id_mmfr1 = 0x20000000; 1187 cpu->id_mmfr2 = 0x01202000; 1188 cpu->id_mmfr3 = 0x11; 1189 cpu->id_isar0 = 0x00101111; 1190 cpu->id_isar1 = 0x12112111; 1191 cpu->id_isar2 = 0x21232031; 1192 cpu->id_isar3 = 0x11112131; 1193 cpu->id_isar4 = 0x00111142; 1194 cpu->dbgdidr = 0x15141000; 1195 cpu->clidr = (1 << 27) | (2 << 24) | 3; 1196 cpu->ccsidr[0] = 0xe007e01a; /* 16k L1 dcache. */ 1197 cpu->ccsidr[1] = 0x2007e01a; /* 16k L1 icache. */ 1198 cpu->ccsidr[2] = 0xf0000000; /* No L2 icache. */ 1199 cpu->reset_auxcr = 2; 1200 define_arm_cp_regs(cpu, cortexa8_cp_reginfo); 1201 } 1202 1203 static const ARMCPRegInfo cortexa9_cp_reginfo[] = { 1204 /* power_control should be set to maximum latency. Again, 1205 * default to 0 and set by private hook 1206 */ 1207 { .name = "A9_PWRCTL", .cp = 15, .crn = 15, .crm = 0, .opc1 = 0, .opc2 = 0, 1208 .access = PL1_RW, .resetvalue = 0, 1209 .fieldoffset = offsetof(CPUARMState, cp15.c15_power_control) }, 1210 { .name = "A9_DIAG", .cp = 15, .crn = 15, .crm = 0, .opc1 = 0, .opc2 = 1, 1211 .access = PL1_RW, .resetvalue = 0, 1212 .fieldoffset = offsetof(CPUARMState, cp15.c15_diagnostic) }, 1213 { .name = "A9_PWRDIAG", .cp = 15, .crn = 15, .crm = 0, .opc1 = 0, .opc2 = 2, 1214 .access = PL1_RW, .resetvalue = 0, 1215 .fieldoffset = offsetof(CPUARMState, cp15.c15_power_diagnostic) }, 1216 { .name = "NEONBUSY", .cp = 15, .crn = 15, .crm = 1, .opc1 = 0, .opc2 = 0, 1217 .access = PL1_RW, .resetvalue = 0, .type = ARM_CP_CONST }, 1218 /* TLB lockdown control */ 1219 { .name = "TLB_LOCKR", .cp = 15, .crn = 15, .crm = 4, .opc1 = 5, .opc2 = 2, 1220 .access = PL1_W, .resetvalue = 0, .type = ARM_CP_NOP }, 1221 { .name = "TLB_LOCKW", .cp = 15, .crn = 15, .crm = 4, .opc1 = 5, .opc2 = 4, 1222 .access = PL1_W, .resetvalue = 0, .type = ARM_CP_NOP }, 1223 { .name = "TLB_VA", .cp = 15, .crn = 15, .crm = 5, .opc1 = 5, .opc2 = 2, 1224 .access = PL1_RW, .resetvalue = 0, .type = ARM_CP_CONST }, 1225 { .name = "TLB_PA", .cp = 15, .crn = 15, .crm = 6, .opc1 = 5, .opc2 = 2, 1226 .access = PL1_RW, .resetvalue = 0, .type = ARM_CP_CONST }, 1227 { .name = "TLB_ATTR", .cp = 15, .crn = 15, .crm = 7, .opc1 = 5, .opc2 = 2, 1228 .access = PL1_RW, .resetvalue = 0, .type = ARM_CP_CONST }, 1229 REGINFO_SENTINEL 1230 }; 1231 1232 static void cortex_a9_initfn(Object *obj) 1233 { 1234 ARMCPU *cpu = ARM_CPU(obj); 1235 1236 cpu->dtb_compatible = "arm,cortex-a9"; 1237 set_feature(&cpu->env, ARM_FEATURE_V7); 1238 set_feature(&cpu->env, ARM_FEATURE_VFP3); 1239 set_feature(&cpu->env, ARM_FEATURE_VFP_FP16); 1240 set_feature(&cpu->env, ARM_FEATURE_NEON); 1241 set_feature(&cpu->env, ARM_FEATURE_THUMB2EE); 1242 set_feature(&cpu->env, ARM_FEATURE_EL3); 1243 /* Note that A9 supports the MP extensions even for 1244 * A9UP and single-core A9MP (which are both different 1245 * and valid configurations; we don't model A9UP). 1246 */ 1247 set_feature(&cpu->env, ARM_FEATURE_V7MP); 1248 set_feature(&cpu->env, ARM_FEATURE_CBAR); 1249 cpu->midr = 0x410fc090; 1250 cpu->reset_fpsid = 0x41033090; 1251 cpu->mvfr0 = 0x11110222; 1252 cpu->mvfr1 = 0x01111111; 1253 cpu->ctr = 0x80038003; 1254 cpu->reset_sctlr = 0x00c50078; 1255 cpu->id_pfr0 = 0x1031; 1256 cpu->id_pfr1 = 0x11; 1257 cpu->id_dfr0 = 0x000; 1258 cpu->id_afr0 = 0; 1259 cpu->id_mmfr0 = 0x00100103; 1260 cpu->id_mmfr1 = 0x20000000; 1261 cpu->id_mmfr2 = 0x01230000; 1262 cpu->id_mmfr3 = 0x00002111; 1263 cpu->id_isar0 = 0x00101111; 1264 cpu->id_isar1 = 0x13112111; 1265 cpu->id_isar2 = 0x21232041; 1266 cpu->id_isar3 = 0x11112131; 1267 cpu->id_isar4 = 0x00111142; 1268 cpu->dbgdidr = 0x35141000; 1269 cpu->clidr = (1 << 27) | (1 << 24) | 3; 1270 cpu->ccsidr[0] = 0xe00fe019; /* 16k L1 dcache. */ 1271 cpu->ccsidr[1] = 0x200fe019; /* 16k L1 icache. */ 1272 define_arm_cp_regs(cpu, cortexa9_cp_reginfo); 1273 } 1274 1275 #ifndef CONFIG_USER_ONLY 1276 static uint64_t a15_l2ctlr_read(CPUARMState *env, const ARMCPRegInfo *ri) 1277 { 1278 /* Linux wants the number of processors from here. 1279 * Might as well set the interrupt-controller bit too. 1280 */ 1281 return ((smp_cpus - 1) << 24) | (1 << 23); 1282 } 1283 #endif 1284 1285 static const ARMCPRegInfo cortexa15_cp_reginfo[] = { 1286 #ifndef CONFIG_USER_ONLY 1287 { .name = "L2CTLR", .cp = 15, .crn = 9, .crm = 0, .opc1 = 1, .opc2 = 2, 1288 .access = PL1_RW, .resetvalue = 0, .readfn = a15_l2ctlr_read, 1289 .writefn = arm_cp_write_ignore, }, 1290 #endif 1291 { .name = "L2ECTLR", .cp = 15, .crn = 9, .crm = 0, .opc1 = 1, .opc2 = 3, 1292 .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0 }, 1293 REGINFO_SENTINEL 1294 }; 1295 1296 static void cortex_a7_initfn(Object *obj) 1297 { 1298 ARMCPU *cpu = ARM_CPU(obj); 1299 1300 cpu->dtb_compatible = "arm,cortex-a7"; 1301 set_feature(&cpu->env, ARM_FEATURE_V7); 1302 set_feature(&cpu->env, ARM_FEATURE_VFP4); 1303 set_feature(&cpu->env, ARM_FEATURE_NEON); 1304 set_feature(&cpu->env, ARM_FEATURE_THUMB2EE); 1305 set_feature(&cpu->env, ARM_FEATURE_ARM_DIV); 1306 set_feature(&cpu->env, ARM_FEATURE_GENERIC_TIMER); 1307 set_feature(&cpu->env, ARM_FEATURE_DUMMY_C15_REGS); 1308 set_feature(&cpu->env, ARM_FEATURE_CBAR_RO); 1309 set_feature(&cpu->env, ARM_FEATURE_LPAE); 1310 set_feature(&cpu->env, ARM_FEATURE_EL3); 1311 cpu->kvm_target = QEMU_KVM_ARM_TARGET_CORTEX_A7; 1312 cpu->midr = 0x410fc075; 1313 cpu->reset_fpsid = 0x41023075; 1314 cpu->mvfr0 = 0x10110222; 1315 cpu->mvfr1 = 0x11111111; 1316 cpu->ctr = 0x84448003; 1317 cpu->reset_sctlr = 0x00c50078; 1318 cpu->id_pfr0 = 0x00001131; 1319 cpu->id_pfr1 = 0x00011011; 1320 cpu->id_dfr0 = 0x02010555; 1321 cpu->pmceid0 = 0x00000000; 1322 cpu->pmceid1 = 0x00000000; 1323 cpu->id_afr0 = 0x00000000; 1324 cpu->id_mmfr0 = 0x10101105; 1325 cpu->id_mmfr1 = 0x40000000; 1326 cpu->id_mmfr2 = 0x01240000; 1327 cpu->id_mmfr3 = 0x02102211; 1328 cpu->id_isar0 = 0x01101110; 1329 cpu->id_isar1 = 0x13112111; 1330 cpu->id_isar2 = 0x21232041; 1331 cpu->id_isar3 = 0x11112131; 1332 cpu->id_isar4 = 0x10011142; 1333 cpu->dbgdidr = 0x3515f005; 1334 cpu->clidr = 0x0a200023; 1335 cpu->ccsidr[0] = 0x701fe00a; /* 32K L1 dcache */ 1336 cpu->ccsidr[1] = 0x201fe00a; /* 32K L1 icache */ 1337 cpu->ccsidr[2] = 0x711fe07a; /* 4096K L2 unified cache */ 1338 define_arm_cp_regs(cpu, cortexa15_cp_reginfo); /* Same as A15 */ 1339 } 1340 1341 static void cortex_a15_initfn(Object *obj) 1342 { 1343 ARMCPU *cpu = ARM_CPU(obj); 1344 1345 cpu->dtb_compatible = "arm,cortex-a15"; 1346 set_feature(&cpu->env, ARM_FEATURE_V7); 1347 set_feature(&cpu->env, ARM_FEATURE_VFP4); 1348 set_feature(&cpu->env, ARM_FEATURE_NEON); 1349 set_feature(&cpu->env, ARM_FEATURE_THUMB2EE); 1350 set_feature(&cpu->env, ARM_FEATURE_ARM_DIV); 1351 set_feature(&cpu->env, ARM_FEATURE_GENERIC_TIMER); 1352 set_feature(&cpu->env, ARM_FEATURE_DUMMY_C15_REGS); 1353 set_feature(&cpu->env, ARM_FEATURE_CBAR_RO); 1354 set_feature(&cpu->env, ARM_FEATURE_LPAE); 1355 set_feature(&cpu->env, ARM_FEATURE_EL3); 1356 cpu->kvm_target = QEMU_KVM_ARM_TARGET_CORTEX_A15; 1357 cpu->midr = 0x412fc0f1; 1358 cpu->reset_fpsid = 0x410430f0; 1359 cpu->mvfr0 = 0x10110222; 1360 cpu->mvfr1 = 0x11111111; 1361 cpu->ctr = 0x8444c004; 1362 cpu->reset_sctlr = 0x00c50078; 1363 cpu->id_pfr0 = 0x00001131; 1364 cpu->id_pfr1 = 0x00011011; 1365 cpu->id_dfr0 = 0x02010555; 1366 cpu->pmceid0 = 0x0000000; 1367 cpu->pmceid1 = 0x00000000; 1368 cpu->id_afr0 = 0x00000000; 1369 cpu->id_mmfr0 = 0x10201105; 1370 cpu->id_mmfr1 = 0x20000000; 1371 cpu->id_mmfr2 = 0x01240000; 1372 cpu->id_mmfr3 = 0x02102211; 1373 cpu->id_isar0 = 0x02101110; 1374 cpu->id_isar1 = 0x13112111; 1375 cpu->id_isar2 = 0x21232041; 1376 cpu->id_isar3 = 0x11112131; 1377 cpu->id_isar4 = 0x10011142; 1378 cpu->dbgdidr = 0x3515f021; 1379 cpu->clidr = 0x0a200023; 1380 cpu->ccsidr[0] = 0x701fe00a; /* 32K L1 dcache */ 1381 cpu->ccsidr[1] = 0x201fe00a; /* 32K L1 icache */ 1382 cpu->ccsidr[2] = 0x711fe07a; /* 4096K L2 unified cache */ 1383 define_arm_cp_regs(cpu, cortexa15_cp_reginfo); 1384 } 1385 1386 static void ti925t_initfn(Object *obj) 1387 { 1388 ARMCPU *cpu = ARM_CPU(obj); 1389 set_feature(&cpu->env, ARM_FEATURE_V4T); 1390 set_feature(&cpu->env, ARM_FEATURE_OMAPCP); 1391 cpu->midr = ARM_CPUID_TI925T; 1392 cpu->ctr = 0x5109149; 1393 cpu->reset_sctlr = 0x00000070; 1394 } 1395 1396 static void sa1100_initfn(Object *obj) 1397 { 1398 ARMCPU *cpu = ARM_CPU(obj); 1399 1400 cpu->dtb_compatible = "intel,sa1100"; 1401 set_feature(&cpu->env, ARM_FEATURE_STRONGARM); 1402 set_feature(&cpu->env, ARM_FEATURE_DUMMY_C15_REGS); 1403 cpu->midr = 0x4401A11B; 1404 cpu->reset_sctlr = 0x00000070; 1405 } 1406 1407 static void sa1110_initfn(Object *obj) 1408 { 1409 ARMCPU *cpu = ARM_CPU(obj); 1410 set_feature(&cpu->env, ARM_FEATURE_STRONGARM); 1411 set_feature(&cpu->env, ARM_FEATURE_DUMMY_C15_REGS); 1412 cpu->midr = 0x6901B119; 1413 cpu->reset_sctlr = 0x00000070; 1414 } 1415 1416 static void pxa250_initfn(Object *obj) 1417 { 1418 ARMCPU *cpu = ARM_CPU(obj); 1419 1420 cpu->dtb_compatible = "marvell,xscale"; 1421 set_feature(&cpu->env, ARM_FEATURE_V5); 1422 set_feature(&cpu->env, ARM_FEATURE_XSCALE); 1423 cpu->midr = 0x69052100; 1424 cpu->ctr = 0xd172172; 1425 cpu->reset_sctlr = 0x00000078; 1426 } 1427 1428 static void pxa255_initfn(Object *obj) 1429 { 1430 ARMCPU *cpu = ARM_CPU(obj); 1431 1432 cpu->dtb_compatible = "marvell,xscale"; 1433 set_feature(&cpu->env, ARM_FEATURE_V5); 1434 set_feature(&cpu->env, ARM_FEATURE_XSCALE); 1435 cpu->midr = 0x69052d00; 1436 cpu->ctr = 0xd172172; 1437 cpu->reset_sctlr = 0x00000078; 1438 } 1439 1440 static void pxa260_initfn(Object *obj) 1441 { 1442 ARMCPU *cpu = ARM_CPU(obj); 1443 1444 cpu->dtb_compatible = "marvell,xscale"; 1445 set_feature(&cpu->env, ARM_FEATURE_V5); 1446 set_feature(&cpu->env, ARM_FEATURE_XSCALE); 1447 cpu->midr = 0x69052903; 1448 cpu->ctr = 0xd172172; 1449 cpu->reset_sctlr = 0x00000078; 1450 } 1451 1452 static void pxa261_initfn(Object *obj) 1453 { 1454 ARMCPU *cpu = ARM_CPU(obj); 1455 1456 cpu->dtb_compatible = "marvell,xscale"; 1457 set_feature(&cpu->env, ARM_FEATURE_V5); 1458 set_feature(&cpu->env, ARM_FEATURE_XSCALE); 1459 cpu->midr = 0x69052d05; 1460 cpu->ctr = 0xd172172; 1461 cpu->reset_sctlr = 0x00000078; 1462 } 1463 1464 static void pxa262_initfn(Object *obj) 1465 { 1466 ARMCPU *cpu = ARM_CPU(obj); 1467 1468 cpu->dtb_compatible = "marvell,xscale"; 1469 set_feature(&cpu->env, ARM_FEATURE_V5); 1470 set_feature(&cpu->env, ARM_FEATURE_XSCALE); 1471 cpu->midr = 0x69052d06; 1472 cpu->ctr = 0xd172172; 1473 cpu->reset_sctlr = 0x00000078; 1474 } 1475 1476 static void pxa270a0_initfn(Object *obj) 1477 { 1478 ARMCPU *cpu = ARM_CPU(obj); 1479 1480 cpu->dtb_compatible = "marvell,xscale"; 1481 set_feature(&cpu->env, ARM_FEATURE_V5); 1482 set_feature(&cpu->env, ARM_FEATURE_XSCALE); 1483 set_feature(&cpu->env, ARM_FEATURE_IWMMXT); 1484 cpu->midr = 0x69054110; 1485 cpu->ctr = 0xd172172; 1486 cpu->reset_sctlr = 0x00000078; 1487 } 1488 1489 static void pxa270a1_initfn(Object *obj) 1490 { 1491 ARMCPU *cpu = ARM_CPU(obj); 1492 1493 cpu->dtb_compatible = "marvell,xscale"; 1494 set_feature(&cpu->env, ARM_FEATURE_V5); 1495 set_feature(&cpu->env, ARM_FEATURE_XSCALE); 1496 set_feature(&cpu->env, ARM_FEATURE_IWMMXT); 1497 cpu->midr = 0x69054111; 1498 cpu->ctr = 0xd172172; 1499 cpu->reset_sctlr = 0x00000078; 1500 } 1501 1502 static void pxa270b0_initfn(Object *obj) 1503 { 1504 ARMCPU *cpu = ARM_CPU(obj); 1505 1506 cpu->dtb_compatible = "marvell,xscale"; 1507 set_feature(&cpu->env, ARM_FEATURE_V5); 1508 set_feature(&cpu->env, ARM_FEATURE_XSCALE); 1509 set_feature(&cpu->env, ARM_FEATURE_IWMMXT); 1510 cpu->midr = 0x69054112; 1511 cpu->ctr = 0xd172172; 1512 cpu->reset_sctlr = 0x00000078; 1513 } 1514 1515 static void pxa270b1_initfn(Object *obj) 1516 { 1517 ARMCPU *cpu = ARM_CPU(obj); 1518 1519 cpu->dtb_compatible = "marvell,xscale"; 1520 set_feature(&cpu->env, ARM_FEATURE_V5); 1521 set_feature(&cpu->env, ARM_FEATURE_XSCALE); 1522 set_feature(&cpu->env, ARM_FEATURE_IWMMXT); 1523 cpu->midr = 0x69054113; 1524 cpu->ctr = 0xd172172; 1525 cpu->reset_sctlr = 0x00000078; 1526 } 1527 1528 static void pxa270c0_initfn(Object *obj) 1529 { 1530 ARMCPU *cpu = ARM_CPU(obj); 1531 1532 cpu->dtb_compatible = "marvell,xscale"; 1533 set_feature(&cpu->env, ARM_FEATURE_V5); 1534 set_feature(&cpu->env, ARM_FEATURE_XSCALE); 1535 set_feature(&cpu->env, ARM_FEATURE_IWMMXT); 1536 cpu->midr = 0x69054114; 1537 cpu->ctr = 0xd172172; 1538 cpu->reset_sctlr = 0x00000078; 1539 } 1540 1541 static void pxa270c5_initfn(Object *obj) 1542 { 1543 ARMCPU *cpu = ARM_CPU(obj); 1544 1545 cpu->dtb_compatible = "marvell,xscale"; 1546 set_feature(&cpu->env, ARM_FEATURE_V5); 1547 set_feature(&cpu->env, ARM_FEATURE_XSCALE); 1548 set_feature(&cpu->env, ARM_FEATURE_IWMMXT); 1549 cpu->midr = 0x69054117; 1550 cpu->ctr = 0xd172172; 1551 cpu->reset_sctlr = 0x00000078; 1552 } 1553 1554 #ifdef CONFIG_USER_ONLY 1555 static void arm_any_initfn(Object *obj) 1556 { 1557 ARMCPU *cpu = ARM_CPU(obj); 1558 set_feature(&cpu->env, ARM_FEATURE_V8); 1559 set_feature(&cpu->env, ARM_FEATURE_VFP4); 1560 set_feature(&cpu->env, ARM_FEATURE_NEON); 1561 set_feature(&cpu->env, ARM_FEATURE_THUMB2EE); 1562 set_feature(&cpu->env, ARM_FEATURE_V8_AES); 1563 set_feature(&cpu->env, ARM_FEATURE_V8_SHA1); 1564 set_feature(&cpu->env, ARM_FEATURE_V8_SHA256); 1565 set_feature(&cpu->env, ARM_FEATURE_V8_PMULL); 1566 set_feature(&cpu->env, ARM_FEATURE_CRC); 1567 cpu->midr = 0xffffffff; 1568 } 1569 #endif 1570 1571 #endif /* !defined(CONFIG_USER_ONLY) || !defined(TARGET_AARCH64) */ 1572 1573 typedef struct ARMCPUInfo { 1574 const char *name; 1575 void (*initfn)(Object *obj); 1576 void (*class_init)(ObjectClass *oc, void *data); 1577 } ARMCPUInfo; 1578 1579 static const ARMCPUInfo arm_cpus[] = { 1580 #if !defined(CONFIG_USER_ONLY) || !defined(TARGET_AARCH64) 1581 { .name = "arm926", .initfn = arm926_initfn }, 1582 { .name = "arm946", .initfn = arm946_initfn }, 1583 { .name = "arm1026", .initfn = arm1026_initfn }, 1584 /* What QEMU calls "arm1136-r2" is actually the 1136 r0p2, i.e. an 1585 * older core than plain "arm1136". In particular this does not 1586 * have the v6K features. 1587 */ 1588 { .name = "arm1136-r2", .initfn = arm1136_r2_initfn }, 1589 { .name = "arm1136", .initfn = arm1136_initfn }, 1590 { .name = "arm1176", .initfn = arm1176_initfn }, 1591 { .name = "arm11mpcore", .initfn = arm11mpcore_initfn }, 1592 { .name = "cortex-m3", .initfn = cortex_m3_initfn, 1593 .class_init = arm_v7m_class_init }, 1594 { .name = "cortex-m4", .initfn = cortex_m4_initfn, 1595 .class_init = arm_v7m_class_init }, 1596 { .name = "cortex-r5", .initfn = cortex_r5_initfn }, 1597 { .name = "cortex-a7", .initfn = cortex_a7_initfn }, 1598 { .name = "cortex-a8", .initfn = cortex_a8_initfn }, 1599 { .name = "cortex-a9", .initfn = cortex_a9_initfn }, 1600 { .name = "cortex-a15", .initfn = cortex_a15_initfn }, 1601 { .name = "ti925t", .initfn = ti925t_initfn }, 1602 { .name = "sa1100", .initfn = sa1100_initfn }, 1603 { .name = "sa1110", .initfn = sa1110_initfn }, 1604 { .name = "pxa250", .initfn = pxa250_initfn }, 1605 { .name = "pxa255", .initfn = pxa255_initfn }, 1606 { .name = "pxa260", .initfn = pxa260_initfn }, 1607 { .name = "pxa261", .initfn = pxa261_initfn }, 1608 { .name = "pxa262", .initfn = pxa262_initfn }, 1609 /* "pxa270" is an alias for "pxa270-a0" */ 1610 { .name = "pxa270", .initfn = pxa270a0_initfn }, 1611 { .name = "pxa270-a0", .initfn = pxa270a0_initfn }, 1612 { .name = "pxa270-a1", .initfn = pxa270a1_initfn }, 1613 { .name = "pxa270-b0", .initfn = pxa270b0_initfn }, 1614 { .name = "pxa270-b1", .initfn = pxa270b1_initfn }, 1615 { .name = "pxa270-c0", .initfn = pxa270c0_initfn }, 1616 { .name = "pxa270-c5", .initfn = pxa270c5_initfn }, 1617 #ifdef CONFIG_USER_ONLY 1618 { .name = "any", .initfn = arm_any_initfn }, 1619 #endif 1620 #endif 1621 { .name = NULL } 1622 }; 1623 1624 static Property arm_cpu_properties[] = { 1625 DEFINE_PROP_BOOL("start-powered-off", ARMCPU, start_powered_off, false), 1626 DEFINE_PROP_UINT32("psci-conduit", ARMCPU, psci_conduit, 0), 1627 DEFINE_PROP_UINT32("midr", ARMCPU, midr, 0), 1628 DEFINE_PROP_UINT64("mp-affinity", ARMCPU, 1629 mp_affinity, ARM64_AFFINITY_INVALID), 1630 DEFINE_PROP_INT32("node-id", ARMCPU, node_id, CPU_UNSET_NUMA_NODE_ID), 1631 DEFINE_PROP_END_OF_LIST() 1632 }; 1633 1634 #ifdef CONFIG_USER_ONLY 1635 static int arm_cpu_handle_mmu_fault(CPUState *cs, vaddr address, int rw, 1636 int mmu_idx) 1637 { 1638 ARMCPU *cpu = ARM_CPU(cs); 1639 CPUARMState *env = &cpu->env; 1640 1641 env->exception.vaddress = address; 1642 if (rw == 2) { 1643 cs->exception_index = EXCP_PREFETCH_ABORT; 1644 } else { 1645 cs->exception_index = EXCP_DATA_ABORT; 1646 } 1647 return 1; 1648 } 1649 #endif 1650 1651 static gchar *arm_gdb_arch_name(CPUState *cs) 1652 { 1653 ARMCPU *cpu = ARM_CPU(cs); 1654 CPUARMState *env = &cpu->env; 1655 1656 if (arm_feature(env, ARM_FEATURE_IWMMXT)) { 1657 return g_strdup("iwmmxt"); 1658 } 1659 return g_strdup("arm"); 1660 } 1661 1662 static void arm_cpu_class_init(ObjectClass *oc, void *data) 1663 { 1664 ARMCPUClass *acc = ARM_CPU_CLASS(oc); 1665 CPUClass *cc = CPU_CLASS(acc); 1666 DeviceClass *dc = DEVICE_CLASS(oc); 1667 1668 acc->parent_realize = dc->realize; 1669 dc->realize = arm_cpu_realizefn; 1670 dc->props = arm_cpu_properties; 1671 1672 acc->parent_reset = cc->reset; 1673 cc->reset = arm_cpu_reset; 1674 1675 cc->class_by_name = arm_cpu_class_by_name; 1676 cc->has_work = arm_cpu_has_work; 1677 cc->cpu_exec_interrupt = arm_cpu_exec_interrupt; 1678 cc->dump_state = arm_cpu_dump_state; 1679 cc->set_pc = arm_cpu_set_pc; 1680 cc->gdb_read_register = arm_cpu_gdb_read_register; 1681 cc->gdb_write_register = arm_cpu_gdb_write_register; 1682 #ifdef CONFIG_USER_ONLY 1683 cc->handle_mmu_fault = arm_cpu_handle_mmu_fault; 1684 #else 1685 cc->do_interrupt = arm_cpu_do_interrupt; 1686 cc->do_unaligned_access = arm_cpu_do_unaligned_access; 1687 cc->get_phys_page_attrs_debug = arm_cpu_get_phys_page_attrs_debug; 1688 cc->asidx_from_attrs = arm_asidx_from_attrs; 1689 cc->vmsd = &vmstate_arm_cpu; 1690 cc->virtio_is_big_endian = arm_cpu_virtio_is_big_endian; 1691 cc->write_elf64_note = arm_cpu_write_elf64_note; 1692 cc->write_elf32_note = arm_cpu_write_elf32_note; 1693 #endif 1694 cc->gdb_num_core_regs = 26; 1695 cc->gdb_core_xml_file = "arm-core.xml"; 1696 cc->gdb_arch_name = arm_gdb_arch_name; 1697 cc->gdb_stop_before_watchpoint = true; 1698 cc->debug_excp_handler = arm_debug_excp_handler; 1699 cc->debug_check_watchpoint = arm_debug_check_watchpoint; 1700 #if !defined(CONFIG_USER_ONLY) 1701 cc->adjust_watchpoint_address = arm_adjust_watchpoint_address; 1702 #endif 1703 1704 cc->disas_set_info = arm_disas_set_info; 1705 } 1706 1707 static void cpu_register(const ARMCPUInfo *info) 1708 { 1709 TypeInfo type_info = { 1710 .parent = TYPE_ARM_CPU, 1711 .instance_size = sizeof(ARMCPU), 1712 .instance_init = info->initfn, 1713 .class_size = sizeof(ARMCPUClass), 1714 .class_init = info->class_init, 1715 }; 1716 1717 type_info.name = g_strdup_printf("%s-" TYPE_ARM_CPU, info->name); 1718 type_register(&type_info); 1719 g_free((void *)type_info.name); 1720 } 1721 1722 static const TypeInfo arm_cpu_type_info = { 1723 .name = TYPE_ARM_CPU, 1724 .parent = TYPE_CPU, 1725 .instance_size = sizeof(ARMCPU), 1726 .instance_init = arm_cpu_initfn, 1727 .instance_post_init = arm_cpu_post_init, 1728 .instance_finalize = arm_cpu_finalizefn, 1729 .abstract = true, 1730 .class_size = sizeof(ARMCPUClass), 1731 .class_init = arm_cpu_class_init, 1732 }; 1733 1734 static void arm_cpu_register_types(void) 1735 { 1736 const ARMCPUInfo *info = arm_cpus; 1737 1738 type_register_static(&arm_cpu_type_info); 1739 1740 while (info->name) { 1741 cpu_register(info); 1742 info++; 1743 } 1744 } 1745 1746 type_init(arm_cpu_register_types) 1747