1 /* 2 * QEMU ARM CPU 3 * 4 * Copyright (c) 2012 SUSE LINUX Products GmbH 5 * 6 * This program is free software; you can redistribute it and/or 7 * modify it under the terms of the GNU General Public License 8 * as published by the Free Software Foundation; either version 2 9 * of the License, or (at your option) any later version. 10 * 11 * This program is distributed in the hope that it will be useful, 12 * but WITHOUT ANY WARRANTY; without even the implied warranty of 13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 14 * GNU General Public License for more details. 15 * 16 * You should have received a copy of the GNU General Public License 17 * along with this program; if not, see 18 * <http://www.gnu.org/licenses/gpl-2.0.html> 19 */ 20 21 #include "qemu/osdep.h" 22 #include "qemu/qemu-print.h" 23 #include "qemu/timer.h" 24 #include "qemu/log.h" 25 #include "exec/page-vary.h" 26 #include "target/arm/idau.h" 27 #include "qemu/module.h" 28 #include "qapi/error.h" 29 #include "qapi/visitor.h" 30 #include "cpu.h" 31 #ifdef CONFIG_TCG 32 #include "hw/core/tcg-cpu-ops.h" 33 #endif /* CONFIG_TCG */ 34 #include "internals.h" 35 #include "exec/exec-all.h" 36 #include "hw/qdev-properties.h" 37 #if !defined(CONFIG_USER_ONLY) 38 #include "hw/loader.h" 39 #include "hw/boards.h" 40 #endif 41 #include "sysemu/tcg.h" 42 #include "sysemu/qtest.h" 43 #include "sysemu/hw_accel.h" 44 #include "kvm_arm.h" 45 #include "disas/capstone.h" 46 #include "fpu/softfloat.h" 47 #include "cpregs.h" 48 49 static void arm_cpu_set_pc(CPUState *cs, vaddr value) 50 { 51 ARMCPU *cpu = ARM_CPU(cs); 52 CPUARMState *env = &cpu->env; 53 54 if (is_a64(env)) { 55 env->pc = value; 56 env->thumb = false; 57 } else { 58 env->regs[15] = value & ~1; 59 env->thumb = value & 1; 60 } 61 } 62 63 #ifdef CONFIG_TCG 64 void arm_cpu_synchronize_from_tb(CPUState *cs, 65 const TranslationBlock *tb) 66 { 67 ARMCPU *cpu = ARM_CPU(cs); 68 CPUARMState *env = &cpu->env; 69 70 /* 71 * It's OK to look at env for the current mode here, because it's 72 * never possible for an AArch64 TB to chain to an AArch32 TB. 73 */ 74 if (is_a64(env)) { 75 env->pc = tb->pc; 76 } else { 77 env->regs[15] = tb->pc; 78 } 79 } 80 #endif /* CONFIG_TCG */ 81 82 static bool arm_cpu_has_work(CPUState *cs) 83 { 84 ARMCPU *cpu = ARM_CPU(cs); 85 86 return (cpu->power_state != PSCI_OFF) 87 && cs->interrupt_request & 88 (CPU_INTERRUPT_FIQ | CPU_INTERRUPT_HARD 89 | CPU_INTERRUPT_VFIQ | CPU_INTERRUPT_VIRQ | CPU_INTERRUPT_VSERR 90 | CPU_INTERRUPT_EXITTB); 91 } 92 93 void arm_register_pre_el_change_hook(ARMCPU *cpu, ARMELChangeHookFn *hook, 94 void *opaque) 95 { 96 ARMELChangeHook *entry = g_new0(ARMELChangeHook, 1); 97 98 entry->hook = hook; 99 entry->opaque = opaque; 100 101 QLIST_INSERT_HEAD(&cpu->pre_el_change_hooks, entry, node); 102 } 103 104 void arm_register_el_change_hook(ARMCPU *cpu, ARMELChangeHookFn *hook, 105 void *opaque) 106 { 107 ARMELChangeHook *entry = g_new0(ARMELChangeHook, 1); 108 109 entry->hook = hook; 110 entry->opaque = opaque; 111 112 QLIST_INSERT_HEAD(&cpu->el_change_hooks, entry, node); 113 } 114 115 static void cp_reg_reset(gpointer key, gpointer value, gpointer opaque) 116 { 117 /* Reset a single ARMCPRegInfo register */ 118 ARMCPRegInfo *ri = value; 119 ARMCPU *cpu = opaque; 120 121 if (ri->type & (ARM_CP_SPECIAL_MASK | ARM_CP_ALIAS)) { 122 return; 123 } 124 125 if (ri->resetfn) { 126 ri->resetfn(&cpu->env, ri); 127 return; 128 } 129 130 /* A zero offset is never possible as it would be regs[0] 131 * so we use it to indicate that reset is being handled elsewhere. 132 * This is basically only used for fields in non-core coprocessors 133 * (like the pxa2xx ones). 134 */ 135 if (!ri->fieldoffset) { 136 return; 137 } 138 139 if (cpreg_field_is_64bit(ri)) { 140 CPREG_FIELD64(&cpu->env, ri) = ri->resetvalue; 141 } else { 142 CPREG_FIELD32(&cpu->env, ri) = ri->resetvalue; 143 } 144 } 145 146 static void cp_reg_check_reset(gpointer key, gpointer value, gpointer opaque) 147 { 148 /* Purely an assertion check: we've already done reset once, 149 * so now check that running the reset for the cpreg doesn't 150 * change its value. This traps bugs where two different cpregs 151 * both try to reset the same state field but to different values. 152 */ 153 ARMCPRegInfo *ri = value; 154 ARMCPU *cpu = opaque; 155 uint64_t oldvalue, newvalue; 156 157 if (ri->type & (ARM_CP_SPECIAL_MASK | ARM_CP_ALIAS | ARM_CP_NO_RAW)) { 158 return; 159 } 160 161 oldvalue = read_raw_cp_reg(&cpu->env, ri); 162 cp_reg_reset(key, value, opaque); 163 newvalue = read_raw_cp_reg(&cpu->env, ri); 164 assert(oldvalue == newvalue); 165 } 166 167 static void arm_cpu_reset(DeviceState *dev) 168 { 169 CPUState *s = CPU(dev); 170 ARMCPU *cpu = ARM_CPU(s); 171 ARMCPUClass *acc = ARM_CPU_GET_CLASS(cpu); 172 CPUARMState *env = &cpu->env; 173 174 acc->parent_reset(dev); 175 176 memset(env, 0, offsetof(CPUARMState, end_reset_fields)); 177 178 g_hash_table_foreach(cpu->cp_regs, cp_reg_reset, cpu); 179 g_hash_table_foreach(cpu->cp_regs, cp_reg_check_reset, cpu); 180 181 env->vfp.xregs[ARM_VFP_FPSID] = cpu->reset_fpsid; 182 env->vfp.xregs[ARM_VFP_MVFR0] = cpu->isar.mvfr0; 183 env->vfp.xregs[ARM_VFP_MVFR1] = cpu->isar.mvfr1; 184 env->vfp.xregs[ARM_VFP_MVFR2] = cpu->isar.mvfr2; 185 186 cpu->power_state = s->start_powered_off ? PSCI_OFF : PSCI_ON; 187 188 if (arm_feature(env, ARM_FEATURE_IWMMXT)) { 189 env->iwmmxt.cregs[ARM_IWMMXT_wCID] = 0x69051000 | 'Q'; 190 } 191 192 if (arm_feature(env, ARM_FEATURE_AARCH64)) { 193 /* 64 bit CPUs always start in 64 bit mode */ 194 env->aarch64 = true; 195 #if defined(CONFIG_USER_ONLY) 196 env->pstate = PSTATE_MODE_EL0t; 197 /* Userspace expects access to DC ZVA, CTL_EL0 and the cache ops */ 198 env->cp15.sctlr_el[1] |= SCTLR_UCT | SCTLR_UCI | SCTLR_DZE; 199 /* Enable all PAC keys. */ 200 env->cp15.sctlr_el[1] |= (SCTLR_EnIA | SCTLR_EnIB | 201 SCTLR_EnDA | SCTLR_EnDB); 202 /* Trap on btype=3 for PACIxSP. */ 203 env->cp15.sctlr_el[1] |= SCTLR_BT0; 204 /* and to the FP/Neon instructions */ 205 env->cp15.cpacr_el1 = FIELD_DP64(env->cp15.cpacr_el1, 206 CPACR_EL1, FPEN, 3); 207 /* and to the SVE instructions */ 208 env->cp15.cpacr_el1 = FIELD_DP64(env->cp15.cpacr_el1, 209 CPACR_EL1, ZEN, 3); 210 /* with reasonable vector length */ 211 if (cpu_isar_feature(aa64_sve, cpu)) { 212 env->vfp.zcr_el[1] = cpu->sve_default_vq - 1; 213 } 214 /* 215 * Enable 48-bit address space (TODO: take reserved_va into account). 216 * Enable TBI0 but not TBI1. 217 * Note that this must match useronly_clean_ptr. 218 */ 219 env->cp15.tcr_el[1].raw_tcr = 5 | (1ULL << 37); 220 221 /* Enable MTE */ 222 if (cpu_isar_feature(aa64_mte, cpu)) { 223 /* Enable tag access, but leave TCF0 as No Effect (0). */ 224 env->cp15.sctlr_el[1] |= SCTLR_ATA0; 225 /* 226 * Exclude all tags, so that tag 0 is always used. 227 * This corresponds to Linux current->thread.gcr_incl = 0. 228 * 229 * Set RRND, so that helper_irg() will generate a seed later. 230 * Here in cpu_reset(), the crypto subsystem has not yet been 231 * initialized. 232 */ 233 env->cp15.gcr_el1 = 0x1ffff; 234 } 235 /* 236 * Disable access to SCXTNUM_EL0 from CSV2_1p2. 237 * This is not yet exposed from the Linux kernel in any way. 238 */ 239 env->cp15.sctlr_el[1] |= SCTLR_TSCXT; 240 #else 241 /* Reset into the highest available EL */ 242 if (arm_feature(env, ARM_FEATURE_EL3)) { 243 env->pstate = PSTATE_MODE_EL3h; 244 } else if (arm_feature(env, ARM_FEATURE_EL2)) { 245 env->pstate = PSTATE_MODE_EL2h; 246 } else { 247 env->pstate = PSTATE_MODE_EL1h; 248 } 249 250 /* Sample rvbar at reset. */ 251 env->cp15.rvbar = cpu->rvbar_prop; 252 env->pc = env->cp15.rvbar; 253 #endif 254 } else { 255 #if defined(CONFIG_USER_ONLY) 256 /* Userspace expects access to cp10 and cp11 for FP/Neon */ 257 env->cp15.cpacr_el1 = FIELD_DP64(env->cp15.cpacr_el1, 258 CPACR, CP10, 3); 259 env->cp15.cpacr_el1 = FIELD_DP64(env->cp15.cpacr_el1, 260 CPACR, CP11, 3); 261 #endif 262 } 263 264 #if defined(CONFIG_USER_ONLY) 265 env->uncached_cpsr = ARM_CPU_MODE_USR; 266 /* For user mode we must enable access to coprocessors */ 267 env->vfp.xregs[ARM_VFP_FPEXC] = 1 << 30; 268 if (arm_feature(env, ARM_FEATURE_IWMMXT)) { 269 env->cp15.c15_cpar = 3; 270 } else if (arm_feature(env, ARM_FEATURE_XSCALE)) { 271 env->cp15.c15_cpar = 1; 272 } 273 #else 274 275 /* 276 * If the highest available EL is EL2, AArch32 will start in Hyp 277 * mode; otherwise it starts in SVC. Note that if we start in 278 * AArch64 then these values in the uncached_cpsr will be ignored. 279 */ 280 if (arm_feature(env, ARM_FEATURE_EL2) && 281 !arm_feature(env, ARM_FEATURE_EL3)) { 282 env->uncached_cpsr = ARM_CPU_MODE_HYP; 283 } else { 284 env->uncached_cpsr = ARM_CPU_MODE_SVC; 285 } 286 env->daif = PSTATE_D | PSTATE_A | PSTATE_I | PSTATE_F; 287 288 /* AArch32 has a hard highvec setting of 0xFFFF0000. If we are currently 289 * executing as AArch32 then check if highvecs are enabled and 290 * adjust the PC accordingly. 291 */ 292 if (A32_BANKED_CURRENT_REG_GET(env, sctlr) & SCTLR_V) { 293 env->regs[15] = 0xFFFF0000; 294 } 295 296 env->vfp.xregs[ARM_VFP_FPEXC] = 0; 297 #endif 298 299 if (arm_feature(env, ARM_FEATURE_M)) { 300 #ifndef CONFIG_USER_ONLY 301 uint32_t initial_msp; /* Loaded from 0x0 */ 302 uint32_t initial_pc; /* Loaded from 0x4 */ 303 uint8_t *rom; 304 uint32_t vecbase; 305 #endif 306 307 if (cpu_isar_feature(aa32_lob, cpu)) { 308 /* 309 * LTPSIZE is constant 4 if MVE not implemented, and resets 310 * to an UNKNOWN value if MVE is implemented. We choose to 311 * always reset to 4. 312 */ 313 env->v7m.ltpsize = 4; 314 /* The LTPSIZE field in FPDSCR is constant and reads as 4. */ 315 env->v7m.fpdscr[M_REG_NS] = 4 << FPCR_LTPSIZE_SHIFT; 316 env->v7m.fpdscr[M_REG_S] = 4 << FPCR_LTPSIZE_SHIFT; 317 } 318 319 if (arm_feature(env, ARM_FEATURE_M_SECURITY)) { 320 env->v7m.secure = true; 321 } else { 322 /* This bit resets to 0 if security is supported, but 1 if 323 * it is not. The bit is not present in v7M, but we set it 324 * here so we can avoid having to make checks on it conditional 325 * on ARM_FEATURE_V8 (we don't let the guest see the bit). 326 */ 327 env->v7m.aircr = R_V7M_AIRCR_BFHFNMINS_MASK; 328 /* 329 * Set NSACR to indicate "NS access permitted to everything"; 330 * this avoids having to have all the tests of it being 331 * conditional on ARM_FEATURE_M_SECURITY. Note also that from 332 * v8.1M the guest-visible value of NSACR in a CPU without the 333 * Security Extension is 0xcff. 334 */ 335 env->v7m.nsacr = 0xcff; 336 } 337 338 /* In v7M the reset value of this bit is IMPDEF, but ARM recommends 339 * that it resets to 1, so QEMU always does that rather than making 340 * it dependent on CPU model. In v8M it is RES1. 341 */ 342 env->v7m.ccr[M_REG_NS] = R_V7M_CCR_STKALIGN_MASK; 343 env->v7m.ccr[M_REG_S] = R_V7M_CCR_STKALIGN_MASK; 344 if (arm_feature(env, ARM_FEATURE_V8)) { 345 /* in v8M the NONBASETHRDENA bit [0] is RES1 */ 346 env->v7m.ccr[M_REG_NS] |= R_V7M_CCR_NONBASETHRDENA_MASK; 347 env->v7m.ccr[M_REG_S] |= R_V7M_CCR_NONBASETHRDENA_MASK; 348 } 349 if (!arm_feature(env, ARM_FEATURE_M_MAIN)) { 350 env->v7m.ccr[M_REG_NS] |= R_V7M_CCR_UNALIGN_TRP_MASK; 351 env->v7m.ccr[M_REG_S] |= R_V7M_CCR_UNALIGN_TRP_MASK; 352 } 353 354 if (cpu_isar_feature(aa32_vfp_simd, cpu)) { 355 env->v7m.fpccr[M_REG_NS] = R_V7M_FPCCR_ASPEN_MASK; 356 env->v7m.fpccr[M_REG_S] = R_V7M_FPCCR_ASPEN_MASK | 357 R_V7M_FPCCR_LSPEN_MASK | R_V7M_FPCCR_S_MASK; 358 } 359 360 #ifndef CONFIG_USER_ONLY 361 /* Unlike A/R profile, M profile defines the reset LR value */ 362 env->regs[14] = 0xffffffff; 363 364 env->v7m.vecbase[M_REG_S] = cpu->init_svtor & 0xffffff80; 365 env->v7m.vecbase[M_REG_NS] = cpu->init_nsvtor & 0xffffff80; 366 367 /* Load the initial SP and PC from offset 0 and 4 in the vector table */ 368 vecbase = env->v7m.vecbase[env->v7m.secure]; 369 rom = rom_ptr_for_as(s->as, vecbase, 8); 370 if (rom) { 371 /* Address zero is covered by ROM which hasn't yet been 372 * copied into physical memory. 373 */ 374 initial_msp = ldl_p(rom); 375 initial_pc = ldl_p(rom + 4); 376 } else { 377 /* Address zero not covered by a ROM blob, or the ROM blob 378 * is in non-modifiable memory and this is a second reset after 379 * it got copied into memory. In the latter case, rom_ptr 380 * will return a NULL pointer and we should use ldl_phys instead. 381 */ 382 initial_msp = ldl_phys(s->as, vecbase); 383 initial_pc = ldl_phys(s->as, vecbase + 4); 384 } 385 386 qemu_log_mask(CPU_LOG_INT, 387 "Loaded reset SP 0x%x PC 0x%x from vector table\n", 388 initial_msp, initial_pc); 389 390 env->regs[13] = initial_msp & 0xFFFFFFFC; 391 env->regs[15] = initial_pc & ~1; 392 env->thumb = initial_pc & 1; 393 #else 394 /* 395 * For user mode we run non-secure and with access to the FPU. 396 * The FPU context is active (ie does not need further setup) 397 * and is owned by non-secure. 398 */ 399 env->v7m.secure = false; 400 env->v7m.nsacr = 0xcff; 401 env->v7m.cpacr[M_REG_NS] = 0xf0ffff; 402 env->v7m.fpccr[M_REG_S] &= 403 ~(R_V7M_FPCCR_LSPEN_MASK | R_V7M_FPCCR_S_MASK); 404 env->v7m.control[M_REG_S] |= R_V7M_CONTROL_FPCA_MASK; 405 #endif 406 } 407 408 /* M profile requires that reset clears the exclusive monitor; 409 * A profile does not, but clearing it makes more sense than having it 410 * set with an exclusive access on address zero. 411 */ 412 arm_clear_exclusive(env); 413 414 if (arm_feature(env, ARM_FEATURE_PMSA)) { 415 if (cpu->pmsav7_dregion > 0) { 416 if (arm_feature(env, ARM_FEATURE_V8)) { 417 memset(env->pmsav8.rbar[M_REG_NS], 0, 418 sizeof(*env->pmsav8.rbar[M_REG_NS]) 419 * cpu->pmsav7_dregion); 420 memset(env->pmsav8.rlar[M_REG_NS], 0, 421 sizeof(*env->pmsav8.rlar[M_REG_NS]) 422 * cpu->pmsav7_dregion); 423 if (arm_feature(env, ARM_FEATURE_M_SECURITY)) { 424 memset(env->pmsav8.rbar[M_REG_S], 0, 425 sizeof(*env->pmsav8.rbar[M_REG_S]) 426 * cpu->pmsav7_dregion); 427 memset(env->pmsav8.rlar[M_REG_S], 0, 428 sizeof(*env->pmsav8.rlar[M_REG_S]) 429 * cpu->pmsav7_dregion); 430 } 431 } else if (arm_feature(env, ARM_FEATURE_V7)) { 432 memset(env->pmsav7.drbar, 0, 433 sizeof(*env->pmsav7.drbar) * cpu->pmsav7_dregion); 434 memset(env->pmsav7.drsr, 0, 435 sizeof(*env->pmsav7.drsr) * cpu->pmsav7_dregion); 436 memset(env->pmsav7.dracr, 0, 437 sizeof(*env->pmsav7.dracr) * cpu->pmsav7_dregion); 438 } 439 } 440 env->pmsav7.rnr[M_REG_NS] = 0; 441 env->pmsav7.rnr[M_REG_S] = 0; 442 env->pmsav8.mair0[M_REG_NS] = 0; 443 env->pmsav8.mair0[M_REG_S] = 0; 444 env->pmsav8.mair1[M_REG_NS] = 0; 445 env->pmsav8.mair1[M_REG_S] = 0; 446 } 447 448 if (arm_feature(env, ARM_FEATURE_M_SECURITY)) { 449 if (cpu->sau_sregion > 0) { 450 memset(env->sau.rbar, 0, sizeof(*env->sau.rbar) * cpu->sau_sregion); 451 memset(env->sau.rlar, 0, sizeof(*env->sau.rlar) * cpu->sau_sregion); 452 } 453 env->sau.rnr = 0; 454 /* SAU_CTRL reset value is IMPDEF; we choose 0, which is what 455 * the Cortex-M33 does. 456 */ 457 env->sau.ctrl = 0; 458 } 459 460 set_flush_to_zero(1, &env->vfp.standard_fp_status); 461 set_flush_inputs_to_zero(1, &env->vfp.standard_fp_status); 462 set_default_nan_mode(1, &env->vfp.standard_fp_status); 463 set_default_nan_mode(1, &env->vfp.standard_fp_status_f16); 464 set_float_detect_tininess(float_tininess_before_rounding, 465 &env->vfp.fp_status); 466 set_float_detect_tininess(float_tininess_before_rounding, 467 &env->vfp.standard_fp_status); 468 set_float_detect_tininess(float_tininess_before_rounding, 469 &env->vfp.fp_status_f16); 470 set_float_detect_tininess(float_tininess_before_rounding, 471 &env->vfp.standard_fp_status_f16); 472 #ifndef CONFIG_USER_ONLY 473 if (kvm_enabled()) { 474 kvm_arm_reset_vcpu(cpu); 475 } 476 #endif 477 478 hw_breakpoint_update_all(cpu); 479 hw_watchpoint_update_all(cpu); 480 arm_rebuild_hflags(env); 481 } 482 483 #ifndef CONFIG_USER_ONLY 484 485 static inline bool arm_excp_unmasked(CPUState *cs, unsigned int excp_idx, 486 unsigned int target_el, 487 unsigned int cur_el, bool secure, 488 uint64_t hcr_el2) 489 { 490 CPUARMState *env = cs->env_ptr; 491 bool pstate_unmasked; 492 bool unmasked = false; 493 494 /* 495 * Don't take exceptions if they target a lower EL. 496 * This check should catch any exceptions that would not be taken 497 * but left pending. 498 */ 499 if (cur_el > target_el) { 500 return false; 501 } 502 503 switch (excp_idx) { 504 case EXCP_FIQ: 505 pstate_unmasked = !(env->daif & PSTATE_F); 506 break; 507 508 case EXCP_IRQ: 509 pstate_unmasked = !(env->daif & PSTATE_I); 510 break; 511 512 case EXCP_VFIQ: 513 if (!(hcr_el2 & HCR_FMO) || (hcr_el2 & HCR_TGE)) { 514 /* VFIQs are only taken when hypervized. */ 515 return false; 516 } 517 return !(env->daif & PSTATE_F); 518 case EXCP_VIRQ: 519 if (!(hcr_el2 & HCR_IMO) || (hcr_el2 & HCR_TGE)) { 520 /* VIRQs are only taken when hypervized. */ 521 return false; 522 } 523 return !(env->daif & PSTATE_I); 524 case EXCP_VSERR: 525 if (!(hcr_el2 & HCR_AMO) || (hcr_el2 & HCR_TGE)) { 526 /* VIRQs are only taken when hypervized. */ 527 return false; 528 } 529 return !(env->daif & PSTATE_A); 530 default: 531 g_assert_not_reached(); 532 } 533 534 /* 535 * Use the target EL, current execution state and SCR/HCR settings to 536 * determine whether the corresponding CPSR bit is used to mask the 537 * interrupt. 538 */ 539 if ((target_el > cur_el) && (target_el != 1)) { 540 /* Exceptions targeting a higher EL may not be maskable */ 541 if (arm_feature(env, ARM_FEATURE_AARCH64)) { 542 /* 543 * 64-bit masking rules are simple: exceptions to EL3 544 * can't be masked, and exceptions to EL2 can only be 545 * masked from Secure state. The HCR and SCR settings 546 * don't affect the masking logic, only the interrupt routing. 547 */ 548 if (target_el == 3 || !secure || (env->cp15.scr_el3 & SCR_EEL2)) { 549 unmasked = true; 550 } 551 } else { 552 /* 553 * The old 32-bit-only environment has a more complicated 554 * masking setup. HCR and SCR bits not only affect interrupt 555 * routing but also change the behaviour of masking. 556 */ 557 bool hcr, scr; 558 559 switch (excp_idx) { 560 case EXCP_FIQ: 561 /* 562 * If FIQs are routed to EL3 or EL2 then there are cases where 563 * we override the CPSR.F in determining if the exception is 564 * masked or not. If neither of these are set then we fall back 565 * to the CPSR.F setting otherwise we further assess the state 566 * below. 567 */ 568 hcr = hcr_el2 & HCR_FMO; 569 scr = (env->cp15.scr_el3 & SCR_FIQ); 570 571 /* 572 * When EL3 is 32-bit, the SCR.FW bit controls whether the 573 * CPSR.F bit masks FIQ interrupts when taken in non-secure 574 * state. If SCR.FW is set then FIQs can be masked by CPSR.F 575 * when non-secure but only when FIQs are only routed to EL3. 576 */ 577 scr = scr && !((env->cp15.scr_el3 & SCR_FW) && !hcr); 578 break; 579 case EXCP_IRQ: 580 /* 581 * When EL3 execution state is 32-bit, if HCR.IMO is set then 582 * we may override the CPSR.I masking when in non-secure state. 583 * The SCR.IRQ setting has already been taken into consideration 584 * when setting the target EL, so it does not have a further 585 * affect here. 586 */ 587 hcr = hcr_el2 & HCR_IMO; 588 scr = false; 589 break; 590 default: 591 g_assert_not_reached(); 592 } 593 594 if ((scr || hcr) && !secure) { 595 unmasked = true; 596 } 597 } 598 } 599 600 /* 601 * The PSTATE bits only mask the interrupt if we have not overriden the 602 * ability above. 603 */ 604 return unmasked || pstate_unmasked; 605 } 606 607 static bool arm_cpu_exec_interrupt(CPUState *cs, int interrupt_request) 608 { 609 CPUClass *cc = CPU_GET_CLASS(cs); 610 CPUARMState *env = cs->env_ptr; 611 uint32_t cur_el = arm_current_el(env); 612 bool secure = arm_is_secure(env); 613 uint64_t hcr_el2 = arm_hcr_el2_eff(env); 614 uint32_t target_el; 615 uint32_t excp_idx; 616 617 /* The prioritization of interrupts is IMPLEMENTATION DEFINED. */ 618 619 if (interrupt_request & CPU_INTERRUPT_FIQ) { 620 excp_idx = EXCP_FIQ; 621 target_el = arm_phys_excp_target_el(cs, excp_idx, cur_el, secure); 622 if (arm_excp_unmasked(cs, excp_idx, target_el, 623 cur_el, secure, hcr_el2)) { 624 goto found; 625 } 626 } 627 if (interrupt_request & CPU_INTERRUPT_HARD) { 628 excp_idx = EXCP_IRQ; 629 target_el = arm_phys_excp_target_el(cs, excp_idx, cur_el, secure); 630 if (arm_excp_unmasked(cs, excp_idx, target_el, 631 cur_el, secure, hcr_el2)) { 632 goto found; 633 } 634 } 635 if (interrupt_request & CPU_INTERRUPT_VIRQ) { 636 excp_idx = EXCP_VIRQ; 637 target_el = 1; 638 if (arm_excp_unmasked(cs, excp_idx, target_el, 639 cur_el, secure, hcr_el2)) { 640 goto found; 641 } 642 } 643 if (interrupt_request & CPU_INTERRUPT_VFIQ) { 644 excp_idx = EXCP_VFIQ; 645 target_el = 1; 646 if (arm_excp_unmasked(cs, excp_idx, target_el, 647 cur_el, secure, hcr_el2)) { 648 goto found; 649 } 650 } 651 if (interrupt_request & CPU_INTERRUPT_VSERR) { 652 excp_idx = EXCP_VSERR; 653 target_el = 1; 654 if (arm_excp_unmasked(cs, excp_idx, target_el, 655 cur_el, secure, hcr_el2)) { 656 /* Taking a virtual abort clears HCR_EL2.VSE */ 657 env->cp15.hcr_el2 &= ~HCR_VSE; 658 cpu_reset_interrupt(cs, CPU_INTERRUPT_VSERR); 659 goto found; 660 } 661 } 662 return false; 663 664 found: 665 cs->exception_index = excp_idx; 666 env->exception.target_el = target_el; 667 cc->tcg_ops->do_interrupt(cs); 668 return true; 669 } 670 #endif /* !CONFIG_USER_ONLY */ 671 672 void arm_cpu_update_virq(ARMCPU *cpu) 673 { 674 /* 675 * Update the interrupt level for VIRQ, which is the logical OR of 676 * the HCR_EL2.VI bit and the input line level from the GIC. 677 */ 678 CPUARMState *env = &cpu->env; 679 CPUState *cs = CPU(cpu); 680 681 bool new_state = (env->cp15.hcr_el2 & HCR_VI) || 682 (env->irq_line_state & CPU_INTERRUPT_VIRQ); 683 684 if (new_state != ((cs->interrupt_request & CPU_INTERRUPT_VIRQ) != 0)) { 685 if (new_state) { 686 cpu_interrupt(cs, CPU_INTERRUPT_VIRQ); 687 } else { 688 cpu_reset_interrupt(cs, CPU_INTERRUPT_VIRQ); 689 } 690 } 691 } 692 693 void arm_cpu_update_vfiq(ARMCPU *cpu) 694 { 695 /* 696 * Update the interrupt level for VFIQ, which is the logical OR of 697 * the HCR_EL2.VF bit and the input line level from the GIC. 698 */ 699 CPUARMState *env = &cpu->env; 700 CPUState *cs = CPU(cpu); 701 702 bool new_state = (env->cp15.hcr_el2 & HCR_VF) || 703 (env->irq_line_state & CPU_INTERRUPT_VFIQ); 704 705 if (new_state != ((cs->interrupt_request & CPU_INTERRUPT_VFIQ) != 0)) { 706 if (new_state) { 707 cpu_interrupt(cs, CPU_INTERRUPT_VFIQ); 708 } else { 709 cpu_reset_interrupt(cs, CPU_INTERRUPT_VFIQ); 710 } 711 } 712 } 713 714 void arm_cpu_update_vserr(ARMCPU *cpu) 715 { 716 /* 717 * Update the interrupt level for VSERR, which is the HCR_EL2.VSE bit. 718 */ 719 CPUARMState *env = &cpu->env; 720 CPUState *cs = CPU(cpu); 721 722 bool new_state = env->cp15.hcr_el2 & HCR_VSE; 723 724 if (new_state != ((cs->interrupt_request & CPU_INTERRUPT_VSERR) != 0)) { 725 if (new_state) { 726 cpu_interrupt(cs, CPU_INTERRUPT_VSERR); 727 } else { 728 cpu_reset_interrupt(cs, CPU_INTERRUPT_VSERR); 729 } 730 } 731 } 732 733 #ifndef CONFIG_USER_ONLY 734 static void arm_cpu_set_irq(void *opaque, int irq, int level) 735 { 736 ARMCPU *cpu = opaque; 737 CPUARMState *env = &cpu->env; 738 CPUState *cs = CPU(cpu); 739 static const int mask[] = { 740 [ARM_CPU_IRQ] = CPU_INTERRUPT_HARD, 741 [ARM_CPU_FIQ] = CPU_INTERRUPT_FIQ, 742 [ARM_CPU_VIRQ] = CPU_INTERRUPT_VIRQ, 743 [ARM_CPU_VFIQ] = CPU_INTERRUPT_VFIQ 744 }; 745 746 if (!arm_feature(env, ARM_FEATURE_EL2) && 747 (irq == ARM_CPU_VIRQ || irq == ARM_CPU_VFIQ)) { 748 /* 749 * The GIC might tell us about VIRQ and VFIQ state, but if we don't 750 * have EL2 support we don't care. (Unless the guest is doing something 751 * silly this will only be calls saying "level is still 0".) 752 */ 753 return; 754 } 755 756 if (level) { 757 env->irq_line_state |= mask[irq]; 758 } else { 759 env->irq_line_state &= ~mask[irq]; 760 } 761 762 switch (irq) { 763 case ARM_CPU_VIRQ: 764 arm_cpu_update_virq(cpu); 765 break; 766 case ARM_CPU_VFIQ: 767 arm_cpu_update_vfiq(cpu); 768 break; 769 case ARM_CPU_IRQ: 770 case ARM_CPU_FIQ: 771 if (level) { 772 cpu_interrupt(cs, mask[irq]); 773 } else { 774 cpu_reset_interrupt(cs, mask[irq]); 775 } 776 break; 777 default: 778 g_assert_not_reached(); 779 } 780 } 781 782 static void arm_cpu_kvm_set_irq(void *opaque, int irq, int level) 783 { 784 #ifdef CONFIG_KVM 785 ARMCPU *cpu = opaque; 786 CPUARMState *env = &cpu->env; 787 CPUState *cs = CPU(cpu); 788 uint32_t linestate_bit; 789 int irq_id; 790 791 switch (irq) { 792 case ARM_CPU_IRQ: 793 irq_id = KVM_ARM_IRQ_CPU_IRQ; 794 linestate_bit = CPU_INTERRUPT_HARD; 795 break; 796 case ARM_CPU_FIQ: 797 irq_id = KVM_ARM_IRQ_CPU_FIQ; 798 linestate_bit = CPU_INTERRUPT_FIQ; 799 break; 800 default: 801 g_assert_not_reached(); 802 } 803 804 if (level) { 805 env->irq_line_state |= linestate_bit; 806 } else { 807 env->irq_line_state &= ~linestate_bit; 808 } 809 kvm_arm_set_irq(cs->cpu_index, KVM_ARM_IRQ_TYPE_CPU, irq_id, !!level); 810 #endif 811 } 812 813 static bool arm_cpu_virtio_is_big_endian(CPUState *cs) 814 { 815 ARMCPU *cpu = ARM_CPU(cs); 816 CPUARMState *env = &cpu->env; 817 818 cpu_synchronize_state(cs); 819 return arm_cpu_data_is_big_endian(env); 820 } 821 822 #endif 823 824 static void arm_disas_set_info(CPUState *cpu, disassemble_info *info) 825 { 826 ARMCPU *ac = ARM_CPU(cpu); 827 CPUARMState *env = &ac->env; 828 bool sctlr_b; 829 830 if (is_a64(env)) { 831 /* We might not be compiled with the A64 disassembler 832 * because it needs a C++ compiler. Leave print_insn 833 * unset in this case to use the caller default behaviour. 834 */ 835 #if defined(CONFIG_ARM_A64_DIS) 836 info->print_insn = print_insn_arm_a64; 837 #endif 838 info->cap_arch = CS_ARCH_ARM64; 839 info->cap_insn_unit = 4; 840 info->cap_insn_split = 4; 841 } else { 842 int cap_mode; 843 if (env->thumb) { 844 info->cap_insn_unit = 2; 845 info->cap_insn_split = 4; 846 cap_mode = CS_MODE_THUMB; 847 } else { 848 info->cap_insn_unit = 4; 849 info->cap_insn_split = 4; 850 cap_mode = CS_MODE_ARM; 851 } 852 if (arm_feature(env, ARM_FEATURE_V8)) { 853 cap_mode |= CS_MODE_V8; 854 } 855 if (arm_feature(env, ARM_FEATURE_M)) { 856 cap_mode |= CS_MODE_MCLASS; 857 } 858 info->cap_arch = CS_ARCH_ARM; 859 info->cap_mode = cap_mode; 860 } 861 862 sctlr_b = arm_sctlr_b(env); 863 if (bswap_code(sctlr_b)) { 864 #if TARGET_BIG_ENDIAN 865 info->endian = BFD_ENDIAN_LITTLE; 866 #else 867 info->endian = BFD_ENDIAN_BIG; 868 #endif 869 } 870 info->flags &= ~INSN_ARM_BE32; 871 #ifndef CONFIG_USER_ONLY 872 if (sctlr_b) { 873 info->flags |= INSN_ARM_BE32; 874 } 875 #endif 876 } 877 878 #ifdef TARGET_AARCH64 879 880 static void aarch64_cpu_dump_state(CPUState *cs, FILE *f, int flags) 881 { 882 ARMCPU *cpu = ARM_CPU(cs); 883 CPUARMState *env = &cpu->env; 884 uint32_t psr = pstate_read(env); 885 int i; 886 int el = arm_current_el(env); 887 const char *ns_status; 888 889 qemu_fprintf(f, " PC=%016" PRIx64 " ", env->pc); 890 for (i = 0; i < 32; i++) { 891 if (i == 31) { 892 qemu_fprintf(f, " SP=%016" PRIx64 "\n", env->xregs[i]); 893 } else { 894 qemu_fprintf(f, "X%02d=%016" PRIx64 "%s", i, env->xregs[i], 895 (i + 2) % 3 ? " " : "\n"); 896 } 897 } 898 899 if (arm_feature(env, ARM_FEATURE_EL3) && el != 3) { 900 ns_status = env->cp15.scr_el3 & SCR_NS ? "NS " : "S "; 901 } else { 902 ns_status = ""; 903 } 904 qemu_fprintf(f, "PSTATE=%08x %c%c%c%c %sEL%d%c", 905 psr, 906 psr & PSTATE_N ? 'N' : '-', 907 psr & PSTATE_Z ? 'Z' : '-', 908 psr & PSTATE_C ? 'C' : '-', 909 psr & PSTATE_V ? 'V' : '-', 910 ns_status, 911 el, 912 psr & PSTATE_SP ? 'h' : 't'); 913 914 if (cpu_isar_feature(aa64_bti, cpu)) { 915 qemu_fprintf(f, " BTYPE=%d", (psr & PSTATE_BTYPE) >> 10); 916 } 917 if (!(flags & CPU_DUMP_FPU)) { 918 qemu_fprintf(f, "\n"); 919 return; 920 } 921 if (fp_exception_el(env, el) != 0) { 922 qemu_fprintf(f, " FPU disabled\n"); 923 return; 924 } 925 qemu_fprintf(f, " FPCR=%08x FPSR=%08x\n", 926 vfp_get_fpcr(env), vfp_get_fpsr(env)); 927 928 if (cpu_isar_feature(aa64_sve, cpu) && sve_exception_el(env, el) == 0) { 929 int j, zcr_len = sve_vqm1_for_el(env, el); 930 931 for (i = 0; i <= FFR_PRED_NUM; i++) { 932 bool eol; 933 if (i == FFR_PRED_NUM) { 934 qemu_fprintf(f, "FFR="); 935 /* It's last, so end the line. */ 936 eol = true; 937 } else { 938 qemu_fprintf(f, "P%02d=", i); 939 switch (zcr_len) { 940 case 0: 941 eol = i % 8 == 7; 942 break; 943 case 1: 944 eol = i % 6 == 5; 945 break; 946 case 2: 947 case 3: 948 eol = i % 3 == 2; 949 break; 950 default: 951 /* More than one quadword per predicate. */ 952 eol = true; 953 break; 954 } 955 } 956 for (j = zcr_len / 4; j >= 0; j--) { 957 int digits; 958 if (j * 4 + 4 <= zcr_len + 1) { 959 digits = 16; 960 } else { 961 digits = (zcr_len % 4 + 1) * 4; 962 } 963 qemu_fprintf(f, "%0*" PRIx64 "%s", digits, 964 env->vfp.pregs[i].p[j], 965 j ? ":" : eol ? "\n" : " "); 966 } 967 } 968 969 for (i = 0; i < 32; i++) { 970 if (zcr_len == 0) { 971 qemu_fprintf(f, "Z%02d=%016" PRIx64 ":%016" PRIx64 "%s", 972 i, env->vfp.zregs[i].d[1], 973 env->vfp.zregs[i].d[0], i & 1 ? "\n" : " "); 974 } else if (zcr_len == 1) { 975 qemu_fprintf(f, "Z%02d=%016" PRIx64 ":%016" PRIx64 976 ":%016" PRIx64 ":%016" PRIx64 "\n", 977 i, env->vfp.zregs[i].d[3], env->vfp.zregs[i].d[2], 978 env->vfp.zregs[i].d[1], env->vfp.zregs[i].d[0]); 979 } else { 980 for (j = zcr_len; j >= 0; j--) { 981 bool odd = (zcr_len - j) % 2 != 0; 982 if (j == zcr_len) { 983 qemu_fprintf(f, "Z%02d[%x-%x]=", i, j, j - 1); 984 } else if (!odd) { 985 if (j > 0) { 986 qemu_fprintf(f, " [%x-%x]=", j, j - 1); 987 } else { 988 qemu_fprintf(f, " [%x]=", j); 989 } 990 } 991 qemu_fprintf(f, "%016" PRIx64 ":%016" PRIx64 "%s", 992 env->vfp.zregs[i].d[j * 2 + 1], 993 env->vfp.zregs[i].d[j * 2], 994 odd || j == 0 ? "\n" : ":"); 995 } 996 } 997 } 998 } else { 999 for (i = 0; i < 32; i++) { 1000 uint64_t *q = aa64_vfp_qreg(env, i); 1001 qemu_fprintf(f, "Q%02d=%016" PRIx64 ":%016" PRIx64 "%s", 1002 i, q[1], q[0], (i & 1 ? "\n" : " ")); 1003 } 1004 } 1005 } 1006 1007 #else 1008 1009 static inline void aarch64_cpu_dump_state(CPUState *cs, FILE *f, int flags) 1010 { 1011 g_assert_not_reached(); 1012 } 1013 1014 #endif 1015 1016 static void arm_cpu_dump_state(CPUState *cs, FILE *f, int flags) 1017 { 1018 ARMCPU *cpu = ARM_CPU(cs); 1019 CPUARMState *env = &cpu->env; 1020 int i; 1021 1022 if (is_a64(env)) { 1023 aarch64_cpu_dump_state(cs, f, flags); 1024 return; 1025 } 1026 1027 for (i = 0; i < 16; i++) { 1028 qemu_fprintf(f, "R%02d=%08x", i, env->regs[i]); 1029 if ((i % 4) == 3) { 1030 qemu_fprintf(f, "\n"); 1031 } else { 1032 qemu_fprintf(f, " "); 1033 } 1034 } 1035 1036 if (arm_feature(env, ARM_FEATURE_M)) { 1037 uint32_t xpsr = xpsr_read(env); 1038 const char *mode; 1039 const char *ns_status = ""; 1040 1041 if (arm_feature(env, ARM_FEATURE_M_SECURITY)) { 1042 ns_status = env->v7m.secure ? "S " : "NS "; 1043 } 1044 1045 if (xpsr & XPSR_EXCP) { 1046 mode = "handler"; 1047 } else { 1048 if (env->v7m.control[env->v7m.secure] & R_V7M_CONTROL_NPRIV_MASK) { 1049 mode = "unpriv-thread"; 1050 } else { 1051 mode = "priv-thread"; 1052 } 1053 } 1054 1055 qemu_fprintf(f, "XPSR=%08x %c%c%c%c %c %s%s\n", 1056 xpsr, 1057 xpsr & XPSR_N ? 'N' : '-', 1058 xpsr & XPSR_Z ? 'Z' : '-', 1059 xpsr & XPSR_C ? 'C' : '-', 1060 xpsr & XPSR_V ? 'V' : '-', 1061 xpsr & XPSR_T ? 'T' : 'A', 1062 ns_status, 1063 mode); 1064 } else { 1065 uint32_t psr = cpsr_read(env); 1066 const char *ns_status = ""; 1067 1068 if (arm_feature(env, ARM_FEATURE_EL3) && 1069 (psr & CPSR_M) != ARM_CPU_MODE_MON) { 1070 ns_status = env->cp15.scr_el3 & SCR_NS ? "NS " : "S "; 1071 } 1072 1073 qemu_fprintf(f, "PSR=%08x %c%c%c%c %c %s%s%d\n", 1074 psr, 1075 psr & CPSR_N ? 'N' : '-', 1076 psr & CPSR_Z ? 'Z' : '-', 1077 psr & CPSR_C ? 'C' : '-', 1078 psr & CPSR_V ? 'V' : '-', 1079 psr & CPSR_T ? 'T' : 'A', 1080 ns_status, 1081 aarch32_mode_name(psr), (psr & 0x10) ? 32 : 26); 1082 } 1083 1084 if (flags & CPU_DUMP_FPU) { 1085 int numvfpregs = 0; 1086 if (cpu_isar_feature(aa32_simd_r32, cpu)) { 1087 numvfpregs = 32; 1088 } else if (cpu_isar_feature(aa32_vfp_simd, cpu)) { 1089 numvfpregs = 16; 1090 } 1091 for (i = 0; i < numvfpregs; i++) { 1092 uint64_t v = *aa32_vfp_dreg(env, i); 1093 qemu_fprintf(f, "s%02d=%08x s%02d=%08x d%02d=%016" PRIx64 "\n", 1094 i * 2, (uint32_t)v, 1095 i * 2 + 1, (uint32_t)(v >> 32), 1096 i, v); 1097 } 1098 qemu_fprintf(f, "FPSCR: %08x\n", vfp_get_fpscr(env)); 1099 if (cpu_isar_feature(aa32_mve, cpu)) { 1100 qemu_fprintf(f, "VPR: %08x\n", env->v7m.vpr); 1101 } 1102 } 1103 } 1104 1105 uint64_t arm_cpu_mp_affinity(int idx, uint8_t clustersz) 1106 { 1107 uint32_t Aff1 = idx / clustersz; 1108 uint32_t Aff0 = idx % clustersz; 1109 return (Aff1 << ARM_AFF1_SHIFT) | Aff0; 1110 } 1111 1112 static void arm_cpu_initfn(Object *obj) 1113 { 1114 ARMCPU *cpu = ARM_CPU(obj); 1115 1116 cpu_set_cpustate_pointers(cpu); 1117 cpu->cp_regs = g_hash_table_new_full(g_direct_hash, g_direct_equal, 1118 NULL, g_free); 1119 1120 QLIST_INIT(&cpu->pre_el_change_hooks); 1121 QLIST_INIT(&cpu->el_change_hooks); 1122 1123 #ifdef CONFIG_USER_ONLY 1124 # ifdef TARGET_AARCH64 1125 /* 1126 * The linux kernel defaults to 512-bit for SVE, and 256-bit for SME. 1127 * These values were chosen to fit within the default signal frame. 1128 * See documentation for /proc/sys/abi/{sve,sme}_default_vector_length, 1129 * and our corresponding cpu property. 1130 */ 1131 cpu->sve_default_vq = 4; 1132 cpu->sme_default_vq = 2; 1133 # endif 1134 #else 1135 /* Our inbound IRQ and FIQ lines */ 1136 if (kvm_enabled()) { 1137 /* VIRQ and VFIQ are unused with KVM but we add them to maintain 1138 * the same interface as non-KVM CPUs. 1139 */ 1140 qdev_init_gpio_in(DEVICE(cpu), arm_cpu_kvm_set_irq, 4); 1141 } else { 1142 qdev_init_gpio_in(DEVICE(cpu), arm_cpu_set_irq, 4); 1143 } 1144 1145 qdev_init_gpio_out(DEVICE(cpu), cpu->gt_timer_outputs, 1146 ARRAY_SIZE(cpu->gt_timer_outputs)); 1147 1148 qdev_init_gpio_out_named(DEVICE(cpu), &cpu->gicv3_maintenance_interrupt, 1149 "gicv3-maintenance-interrupt", 1); 1150 qdev_init_gpio_out_named(DEVICE(cpu), &cpu->pmu_interrupt, 1151 "pmu-interrupt", 1); 1152 #endif 1153 1154 /* DTB consumers generally don't in fact care what the 'compatible' 1155 * string is, so always provide some string and trust that a hypothetical 1156 * picky DTB consumer will also provide a helpful error message. 1157 */ 1158 cpu->dtb_compatible = "qemu,unknown"; 1159 cpu->psci_version = QEMU_PSCI_VERSION_0_1; /* By default assume PSCI v0.1 */ 1160 cpu->kvm_target = QEMU_KVM_ARM_TARGET_NONE; 1161 1162 if (tcg_enabled() || hvf_enabled()) { 1163 /* TCG and HVF implement PSCI 1.1 */ 1164 cpu->psci_version = QEMU_PSCI_VERSION_1_1; 1165 } 1166 } 1167 1168 static Property arm_cpu_gt_cntfrq_property = 1169 DEFINE_PROP_UINT64("cntfrq", ARMCPU, gt_cntfrq_hz, 1170 NANOSECONDS_PER_SECOND / GTIMER_SCALE); 1171 1172 static Property arm_cpu_reset_cbar_property = 1173 DEFINE_PROP_UINT64("reset-cbar", ARMCPU, reset_cbar, 0); 1174 1175 static Property arm_cpu_reset_hivecs_property = 1176 DEFINE_PROP_BOOL("reset-hivecs", ARMCPU, reset_hivecs, false); 1177 1178 #ifndef CONFIG_USER_ONLY 1179 static Property arm_cpu_has_el2_property = 1180 DEFINE_PROP_BOOL("has_el2", ARMCPU, has_el2, true); 1181 1182 static Property arm_cpu_has_el3_property = 1183 DEFINE_PROP_BOOL("has_el3", ARMCPU, has_el3, true); 1184 #endif 1185 1186 static Property arm_cpu_cfgend_property = 1187 DEFINE_PROP_BOOL("cfgend", ARMCPU, cfgend, false); 1188 1189 static Property arm_cpu_has_vfp_property = 1190 DEFINE_PROP_BOOL("vfp", ARMCPU, has_vfp, true); 1191 1192 static Property arm_cpu_has_neon_property = 1193 DEFINE_PROP_BOOL("neon", ARMCPU, has_neon, true); 1194 1195 static Property arm_cpu_has_dsp_property = 1196 DEFINE_PROP_BOOL("dsp", ARMCPU, has_dsp, true); 1197 1198 static Property arm_cpu_has_mpu_property = 1199 DEFINE_PROP_BOOL("has-mpu", ARMCPU, has_mpu, true); 1200 1201 /* This is like DEFINE_PROP_UINT32 but it doesn't set the default value, 1202 * because the CPU initfn will have already set cpu->pmsav7_dregion to 1203 * the right value for that particular CPU type, and we don't want 1204 * to override that with an incorrect constant value. 1205 */ 1206 static Property arm_cpu_pmsav7_dregion_property = 1207 DEFINE_PROP_UNSIGNED_NODEFAULT("pmsav7-dregion", ARMCPU, 1208 pmsav7_dregion, 1209 qdev_prop_uint32, uint32_t); 1210 1211 static bool arm_get_pmu(Object *obj, Error **errp) 1212 { 1213 ARMCPU *cpu = ARM_CPU(obj); 1214 1215 return cpu->has_pmu; 1216 } 1217 1218 static void arm_set_pmu(Object *obj, bool value, Error **errp) 1219 { 1220 ARMCPU *cpu = ARM_CPU(obj); 1221 1222 if (value) { 1223 if (kvm_enabled() && !kvm_arm_pmu_supported()) { 1224 error_setg(errp, "'pmu' feature not supported by KVM on this host"); 1225 return; 1226 } 1227 set_feature(&cpu->env, ARM_FEATURE_PMU); 1228 } else { 1229 unset_feature(&cpu->env, ARM_FEATURE_PMU); 1230 } 1231 cpu->has_pmu = value; 1232 } 1233 1234 unsigned int gt_cntfrq_period_ns(ARMCPU *cpu) 1235 { 1236 /* 1237 * The exact approach to calculating guest ticks is: 1238 * 1239 * muldiv64(qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL), cpu->gt_cntfrq_hz, 1240 * NANOSECONDS_PER_SECOND); 1241 * 1242 * We don't do that. Rather we intentionally use integer division 1243 * truncation below and in the caller for the conversion of host monotonic 1244 * time to guest ticks to provide the exact inverse for the semantics of 1245 * the QEMUTimer scale factor. QEMUTimer's scale facter is an integer, so 1246 * it loses precision when representing frequencies where 1247 * `(NANOSECONDS_PER_SECOND % cpu->gt_cntfrq) > 0` holds. Failing to 1248 * provide an exact inverse leads to scheduling timers with negative 1249 * periods, which in turn leads to sticky behaviour in the guest. 1250 * 1251 * Finally, CNTFRQ is effectively capped at 1GHz to ensure our scale factor 1252 * cannot become zero. 1253 */ 1254 return NANOSECONDS_PER_SECOND > cpu->gt_cntfrq_hz ? 1255 NANOSECONDS_PER_SECOND / cpu->gt_cntfrq_hz : 1; 1256 } 1257 1258 void arm_cpu_post_init(Object *obj) 1259 { 1260 ARMCPU *cpu = ARM_CPU(obj); 1261 1262 /* M profile implies PMSA. We have to do this here rather than 1263 * in realize with the other feature-implication checks because 1264 * we look at the PMSA bit to see if we should add some properties. 1265 */ 1266 if (arm_feature(&cpu->env, ARM_FEATURE_M)) { 1267 set_feature(&cpu->env, ARM_FEATURE_PMSA); 1268 } 1269 1270 if (arm_feature(&cpu->env, ARM_FEATURE_CBAR) || 1271 arm_feature(&cpu->env, ARM_FEATURE_CBAR_RO)) { 1272 qdev_property_add_static(DEVICE(obj), &arm_cpu_reset_cbar_property); 1273 } 1274 1275 if (!arm_feature(&cpu->env, ARM_FEATURE_M)) { 1276 qdev_property_add_static(DEVICE(obj), &arm_cpu_reset_hivecs_property); 1277 } 1278 1279 if (arm_feature(&cpu->env, ARM_FEATURE_AARCH64)) { 1280 object_property_add_uint64_ptr(obj, "rvbar", 1281 &cpu->rvbar_prop, 1282 OBJ_PROP_FLAG_READWRITE); 1283 } 1284 1285 #ifndef CONFIG_USER_ONLY 1286 if (arm_feature(&cpu->env, ARM_FEATURE_EL3)) { 1287 /* Add the has_el3 state CPU property only if EL3 is allowed. This will 1288 * prevent "has_el3" from existing on CPUs which cannot support EL3. 1289 */ 1290 qdev_property_add_static(DEVICE(obj), &arm_cpu_has_el3_property); 1291 1292 object_property_add_link(obj, "secure-memory", 1293 TYPE_MEMORY_REGION, 1294 (Object **)&cpu->secure_memory, 1295 qdev_prop_allow_set_link_before_realize, 1296 OBJ_PROP_LINK_STRONG); 1297 } 1298 1299 if (arm_feature(&cpu->env, ARM_FEATURE_EL2)) { 1300 qdev_property_add_static(DEVICE(obj), &arm_cpu_has_el2_property); 1301 } 1302 #endif 1303 1304 if (arm_feature(&cpu->env, ARM_FEATURE_PMU)) { 1305 cpu->has_pmu = true; 1306 object_property_add_bool(obj, "pmu", arm_get_pmu, arm_set_pmu); 1307 } 1308 1309 /* 1310 * Allow user to turn off VFP and Neon support, but only for TCG -- 1311 * KVM does not currently allow us to lie to the guest about its 1312 * ID/feature registers, so the guest always sees what the host has. 1313 */ 1314 if (arm_feature(&cpu->env, ARM_FEATURE_AARCH64) 1315 ? cpu_isar_feature(aa64_fp_simd, cpu) 1316 : cpu_isar_feature(aa32_vfp, cpu)) { 1317 cpu->has_vfp = true; 1318 if (!kvm_enabled()) { 1319 qdev_property_add_static(DEVICE(obj), &arm_cpu_has_vfp_property); 1320 } 1321 } 1322 1323 if (arm_feature(&cpu->env, ARM_FEATURE_NEON)) { 1324 cpu->has_neon = true; 1325 if (!kvm_enabled()) { 1326 qdev_property_add_static(DEVICE(obj), &arm_cpu_has_neon_property); 1327 } 1328 } 1329 1330 if (arm_feature(&cpu->env, ARM_FEATURE_M) && 1331 arm_feature(&cpu->env, ARM_FEATURE_THUMB_DSP)) { 1332 qdev_property_add_static(DEVICE(obj), &arm_cpu_has_dsp_property); 1333 } 1334 1335 if (arm_feature(&cpu->env, ARM_FEATURE_PMSA)) { 1336 qdev_property_add_static(DEVICE(obj), &arm_cpu_has_mpu_property); 1337 if (arm_feature(&cpu->env, ARM_FEATURE_V7)) { 1338 qdev_property_add_static(DEVICE(obj), 1339 &arm_cpu_pmsav7_dregion_property); 1340 } 1341 } 1342 1343 if (arm_feature(&cpu->env, ARM_FEATURE_M_SECURITY)) { 1344 object_property_add_link(obj, "idau", TYPE_IDAU_INTERFACE, &cpu->idau, 1345 qdev_prop_allow_set_link_before_realize, 1346 OBJ_PROP_LINK_STRONG); 1347 /* 1348 * M profile: initial value of the Secure VTOR. We can't just use 1349 * a simple DEFINE_PROP_UINT32 for this because we want to permit 1350 * the property to be set after realize. 1351 */ 1352 object_property_add_uint32_ptr(obj, "init-svtor", 1353 &cpu->init_svtor, 1354 OBJ_PROP_FLAG_READWRITE); 1355 } 1356 if (arm_feature(&cpu->env, ARM_FEATURE_M)) { 1357 /* 1358 * Initial value of the NS VTOR (for cores without the Security 1359 * extension, this is the only VTOR) 1360 */ 1361 object_property_add_uint32_ptr(obj, "init-nsvtor", 1362 &cpu->init_nsvtor, 1363 OBJ_PROP_FLAG_READWRITE); 1364 } 1365 1366 /* Not DEFINE_PROP_UINT32: we want this to be settable after realize */ 1367 object_property_add_uint32_ptr(obj, "psci-conduit", 1368 &cpu->psci_conduit, 1369 OBJ_PROP_FLAG_READWRITE); 1370 1371 qdev_property_add_static(DEVICE(obj), &arm_cpu_cfgend_property); 1372 1373 if (arm_feature(&cpu->env, ARM_FEATURE_GENERIC_TIMER)) { 1374 qdev_property_add_static(DEVICE(cpu), &arm_cpu_gt_cntfrq_property); 1375 } 1376 1377 if (kvm_enabled()) { 1378 kvm_arm_add_vcpu_properties(obj); 1379 } 1380 1381 #ifndef CONFIG_USER_ONLY 1382 if (arm_feature(&cpu->env, ARM_FEATURE_AARCH64) && 1383 cpu_isar_feature(aa64_mte, cpu)) { 1384 object_property_add_link(obj, "tag-memory", 1385 TYPE_MEMORY_REGION, 1386 (Object **)&cpu->tag_memory, 1387 qdev_prop_allow_set_link_before_realize, 1388 OBJ_PROP_LINK_STRONG); 1389 1390 if (arm_feature(&cpu->env, ARM_FEATURE_EL3)) { 1391 object_property_add_link(obj, "secure-tag-memory", 1392 TYPE_MEMORY_REGION, 1393 (Object **)&cpu->secure_tag_memory, 1394 qdev_prop_allow_set_link_before_realize, 1395 OBJ_PROP_LINK_STRONG); 1396 } 1397 } 1398 #endif 1399 } 1400 1401 static void arm_cpu_finalizefn(Object *obj) 1402 { 1403 ARMCPU *cpu = ARM_CPU(obj); 1404 ARMELChangeHook *hook, *next; 1405 1406 g_hash_table_destroy(cpu->cp_regs); 1407 1408 QLIST_FOREACH_SAFE(hook, &cpu->pre_el_change_hooks, node, next) { 1409 QLIST_REMOVE(hook, node); 1410 g_free(hook); 1411 } 1412 QLIST_FOREACH_SAFE(hook, &cpu->el_change_hooks, node, next) { 1413 QLIST_REMOVE(hook, node); 1414 g_free(hook); 1415 } 1416 #ifndef CONFIG_USER_ONLY 1417 if (cpu->pmu_timer) { 1418 timer_free(cpu->pmu_timer); 1419 } 1420 #endif 1421 } 1422 1423 void arm_cpu_finalize_features(ARMCPU *cpu, Error **errp) 1424 { 1425 Error *local_err = NULL; 1426 1427 #ifdef TARGET_AARCH64 1428 if (arm_feature(&cpu->env, ARM_FEATURE_AARCH64)) { 1429 arm_cpu_sve_finalize(cpu, &local_err); 1430 if (local_err != NULL) { 1431 error_propagate(errp, local_err); 1432 return; 1433 } 1434 1435 arm_cpu_sme_finalize(cpu, &local_err); 1436 if (local_err != NULL) { 1437 error_propagate(errp, local_err); 1438 return; 1439 } 1440 1441 arm_cpu_pauth_finalize(cpu, &local_err); 1442 if (local_err != NULL) { 1443 error_propagate(errp, local_err); 1444 return; 1445 } 1446 1447 arm_cpu_lpa2_finalize(cpu, &local_err); 1448 if (local_err != NULL) { 1449 error_propagate(errp, local_err); 1450 return; 1451 } 1452 } 1453 #endif 1454 1455 if (kvm_enabled()) { 1456 kvm_arm_steal_time_finalize(cpu, &local_err); 1457 if (local_err != NULL) { 1458 error_propagate(errp, local_err); 1459 return; 1460 } 1461 } 1462 } 1463 1464 static void arm_cpu_realizefn(DeviceState *dev, Error **errp) 1465 { 1466 CPUState *cs = CPU(dev); 1467 ARMCPU *cpu = ARM_CPU(dev); 1468 ARMCPUClass *acc = ARM_CPU_GET_CLASS(dev); 1469 CPUARMState *env = &cpu->env; 1470 int pagebits; 1471 Error *local_err = NULL; 1472 bool no_aa32 = false; 1473 1474 /* If we needed to query the host kernel for the CPU features 1475 * then it's possible that might have failed in the initfn, but 1476 * this is the first point where we can report it. 1477 */ 1478 if (cpu->host_cpu_probe_failed) { 1479 if (!kvm_enabled() && !hvf_enabled()) { 1480 error_setg(errp, "The 'host' CPU type can only be used with KVM or HVF"); 1481 } else { 1482 error_setg(errp, "Failed to retrieve host CPU features"); 1483 } 1484 return; 1485 } 1486 1487 #ifndef CONFIG_USER_ONLY 1488 /* The NVIC and M-profile CPU are two halves of a single piece of 1489 * hardware; trying to use one without the other is a command line 1490 * error and will result in segfaults if not caught here. 1491 */ 1492 if (arm_feature(env, ARM_FEATURE_M)) { 1493 if (!env->nvic) { 1494 error_setg(errp, "This board cannot be used with Cortex-M CPUs"); 1495 return; 1496 } 1497 } else { 1498 if (env->nvic) { 1499 error_setg(errp, "This board can only be used with Cortex-M CPUs"); 1500 return; 1501 } 1502 } 1503 1504 if (!tcg_enabled() && !qtest_enabled()) { 1505 /* 1506 * We assume that no accelerator except TCG (and the "not really an 1507 * accelerator" qtest) can handle these features, because Arm hardware 1508 * virtualization can't virtualize them. 1509 * 1510 * Catch all the cases which might cause us to create more than one 1511 * address space for the CPU (otherwise we will assert() later in 1512 * cpu_address_space_init()). 1513 */ 1514 if (arm_feature(env, ARM_FEATURE_M)) { 1515 error_setg(errp, 1516 "Cannot enable %s when using an M-profile guest CPU", 1517 current_accel_name()); 1518 return; 1519 } 1520 if (cpu->has_el3) { 1521 error_setg(errp, 1522 "Cannot enable %s when guest CPU has EL3 enabled", 1523 current_accel_name()); 1524 return; 1525 } 1526 if (cpu->tag_memory) { 1527 error_setg(errp, 1528 "Cannot enable %s when guest CPUs has MTE enabled", 1529 current_accel_name()); 1530 return; 1531 } 1532 } 1533 1534 { 1535 uint64_t scale; 1536 1537 if (arm_feature(env, ARM_FEATURE_GENERIC_TIMER)) { 1538 if (!cpu->gt_cntfrq_hz) { 1539 error_setg(errp, "Invalid CNTFRQ: %"PRId64"Hz", 1540 cpu->gt_cntfrq_hz); 1541 return; 1542 } 1543 scale = gt_cntfrq_period_ns(cpu); 1544 } else { 1545 scale = GTIMER_SCALE; 1546 } 1547 1548 cpu->gt_timer[GTIMER_PHYS] = timer_new(QEMU_CLOCK_VIRTUAL, scale, 1549 arm_gt_ptimer_cb, cpu); 1550 cpu->gt_timer[GTIMER_VIRT] = timer_new(QEMU_CLOCK_VIRTUAL, scale, 1551 arm_gt_vtimer_cb, cpu); 1552 cpu->gt_timer[GTIMER_HYP] = timer_new(QEMU_CLOCK_VIRTUAL, scale, 1553 arm_gt_htimer_cb, cpu); 1554 cpu->gt_timer[GTIMER_SEC] = timer_new(QEMU_CLOCK_VIRTUAL, scale, 1555 arm_gt_stimer_cb, cpu); 1556 cpu->gt_timer[GTIMER_HYPVIRT] = timer_new(QEMU_CLOCK_VIRTUAL, scale, 1557 arm_gt_hvtimer_cb, cpu); 1558 } 1559 #endif 1560 1561 cpu_exec_realizefn(cs, &local_err); 1562 if (local_err != NULL) { 1563 error_propagate(errp, local_err); 1564 return; 1565 } 1566 1567 arm_cpu_finalize_features(cpu, &local_err); 1568 if (local_err != NULL) { 1569 error_propagate(errp, local_err); 1570 return; 1571 } 1572 1573 if (arm_feature(env, ARM_FEATURE_AARCH64) && 1574 cpu->has_vfp != cpu->has_neon) { 1575 /* 1576 * This is an architectural requirement for AArch64; AArch32 is 1577 * more flexible and permits VFP-no-Neon and Neon-no-VFP. 1578 */ 1579 error_setg(errp, 1580 "AArch64 CPUs must have both VFP and Neon or neither"); 1581 return; 1582 } 1583 1584 if (!cpu->has_vfp) { 1585 uint64_t t; 1586 uint32_t u; 1587 1588 t = cpu->isar.id_aa64isar1; 1589 t = FIELD_DP64(t, ID_AA64ISAR1, JSCVT, 0); 1590 cpu->isar.id_aa64isar1 = t; 1591 1592 t = cpu->isar.id_aa64pfr0; 1593 t = FIELD_DP64(t, ID_AA64PFR0, FP, 0xf); 1594 cpu->isar.id_aa64pfr0 = t; 1595 1596 u = cpu->isar.id_isar6; 1597 u = FIELD_DP32(u, ID_ISAR6, JSCVT, 0); 1598 u = FIELD_DP32(u, ID_ISAR6, BF16, 0); 1599 cpu->isar.id_isar6 = u; 1600 1601 u = cpu->isar.mvfr0; 1602 u = FIELD_DP32(u, MVFR0, FPSP, 0); 1603 u = FIELD_DP32(u, MVFR0, FPDP, 0); 1604 u = FIELD_DP32(u, MVFR0, FPDIVIDE, 0); 1605 u = FIELD_DP32(u, MVFR0, FPSQRT, 0); 1606 u = FIELD_DP32(u, MVFR0, FPROUND, 0); 1607 if (!arm_feature(env, ARM_FEATURE_M)) { 1608 u = FIELD_DP32(u, MVFR0, FPTRAP, 0); 1609 u = FIELD_DP32(u, MVFR0, FPSHVEC, 0); 1610 } 1611 cpu->isar.mvfr0 = u; 1612 1613 u = cpu->isar.mvfr1; 1614 u = FIELD_DP32(u, MVFR1, FPFTZ, 0); 1615 u = FIELD_DP32(u, MVFR1, FPDNAN, 0); 1616 u = FIELD_DP32(u, MVFR1, FPHP, 0); 1617 if (arm_feature(env, ARM_FEATURE_M)) { 1618 u = FIELD_DP32(u, MVFR1, FP16, 0); 1619 } 1620 cpu->isar.mvfr1 = u; 1621 1622 u = cpu->isar.mvfr2; 1623 u = FIELD_DP32(u, MVFR2, FPMISC, 0); 1624 cpu->isar.mvfr2 = u; 1625 } 1626 1627 if (!cpu->has_neon) { 1628 uint64_t t; 1629 uint32_t u; 1630 1631 unset_feature(env, ARM_FEATURE_NEON); 1632 1633 t = cpu->isar.id_aa64isar0; 1634 t = FIELD_DP64(t, ID_AA64ISAR0, AES, 0); 1635 t = FIELD_DP64(t, ID_AA64ISAR0, SHA1, 0); 1636 t = FIELD_DP64(t, ID_AA64ISAR0, SHA2, 0); 1637 t = FIELD_DP64(t, ID_AA64ISAR0, SHA3, 0); 1638 t = FIELD_DP64(t, ID_AA64ISAR0, SM3, 0); 1639 t = FIELD_DP64(t, ID_AA64ISAR0, SM4, 0); 1640 t = FIELD_DP64(t, ID_AA64ISAR0, DP, 0); 1641 cpu->isar.id_aa64isar0 = t; 1642 1643 t = cpu->isar.id_aa64isar1; 1644 t = FIELD_DP64(t, ID_AA64ISAR1, FCMA, 0); 1645 t = FIELD_DP64(t, ID_AA64ISAR1, BF16, 0); 1646 t = FIELD_DP64(t, ID_AA64ISAR1, I8MM, 0); 1647 cpu->isar.id_aa64isar1 = t; 1648 1649 t = cpu->isar.id_aa64pfr0; 1650 t = FIELD_DP64(t, ID_AA64PFR0, ADVSIMD, 0xf); 1651 cpu->isar.id_aa64pfr0 = t; 1652 1653 u = cpu->isar.id_isar5; 1654 u = FIELD_DP32(u, ID_ISAR5, AES, 0); 1655 u = FIELD_DP32(u, ID_ISAR5, SHA1, 0); 1656 u = FIELD_DP32(u, ID_ISAR5, SHA2, 0); 1657 u = FIELD_DP32(u, ID_ISAR5, RDM, 0); 1658 u = FIELD_DP32(u, ID_ISAR5, VCMA, 0); 1659 cpu->isar.id_isar5 = u; 1660 1661 u = cpu->isar.id_isar6; 1662 u = FIELD_DP32(u, ID_ISAR6, DP, 0); 1663 u = FIELD_DP32(u, ID_ISAR6, FHM, 0); 1664 u = FIELD_DP32(u, ID_ISAR6, BF16, 0); 1665 u = FIELD_DP32(u, ID_ISAR6, I8MM, 0); 1666 cpu->isar.id_isar6 = u; 1667 1668 if (!arm_feature(env, ARM_FEATURE_M)) { 1669 u = cpu->isar.mvfr1; 1670 u = FIELD_DP32(u, MVFR1, SIMDLS, 0); 1671 u = FIELD_DP32(u, MVFR1, SIMDINT, 0); 1672 u = FIELD_DP32(u, MVFR1, SIMDSP, 0); 1673 u = FIELD_DP32(u, MVFR1, SIMDHP, 0); 1674 cpu->isar.mvfr1 = u; 1675 1676 u = cpu->isar.mvfr2; 1677 u = FIELD_DP32(u, MVFR2, SIMDMISC, 0); 1678 cpu->isar.mvfr2 = u; 1679 } 1680 } 1681 1682 if (!cpu->has_neon && !cpu->has_vfp) { 1683 uint64_t t; 1684 uint32_t u; 1685 1686 t = cpu->isar.id_aa64isar0; 1687 t = FIELD_DP64(t, ID_AA64ISAR0, FHM, 0); 1688 cpu->isar.id_aa64isar0 = t; 1689 1690 t = cpu->isar.id_aa64isar1; 1691 t = FIELD_DP64(t, ID_AA64ISAR1, FRINTTS, 0); 1692 cpu->isar.id_aa64isar1 = t; 1693 1694 u = cpu->isar.mvfr0; 1695 u = FIELD_DP32(u, MVFR0, SIMDREG, 0); 1696 cpu->isar.mvfr0 = u; 1697 1698 /* Despite the name, this field covers both VFP and Neon */ 1699 u = cpu->isar.mvfr1; 1700 u = FIELD_DP32(u, MVFR1, SIMDFMAC, 0); 1701 cpu->isar.mvfr1 = u; 1702 } 1703 1704 if (arm_feature(env, ARM_FEATURE_M) && !cpu->has_dsp) { 1705 uint32_t u; 1706 1707 unset_feature(env, ARM_FEATURE_THUMB_DSP); 1708 1709 u = cpu->isar.id_isar1; 1710 u = FIELD_DP32(u, ID_ISAR1, EXTEND, 1); 1711 cpu->isar.id_isar1 = u; 1712 1713 u = cpu->isar.id_isar2; 1714 u = FIELD_DP32(u, ID_ISAR2, MULTU, 1); 1715 u = FIELD_DP32(u, ID_ISAR2, MULTS, 1); 1716 cpu->isar.id_isar2 = u; 1717 1718 u = cpu->isar.id_isar3; 1719 u = FIELD_DP32(u, ID_ISAR3, SIMD, 1); 1720 u = FIELD_DP32(u, ID_ISAR3, SATURATE, 0); 1721 cpu->isar.id_isar3 = u; 1722 } 1723 1724 /* Some features automatically imply others: */ 1725 if (arm_feature(env, ARM_FEATURE_V8)) { 1726 if (arm_feature(env, ARM_FEATURE_M)) { 1727 set_feature(env, ARM_FEATURE_V7); 1728 } else { 1729 set_feature(env, ARM_FEATURE_V7VE); 1730 } 1731 } 1732 1733 /* 1734 * There exist AArch64 cpus without AArch32 support. When KVM 1735 * queries ID_ISAR0_EL1 on such a host, the value is UNKNOWN. 1736 * Similarly, we cannot check ID_AA64PFR0 without AArch64 support. 1737 * As a general principle, we also do not make ID register 1738 * consistency checks anywhere unless using TCG, because only 1739 * for TCG would a consistency-check failure be a QEMU bug. 1740 */ 1741 if (arm_feature(&cpu->env, ARM_FEATURE_AARCH64)) { 1742 no_aa32 = !cpu_isar_feature(aa64_aa32, cpu); 1743 } 1744 1745 if (arm_feature(env, ARM_FEATURE_V7VE)) { 1746 /* v7 Virtualization Extensions. In real hardware this implies 1747 * EL2 and also the presence of the Security Extensions. 1748 * For QEMU, for backwards-compatibility we implement some 1749 * CPUs or CPU configs which have no actual EL2 or EL3 but do 1750 * include the various other features that V7VE implies. 1751 * Presence of EL2 itself is ARM_FEATURE_EL2, and of the 1752 * Security Extensions is ARM_FEATURE_EL3. 1753 */ 1754 assert(!tcg_enabled() || no_aa32 || 1755 cpu_isar_feature(aa32_arm_div, cpu)); 1756 set_feature(env, ARM_FEATURE_LPAE); 1757 set_feature(env, ARM_FEATURE_V7); 1758 } 1759 if (arm_feature(env, ARM_FEATURE_V7)) { 1760 set_feature(env, ARM_FEATURE_VAPA); 1761 set_feature(env, ARM_FEATURE_THUMB2); 1762 set_feature(env, ARM_FEATURE_MPIDR); 1763 if (!arm_feature(env, ARM_FEATURE_M)) { 1764 set_feature(env, ARM_FEATURE_V6K); 1765 } else { 1766 set_feature(env, ARM_FEATURE_V6); 1767 } 1768 1769 /* Always define VBAR for V7 CPUs even if it doesn't exist in 1770 * non-EL3 configs. This is needed by some legacy boards. 1771 */ 1772 set_feature(env, ARM_FEATURE_VBAR); 1773 } 1774 if (arm_feature(env, ARM_FEATURE_V6K)) { 1775 set_feature(env, ARM_FEATURE_V6); 1776 set_feature(env, ARM_FEATURE_MVFR); 1777 } 1778 if (arm_feature(env, ARM_FEATURE_V6)) { 1779 set_feature(env, ARM_FEATURE_V5); 1780 if (!arm_feature(env, ARM_FEATURE_M)) { 1781 assert(!tcg_enabled() || no_aa32 || 1782 cpu_isar_feature(aa32_jazelle, cpu)); 1783 set_feature(env, ARM_FEATURE_AUXCR); 1784 } 1785 } 1786 if (arm_feature(env, ARM_FEATURE_V5)) { 1787 set_feature(env, ARM_FEATURE_V4T); 1788 } 1789 if (arm_feature(env, ARM_FEATURE_LPAE)) { 1790 set_feature(env, ARM_FEATURE_V7MP); 1791 } 1792 if (arm_feature(env, ARM_FEATURE_CBAR_RO)) { 1793 set_feature(env, ARM_FEATURE_CBAR); 1794 } 1795 if (arm_feature(env, ARM_FEATURE_THUMB2) && 1796 !arm_feature(env, ARM_FEATURE_M)) { 1797 set_feature(env, ARM_FEATURE_THUMB_DSP); 1798 } 1799 1800 /* 1801 * We rely on no XScale CPU having VFP so we can use the same bits in the 1802 * TB flags field for VECSTRIDE and XSCALE_CPAR. 1803 */ 1804 assert(arm_feature(&cpu->env, ARM_FEATURE_AARCH64) || 1805 !cpu_isar_feature(aa32_vfp_simd, cpu) || 1806 !arm_feature(env, ARM_FEATURE_XSCALE)); 1807 1808 if (arm_feature(env, ARM_FEATURE_V7) && 1809 !arm_feature(env, ARM_FEATURE_M) && 1810 !arm_feature(env, ARM_FEATURE_PMSA)) { 1811 /* v7VMSA drops support for the old ARMv5 tiny pages, so we 1812 * can use 4K pages. 1813 */ 1814 pagebits = 12; 1815 } else { 1816 /* For CPUs which might have tiny 1K pages, or which have an 1817 * MPU and might have small region sizes, stick with 1K pages. 1818 */ 1819 pagebits = 10; 1820 } 1821 if (!set_preferred_target_page_bits(pagebits)) { 1822 /* This can only ever happen for hotplugging a CPU, or if 1823 * the board code incorrectly creates a CPU which it has 1824 * promised via minimum_page_size that it will not. 1825 */ 1826 error_setg(errp, "This CPU requires a smaller page size than the " 1827 "system is using"); 1828 return; 1829 } 1830 1831 /* This cpu-id-to-MPIDR affinity is used only for TCG; KVM will override it. 1832 * We don't support setting cluster ID ([16..23]) (known as Aff2 1833 * in later ARM ARM versions), or any of the higher affinity level fields, 1834 * so these bits always RAZ. 1835 */ 1836 if (cpu->mp_affinity == ARM64_AFFINITY_INVALID) { 1837 cpu->mp_affinity = arm_cpu_mp_affinity(cs->cpu_index, 1838 ARM_DEFAULT_CPUS_PER_CLUSTER); 1839 } 1840 1841 if (cpu->reset_hivecs) { 1842 cpu->reset_sctlr |= (1 << 13); 1843 } 1844 1845 if (cpu->cfgend) { 1846 if (arm_feature(&cpu->env, ARM_FEATURE_V7)) { 1847 cpu->reset_sctlr |= SCTLR_EE; 1848 } else { 1849 cpu->reset_sctlr |= SCTLR_B; 1850 } 1851 } 1852 1853 if (!arm_feature(env, ARM_FEATURE_M) && !cpu->has_el3) { 1854 /* If the has_el3 CPU property is disabled then we need to disable the 1855 * feature. 1856 */ 1857 unset_feature(env, ARM_FEATURE_EL3); 1858 1859 /* 1860 * Disable the security extension feature bits in the processor 1861 * feature registers as well. 1862 */ 1863 cpu->isar.id_pfr1 = FIELD_DP32(cpu->isar.id_pfr1, ID_PFR1, SECURITY, 0); 1864 cpu->isar.id_dfr0 = FIELD_DP32(cpu->isar.id_dfr0, ID_DFR0, COPSDBG, 0); 1865 cpu->isar.id_aa64pfr0 = FIELD_DP64(cpu->isar.id_aa64pfr0, 1866 ID_AA64PFR0, EL3, 0); 1867 } 1868 1869 if (!cpu->has_el2) { 1870 unset_feature(env, ARM_FEATURE_EL2); 1871 } 1872 1873 if (!cpu->has_pmu) { 1874 unset_feature(env, ARM_FEATURE_PMU); 1875 } 1876 if (arm_feature(env, ARM_FEATURE_PMU)) { 1877 pmu_init(cpu); 1878 1879 if (!kvm_enabled()) { 1880 arm_register_pre_el_change_hook(cpu, &pmu_pre_el_change, 0); 1881 arm_register_el_change_hook(cpu, &pmu_post_el_change, 0); 1882 } 1883 1884 #ifndef CONFIG_USER_ONLY 1885 cpu->pmu_timer = timer_new_ns(QEMU_CLOCK_VIRTUAL, arm_pmu_timer_cb, 1886 cpu); 1887 #endif 1888 } else { 1889 cpu->isar.id_aa64dfr0 = 1890 FIELD_DP64(cpu->isar.id_aa64dfr0, ID_AA64DFR0, PMUVER, 0); 1891 cpu->isar.id_dfr0 = FIELD_DP32(cpu->isar.id_dfr0, ID_DFR0, PERFMON, 0); 1892 cpu->pmceid0 = 0; 1893 cpu->pmceid1 = 0; 1894 } 1895 1896 if (!arm_feature(env, ARM_FEATURE_EL2)) { 1897 /* 1898 * Disable the hypervisor feature bits in the processor feature 1899 * registers if we don't have EL2. 1900 */ 1901 cpu->isar.id_aa64pfr0 = FIELD_DP64(cpu->isar.id_aa64pfr0, 1902 ID_AA64PFR0, EL2, 0); 1903 cpu->isar.id_pfr1 = FIELD_DP32(cpu->isar.id_pfr1, 1904 ID_PFR1, VIRTUALIZATION, 0); 1905 } 1906 1907 #ifndef CONFIG_USER_ONLY 1908 if (cpu->tag_memory == NULL && cpu_isar_feature(aa64_mte, cpu)) { 1909 /* 1910 * Disable the MTE feature bits if we do not have tag-memory 1911 * provided by the machine. 1912 */ 1913 cpu->isar.id_aa64pfr1 = 1914 FIELD_DP64(cpu->isar.id_aa64pfr1, ID_AA64PFR1, MTE, 0); 1915 } 1916 #endif 1917 1918 /* MPU can be configured out of a PMSA CPU either by setting has-mpu 1919 * to false or by setting pmsav7-dregion to 0. 1920 */ 1921 if (!cpu->has_mpu) { 1922 cpu->pmsav7_dregion = 0; 1923 } 1924 if (cpu->pmsav7_dregion == 0) { 1925 cpu->has_mpu = false; 1926 } 1927 1928 if (arm_feature(env, ARM_FEATURE_PMSA) && 1929 arm_feature(env, ARM_FEATURE_V7)) { 1930 uint32_t nr = cpu->pmsav7_dregion; 1931 1932 if (nr > 0xff) { 1933 error_setg(errp, "PMSAv7 MPU #regions invalid %" PRIu32, nr); 1934 return; 1935 } 1936 1937 if (nr) { 1938 if (arm_feature(env, ARM_FEATURE_V8)) { 1939 /* PMSAv8 */ 1940 env->pmsav8.rbar[M_REG_NS] = g_new0(uint32_t, nr); 1941 env->pmsav8.rlar[M_REG_NS] = g_new0(uint32_t, nr); 1942 if (arm_feature(env, ARM_FEATURE_M_SECURITY)) { 1943 env->pmsav8.rbar[M_REG_S] = g_new0(uint32_t, nr); 1944 env->pmsav8.rlar[M_REG_S] = g_new0(uint32_t, nr); 1945 } 1946 } else { 1947 env->pmsav7.drbar = g_new0(uint32_t, nr); 1948 env->pmsav7.drsr = g_new0(uint32_t, nr); 1949 env->pmsav7.dracr = g_new0(uint32_t, nr); 1950 } 1951 } 1952 } 1953 1954 if (arm_feature(env, ARM_FEATURE_M_SECURITY)) { 1955 uint32_t nr = cpu->sau_sregion; 1956 1957 if (nr > 0xff) { 1958 error_setg(errp, "v8M SAU #regions invalid %" PRIu32, nr); 1959 return; 1960 } 1961 1962 if (nr) { 1963 env->sau.rbar = g_new0(uint32_t, nr); 1964 env->sau.rlar = g_new0(uint32_t, nr); 1965 } 1966 } 1967 1968 if (arm_feature(env, ARM_FEATURE_EL3)) { 1969 set_feature(env, ARM_FEATURE_VBAR); 1970 } 1971 1972 register_cp_regs_for_features(cpu); 1973 arm_cpu_register_gdb_regs_for_features(cpu); 1974 1975 init_cpreg_list(cpu); 1976 1977 #ifndef CONFIG_USER_ONLY 1978 MachineState *ms = MACHINE(qdev_get_machine()); 1979 unsigned int smp_cpus = ms->smp.cpus; 1980 bool has_secure = cpu->has_el3 || arm_feature(env, ARM_FEATURE_M_SECURITY); 1981 1982 /* 1983 * We must set cs->num_ases to the final value before 1984 * the first call to cpu_address_space_init. 1985 */ 1986 if (cpu->tag_memory != NULL) { 1987 cs->num_ases = 3 + has_secure; 1988 } else { 1989 cs->num_ases = 1 + has_secure; 1990 } 1991 1992 if (has_secure) { 1993 if (!cpu->secure_memory) { 1994 cpu->secure_memory = cs->memory; 1995 } 1996 cpu_address_space_init(cs, ARMASIdx_S, "cpu-secure-memory", 1997 cpu->secure_memory); 1998 } 1999 2000 if (cpu->tag_memory != NULL) { 2001 cpu_address_space_init(cs, ARMASIdx_TagNS, "cpu-tag-memory", 2002 cpu->tag_memory); 2003 if (has_secure) { 2004 cpu_address_space_init(cs, ARMASIdx_TagS, "cpu-tag-memory", 2005 cpu->secure_tag_memory); 2006 } 2007 } 2008 2009 cpu_address_space_init(cs, ARMASIdx_NS, "cpu-memory", cs->memory); 2010 2011 /* No core_count specified, default to smp_cpus. */ 2012 if (cpu->core_count == -1) { 2013 cpu->core_count = smp_cpus; 2014 } 2015 #endif 2016 2017 if (tcg_enabled()) { 2018 int dcz_blocklen = 4 << cpu->dcz_blocksize; 2019 2020 /* 2021 * We only support DCZ blocklen that fits on one page. 2022 * 2023 * Architectually this is always true. However TARGET_PAGE_SIZE 2024 * is variable and, for compatibility with -machine virt-2.7, 2025 * is only 1KiB, as an artifact of legacy ARMv5 subpage support. 2026 * But even then, while the largest architectural DCZ blocklen 2027 * is 2KiB, no cpu actually uses such a large blocklen. 2028 */ 2029 assert(dcz_blocklen <= TARGET_PAGE_SIZE); 2030 2031 /* 2032 * We only support DCZ blocksize >= 2*TAG_GRANULE, which is to say 2033 * both nibbles of each byte storing tag data may be written at once. 2034 * Since TAG_GRANULE is 16, this means that blocklen must be >= 32. 2035 */ 2036 if (cpu_isar_feature(aa64_mte, cpu)) { 2037 assert(dcz_blocklen >= 2 * TAG_GRANULE); 2038 } 2039 } 2040 2041 qemu_init_vcpu(cs); 2042 cpu_reset(cs); 2043 2044 acc->parent_realize(dev, errp); 2045 } 2046 2047 static ObjectClass *arm_cpu_class_by_name(const char *cpu_model) 2048 { 2049 ObjectClass *oc; 2050 char *typename; 2051 char **cpuname; 2052 const char *cpunamestr; 2053 2054 cpuname = g_strsplit(cpu_model, ",", 1); 2055 cpunamestr = cpuname[0]; 2056 #ifdef CONFIG_USER_ONLY 2057 /* For backwards compatibility usermode emulation allows "-cpu any", 2058 * which has the same semantics as "-cpu max". 2059 */ 2060 if (!strcmp(cpunamestr, "any")) { 2061 cpunamestr = "max"; 2062 } 2063 #endif 2064 typename = g_strdup_printf(ARM_CPU_TYPE_NAME("%s"), cpunamestr); 2065 oc = object_class_by_name(typename); 2066 g_strfreev(cpuname); 2067 g_free(typename); 2068 if (!oc || !object_class_dynamic_cast(oc, TYPE_ARM_CPU) || 2069 object_class_is_abstract(oc)) { 2070 return NULL; 2071 } 2072 return oc; 2073 } 2074 2075 static Property arm_cpu_properties[] = { 2076 DEFINE_PROP_UINT64("midr", ARMCPU, midr, 0), 2077 DEFINE_PROP_UINT64("mp-affinity", ARMCPU, 2078 mp_affinity, ARM64_AFFINITY_INVALID), 2079 DEFINE_PROP_INT32("node-id", ARMCPU, node_id, CPU_UNSET_NUMA_NODE_ID), 2080 DEFINE_PROP_INT32("core-count", ARMCPU, core_count, -1), 2081 DEFINE_PROP_END_OF_LIST() 2082 }; 2083 2084 static gchar *arm_gdb_arch_name(CPUState *cs) 2085 { 2086 ARMCPU *cpu = ARM_CPU(cs); 2087 CPUARMState *env = &cpu->env; 2088 2089 if (arm_feature(env, ARM_FEATURE_IWMMXT)) { 2090 return g_strdup("iwmmxt"); 2091 } 2092 return g_strdup("arm"); 2093 } 2094 2095 #ifndef CONFIG_USER_ONLY 2096 #include "hw/core/sysemu-cpu-ops.h" 2097 2098 static const struct SysemuCPUOps arm_sysemu_ops = { 2099 .get_phys_page_attrs_debug = arm_cpu_get_phys_page_attrs_debug, 2100 .asidx_from_attrs = arm_asidx_from_attrs, 2101 .write_elf32_note = arm_cpu_write_elf32_note, 2102 .write_elf64_note = arm_cpu_write_elf64_note, 2103 .virtio_is_big_endian = arm_cpu_virtio_is_big_endian, 2104 .legacy_vmsd = &vmstate_arm_cpu, 2105 }; 2106 #endif 2107 2108 #ifdef CONFIG_TCG 2109 static const struct TCGCPUOps arm_tcg_ops = { 2110 .initialize = arm_translate_init, 2111 .synchronize_from_tb = arm_cpu_synchronize_from_tb, 2112 .debug_excp_handler = arm_debug_excp_handler, 2113 2114 #ifdef CONFIG_USER_ONLY 2115 .record_sigsegv = arm_cpu_record_sigsegv, 2116 .record_sigbus = arm_cpu_record_sigbus, 2117 #else 2118 .tlb_fill = arm_cpu_tlb_fill, 2119 .cpu_exec_interrupt = arm_cpu_exec_interrupt, 2120 .do_interrupt = arm_cpu_do_interrupt, 2121 .do_transaction_failed = arm_cpu_do_transaction_failed, 2122 .do_unaligned_access = arm_cpu_do_unaligned_access, 2123 .adjust_watchpoint_address = arm_adjust_watchpoint_address, 2124 .debug_check_watchpoint = arm_debug_check_watchpoint, 2125 .debug_check_breakpoint = arm_debug_check_breakpoint, 2126 #endif /* !CONFIG_USER_ONLY */ 2127 }; 2128 #endif /* CONFIG_TCG */ 2129 2130 static void arm_cpu_class_init(ObjectClass *oc, void *data) 2131 { 2132 ARMCPUClass *acc = ARM_CPU_CLASS(oc); 2133 CPUClass *cc = CPU_CLASS(acc); 2134 DeviceClass *dc = DEVICE_CLASS(oc); 2135 2136 device_class_set_parent_realize(dc, arm_cpu_realizefn, 2137 &acc->parent_realize); 2138 2139 device_class_set_props(dc, arm_cpu_properties); 2140 device_class_set_parent_reset(dc, arm_cpu_reset, &acc->parent_reset); 2141 2142 cc->class_by_name = arm_cpu_class_by_name; 2143 cc->has_work = arm_cpu_has_work; 2144 cc->dump_state = arm_cpu_dump_state; 2145 cc->set_pc = arm_cpu_set_pc; 2146 cc->gdb_read_register = arm_cpu_gdb_read_register; 2147 cc->gdb_write_register = arm_cpu_gdb_write_register; 2148 #ifndef CONFIG_USER_ONLY 2149 cc->sysemu_ops = &arm_sysemu_ops; 2150 #endif 2151 cc->gdb_num_core_regs = 26; 2152 cc->gdb_core_xml_file = "arm-core.xml"; 2153 cc->gdb_arch_name = arm_gdb_arch_name; 2154 cc->gdb_get_dynamic_xml = arm_gdb_get_dynamic_xml; 2155 cc->gdb_stop_before_watchpoint = true; 2156 cc->disas_set_info = arm_disas_set_info; 2157 2158 #ifdef CONFIG_TCG 2159 cc->tcg_ops = &arm_tcg_ops; 2160 #endif /* CONFIG_TCG */ 2161 } 2162 2163 static void arm_cpu_instance_init(Object *obj) 2164 { 2165 ARMCPUClass *acc = ARM_CPU_GET_CLASS(obj); 2166 2167 acc->info->initfn(obj); 2168 arm_cpu_post_init(obj); 2169 } 2170 2171 static void cpu_register_class_init(ObjectClass *oc, void *data) 2172 { 2173 ARMCPUClass *acc = ARM_CPU_CLASS(oc); 2174 2175 acc->info = data; 2176 } 2177 2178 void arm_cpu_register(const ARMCPUInfo *info) 2179 { 2180 TypeInfo type_info = { 2181 .parent = TYPE_ARM_CPU, 2182 .instance_size = sizeof(ARMCPU), 2183 .instance_align = __alignof__(ARMCPU), 2184 .instance_init = arm_cpu_instance_init, 2185 .class_size = sizeof(ARMCPUClass), 2186 .class_init = info->class_init ?: cpu_register_class_init, 2187 .class_data = (void *)info, 2188 }; 2189 2190 type_info.name = g_strdup_printf("%s-" TYPE_ARM_CPU, info->name); 2191 type_register(&type_info); 2192 g_free((void *)type_info.name); 2193 } 2194 2195 static const TypeInfo arm_cpu_type_info = { 2196 .name = TYPE_ARM_CPU, 2197 .parent = TYPE_CPU, 2198 .instance_size = sizeof(ARMCPU), 2199 .instance_align = __alignof__(ARMCPU), 2200 .instance_init = arm_cpu_initfn, 2201 .instance_finalize = arm_cpu_finalizefn, 2202 .abstract = true, 2203 .class_size = sizeof(ARMCPUClass), 2204 .class_init = arm_cpu_class_init, 2205 }; 2206 2207 static void arm_cpu_register_types(void) 2208 { 2209 type_register_static(&arm_cpu_type_info); 2210 } 2211 2212 type_init(arm_cpu_register_types) 2213