1 /* 2 * QEMU ARM CPU 3 * 4 * Copyright (c) 2012 SUSE LINUX Products GmbH 5 * 6 * This program is free software; you can redistribute it and/or 7 * modify it under the terms of the GNU General Public License 8 * as published by the Free Software Foundation; either version 2 9 * of the License, or (at your option) any later version. 10 * 11 * This program is distributed in the hope that it will be useful, 12 * but WITHOUT ANY WARRANTY; without even the implied warranty of 13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 14 * GNU General Public License for more details. 15 * 16 * You should have received a copy of the GNU General Public License 17 * along with this program; if not, see 18 * <http://www.gnu.org/licenses/gpl-2.0.html> 19 */ 20 21 #include "qemu/osdep.h" 22 #include "qemu/qemu-print.h" 23 #include "qemu/timer.h" 24 #include "qemu/log.h" 25 #include "exec/page-vary.h" 26 #include "target/arm/idau.h" 27 #include "qemu/module.h" 28 #include "qapi/error.h" 29 #include "qapi/visitor.h" 30 #include "cpu.h" 31 #ifdef CONFIG_TCG 32 #include "hw/core/tcg-cpu-ops.h" 33 #endif /* CONFIG_TCG */ 34 #include "internals.h" 35 #include "exec/exec-all.h" 36 #include "hw/qdev-properties.h" 37 #if !defined(CONFIG_USER_ONLY) 38 #include "hw/loader.h" 39 #include "hw/boards.h" 40 #endif 41 #include "sysemu/tcg.h" 42 #include "sysemu/hw_accel.h" 43 #include "kvm_arm.h" 44 #include "disas/capstone.h" 45 #include "fpu/softfloat.h" 46 #include "cpregs.h" 47 48 static void arm_cpu_set_pc(CPUState *cs, vaddr value) 49 { 50 ARMCPU *cpu = ARM_CPU(cs); 51 CPUARMState *env = &cpu->env; 52 53 if (is_a64(env)) { 54 env->pc = value; 55 env->thumb = false; 56 } else { 57 env->regs[15] = value & ~1; 58 env->thumb = value & 1; 59 } 60 } 61 62 #ifdef CONFIG_TCG 63 void arm_cpu_synchronize_from_tb(CPUState *cs, 64 const TranslationBlock *tb) 65 { 66 ARMCPU *cpu = ARM_CPU(cs); 67 CPUARMState *env = &cpu->env; 68 69 /* 70 * It's OK to look at env for the current mode here, because it's 71 * never possible for an AArch64 TB to chain to an AArch32 TB. 72 */ 73 if (is_a64(env)) { 74 env->pc = tb->pc; 75 } else { 76 env->regs[15] = tb->pc; 77 } 78 } 79 #endif /* CONFIG_TCG */ 80 81 static bool arm_cpu_has_work(CPUState *cs) 82 { 83 ARMCPU *cpu = ARM_CPU(cs); 84 85 return (cpu->power_state != PSCI_OFF) 86 && cs->interrupt_request & 87 (CPU_INTERRUPT_FIQ | CPU_INTERRUPT_HARD 88 | CPU_INTERRUPT_VFIQ | CPU_INTERRUPT_VIRQ | CPU_INTERRUPT_VSERR 89 | CPU_INTERRUPT_EXITTB); 90 } 91 92 void arm_register_pre_el_change_hook(ARMCPU *cpu, ARMELChangeHookFn *hook, 93 void *opaque) 94 { 95 ARMELChangeHook *entry = g_new0(ARMELChangeHook, 1); 96 97 entry->hook = hook; 98 entry->opaque = opaque; 99 100 QLIST_INSERT_HEAD(&cpu->pre_el_change_hooks, entry, node); 101 } 102 103 void arm_register_el_change_hook(ARMCPU *cpu, ARMELChangeHookFn *hook, 104 void *opaque) 105 { 106 ARMELChangeHook *entry = g_new0(ARMELChangeHook, 1); 107 108 entry->hook = hook; 109 entry->opaque = opaque; 110 111 QLIST_INSERT_HEAD(&cpu->el_change_hooks, entry, node); 112 } 113 114 static void cp_reg_reset(gpointer key, gpointer value, gpointer opaque) 115 { 116 /* Reset a single ARMCPRegInfo register */ 117 ARMCPRegInfo *ri = value; 118 ARMCPU *cpu = opaque; 119 120 if (ri->type & (ARM_CP_SPECIAL_MASK | ARM_CP_ALIAS)) { 121 return; 122 } 123 124 if (ri->resetfn) { 125 ri->resetfn(&cpu->env, ri); 126 return; 127 } 128 129 /* A zero offset is never possible as it would be regs[0] 130 * so we use it to indicate that reset is being handled elsewhere. 131 * This is basically only used for fields in non-core coprocessors 132 * (like the pxa2xx ones). 133 */ 134 if (!ri->fieldoffset) { 135 return; 136 } 137 138 if (cpreg_field_is_64bit(ri)) { 139 CPREG_FIELD64(&cpu->env, ri) = ri->resetvalue; 140 } else { 141 CPREG_FIELD32(&cpu->env, ri) = ri->resetvalue; 142 } 143 } 144 145 static void cp_reg_check_reset(gpointer key, gpointer value, gpointer opaque) 146 { 147 /* Purely an assertion check: we've already done reset once, 148 * so now check that running the reset for the cpreg doesn't 149 * change its value. This traps bugs where two different cpregs 150 * both try to reset the same state field but to different values. 151 */ 152 ARMCPRegInfo *ri = value; 153 ARMCPU *cpu = opaque; 154 uint64_t oldvalue, newvalue; 155 156 if (ri->type & (ARM_CP_SPECIAL_MASK | ARM_CP_ALIAS | ARM_CP_NO_RAW)) { 157 return; 158 } 159 160 oldvalue = read_raw_cp_reg(&cpu->env, ri); 161 cp_reg_reset(key, value, opaque); 162 newvalue = read_raw_cp_reg(&cpu->env, ri); 163 assert(oldvalue == newvalue); 164 } 165 166 static void arm_cpu_reset(DeviceState *dev) 167 { 168 CPUState *s = CPU(dev); 169 ARMCPU *cpu = ARM_CPU(s); 170 ARMCPUClass *acc = ARM_CPU_GET_CLASS(cpu); 171 CPUARMState *env = &cpu->env; 172 173 acc->parent_reset(dev); 174 175 memset(env, 0, offsetof(CPUARMState, end_reset_fields)); 176 177 g_hash_table_foreach(cpu->cp_regs, cp_reg_reset, cpu); 178 g_hash_table_foreach(cpu->cp_regs, cp_reg_check_reset, cpu); 179 180 env->vfp.xregs[ARM_VFP_FPSID] = cpu->reset_fpsid; 181 env->vfp.xregs[ARM_VFP_MVFR0] = cpu->isar.mvfr0; 182 env->vfp.xregs[ARM_VFP_MVFR1] = cpu->isar.mvfr1; 183 env->vfp.xregs[ARM_VFP_MVFR2] = cpu->isar.mvfr2; 184 185 cpu->power_state = s->start_powered_off ? PSCI_OFF : PSCI_ON; 186 187 if (arm_feature(env, ARM_FEATURE_IWMMXT)) { 188 env->iwmmxt.cregs[ARM_IWMMXT_wCID] = 0x69051000 | 'Q'; 189 } 190 191 if (arm_feature(env, ARM_FEATURE_AARCH64)) { 192 /* 64 bit CPUs always start in 64 bit mode */ 193 env->aarch64 = true; 194 #if defined(CONFIG_USER_ONLY) 195 env->pstate = PSTATE_MODE_EL0t; 196 /* Userspace expects access to DC ZVA, CTL_EL0 and the cache ops */ 197 env->cp15.sctlr_el[1] |= SCTLR_UCT | SCTLR_UCI | SCTLR_DZE; 198 /* Enable all PAC keys. */ 199 env->cp15.sctlr_el[1] |= (SCTLR_EnIA | SCTLR_EnIB | 200 SCTLR_EnDA | SCTLR_EnDB); 201 /* Trap on btype=3 for PACIxSP. */ 202 env->cp15.sctlr_el[1] |= SCTLR_BT0; 203 /* and to the FP/Neon instructions */ 204 env->cp15.cpacr_el1 = deposit64(env->cp15.cpacr_el1, 20, 2, 3); 205 /* and to the SVE instructions */ 206 env->cp15.cpacr_el1 = deposit64(env->cp15.cpacr_el1, 16, 2, 3); 207 /* with reasonable vector length */ 208 if (cpu_isar_feature(aa64_sve, cpu)) { 209 env->vfp.zcr_el[1] = 210 aarch64_sve_zcr_get_valid_len(cpu, cpu->sve_default_vq - 1); 211 } 212 /* 213 * Enable 48-bit address space (TODO: take reserved_va into account). 214 * Enable TBI0 but not TBI1. 215 * Note that this must match useronly_clean_ptr. 216 */ 217 env->cp15.tcr_el[1].raw_tcr = 5 | (1ULL << 37); 218 219 /* Enable MTE */ 220 if (cpu_isar_feature(aa64_mte, cpu)) { 221 /* Enable tag access, but leave TCF0 as No Effect (0). */ 222 env->cp15.sctlr_el[1] |= SCTLR_ATA0; 223 /* 224 * Exclude all tags, so that tag 0 is always used. 225 * This corresponds to Linux current->thread.gcr_incl = 0. 226 * 227 * Set RRND, so that helper_irg() will generate a seed later. 228 * Here in cpu_reset(), the crypto subsystem has not yet been 229 * initialized. 230 */ 231 env->cp15.gcr_el1 = 0x1ffff; 232 } 233 #else 234 /* Reset into the highest available EL */ 235 if (arm_feature(env, ARM_FEATURE_EL3)) { 236 env->pstate = PSTATE_MODE_EL3h; 237 } else if (arm_feature(env, ARM_FEATURE_EL2)) { 238 env->pstate = PSTATE_MODE_EL2h; 239 } else { 240 env->pstate = PSTATE_MODE_EL1h; 241 } 242 243 /* Sample rvbar at reset. */ 244 env->cp15.rvbar = cpu->rvbar_prop; 245 env->pc = env->cp15.rvbar; 246 #endif 247 } else { 248 #if defined(CONFIG_USER_ONLY) 249 /* Userspace expects access to cp10 and cp11 for FP/Neon */ 250 env->cp15.cpacr_el1 = deposit64(env->cp15.cpacr_el1, 20, 4, 0xf); 251 #endif 252 } 253 254 #if defined(CONFIG_USER_ONLY) 255 env->uncached_cpsr = ARM_CPU_MODE_USR; 256 /* For user mode we must enable access to coprocessors */ 257 env->vfp.xregs[ARM_VFP_FPEXC] = 1 << 30; 258 if (arm_feature(env, ARM_FEATURE_IWMMXT)) { 259 env->cp15.c15_cpar = 3; 260 } else if (arm_feature(env, ARM_FEATURE_XSCALE)) { 261 env->cp15.c15_cpar = 1; 262 } 263 #else 264 265 /* 266 * If the highest available EL is EL2, AArch32 will start in Hyp 267 * mode; otherwise it starts in SVC. Note that if we start in 268 * AArch64 then these values in the uncached_cpsr will be ignored. 269 */ 270 if (arm_feature(env, ARM_FEATURE_EL2) && 271 !arm_feature(env, ARM_FEATURE_EL3)) { 272 env->uncached_cpsr = ARM_CPU_MODE_HYP; 273 } else { 274 env->uncached_cpsr = ARM_CPU_MODE_SVC; 275 } 276 env->daif = PSTATE_D | PSTATE_A | PSTATE_I | PSTATE_F; 277 278 /* AArch32 has a hard highvec setting of 0xFFFF0000. If we are currently 279 * executing as AArch32 then check if highvecs are enabled and 280 * adjust the PC accordingly. 281 */ 282 if (A32_BANKED_CURRENT_REG_GET(env, sctlr) & SCTLR_V) { 283 env->regs[15] = 0xFFFF0000; 284 } 285 286 env->vfp.xregs[ARM_VFP_FPEXC] = 0; 287 #endif 288 289 if (arm_feature(env, ARM_FEATURE_M)) { 290 #ifndef CONFIG_USER_ONLY 291 uint32_t initial_msp; /* Loaded from 0x0 */ 292 uint32_t initial_pc; /* Loaded from 0x4 */ 293 uint8_t *rom; 294 uint32_t vecbase; 295 #endif 296 297 if (cpu_isar_feature(aa32_lob, cpu)) { 298 /* 299 * LTPSIZE is constant 4 if MVE not implemented, and resets 300 * to an UNKNOWN value if MVE is implemented. We choose to 301 * always reset to 4. 302 */ 303 env->v7m.ltpsize = 4; 304 /* The LTPSIZE field in FPDSCR is constant and reads as 4. */ 305 env->v7m.fpdscr[M_REG_NS] = 4 << FPCR_LTPSIZE_SHIFT; 306 env->v7m.fpdscr[M_REG_S] = 4 << FPCR_LTPSIZE_SHIFT; 307 } 308 309 if (arm_feature(env, ARM_FEATURE_M_SECURITY)) { 310 env->v7m.secure = true; 311 } else { 312 /* This bit resets to 0 if security is supported, but 1 if 313 * it is not. The bit is not present in v7M, but we set it 314 * here so we can avoid having to make checks on it conditional 315 * on ARM_FEATURE_V8 (we don't let the guest see the bit). 316 */ 317 env->v7m.aircr = R_V7M_AIRCR_BFHFNMINS_MASK; 318 /* 319 * Set NSACR to indicate "NS access permitted to everything"; 320 * this avoids having to have all the tests of it being 321 * conditional on ARM_FEATURE_M_SECURITY. Note also that from 322 * v8.1M the guest-visible value of NSACR in a CPU without the 323 * Security Extension is 0xcff. 324 */ 325 env->v7m.nsacr = 0xcff; 326 } 327 328 /* In v7M the reset value of this bit is IMPDEF, but ARM recommends 329 * that it resets to 1, so QEMU always does that rather than making 330 * it dependent on CPU model. In v8M it is RES1. 331 */ 332 env->v7m.ccr[M_REG_NS] = R_V7M_CCR_STKALIGN_MASK; 333 env->v7m.ccr[M_REG_S] = R_V7M_CCR_STKALIGN_MASK; 334 if (arm_feature(env, ARM_FEATURE_V8)) { 335 /* in v8M the NONBASETHRDENA bit [0] is RES1 */ 336 env->v7m.ccr[M_REG_NS] |= R_V7M_CCR_NONBASETHRDENA_MASK; 337 env->v7m.ccr[M_REG_S] |= R_V7M_CCR_NONBASETHRDENA_MASK; 338 } 339 if (!arm_feature(env, ARM_FEATURE_M_MAIN)) { 340 env->v7m.ccr[M_REG_NS] |= R_V7M_CCR_UNALIGN_TRP_MASK; 341 env->v7m.ccr[M_REG_S] |= R_V7M_CCR_UNALIGN_TRP_MASK; 342 } 343 344 if (cpu_isar_feature(aa32_vfp_simd, cpu)) { 345 env->v7m.fpccr[M_REG_NS] = R_V7M_FPCCR_ASPEN_MASK; 346 env->v7m.fpccr[M_REG_S] = R_V7M_FPCCR_ASPEN_MASK | 347 R_V7M_FPCCR_LSPEN_MASK | R_V7M_FPCCR_S_MASK; 348 } 349 350 #ifndef CONFIG_USER_ONLY 351 /* Unlike A/R profile, M profile defines the reset LR value */ 352 env->regs[14] = 0xffffffff; 353 354 env->v7m.vecbase[M_REG_S] = cpu->init_svtor & 0xffffff80; 355 env->v7m.vecbase[M_REG_NS] = cpu->init_nsvtor & 0xffffff80; 356 357 /* Load the initial SP and PC from offset 0 and 4 in the vector table */ 358 vecbase = env->v7m.vecbase[env->v7m.secure]; 359 rom = rom_ptr_for_as(s->as, vecbase, 8); 360 if (rom) { 361 /* Address zero is covered by ROM which hasn't yet been 362 * copied into physical memory. 363 */ 364 initial_msp = ldl_p(rom); 365 initial_pc = ldl_p(rom + 4); 366 } else { 367 /* Address zero not covered by a ROM blob, or the ROM blob 368 * is in non-modifiable memory and this is a second reset after 369 * it got copied into memory. In the latter case, rom_ptr 370 * will return a NULL pointer and we should use ldl_phys instead. 371 */ 372 initial_msp = ldl_phys(s->as, vecbase); 373 initial_pc = ldl_phys(s->as, vecbase + 4); 374 } 375 376 qemu_log_mask(CPU_LOG_INT, 377 "Loaded reset SP 0x%x PC 0x%x from vector table\n", 378 initial_msp, initial_pc); 379 380 env->regs[13] = initial_msp & 0xFFFFFFFC; 381 env->regs[15] = initial_pc & ~1; 382 env->thumb = initial_pc & 1; 383 #else 384 /* 385 * For user mode we run non-secure and with access to the FPU. 386 * The FPU context is active (ie does not need further setup) 387 * and is owned by non-secure. 388 */ 389 env->v7m.secure = false; 390 env->v7m.nsacr = 0xcff; 391 env->v7m.cpacr[M_REG_NS] = 0xf0ffff; 392 env->v7m.fpccr[M_REG_S] &= 393 ~(R_V7M_FPCCR_LSPEN_MASK | R_V7M_FPCCR_S_MASK); 394 env->v7m.control[M_REG_S] |= R_V7M_CONTROL_FPCA_MASK; 395 #endif 396 } 397 398 /* M profile requires that reset clears the exclusive monitor; 399 * A profile does not, but clearing it makes more sense than having it 400 * set with an exclusive access on address zero. 401 */ 402 arm_clear_exclusive(env); 403 404 if (arm_feature(env, ARM_FEATURE_PMSA)) { 405 if (cpu->pmsav7_dregion > 0) { 406 if (arm_feature(env, ARM_FEATURE_V8)) { 407 memset(env->pmsav8.rbar[M_REG_NS], 0, 408 sizeof(*env->pmsav8.rbar[M_REG_NS]) 409 * cpu->pmsav7_dregion); 410 memset(env->pmsav8.rlar[M_REG_NS], 0, 411 sizeof(*env->pmsav8.rlar[M_REG_NS]) 412 * cpu->pmsav7_dregion); 413 if (arm_feature(env, ARM_FEATURE_M_SECURITY)) { 414 memset(env->pmsav8.rbar[M_REG_S], 0, 415 sizeof(*env->pmsav8.rbar[M_REG_S]) 416 * cpu->pmsav7_dregion); 417 memset(env->pmsav8.rlar[M_REG_S], 0, 418 sizeof(*env->pmsav8.rlar[M_REG_S]) 419 * cpu->pmsav7_dregion); 420 } 421 } else if (arm_feature(env, ARM_FEATURE_V7)) { 422 memset(env->pmsav7.drbar, 0, 423 sizeof(*env->pmsav7.drbar) * cpu->pmsav7_dregion); 424 memset(env->pmsav7.drsr, 0, 425 sizeof(*env->pmsav7.drsr) * cpu->pmsav7_dregion); 426 memset(env->pmsav7.dracr, 0, 427 sizeof(*env->pmsav7.dracr) * cpu->pmsav7_dregion); 428 } 429 } 430 env->pmsav7.rnr[M_REG_NS] = 0; 431 env->pmsav7.rnr[M_REG_S] = 0; 432 env->pmsav8.mair0[M_REG_NS] = 0; 433 env->pmsav8.mair0[M_REG_S] = 0; 434 env->pmsav8.mair1[M_REG_NS] = 0; 435 env->pmsav8.mair1[M_REG_S] = 0; 436 } 437 438 if (arm_feature(env, ARM_FEATURE_M_SECURITY)) { 439 if (cpu->sau_sregion > 0) { 440 memset(env->sau.rbar, 0, sizeof(*env->sau.rbar) * cpu->sau_sregion); 441 memset(env->sau.rlar, 0, sizeof(*env->sau.rlar) * cpu->sau_sregion); 442 } 443 env->sau.rnr = 0; 444 /* SAU_CTRL reset value is IMPDEF; we choose 0, which is what 445 * the Cortex-M33 does. 446 */ 447 env->sau.ctrl = 0; 448 } 449 450 set_flush_to_zero(1, &env->vfp.standard_fp_status); 451 set_flush_inputs_to_zero(1, &env->vfp.standard_fp_status); 452 set_default_nan_mode(1, &env->vfp.standard_fp_status); 453 set_default_nan_mode(1, &env->vfp.standard_fp_status_f16); 454 set_float_detect_tininess(float_tininess_before_rounding, 455 &env->vfp.fp_status); 456 set_float_detect_tininess(float_tininess_before_rounding, 457 &env->vfp.standard_fp_status); 458 set_float_detect_tininess(float_tininess_before_rounding, 459 &env->vfp.fp_status_f16); 460 set_float_detect_tininess(float_tininess_before_rounding, 461 &env->vfp.standard_fp_status_f16); 462 #ifndef CONFIG_USER_ONLY 463 if (kvm_enabled()) { 464 kvm_arm_reset_vcpu(cpu); 465 } 466 #endif 467 468 hw_breakpoint_update_all(cpu); 469 hw_watchpoint_update_all(cpu); 470 arm_rebuild_hflags(env); 471 } 472 473 #ifndef CONFIG_USER_ONLY 474 475 static inline bool arm_excp_unmasked(CPUState *cs, unsigned int excp_idx, 476 unsigned int target_el, 477 unsigned int cur_el, bool secure, 478 uint64_t hcr_el2) 479 { 480 CPUARMState *env = cs->env_ptr; 481 bool pstate_unmasked; 482 bool unmasked = false; 483 484 /* 485 * Don't take exceptions if they target a lower EL. 486 * This check should catch any exceptions that would not be taken 487 * but left pending. 488 */ 489 if (cur_el > target_el) { 490 return false; 491 } 492 493 switch (excp_idx) { 494 case EXCP_FIQ: 495 pstate_unmasked = !(env->daif & PSTATE_F); 496 break; 497 498 case EXCP_IRQ: 499 pstate_unmasked = !(env->daif & PSTATE_I); 500 break; 501 502 case EXCP_VFIQ: 503 if (!(hcr_el2 & HCR_FMO) || (hcr_el2 & HCR_TGE)) { 504 /* VFIQs are only taken when hypervized. */ 505 return false; 506 } 507 return !(env->daif & PSTATE_F); 508 case EXCP_VIRQ: 509 if (!(hcr_el2 & HCR_IMO) || (hcr_el2 & HCR_TGE)) { 510 /* VIRQs are only taken when hypervized. */ 511 return false; 512 } 513 return !(env->daif & PSTATE_I); 514 case EXCP_VSERR: 515 if (!(hcr_el2 & HCR_AMO) || (hcr_el2 & HCR_TGE)) { 516 /* VIRQs are only taken when hypervized. */ 517 return false; 518 } 519 return !(env->daif & PSTATE_A); 520 default: 521 g_assert_not_reached(); 522 } 523 524 /* 525 * Use the target EL, current execution state and SCR/HCR settings to 526 * determine whether the corresponding CPSR bit is used to mask the 527 * interrupt. 528 */ 529 if ((target_el > cur_el) && (target_el != 1)) { 530 /* Exceptions targeting a higher EL may not be maskable */ 531 if (arm_feature(env, ARM_FEATURE_AARCH64)) { 532 /* 533 * 64-bit masking rules are simple: exceptions to EL3 534 * can't be masked, and exceptions to EL2 can only be 535 * masked from Secure state. The HCR and SCR settings 536 * don't affect the masking logic, only the interrupt routing. 537 */ 538 if (target_el == 3 || !secure || (env->cp15.scr_el3 & SCR_EEL2)) { 539 unmasked = true; 540 } 541 } else { 542 /* 543 * The old 32-bit-only environment has a more complicated 544 * masking setup. HCR and SCR bits not only affect interrupt 545 * routing but also change the behaviour of masking. 546 */ 547 bool hcr, scr; 548 549 switch (excp_idx) { 550 case EXCP_FIQ: 551 /* 552 * If FIQs are routed to EL3 or EL2 then there are cases where 553 * we override the CPSR.F in determining if the exception is 554 * masked or not. If neither of these are set then we fall back 555 * to the CPSR.F setting otherwise we further assess the state 556 * below. 557 */ 558 hcr = hcr_el2 & HCR_FMO; 559 scr = (env->cp15.scr_el3 & SCR_FIQ); 560 561 /* 562 * When EL3 is 32-bit, the SCR.FW bit controls whether the 563 * CPSR.F bit masks FIQ interrupts when taken in non-secure 564 * state. If SCR.FW is set then FIQs can be masked by CPSR.F 565 * when non-secure but only when FIQs are only routed to EL3. 566 */ 567 scr = scr && !((env->cp15.scr_el3 & SCR_FW) && !hcr); 568 break; 569 case EXCP_IRQ: 570 /* 571 * When EL3 execution state is 32-bit, if HCR.IMO is set then 572 * we may override the CPSR.I masking when in non-secure state. 573 * The SCR.IRQ setting has already been taken into consideration 574 * when setting the target EL, so it does not have a further 575 * affect here. 576 */ 577 hcr = hcr_el2 & HCR_IMO; 578 scr = false; 579 break; 580 default: 581 g_assert_not_reached(); 582 } 583 584 if ((scr || hcr) && !secure) { 585 unmasked = true; 586 } 587 } 588 } 589 590 /* 591 * The PSTATE bits only mask the interrupt if we have not overriden the 592 * ability above. 593 */ 594 return unmasked || pstate_unmasked; 595 } 596 597 static bool arm_cpu_exec_interrupt(CPUState *cs, int interrupt_request) 598 { 599 CPUClass *cc = CPU_GET_CLASS(cs); 600 CPUARMState *env = cs->env_ptr; 601 uint32_t cur_el = arm_current_el(env); 602 bool secure = arm_is_secure(env); 603 uint64_t hcr_el2 = arm_hcr_el2_eff(env); 604 uint32_t target_el; 605 uint32_t excp_idx; 606 607 /* The prioritization of interrupts is IMPLEMENTATION DEFINED. */ 608 609 if (interrupt_request & CPU_INTERRUPT_FIQ) { 610 excp_idx = EXCP_FIQ; 611 target_el = arm_phys_excp_target_el(cs, excp_idx, cur_el, secure); 612 if (arm_excp_unmasked(cs, excp_idx, target_el, 613 cur_el, secure, hcr_el2)) { 614 goto found; 615 } 616 } 617 if (interrupt_request & CPU_INTERRUPT_HARD) { 618 excp_idx = EXCP_IRQ; 619 target_el = arm_phys_excp_target_el(cs, excp_idx, cur_el, secure); 620 if (arm_excp_unmasked(cs, excp_idx, target_el, 621 cur_el, secure, hcr_el2)) { 622 goto found; 623 } 624 } 625 if (interrupt_request & CPU_INTERRUPT_VIRQ) { 626 excp_idx = EXCP_VIRQ; 627 target_el = 1; 628 if (arm_excp_unmasked(cs, excp_idx, target_el, 629 cur_el, secure, hcr_el2)) { 630 goto found; 631 } 632 } 633 if (interrupt_request & CPU_INTERRUPT_VFIQ) { 634 excp_idx = EXCP_VFIQ; 635 target_el = 1; 636 if (arm_excp_unmasked(cs, excp_idx, target_el, 637 cur_el, secure, hcr_el2)) { 638 goto found; 639 } 640 } 641 if (interrupt_request & CPU_INTERRUPT_VSERR) { 642 excp_idx = EXCP_VSERR; 643 target_el = 1; 644 if (arm_excp_unmasked(cs, excp_idx, target_el, 645 cur_el, secure, hcr_el2)) { 646 /* Taking a virtual abort clears HCR_EL2.VSE */ 647 env->cp15.hcr_el2 &= ~HCR_VSE; 648 cpu_reset_interrupt(cs, CPU_INTERRUPT_VSERR); 649 goto found; 650 } 651 } 652 return false; 653 654 found: 655 cs->exception_index = excp_idx; 656 env->exception.target_el = target_el; 657 cc->tcg_ops->do_interrupt(cs); 658 return true; 659 } 660 #endif /* !CONFIG_USER_ONLY */ 661 662 void arm_cpu_update_virq(ARMCPU *cpu) 663 { 664 /* 665 * Update the interrupt level for VIRQ, which is the logical OR of 666 * the HCR_EL2.VI bit and the input line level from the GIC. 667 */ 668 CPUARMState *env = &cpu->env; 669 CPUState *cs = CPU(cpu); 670 671 bool new_state = (env->cp15.hcr_el2 & HCR_VI) || 672 (env->irq_line_state & CPU_INTERRUPT_VIRQ); 673 674 if (new_state != ((cs->interrupt_request & CPU_INTERRUPT_VIRQ) != 0)) { 675 if (new_state) { 676 cpu_interrupt(cs, CPU_INTERRUPT_VIRQ); 677 } else { 678 cpu_reset_interrupt(cs, CPU_INTERRUPT_VIRQ); 679 } 680 } 681 } 682 683 void arm_cpu_update_vfiq(ARMCPU *cpu) 684 { 685 /* 686 * Update the interrupt level for VFIQ, which is the logical OR of 687 * the HCR_EL2.VF bit and the input line level from the GIC. 688 */ 689 CPUARMState *env = &cpu->env; 690 CPUState *cs = CPU(cpu); 691 692 bool new_state = (env->cp15.hcr_el2 & HCR_VF) || 693 (env->irq_line_state & CPU_INTERRUPT_VFIQ); 694 695 if (new_state != ((cs->interrupt_request & CPU_INTERRUPT_VFIQ) != 0)) { 696 if (new_state) { 697 cpu_interrupt(cs, CPU_INTERRUPT_VFIQ); 698 } else { 699 cpu_reset_interrupt(cs, CPU_INTERRUPT_VFIQ); 700 } 701 } 702 } 703 704 void arm_cpu_update_vserr(ARMCPU *cpu) 705 { 706 /* 707 * Update the interrupt level for VSERR, which is the HCR_EL2.VSE bit. 708 */ 709 CPUARMState *env = &cpu->env; 710 CPUState *cs = CPU(cpu); 711 712 bool new_state = env->cp15.hcr_el2 & HCR_VSE; 713 714 if (new_state != ((cs->interrupt_request & CPU_INTERRUPT_VSERR) != 0)) { 715 if (new_state) { 716 cpu_interrupt(cs, CPU_INTERRUPT_VSERR); 717 } else { 718 cpu_reset_interrupt(cs, CPU_INTERRUPT_VSERR); 719 } 720 } 721 } 722 723 #ifndef CONFIG_USER_ONLY 724 static void arm_cpu_set_irq(void *opaque, int irq, int level) 725 { 726 ARMCPU *cpu = opaque; 727 CPUARMState *env = &cpu->env; 728 CPUState *cs = CPU(cpu); 729 static const int mask[] = { 730 [ARM_CPU_IRQ] = CPU_INTERRUPT_HARD, 731 [ARM_CPU_FIQ] = CPU_INTERRUPT_FIQ, 732 [ARM_CPU_VIRQ] = CPU_INTERRUPT_VIRQ, 733 [ARM_CPU_VFIQ] = CPU_INTERRUPT_VFIQ 734 }; 735 736 if (!arm_feature(env, ARM_FEATURE_EL2) && 737 (irq == ARM_CPU_VIRQ || irq == ARM_CPU_VFIQ)) { 738 /* 739 * The GIC might tell us about VIRQ and VFIQ state, but if we don't 740 * have EL2 support we don't care. (Unless the guest is doing something 741 * silly this will only be calls saying "level is still 0".) 742 */ 743 return; 744 } 745 746 if (level) { 747 env->irq_line_state |= mask[irq]; 748 } else { 749 env->irq_line_state &= ~mask[irq]; 750 } 751 752 switch (irq) { 753 case ARM_CPU_VIRQ: 754 arm_cpu_update_virq(cpu); 755 break; 756 case ARM_CPU_VFIQ: 757 arm_cpu_update_vfiq(cpu); 758 break; 759 case ARM_CPU_IRQ: 760 case ARM_CPU_FIQ: 761 if (level) { 762 cpu_interrupt(cs, mask[irq]); 763 } else { 764 cpu_reset_interrupt(cs, mask[irq]); 765 } 766 break; 767 default: 768 g_assert_not_reached(); 769 } 770 } 771 772 static void arm_cpu_kvm_set_irq(void *opaque, int irq, int level) 773 { 774 #ifdef CONFIG_KVM 775 ARMCPU *cpu = opaque; 776 CPUARMState *env = &cpu->env; 777 CPUState *cs = CPU(cpu); 778 uint32_t linestate_bit; 779 int irq_id; 780 781 switch (irq) { 782 case ARM_CPU_IRQ: 783 irq_id = KVM_ARM_IRQ_CPU_IRQ; 784 linestate_bit = CPU_INTERRUPT_HARD; 785 break; 786 case ARM_CPU_FIQ: 787 irq_id = KVM_ARM_IRQ_CPU_FIQ; 788 linestate_bit = CPU_INTERRUPT_FIQ; 789 break; 790 default: 791 g_assert_not_reached(); 792 } 793 794 if (level) { 795 env->irq_line_state |= linestate_bit; 796 } else { 797 env->irq_line_state &= ~linestate_bit; 798 } 799 kvm_arm_set_irq(cs->cpu_index, KVM_ARM_IRQ_TYPE_CPU, irq_id, !!level); 800 #endif 801 } 802 803 static bool arm_cpu_virtio_is_big_endian(CPUState *cs) 804 { 805 ARMCPU *cpu = ARM_CPU(cs); 806 CPUARMState *env = &cpu->env; 807 808 cpu_synchronize_state(cs); 809 return arm_cpu_data_is_big_endian(env); 810 } 811 812 #endif 813 814 static int 815 print_insn_thumb1(bfd_vma pc, disassemble_info *info) 816 { 817 return print_insn_arm(pc | 1, info); 818 } 819 820 static void arm_disas_set_info(CPUState *cpu, disassemble_info *info) 821 { 822 ARMCPU *ac = ARM_CPU(cpu); 823 CPUARMState *env = &ac->env; 824 bool sctlr_b; 825 826 if (is_a64(env)) { 827 /* We might not be compiled with the A64 disassembler 828 * because it needs a C++ compiler. Leave print_insn 829 * unset in this case to use the caller default behaviour. 830 */ 831 #if defined(CONFIG_ARM_A64_DIS) 832 info->print_insn = print_insn_arm_a64; 833 #endif 834 info->cap_arch = CS_ARCH_ARM64; 835 info->cap_insn_unit = 4; 836 info->cap_insn_split = 4; 837 } else { 838 int cap_mode; 839 if (env->thumb) { 840 info->print_insn = print_insn_thumb1; 841 info->cap_insn_unit = 2; 842 info->cap_insn_split = 4; 843 cap_mode = CS_MODE_THUMB; 844 } else { 845 info->print_insn = print_insn_arm; 846 info->cap_insn_unit = 4; 847 info->cap_insn_split = 4; 848 cap_mode = CS_MODE_ARM; 849 } 850 if (arm_feature(env, ARM_FEATURE_V8)) { 851 cap_mode |= CS_MODE_V8; 852 } 853 if (arm_feature(env, ARM_FEATURE_M)) { 854 cap_mode |= CS_MODE_MCLASS; 855 } 856 info->cap_arch = CS_ARCH_ARM; 857 info->cap_mode = cap_mode; 858 } 859 860 sctlr_b = arm_sctlr_b(env); 861 if (bswap_code(sctlr_b)) { 862 #if TARGET_BIG_ENDIAN 863 info->endian = BFD_ENDIAN_LITTLE; 864 #else 865 info->endian = BFD_ENDIAN_BIG; 866 #endif 867 } 868 info->flags &= ~INSN_ARM_BE32; 869 #ifndef CONFIG_USER_ONLY 870 if (sctlr_b) { 871 info->flags |= INSN_ARM_BE32; 872 } 873 #endif 874 } 875 876 #ifdef TARGET_AARCH64 877 878 static void aarch64_cpu_dump_state(CPUState *cs, FILE *f, int flags) 879 { 880 ARMCPU *cpu = ARM_CPU(cs); 881 CPUARMState *env = &cpu->env; 882 uint32_t psr = pstate_read(env); 883 int i; 884 int el = arm_current_el(env); 885 const char *ns_status; 886 887 qemu_fprintf(f, " PC=%016" PRIx64 " ", env->pc); 888 for (i = 0; i < 32; i++) { 889 if (i == 31) { 890 qemu_fprintf(f, " SP=%016" PRIx64 "\n", env->xregs[i]); 891 } else { 892 qemu_fprintf(f, "X%02d=%016" PRIx64 "%s", i, env->xregs[i], 893 (i + 2) % 3 ? " " : "\n"); 894 } 895 } 896 897 if (arm_feature(env, ARM_FEATURE_EL3) && el != 3) { 898 ns_status = env->cp15.scr_el3 & SCR_NS ? "NS " : "S "; 899 } else { 900 ns_status = ""; 901 } 902 qemu_fprintf(f, "PSTATE=%08x %c%c%c%c %sEL%d%c", 903 psr, 904 psr & PSTATE_N ? 'N' : '-', 905 psr & PSTATE_Z ? 'Z' : '-', 906 psr & PSTATE_C ? 'C' : '-', 907 psr & PSTATE_V ? 'V' : '-', 908 ns_status, 909 el, 910 psr & PSTATE_SP ? 'h' : 't'); 911 912 if (cpu_isar_feature(aa64_bti, cpu)) { 913 qemu_fprintf(f, " BTYPE=%d", (psr & PSTATE_BTYPE) >> 10); 914 } 915 if (!(flags & CPU_DUMP_FPU)) { 916 qemu_fprintf(f, "\n"); 917 return; 918 } 919 if (fp_exception_el(env, el) != 0) { 920 qemu_fprintf(f, " FPU disabled\n"); 921 return; 922 } 923 qemu_fprintf(f, " FPCR=%08x FPSR=%08x\n", 924 vfp_get_fpcr(env), vfp_get_fpsr(env)); 925 926 if (cpu_isar_feature(aa64_sve, cpu) && sve_exception_el(env, el) == 0) { 927 int j, zcr_len = sve_zcr_len_for_el(env, el); 928 929 for (i = 0; i <= FFR_PRED_NUM; i++) { 930 bool eol; 931 if (i == FFR_PRED_NUM) { 932 qemu_fprintf(f, "FFR="); 933 /* It's last, so end the line. */ 934 eol = true; 935 } else { 936 qemu_fprintf(f, "P%02d=", i); 937 switch (zcr_len) { 938 case 0: 939 eol = i % 8 == 7; 940 break; 941 case 1: 942 eol = i % 6 == 5; 943 break; 944 case 2: 945 case 3: 946 eol = i % 3 == 2; 947 break; 948 default: 949 /* More than one quadword per predicate. */ 950 eol = true; 951 break; 952 } 953 } 954 for (j = zcr_len / 4; j >= 0; j--) { 955 int digits; 956 if (j * 4 + 4 <= zcr_len + 1) { 957 digits = 16; 958 } else { 959 digits = (zcr_len % 4 + 1) * 4; 960 } 961 qemu_fprintf(f, "%0*" PRIx64 "%s", digits, 962 env->vfp.pregs[i].p[j], 963 j ? ":" : eol ? "\n" : " "); 964 } 965 } 966 967 for (i = 0; i < 32; i++) { 968 if (zcr_len == 0) { 969 qemu_fprintf(f, "Z%02d=%016" PRIx64 ":%016" PRIx64 "%s", 970 i, env->vfp.zregs[i].d[1], 971 env->vfp.zregs[i].d[0], i & 1 ? "\n" : " "); 972 } else if (zcr_len == 1) { 973 qemu_fprintf(f, "Z%02d=%016" PRIx64 ":%016" PRIx64 974 ":%016" PRIx64 ":%016" PRIx64 "\n", 975 i, env->vfp.zregs[i].d[3], env->vfp.zregs[i].d[2], 976 env->vfp.zregs[i].d[1], env->vfp.zregs[i].d[0]); 977 } else { 978 for (j = zcr_len; j >= 0; j--) { 979 bool odd = (zcr_len - j) % 2 != 0; 980 if (j == zcr_len) { 981 qemu_fprintf(f, "Z%02d[%x-%x]=", i, j, j - 1); 982 } else if (!odd) { 983 if (j > 0) { 984 qemu_fprintf(f, " [%x-%x]=", j, j - 1); 985 } else { 986 qemu_fprintf(f, " [%x]=", j); 987 } 988 } 989 qemu_fprintf(f, "%016" PRIx64 ":%016" PRIx64 "%s", 990 env->vfp.zregs[i].d[j * 2 + 1], 991 env->vfp.zregs[i].d[j * 2], 992 odd || j == 0 ? "\n" : ":"); 993 } 994 } 995 } 996 } else { 997 for (i = 0; i < 32; i++) { 998 uint64_t *q = aa64_vfp_qreg(env, i); 999 qemu_fprintf(f, "Q%02d=%016" PRIx64 ":%016" PRIx64 "%s", 1000 i, q[1], q[0], (i & 1 ? "\n" : " ")); 1001 } 1002 } 1003 } 1004 1005 #else 1006 1007 static inline void aarch64_cpu_dump_state(CPUState *cs, FILE *f, int flags) 1008 { 1009 g_assert_not_reached(); 1010 } 1011 1012 #endif 1013 1014 static void arm_cpu_dump_state(CPUState *cs, FILE *f, int flags) 1015 { 1016 ARMCPU *cpu = ARM_CPU(cs); 1017 CPUARMState *env = &cpu->env; 1018 int i; 1019 1020 if (is_a64(env)) { 1021 aarch64_cpu_dump_state(cs, f, flags); 1022 return; 1023 } 1024 1025 for (i = 0; i < 16; i++) { 1026 qemu_fprintf(f, "R%02d=%08x", i, env->regs[i]); 1027 if ((i % 4) == 3) { 1028 qemu_fprintf(f, "\n"); 1029 } else { 1030 qemu_fprintf(f, " "); 1031 } 1032 } 1033 1034 if (arm_feature(env, ARM_FEATURE_M)) { 1035 uint32_t xpsr = xpsr_read(env); 1036 const char *mode; 1037 const char *ns_status = ""; 1038 1039 if (arm_feature(env, ARM_FEATURE_M_SECURITY)) { 1040 ns_status = env->v7m.secure ? "S " : "NS "; 1041 } 1042 1043 if (xpsr & XPSR_EXCP) { 1044 mode = "handler"; 1045 } else { 1046 if (env->v7m.control[env->v7m.secure] & R_V7M_CONTROL_NPRIV_MASK) { 1047 mode = "unpriv-thread"; 1048 } else { 1049 mode = "priv-thread"; 1050 } 1051 } 1052 1053 qemu_fprintf(f, "XPSR=%08x %c%c%c%c %c %s%s\n", 1054 xpsr, 1055 xpsr & XPSR_N ? 'N' : '-', 1056 xpsr & XPSR_Z ? 'Z' : '-', 1057 xpsr & XPSR_C ? 'C' : '-', 1058 xpsr & XPSR_V ? 'V' : '-', 1059 xpsr & XPSR_T ? 'T' : 'A', 1060 ns_status, 1061 mode); 1062 } else { 1063 uint32_t psr = cpsr_read(env); 1064 const char *ns_status = ""; 1065 1066 if (arm_feature(env, ARM_FEATURE_EL3) && 1067 (psr & CPSR_M) != ARM_CPU_MODE_MON) { 1068 ns_status = env->cp15.scr_el3 & SCR_NS ? "NS " : "S "; 1069 } 1070 1071 qemu_fprintf(f, "PSR=%08x %c%c%c%c %c %s%s%d\n", 1072 psr, 1073 psr & CPSR_N ? 'N' : '-', 1074 psr & CPSR_Z ? 'Z' : '-', 1075 psr & CPSR_C ? 'C' : '-', 1076 psr & CPSR_V ? 'V' : '-', 1077 psr & CPSR_T ? 'T' : 'A', 1078 ns_status, 1079 aarch32_mode_name(psr), (psr & 0x10) ? 32 : 26); 1080 } 1081 1082 if (flags & CPU_DUMP_FPU) { 1083 int numvfpregs = 0; 1084 if (cpu_isar_feature(aa32_simd_r32, cpu)) { 1085 numvfpregs = 32; 1086 } else if (cpu_isar_feature(aa32_vfp_simd, cpu)) { 1087 numvfpregs = 16; 1088 } 1089 for (i = 0; i < numvfpregs; i++) { 1090 uint64_t v = *aa32_vfp_dreg(env, i); 1091 qemu_fprintf(f, "s%02d=%08x s%02d=%08x d%02d=%016" PRIx64 "\n", 1092 i * 2, (uint32_t)v, 1093 i * 2 + 1, (uint32_t)(v >> 32), 1094 i, v); 1095 } 1096 qemu_fprintf(f, "FPSCR: %08x\n", vfp_get_fpscr(env)); 1097 if (cpu_isar_feature(aa32_mve, cpu)) { 1098 qemu_fprintf(f, "VPR: %08x\n", env->v7m.vpr); 1099 } 1100 } 1101 } 1102 1103 uint64_t arm_cpu_mp_affinity(int idx, uint8_t clustersz) 1104 { 1105 uint32_t Aff1 = idx / clustersz; 1106 uint32_t Aff0 = idx % clustersz; 1107 return (Aff1 << ARM_AFF1_SHIFT) | Aff0; 1108 } 1109 1110 static void arm_cpu_initfn(Object *obj) 1111 { 1112 ARMCPU *cpu = ARM_CPU(obj); 1113 1114 cpu_set_cpustate_pointers(cpu); 1115 cpu->cp_regs = g_hash_table_new_full(g_direct_hash, g_direct_equal, 1116 NULL, g_free); 1117 1118 QLIST_INIT(&cpu->pre_el_change_hooks); 1119 QLIST_INIT(&cpu->el_change_hooks); 1120 1121 #ifdef CONFIG_USER_ONLY 1122 # ifdef TARGET_AARCH64 1123 /* 1124 * The linux kernel defaults to 512-bit vectors, when sve is supported. 1125 * See documentation for /proc/sys/abi/sve_default_vector_length, and 1126 * our corresponding sve-default-vector-length cpu property. 1127 */ 1128 cpu->sve_default_vq = 4; 1129 # endif 1130 #else 1131 /* Our inbound IRQ and FIQ lines */ 1132 if (kvm_enabled()) { 1133 /* VIRQ and VFIQ are unused with KVM but we add them to maintain 1134 * the same interface as non-KVM CPUs. 1135 */ 1136 qdev_init_gpio_in(DEVICE(cpu), arm_cpu_kvm_set_irq, 4); 1137 } else { 1138 qdev_init_gpio_in(DEVICE(cpu), arm_cpu_set_irq, 4); 1139 } 1140 1141 qdev_init_gpio_out(DEVICE(cpu), cpu->gt_timer_outputs, 1142 ARRAY_SIZE(cpu->gt_timer_outputs)); 1143 1144 qdev_init_gpio_out_named(DEVICE(cpu), &cpu->gicv3_maintenance_interrupt, 1145 "gicv3-maintenance-interrupt", 1); 1146 qdev_init_gpio_out_named(DEVICE(cpu), &cpu->pmu_interrupt, 1147 "pmu-interrupt", 1); 1148 #endif 1149 1150 /* DTB consumers generally don't in fact care what the 'compatible' 1151 * string is, so always provide some string and trust that a hypothetical 1152 * picky DTB consumer will also provide a helpful error message. 1153 */ 1154 cpu->dtb_compatible = "qemu,unknown"; 1155 cpu->psci_version = QEMU_PSCI_VERSION_0_1; /* By default assume PSCI v0.1 */ 1156 cpu->kvm_target = QEMU_KVM_ARM_TARGET_NONE; 1157 1158 if (tcg_enabled() || hvf_enabled()) { 1159 /* TCG and HVF implement PSCI 1.1 */ 1160 cpu->psci_version = QEMU_PSCI_VERSION_1_1; 1161 } 1162 } 1163 1164 static Property arm_cpu_gt_cntfrq_property = 1165 DEFINE_PROP_UINT64("cntfrq", ARMCPU, gt_cntfrq_hz, 1166 NANOSECONDS_PER_SECOND / GTIMER_SCALE); 1167 1168 static Property arm_cpu_reset_cbar_property = 1169 DEFINE_PROP_UINT64("reset-cbar", ARMCPU, reset_cbar, 0); 1170 1171 static Property arm_cpu_reset_hivecs_property = 1172 DEFINE_PROP_BOOL("reset-hivecs", ARMCPU, reset_hivecs, false); 1173 1174 #ifndef CONFIG_USER_ONLY 1175 static Property arm_cpu_has_el2_property = 1176 DEFINE_PROP_BOOL("has_el2", ARMCPU, has_el2, true); 1177 1178 static Property arm_cpu_has_el3_property = 1179 DEFINE_PROP_BOOL("has_el3", ARMCPU, has_el3, true); 1180 #endif 1181 1182 static Property arm_cpu_cfgend_property = 1183 DEFINE_PROP_BOOL("cfgend", ARMCPU, cfgend, false); 1184 1185 static Property arm_cpu_has_vfp_property = 1186 DEFINE_PROP_BOOL("vfp", ARMCPU, has_vfp, true); 1187 1188 static Property arm_cpu_has_neon_property = 1189 DEFINE_PROP_BOOL("neon", ARMCPU, has_neon, true); 1190 1191 static Property arm_cpu_has_dsp_property = 1192 DEFINE_PROP_BOOL("dsp", ARMCPU, has_dsp, true); 1193 1194 static Property arm_cpu_has_mpu_property = 1195 DEFINE_PROP_BOOL("has-mpu", ARMCPU, has_mpu, true); 1196 1197 /* This is like DEFINE_PROP_UINT32 but it doesn't set the default value, 1198 * because the CPU initfn will have already set cpu->pmsav7_dregion to 1199 * the right value for that particular CPU type, and we don't want 1200 * to override that with an incorrect constant value. 1201 */ 1202 static Property arm_cpu_pmsav7_dregion_property = 1203 DEFINE_PROP_UNSIGNED_NODEFAULT("pmsav7-dregion", ARMCPU, 1204 pmsav7_dregion, 1205 qdev_prop_uint32, uint32_t); 1206 1207 static bool arm_get_pmu(Object *obj, Error **errp) 1208 { 1209 ARMCPU *cpu = ARM_CPU(obj); 1210 1211 return cpu->has_pmu; 1212 } 1213 1214 static void arm_set_pmu(Object *obj, bool value, Error **errp) 1215 { 1216 ARMCPU *cpu = ARM_CPU(obj); 1217 1218 if (value) { 1219 if (kvm_enabled() && !kvm_arm_pmu_supported()) { 1220 error_setg(errp, "'pmu' feature not supported by KVM on this host"); 1221 return; 1222 } 1223 set_feature(&cpu->env, ARM_FEATURE_PMU); 1224 } else { 1225 unset_feature(&cpu->env, ARM_FEATURE_PMU); 1226 } 1227 cpu->has_pmu = value; 1228 } 1229 1230 unsigned int gt_cntfrq_period_ns(ARMCPU *cpu) 1231 { 1232 /* 1233 * The exact approach to calculating guest ticks is: 1234 * 1235 * muldiv64(qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL), cpu->gt_cntfrq_hz, 1236 * NANOSECONDS_PER_SECOND); 1237 * 1238 * We don't do that. Rather we intentionally use integer division 1239 * truncation below and in the caller for the conversion of host monotonic 1240 * time to guest ticks to provide the exact inverse for the semantics of 1241 * the QEMUTimer scale factor. QEMUTimer's scale facter is an integer, so 1242 * it loses precision when representing frequencies where 1243 * `(NANOSECONDS_PER_SECOND % cpu->gt_cntfrq) > 0` holds. Failing to 1244 * provide an exact inverse leads to scheduling timers with negative 1245 * periods, which in turn leads to sticky behaviour in the guest. 1246 * 1247 * Finally, CNTFRQ is effectively capped at 1GHz to ensure our scale factor 1248 * cannot become zero. 1249 */ 1250 return NANOSECONDS_PER_SECOND > cpu->gt_cntfrq_hz ? 1251 NANOSECONDS_PER_SECOND / cpu->gt_cntfrq_hz : 1; 1252 } 1253 1254 void arm_cpu_post_init(Object *obj) 1255 { 1256 ARMCPU *cpu = ARM_CPU(obj); 1257 1258 /* M profile implies PMSA. We have to do this here rather than 1259 * in realize with the other feature-implication checks because 1260 * we look at the PMSA bit to see if we should add some properties. 1261 */ 1262 if (arm_feature(&cpu->env, ARM_FEATURE_M)) { 1263 set_feature(&cpu->env, ARM_FEATURE_PMSA); 1264 } 1265 1266 if (arm_feature(&cpu->env, ARM_FEATURE_CBAR) || 1267 arm_feature(&cpu->env, ARM_FEATURE_CBAR_RO)) { 1268 qdev_property_add_static(DEVICE(obj), &arm_cpu_reset_cbar_property); 1269 } 1270 1271 if (!arm_feature(&cpu->env, ARM_FEATURE_M)) { 1272 qdev_property_add_static(DEVICE(obj), &arm_cpu_reset_hivecs_property); 1273 } 1274 1275 if (arm_feature(&cpu->env, ARM_FEATURE_AARCH64)) { 1276 object_property_add_uint64_ptr(obj, "rvbar", 1277 &cpu->rvbar_prop, 1278 OBJ_PROP_FLAG_READWRITE); 1279 } 1280 1281 #ifndef CONFIG_USER_ONLY 1282 if (arm_feature(&cpu->env, ARM_FEATURE_EL3)) { 1283 /* Add the has_el3 state CPU property only if EL3 is allowed. This will 1284 * prevent "has_el3" from existing on CPUs which cannot support EL3. 1285 */ 1286 qdev_property_add_static(DEVICE(obj), &arm_cpu_has_el3_property); 1287 1288 object_property_add_link(obj, "secure-memory", 1289 TYPE_MEMORY_REGION, 1290 (Object **)&cpu->secure_memory, 1291 qdev_prop_allow_set_link_before_realize, 1292 OBJ_PROP_LINK_STRONG); 1293 } 1294 1295 if (arm_feature(&cpu->env, ARM_FEATURE_EL2)) { 1296 qdev_property_add_static(DEVICE(obj), &arm_cpu_has_el2_property); 1297 } 1298 #endif 1299 1300 if (arm_feature(&cpu->env, ARM_FEATURE_PMU)) { 1301 cpu->has_pmu = true; 1302 object_property_add_bool(obj, "pmu", arm_get_pmu, arm_set_pmu); 1303 } 1304 1305 /* 1306 * Allow user to turn off VFP and Neon support, but only for TCG -- 1307 * KVM does not currently allow us to lie to the guest about its 1308 * ID/feature registers, so the guest always sees what the host has. 1309 */ 1310 if (arm_feature(&cpu->env, ARM_FEATURE_AARCH64) 1311 ? cpu_isar_feature(aa64_fp_simd, cpu) 1312 : cpu_isar_feature(aa32_vfp, cpu)) { 1313 cpu->has_vfp = true; 1314 if (!kvm_enabled()) { 1315 qdev_property_add_static(DEVICE(obj), &arm_cpu_has_vfp_property); 1316 } 1317 } 1318 1319 if (arm_feature(&cpu->env, ARM_FEATURE_NEON)) { 1320 cpu->has_neon = true; 1321 if (!kvm_enabled()) { 1322 qdev_property_add_static(DEVICE(obj), &arm_cpu_has_neon_property); 1323 } 1324 } 1325 1326 if (arm_feature(&cpu->env, ARM_FEATURE_M) && 1327 arm_feature(&cpu->env, ARM_FEATURE_THUMB_DSP)) { 1328 qdev_property_add_static(DEVICE(obj), &arm_cpu_has_dsp_property); 1329 } 1330 1331 if (arm_feature(&cpu->env, ARM_FEATURE_PMSA)) { 1332 qdev_property_add_static(DEVICE(obj), &arm_cpu_has_mpu_property); 1333 if (arm_feature(&cpu->env, ARM_FEATURE_V7)) { 1334 qdev_property_add_static(DEVICE(obj), 1335 &arm_cpu_pmsav7_dregion_property); 1336 } 1337 } 1338 1339 if (arm_feature(&cpu->env, ARM_FEATURE_M_SECURITY)) { 1340 object_property_add_link(obj, "idau", TYPE_IDAU_INTERFACE, &cpu->idau, 1341 qdev_prop_allow_set_link_before_realize, 1342 OBJ_PROP_LINK_STRONG); 1343 /* 1344 * M profile: initial value of the Secure VTOR. We can't just use 1345 * a simple DEFINE_PROP_UINT32 for this because we want to permit 1346 * the property to be set after realize. 1347 */ 1348 object_property_add_uint32_ptr(obj, "init-svtor", 1349 &cpu->init_svtor, 1350 OBJ_PROP_FLAG_READWRITE); 1351 } 1352 if (arm_feature(&cpu->env, ARM_FEATURE_M)) { 1353 /* 1354 * Initial value of the NS VTOR (for cores without the Security 1355 * extension, this is the only VTOR) 1356 */ 1357 object_property_add_uint32_ptr(obj, "init-nsvtor", 1358 &cpu->init_nsvtor, 1359 OBJ_PROP_FLAG_READWRITE); 1360 } 1361 1362 /* Not DEFINE_PROP_UINT32: we want this to be settable after realize */ 1363 object_property_add_uint32_ptr(obj, "psci-conduit", 1364 &cpu->psci_conduit, 1365 OBJ_PROP_FLAG_READWRITE); 1366 1367 qdev_property_add_static(DEVICE(obj), &arm_cpu_cfgend_property); 1368 1369 if (arm_feature(&cpu->env, ARM_FEATURE_GENERIC_TIMER)) { 1370 qdev_property_add_static(DEVICE(cpu), &arm_cpu_gt_cntfrq_property); 1371 } 1372 1373 if (kvm_enabled()) { 1374 kvm_arm_add_vcpu_properties(obj); 1375 } 1376 1377 #ifndef CONFIG_USER_ONLY 1378 if (arm_feature(&cpu->env, ARM_FEATURE_AARCH64) && 1379 cpu_isar_feature(aa64_mte, cpu)) { 1380 object_property_add_link(obj, "tag-memory", 1381 TYPE_MEMORY_REGION, 1382 (Object **)&cpu->tag_memory, 1383 qdev_prop_allow_set_link_before_realize, 1384 OBJ_PROP_LINK_STRONG); 1385 1386 if (arm_feature(&cpu->env, ARM_FEATURE_EL3)) { 1387 object_property_add_link(obj, "secure-tag-memory", 1388 TYPE_MEMORY_REGION, 1389 (Object **)&cpu->secure_tag_memory, 1390 qdev_prop_allow_set_link_before_realize, 1391 OBJ_PROP_LINK_STRONG); 1392 } 1393 } 1394 #endif 1395 } 1396 1397 static void arm_cpu_finalizefn(Object *obj) 1398 { 1399 ARMCPU *cpu = ARM_CPU(obj); 1400 ARMELChangeHook *hook, *next; 1401 1402 g_hash_table_destroy(cpu->cp_regs); 1403 1404 QLIST_FOREACH_SAFE(hook, &cpu->pre_el_change_hooks, node, next) { 1405 QLIST_REMOVE(hook, node); 1406 g_free(hook); 1407 } 1408 QLIST_FOREACH_SAFE(hook, &cpu->el_change_hooks, node, next) { 1409 QLIST_REMOVE(hook, node); 1410 g_free(hook); 1411 } 1412 #ifndef CONFIG_USER_ONLY 1413 if (cpu->pmu_timer) { 1414 timer_free(cpu->pmu_timer); 1415 } 1416 #endif 1417 } 1418 1419 void arm_cpu_finalize_features(ARMCPU *cpu, Error **errp) 1420 { 1421 Error *local_err = NULL; 1422 1423 if (arm_feature(&cpu->env, ARM_FEATURE_AARCH64)) { 1424 arm_cpu_sve_finalize(cpu, &local_err); 1425 if (local_err != NULL) { 1426 error_propagate(errp, local_err); 1427 return; 1428 } 1429 1430 arm_cpu_pauth_finalize(cpu, &local_err); 1431 if (local_err != NULL) { 1432 error_propagate(errp, local_err); 1433 return; 1434 } 1435 1436 arm_cpu_lpa2_finalize(cpu, &local_err); 1437 if (local_err != NULL) { 1438 error_propagate(errp, local_err); 1439 return; 1440 } 1441 } 1442 1443 if (kvm_enabled()) { 1444 kvm_arm_steal_time_finalize(cpu, &local_err); 1445 if (local_err != NULL) { 1446 error_propagate(errp, local_err); 1447 return; 1448 } 1449 } 1450 } 1451 1452 static void arm_cpu_realizefn(DeviceState *dev, Error **errp) 1453 { 1454 CPUState *cs = CPU(dev); 1455 ARMCPU *cpu = ARM_CPU(dev); 1456 ARMCPUClass *acc = ARM_CPU_GET_CLASS(dev); 1457 CPUARMState *env = &cpu->env; 1458 int pagebits; 1459 Error *local_err = NULL; 1460 bool no_aa32 = false; 1461 1462 /* If we needed to query the host kernel for the CPU features 1463 * then it's possible that might have failed in the initfn, but 1464 * this is the first point where we can report it. 1465 */ 1466 if (cpu->host_cpu_probe_failed) { 1467 if (!kvm_enabled() && !hvf_enabled()) { 1468 error_setg(errp, "The 'host' CPU type can only be used with KVM or HVF"); 1469 } else { 1470 error_setg(errp, "Failed to retrieve host CPU features"); 1471 } 1472 return; 1473 } 1474 1475 #ifndef CONFIG_USER_ONLY 1476 /* The NVIC and M-profile CPU are two halves of a single piece of 1477 * hardware; trying to use one without the other is a command line 1478 * error and will result in segfaults if not caught here. 1479 */ 1480 if (arm_feature(env, ARM_FEATURE_M)) { 1481 if (!env->nvic) { 1482 error_setg(errp, "This board cannot be used with Cortex-M CPUs"); 1483 return; 1484 } 1485 } else { 1486 if (env->nvic) { 1487 error_setg(errp, "This board can only be used with Cortex-M CPUs"); 1488 return; 1489 } 1490 } 1491 1492 if (kvm_enabled()) { 1493 /* 1494 * Catch all the cases which might cause us to create more than one 1495 * address space for the CPU (otherwise we will assert() later in 1496 * cpu_address_space_init()). 1497 */ 1498 if (arm_feature(env, ARM_FEATURE_M)) { 1499 error_setg(errp, 1500 "Cannot enable KVM when using an M-profile guest CPU"); 1501 return; 1502 } 1503 if (cpu->has_el3) { 1504 error_setg(errp, 1505 "Cannot enable KVM when guest CPU has EL3 enabled"); 1506 return; 1507 } 1508 if (cpu->tag_memory) { 1509 error_setg(errp, 1510 "Cannot enable KVM when guest CPUs has MTE enabled"); 1511 return; 1512 } 1513 } 1514 1515 { 1516 uint64_t scale; 1517 1518 if (arm_feature(env, ARM_FEATURE_GENERIC_TIMER)) { 1519 if (!cpu->gt_cntfrq_hz) { 1520 error_setg(errp, "Invalid CNTFRQ: %"PRId64"Hz", 1521 cpu->gt_cntfrq_hz); 1522 return; 1523 } 1524 scale = gt_cntfrq_period_ns(cpu); 1525 } else { 1526 scale = GTIMER_SCALE; 1527 } 1528 1529 cpu->gt_timer[GTIMER_PHYS] = timer_new(QEMU_CLOCK_VIRTUAL, scale, 1530 arm_gt_ptimer_cb, cpu); 1531 cpu->gt_timer[GTIMER_VIRT] = timer_new(QEMU_CLOCK_VIRTUAL, scale, 1532 arm_gt_vtimer_cb, cpu); 1533 cpu->gt_timer[GTIMER_HYP] = timer_new(QEMU_CLOCK_VIRTUAL, scale, 1534 arm_gt_htimer_cb, cpu); 1535 cpu->gt_timer[GTIMER_SEC] = timer_new(QEMU_CLOCK_VIRTUAL, scale, 1536 arm_gt_stimer_cb, cpu); 1537 cpu->gt_timer[GTIMER_HYPVIRT] = timer_new(QEMU_CLOCK_VIRTUAL, scale, 1538 arm_gt_hvtimer_cb, cpu); 1539 } 1540 #endif 1541 1542 cpu_exec_realizefn(cs, &local_err); 1543 if (local_err != NULL) { 1544 error_propagate(errp, local_err); 1545 return; 1546 } 1547 1548 arm_cpu_finalize_features(cpu, &local_err); 1549 if (local_err != NULL) { 1550 error_propagate(errp, local_err); 1551 return; 1552 } 1553 1554 if (arm_feature(env, ARM_FEATURE_AARCH64) && 1555 cpu->has_vfp != cpu->has_neon) { 1556 /* 1557 * This is an architectural requirement for AArch64; AArch32 is 1558 * more flexible and permits VFP-no-Neon and Neon-no-VFP. 1559 */ 1560 error_setg(errp, 1561 "AArch64 CPUs must have both VFP and Neon or neither"); 1562 return; 1563 } 1564 1565 if (!cpu->has_vfp) { 1566 uint64_t t; 1567 uint32_t u; 1568 1569 t = cpu->isar.id_aa64isar1; 1570 t = FIELD_DP64(t, ID_AA64ISAR1, JSCVT, 0); 1571 cpu->isar.id_aa64isar1 = t; 1572 1573 t = cpu->isar.id_aa64pfr0; 1574 t = FIELD_DP64(t, ID_AA64PFR0, FP, 0xf); 1575 cpu->isar.id_aa64pfr0 = t; 1576 1577 u = cpu->isar.id_isar6; 1578 u = FIELD_DP32(u, ID_ISAR6, JSCVT, 0); 1579 u = FIELD_DP32(u, ID_ISAR6, BF16, 0); 1580 cpu->isar.id_isar6 = u; 1581 1582 u = cpu->isar.mvfr0; 1583 u = FIELD_DP32(u, MVFR0, FPSP, 0); 1584 u = FIELD_DP32(u, MVFR0, FPDP, 0); 1585 u = FIELD_DP32(u, MVFR0, FPDIVIDE, 0); 1586 u = FIELD_DP32(u, MVFR0, FPSQRT, 0); 1587 u = FIELD_DP32(u, MVFR0, FPROUND, 0); 1588 if (!arm_feature(env, ARM_FEATURE_M)) { 1589 u = FIELD_DP32(u, MVFR0, FPTRAP, 0); 1590 u = FIELD_DP32(u, MVFR0, FPSHVEC, 0); 1591 } 1592 cpu->isar.mvfr0 = u; 1593 1594 u = cpu->isar.mvfr1; 1595 u = FIELD_DP32(u, MVFR1, FPFTZ, 0); 1596 u = FIELD_DP32(u, MVFR1, FPDNAN, 0); 1597 u = FIELD_DP32(u, MVFR1, FPHP, 0); 1598 if (arm_feature(env, ARM_FEATURE_M)) { 1599 u = FIELD_DP32(u, MVFR1, FP16, 0); 1600 } 1601 cpu->isar.mvfr1 = u; 1602 1603 u = cpu->isar.mvfr2; 1604 u = FIELD_DP32(u, MVFR2, FPMISC, 0); 1605 cpu->isar.mvfr2 = u; 1606 } 1607 1608 if (!cpu->has_neon) { 1609 uint64_t t; 1610 uint32_t u; 1611 1612 unset_feature(env, ARM_FEATURE_NEON); 1613 1614 t = cpu->isar.id_aa64isar0; 1615 t = FIELD_DP64(t, ID_AA64ISAR0, AES, 0); 1616 t = FIELD_DP64(t, ID_AA64ISAR0, SHA1, 0); 1617 t = FIELD_DP64(t, ID_AA64ISAR0, SHA2, 0); 1618 t = FIELD_DP64(t, ID_AA64ISAR0, SHA3, 0); 1619 t = FIELD_DP64(t, ID_AA64ISAR0, SM3, 0); 1620 t = FIELD_DP64(t, ID_AA64ISAR0, SM4, 0); 1621 t = FIELD_DP64(t, ID_AA64ISAR0, DP, 0); 1622 cpu->isar.id_aa64isar0 = t; 1623 1624 t = cpu->isar.id_aa64isar1; 1625 t = FIELD_DP64(t, ID_AA64ISAR1, FCMA, 0); 1626 t = FIELD_DP64(t, ID_AA64ISAR1, BF16, 0); 1627 t = FIELD_DP64(t, ID_AA64ISAR1, I8MM, 0); 1628 cpu->isar.id_aa64isar1 = t; 1629 1630 t = cpu->isar.id_aa64pfr0; 1631 t = FIELD_DP64(t, ID_AA64PFR0, ADVSIMD, 0xf); 1632 cpu->isar.id_aa64pfr0 = t; 1633 1634 u = cpu->isar.id_isar5; 1635 u = FIELD_DP32(u, ID_ISAR5, AES, 0); 1636 u = FIELD_DP32(u, ID_ISAR5, SHA1, 0); 1637 u = FIELD_DP32(u, ID_ISAR5, SHA2, 0); 1638 u = FIELD_DP32(u, ID_ISAR5, RDM, 0); 1639 u = FIELD_DP32(u, ID_ISAR5, VCMA, 0); 1640 cpu->isar.id_isar5 = u; 1641 1642 u = cpu->isar.id_isar6; 1643 u = FIELD_DP32(u, ID_ISAR6, DP, 0); 1644 u = FIELD_DP32(u, ID_ISAR6, FHM, 0); 1645 u = FIELD_DP32(u, ID_ISAR6, BF16, 0); 1646 u = FIELD_DP32(u, ID_ISAR6, I8MM, 0); 1647 cpu->isar.id_isar6 = u; 1648 1649 if (!arm_feature(env, ARM_FEATURE_M)) { 1650 u = cpu->isar.mvfr1; 1651 u = FIELD_DP32(u, MVFR1, SIMDLS, 0); 1652 u = FIELD_DP32(u, MVFR1, SIMDINT, 0); 1653 u = FIELD_DP32(u, MVFR1, SIMDSP, 0); 1654 u = FIELD_DP32(u, MVFR1, SIMDHP, 0); 1655 cpu->isar.mvfr1 = u; 1656 1657 u = cpu->isar.mvfr2; 1658 u = FIELD_DP32(u, MVFR2, SIMDMISC, 0); 1659 cpu->isar.mvfr2 = u; 1660 } 1661 } 1662 1663 if (!cpu->has_neon && !cpu->has_vfp) { 1664 uint64_t t; 1665 uint32_t u; 1666 1667 t = cpu->isar.id_aa64isar0; 1668 t = FIELD_DP64(t, ID_AA64ISAR0, FHM, 0); 1669 cpu->isar.id_aa64isar0 = t; 1670 1671 t = cpu->isar.id_aa64isar1; 1672 t = FIELD_DP64(t, ID_AA64ISAR1, FRINTTS, 0); 1673 cpu->isar.id_aa64isar1 = t; 1674 1675 u = cpu->isar.mvfr0; 1676 u = FIELD_DP32(u, MVFR0, SIMDREG, 0); 1677 cpu->isar.mvfr0 = u; 1678 1679 /* Despite the name, this field covers both VFP and Neon */ 1680 u = cpu->isar.mvfr1; 1681 u = FIELD_DP32(u, MVFR1, SIMDFMAC, 0); 1682 cpu->isar.mvfr1 = u; 1683 } 1684 1685 if (arm_feature(env, ARM_FEATURE_M) && !cpu->has_dsp) { 1686 uint32_t u; 1687 1688 unset_feature(env, ARM_FEATURE_THUMB_DSP); 1689 1690 u = cpu->isar.id_isar1; 1691 u = FIELD_DP32(u, ID_ISAR1, EXTEND, 1); 1692 cpu->isar.id_isar1 = u; 1693 1694 u = cpu->isar.id_isar2; 1695 u = FIELD_DP32(u, ID_ISAR2, MULTU, 1); 1696 u = FIELD_DP32(u, ID_ISAR2, MULTS, 1); 1697 cpu->isar.id_isar2 = u; 1698 1699 u = cpu->isar.id_isar3; 1700 u = FIELD_DP32(u, ID_ISAR3, SIMD, 1); 1701 u = FIELD_DP32(u, ID_ISAR3, SATURATE, 0); 1702 cpu->isar.id_isar3 = u; 1703 } 1704 1705 /* Some features automatically imply others: */ 1706 if (arm_feature(env, ARM_FEATURE_V8)) { 1707 if (arm_feature(env, ARM_FEATURE_M)) { 1708 set_feature(env, ARM_FEATURE_V7); 1709 } else { 1710 set_feature(env, ARM_FEATURE_V7VE); 1711 } 1712 } 1713 1714 /* 1715 * There exist AArch64 cpus without AArch32 support. When KVM 1716 * queries ID_ISAR0_EL1 on such a host, the value is UNKNOWN. 1717 * Similarly, we cannot check ID_AA64PFR0 without AArch64 support. 1718 * As a general principle, we also do not make ID register 1719 * consistency checks anywhere unless using TCG, because only 1720 * for TCG would a consistency-check failure be a QEMU bug. 1721 */ 1722 if (arm_feature(&cpu->env, ARM_FEATURE_AARCH64)) { 1723 no_aa32 = !cpu_isar_feature(aa64_aa32, cpu); 1724 } 1725 1726 if (arm_feature(env, ARM_FEATURE_V7VE)) { 1727 /* v7 Virtualization Extensions. In real hardware this implies 1728 * EL2 and also the presence of the Security Extensions. 1729 * For QEMU, for backwards-compatibility we implement some 1730 * CPUs or CPU configs which have no actual EL2 or EL3 but do 1731 * include the various other features that V7VE implies. 1732 * Presence of EL2 itself is ARM_FEATURE_EL2, and of the 1733 * Security Extensions is ARM_FEATURE_EL3. 1734 */ 1735 assert(!tcg_enabled() || no_aa32 || 1736 cpu_isar_feature(aa32_arm_div, cpu)); 1737 set_feature(env, ARM_FEATURE_LPAE); 1738 set_feature(env, ARM_FEATURE_V7); 1739 } 1740 if (arm_feature(env, ARM_FEATURE_V7)) { 1741 set_feature(env, ARM_FEATURE_VAPA); 1742 set_feature(env, ARM_FEATURE_THUMB2); 1743 set_feature(env, ARM_FEATURE_MPIDR); 1744 if (!arm_feature(env, ARM_FEATURE_M)) { 1745 set_feature(env, ARM_FEATURE_V6K); 1746 } else { 1747 set_feature(env, ARM_FEATURE_V6); 1748 } 1749 1750 /* Always define VBAR for V7 CPUs even if it doesn't exist in 1751 * non-EL3 configs. This is needed by some legacy boards. 1752 */ 1753 set_feature(env, ARM_FEATURE_VBAR); 1754 } 1755 if (arm_feature(env, ARM_FEATURE_V6K)) { 1756 set_feature(env, ARM_FEATURE_V6); 1757 set_feature(env, ARM_FEATURE_MVFR); 1758 } 1759 if (arm_feature(env, ARM_FEATURE_V6)) { 1760 set_feature(env, ARM_FEATURE_V5); 1761 if (!arm_feature(env, ARM_FEATURE_M)) { 1762 assert(!tcg_enabled() || no_aa32 || 1763 cpu_isar_feature(aa32_jazelle, cpu)); 1764 set_feature(env, ARM_FEATURE_AUXCR); 1765 } 1766 } 1767 if (arm_feature(env, ARM_FEATURE_V5)) { 1768 set_feature(env, ARM_FEATURE_V4T); 1769 } 1770 if (arm_feature(env, ARM_FEATURE_LPAE)) { 1771 set_feature(env, ARM_FEATURE_V7MP); 1772 } 1773 if (arm_feature(env, ARM_FEATURE_CBAR_RO)) { 1774 set_feature(env, ARM_FEATURE_CBAR); 1775 } 1776 if (arm_feature(env, ARM_FEATURE_THUMB2) && 1777 !arm_feature(env, ARM_FEATURE_M)) { 1778 set_feature(env, ARM_FEATURE_THUMB_DSP); 1779 } 1780 1781 /* 1782 * We rely on no XScale CPU having VFP so we can use the same bits in the 1783 * TB flags field for VECSTRIDE and XSCALE_CPAR. 1784 */ 1785 assert(arm_feature(&cpu->env, ARM_FEATURE_AARCH64) || 1786 !cpu_isar_feature(aa32_vfp_simd, cpu) || 1787 !arm_feature(env, ARM_FEATURE_XSCALE)); 1788 1789 if (arm_feature(env, ARM_FEATURE_V7) && 1790 !arm_feature(env, ARM_FEATURE_M) && 1791 !arm_feature(env, ARM_FEATURE_PMSA)) { 1792 /* v7VMSA drops support for the old ARMv5 tiny pages, so we 1793 * can use 4K pages. 1794 */ 1795 pagebits = 12; 1796 } else { 1797 /* For CPUs which might have tiny 1K pages, or which have an 1798 * MPU and might have small region sizes, stick with 1K pages. 1799 */ 1800 pagebits = 10; 1801 } 1802 if (!set_preferred_target_page_bits(pagebits)) { 1803 /* This can only ever happen for hotplugging a CPU, or if 1804 * the board code incorrectly creates a CPU which it has 1805 * promised via minimum_page_size that it will not. 1806 */ 1807 error_setg(errp, "This CPU requires a smaller page size than the " 1808 "system is using"); 1809 return; 1810 } 1811 1812 /* This cpu-id-to-MPIDR affinity is used only for TCG; KVM will override it. 1813 * We don't support setting cluster ID ([16..23]) (known as Aff2 1814 * in later ARM ARM versions), or any of the higher affinity level fields, 1815 * so these bits always RAZ. 1816 */ 1817 if (cpu->mp_affinity == ARM64_AFFINITY_INVALID) { 1818 cpu->mp_affinity = arm_cpu_mp_affinity(cs->cpu_index, 1819 ARM_DEFAULT_CPUS_PER_CLUSTER); 1820 } 1821 1822 if (cpu->reset_hivecs) { 1823 cpu->reset_sctlr |= (1 << 13); 1824 } 1825 1826 if (cpu->cfgend) { 1827 if (arm_feature(&cpu->env, ARM_FEATURE_V7)) { 1828 cpu->reset_sctlr |= SCTLR_EE; 1829 } else { 1830 cpu->reset_sctlr |= SCTLR_B; 1831 } 1832 } 1833 1834 if (!arm_feature(env, ARM_FEATURE_M) && !cpu->has_el3) { 1835 /* If the has_el3 CPU property is disabled then we need to disable the 1836 * feature. 1837 */ 1838 unset_feature(env, ARM_FEATURE_EL3); 1839 1840 /* 1841 * Disable the security extension feature bits in the processor 1842 * feature registers as well. 1843 */ 1844 cpu->isar.id_pfr1 = FIELD_DP32(cpu->isar.id_pfr1, ID_PFR1, SECURITY, 0); 1845 cpu->isar.id_dfr0 = FIELD_DP32(cpu->isar.id_dfr0, ID_DFR0, COPSDBG, 0); 1846 cpu->isar.id_aa64pfr0 = FIELD_DP64(cpu->isar.id_aa64pfr0, 1847 ID_AA64PFR0, EL3, 0); 1848 } 1849 1850 if (!cpu->has_el2) { 1851 unset_feature(env, ARM_FEATURE_EL2); 1852 } 1853 1854 if (!cpu->has_pmu) { 1855 unset_feature(env, ARM_FEATURE_PMU); 1856 } 1857 if (arm_feature(env, ARM_FEATURE_PMU)) { 1858 pmu_init(cpu); 1859 1860 if (!kvm_enabled()) { 1861 arm_register_pre_el_change_hook(cpu, &pmu_pre_el_change, 0); 1862 arm_register_el_change_hook(cpu, &pmu_post_el_change, 0); 1863 } 1864 1865 #ifndef CONFIG_USER_ONLY 1866 cpu->pmu_timer = timer_new_ns(QEMU_CLOCK_VIRTUAL, arm_pmu_timer_cb, 1867 cpu); 1868 #endif 1869 } else { 1870 cpu->isar.id_aa64dfr0 = 1871 FIELD_DP64(cpu->isar.id_aa64dfr0, ID_AA64DFR0, PMUVER, 0); 1872 cpu->isar.id_dfr0 = FIELD_DP32(cpu->isar.id_dfr0, ID_DFR0, PERFMON, 0); 1873 cpu->pmceid0 = 0; 1874 cpu->pmceid1 = 0; 1875 } 1876 1877 if (!arm_feature(env, ARM_FEATURE_EL2)) { 1878 /* 1879 * Disable the hypervisor feature bits in the processor feature 1880 * registers if we don't have EL2. 1881 */ 1882 cpu->isar.id_aa64pfr0 = FIELD_DP64(cpu->isar.id_aa64pfr0, 1883 ID_AA64PFR0, EL2, 0); 1884 cpu->isar.id_pfr1 = FIELD_DP32(cpu->isar.id_pfr1, 1885 ID_PFR1, VIRTUALIZATION, 0); 1886 } 1887 1888 #ifndef CONFIG_USER_ONLY 1889 if (cpu->tag_memory == NULL && cpu_isar_feature(aa64_mte, cpu)) { 1890 /* 1891 * Disable the MTE feature bits if we do not have tag-memory 1892 * provided by the machine. 1893 */ 1894 cpu->isar.id_aa64pfr1 = 1895 FIELD_DP64(cpu->isar.id_aa64pfr1, ID_AA64PFR1, MTE, 0); 1896 } 1897 #endif 1898 1899 /* MPU can be configured out of a PMSA CPU either by setting has-mpu 1900 * to false or by setting pmsav7-dregion to 0. 1901 */ 1902 if (!cpu->has_mpu) { 1903 cpu->pmsav7_dregion = 0; 1904 } 1905 if (cpu->pmsav7_dregion == 0) { 1906 cpu->has_mpu = false; 1907 } 1908 1909 if (arm_feature(env, ARM_FEATURE_PMSA) && 1910 arm_feature(env, ARM_FEATURE_V7)) { 1911 uint32_t nr = cpu->pmsav7_dregion; 1912 1913 if (nr > 0xff) { 1914 error_setg(errp, "PMSAv7 MPU #regions invalid %" PRIu32, nr); 1915 return; 1916 } 1917 1918 if (nr) { 1919 if (arm_feature(env, ARM_FEATURE_V8)) { 1920 /* PMSAv8 */ 1921 env->pmsav8.rbar[M_REG_NS] = g_new0(uint32_t, nr); 1922 env->pmsav8.rlar[M_REG_NS] = g_new0(uint32_t, nr); 1923 if (arm_feature(env, ARM_FEATURE_M_SECURITY)) { 1924 env->pmsav8.rbar[M_REG_S] = g_new0(uint32_t, nr); 1925 env->pmsav8.rlar[M_REG_S] = g_new0(uint32_t, nr); 1926 } 1927 } else { 1928 env->pmsav7.drbar = g_new0(uint32_t, nr); 1929 env->pmsav7.drsr = g_new0(uint32_t, nr); 1930 env->pmsav7.dracr = g_new0(uint32_t, nr); 1931 } 1932 } 1933 } 1934 1935 if (arm_feature(env, ARM_FEATURE_M_SECURITY)) { 1936 uint32_t nr = cpu->sau_sregion; 1937 1938 if (nr > 0xff) { 1939 error_setg(errp, "v8M SAU #regions invalid %" PRIu32, nr); 1940 return; 1941 } 1942 1943 if (nr) { 1944 env->sau.rbar = g_new0(uint32_t, nr); 1945 env->sau.rlar = g_new0(uint32_t, nr); 1946 } 1947 } 1948 1949 if (arm_feature(env, ARM_FEATURE_EL3)) { 1950 set_feature(env, ARM_FEATURE_VBAR); 1951 } 1952 1953 register_cp_regs_for_features(cpu); 1954 arm_cpu_register_gdb_regs_for_features(cpu); 1955 1956 init_cpreg_list(cpu); 1957 1958 #ifndef CONFIG_USER_ONLY 1959 MachineState *ms = MACHINE(qdev_get_machine()); 1960 unsigned int smp_cpus = ms->smp.cpus; 1961 bool has_secure = cpu->has_el3 || arm_feature(env, ARM_FEATURE_M_SECURITY); 1962 1963 /* 1964 * We must set cs->num_ases to the final value before 1965 * the first call to cpu_address_space_init. 1966 */ 1967 if (cpu->tag_memory != NULL) { 1968 cs->num_ases = 3 + has_secure; 1969 } else { 1970 cs->num_ases = 1 + has_secure; 1971 } 1972 1973 if (has_secure) { 1974 if (!cpu->secure_memory) { 1975 cpu->secure_memory = cs->memory; 1976 } 1977 cpu_address_space_init(cs, ARMASIdx_S, "cpu-secure-memory", 1978 cpu->secure_memory); 1979 } 1980 1981 if (cpu->tag_memory != NULL) { 1982 cpu_address_space_init(cs, ARMASIdx_TagNS, "cpu-tag-memory", 1983 cpu->tag_memory); 1984 if (has_secure) { 1985 cpu_address_space_init(cs, ARMASIdx_TagS, "cpu-tag-memory", 1986 cpu->secure_tag_memory); 1987 } 1988 } 1989 1990 cpu_address_space_init(cs, ARMASIdx_NS, "cpu-memory", cs->memory); 1991 1992 /* No core_count specified, default to smp_cpus. */ 1993 if (cpu->core_count == -1) { 1994 cpu->core_count = smp_cpus; 1995 } 1996 #endif 1997 1998 if (tcg_enabled()) { 1999 int dcz_blocklen = 4 << cpu->dcz_blocksize; 2000 2001 /* 2002 * We only support DCZ blocklen that fits on one page. 2003 * 2004 * Architectually this is always true. However TARGET_PAGE_SIZE 2005 * is variable and, for compatibility with -machine virt-2.7, 2006 * is only 1KiB, as an artifact of legacy ARMv5 subpage support. 2007 * But even then, while the largest architectural DCZ blocklen 2008 * is 2KiB, no cpu actually uses such a large blocklen. 2009 */ 2010 assert(dcz_blocklen <= TARGET_PAGE_SIZE); 2011 2012 /* 2013 * We only support DCZ blocksize >= 2*TAG_GRANULE, which is to say 2014 * both nibbles of each byte storing tag data may be written at once. 2015 * Since TAG_GRANULE is 16, this means that blocklen must be >= 32. 2016 */ 2017 if (cpu_isar_feature(aa64_mte, cpu)) { 2018 assert(dcz_blocklen >= 2 * TAG_GRANULE); 2019 } 2020 } 2021 2022 qemu_init_vcpu(cs); 2023 cpu_reset(cs); 2024 2025 acc->parent_realize(dev, errp); 2026 } 2027 2028 static ObjectClass *arm_cpu_class_by_name(const char *cpu_model) 2029 { 2030 ObjectClass *oc; 2031 char *typename; 2032 char **cpuname; 2033 const char *cpunamestr; 2034 2035 cpuname = g_strsplit(cpu_model, ",", 1); 2036 cpunamestr = cpuname[0]; 2037 #ifdef CONFIG_USER_ONLY 2038 /* For backwards compatibility usermode emulation allows "-cpu any", 2039 * which has the same semantics as "-cpu max". 2040 */ 2041 if (!strcmp(cpunamestr, "any")) { 2042 cpunamestr = "max"; 2043 } 2044 #endif 2045 typename = g_strdup_printf(ARM_CPU_TYPE_NAME("%s"), cpunamestr); 2046 oc = object_class_by_name(typename); 2047 g_strfreev(cpuname); 2048 g_free(typename); 2049 if (!oc || !object_class_dynamic_cast(oc, TYPE_ARM_CPU) || 2050 object_class_is_abstract(oc)) { 2051 return NULL; 2052 } 2053 return oc; 2054 } 2055 2056 static Property arm_cpu_properties[] = { 2057 DEFINE_PROP_UINT64("midr", ARMCPU, midr, 0), 2058 DEFINE_PROP_UINT64("mp-affinity", ARMCPU, 2059 mp_affinity, ARM64_AFFINITY_INVALID), 2060 DEFINE_PROP_INT32("node-id", ARMCPU, node_id, CPU_UNSET_NUMA_NODE_ID), 2061 DEFINE_PROP_INT32("core-count", ARMCPU, core_count, -1), 2062 DEFINE_PROP_END_OF_LIST() 2063 }; 2064 2065 static gchar *arm_gdb_arch_name(CPUState *cs) 2066 { 2067 ARMCPU *cpu = ARM_CPU(cs); 2068 CPUARMState *env = &cpu->env; 2069 2070 if (arm_feature(env, ARM_FEATURE_IWMMXT)) { 2071 return g_strdup("iwmmxt"); 2072 } 2073 return g_strdup("arm"); 2074 } 2075 2076 #ifndef CONFIG_USER_ONLY 2077 #include "hw/core/sysemu-cpu-ops.h" 2078 2079 static const struct SysemuCPUOps arm_sysemu_ops = { 2080 .get_phys_page_attrs_debug = arm_cpu_get_phys_page_attrs_debug, 2081 .asidx_from_attrs = arm_asidx_from_attrs, 2082 .write_elf32_note = arm_cpu_write_elf32_note, 2083 .write_elf64_note = arm_cpu_write_elf64_note, 2084 .virtio_is_big_endian = arm_cpu_virtio_is_big_endian, 2085 .legacy_vmsd = &vmstate_arm_cpu, 2086 }; 2087 #endif 2088 2089 #ifdef CONFIG_TCG 2090 static const struct TCGCPUOps arm_tcg_ops = { 2091 .initialize = arm_translate_init, 2092 .synchronize_from_tb = arm_cpu_synchronize_from_tb, 2093 .debug_excp_handler = arm_debug_excp_handler, 2094 2095 #ifdef CONFIG_USER_ONLY 2096 .record_sigsegv = arm_cpu_record_sigsegv, 2097 .record_sigbus = arm_cpu_record_sigbus, 2098 #else 2099 .tlb_fill = arm_cpu_tlb_fill, 2100 .cpu_exec_interrupt = arm_cpu_exec_interrupt, 2101 .do_interrupt = arm_cpu_do_interrupt, 2102 .do_transaction_failed = arm_cpu_do_transaction_failed, 2103 .do_unaligned_access = arm_cpu_do_unaligned_access, 2104 .adjust_watchpoint_address = arm_adjust_watchpoint_address, 2105 .debug_check_watchpoint = arm_debug_check_watchpoint, 2106 .debug_check_breakpoint = arm_debug_check_breakpoint, 2107 #endif /* !CONFIG_USER_ONLY */ 2108 }; 2109 #endif /* CONFIG_TCG */ 2110 2111 static void arm_cpu_class_init(ObjectClass *oc, void *data) 2112 { 2113 ARMCPUClass *acc = ARM_CPU_CLASS(oc); 2114 CPUClass *cc = CPU_CLASS(acc); 2115 DeviceClass *dc = DEVICE_CLASS(oc); 2116 2117 device_class_set_parent_realize(dc, arm_cpu_realizefn, 2118 &acc->parent_realize); 2119 2120 device_class_set_props(dc, arm_cpu_properties); 2121 device_class_set_parent_reset(dc, arm_cpu_reset, &acc->parent_reset); 2122 2123 cc->class_by_name = arm_cpu_class_by_name; 2124 cc->has_work = arm_cpu_has_work; 2125 cc->dump_state = arm_cpu_dump_state; 2126 cc->set_pc = arm_cpu_set_pc; 2127 cc->gdb_read_register = arm_cpu_gdb_read_register; 2128 cc->gdb_write_register = arm_cpu_gdb_write_register; 2129 #ifndef CONFIG_USER_ONLY 2130 cc->sysemu_ops = &arm_sysemu_ops; 2131 #endif 2132 cc->gdb_num_core_regs = 26; 2133 cc->gdb_core_xml_file = "arm-core.xml"; 2134 cc->gdb_arch_name = arm_gdb_arch_name; 2135 cc->gdb_get_dynamic_xml = arm_gdb_get_dynamic_xml; 2136 cc->gdb_stop_before_watchpoint = true; 2137 cc->disas_set_info = arm_disas_set_info; 2138 2139 #ifdef CONFIG_TCG 2140 cc->tcg_ops = &arm_tcg_ops; 2141 #endif /* CONFIG_TCG */ 2142 } 2143 2144 static void arm_cpu_instance_init(Object *obj) 2145 { 2146 ARMCPUClass *acc = ARM_CPU_GET_CLASS(obj); 2147 2148 acc->info->initfn(obj); 2149 arm_cpu_post_init(obj); 2150 } 2151 2152 static void cpu_register_class_init(ObjectClass *oc, void *data) 2153 { 2154 ARMCPUClass *acc = ARM_CPU_CLASS(oc); 2155 2156 acc->info = data; 2157 } 2158 2159 void arm_cpu_register(const ARMCPUInfo *info) 2160 { 2161 TypeInfo type_info = { 2162 .parent = TYPE_ARM_CPU, 2163 .instance_size = sizeof(ARMCPU), 2164 .instance_align = __alignof__(ARMCPU), 2165 .instance_init = arm_cpu_instance_init, 2166 .class_size = sizeof(ARMCPUClass), 2167 .class_init = info->class_init ?: cpu_register_class_init, 2168 .class_data = (void *)info, 2169 }; 2170 2171 type_info.name = g_strdup_printf("%s-" TYPE_ARM_CPU, info->name); 2172 type_register(&type_info); 2173 g_free((void *)type_info.name); 2174 } 2175 2176 static const TypeInfo arm_cpu_type_info = { 2177 .name = TYPE_ARM_CPU, 2178 .parent = TYPE_CPU, 2179 .instance_size = sizeof(ARMCPU), 2180 .instance_align = __alignof__(ARMCPU), 2181 .instance_init = arm_cpu_initfn, 2182 .instance_finalize = arm_cpu_finalizefn, 2183 .abstract = true, 2184 .class_size = sizeof(ARMCPUClass), 2185 .class_init = arm_cpu_class_init, 2186 }; 2187 2188 static void arm_cpu_register_types(void) 2189 { 2190 type_register_static(&arm_cpu_type_info); 2191 } 2192 2193 type_init(arm_cpu_register_types) 2194