1 /* 2 * QEMU ARM CPU 3 * 4 * Copyright (c) 2012 SUSE LINUX Products GmbH 5 * 6 * This program is free software; you can redistribute it and/or 7 * modify it under the terms of the GNU General Public License 8 * as published by the Free Software Foundation; either version 2 9 * of the License, or (at your option) any later version. 10 * 11 * This program is distributed in the hope that it will be useful, 12 * but WITHOUT ANY WARRANTY; without even the implied warranty of 13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 14 * GNU General Public License for more details. 15 * 16 * You should have received a copy of the GNU General Public License 17 * along with this program; if not, see 18 * <http://www.gnu.org/licenses/gpl-2.0.html> 19 */ 20 21 #include "qemu/osdep.h" 22 #include "target/arm/idau.h" 23 #include "qemu/error-report.h" 24 #include "qapi/error.h" 25 #include "cpu.h" 26 #include "internals.h" 27 #include "qemu-common.h" 28 #include "exec/exec-all.h" 29 #include "hw/qdev-properties.h" 30 #if !defined(CONFIG_USER_ONLY) 31 #include "hw/loader.h" 32 #endif 33 #include "hw/arm/arm.h" 34 #include "sysemu/sysemu.h" 35 #include "sysemu/hw_accel.h" 36 #include "kvm_arm.h" 37 #include "disas/capstone.h" 38 #include "fpu/softfloat.h" 39 40 static void arm_cpu_set_pc(CPUState *cs, vaddr value) 41 { 42 ARMCPU *cpu = ARM_CPU(cs); 43 CPUARMState *env = &cpu->env; 44 45 if (is_a64(env)) { 46 env->pc = value; 47 env->thumb = 0; 48 } else { 49 env->regs[15] = value & ~1; 50 env->thumb = value & 1; 51 } 52 } 53 54 static void arm_cpu_synchronize_from_tb(CPUState *cs, TranslationBlock *tb) 55 { 56 ARMCPU *cpu = ARM_CPU(cs); 57 CPUARMState *env = &cpu->env; 58 59 /* 60 * It's OK to look at env for the current mode here, because it's 61 * never possible for an AArch64 TB to chain to an AArch32 TB. 62 */ 63 if (is_a64(env)) { 64 env->pc = tb->pc; 65 } else { 66 env->regs[15] = tb->pc; 67 } 68 } 69 70 static bool arm_cpu_has_work(CPUState *cs) 71 { 72 ARMCPU *cpu = ARM_CPU(cs); 73 74 return (cpu->power_state != PSCI_OFF) 75 && cs->interrupt_request & 76 (CPU_INTERRUPT_FIQ | CPU_INTERRUPT_HARD 77 | CPU_INTERRUPT_VFIQ | CPU_INTERRUPT_VIRQ 78 | CPU_INTERRUPT_EXITTB); 79 } 80 81 void arm_register_pre_el_change_hook(ARMCPU *cpu, ARMELChangeHookFn *hook, 82 void *opaque) 83 { 84 ARMELChangeHook *entry = g_new0(ARMELChangeHook, 1); 85 86 entry->hook = hook; 87 entry->opaque = opaque; 88 89 QLIST_INSERT_HEAD(&cpu->pre_el_change_hooks, entry, node); 90 } 91 92 void arm_register_el_change_hook(ARMCPU *cpu, ARMELChangeHookFn *hook, 93 void *opaque) 94 { 95 ARMELChangeHook *entry = g_new0(ARMELChangeHook, 1); 96 97 entry->hook = hook; 98 entry->opaque = opaque; 99 100 QLIST_INSERT_HEAD(&cpu->el_change_hooks, entry, node); 101 } 102 103 static void cp_reg_reset(gpointer key, gpointer value, gpointer opaque) 104 { 105 /* Reset a single ARMCPRegInfo register */ 106 ARMCPRegInfo *ri = value; 107 ARMCPU *cpu = opaque; 108 109 if (ri->type & (ARM_CP_SPECIAL | ARM_CP_ALIAS)) { 110 return; 111 } 112 113 if (ri->resetfn) { 114 ri->resetfn(&cpu->env, ri); 115 return; 116 } 117 118 /* A zero offset is never possible as it would be regs[0] 119 * so we use it to indicate that reset is being handled elsewhere. 120 * This is basically only used for fields in non-core coprocessors 121 * (like the pxa2xx ones). 122 */ 123 if (!ri->fieldoffset) { 124 return; 125 } 126 127 if (cpreg_field_is_64bit(ri)) { 128 CPREG_FIELD64(&cpu->env, ri) = ri->resetvalue; 129 } else { 130 CPREG_FIELD32(&cpu->env, ri) = ri->resetvalue; 131 } 132 } 133 134 static void cp_reg_check_reset(gpointer key, gpointer value, gpointer opaque) 135 { 136 /* Purely an assertion check: we've already done reset once, 137 * so now check that running the reset for the cpreg doesn't 138 * change its value. This traps bugs where two different cpregs 139 * both try to reset the same state field but to different values. 140 */ 141 ARMCPRegInfo *ri = value; 142 ARMCPU *cpu = opaque; 143 uint64_t oldvalue, newvalue; 144 145 if (ri->type & (ARM_CP_SPECIAL | ARM_CP_ALIAS | ARM_CP_NO_RAW)) { 146 return; 147 } 148 149 oldvalue = read_raw_cp_reg(&cpu->env, ri); 150 cp_reg_reset(key, value, opaque); 151 newvalue = read_raw_cp_reg(&cpu->env, ri); 152 assert(oldvalue == newvalue); 153 } 154 155 /* CPUClass::reset() */ 156 static void arm_cpu_reset(CPUState *s) 157 { 158 ARMCPU *cpu = ARM_CPU(s); 159 ARMCPUClass *acc = ARM_CPU_GET_CLASS(cpu); 160 CPUARMState *env = &cpu->env; 161 162 acc->parent_reset(s); 163 164 memset(env, 0, offsetof(CPUARMState, end_reset_fields)); 165 166 g_hash_table_foreach(cpu->cp_regs, cp_reg_reset, cpu); 167 g_hash_table_foreach(cpu->cp_regs, cp_reg_check_reset, cpu); 168 169 env->vfp.xregs[ARM_VFP_FPSID] = cpu->reset_fpsid; 170 env->vfp.xregs[ARM_VFP_MVFR0] = cpu->isar.mvfr0; 171 env->vfp.xregs[ARM_VFP_MVFR1] = cpu->isar.mvfr1; 172 env->vfp.xregs[ARM_VFP_MVFR2] = cpu->isar.mvfr2; 173 174 cpu->power_state = cpu->start_powered_off ? PSCI_OFF : PSCI_ON; 175 s->halted = cpu->start_powered_off; 176 177 if (arm_feature(env, ARM_FEATURE_IWMMXT)) { 178 env->iwmmxt.cregs[ARM_IWMMXT_wCID] = 0x69051000 | 'Q'; 179 } 180 181 if (arm_feature(env, ARM_FEATURE_AARCH64)) { 182 /* 64 bit CPUs always start in 64 bit mode */ 183 env->aarch64 = 1; 184 #if defined(CONFIG_USER_ONLY) 185 env->pstate = PSTATE_MODE_EL0t; 186 /* Userspace expects access to DC ZVA, CTL_EL0 and the cache ops */ 187 env->cp15.sctlr_el[1] |= SCTLR_UCT | SCTLR_UCI | SCTLR_DZE; 188 /* Enable all PAC keys. */ 189 env->cp15.sctlr_el[1] |= (SCTLR_EnIA | SCTLR_EnIB | 190 SCTLR_EnDA | SCTLR_EnDB); 191 /* Enable all PAC instructions */ 192 env->cp15.hcr_el2 |= HCR_API; 193 env->cp15.scr_el3 |= SCR_API; 194 /* and to the FP/Neon instructions */ 195 env->cp15.cpacr_el1 = deposit64(env->cp15.cpacr_el1, 20, 2, 3); 196 /* and to the SVE instructions */ 197 env->cp15.cpacr_el1 = deposit64(env->cp15.cpacr_el1, 16, 2, 3); 198 env->cp15.cptr_el[3] |= CPTR_EZ; 199 /* with maximum vector length */ 200 env->vfp.zcr_el[1] = cpu->sve_max_vq - 1; 201 env->vfp.zcr_el[2] = env->vfp.zcr_el[1]; 202 env->vfp.zcr_el[3] = env->vfp.zcr_el[1]; 203 /* 204 * Enable TBI0 and TBI1. While the real kernel only enables TBI0, 205 * turning on both here will produce smaller code and otherwise 206 * make no difference to the user-level emulation. 207 */ 208 env->cp15.tcr_el[1].raw_tcr = (3ULL << 37); 209 #else 210 /* Reset into the highest available EL */ 211 if (arm_feature(env, ARM_FEATURE_EL3)) { 212 env->pstate = PSTATE_MODE_EL3h; 213 } else if (arm_feature(env, ARM_FEATURE_EL2)) { 214 env->pstate = PSTATE_MODE_EL2h; 215 } else { 216 env->pstate = PSTATE_MODE_EL1h; 217 } 218 env->pc = cpu->rvbar; 219 #endif 220 } else { 221 #if defined(CONFIG_USER_ONLY) 222 /* Userspace expects access to cp10 and cp11 for FP/Neon */ 223 env->cp15.cpacr_el1 = deposit64(env->cp15.cpacr_el1, 20, 4, 0xf); 224 #endif 225 } 226 227 #if defined(CONFIG_USER_ONLY) 228 env->uncached_cpsr = ARM_CPU_MODE_USR; 229 /* For user mode we must enable access to coprocessors */ 230 env->vfp.xregs[ARM_VFP_FPEXC] = 1 << 30; 231 if (arm_feature(env, ARM_FEATURE_IWMMXT)) { 232 env->cp15.c15_cpar = 3; 233 } else if (arm_feature(env, ARM_FEATURE_XSCALE)) { 234 env->cp15.c15_cpar = 1; 235 } 236 #else 237 238 /* 239 * If the highest available EL is EL2, AArch32 will start in Hyp 240 * mode; otherwise it starts in SVC. Note that if we start in 241 * AArch64 then these values in the uncached_cpsr will be ignored. 242 */ 243 if (arm_feature(env, ARM_FEATURE_EL2) && 244 !arm_feature(env, ARM_FEATURE_EL3)) { 245 env->uncached_cpsr = ARM_CPU_MODE_HYP; 246 } else { 247 env->uncached_cpsr = ARM_CPU_MODE_SVC; 248 } 249 env->daif = PSTATE_D | PSTATE_A | PSTATE_I | PSTATE_F; 250 251 if (arm_feature(env, ARM_FEATURE_M)) { 252 uint32_t initial_msp; /* Loaded from 0x0 */ 253 uint32_t initial_pc; /* Loaded from 0x4 */ 254 uint8_t *rom; 255 uint32_t vecbase; 256 257 if (arm_feature(env, ARM_FEATURE_M_SECURITY)) { 258 env->v7m.secure = true; 259 } else { 260 /* This bit resets to 0 if security is supported, but 1 if 261 * it is not. The bit is not present in v7M, but we set it 262 * here so we can avoid having to make checks on it conditional 263 * on ARM_FEATURE_V8 (we don't let the guest see the bit). 264 */ 265 env->v7m.aircr = R_V7M_AIRCR_BFHFNMINS_MASK; 266 } 267 268 /* In v7M the reset value of this bit is IMPDEF, but ARM recommends 269 * that it resets to 1, so QEMU always does that rather than making 270 * it dependent on CPU model. In v8M it is RES1. 271 */ 272 env->v7m.ccr[M_REG_NS] = R_V7M_CCR_STKALIGN_MASK; 273 env->v7m.ccr[M_REG_S] = R_V7M_CCR_STKALIGN_MASK; 274 if (arm_feature(env, ARM_FEATURE_V8)) { 275 /* in v8M the NONBASETHRDENA bit [0] is RES1 */ 276 env->v7m.ccr[M_REG_NS] |= R_V7M_CCR_NONBASETHRDENA_MASK; 277 env->v7m.ccr[M_REG_S] |= R_V7M_CCR_NONBASETHRDENA_MASK; 278 } 279 if (!arm_feature(env, ARM_FEATURE_M_MAIN)) { 280 env->v7m.ccr[M_REG_NS] |= R_V7M_CCR_UNALIGN_TRP_MASK; 281 env->v7m.ccr[M_REG_S] |= R_V7M_CCR_UNALIGN_TRP_MASK; 282 } 283 284 /* Unlike A/R profile, M profile defines the reset LR value */ 285 env->regs[14] = 0xffffffff; 286 287 env->v7m.vecbase[M_REG_S] = cpu->init_svtor & 0xffffff80; 288 289 /* Load the initial SP and PC from offset 0 and 4 in the vector table */ 290 vecbase = env->v7m.vecbase[env->v7m.secure]; 291 rom = rom_ptr(vecbase, 8); 292 if (rom) { 293 /* Address zero is covered by ROM which hasn't yet been 294 * copied into physical memory. 295 */ 296 initial_msp = ldl_p(rom); 297 initial_pc = ldl_p(rom + 4); 298 } else { 299 /* Address zero not covered by a ROM blob, or the ROM blob 300 * is in non-modifiable memory and this is a second reset after 301 * it got copied into memory. In the latter case, rom_ptr 302 * will return a NULL pointer and we should use ldl_phys instead. 303 */ 304 initial_msp = ldl_phys(s->as, vecbase); 305 initial_pc = ldl_phys(s->as, vecbase + 4); 306 } 307 308 env->regs[13] = initial_msp & 0xFFFFFFFC; 309 env->regs[15] = initial_pc & ~1; 310 env->thumb = initial_pc & 1; 311 } 312 313 /* AArch32 has a hard highvec setting of 0xFFFF0000. If we are currently 314 * executing as AArch32 then check if highvecs are enabled and 315 * adjust the PC accordingly. 316 */ 317 if (A32_BANKED_CURRENT_REG_GET(env, sctlr) & SCTLR_V) { 318 env->regs[15] = 0xFFFF0000; 319 } 320 321 /* M profile requires that reset clears the exclusive monitor; 322 * A profile does not, but clearing it makes more sense than having it 323 * set with an exclusive access on address zero. 324 */ 325 arm_clear_exclusive(env); 326 327 env->vfp.xregs[ARM_VFP_FPEXC] = 0; 328 #endif 329 330 if (arm_feature(env, ARM_FEATURE_PMSA)) { 331 if (cpu->pmsav7_dregion > 0) { 332 if (arm_feature(env, ARM_FEATURE_V8)) { 333 memset(env->pmsav8.rbar[M_REG_NS], 0, 334 sizeof(*env->pmsav8.rbar[M_REG_NS]) 335 * cpu->pmsav7_dregion); 336 memset(env->pmsav8.rlar[M_REG_NS], 0, 337 sizeof(*env->pmsav8.rlar[M_REG_NS]) 338 * cpu->pmsav7_dregion); 339 if (arm_feature(env, ARM_FEATURE_M_SECURITY)) { 340 memset(env->pmsav8.rbar[M_REG_S], 0, 341 sizeof(*env->pmsav8.rbar[M_REG_S]) 342 * cpu->pmsav7_dregion); 343 memset(env->pmsav8.rlar[M_REG_S], 0, 344 sizeof(*env->pmsav8.rlar[M_REG_S]) 345 * cpu->pmsav7_dregion); 346 } 347 } else if (arm_feature(env, ARM_FEATURE_V7)) { 348 memset(env->pmsav7.drbar, 0, 349 sizeof(*env->pmsav7.drbar) * cpu->pmsav7_dregion); 350 memset(env->pmsav7.drsr, 0, 351 sizeof(*env->pmsav7.drsr) * cpu->pmsav7_dregion); 352 memset(env->pmsav7.dracr, 0, 353 sizeof(*env->pmsav7.dracr) * cpu->pmsav7_dregion); 354 } 355 } 356 env->pmsav7.rnr[M_REG_NS] = 0; 357 env->pmsav7.rnr[M_REG_S] = 0; 358 env->pmsav8.mair0[M_REG_NS] = 0; 359 env->pmsav8.mair0[M_REG_S] = 0; 360 env->pmsav8.mair1[M_REG_NS] = 0; 361 env->pmsav8.mair1[M_REG_S] = 0; 362 } 363 364 if (arm_feature(env, ARM_FEATURE_M_SECURITY)) { 365 if (cpu->sau_sregion > 0) { 366 memset(env->sau.rbar, 0, sizeof(*env->sau.rbar) * cpu->sau_sregion); 367 memset(env->sau.rlar, 0, sizeof(*env->sau.rlar) * cpu->sau_sregion); 368 } 369 env->sau.rnr = 0; 370 /* SAU_CTRL reset value is IMPDEF; we choose 0, which is what 371 * the Cortex-M33 does. 372 */ 373 env->sau.ctrl = 0; 374 } 375 376 set_flush_to_zero(1, &env->vfp.standard_fp_status); 377 set_flush_inputs_to_zero(1, &env->vfp.standard_fp_status); 378 set_default_nan_mode(1, &env->vfp.standard_fp_status); 379 set_float_detect_tininess(float_tininess_before_rounding, 380 &env->vfp.fp_status); 381 set_float_detect_tininess(float_tininess_before_rounding, 382 &env->vfp.standard_fp_status); 383 set_float_detect_tininess(float_tininess_before_rounding, 384 &env->vfp.fp_status_f16); 385 #ifndef CONFIG_USER_ONLY 386 if (kvm_enabled()) { 387 kvm_arm_reset_vcpu(cpu); 388 } 389 #endif 390 391 hw_breakpoint_update_all(cpu); 392 hw_watchpoint_update_all(cpu); 393 } 394 395 bool arm_cpu_exec_interrupt(CPUState *cs, int interrupt_request) 396 { 397 CPUClass *cc = CPU_GET_CLASS(cs); 398 CPUARMState *env = cs->env_ptr; 399 uint32_t cur_el = arm_current_el(env); 400 bool secure = arm_is_secure(env); 401 uint32_t target_el; 402 uint32_t excp_idx; 403 bool ret = false; 404 405 if (interrupt_request & CPU_INTERRUPT_FIQ) { 406 excp_idx = EXCP_FIQ; 407 target_el = arm_phys_excp_target_el(cs, excp_idx, cur_el, secure); 408 if (arm_excp_unmasked(cs, excp_idx, target_el)) { 409 cs->exception_index = excp_idx; 410 env->exception.target_el = target_el; 411 cc->do_interrupt(cs); 412 ret = true; 413 } 414 } 415 if (interrupt_request & CPU_INTERRUPT_HARD) { 416 excp_idx = EXCP_IRQ; 417 target_el = arm_phys_excp_target_el(cs, excp_idx, cur_el, secure); 418 if (arm_excp_unmasked(cs, excp_idx, target_el)) { 419 cs->exception_index = excp_idx; 420 env->exception.target_el = target_el; 421 cc->do_interrupt(cs); 422 ret = true; 423 } 424 } 425 if (interrupt_request & CPU_INTERRUPT_VIRQ) { 426 excp_idx = EXCP_VIRQ; 427 target_el = 1; 428 if (arm_excp_unmasked(cs, excp_idx, target_el)) { 429 cs->exception_index = excp_idx; 430 env->exception.target_el = target_el; 431 cc->do_interrupt(cs); 432 ret = true; 433 } 434 } 435 if (interrupt_request & CPU_INTERRUPT_VFIQ) { 436 excp_idx = EXCP_VFIQ; 437 target_el = 1; 438 if (arm_excp_unmasked(cs, excp_idx, target_el)) { 439 cs->exception_index = excp_idx; 440 env->exception.target_el = target_el; 441 cc->do_interrupt(cs); 442 ret = true; 443 } 444 } 445 446 return ret; 447 } 448 449 #if !defined(CONFIG_USER_ONLY) || !defined(TARGET_AARCH64) 450 static bool arm_v7m_cpu_exec_interrupt(CPUState *cs, int interrupt_request) 451 { 452 CPUClass *cc = CPU_GET_CLASS(cs); 453 ARMCPU *cpu = ARM_CPU(cs); 454 CPUARMState *env = &cpu->env; 455 bool ret = false; 456 457 /* ARMv7-M interrupt masking works differently than -A or -R. 458 * There is no FIQ/IRQ distinction. Instead of I and F bits 459 * masking FIQ and IRQ interrupts, an exception is taken only 460 * if it is higher priority than the current execution priority 461 * (which depends on state like BASEPRI, FAULTMASK and the 462 * currently active exception). 463 */ 464 if (interrupt_request & CPU_INTERRUPT_HARD 465 && (armv7m_nvic_can_take_pending_exception(env->nvic))) { 466 cs->exception_index = EXCP_IRQ; 467 cc->do_interrupt(cs); 468 ret = true; 469 } 470 return ret; 471 } 472 #endif 473 474 void arm_cpu_update_virq(ARMCPU *cpu) 475 { 476 /* 477 * Update the interrupt level for VIRQ, which is the logical OR of 478 * the HCR_EL2.VI bit and the input line level from the GIC. 479 */ 480 CPUARMState *env = &cpu->env; 481 CPUState *cs = CPU(cpu); 482 483 bool new_state = (env->cp15.hcr_el2 & HCR_VI) || 484 (env->irq_line_state & CPU_INTERRUPT_VIRQ); 485 486 if (new_state != ((cs->interrupt_request & CPU_INTERRUPT_VIRQ) != 0)) { 487 if (new_state) { 488 cpu_interrupt(cs, CPU_INTERRUPT_VIRQ); 489 } else { 490 cpu_reset_interrupt(cs, CPU_INTERRUPT_VIRQ); 491 } 492 } 493 } 494 495 void arm_cpu_update_vfiq(ARMCPU *cpu) 496 { 497 /* 498 * Update the interrupt level for VFIQ, which is the logical OR of 499 * the HCR_EL2.VF bit and the input line level from the GIC. 500 */ 501 CPUARMState *env = &cpu->env; 502 CPUState *cs = CPU(cpu); 503 504 bool new_state = (env->cp15.hcr_el2 & HCR_VF) || 505 (env->irq_line_state & CPU_INTERRUPT_VFIQ); 506 507 if (new_state != ((cs->interrupt_request & CPU_INTERRUPT_VFIQ) != 0)) { 508 if (new_state) { 509 cpu_interrupt(cs, CPU_INTERRUPT_VFIQ); 510 } else { 511 cpu_reset_interrupt(cs, CPU_INTERRUPT_VFIQ); 512 } 513 } 514 } 515 516 #ifndef CONFIG_USER_ONLY 517 static void arm_cpu_set_irq(void *opaque, int irq, int level) 518 { 519 ARMCPU *cpu = opaque; 520 CPUARMState *env = &cpu->env; 521 CPUState *cs = CPU(cpu); 522 static const int mask[] = { 523 [ARM_CPU_IRQ] = CPU_INTERRUPT_HARD, 524 [ARM_CPU_FIQ] = CPU_INTERRUPT_FIQ, 525 [ARM_CPU_VIRQ] = CPU_INTERRUPT_VIRQ, 526 [ARM_CPU_VFIQ] = CPU_INTERRUPT_VFIQ 527 }; 528 529 if (level) { 530 env->irq_line_state |= mask[irq]; 531 } else { 532 env->irq_line_state &= ~mask[irq]; 533 } 534 535 switch (irq) { 536 case ARM_CPU_VIRQ: 537 assert(arm_feature(env, ARM_FEATURE_EL2)); 538 arm_cpu_update_virq(cpu); 539 break; 540 case ARM_CPU_VFIQ: 541 assert(arm_feature(env, ARM_FEATURE_EL2)); 542 arm_cpu_update_vfiq(cpu); 543 break; 544 case ARM_CPU_IRQ: 545 case ARM_CPU_FIQ: 546 if (level) { 547 cpu_interrupt(cs, mask[irq]); 548 } else { 549 cpu_reset_interrupt(cs, mask[irq]); 550 } 551 break; 552 default: 553 g_assert_not_reached(); 554 } 555 } 556 557 static void arm_cpu_kvm_set_irq(void *opaque, int irq, int level) 558 { 559 #ifdef CONFIG_KVM 560 ARMCPU *cpu = opaque; 561 CPUARMState *env = &cpu->env; 562 CPUState *cs = CPU(cpu); 563 int kvm_irq = KVM_ARM_IRQ_TYPE_CPU << KVM_ARM_IRQ_TYPE_SHIFT; 564 uint32_t linestate_bit; 565 566 switch (irq) { 567 case ARM_CPU_IRQ: 568 kvm_irq |= KVM_ARM_IRQ_CPU_IRQ; 569 linestate_bit = CPU_INTERRUPT_HARD; 570 break; 571 case ARM_CPU_FIQ: 572 kvm_irq |= KVM_ARM_IRQ_CPU_FIQ; 573 linestate_bit = CPU_INTERRUPT_FIQ; 574 break; 575 default: 576 g_assert_not_reached(); 577 } 578 579 if (level) { 580 env->irq_line_state |= linestate_bit; 581 } else { 582 env->irq_line_state &= ~linestate_bit; 583 } 584 585 kvm_irq |= cs->cpu_index << KVM_ARM_IRQ_VCPU_SHIFT; 586 kvm_set_irq(kvm_state, kvm_irq, level ? 1 : 0); 587 #endif 588 } 589 590 static bool arm_cpu_virtio_is_big_endian(CPUState *cs) 591 { 592 ARMCPU *cpu = ARM_CPU(cs); 593 CPUARMState *env = &cpu->env; 594 595 cpu_synchronize_state(cs); 596 return arm_cpu_data_is_big_endian(env); 597 } 598 599 #endif 600 601 static inline void set_feature(CPUARMState *env, int feature) 602 { 603 env->features |= 1ULL << feature; 604 } 605 606 static inline void unset_feature(CPUARMState *env, int feature) 607 { 608 env->features &= ~(1ULL << feature); 609 } 610 611 static int 612 print_insn_thumb1(bfd_vma pc, disassemble_info *info) 613 { 614 return print_insn_arm(pc | 1, info); 615 } 616 617 static void arm_disas_set_info(CPUState *cpu, disassemble_info *info) 618 { 619 ARMCPU *ac = ARM_CPU(cpu); 620 CPUARMState *env = &ac->env; 621 bool sctlr_b; 622 623 if (is_a64(env)) { 624 /* We might not be compiled with the A64 disassembler 625 * because it needs a C++ compiler. Leave print_insn 626 * unset in this case to use the caller default behaviour. 627 */ 628 #if defined(CONFIG_ARM_A64_DIS) 629 info->print_insn = print_insn_arm_a64; 630 #endif 631 info->cap_arch = CS_ARCH_ARM64; 632 info->cap_insn_unit = 4; 633 info->cap_insn_split = 4; 634 } else { 635 int cap_mode; 636 if (env->thumb) { 637 info->print_insn = print_insn_thumb1; 638 info->cap_insn_unit = 2; 639 info->cap_insn_split = 4; 640 cap_mode = CS_MODE_THUMB; 641 } else { 642 info->print_insn = print_insn_arm; 643 info->cap_insn_unit = 4; 644 info->cap_insn_split = 4; 645 cap_mode = CS_MODE_ARM; 646 } 647 if (arm_feature(env, ARM_FEATURE_V8)) { 648 cap_mode |= CS_MODE_V8; 649 } 650 if (arm_feature(env, ARM_FEATURE_M)) { 651 cap_mode |= CS_MODE_MCLASS; 652 } 653 info->cap_arch = CS_ARCH_ARM; 654 info->cap_mode = cap_mode; 655 } 656 657 sctlr_b = arm_sctlr_b(env); 658 if (bswap_code(sctlr_b)) { 659 #ifdef TARGET_WORDS_BIGENDIAN 660 info->endian = BFD_ENDIAN_LITTLE; 661 #else 662 info->endian = BFD_ENDIAN_BIG; 663 #endif 664 } 665 info->flags &= ~INSN_ARM_BE32; 666 #ifndef CONFIG_USER_ONLY 667 if (sctlr_b) { 668 info->flags |= INSN_ARM_BE32; 669 } 670 #endif 671 } 672 673 uint64_t arm_cpu_mp_affinity(int idx, uint8_t clustersz) 674 { 675 uint32_t Aff1 = idx / clustersz; 676 uint32_t Aff0 = idx % clustersz; 677 return (Aff1 << ARM_AFF1_SHIFT) | Aff0; 678 } 679 680 static void cpreg_hashtable_data_destroy(gpointer data) 681 { 682 /* 683 * Destroy function for cpu->cp_regs hashtable data entries. 684 * We must free the name string because it was g_strdup()ed in 685 * add_cpreg_to_hashtable(). It's OK to cast away the 'const' 686 * from r->name because we know we definitely allocated it. 687 */ 688 ARMCPRegInfo *r = data; 689 690 g_free((void *)r->name); 691 g_free(r); 692 } 693 694 static void arm_cpu_initfn(Object *obj) 695 { 696 CPUState *cs = CPU(obj); 697 ARMCPU *cpu = ARM_CPU(obj); 698 699 cs->env_ptr = &cpu->env; 700 cpu->cp_regs = g_hash_table_new_full(g_int_hash, g_int_equal, 701 g_free, cpreg_hashtable_data_destroy); 702 703 QLIST_INIT(&cpu->pre_el_change_hooks); 704 QLIST_INIT(&cpu->el_change_hooks); 705 706 #ifndef CONFIG_USER_ONLY 707 /* Our inbound IRQ and FIQ lines */ 708 if (kvm_enabled()) { 709 /* VIRQ and VFIQ are unused with KVM but we add them to maintain 710 * the same interface as non-KVM CPUs. 711 */ 712 qdev_init_gpio_in(DEVICE(cpu), arm_cpu_kvm_set_irq, 4); 713 } else { 714 qdev_init_gpio_in(DEVICE(cpu), arm_cpu_set_irq, 4); 715 } 716 717 qdev_init_gpio_out(DEVICE(cpu), cpu->gt_timer_outputs, 718 ARRAY_SIZE(cpu->gt_timer_outputs)); 719 720 qdev_init_gpio_out_named(DEVICE(cpu), &cpu->gicv3_maintenance_interrupt, 721 "gicv3-maintenance-interrupt", 1); 722 qdev_init_gpio_out_named(DEVICE(cpu), &cpu->pmu_interrupt, 723 "pmu-interrupt", 1); 724 #endif 725 726 /* DTB consumers generally don't in fact care what the 'compatible' 727 * string is, so always provide some string and trust that a hypothetical 728 * picky DTB consumer will also provide a helpful error message. 729 */ 730 cpu->dtb_compatible = "qemu,unknown"; 731 cpu->psci_version = 1; /* By default assume PSCI v0.1 */ 732 cpu->kvm_target = QEMU_KVM_ARM_TARGET_NONE; 733 734 if (tcg_enabled()) { 735 cpu->psci_version = 2; /* TCG implements PSCI 0.2 */ 736 } 737 } 738 739 static Property arm_cpu_reset_cbar_property = 740 DEFINE_PROP_UINT64("reset-cbar", ARMCPU, reset_cbar, 0); 741 742 static Property arm_cpu_reset_hivecs_property = 743 DEFINE_PROP_BOOL("reset-hivecs", ARMCPU, reset_hivecs, false); 744 745 static Property arm_cpu_rvbar_property = 746 DEFINE_PROP_UINT64("rvbar", ARMCPU, rvbar, 0); 747 748 static Property arm_cpu_has_el2_property = 749 DEFINE_PROP_BOOL("has_el2", ARMCPU, has_el2, true); 750 751 static Property arm_cpu_has_el3_property = 752 DEFINE_PROP_BOOL("has_el3", ARMCPU, has_el3, true); 753 754 static Property arm_cpu_cfgend_property = 755 DEFINE_PROP_BOOL("cfgend", ARMCPU, cfgend, false); 756 757 /* use property name "pmu" to match other archs and virt tools */ 758 static Property arm_cpu_has_pmu_property = 759 DEFINE_PROP_BOOL("pmu", ARMCPU, has_pmu, true); 760 761 static Property arm_cpu_has_mpu_property = 762 DEFINE_PROP_BOOL("has-mpu", ARMCPU, has_mpu, true); 763 764 /* This is like DEFINE_PROP_UINT32 but it doesn't set the default value, 765 * because the CPU initfn will have already set cpu->pmsav7_dregion to 766 * the right value for that particular CPU type, and we don't want 767 * to override that with an incorrect constant value. 768 */ 769 static Property arm_cpu_pmsav7_dregion_property = 770 DEFINE_PROP_UNSIGNED_NODEFAULT("pmsav7-dregion", ARMCPU, 771 pmsav7_dregion, 772 qdev_prop_uint32, uint32_t); 773 774 /* M profile: initial value of the Secure VTOR */ 775 static Property arm_cpu_initsvtor_property = 776 DEFINE_PROP_UINT32("init-svtor", ARMCPU, init_svtor, 0); 777 778 void arm_cpu_post_init(Object *obj) 779 { 780 ARMCPU *cpu = ARM_CPU(obj); 781 782 /* M profile implies PMSA. We have to do this here rather than 783 * in realize with the other feature-implication checks because 784 * we look at the PMSA bit to see if we should add some properties. 785 */ 786 if (arm_feature(&cpu->env, ARM_FEATURE_M)) { 787 set_feature(&cpu->env, ARM_FEATURE_PMSA); 788 } 789 790 if (arm_feature(&cpu->env, ARM_FEATURE_CBAR) || 791 arm_feature(&cpu->env, ARM_FEATURE_CBAR_RO)) { 792 qdev_property_add_static(DEVICE(obj), &arm_cpu_reset_cbar_property, 793 &error_abort); 794 } 795 796 if (!arm_feature(&cpu->env, ARM_FEATURE_M)) { 797 qdev_property_add_static(DEVICE(obj), &arm_cpu_reset_hivecs_property, 798 &error_abort); 799 } 800 801 if (arm_feature(&cpu->env, ARM_FEATURE_AARCH64)) { 802 qdev_property_add_static(DEVICE(obj), &arm_cpu_rvbar_property, 803 &error_abort); 804 } 805 806 if (arm_feature(&cpu->env, ARM_FEATURE_EL3)) { 807 /* Add the has_el3 state CPU property only if EL3 is allowed. This will 808 * prevent "has_el3" from existing on CPUs which cannot support EL3. 809 */ 810 qdev_property_add_static(DEVICE(obj), &arm_cpu_has_el3_property, 811 &error_abort); 812 813 #ifndef CONFIG_USER_ONLY 814 object_property_add_link(obj, "secure-memory", 815 TYPE_MEMORY_REGION, 816 (Object **)&cpu->secure_memory, 817 qdev_prop_allow_set_link_before_realize, 818 OBJ_PROP_LINK_STRONG, 819 &error_abort); 820 #endif 821 } 822 823 if (arm_feature(&cpu->env, ARM_FEATURE_EL2)) { 824 qdev_property_add_static(DEVICE(obj), &arm_cpu_has_el2_property, 825 &error_abort); 826 } 827 828 if (arm_feature(&cpu->env, ARM_FEATURE_PMU)) { 829 qdev_property_add_static(DEVICE(obj), &arm_cpu_has_pmu_property, 830 &error_abort); 831 } 832 833 if (arm_feature(&cpu->env, ARM_FEATURE_PMSA)) { 834 qdev_property_add_static(DEVICE(obj), &arm_cpu_has_mpu_property, 835 &error_abort); 836 if (arm_feature(&cpu->env, ARM_FEATURE_V7)) { 837 qdev_property_add_static(DEVICE(obj), 838 &arm_cpu_pmsav7_dregion_property, 839 &error_abort); 840 } 841 } 842 843 if (arm_feature(&cpu->env, ARM_FEATURE_M_SECURITY)) { 844 object_property_add_link(obj, "idau", TYPE_IDAU_INTERFACE, &cpu->idau, 845 qdev_prop_allow_set_link_before_realize, 846 OBJ_PROP_LINK_STRONG, 847 &error_abort); 848 qdev_property_add_static(DEVICE(obj), &arm_cpu_initsvtor_property, 849 &error_abort); 850 } 851 852 qdev_property_add_static(DEVICE(obj), &arm_cpu_cfgend_property, 853 &error_abort); 854 } 855 856 static void arm_cpu_finalizefn(Object *obj) 857 { 858 ARMCPU *cpu = ARM_CPU(obj); 859 ARMELChangeHook *hook, *next; 860 861 g_hash_table_destroy(cpu->cp_regs); 862 863 QLIST_FOREACH_SAFE(hook, &cpu->pre_el_change_hooks, node, next) { 864 QLIST_REMOVE(hook, node); 865 g_free(hook); 866 } 867 QLIST_FOREACH_SAFE(hook, &cpu->el_change_hooks, node, next) { 868 QLIST_REMOVE(hook, node); 869 g_free(hook); 870 } 871 #ifndef CONFIG_USER_ONLY 872 if (cpu->pmu_timer) { 873 timer_del(cpu->pmu_timer); 874 timer_deinit(cpu->pmu_timer); 875 timer_free(cpu->pmu_timer); 876 } 877 #endif 878 } 879 880 static void arm_cpu_realizefn(DeviceState *dev, Error **errp) 881 { 882 CPUState *cs = CPU(dev); 883 ARMCPU *cpu = ARM_CPU(dev); 884 ARMCPUClass *acc = ARM_CPU_GET_CLASS(dev); 885 CPUARMState *env = &cpu->env; 886 int pagebits; 887 Error *local_err = NULL; 888 bool no_aa32 = false; 889 890 /* If we needed to query the host kernel for the CPU features 891 * then it's possible that might have failed in the initfn, but 892 * this is the first point where we can report it. 893 */ 894 if (cpu->host_cpu_probe_failed) { 895 if (!kvm_enabled()) { 896 error_setg(errp, "The 'host' CPU type can only be used with KVM"); 897 } else { 898 error_setg(errp, "Failed to retrieve host CPU features"); 899 } 900 return; 901 } 902 903 #ifndef CONFIG_USER_ONLY 904 /* The NVIC and M-profile CPU are two halves of a single piece of 905 * hardware; trying to use one without the other is a command line 906 * error and will result in segfaults if not caught here. 907 */ 908 if (arm_feature(env, ARM_FEATURE_M)) { 909 if (!env->nvic) { 910 error_setg(errp, "This board cannot be used with Cortex-M CPUs"); 911 return; 912 } 913 } else { 914 if (env->nvic) { 915 error_setg(errp, "This board can only be used with Cortex-M CPUs"); 916 return; 917 } 918 } 919 920 cpu->gt_timer[GTIMER_PHYS] = timer_new(QEMU_CLOCK_VIRTUAL, GTIMER_SCALE, 921 arm_gt_ptimer_cb, cpu); 922 cpu->gt_timer[GTIMER_VIRT] = timer_new(QEMU_CLOCK_VIRTUAL, GTIMER_SCALE, 923 arm_gt_vtimer_cb, cpu); 924 cpu->gt_timer[GTIMER_HYP] = timer_new(QEMU_CLOCK_VIRTUAL, GTIMER_SCALE, 925 arm_gt_htimer_cb, cpu); 926 cpu->gt_timer[GTIMER_SEC] = timer_new(QEMU_CLOCK_VIRTUAL, GTIMER_SCALE, 927 arm_gt_stimer_cb, cpu); 928 #endif 929 930 cpu_exec_realizefn(cs, &local_err); 931 if (local_err != NULL) { 932 error_propagate(errp, local_err); 933 return; 934 } 935 936 /* Some features automatically imply others: */ 937 if (arm_feature(env, ARM_FEATURE_V8)) { 938 if (arm_feature(env, ARM_FEATURE_M)) { 939 set_feature(env, ARM_FEATURE_V7); 940 } else { 941 set_feature(env, ARM_FEATURE_V7VE); 942 } 943 } 944 945 /* 946 * There exist AArch64 cpus without AArch32 support. When KVM 947 * queries ID_ISAR0_EL1 on such a host, the value is UNKNOWN. 948 * Similarly, we cannot check ID_AA64PFR0 without AArch64 support. 949 */ 950 if (arm_feature(&cpu->env, ARM_FEATURE_AARCH64)) { 951 no_aa32 = !cpu_isar_feature(aa64_aa32, cpu); 952 } 953 954 if (arm_feature(env, ARM_FEATURE_V7VE)) { 955 /* v7 Virtualization Extensions. In real hardware this implies 956 * EL2 and also the presence of the Security Extensions. 957 * For QEMU, for backwards-compatibility we implement some 958 * CPUs or CPU configs which have no actual EL2 or EL3 but do 959 * include the various other features that V7VE implies. 960 * Presence of EL2 itself is ARM_FEATURE_EL2, and of the 961 * Security Extensions is ARM_FEATURE_EL3. 962 */ 963 assert(no_aa32 || cpu_isar_feature(arm_div, cpu)); 964 set_feature(env, ARM_FEATURE_LPAE); 965 set_feature(env, ARM_FEATURE_V7); 966 } 967 if (arm_feature(env, ARM_FEATURE_V7)) { 968 set_feature(env, ARM_FEATURE_VAPA); 969 set_feature(env, ARM_FEATURE_THUMB2); 970 set_feature(env, ARM_FEATURE_MPIDR); 971 if (!arm_feature(env, ARM_FEATURE_M)) { 972 set_feature(env, ARM_FEATURE_V6K); 973 } else { 974 set_feature(env, ARM_FEATURE_V6); 975 } 976 977 /* Always define VBAR for V7 CPUs even if it doesn't exist in 978 * non-EL3 configs. This is needed by some legacy boards. 979 */ 980 set_feature(env, ARM_FEATURE_VBAR); 981 } 982 if (arm_feature(env, ARM_FEATURE_V6K)) { 983 set_feature(env, ARM_FEATURE_V6); 984 set_feature(env, ARM_FEATURE_MVFR); 985 } 986 if (arm_feature(env, ARM_FEATURE_V6)) { 987 set_feature(env, ARM_FEATURE_V5); 988 if (!arm_feature(env, ARM_FEATURE_M)) { 989 assert(no_aa32 || cpu_isar_feature(jazelle, cpu)); 990 set_feature(env, ARM_FEATURE_AUXCR); 991 } 992 } 993 if (arm_feature(env, ARM_FEATURE_V5)) { 994 set_feature(env, ARM_FEATURE_V4T); 995 } 996 if (arm_feature(env, ARM_FEATURE_VFP4)) { 997 set_feature(env, ARM_FEATURE_VFP3); 998 set_feature(env, ARM_FEATURE_VFP_FP16); 999 } 1000 if (arm_feature(env, ARM_FEATURE_VFP3)) { 1001 set_feature(env, ARM_FEATURE_VFP); 1002 } 1003 if (arm_feature(env, ARM_FEATURE_LPAE)) { 1004 set_feature(env, ARM_FEATURE_V7MP); 1005 set_feature(env, ARM_FEATURE_PXN); 1006 } 1007 if (arm_feature(env, ARM_FEATURE_CBAR_RO)) { 1008 set_feature(env, ARM_FEATURE_CBAR); 1009 } 1010 if (arm_feature(env, ARM_FEATURE_THUMB2) && 1011 !arm_feature(env, ARM_FEATURE_M)) { 1012 set_feature(env, ARM_FEATURE_THUMB_DSP); 1013 } 1014 1015 if (arm_feature(env, ARM_FEATURE_V7) && 1016 !arm_feature(env, ARM_FEATURE_M) && 1017 !arm_feature(env, ARM_FEATURE_PMSA)) { 1018 /* v7VMSA drops support for the old ARMv5 tiny pages, so we 1019 * can use 4K pages. 1020 */ 1021 pagebits = 12; 1022 } else { 1023 /* For CPUs which might have tiny 1K pages, or which have an 1024 * MPU and might have small region sizes, stick with 1K pages. 1025 */ 1026 pagebits = 10; 1027 } 1028 if (!set_preferred_target_page_bits(pagebits)) { 1029 /* This can only ever happen for hotplugging a CPU, or if 1030 * the board code incorrectly creates a CPU which it has 1031 * promised via minimum_page_size that it will not. 1032 */ 1033 error_setg(errp, "This CPU requires a smaller page size than the " 1034 "system is using"); 1035 return; 1036 } 1037 1038 /* This cpu-id-to-MPIDR affinity is used only for TCG; KVM will override it. 1039 * We don't support setting cluster ID ([16..23]) (known as Aff2 1040 * in later ARM ARM versions), or any of the higher affinity level fields, 1041 * so these bits always RAZ. 1042 */ 1043 if (cpu->mp_affinity == ARM64_AFFINITY_INVALID) { 1044 cpu->mp_affinity = arm_cpu_mp_affinity(cs->cpu_index, 1045 ARM_DEFAULT_CPUS_PER_CLUSTER); 1046 } 1047 1048 if (cpu->reset_hivecs) { 1049 cpu->reset_sctlr |= (1 << 13); 1050 } 1051 1052 if (cpu->cfgend) { 1053 if (arm_feature(&cpu->env, ARM_FEATURE_V7)) { 1054 cpu->reset_sctlr |= SCTLR_EE; 1055 } else { 1056 cpu->reset_sctlr |= SCTLR_B; 1057 } 1058 } 1059 1060 if (!cpu->has_el3) { 1061 /* If the has_el3 CPU property is disabled then we need to disable the 1062 * feature. 1063 */ 1064 unset_feature(env, ARM_FEATURE_EL3); 1065 1066 /* Disable the security extension feature bits in the processor feature 1067 * registers as well. These are id_pfr1[7:4] and id_aa64pfr0[15:12]. 1068 */ 1069 cpu->id_pfr1 &= ~0xf0; 1070 cpu->isar.id_aa64pfr0 &= ~0xf000; 1071 } 1072 1073 if (!cpu->has_el2) { 1074 unset_feature(env, ARM_FEATURE_EL2); 1075 } 1076 1077 if (!cpu->has_pmu) { 1078 unset_feature(env, ARM_FEATURE_PMU); 1079 } 1080 if (arm_feature(env, ARM_FEATURE_PMU)) { 1081 pmu_init(cpu); 1082 1083 if (!kvm_enabled()) { 1084 arm_register_pre_el_change_hook(cpu, &pmu_pre_el_change, 0); 1085 arm_register_el_change_hook(cpu, &pmu_post_el_change, 0); 1086 } 1087 1088 #ifndef CONFIG_USER_ONLY 1089 cpu->pmu_timer = timer_new_ns(QEMU_CLOCK_VIRTUAL, arm_pmu_timer_cb, 1090 cpu); 1091 #endif 1092 } else { 1093 cpu->id_aa64dfr0 &= ~0xf00; 1094 cpu->pmceid0 = 0; 1095 cpu->pmceid1 = 0; 1096 } 1097 1098 if (!arm_feature(env, ARM_FEATURE_EL2)) { 1099 /* Disable the hypervisor feature bits in the processor feature 1100 * registers if we don't have EL2. These are id_pfr1[15:12] and 1101 * id_aa64pfr0_el1[11:8]. 1102 */ 1103 cpu->isar.id_aa64pfr0 &= ~0xf00; 1104 cpu->id_pfr1 &= ~0xf000; 1105 } 1106 1107 /* MPU can be configured out of a PMSA CPU either by setting has-mpu 1108 * to false or by setting pmsav7-dregion to 0. 1109 */ 1110 if (!cpu->has_mpu) { 1111 cpu->pmsav7_dregion = 0; 1112 } 1113 if (cpu->pmsav7_dregion == 0) { 1114 cpu->has_mpu = false; 1115 } 1116 1117 if (arm_feature(env, ARM_FEATURE_PMSA) && 1118 arm_feature(env, ARM_FEATURE_V7)) { 1119 uint32_t nr = cpu->pmsav7_dregion; 1120 1121 if (nr > 0xff) { 1122 error_setg(errp, "PMSAv7 MPU #regions invalid %" PRIu32, nr); 1123 return; 1124 } 1125 1126 if (nr) { 1127 if (arm_feature(env, ARM_FEATURE_V8)) { 1128 /* PMSAv8 */ 1129 env->pmsav8.rbar[M_REG_NS] = g_new0(uint32_t, nr); 1130 env->pmsav8.rlar[M_REG_NS] = g_new0(uint32_t, nr); 1131 if (arm_feature(env, ARM_FEATURE_M_SECURITY)) { 1132 env->pmsav8.rbar[M_REG_S] = g_new0(uint32_t, nr); 1133 env->pmsav8.rlar[M_REG_S] = g_new0(uint32_t, nr); 1134 } 1135 } else { 1136 env->pmsav7.drbar = g_new0(uint32_t, nr); 1137 env->pmsav7.drsr = g_new0(uint32_t, nr); 1138 env->pmsav7.dracr = g_new0(uint32_t, nr); 1139 } 1140 } 1141 } 1142 1143 if (arm_feature(env, ARM_FEATURE_M_SECURITY)) { 1144 uint32_t nr = cpu->sau_sregion; 1145 1146 if (nr > 0xff) { 1147 error_setg(errp, "v8M SAU #regions invalid %" PRIu32, nr); 1148 return; 1149 } 1150 1151 if (nr) { 1152 env->sau.rbar = g_new0(uint32_t, nr); 1153 env->sau.rlar = g_new0(uint32_t, nr); 1154 } 1155 } 1156 1157 if (arm_feature(env, ARM_FEATURE_EL3)) { 1158 set_feature(env, ARM_FEATURE_VBAR); 1159 } 1160 1161 register_cp_regs_for_features(cpu); 1162 arm_cpu_register_gdb_regs_for_features(cpu); 1163 1164 init_cpreg_list(cpu); 1165 1166 #ifndef CONFIG_USER_ONLY 1167 if (cpu->has_el3 || arm_feature(env, ARM_FEATURE_M_SECURITY)) { 1168 cs->num_ases = 2; 1169 1170 if (!cpu->secure_memory) { 1171 cpu->secure_memory = cs->memory; 1172 } 1173 cpu_address_space_init(cs, ARMASIdx_S, "cpu-secure-memory", 1174 cpu->secure_memory); 1175 } else { 1176 cs->num_ases = 1; 1177 } 1178 cpu_address_space_init(cs, ARMASIdx_NS, "cpu-memory", cs->memory); 1179 1180 /* No core_count specified, default to smp_cpus. */ 1181 if (cpu->core_count == -1) { 1182 cpu->core_count = smp_cpus; 1183 } 1184 #endif 1185 1186 qemu_init_vcpu(cs); 1187 cpu_reset(cs); 1188 1189 acc->parent_realize(dev, errp); 1190 } 1191 1192 static ObjectClass *arm_cpu_class_by_name(const char *cpu_model) 1193 { 1194 ObjectClass *oc; 1195 char *typename; 1196 char **cpuname; 1197 const char *cpunamestr; 1198 1199 cpuname = g_strsplit(cpu_model, ",", 1); 1200 cpunamestr = cpuname[0]; 1201 #ifdef CONFIG_USER_ONLY 1202 /* For backwards compatibility usermode emulation allows "-cpu any", 1203 * which has the same semantics as "-cpu max". 1204 */ 1205 if (!strcmp(cpunamestr, "any")) { 1206 cpunamestr = "max"; 1207 } 1208 #endif 1209 typename = g_strdup_printf(ARM_CPU_TYPE_NAME("%s"), cpunamestr); 1210 oc = object_class_by_name(typename); 1211 g_strfreev(cpuname); 1212 g_free(typename); 1213 if (!oc || !object_class_dynamic_cast(oc, TYPE_ARM_CPU) || 1214 object_class_is_abstract(oc)) { 1215 return NULL; 1216 } 1217 return oc; 1218 } 1219 1220 /* CPU models. These are not needed for the AArch64 linux-user build. */ 1221 #if !defined(CONFIG_USER_ONLY) || !defined(TARGET_AARCH64) 1222 1223 static void arm926_initfn(Object *obj) 1224 { 1225 ARMCPU *cpu = ARM_CPU(obj); 1226 1227 cpu->dtb_compatible = "arm,arm926"; 1228 set_feature(&cpu->env, ARM_FEATURE_V5); 1229 set_feature(&cpu->env, ARM_FEATURE_VFP); 1230 set_feature(&cpu->env, ARM_FEATURE_DUMMY_C15_REGS); 1231 set_feature(&cpu->env, ARM_FEATURE_CACHE_TEST_CLEAN); 1232 cpu->midr = 0x41069265; 1233 cpu->reset_fpsid = 0x41011090; 1234 cpu->ctr = 0x1dd20d2; 1235 cpu->reset_sctlr = 0x00090078; 1236 1237 /* 1238 * ARMv5 does not have the ID_ISAR registers, but we can still 1239 * set the field to indicate Jazelle support within QEMU. 1240 */ 1241 cpu->isar.id_isar1 = FIELD_DP32(cpu->isar.id_isar1, ID_ISAR1, JAZELLE, 1); 1242 } 1243 1244 static void arm946_initfn(Object *obj) 1245 { 1246 ARMCPU *cpu = ARM_CPU(obj); 1247 1248 cpu->dtb_compatible = "arm,arm946"; 1249 set_feature(&cpu->env, ARM_FEATURE_V5); 1250 set_feature(&cpu->env, ARM_FEATURE_PMSA); 1251 set_feature(&cpu->env, ARM_FEATURE_DUMMY_C15_REGS); 1252 cpu->midr = 0x41059461; 1253 cpu->ctr = 0x0f004006; 1254 cpu->reset_sctlr = 0x00000078; 1255 } 1256 1257 static void arm1026_initfn(Object *obj) 1258 { 1259 ARMCPU *cpu = ARM_CPU(obj); 1260 1261 cpu->dtb_compatible = "arm,arm1026"; 1262 set_feature(&cpu->env, ARM_FEATURE_V5); 1263 set_feature(&cpu->env, ARM_FEATURE_VFP); 1264 set_feature(&cpu->env, ARM_FEATURE_AUXCR); 1265 set_feature(&cpu->env, ARM_FEATURE_DUMMY_C15_REGS); 1266 set_feature(&cpu->env, ARM_FEATURE_CACHE_TEST_CLEAN); 1267 cpu->midr = 0x4106a262; 1268 cpu->reset_fpsid = 0x410110a0; 1269 cpu->ctr = 0x1dd20d2; 1270 cpu->reset_sctlr = 0x00090078; 1271 cpu->reset_auxcr = 1; 1272 1273 /* 1274 * ARMv5 does not have the ID_ISAR registers, but we can still 1275 * set the field to indicate Jazelle support within QEMU. 1276 */ 1277 cpu->isar.id_isar1 = FIELD_DP32(cpu->isar.id_isar1, ID_ISAR1, JAZELLE, 1); 1278 1279 { 1280 /* The 1026 had an IFAR at c6,c0,0,1 rather than the ARMv6 c6,c0,0,2 */ 1281 ARMCPRegInfo ifar = { 1282 .name = "IFAR", .cp = 15, .crn = 6, .crm = 0, .opc1 = 0, .opc2 = 1, 1283 .access = PL1_RW, 1284 .fieldoffset = offsetof(CPUARMState, cp15.ifar_ns), 1285 .resetvalue = 0 1286 }; 1287 define_one_arm_cp_reg(cpu, &ifar); 1288 } 1289 } 1290 1291 static void arm1136_r2_initfn(Object *obj) 1292 { 1293 ARMCPU *cpu = ARM_CPU(obj); 1294 /* What qemu calls "arm1136_r2" is actually the 1136 r0p2, ie an 1295 * older core than plain "arm1136". In particular this does not 1296 * have the v6K features. 1297 * These ID register values are correct for 1136 but may be wrong 1298 * for 1136_r2 (in particular r0p2 does not actually implement most 1299 * of the ID registers). 1300 */ 1301 1302 cpu->dtb_compatible = "arm,arm1136"; 1303 set_feature(&cpu->env, ARM_FEATURE_V6); 1304 set_feature(&cpu->env, ARM_FEATURE_VFP); 1305 set_feature(&cpu->env, ARM_FEATURE_DUMMY_C15_REGS); 1306 set_feature(&cpu->env, ARM_FEATURE_CACHE_DIRTY_REG); 1307 set_feature(&cpu->env, ARM_FEATURE_CACHE_BLOCK_OPS); 1308 cpu->midr = 0x4107b362; 1309 cpu->reset_fpsid = 0x410120b4; 1310 cpu->isar.mvfr0 = 0x11111111; 1311 cpu->isar.mvfr1 = 0x00000000; 1312 cpu->ctr = 0x1dd20d2; 1313 cpu->reset_sctlr = 0x00050078; 1314 cpu->id_pfr0 = 0x111; 1315 cpu->id_pfr1 = 0x1; 1316 cpu->id_dfr0 = 0x2; 1317 cpu->id_afr0 = 0x3; 1318 cpu->id_mmfr0 = 0x01130003; 1319 cpu->id_mmfr1 = 0x10030302; 1320 cpu->id_mmfr2 = 0x01222110; 1321 cpu->isar.id_isar0 = 0x00140011; 1322 cpu->isar.id_isar1 = 0x12002111; 1323 cpu->isar.id_isar2 = 0x11231111; 1324 cpu->isar.id_isar3 = 0x01102131; 1325 cpu->isar.id_isar4 = 0x141; 1326 cpu->reset_auxcr = 7; 1327 } 1328 1329 static void arm1136_initfn(Object *obj) 1330 { 1331 ARMCPU *cpu = ARM_CPU(obj); 1332 1333 cpu->dtb_compatible = "arm,arm1136"; 1334 set_feature(&cpu->env, ARM_FEATURE_V6K); 1335 set_feature(&cpu->env, ARM_FEATURE_V6); 1336 set_feature(&cpu->env, ARM_FEATURE_VFP); 1337 set_feature(&cpu->env, ARM_FEATURE_DUMMY_C15_REGS); 1338 set_feature(&cpu->env, ARM_FEATURE_CACHE_DIRTY_REG); 1339 set_feature(&cpu->env, ARM_FEATURE_CACHE_BLOCK_OPS); 1340 cpu->midr = 0x4117b363; 1341 cpu->reset_fpsid = 0x410120b4; 1342 cpu->isar.mvfr0 = 0x11111111; 1343 cpu->isar.mvfr1 = 0x00000000; 1344 cpu->ctr = 0x1dd20d2; 1345 cpu->reset_sctlr = 0x00050078; 1346 cpu->id_pfr0 = 0x111; 1347 cpu->id_pfr1 = 0x1; 1348 cpu->id_dfr0 = 0x2; 1349 cpu->id_afr0 = 0x3; 1350 cpu->id_mmfr0 = 0x01130003; 1351 cpu->id_mmfr1 = 0x10030302; 1352 cpu->id_mmfr2 = 0x01222110; 1353 cpu->isar.id_isar0 = 0x00140011; 1354 cpu->isar.id_isar1 = 0x12002111; 1355 cpu->isar.id_isar2 = 0x11231111; 1356 cpu->isar.id_isar3 = 0x01102131; 1357 cpu->isar.id_isar4 = 0x141; 1358 cpu->reset_auxcr = 7; 1359 } 1360 1361 static void arm1176_initfn(Object *obj) 1362 { 1363 ARMCPU *cpu = ARM_CPU(obj); 1364 1365 cpu->dtb_compatible = "arm,arm1176"; 1366 set_feature(&cpu->env, ARM_FEATURE_V6K); 1367 set_feature(&cpu->env, ARM_FEATURE_VFP); 1368 set_feature(&cpu->env, ARM_FEATURE_VAPA); 1369 set_feature(&cpu->env, ARM_FEATURE_DUMMY_C15_REGS); 1370 set_feature(&cpu->env, ARM_FEATURE_CACHE_DIRTY_REG); 1371 set_feature(&cpu->env, ARM_FEATURE_CACHE_BLOCK_OPS); 1372 set_feature(&cpu->env, ARM_FEATURE_EL3); 1373 cpu->midr = 0x410fb767; 1374 cpu->reset_fpsid = 0x410120b5; 1375 cpu->isar.mvfr0 = 0x11111111; 1376 cpu->isar.mvfr1 = 0x00000000; 1377 cpu->ctr = 0x1dd20d2; 1378 cpu->reset_sctlr = 0x00050078; 1379 cpu->id_pfr0 = 0x111; 1380 cpu->id_pfr1 = 0x11; 1381 cpu->id_dfr0 = 0x33; 1382 cpu->id_afr0 = 0; 1383 cpu->id_mmfr0 = 0x01130003; 1384 cpu->id_mmfr1 = 0x10030302; 1385 cpu->id_mmfr2 = 0x01222100; 1386 cpu->isar.id_isar0 = 0x0140011; 1387 cpu->isar.id_isar1 = 0x12002111; 1388 cpu->isar.id_isar2 = 0x11231121; 1389 cpu->isar.id_isar3 = 0x01102131; 1390 cpu->isar.id_isar4 = 0x01141; 1391 cpu->reset_auxcr = 7; 1392 } 1393 1394 static void arm11mpcore_initfn(Object *obj) 1395 { 1396 ARMCPU *cpu = ARM_CPU(obj); 1397 1398 cpu->dtb_compatible = "arm,arm11mpcore"; 1399 set_feature(&cpu->env, ARM_FEATURE_V6K); 1400 set_feature(&cpu->env, ARM_FEATURE_VFP); 1401 set_feature(&cpu->env, ARM_FEATURE_VAPA); 1402 set_feature(&cpu->env, ARM_FEATURE_MPIDR); 1403 set_feature(&cpu->env, ARM_FEATURE_DUMMY_C15_REGS); 1404 cpu->midr = 0x410fb022; 1405 cpu->reset_fpsid = 0x410120b4; 1406 cpu->isar.mvfr0 = 0x11111111; 1407 cpu->isar.mvfr1 = 0x00000000; 1408 cpu->ctr = 0x1d192992; /* 32K icache 32K dcache */ 1409 cpu->id_pfr0 = 0x111; 1410 cpu->id_pfr1 = 0x1; 1411 cpu->id_dfr0 = 0; 1412 cpu->id_afr0 = 0x2; 1413 cpu->id_mmfr0 = 0x01100103; 1414 cpu->id_mmfr1 = 0x10020302; 1415 cpu->id_mmfr2 = 0x01222000; 1416 cpu->isar.id_isar0 = 0x00100011; 1417 cpu->isar.id_isar1 = 0x12002111; 1418 cpu->isar.id_isar2 = 0x11221011; 1419 cpu->isar.id_isar3 = 0x01102131; 1420 cpu->isar.id_isar4 = 0x141; 1421 cpu->reset_auxcr = 1; 1422 } 1423 1424 static void cortex_m0_initfn(Object *obj) 1425 { 1426 ARMCPU *cpu = ARM_CPU(obj); 1427 set_feature(&cpu->env, ARM_FEATURE_V6); 1428 set_feature(&cpu->env, ARM_FEATURE_M); 1429 1430 cpu->midr = 0x410cc200; 1431 } 1432 1433 static void cortex_m3_initfn(Object *obj) 1434 { 1435 ARMCPU *cpu = ARM_CPU(obj); 1436 set_feature(&cpu->env, ARM_FEATURE_V7); 1437 set_feature(&cpu->env, ARM_FEATURE_M); 1438 set_feature(&cpu->env, ARM_FEATURE_M_MAIN); 1439 cpu->midr = 0x410fc231; 1440 cpu->pmsav7_dregion = 8; 1441 cpu->id_pfr0 = 0x00000030; 1442 cpu->id_pfr1 = 0x00000200; 1443 cpu->id_dfr0 = 0x00100000; 1444 cpu->id_afr0 = 0x00000000; 1445 cpu->id_mmfr0 = 0x00000030; 1446 cpu->id_mmfr1 = 0x00000000; 1447 cpu->id_mmfr2 = 0x00000000; 1448 cpu->id_mmfr3 = 0x00000000; 1449 cpu->isar.id_isar0 = 0x01141110; 1450 cpu->isar.id_isar1 = 0x02111000; 1451 cpu->isar.id_isar2 = 0x21112231; 1452 cpu->isar.id_isar3 = 0x01111110; 1453 cpu->isar.id_isar4 = 0x01310102; 1454 cpu->isar.id_isar5 = 0x00000000; 1455 cpu->isar.id_isar6 = 0x00000000; 1456 } 1457 1458 static void cortex_m4_initfn(Object *obj) 1459 { 1460 ARMCPU *cpu = ARM_CPU(obj); 1461 1462 set_feature(&cpu->env, ARM_FEATURE_V7); 1463 set_feature(&cpu->env, ARM_FEATURE_M); 1464 set_feature(&cpu->env, ARM_FEATURE_M_MAIN); 1465 set_feature(&cpu->env, ARM_FEATURE_THUMB_DSP); 1466 cpu->midr = 0x410fc240; /* r0p0 */ 1467 cpu->pmsav7_dregion = 8; 1468 cpu->id_pfr0 = 0x00000030; 1469 cpu->id_pfr1 = 0x00000200; 1470 cpu->id_dfr0 = 0x00100000; 1471 cpu->id_afr0 = 0x00000000; 1472 cpu->id_mmfr0 = 0x00000030; 1473 cpu->id_mmfr1 = 0x00000000; 1474 cpu->id_mmfr2 = 0x00000000; 1475 cpu->id_mmfr3 = 0x00000000; 1476 cpu->isar.id_isar0 = 0x01141110; 1477 cpu->isar.id_isar1 = 0x02111000; 1478 cpu->isar.id_isar2 = 0x21112231; 1479 cpu->isar.id_isar3 = 0x01111110; 1480 cpu->isar.id_isar4 = 0x01310102; 1481 cpu->isar.id_isar5 = 0x00000000; 1482 cpu->isar.id_isar6 = 0x00000000; 1483 } 1484 1485 static void cortex_m33_initfn(Object *obj) 1486 { 1487 ARMCPU *cpu = ARM_CPU(obj); 1488 1489 set_feature(&cpu->env, ARM_FEATURE_V8); 1490 set_feature(&cpu->env, ARM_FEATURE_M); 1491 set_feature(&cpu->env, ARM_FEATURE_M_MAIN); 1492 set_feature(&cpu->env, ARM_FEATURE_M_SECURITY); 1493 set_feature(&cpu->env, ARM_FEATURE_THUMB_DSP); 1494 cpu->midr = 0x410fd213; /* r0p3 */ 1495 cpu->pmsav7_dregion = 16; 1496 cpu->sau_sregion = 8; 1497 cpu->id_pfr0 = 0x00000030; 1498 cpu->id_pfr1 = 0x00000210; 1499 cpu->id_dfr0 = 0x00200000; 1500 cpu->id_afr0 = 0x00000000; 1501 cpu->id_mmfr0 = 0x00101F40; 1502 cpu->id_mmfr1 = 0x00000000; 1503 cpu->id_mmfr2 = 0x01000000; 1504 cpu->id_mmfr3 = 0x00000000; 1505 cpu->isar.id_isar0 = 0x01101110; 1506 cpu->isar.id_isar1 = 0x02212000; 1507 cpu->isar.id_isar2 = 0x20232232; 1508 cpu->isar.id_isar3 = 0x01111131; 1509 cpu->isar.id_isar4 = 0x01310132; 1510 cpu->isar.id_isar5 = 0x00000000; 1511 cpu->isar.id_isar6 = 0x00000000; 1512 cpu->clidr = 0x00000000; 1513 cpu->ctr = 0x8000c000; 1514 } 1515 1516 static void arm_v7m_class_init(ObjectClass *oc, void *data) 1517 { 1518 ARMCPUClass *acc = ARM_CPU_CLASS(oc); 1519 CPUClass *cc = CPU_CLASS(oc); 1520 1521 acc->info = data; 1522 #ifndef CONFIG_USER_ONLY 1523 cc->do_interrupt = arm_v7m_cpu_do_interrupt; 1524 #endif 1525 1526 cc->cpu_exec_interrupt = arm_v7m_cpu_exec_interrupt; 1527 } 1528 1529 static const ARMCPRegInfo cortexr5_cp_reginfo[] = { 1530 /* Dummy the TCM region regs for the moment */ 1531 { .name = "ATCM", .cp = 15, .opc1 = 0, .crn = 9, .crm = 1, .opc2 = 0, 1532 .access = PL1_RW, .type = ARM_CP_CONST }, 1533 { .name = "BTCM", .cp = 15, .opc1 = 0, .crn = 9, .crm = 1, .opc2 = 1, 1534 .access = PL1_RW, .type = ARM_CP_CONST }, 1535 { .name = "DCACHE_INVAL", .cp = 15, .opc1 = 0, .crn = 15, .crm = 5, 1536 .opc2 = 0, .access = PL1_W, .type = ARM_CP_NOP }, 1537 REGINFO_SENTINEL 1538 }; 1539 1540 static void cortex_r5_initfn(Object *obj) 1541 { 1542 ARMCPU *cpu = ARM_CPU(obj); 1543 1544 set_feature(&cpu->env, ARM_FEATURE_V7); 1545 set_feature(&cpu->env, ARM_FEATURE_V7MP); 1546 set_feature(&cpu->env, ARM_FEATURE_PMSA); 1547 cpu->midr = 0x411fc153; /* r1p3 */ 1548 cpu->id_pfr0 = 0x0131; 1549 cpu->id_pfr1 = 0x001; 1550 cpu->id_dfr0 = 0x010400; 1551 cpu->id_afr0 = 0x0; 1552 cpu->id_mmfr0 = 0x0210030; 1553 cpu->id_mmfr1 = 0x00000000; 1554 cpu->id_mmfr2 = 0x01200000; 1555 cpu->id_mmfr3 = 0x0211; 1556 cpu->isar.id_isar0 = 0x02101111; 1557 cpu->isar.id_isar1 = 0x13112111; 1558 cpu->isar.id_isar2 = 0x21232141; 1559 cpu->isar.id_isar3 = 0x01112131; 1560 cpu->isar.id_isar4 = 0x0010142; 1561 cpu->isar.id_isar5 = 0x0; 1562 cpu->isar.id_isar6 = 0x0; 1563 cpu->mp_is_up = true; 1564 cpu->pmsav7_dregion = 16; 1565 define_arm_cp_regs(cpu, cortexr5_cp_reginfo); 1566 } 1567 1568 static void cortex_r5f_initfn(Object *obj) 1569 { 1570 ARMCPU *cpu = ARM_CPU(obj); 1571 1572 cortex_r5_initfn(obj); 1573 set_feature(&cpu->env, ARM_FEATURE_VFP3); 1574 } 1575 1576 static const ARMCPRegInfo cortexa8_cp_reginfo[] = { 1577 { .name = "L2LOCKDOWN", .cp = 15, .crn = 9, .crm = 0, .opc1 = 1, .opc2 = 0, 1578 .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0 }, 1579 { .name = "L2AUXCR", .cp = 15, .crn = 9, .crm = 0, .opc1 = 1, .opc2 = 2, 1580 .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0 }, 1581 REGINFO_SENTINEL 1582 }; 1583 1584 static void cortex_a8_initfn(Object *obj) 1585 { 1586 ARMCPU *cpu = ARM_CPU(obj); 1587 1588 cpu->dtb_compatible = "arm,cortex-a8"; 1589 set_feature(&cpu->env, ARM_FEATURE_V7); 1590 set_feature(&cpu->env, ARM_FEATURE_VFP3); 1591 set_feature(&cpu->env, ARM_FEATURE_NEON); 1592 set_feature(&cpu->env, ARM_FEATURE_THUMB2EE); 1593 set_feature(&cpu->env, ARM_FEATURE_DUMMY_C15_REGS); 1594 set_feature(&cpu->env, ARM_FEATURE_EL3); 1595 cpu->midr = 0x410fc080; 1596 cpu->reset_fpsid = 0x410330c0; 1597 cpu->isar.mvfr0 = 0x11110222; 1598 cpu->isar.mvfr1 = 0x00011111; 1599 cpu->ctr = 0x82048004; 1600 cpu->reset_sctlr = 0x00c50078; 1601 cpu->id_pfr0 = 0x1031; 1602 cpu->id_pfr1 = 0x11; 1603 cpu->id_dfr0 = 0x400; 1604 cpu->id_afr0 = 0; 1605 cpu->id_mmfr0 = 0x31100003; 1606 cpu->id_mmfr1 = 0x20000000; 1607 cpu->id_mmfr2 = 0x01202000; 1608 cpu->id_mmfr3 = 0x11; 1609 cpu->isar.id_isar0 = 0x00101111; 1610 cpu->isar.id_isar1 = 0x12112111; 1611 cpu->isar.id_isar2 = 0x21232031; 1612 cpu->isar.id_isar3 = 0x11112131; 1613 cpu->isar.id_isar4 = 0x00111142; 1614 cpu->dbgdidr = 0x15141000; 1615 cpu->clidr = (1 << 27) | (2 << 24) | 3; 1616 cpu->ccsidr[0] = 0xe007e01a; /* 16k L1 dcache. */ 1617 cpu->ccsidr[1] = 0x2007e01a; /* 16k L1 icache. */ 1618 cpu->ccsidr[2] = 0xf0000000; /* No L2 icache. */ 1619 cpu->reset_auxcr = 2; 1620 define_arm_cp_regs(cpu, cortexa8_cp_reginfo); 1621 } 1622 1623 static const ARMCPRegInfo cortexa9_cp_reginfo[] = { 1624 /* power_control should be set to maximum latency. Again, 1625 * default to 0 and set by private hook 1626 */ 1627 { .name = "A9_PWRCTL", .cp = 15, .crn = 15, .crm = 0, .opc1 = 0, .opc2 = 0, 1628 .access = PL1_RW, .resetvalue = 0, 1629 .fieldoffset = offsetof(CPUARMState, cp15.c15_power_control) }, 1630 { .name = "A9_DIAG", .cp = 15, .crn = 15, .crm = 0, .opc1 = 0, .opc2 = 1, 1631 .access = PL1_RW, .resetvalue = 0, 1632 .fieldoffset = offsetof(CPUARMState, cp15.c15_diagnostic) }, 1633 { .name = "A9_PWRDIAG", .cp = 15, .crn = 15, .crm = 0, .opc1 = 0, .opc2 = 2, 1634 .access = PL1_RW, .resetvalue = 0, 1635 .fieldoffset = offsetof(CPUARMState, cp15.c15_power_diagnostic) }, 1636 { .name = "NEONBUSY", .cp = 15, .crn = 15, .crm = 1, .opc1 = 0, .opc2 = 0, 1637 .access = PL1_RW, .resetvalue = 0, .type = ARM_CP_CONST }, 1638 /* TLB lockdown control */ 1639 { .name = "TLB_LOCKR", .cp = 15, .crn = 15, .crm = 4, .opc1 = 5, .opc2 = 2, 1640 .access = PL1_W, .resetvalue = 0, .type = ARM_CP_NOP }, 1641 { .name = "TLB_LOCKW", .cp = 15, .crn = 15, .crm = 4, .opc1 = 5, .opc2 = 4, 1642 .access = PL1_W, .resetvalue = 0, .type = ARM_CP_NOP }, 1643 { .name = "TLB_VA", .cp = 15, .crn = 15, .crm = 5, .opc1 = 5, .opc2 = 2, 1644 .access = PL1_RW, .resetvalue = 0, .type = ARM_CP_CONST }, 1645 { .name = "TLB_PA", .cp = 15, .crn = 15, .crm = 6, .opc1 = 5, .opc2 = 2, 1646 .access = PL1_RW, .resetvalue = 0, .type = ARM_CP_CONST }, 1647 { .name = "TLB_ATTR", .cp = 15, .crn = 15, .crm = 7, .opc1 = 5, .opc2 = 2, 1648 .access = PL1_RW, .resetvalue = 0, .type = ARM_CP_CONST }, 1649 REGINFO_SENTINEL 1650 }; 1651 1652 static void cortex_a9_initfn(Object *obj) 1653 { 1654 ARMCPU *cpu = ARM_CPU(obj); 1655 1656 cpu->dtb_compatible = "arm,cortex-a9"; 1657 set_feature(&cpu->env, ARM_FEATURE_V7); 1658 set_feature(&cpu->env, ARM_FEATURE_VFP3); 1659 set_feature(&cpu->env, ARM_FEATURE_VFP_FP16); 1660 set_feature(&cpu->env, ARM_FEATURE_NEON); 1661 set_feature(&cpu->env, ARM_FEATURE_THUMB2EE); 1662 set_feature(&cpu->env, ARM_FEATURE_EL3); 1663 /* Note that A9 supports the MP extensions even for 1664 * A9UP and single-core A9MP (which are both different 1665 * and valid configurations; we don't model A9UP). 1666 */ 1667 set_feature(&cpu->env, ARM_FEATURE_V7MP); 1668 set_feature(&cpu->env, ARM_FEATURE_CBAR); 1669 cpu->midr = 0x410fc090; 1670 cpu->reset_fpsid = 0x41033090; 1671 cpu->isar.mvfr0 = 0x11110222; 1672 cpu->isar.mvfr1 = 0x01111111; 1673 cpu->ctr = 0x80038003; 1674 cpu->reset_sctlr = 0x00c50078; 1675 cpu->id_pfr0 = 0x1031; 1676 cpu->id_pfr1 = 0x11; 1677 cpu->id_dfr0 = 0x000; 1678 cpu->id_afr0 = 0; 1679 cpu->id_mmfr0 = 0x00100103; 1680 cpu->id_mmfr1 = 0x20000000; 1681 cpu->id_mmfr2 = 0x01230000; 1682 cpu->id_mmfr3 = 0x00002111; 1683 cpu->isar.id_isar0 = 0x00101111; 1684 cpu->isar.id_isar1 = 0x13112111; 1685 cpu->isar.id_isar2 = 0x21232041; 1686 cpu->isar.id_isar3 = 0x11112131; 1687 cpu->isar.id_isar4 = 0x00111142; 1688 cpu->dbgdidr = 0x35141000; 1689 cpu->clidr = (1 << 27) | (1 << 24) | 3; 1690 cpu->ccsidr[0] = 0xe00fe019; /* 16k L1 dcache. */ 1691 cpu->ccsidr[1] = 0x200fe019; /* 16k L1 icache. */ 1692 define_arm_cp_regs(cpu, cortexa9_cp_reginfo); 1693 } 1694 1695 #ifndef CONFIG_USER_ONLY 1696 static uint64_t a15_l2ctlr_read(CPUARMState *env, const ARMCPRegInfo *ri) 1697 { 1698 /* Linux wants the number of processors from here. 1699 * Might as well set the interrupt-controller bit too. 1700 */ 1701 return ((smp_cpus - 1) << 24) | (1 << 23); 1702 } 1703 #endif 1704 1705 static const ARMCPRegInfo cortexa15_cp_reginfo[] = { 1706 #ifndef CONFIG_USER_ONLY 1707 { .name = "L2CTLR", .cp = 15, .crn = 9, .crm = 0, .opc1 = 1, .opc2 = 2, 1708 .access = PL1_RW, .resetvalue = 0, .readfn = a15_l2ctlr_read, 1709 .writefn = arm_cp_write_ignore, }, 1710 #endif 1711 { .name = "L2ECTLR", .cp = 15, .crn = 9, .crm = 0, .opc1 = 1, .opc2 = 3, 1712 .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0 }, 1713 REGINFO_SENTINEL 1714 }; 1715 1716 static void cortex_a7_initfn(Object *obj) 1717 { 1718 ARMCPU *cpu = ARM_CPU(obj); 1719 1720 cpu->dtb_compatible = "arm,cortex-a7"; 1721 set_feature(&cpu->env, ARM_FEATURE_V7VE); 1722 set_feature(&cpu->env, ARM_FEATURE_VFP4); 1723 set_feature(&cpu->env, ARM_FEATURE_NEON); 1724 set_feature(&cpu->env, ARM_FEATURE_THUMB2EE); 1725 set_feature(&cpu->env, ARM_FEATURE_GENERIC_TIMER); 1726 set_feature(&cpu->env, ARM_FEATURE_DUMMY_C15_REGS); 1727 set_feature(&cpu->env, ARM_FEATURE_CBAR_RO); 1728 set_feature(&cpu->env, ARM_FEATURE_EL2); 1729 set_feature(&cpu->env, ARM_FEATURE_EL3); 1730 cpu->kvm_target = QEMU_KVM_ARM_TARGET_CORTEX_A7; 1731 cpu->midr = 0x410fc075; 1732 cpu->reset_fpsid = 0x41023075; 1733 cpu->isar.mvfr0 = 0x10110222; 1734 cpu->isar.mvfr1 = 0x11111111; 1735 cpu->ctr = 0x84448003; 1736 cpu->reset_sctlr = 0x00c50078; 1737 cpu->id_pfr0 = 0x00001131; 1738 cpu->id_pfr1 = 0x00011011; 1739 cpu->id_dfr0 = 0x02010555; 1740 cpu->id_afr0 = 0x00000000; 1741 cpu->id_mmfr0 = 0x10101105; 1742 cpu->id_mmfr1 = 0x40000000; 1743 cpu->id_mmfr2 = 0x01240000; 1744 cpu->id_mmfr3 = 0x02102211; 1745 /* a7_mpcore_r0p5_trm, page 4-4 gives 0x01101110; but 1746 * table 4-41 gives 0x02101110, which includes the arm div insns. 1747 */ 1748 cpu->isar.id_isar0 = 0x02101110; 1749 cpu->isar.id_isar1 = 0x13112111; 1750 cpu->isar.id_isar2 = 0x21232041; 1751 cpu->isar.id_isar3 = 0x11112131; 1752 cpu->isar.id_isar4 = 0x10011142; 1753 cpu->dbgdidr = 0x3515f005; 1754 cpu->clidr = 0x0a200023; 1755 cpu->ccsidr[0] = 0x701fe00a; /* 32K L1 dcache */ 1756 cpu->ccsidr[1] = 0x201fe00a; /* 32K L1 icache */ 1757 cpu->ccsidr[2] = 0x711fe07a; /* 4096K L2 unified cache */ 1758 define_arm_cp_regs(cpu, cortexa15_cp_reginfo); /* Same as A15 */ 1759 } 1760 1761 static void cortex_a15_initfn(Object *obj) 1762 { 1763 ARMCPU *cpu = ARM_CPU(obj); 1764 1765 cpu->dtb_compatible = "arm,cortex-a15"; 1766 set_feature(&cpu->env, ARM_FEATURE_V7VE); 1767 set_feature(&cpu->env, ARM_FEATURE_VFP4); 1768 set_feature(&cpu->env, ARM_FEATURE_NEON); 1769 set_feature(&cpu->env, ARM_FEATURE_THUMB2EE); 1770 set_feature(&cpu->env, ARM_FEATURE_GENERIC_TIMER); 1771 set_feature(&cpu->env, ARM_FEATURE_DUMMY_C15_REGS); 1772 set_feature(&cpu->env, ARM_FEATURE_CBAR_RO); 1773 set_feature(&cpu->env, ARM_FEATURE_EL2); 1774 set_feature(&cpu->env, ARM_FEATURE_EL3); 1775 cpu->kvm_target = QEMU_KVM_ARM_TARGET_CORTEX_A15; 1776 cpu->midr = 0x412fc0f1; 1777 cpu->reset_fpsid = 0x410430f0; 1778 cpu->isar.mvfr0 = 0x10110222; 1779 cpu->isar.mvfr1 = 0x11111111; 1780 cpu->ctr = 0x8444c004; 1781 cpu->reset_sctlr = 0x00c50078; 1782 cpu->id_pfr0 = 0x00001131; 1783 cpu->id_pfr1 = 0x00011011; 1784 cpu->id_dfr0 = 0x02010555; 1785 cpu->id_afr0 = 0x00000000; 1786 cpu->id_mmfr0 = 0x10201105; 1787 cpu->id_mmfr1 = 0x20000000; 1788 cpu->id_mmfr2 = 0x01240000; 1789 cpu->id_mmfr3 = 0x02102211; 1790 cpu->isar.id_isar0 = 0x02101110; 1791 cpu->isar.id_isar1 = 0x13112111; 1792 cpu->isar.id_isar2 = 0x21232041; 1793 cpu->isar.id_isar3 = 0x11112131; 1794 cpu->isar.id_isar4 = 0x10011142; 1795 cpu->dbgdidr = 0x3515f021; 1796 cpu->clidr = 0x0a200023; 1797 cpu->ccsidr[0] = 0x701fe00a; /* 32K L1 dcache */ 1798 cpu->ccsidr[1] = 0x201fe00a; /* 32K L1 icache */ 1799 cpu->ccsidr[2] = 0x711fe07a; /* 4096K L2 unified cache */ 1800 define_arm_cp_regs(cpu, cortexa15_cp_reginfo); 1801 } 1802 1803 static void ti925t_initfn(Object *obj) 1804 { 1805 ARMCPU *cpu = ARM_CPU(obj); 1806 set_feature(&cpu->env, ARM_FEATURE_V4T); 1807 set_feature(&cpu->env, ARM_FEATURE_OMAPCP); 1808 cpu->midr = ARM_CPUID_TI925T; 1809 cpu->ctr = 0x5109149; 1810 cpu->reset_sctlr = 0x00000070; 1811 } 1812 1813 static void sa1100_initfn(Object *obj) 1814 { 1815 ARMCPU *cpu = ARM_CPU(obj); 1816 1817 cpu->dtb_compatible = "intel,sa1100"; 1818 set_feature(&cpu->env, ARM_FEATURE_STRONGARM); 1819 set_feature(&cpu->env, ARM_FEATURE_DUMMY_C15_REGS); 1820 cpu->midr = 0x4401A11B; 1821 cpu->reset_sctlr = 0x00000070; 1822 } 1823 1824 static void sa1110_initfn(Object *obj) 1825 { 1826 ARMCPU *cpu = ARM_CPU(obj); 1827 set_feature(&cpu->env, ARM_FEATURE_STRONGARM); 1828 set_feature(&cpu->env, ARM_FEATURE_DUMMY_C15_REGS); 1829 cpu->midr = 0x6901B119; 1830 cpu->reset_sctlr = 0x00000070; 1831 } 1832 1833 static void pxa250_initfn(Object *obj) 1834 { 1835 ARMCPU *cpu = ARM_CPU(obj); 1836 1837 cpu->dtb_compatible = "marvell,xscale"; 1838 set_feature(&cpu->env, ARM_FEATURE_V5); 1839 set_feature(&cpu->env, ARM_FEATURE_XSCALE); 1840 cpu->midr = 0x69052100; 1841 cpu->ctr = 0xd172172; 1842 cpu->reset_sctlr = 0x00000078; 1843 } 1844 1845 static void pxa255_initfn(Object *obj) 1846 { 1847 ARMCPU *cpu = ARM_CPU(obj); 1848 1849 cpu->dtb_compatible = "marvell,xscale"; 1850 set_feature(&cpu->env, ARM_FEATURE_V5); 1851 set_feature(&cpu->env, ARM_FEATURE_XSCALE); 1852 cpu->midr = 0x69052d00; 1853 cpu->ctr = 0xd172172; 1854 cpu->reset_sctlr = 0x00000078; 1855 } 1856 1857 static void pxa260_initfn(Object *obj) 1858 { 1859 ARMCPU *cpu = ARM_CPU(obj); 1860 1861 cpu->dtb_compatible = "marvell,xscale"; 1862 set_feature(&cpu->env, ARM_FEATURE_V5); 1863 set_feature(&cpu->env, ARM_FEATURE_XSCALE); 1864 cpu->midr = 0x69052903; 1865 cpu->ctr = 0xd172172; 1866 cpu->reset_sctlr = 0x00000078; 1867 } 1868 1869 static void pxa261_initfn(Object *obj) 1870 { 1871 ARMCPU *cpu = ARM_CPU(obj); 1872 1873 cpu->dtb_compatible = "marvell,xscale"; 1874 set_feature(&cpu->env, ARM_FEATURE_V5); 1875 set_feature(&cpu->env, ARM_FEATURE_XSCALE); 1876 cpu->midr = 0x69052d05; 1877 cpu->ctr = 0xd172172; 1878 cpu->reset_sctlr = 0x00000078; 1879 } 1880 1881 static void pxa262_initfn(Object *obj) 1882 { 1883 ARMCPU *cpu = ARM_CPU(obj); 1884 1885 cpu->dtb_compatible = "marvell,xscale"; 1886 set_feature(&cpu->env, ARM_FEATURE_V5); 1887 set_feature(&cpu->env, ARM_FEATURE_XSCALE); 1888 cpu->midr = 0x69052d06; 1889 cpu->ctr = 0xd172172; 1890 cpu->reset_sctlr = 0x00000078; 1891 } 1892 1893 static void pxa270a0_initfn(Object *obj) 1894 { 1895 ARMCPU *cpu = ARM_CPU(obj); 1896 1897 cpu->dtb_compatible = "marvell,xscale"; 1898 set_feature(&cpu->env, ARM_FEATURE_V5); 1899 set_feature(&cpu->env, ARM_FEATURE_XSCALE); 1900 set_feature(&cpu->env, ARM_FEATURE_IWMMXT); 1901 cpu->midr = 0x69054110; 1902 cpu->ctr = 0xd172172; 1903 cpu->reset_sctlr = 0x00000078; 1904 } 1905 1906 static void pxa270a1_initfn(Object *obj) 1907 { 1908 ARMCPU *cpu = ARM_CPU(obj); 1909 1910 cpu->dtb_compatible = "marvell,xscale"; 1911 set_feature(&cpu->env, ARM_FEATURE_V5); 1912 set_feature(&cpu->env, ARM_FEATURE_XSCALE); 1913 set_feature(&cpu->env, ARM_FEATURE_IWMMXT); 1914 cpu->midr = 0x69054111; 1915 cpu->ctr = 0xd172172; 1916 cpu->reset_sctlr = 0x00000078; 1917 } 1918 1919 static void pxa270b0_initfn(Object *obj) 1920 { 1921 ARMCPU *cpu = ARM_CPU(obj); 1922 1923 cpu->dtb_compatible = "marvell,xscale"; 1924 set_feature(&cpu->env, ARM_FEATURE_V5); 1925 set_feature(&cpu->env, ARM_FEATURE_XSCALE); 1926 set_feature(&cpu->env, ARM_FEATURE_IWMMXT); 1927 cpu->midr = 0x69054112; 1928 cpu->ctr = 0xd172172; 1929 cpu->reset_sctlr = 0x00000078; 1930 } 1931 1932 static void pxa270b1_initfn(Object *obj) 1933 { 1934 ARMCPU *cpu = ARM_CPU(obj); 1935 1936 cpu->dtb_compatible = "marvell,xscale"; 1937 set_feature(&cpu->env, ARM_FEATURE_V5); 1938 set_feature(&cpu->env, ARM_FEATURE_XSCALE); 1939 set_feature(&cpu->env, ARM_FEATURE_IWMMXT); 1940 cpu->midr = 0x69054113; 1941 cpu->ctr = 0xd172172; 1942 cpu->reset_sctlr = 0x00000078; 1943 } 1944 1945 static void pxa270c0_initfn(Object *obj) 1946 { 1947 ARMCPU *cpu = ARM_CPU(obj); 1948 1949 cpu->dtb_compatible = "marvell,xscale"; 1950 set_feature(&cpu->env, ARM_FEATURE_V5); 1951 set_feature(&cpu->env, ARM_FEATURE_XSCALE); 1952 set_feature(&cpu->env, ARM_FEATURE_IWMMXT); 1953 cpu->midr = 0x69054114; 1954 cpu->ctr = 0xd172172; 1955 cpu->reset_sctlr = 0x00000078; 1956 } 1957 1958 static void pxa270c5_initfn(Object *obj) 1959 { 1960 ARMCPU *cpu = ARM_CPU(obj); 1961 1962 cpu->dtb_compatible = "marvell,xscale"; 1963 set_feature(&cpu->env, ARM_FEATURE_V5); 1964 set_feature(&cpu->env, ARM_FEATURE_XSCALE); 1965 set_feature(&cpu->env, ARM_FEATURE_IWMMXT); 1966 cpu->midr = 0x69054117; 1967 cpu->ctr = 0xd172172; 1968 cpu->reset_sctlr = 0x00000078; 1969 } 1970 1971 #ifndef TARGET_AARCH64 1972 /* -cpu max: if KVM is enabled, like -cpu host (best possible with this host); 1973 * otherwise, a CPU with as many features enabled as our emulation supports. 1974 * The version of '-cpu max' for qemu-system-aarch64 is defined in cpu64.c; 1975 * this only needs to handle 32 bits. 1976 */ 1977 static void arm_max_initfn(Object *obj) 1978 { 1979 ARMCPU *cpu = ARM_CPU(obj); 1980 1981 if (kvm_enabled()) { 1982 kvm_arm_set_cpu_features_from_host(cpu); 1983 } else { 1984 cortex_a15_initfn(obj); 1985 #ifdef CONFIG_USER_ONLY 1986 /* We don't set these in system emulation mode for the moment, 1987 * since we don't correctly set (all of) the ID registers to 1988 * advertise them. 1989 */ 1990 set_feature(&cpu->env, ARM_FEATURE_V8); 1991 { 1992 uint32_t t; 1993 1994 t = cpu->isar.id_isar5; 1995 t = FIELD_DP32(t, ID_ISAR5, AES, 2); 1996 t = FIELD_DP32(t, ID_ISAR5, SHA1, 1); 1997 t = FIELD_DP32(t, ID_ISAR5, SHA2, 1); 1998 t = FIELD_DP32(t, ID_ISAR5, CRC32, 1); 1999 t = FIELD_DP32(t, ID_ISAR5, RDM, 1); 2000 t = FIELD_DP32(t, ID_ISAR5, VCMA, 1); 2001 cpu->isar.id_isar5 = t; 2002 2003 t = cpu->isar.id_isar6; 2004 t = FIELD_DP32(t, ID_ISAR6, DP, 1); 2005 cpu->isar.id_isar6 = t; 2006 2007 t = cpu->id_mmfr4; 2008 t = FIELD_DP32(t, ID_MMFR4, HPDS, 1); /* AA32HPD */ 2009 cpu->id_mmfr4 = t; 2010 } 2011 #endif 2012 } 2013 } 2014 #endif 2015 2016 #endif /* !defined(CONFIG_USER_ONLY) || !defined(TARGET_AARCH64) */ 2017 2018 struct ARMCPUInfo { 2019 const char *name; 2020 void (*initfn)(Object *obj); 2021 void (*class_init)(ObjectClass *oc, void *data); 2022 }; 2023 2024 static const ARMCPUInfo arm_cpus[] = { 2025 #if !defined(CONFIG_USER_ONLY) || !defined(TARGET_AARCH64) 2026 { .name = "arm926", .initfn = arm926_initfn }, 2027 { .name = "arm946", .initfn = arm946_initfn }, 2028 { .name = "arm1026", .initfn = arm1026_initfn }, 2029 /* What QEMU calls "arm1136-r2" is actually the 1136 r0p2, i.e. an 2030 * older core than plain "arm1136". In particular this does not 2031 * have the v6K features. 2032 */ 2033 { .name = "arm1136-r2", .initfn = arm1136_r2_initfn }, 2034 { .name = "arm1136", .initfn = arm1136_initfn }, 2035 { .name = "arm1176", .initfn = arm1176_initfn }, 2036 { .name = "arm11mpcore", .initfn = arm11mpcore_initfn }, 2037 { .name = "cortex-m0", .initfn = cortex_m0_initfn, 2038 .class_init = arm_v7m_class_init }, 2039 { .name = "cortex-m3", .initfn = cortex_m3_initfn, 2040 .class_init = arm_v7m_class_init }, 2041 { .name = "cortex-m4", .initfn = cortex_m4_initfn, 2042 .class_init = arm_v7m_class_init }, 2043 { .name = "cortex-m33", .initfn = cortex_m33_initfn, 2044 .class_init = arm_v7m_class_init }, 2045 { .name = "cortex-r5", .initfn = cortex_r5_initfn }, 2046 { .name = "cortex-r5f", .initfn = cortex_r5f_initfn }, 2047 { .name = "cortex-a7", .initfn = cortex_a7_initfn }, 2048 { .name = "cortex-a8", .initfn = cortex_a8_initfn }, 2049 { .name = "cortex-a9", .initfn = cortex_a9_initfn }, 2050 { .name = "cortex-a15", .initfn = cortex_a15_initfn }, 2051 { .name = "ti925t", .initfn = ti925t_initfn }, 2052 { .name = "sa1100", .initfn = sa1100_initfn }, 2053 { .name = "sa1110", .initfn = sa1110_initfn }, 2054 { .name = "pxa250", .initfn = pxa250_initfn }, 2055 { .name = "pxa255", .initfn = pxa255_initfn }, 2056 { .name = "pxa260", .initfn = pxa260_initfn }, 2057 { .name = "pxa261", .initfn = pxa261_initfn }, 2058 { .name = "pxa262", .initfn = pxa262_initfn }, 2059 /* "pxa270" is an alias for "pxa270-a0" */ 2060 { .name = "pxa270", .initfn = pxa270a0_initfn }, 2061 { .name = "pxa270-a0", .initfn = pxa270a0_initfn }, 2062 { .name = "pxa270-a1", .initfn = pxa270a1_initfn }, 2063 { .name = "pxa270-b0", .initfn = pxa270b0_initfn }, 2064 { .name = "pxa270-b1", .initfn = pxa270b1_initfn }, 2065 { .name = "pxa270-c0", .initfn = pxa270c0_initfn }, 2066 { .name = "pxa270-c5", .initfn = pxa270c5_initfn }, 2067 #ifndef TARGET_AARCH64 2068 { .name = "max", .initfn = arm_max_initfn }, 2069 #endif 2070 #ifdef CONFIG_USER_ONLY 2071 { .name = "any", .initfn = arm_max_initfn }, 2072 #endif 2073 #endif 2074 { .name = NULL } 2075 }; 2076 2077 static Property arm_cpu_properties[] = { 2078 DEFINE_PROP_BOOL("start-powered-off", ARMCPU, start_powered_off, false), 2079 DEFINE_PROP_UINT32("psci-conduit", ARMCPU, psci_conduit, 0), 2080 DEFINE_PROP_UINT32("midr", ARMCPU, midr, 0), 2081 DEFINE_PROP_UINT64("mp-affinity", ARMCPU, 2082 mp_affinity, ARM64_AFFINITY_INVALID), 2083 DEFINE_PROP_INT32("node-id", ARMCPU, node_id, CPU_UNSET_NUMA_NODE_ID), 2084 DEFINE_PROP_INT32("core-count", ARMCPU, core_count, -1), 2085 DEFINE_PROP_END_OF_LIST() 2086 }; 2087 2088 #ifdef CONFIG_USER_ONLY 2089 static int arm_cpu_handle_mmu_fault(CPUState *cs, vaddr address, int size, 2090 int rw, int mmu_idx) 2091 { 2092 ARMCPU *cpu = ARM_CPU(cs); 2093 CPUARMState *env = &cpu->env; 2094 2095 env->exception.vaddress = address; 2096 if (rw == 2) { 2097 cs->exception_index = EXCP_PREFETCH_ABORT; 2098 } else { 2099 cs->exception_index = EXCP_DATA_ABORT; 2100 } 2101 return 1; 2102 } 2103 #endif 2104 2105 static gchar *arm_gdb_arch_name(CPUState *cs) 2106 { 2107 ARMCPU *cpu = ARM_CPU(cs); 2108 CPUARMState *env = &cpu->env; 2109 2110 if (arm_feature(env, ARM_FEATURE_IWMMXT)) { 2111 return g_strdup("iwmmxt"); 2112 } 2113 return g_strdup("arm"); 2114 } 2115 2116 static void arm_cpu_class_init(ObjectClass *oc, void *data) 2117 { 2118 ARMCPUClass *acc = ARM_CPU_CLASS(oc); 2119 CPUClass *cc = CPU_CLASS(acc); 2120 DeviceClass *dc = DEVICE_CLASS(oc); 2121 2122 device_class_set_parent_realize(dc, arm_cpu_realizefn, 2123 &acc->parent_realize); 2124 dc->props = arm_cpu_properties; 2125 2126 acc->parent_reset = cc->reset; 2127 cc->reset = arm_cpu_reset; 2128 2129 cc->class_by_name = arm_cpu_class_by_name; 2130 cc->has_work = arm_cpu_has_work; 2131 cc->cpu_exec_interrupt = arm_cpu_exec_interrupt; 2132 cc->dump_state = arm_cpu_dump_state; 2133 cc->set_pc = arm_cpu_set_pc; 2134 cc->synchronize_from_tb = arm_cpu_synchronize_from_tb; 2135 cc->gdb_read_register = arm_cpu_gdb_read_register; 2136 cc->gdb_write_register = arm_cpu_gdb_write_register; 2137 #ifdef CONFIG_USER_ONLY 2138 cc->handle_mmu_fault = arm_cpu_handle_mmu_fault; 2139 #else 2140 cc->do_interrupt = arm_cpu_do_interrupt; 2141 cc->do_unaligned_access = arm_cpu_do_unaligned_access; 2142 cc->do_transaction_failed = arm_cpu_do_transaction_failed; 2143 cc->get_phys_page_attrs_debug = arm_cpu_get_phys_page_attrs_debug; 2144 cc->asidx_from_attrs = arm_asidx_from_attrs; 2145 cc->vmsd = &vmstate_arm_cpu; 2146 cc->virtio_is_big_endian = arm_cpu_virtio_is_big_endian; 2147 cc->write_elf64_note = arm_cpu_write_elf64_note; 2148 cc->write_elf32_note = arm_cpu_write_elf32_note; 2149 #endif 2150 cc->gdb_num_core_regs = 26; 2151 cc->gdb_core_xml_file = "arm-core.xml"; 2152 cc->gdb_arch_name = arm_gdb_arch_name; 2153 cc->gdb_get_dynamic_xml = arm_gdb_get_dynamic_xml; 2154 cc->gdb_stop_before_watchpoint = true; 2155 cc->debug_excp_handler = arm_debug_excp_handler; 2156 cc->debug_check_watchpoint = arm_debug_check_watchpoint; 2157 #if !defined(CONFIG_USER_ONLY) 2158 cc->adjust_watchpoint_address = arm_adjust_watchpoint_address; 2159 #endif 2160 2161 cc->disas_set_info = arm_disas_set_info; 2162 #ifdef CONFIG_TCG 2163 cc->tcg_initialize = arm_translate_init; 2164 #endif 2165 } 2166 2167 #ifdef CONFIG_KVM 2168 static void arm_host_initfn(Object *obj) 2169 { 2170 ARMCPU *cpu = ARM_CPU(obj); 2171 2172 kvm_arm_set_cpu_features_from_host(cpu); 2173 arm_cpu_post_init(obj); 2174 } 2175 2176 static const TypeInfo host_arm_cpu_type_info = { 2177 .name = TYPE_ARM_HOST_CPU, 2178 #ifdef TARGET_AARCH64 2179 .parent = TYPE_AARCH64_CPU, 2180 #else 2181 .parent = TYPE_ARM_CPU, 2182 #endif 2183 .instance_init = arm_host_initfn, 2184 }; 2185 2186 #endif 2187 2188 static void arm_cpu_instance_init(Object *obj) 2189 { 2190 ARMCPUClass *acc = ARM_CPU_GET_CLASS(obj); 2191 2192 acc->info->initfn(obj); 2193 arm_cpu_post_init(obj); 2194 } 2195 2196 static void cpu_register_class_init(ObjectClass *oc, void *data) 2197 { 2198 ARMCPUClass *acc = ARM_CPU_CLASS(oc); 2199 2200 acc->info = data; 2201 } 2202 2203 static void cpu_register(const ARMCPUInfo *info) 2204 { 2205 TypeInfo type_info = { 2206 .parent = TYPE_ARM_CPU, 2207 .instance_size = sizeof(ARMCPU), 2208 .instance_init = arm_cpu_instance_init, 2209 .class_size = sizeof(ARMCPUClass), 2210 .class_init = info->class_init ?: cpu_register_class_init, 2211 .class_data = (void *)info, 2212 }; 2213 2214 type_info.name = g_strdup_printf("%s-" TYPE_ARM_CPU, info->name); 2215 type_register(&type_info); 2216 g_free((void *)type_info.name); 2217 } 2218 2219 static const TypeInfo arm_cpu_type_info = { 2220 .name = TYPE_ARM_CPU, 2221 .parent = TYPE_CPU, 2222 .instance_size = sizeof(ARMCPU), 2223 .instance_init = arm_cpu_initfn, 2224 .instance_finalize = arm_cpu_finalizefn, 2225 .abstract = true, 2226 .class_size = sizeof(ARMCPUClass), 2227 .class_init = arm_cpu_class_init, 2228 }; 2229 2230 static const TypeInfo idau_interface_type_info = { 2231 .name = TYPE_IDAU_INTERFACE, 2232 .parent = TYPE_INTERFACE, 2233 .class_size = sizeof(IDAUInterfaceClass), 2234 }; 2235 2236 static void arm_cpu_register_types(void) 2237 { 2238 const ARMCPUInfo *info = arm_cpus; 2239 2240 type_register_static(&arm_cpu_type_info); 2241 type_register_static(&idau_interface_type_info); 2242 2243 while (info->name) { 2244 cpu_register(info); 2245 info++; 2246 } 2247 2248 #ifdef CONFIG_KVM 2249 type_register_static(&host_arm_cpu_type_info); 2250 #endif 2251 } 2252 2253 type_init(arm_cpu_register_types) 2254