1 /* 2 * QEMU ARM CPU 3 * 4 * Copyright (c) 2012 SUSE LINUX Products GmbH 5 * 6 * This program is free software; you can redistribute it and/or 7 * modify it under the terms of the GNU General Public License 8 * as published by the Free Software Foundation; either version 2 9 * of the License, or (at your option) any later version. 10 * 11 * This program is distributed in the hope that it will be useful, 12 * but WITHOUT ANY WARRANTY; without even the implied warranty of 13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 14 * GNU General Public License for more details. 15 * 16 * You should have received a copy of the GNU General Public License 17 * along with this program; if not, see 18 * <http://www.gnu.org/licenses/gpl-2.0.html> 19 */ 20 21 #include "qemu/osdep.h" 22 #include "qemu/qemu-print.h" 23 #include "qemu-common.h" 24 #include "target/arm/idau.h" 25 #include "qemu/module.h" 26 #include "qapi/error.h" 27 #include "qapi/visitor.h" 28 #include "cpu.h" 29 #include "internals.h" 30 #include "exec/exec-all.h" 31 #include "hw/qdev-properties.h" 32 #if !defined(CONFIG_USER_ONLY) 33 #include "hw/loader.h" 34 #include "hw/boards.h" 35 #endif 36 #include "sysemu/sysemu.h" 37 #include "sysemu/tcg.h" 38 #include "sysemu/hw_accel.h" 39 #include "kvm_arm.h" 40 #include "disas/capstone.h" 41 #include "fpu/softfloat.h" 42 43 static void arm_cpu_set_pc(CPUState *cs, vaddr value) 44 { 45 ARMCPU *cpu = ARM_CPU(cs); 46 CPUARMState *env = &cpu->env; 47 48 if (is_a64(env)) { 49 env->pc = value; 50 env->thumb = 0; 51 } else { 52 env->regs[15] = value & ~1; 53 env->thumb = value & 1; 54 } 55 } 56 57 static void arm_cpu_synchronize_from_tb(CPUState *cs, TranslationBlock *tb) 58 { 59 ARMCPU *cpu = ARM_CPU(cs); 60 CPUARMState *env = &cpu->env; 61 62 /* 63 * It's OK to look at env for the current mode here, because it's 64 * never possible for an AArch64 TB to chain to an AArch32 TB. 65 */ 66 if (is_a64(env)) { 67 env->pc = tb->pc; 68 } else { 69 env->regs[15] = tb->pc; 70 } 71 } 72 73 static bool arm_cpu_has_work(CPUState *cs) 74 { 75 ARMCPU *cpu = ARM_CPU(cs); 76 77 return (cpu->power_state != PSCI_OFF) 78 && cs->interrupt_request & 79 (CPU_INTERRUPT_FIQ | CPU_INTERRUPT_HARD 80 | CPU_INTERRUPT_VFIQ | CPU_INTERRUPT_VIRQ 81 | CPU_INTERRUPT_EXITTB); 82 } 83 84 void arm_register_pre_el_change_hook(ARMCPU *cpu, ARMELChangeHookFn *hook, 85 void *opaque) 86 { 87 ARMELChangeHook *entry = g_new0(ARMELChangeHook, 1); 88 89 entry->hook = hook; 90 entry->opaque = opaque; 91 92 QLIST_INSERT_HEAD(&cpu->pre_el_change_hooks, entry, node); 93 } 94 95 void arm_register_el_change_hook(ARMCPU *cpu, ARMELChangeHookFn *hook, 96 void *opaque) 97 { 98 ARMELChangeHook *entry = g_new0(ARMELChangeHook, 1); 99 100 entry->hook = hook; 101 entry->opaque = opaque; 102 103 QLIST_INSERT_HEAD(&cpu->el_change_hooks, entry, node); 104 } 105 106 static void cp_reg_reset(gpointer key, gpointer value, gpointer opaque) 107 { 108 /* Reset a single ARMCPRegInfo register */ 109 ARMCPRegInfo *ri = value; 110 ARMCPU *cpu = opaque; 111 112 if (ri->type & (ARM_CP_SPECIAL | ARM_CP_ALIAS)) { 113 return; 114 } 115 116 if (ri->resetfn) { 117 ri->resetfn(&cpu->env, ri); 118 return; 119 } 120 121 /* A zero offset is never possible as it would be regs[0] 122 * so we use it to indicate that reset is being handled elsewhere. 123 * This is basically only used for fields in non-core coprocessors 124 * (like the pxa2xx ones). 125 */ 126 if (!ri->fieldoffset) { 127 return; 128 } 129 130 if (cpreg_field_is_64bit(ri)) { 131 CPREG_FIELD64(&cpu->env, ri) = ri->resetvalue; 132 } else { 133 CPREG_FIELD32(&cpu->env, ri) = ri->resetvalue; 134 } 135 } 136 137 static void cp_reg_check_reset(gpointer key, gpointer value, gpointer opaque) 138 { 139 /* Purely an assertion check: we've already done reset once, 140 * so now check that running the reset for the cpreg doesn't 141 * change its value. This traps bugs where two different cpregs 142 * both try to reset the same state field but to different values. 143 */ 144 ARMCPRegInfo *ri = value; 145 ARMCPU *cpu = opaque; 146 uint64_t oldvalue, newvalue; 147 148 if (ri->type & (ARM_CP_SPECIAL | ARM_CP_ALIAS | ARM_CP_NO_RAW)) { 149 return; 150 } 151 152 oldvalue = read_raw_cp_reg(&cpu->env, ri); 153 cp_reg_reset(key, value, opaque); 154 newvalue = read_raw_cp_reg(&cpu->env, ri); 155 assert(oldvalue == newvalue); 156 } 157 158 /* CPUClass::reset() */ 159 static void arm_cpu_reset(CPUState *s) 160 { 161 ARMCPU *cpu = ARM_CPU(s); 162 ARMCPUClass *acc = ARM_CPU_GET_CLASS(cpu); 163 CPUARMState *env = &cpu->env; 164 165 acc->parent_reset(s); 166 167 memset(env, 0, offsetof(CPUARMState, end_reset_fields)); 168 169 g_hash_table_foreach(cpu->cp_regs, cp_reg_reset, cpu); 170 g_hash_table_foreach(cpu->cp_regs, cp_reg_check_reset, cpu); 171 172 env->vfp.xregs[ARM_VFP_FPSID] = cpu->reset_fpsid; 173 env->vfp.xregs[ARM_VFP_MVFR0] = cpu->isar.mvfr0; 174 env->vfp.xregs[ARM_VFP_MVFR1] = cpu->isar.mvfr1; 175 env->vfp.xregs[ARM_VFP_MVFR2] = cpu->isar.mvfr2; 176 177 cpu->power_state = cpu->start_powered_off ? PSCI_OFF : PSCI_ON; 178 s->halted = cpu->start_powered_off; 179 180 if (arm_feature(env, ARM_FEATURE_IWMMXT)) { 181 env->iwmmxt.cregs[ARM_IWMMXT_wCID] = 0x69051000 | 'Q'; 182 } 183 184 if (arm_feature(env, ARM_FEATURE_AARCH64)) { 185 /* 64 bit CPUs always start in 64 bit mode */ 186 env->aarch64 = 1; 187 #if defined(CONFIG_USER_ONLY) 188 env->pstate = PSTATE_MODE_EL0t; 189 /* Userspace expects access to DC ZVA, CTL_EL0 and the cache ops */ 190 env->cp15.sctlr_el[1] |= SCTLR_UCT | SCTLR_UCI | SCTLR_DZE; 191 /* Enable all PAC keys. */ 192 env->cp15.sctlr_el[1] |= (SCTLR_EnIA | SCTLR_EnIB | 193 SCTLR_EnDA | SCTLR_EnDB); 194 /* Enable all PAC instructions */ 195 env->cp15.hcr_el2 |= HCR_API; 196 env->cp15.scr_el3 |= SCR_API; 197 /* and to the FP/Neon instructions */ 198 env->cp15.cpacr_el1 = deposit64(env->cp15.cpacr_el1, 20, 2, 3); 199 /* and to the SVE instructions */ 200 env->cp15.cpacr_el1 = deposit64(env->cp15.cpacr_el1, 16, 2, 3); 201 env->cp15.cptr_el[3] |= CPTR_EZ; 202 /* with maximum vector length */ 203 env->vfp.zcr_el[1] = cpu->sve_max_vq - 1; 204 env->vfp.zcr_el[2] = env->vfp.zcr_el[1]; 205 env->vfp.zcr_el[3] = env->vfp.zcr_el[1]; 206 /* 207 * Enable TBI0 and TBI1. While the real kernel only enables TBI0, 208 * turning on both here will produce smaller code and otherwise 209 * make no difference to the user-level emulation. 210 */ 211 env->cp15.tcr_el[1].raw_tcr = (3ULL << 37); 212 #else 213 /* Reset into the highest available EL */ 214 if (arm_feature(env, ARM_FEATURE_EL3)) { 215 env->pstate = PSTATE_MODE_EL3h; 216 } else if (arm_feature(env, ARM_FEATURE_EL2)) { 217 env->pstate = PSTATE_MODE_EL2h; 218 } else { 219 env->pstate = PSTATE_MODE_EL1h; 220 } 221 env->pc = cpu->rvbar; 222 #endif 223 } else { 224 #if defined(CONFIG_USER_ONLY) 225 /* Userspace expects access to cp10 and cp11 for FP/Neon */ 226 env->cp15.cpacr_el1 = deposit64(env->cp15.cpacr_el1, 20, 4, 0xf); 227 #endif 228 } 229 230 #if defined(CONFIG_USER_ONLY) 231 env->uncached_cpsr = ARM_CPU_MODE_USR; 232 /* For user mode we must enable access to coprocessors */ 233 env->vfp.xregs[ARM_VFP_FPEXC] = 1 << 30; 234 if (arm_feature(env, ARM_FEATURE_IWMMXT)) { 235 env->cp15.c15_cpar = 3; 236 } else if (arm_feature(env, ARM_FEATURE_XSCALE)) { 237 env->cp15.c15_cpar = 1; 238 } 239 #else 240 241 /* 242 * If the highest available EL is EL2, AArch32 will start in Hyp 243 * mode; otherwise it starts in SVC. Note that if we start in 244 * AArch64 then these values in the uncached_cpsr will be ignored. 245 */ 246 if (arm_feature(env, ARM_FEATURE_EL2) && 247 !arm_feature(env, ARM_FEATURE_EL3)) { 248 env->uncached_cpsr = ARM_CPU_MODE_HYP; 249 } else { 250 env->uncached_cpsr = ARM_CPU_MODE_SVC; 251 } 252 env->daif = PSTATE_D | PSTATE_A | PSTATE_I | PSTATE_F; 253 254 if (arm_feature(env, ARM_FEATURE_M)) { 255 uint32_t initial_msp; /* Loaded from 0x0 */ 256 uint32_t initial_pc; /* Loaded from 0x4 */ 257 uint8_t *rom; 258 uint32_t vecbase; 259 260 if (arm_feature(env, ARM_FEATURE_M_SECURITY)) { 261 env->v7m.secure = true; 262 } else { 263 /* This bit resets to 0 if security is supported, but 1 if 264 * it is not. The bit is not present in v7M, but we set it 265 * here so we can avoid having to make checks on it conditional 266 * on ARM_FEATURE_V8 (we don't let the guest see the bit). 267 */ 268 env->v7m.aircr = R_V7M_AIRCR_BFHFNMINS_MASK; 269 /* 270 * Set NSACR to indicate "NS access permitted to everything"; 271 * this avoids having to have all the tests of it being 272 * conditional on ARM_FEATURE_M_SECURITY. Note also that from 273 * v8.1M the guest-visible value of NSACR in a CPU without the 274 * Security Extension is 0xcff. 275 */ 276 env->v7m.nsacr = 0xcff; 277 } 278 279 /* In v7M the reset value of this bit is IMPDEF, but ARM recommends 280 * that it resets to 1, so QEMU always does that rather than making 281 * it dependent on CPU model. In v8M it is RES1. 282 */ 283 env->v7m.ccr[M_REG_NS] = R_V7M_CCR_STKALIGN_MASK; 284 env->v7m.ccr[M_REG_S] = R_V7M_CCR_STKALIGN_MASK; 285 if (arm_feature(env, ARM_FEATURE_V8)) { 286 /* in v8M the NONBASETHRDENA bit [0] is RES1 */ 287 env->v7m.ccr[M_REG_NS] |= R_V7M_CCR_NONBASETHRDENA_MASK; 288 env->v7m.ccr[M_REG_S] |= R_V7M_CCR_NONBASETHRDENA_MASK; 289 } 290 if (!arm_feature(env, ARM_FEATURE_M_MAIN)) { 291 env->v7m.ccr[M_REG_NS] |= R_V7M_CCR_UNALIGN_TRP_MASK; 292 env->v7m.ccr[M_REG_S] |= R_V7M_CCR_UNALIGN_TRP_MASK; 293 } 294 295 if (arm_feature(env, ARM_FEATURE_VFP)) { 296 env->v7m.fpccr[M_REG_NS] = R_V7M_FPCCR_ASPEN_MASK; 297 env->v7m.fpccr[M_REG_S] = R_V7M_FPCCR_ASPEN_MASK | 298 R_V7M_FPCCR_LSPEN_MASK | R_V7M_FPCCR_S_MASK; 299 } 300 /* Unlike A/R profile, M profile defines the reset LR value */ 301 env->regs[14] = 0xffffffff; 302 303 env->v7m.vecbase[M_REG_S] = cpu->init_svtor & 0xffffff80; 304 305 /* Load the initial SP and PC from offset 0 and 4 in the vector table */ 306 vecbase = env->v7m.vecbase[env->v7m.secure]; 307 rom = rom_ptr(vecbase, 8); 308 if (rom) { 309 /* Address zero is covered by ROM which hasn't yet been 310 * copied into physical memory. 311 */ 312 initial_msp = ldl_p(rom); 313 initial_pc = ldl_p(rom + 4); 314 } else { 315 /* Address zero not covered by a ROM blob, or the ROM blob 316 * is in non-modifiable memory and this is a second reset after 317 * it got copied into memory. In the latter case, rom_ptr 318 * will return a NULL pointer and we should use ldl_phys instead. 319 */ 320 initial_msp = ldl_phys(s->as, vecbase); 321 initial_pc = ldl_phys(s->as, vecbase + 4); 322 } 323 324 env->regs[13] = initial_msp & 0xFFFFFFFC; 325 env->regs[15] = initial_pc & ~1; 326 env->thumb = initial_pc & 1; 327 } 328 329 /* AArch32 has a hard highvec setting of 0xFFFF0000. If we are currently 330 * executing as AArch32 then check if highvecs are enabled and 331 * adjust the PC accordingly. 332 */ 333 if (A32_BANKED_CURRENT_REG_GET(env, sctlr) & SCTLR_V) { 334 env->regs[15] = 0xFFFF0000; 335 } 336 337 /* M profile requires that reset clears the exclusive monitor; 338 * A profile does not, but clearing it makes more sense than having it 339 * set with an exclusive access on address zero. 340 */ 341 arm_clear_exclusive(env); 342 343 env->vfp.xregs[ARM_VFP_FPEXC] = 0; 344 #endif 345 346 if (arm_feature(env, ARM_FEATURE_PMSA)) { 347 if (cpu->pmsav7_dregion > 0) { 348 if (arm_feature(env, ARM_FEATURE_V8)) { 349 memset(env->pmsav8.rbar[M_REG_NS], 0, 350 sizeof(*env->pmsav8.rbar[M_REG_NS]) 351 * cpu->pmsav7_dregion); 352 memset(env->pmsav8.rlar[M_REG_NS], 0, 353 sizeof(*env->pmsav8.rlar[M_REG_NS]) 354 * cpu->pmsav7_dregion); 355 if (arm_feature(env, ARM_FEATURE_M_SECURITY)) { 356 memset(env->pmsav8.rbar[M_REG_S], 0, 357 sizeof(*env->pmsav8.rbar[M_REG_S]) 358 * cpu->pmsav7_dregion); 359 memset(env->pmsav8.rlar[M_REG_S], 0, 360 sizeof(*env->pmsav8.rlar[M_REG_S]) 361 * cpu->pmsav7_dregion); 362 } 363 } else if (arm_feature(env, ARM_FEATURE_V7)) { 364 memset(env->pmsav7.drbar, 0, 365 sizeof(*env->pmsav7.drbar) * cpu->pmsav7_dregion); 366 memset(env->pmsav7.drsr, 0, 367 sizeof(*env->pmsav7.drsr) * cpu->pmsav7_dregion); 368 memset(env->pmsav7.dracr, 0, 369 sizeof(*env->pmsav7.dracr) * cpu->pmsav7_dregion); 370 } 371 } 372 env->pmsav7.rnr[M_REG_NS] = 0; 373 env->pmsav7.rnr[M_REG_S] = 0; 374 env->pmsav8.mair0[M_REG_NS] = 0; 375 env->pmsav8.mair0[M_REG_S] = 0; 376 env->pmsav8.mair1[M_REG_NS] = 0; 377 env->pmsav8.mair1[M_REG_S] = 0; 378 } 379 380 if (arm_feature(env, ARM_FEATURE_M_SECURITY)) { 381 if (cpu->sau_sregion > 0) { 382 memset(env->sau.rbar, 0, sizeof(*env->sau.rbar) * cpu->sau_sregion); 383 memset(env->sau.rlar, 0, sizeof(*env->sau.rlar) * cpu->sau_sregion); 384 } 385 env->sau.rnr = 0; 386 /* SAU_CTRL reset value is IMPDEF; we choose 0, which is what 387 * the Cortex-M33 does. 388 */ 389 env->sau.ctrl = 0; 390 } 391 392 set_flush_to_zero(1, &env->vfp.standard_fp_status); 393 set_flush_inputs_to_zero(1, &env->vfp.standard_fp_status); 394 set_default_nan_mode(1, &env->vfp.standard_fp_status); 395 set_float_detect_tininess(float_tininess_before_rounding, 396 &env->vfp.fp_status); 397 set_float_detect_tininess(float_tininess_before_rounding, 398 &env->vfp.standard_fp_status); 399 set_float_detect_tininess(float_tininess_before_rounding, 400 &env->vfp.fp_status_f16); 401 #ifndef CONFIG_USER_ONLY 402 if (kvm_enabled()) { 403 kvm_arm_reset_vcpu(cpu); 404 } 405 #endif 406 407 hw_breakpoint_update_all(cpu); 408 hw_watchpoint_update_all(cpu); 409 arm_rebuild_hflags(env); 410 } 411 412 bool arm_cpu_exec_interrupt(CPUState *cs, int interrupt_request) 413 { 414 CPUClass *cc = CPU_GET_CLASS(cs); 415 CPUARMState *env = cs->env_ptr; 416 uint32_t cur_el = arm_current_el(env); 417 bool secure = arm_is_secure(env); 418 uint32_t target_el; 419 uint32_t excp_idx; 420 bool ret = false; 421 422 if (interrupt_request & CPU_INTERRUPT_FIQ) { 423 excp_idx = EXCP_FIQ; 424 target_el = arm_phys_excp_target_el(cs, excp_idx, cur_el, secure); 425 if (arm_excp_unmasked(cs, excp_idx, target_el)) { 426 cs->exception_index = excp_idx; 427 env->exception.target_el = target_el; 428 cc->do_interrupt(cs); 429 ret = true; 430 } 431 } 432 if (interrupt_request & CPU_INTERRUPT_HARD) { 433 excp_idx = EXCP_IRQ; 434 target_el = arm_phys_excp_target_el(cs, excp_idx, cur_el, secure); 435 if (arm_excp_unmasked(cs, excp_idx, target_el)) { 436 cs->exception_index = excp_idx; 437 env->exception.target_el = target_el; 438 cc->do_interrupt(cs); 439 ret = true; 440 } 441 } 442 if (interrupt_request & CPU_INTERRUPT_VIRQ) { 443 excp_idx = EXCP_VIRQ; 444 target_el = 1; 445 if (arm_excp_unmasked(cs, excp_idx, target_el)) { 446 cs->exception_index = excp_idx; 447 env->exception.target_el = target_el; 448 cc->do_interrupt(cs); 449 ret = true; 450 } 451 } 452 if (interrupt_request & CPU_INTERRUPT_VFIQ) { 453 excp_idx = EXCP_VFIQ; 454 target_el = 1; 455 if (arm_excp_unmasked(cs, excp_idx, target_el)) { 456 cs->exception_index = excp_idx; 457 env->exception.target_el = target_el; 458 cc->do_interrupt(cs); 459 ret = true; 460 } 461 } 462 463 return ret; 464 } 465 466 #if !defined(CONFIG_USER_ONLY) || !defined(TARGET_AARCH64) 467 static bool arm_v7m_cpu_exec_interrupt(CPUState *cs, int interrupt_request) 468 { 469 CPUClass *cc = CPU_GET_CLASS(cs); 470 ARMCPU *cpu = ARM_CPU(cs); 471 CPUARMState *env = &cpu->env; 472 bool ret = false; 473 474 /* ARMv7-M interrupt masking works differently than -A or -R. 475 * There is no FIQ/IRQ distinction. Instead of I and F bits 476 * masking FIQ and IRQ interrupts, an exception is taken only 477 * if it is higher priority than the current execution priority 478 * (which depends on state like BASEPRI, FAULTMASK and the 479 * currently active exception). 480 */ 481 if (interrupt_request & CPU_INTERRUPT_HARD 482 && (armv7m_nvic_can_take_pending_exception(env->nvic))) { 483 cs->exception_index = EXCP_IRQ; 484 cc->do_interrupt(cs); 485 ret = true; 486 } 487 return ret; 488 } 489 #endif 490 491 void arm_cpu_update_virq(ARMCPU *cpu) 492 { 493 /* 494 * Update the interrupt level for VIRQ, which is the logical OR of 495 * the HCR_EL2.VI bit and the input line level from the GIC. 496 */ 497 CPUARMState *env = &cpu->env; 498 CPUState *cs = CPU(cpu); 499 500 bool new_state = (env->cp15.hcr_el2 & HCR_VI) || 501 (env->irq_line_state & CPU_INTERRUPT_VIRQ); 502 503 if (new_state != ((cs->interrupt_request & CPU_INTERRUPT_VIRQ) != 0)) { 504 if (new_state) { 505 cpu_interrupt(cs, CPU_INTERRUPT_VIRQ); 506 } else { 507 cpu_reset_interrupt(cs, CPU_INTERRUPT_VIRQ); 508 } 509 } 510 } 511 512 void arm_cpu_update_vfiq(ARMCPU *cpu) 513 { 514 /* 515 * Update the interrupt level for VFIQ, which is the logical OR of 516 * the HCR_EL2.VF bit and the input line level from the GIC. 517 */ 518 CPUARMState *env = &cpu->env; 519 CPUState *cs = CPU(cpu); 520 521 bool new_state = (env->cp15.hcr_el2 & HCR_VF) || 522 (env->irq_line_state & CPU_INTERRUPT_VFIQ); 523 524 if (new_state != ((cs->interrupt_request & CPU_INTERRUPT_VFIQ) != 0)) { 525 if (new_state) { 526 cpu_interrupt(cs, CPU_INTERRUPT_VFIQ); 527 } else { 528 cpu_reset_interrupt(cs, CPU_INTERRUPT_VFIQ); 529 } 530 } 531 } 532 533 #ifndef CONFIG_USER_ONLY 534 static void arm_cpu_set_irq(void *opaque, int irq, int level) 535 { 536 ARMCPU *cpu = opaque; 537 CPUARMState *env = &cpu->env; 538 CPUState *cs = CPU(cpu); 539 static const int mask[] = { 540 [ARM_CPU_IRQ] = CPU_INTERRUPT_HARD, 541 [ARM_CPU_FIQ] = CPU_INTERRUPT_FIQ, 542 [ARM_CPU_VIRQ] = CPU_INTERRUPT_VIRQ, 543 [ARM_CPU_VFIQ] = CPU_INTERRUPT_VFIQ 544 }; 545 546 if (level) { 547 env->irq_line_state |= mask[irq]; 548 } else { 549 env->irq_line_state &= ~mask[irq]; 550 } 551 552 switch (irq) { 553 case ARM_CPU_VIRQ: 554 assert(arm_feature(env, ARM_FEATURE_EL2)); 555 arm_cpu_update_virq(cpu); 556 break; 557 case ARM_CPU_VFIQ: 558 assert(arm_feature(env, ARM_FEATURE_EL2)); 559 arm_cpu_update_vfiq(cpu); 560 break; 561 case ARM_CPU_IRQ: 562 case ARM_CPU_FIQ: 563 if (level) { 564 cpu_interrupt(cs, mask[irq]); 565 } else { 566 cpu_reset_interrupt(cs, mask[irq]); 567 } 568 break; 569 default: 570 g_assert_not_reached(); 571 } 572 } 573 574 static void arm_cpu_kvm_set_irq(void *opaque, int irq, int level) 575 { 576 #ifdef CONFIG_KVM 577 ARMCPU *cpu = opaque; 578 CPUARMState *env = &cpu->env; 579 CPUState *cs = CPU(cpu); 580 uint32_t linestate_bit; 581 int irq_id; 582 583 switch (irq) { 584 case ARM_CPU_IRQ: 585 irq_id = KVM_ARM_IRQ_CPU_IRQ; 586 linestate_bit = CPU_INTERRUPT_HARD; 587 break; 588 case ARM_CPU_FIQ: 589 irq_id = KVM_ARM_IRQ_CPU_FIQ; 590 linestate_bit = CPU_INTERRUPT_FIQ; 591 break; 592 default: 593 g_assert_not_reached(); 594 } 595 596 if (level) { 597 env->irq_line_state |= linestate_bit; 598 } else { 599 env->irq_line_state &= ~linestate_bit; 600 } 601 kvm_arm_set_irq(cs->cpu_index, KVM_ARM_IRQ_TYPE_CPU, irq_id, !!level); 602 #endif 603 } 604 605 static bool arm_cpu_virtio_is_big_endian(CPUState *cs) 606 { 607 ARMCPU *cpu = ARM_CPU(cs); 608 CPUARMState *env = &cpu->env; 609 610 cpu_synchronize_state(cs); 611 return arm_cpu_data_is_big_endian(env); 612 } 613 614 #endif 615 616 static inline void set_feature(CPUARMState *env, int feature) 617 { 618 env->features |= 1ULL << feature; 619 } 620 621 static inline void unset_feature(CPUARMState *env, int feature) 622 { 623 env->features &= ~(1ULL << feature); 624 } 625 626 static int 627 print_insn_thumb1(bfd_vma pc, disassemble_info *info) 628 { 629 return print_insn_arm(pc | 1, info); 630 } 631 632 static void arm_disas_set_info(CPUState *cpu, disassemble_info *info) 633 { 634 ARMCPU *ac = ARM_CPU(cpu); 635 CPUARMState *env = &ac->env; 636 bool sctlr_b; 637 638 if (is_a64(env)) { 639 /* We might not be compiled with the A64 disassembler 640 * because it needs a C++ compiler. Leave print_insn 641 * unset in this case to use the caller default behaviour. 642 */ 643 #if defined(CONFIG_ARM_A64_DIS) 644 info->print_insn = print_insn_arm_a64; 645 #endif 646 info->cap_arch = CS_ARCH_ARM64; 647 info->cap_insn_unit = 4; 648 info->cap_insn_split = 4; 649 } else { 650 int cap_mode; 651 if (env->thumb) { 652 info->print_insn = print_insn_thumb1; 653 info->cap_insn_unit = 2; 654 info->cap_insn_split = 4; 655 cap_mode = CS_MODE_THUMB; 656 } else { 657 info->print_insn = print_insn_arm; 658 info->cap_insn_unit = 4; 659 info->cap_insn_split = 4; 660 cap_mode = CS_MODE_ARM; 661 } 662 if (arm_feature(env, ARM_FEATURE_V8)) { 663 cap_mode |= CS_MODE_V8; 664 } 665 if (arm_feature(env, ARM_FEATURE_M)) { 666 cap_mode |= CS_MODE_MCLASS; 667 } 668 info->cap_arch = CS_ARCH_ARM; 669 info->cap_mode = cap_mode; 670 } 671 672 sctlr_b = arm_sctlr_b(env); 673 if (bswap_code(sctlr_b)) { 674 #ifdef TARGET_WORDS_BIGENDIAN 675 info->endian = BFD_ENDIAN_LITTLE; 676 #else 677 info->endian = BFD_ENDIAN_BIG; 678 #endif 679 } 680 info->flags &= ~INSN_ARM_BE32; 681 #ifndef CONFIG_USER_ONLY 682 if (sctlr_b) { 683 info->flags |= INSN_ARM_BE32; 684 } 685 #endif 686 } 687 688 #ifdef TARGET_AARCH64 689 690 static void aarch64_cpu_dump_state(CPUState *cs, FILE *f, int flags) 691 { 692 ARMCPU *cpu = ARM_CPU(cs); 693 CPUARMState *env = &cpu->env; 694 uint32_t psr = pstate_read(env); 695 int i; 696 int el = arm_current_el(env); 697 const char *ns_status; 698 699 qemu_fprintf(f, " PC=%016" PRIx64 " ", env->pc); 700 for (i = 0; i < 32; i++) { 701 if (i == 31) { 702 qemu_fprintf(f, " SP=%016" PRIx64 "\n", env->xregs[i]); 703 } else { 704 qemu_fprintf(f, "X%02d=%016" PRIx64 "%s", i, env->xregs[i], 705 (i + 2) % 3 ? " " : "\n"); 706 } 707 } 708 709 if (arm_feature(env, ARM_FEATURE_EL3) && el != 3) { 710 ns_status = env->cp15.scr_el3 & SCR_NS ? "NS " : "S "; 711 } else { 712 ns_status = ""; 713 } 714 qemu_fprintf(f, "PSTATE=%08x %c%c%c%c %sEL%d%c", 715 psr, 716 psr & PSTATE_N ? 'N' : '-', 717 psr & PSTATE_Z ? 'Z' : '-', 718 psr & PSTATE_C ? 'C' : '-', 719 psr & PSTATE_V ? 'V' : '-', 720 ns_status, 721 el, 722 psr & PSTATE_SP ? 'h' : 't'); 723 724 if (cpu_isar_feature(aa64_bti, cpu)) { 725 qemu_fprintf(f, " BTYPE=%d", (psr & PSTATE_BTYPE) >> 10); 726 } 727 if (!(flags & CPU_DUMP_FPU)) { 728 qemu_fprintf(f, "\n"); 729 return; 730 } 731 if (fp_exception_el(env, el) != 0) { 732 qemu_fprintf(f, " FPU disabled\n"); 733 return; 734 } 735 qemu_fprintf(f, " FPCR=%08x FPSR=%08x\n", 736 vfp_get_fpcr(env), vfp_get_fpsr(env)); 737 738 if (cpu_isar_feature(aa64_sve, cpu) && sve_exception_el(env, el) == 0) { 739 int j, zcr_len = sve_zcr_len_for_el(env, el); 740 741 for (i = 0; i <= FFR_PRED_NUM; i++) { 742 bool eol; 743 if (i == FFR_PRED_NUM) { 744 qemu_fprintf(f, "FFR="); 745 /* It's last, so end the line. */ 746 eol = true; 747 } else { 748 qemu_fprintf(f, "P%02d=", i); 749 switch (zcr_len) { 750 case 0: 751 eol = i % 8 == 7; 752 break; 753 case 1: 754 eol = i % 6 == 5; 755 break; 756 case 2: 757 case 3: 758 eol = i % 3 == 2; 759 break; 760 default: 761 /* More than one quadword per predicate. */ 762 eol = true; 763 break; 764 } 765 } 766 for (j = zcr_len / 4; j >= 0; j--) { 767 int digits; 768 if (j * 4 + 4 <= zcr_len + 1) { 769 digits = 16; 770 } else { 771 digits = (zcr_len % 4 + 1) * 4; 772 } 773 qemu_fprintf(f, "%0*" PRIx64 "%s", digits, 774 env->vfp.pregs[i].p[j], 775 j ? ":" : eol ? "\n" : " "); 776 } 777 } 778 779 for (i = 0; i < 32; i++) { 780 if (zcr_len == 0) { 781 qemu_fprintf(f, "Z%02d=%016" PRIx64 ":%016" PRIx64 "%s", 782 i, env->vfp.zregs[i].d[1], 783 env->vfp.zregs[i].d[0], i & 1 ? "\n" : " "); 784 } else if (zcr_len == 1) { 785 qemu_fprintf(f, "Z%02d=%016" PRIx64 ":%016" PRIx64 786 ":%016" PRIx64 ":%016" PRIx64 "\n", 787 i, env->vfp.zregs[i].d[3], env->vfp.zregs[i].d[2], 788 env->vfp.zregs[i].d[1], env->vfp.zregs[i].d[0]); 789 } else { 790 for (j = zcr_len; j >= 0; j--) { 791 bool odd = (zcr_len - j) % 2 != 0; 792 if (j == zcr_len) { 793 qemu_fprintf(f, "Z%02d[%x-%x]=", i, j, j - 1); 794 } else if (!odd) { 795 if (j > 0) { 796 qemu_fprintf(f, " [%x-%x]=", j, j - 1); 797 } else { 798 qemu_fprintf(f, " [%x]=", j); 799 } 800 } 801 qemu_fprintf(f, "%016" PRIx64 ":%016" PRIx64 "%s", 802 env->vfp.zregs[i].d[j * 2 + 1], 803 env->vfp.zregs[i].d[j * 2], 804 odd || j == 0 ? "\n" : ":"); 805 } 806 } 807 } 808 } else { 809 for (i = 0; i < 32; i++) { 810 uint64_t *q = aa64_vfp_qreg(env, i); 811 qemu_fprintf(f, "Q%02d=%016" PRIx64 ":%016" PRIx64 "%s", 812 i, q[1], q[0], (i & 1 ? "\n" : " ")); 813 } 814 } 815 } 816 817 #else 818 819 static inline void aarch64_cpu_dump_state(CPUState *cs, FILE *f, int flags) 820 { 821 g_assert_not_reached(); 822 } 823 824 #endif 825 826 static void arm_cpu_dump_state(CPUState *cs, FILE *f, int flags) 827 { 828 ARMCPU *cpu = ARM_CPU(cs); 829 CPUARMState *env = &cpu->env; 830 int i; 831 832 if (is_a64(env)) { 833 aarch64_cpu_dump_state(cs, f, flags); 834 return; 835 } 836 837 for (i = 0; i < 16; i++) { 838 qemu_fprintf(f, "R%02d=%08x", i, env->regs[i]); 839 if ((i % 4) == 3) { 840 qemu_fprintf(f, "\n"); 841 } else { 842 qemu_fprintf(f, " "); 843 } 844 } 845 846 if (arm_feature(env, ARM_FEATURE_M)) { 847 uint32_t xpsr = xpsr_read(env); 848 const char *mode; 849 const char *ns_status = ""; 850 851 if (arm_feature(env, ARM_FEATURE_M_SECURITY)) { 852 ns_status = env->v7m.secure ? "S " : "NS "; 853 } 854 855 if (xpsr & XPSR_EXCP) { 856 mode = "handler"; 857 } else { 858 if (env->v7m.control[env->v7m.secure] & R_V7M_CONTROL_NPRIV_MASK) { 859 mode = "unpriv-thread"; 860 } else { 861 mode = "priv-thread"; 862 } 863 } 864 865 qemu_fprintf(f, "XPSR=%08x %c%c%c%c %c %s%s\n", 866 xpsr, 867 xpsr & XPSR_N ? 'N' : '-', 868 xpsr & XPSR_Z ? 'Z' : '-', 869 xpsr & XPSR_C ? 'C' : '-', 870 xpsr & XPSR_V ? 'V' : '-', 871 xpsr & XPSR_T ? 'T' : 'A', 872 ns_status, 873 mode); 874 } else { 875 uint32_t psr = cpsr_read(env); 876 const char *ns_status = ""; 877 878 if (arm_feature(env, ARM_FEATURE_EL3) && 879 (psr & CPSR_M) != ARM_CPU_MODE_MON) { 880 ns_status = env->cp15.scr_el3 & SCR_NS ? "NS " : "S "; 881 } 882 883 qemu_fprintf(f, "PSR=%08x %c%c%c%c %c %s%s%d\n", 884 psr, 885 psr & CPSR_N ? 'N' : '-', 886 psr & CPSR_Z ? 'Z' : '-', 887 psr & CPSR_C ? 'C' : '-', 888 psr & CPSR_V ? 'V' : '-', 889 psr & CPSR_T ? 'T' : 'A', 890 ns_status, 891 aarch32_mode_name(psr), (psr & 0x10) ? 32 : 26); 892 } 893 894 if (flags & CPU_DUMP_FPU) { 895 int numvfpregs = 0; 896 if (arm_feature(env, ARM_FEATURE_VFP)) { 897 numvfpregs += 16; 898 } 899 if (arm_feature(env, ARM_FEATURE_VFP3)) { 900 numvfpregs += 16; 901 } 902 for (i = 0; i < numvfpregs; i++) { 903 uint64_t v = *aa32_vfp_dreg(env, i); 904 qemu_fprintf(f, "s%02d=%08x s%02d=%08x d%02d=%016" PRIx64 "\n", 905 i * 2, (uint32_t)v, 906 i * 2 + 1, (uint32_t)(v >> 32), 907 i, v); 908 } 909 qemu_fprintf(f, "FPSCR: %08x\n", vfp_get_fpscr(env)); 910 } 911 } 912 913 uint64_t arm_cpu_mp_affinity(int idx, uint8_t clustersz) 914 { 915 uint32_t Aff1 = idx / clustersz; 916 uint32_t Aff0 = idx % clustersz; 917 return (Aff1 << ARM_AFF1_SHIFT) | Aff0; 918 } 919 920 static void cpreg_hashtable_data_destroy(gpointer data) 921 { 922 /* 923 * Destroy function for cpu->cp_regs hashtable data entries. 924 * We must free the name string because it was g_strdup()ed in 925 * add_cpreg_to_hashtable(). It's OK to cast away the 'const' 926 * from r->name because we know we definitely allocated it. 927 */ 928 ARMCPRegInfo *r = data; 929 930 g_free((void *)r->name); 931 g_free(r); 932 } 933 934 static void arm_cpu_initfn(Object *obj) 935 { 936 ARMCPU *cpu = ARM_CPU(obj); 937 938 cpu_set_cpustate_pointers(cpu); 939 cpu->cp_regs = g_hash_table_new_full(g_int_hash, g_int_equal, 940 g_free, cpreg_hashtable_data_destroy); 941 942 QLIST_INIT(&cpu->pre_el_change_hooks); 943 QLIST_INIT(&cpu->el_change_hooks); 944 945 #ifndef CONFIG_USER_ONLY 946 /* Our inbound IRQ and FIQ lines */ 947 if (kvm_enabled()) { 948 /* VIRQ and VFIQ are unused with KVM but we add them to maintain 949 * the same interface as non-KVM CPUs. 950 */ 951 qdev_init_gpio_in(DEVICE(cpu), arm_cpu_kvm_set_irq, 4); 952 } else { 953 qdev_init_gpio_in(DEVICE(cpu), arm_cpu_set_irq, 4); 954 } 955 956 qdev_init_gpio_out(DEVICE(cpu), cpu->gt_timer_outputs, 957 ARRAY_SIZE(cpu->gt_timer_outputs)); 958 959 qdev_init_gpio_out_named(DEVICE(cpu), &cpu->gicv3_maintenance_interrupt, 960 "gicv3-maintenance-interrupt", 1); 961 qdev_init_gpio_out_named(DEVICE(cpu), &cpu->pmu_interrupt, 962 "pmu-interrupt", 1); 963 #endif 964 965 /* DTB consumers generally don't in fact care what the 'compatible' 966 * string is, so always provide some string and trust that a hypothetical 967 * picky DTB consumer will also provide a helpful error message. 968 */ 969 cpu->dtb_compatible = "qemu,unknown"; 970 cpu->psci_version = 1; /* By default assume PSCI v0.1 */ 971 cpu->kvm_target = QEMU_KVM_ARM_TARGET_NONE; 972 973 if (tcg_enabled()) { 974 cpu->psci_version = 2; /* TCG implements PSCI 0.2 */ 975 } 976 } 977 978 static Property arm_cpu_reset_cbar_property = 979 DEFINE_PROP_UINT64("reset-cbar", ARMCPU, reset_cbar, 0); 980 981 static Property arm_cpu_reset_hivecs_property = 982 DEFINE_PROP_BOOL("reset-hivecs", ARMCPU, reset_hivecs, false); 983 984 static Property arm_cpu_rvbar_property = 985 DEFINE_PROP_UINT64("rvbar", ARMCPU, rvbar, 0); 986 987 static Property arm_cpu_has_el2_property = 988 DEFINE_PROP_BOOL("has_el2", ARMCPU, has_el2, true); 989 990 static Property arm_cpu_has_el3_property = 991 DEFINE_PROP_BOOL("has_el3", ARMCPU, has_el3, true); 992 993 static Property arm_cpu_cfgend_property = 994 DEFINE_PROP_BOOL("cfgend", ARMCPU, cfgend, false); 995 996 static Property arm_cpu_has_vfp_property = 997 DEFINE_PROP_BOOL("vfp", ARMCPU, has_vfp, true); 998 999 static Property arm_cpu_has_neon_property = 1000 DEFINE_PROP_BOOL("neon", ARMCPU, has_neon, true); 1001 1002 static Property arm_cpu_has_dsp_property = 1003 DEFINE_PROP_BOOL("dsp", ARMCPU, has_dsp, true); 1004 1005 static Property arm_cpu_has_mpu_property = 1006 DEFINE_PROP_BOOL("has-mpu", ARMCPU, has_mpu, true); 1007 1008 /* This is like DEFINE_PROP_UINT32 but it doesn't set the default value, 1009 * because the CPU initfn will have already set cpu->pmsav7_dregion to 1010 * the right value for that particular CPU type, and we don't want 1011 * to override that with an incorrect constant value. 1012 */ 1013 static Property arm_cpu_pmsav7_dregion_property = 1014 DEFINE_PROP_UNSIGNED_NODEFAULT("pmsav7-dregion", ARMCPU, 1015 pmsav7_dregion, 1016 qdev_prop_uint32, uint32_t); 1017 1018 static bool arm_get_pmu(Object *obj, Error **errp) 1019 { 1020 ARMCPU *cpu = ARM_CPU(obj); 1021 1022 return cpu->has_pmu; 1023 } 1024 1025 static void arm_set_pmu(Object *obj, bool value, Error **errp) 1026 { 1027 ARMCPU *cpu = ARM_CPU(obj); 1028 1029 if (value) { 1030 if (kvm_enabled() && !kvm_arm_pmu_supported(CPU(cpu))) { 1031 error_setg(errp, "'pmu' feature not supported by KVM on this host"); 1032 return; 1033 } 1034 set_feature(&cpu->env, ARM_FEATURE_PMU); 1035 } else { 1036 unset_feature(&cpu->env, ARM_FEATURE_PMU); 1037 } 1038 cpu->has_pmu = value; 1039 } 1040 1041 static void arm_get_init_svtor(Object *obj, Visitor *v, const char *name, 1042 void *opaque, Error **errp) 1043 { 1044 ARMCPU *cpu = ARM_CPU(obj); 1045 1046 visit_type_uint32(v, name, &cpu->init_svtor, errp); 1047 } 1048 1049 static void arm_set_init_svtor(Object *obj, Visitor *v, const char *name, 1050 void *opaque, Error **errp) 1051 { 1052 ARMCPU *cpu = ARM_CPU(obj); 1053 1054 visit_type_uint32(v, name, &cpu->init_svtor, errp); 1055 } 1056 1057 void arm_cpu_post_init(Object *obj) 1058 { 1059 ARMCPU *cpu = ARM_CPU(obj); 1060 1061 /* M profile implies PMSA. We have to do this here rather than 1062 * in realize with the other feature-implication checks because 1063 * we look at the PMSA bit to see if we should add some properties. 1064 */ 1065 if (arm_feature(&cpu->env, ARM_FEATURE_M)) { 1066 set_feature(&cpu->env, ARM_FEATURE_PMSA); 1067 } 1068 /* Similarly for the VFP feature bits */ 1069 if (arm_feature(&cpu->env, ARM_FEATURE_VFP4)) { 1070 set_feature(&cpu->env, ARM_FEATURE_VFP3); 1071 } 1072 if (arm_feature(&cpu->env, ARM_FEATURE_VFP3)) { 1073 set_feature(&cpu->env, ARM_FEATURE_VFP); 1074 } 1075 1076 if (arm_feature(&cpu->env, ARM_FEATURE_CBAR) || 1077 arm_feature(&cpu->env, ARM_FEATURE_CBAR_RO)) { 1078 qdev_property_add_static(DEVICE(obj), &arm_cpu_reset_cbar_property, 1079 &error_abort); 1080 } 1081 1082 if (!arm_feature(&cpu->env, ARM_FEATURE_M)) { 1083 qdev_property_add_static(DEVICE(obj), &arm_cpu_reset_hivecs_property, 1084 &error_abort); 1085 } 1086 1087 if (arm_feature(&cpu->env, ARM_FEATURE_AARCH64)) { 1088 qdev_property_add_static(DEVICE(obj), &arm_cpu_rvbar_property, 1089 &error_abort); 1090 } 1091 1092 if (arm_feature(&cpu->env, ARM_FEATURE_EL3)) { 1093 /* Add the has_el3 state CPU property only if EL3 is allowed. This will 1094 * prevent "has_el3" from existing on CPUs which cannot support EL3. 1095 */ 1096 qdev_property_add_static(DEVICE(obj), &arm_cpu_has_el3_property, 1097 &error_abort); 1098 1099 #ifndef CONFIG_USER_ONLY 1100 object_property_add_link(obj, "secure-memory", 1101 TYPE_MEMORY_REGION, 1102 (Object **)&cpu->secure_memory, 1103 qdev_prop_allow_set_link_before_realize, 1104 OBJ_PROP_LINK_STRONG, 1105 &error_abort); 1106 #endif 1107 } 1108 1109 if (arm_feature(&cpu->env, ARM_FEATURE_EL2)) { 1110 qdev_property_add_static(DEVICE(obj), &arm_cpu_has_el2_property, 1111 &error_abort); 1112 } 1113 1114 if (arm_feature(&cpu->env, ARM_FEATURE_PMU)) { 1115 cpu->has_pmu = true; 1116 object_property_add_bool(obj, "pmu", arm_get_pmu, arm_set_pmu, 1117 &error_abort); 1118 } 1119 1120 /* 1121 * Allow user to turn off VFP and Neon support, but only for TCG -- 1122 * KVM does not currently allow us to lie to the guest about its 1123 * ID/feature registers, so the guest always sees what the host has. 1124 */ 1125 if (arm_feature(&cpu->env, ARM_FEATURE_VFP)) { 1126 cpu->has_vfp = true; 1127 if (!kvm_enabled()) { 1128 qdev_property_add_static(DEVICE(obj), &arm_cpu_has_vfp_property, 1129 &error_abort); 1130 } 1131 } 1132 1133 if (arm_feature(&cpu->env, ARM_FEATURE_NEON)) { 1134 cpu->has_neon = true; 1135 if (!kvm_enabled()) { 1136 qdev_property_add_static(DEVICE(obj), &arm_cpu_has_neon_property, 1137 &error_abort); 1138 } 1139 } 1140 1141 if (arm_feature(&cpu->env, ARM_FEATURE_M) && 1142 arm_feature(&cpu->env, ARM_FEATURE_THUMB_DSP)) { 1143 qdev_property_add_static(DEVICE(obj), &arm_cpu_has_dsp_property, 1144 &error_abort); 1145 } 1146 1147 if (arm_feature(&cpu->env, ARM_FEATURE_PMSA)) { 1148 qdev_property_add_static(DEVICE(obj), &arm_cpu_has_mpu_property, 1149 &error_abort); 1150 if (arm_feature(&cpu->env, ARM_FEATURE_V7)) { 1151 qdev_property_add_static(DEVICE(obj), 1152 &arm_cpu_pmsav7_dregion_property, 1153 &error_abort); 1154 } 1155 } 1156 1157 if (arm_feature(&cpu->env, ARM_FEATURE_M_SECURITY)) { 1158 object_property_add_link(obj, "idau", TYPE_IDAU_INTERFACE, &cpu->idau, 1159 qdev_prop_allow_set_link_before_realize, 1160 OBJ_PROP_LINK_STRONG, 1161 &error_abort); 1162 /* 1163 * M profile: initial value of the Secure VTOR. We can't just use 1164 * a simple DEFINE_PROP_UINT32 for this because we want to permit 1165 * the property to be set after realize. 1166 */ 1167 object_property_add(obj, "init-svtor", "uint32", 1168 arm_get_init_svtor, arm_set_init_svtor, 1169 NULL, NULL, &error_abort); 1170 } 1171 1172 qdev_property_add_static(DEVICE(obj), &arm_cpu_cfgend_property, 1173 &error_abort); 1174 } 1175 1176 static void arm_cpu_finalizefn(Object *obj) 1177 { 1178 ARMCPU *cpu = ARM_CPU(obj); 1179 ARMELChangeHook *hook, *next; 1180 1181 g_hash_table_destroy(cpu->cp_regs); 1182 1183 QLIST_FOREACH_SAFE(hook, &cpu->pre_el_change_hooks, node, next) { 1184 QLIST_REMOVE(hook, node); 1185 g_free(hook); 1186 } 1187 QLIST_FOREACH_SAFE(hook, &cpu->el_change_hooks, node, next) { 1188 QLIST_REMOVE(hook, node); 1189 g_free(hook); 1190 } 1191 #ifndef CONFIG_USER_ONLY 1192 if (cpu->pmu_timer) { 1193 timer_del(cpu->pmu_timer); 1194 timer_deinit(cpu->pmu_timer); 1195 timer_free(cpu->pmu_timer); 1196 } 1197 #endif 1198 } 1199 1200 static void arm_cpu_realizefn(DeviceState *dev, Error **errp) 1201 { 1202 CPUState *cs = CPU(dev); 1203 ARMCPU *cpu = ARM_CPU(dev); 1204 ARMCPUClass *acc = ARM_CPU_GET_CLASS(dev); 1205 CPUARMState *env = &cpu->env; 1206 int pagebits; 1207 Error *local_err = NULL; 1208 bool no_aa32 = false; 1209 1210 /* If we needed to query the host kernel for the CPU features 1211 * then it's possible that might have failed in the initfn, but 1212 * this is the first point where we can report it. 1213 */ 1214 if (cpu->host_cpu_probe_failed) { 1215 if (!kvm_enabled()) { 1216 error_setg(errp, "The 'host' CPU type can only be used with KVM"); 1217 } else { 1218 error_setg(errp, "Failed to retrieve host CPU features"); 1219 } 1220 return; 1221 } 1222 1223 #ifndef CONFIG_USER_ONLY 1224 /* The NVIC and M-profile CPU are two halves of a single piece of 1225 * hardware; trying to use one without the other is a command line 1226 * error and will result in segfaults if not caught here. 1227 */ 1228 if (arm_feature(env, ARM_FEATURE_M)) { 1229 if (!env->nvic) { 1230 error_setg(errp, "This board cannot be used with Cortex-M CPUs"); 1231 return; 1232 } 1233 } else { 1234 if (env->nvic) { 1235 error_setg(errp, "This board can only be used with Cortex-M CPUs"); 1236 return; 1237 } 1238 } 1239 1240 cpu->gt_timer[GTIMER_PHYS] = timer_new(QEMU_CLOCK_VIRTUAL, GTIMER_SCALE, 1241 arm_gt_ptimer_cb, cpu); 1242 cpu->gt_timer[GTIMER_VIRT] = timer_new(QEMU_CLOCK_VIRTUAL, GTIMER_SCALE, 1243 arm_gt_vtimer_cb, cpu); 1244 cpu->gt_timer[GTIMER_HYP] = timer_new(QEMU_CLOCK_VIRTUAL, GTIMER_SCALE, 1245 arm_gt_htimer_cb, cpu); 1246 cpu->gt_timer[GTIMER_SEC] = timer_new(QEMU_CLOCK_VIRTUAL, GTIMER_SCALE, 1247 arm_gt_stimer_cb, cpu); 1248 #endif 1249 1250 cpu_exec_realizefn(cs, &local_err); 1251 if (local_err != NULL) { 1252 error_propagate(errp, local_err); 1253 return; 1254 } 1255 1256 if (arm_feature(env, ARM_FEATURE_AARCH64) && 1257 cpu->has_vfp != cpu->has_neon) { 1258 /* 1259 * This is an architectural requirement for AArch64; AArch32 is 1260 * more flexible and permits VFP-no-Neon and Neon-no-VFP. 1261 */ 1262 error_setg(errp, 1263 "AArch64 CPUs must have both VFP and Neon or neither"); 1264 return; 1265 } 1266 1267 if (!cpu->has_vfp) { 1268 uint64_t t; 1269 uint32_t u; 1270 1271 unset_feature(env, ARM_FEATURE_VFP); 1272 unset_feature(env, ARM_FEATURE_VFP3); 1273 unset_feature(env, ARM_FEATURE_VFP4); 1274 1275 t = cpu->isar.id_aa64isar1; 1276 t = FIELD_DP64(t, ID_AA64ISAR1, JSCVT, 0); 1277 cpu->isar.id_aa64isar1 = t; 1278 1279 t = cpu->isar.id_aa64pfr0; 1280 t = FIELD_DP64(t, ID_AA64PFR0, FP, 0xf); 1281 cpu->isar.id_aa64pfr0 = t; 1282 1283 u = cpu->isar.id_isar6; 1284 u = FIELD_DP32(u, ID_ISAR6, JSCVT, 0); 1285 cpu->isar.id_isar6 = u; 1286 1287 u = cpu->isar.mvfr0; 1288 u = FIELD_DP32(u, MVFR0, FPSP, 0); 1289 u = FIELD_DP32(u, MVFR0, FPDP, 0); 1290 u = FIELD_DP32(u, MVFR0, FPTRAP, 0); 1291 u = FIELD_DP32(u, MVFR0, FPDIVIDE, 0); 1292 u = FIELD_DP32(u, MVFR0, FPSQRT, 0); 1293 u = FIELD_DP32(u, MVFR0, FPSHVEC, 0); 1294 u = FIELD_DP32(u, MVFR0, FPROUND, 0); 1295 cpu->isar.mvfr0 = u; 1296 1297 u = cpu->isar.mvfr1; 1298 u = FIELD_DP32(u, MVFR1, FPFTZ, 0); 1299 u = FIELD_DP32(u, MVFR1, FPDNAN, 0); 1300 u = FIELD_DP32(u, MVFR1, FPHP, 0); 1301 cpu->isar.mvfr1 = u; 1302 1303 u = cpu->isar.mvfr2; 1304 u = FIELD_DP32(u, MVFR2, FPMISC, 0); 1305 cpu->isar.mvfr2 = u; 1306 } 1307 1308 if (!cpu->has_neon) { 1309 uint64_t t; 1310 uint32_t u; 1311 1312 unset_feature(env, ARM_FEATURE_NEON); 1313 1314 t = cpu->isar.id_aa64isar0; 1315 t = FIELD_DP64(t, ID_AA64ISAR0, DP, 0); 1316 cpu->isar.id_aa64isar0 = t; 1317 1318 t = cpu->isar.id_aa64isar1; 1319 t = FIELD_DP64(t, ID_AA64ISAR1, FCMA, 0); 1320 cpu->isar.id_aa64isar1 = t; 1321 1322 t = cpu->isar.id_aa64pfr0; 1323 t = FIELD_DP64(t, ID_AA64PFR0, ADVSIMD, 0xf); 1324 cpu->isar.id_aa64pfr0 = t; 1325 1326 u = cpu->isar.id_isar5; 1327 u = FIELD_DP32(u, ID_ISAR5, RDM, 0); 1328 u = FIELD_DP32(u, ID_ISAR5, VCMA, 0); 1329 cpu->isar.id_isar5 = u; 1330 1331 u = cpu->isar.id_isar6; 1332 u = FIELD_DP32(u, ID_ISAR6, DP, 0); 1333 u = FIELD_DP32(u, ID_ISAR6, FHM, 0); 1334 cpu->isar.id_isar6 = u; 1335 1336 u = cpu->isar.mvfr1; 1337 u = FIELD_DP32(u, MVFR1, SIMDLS, 0); 1338 u = FIELD_DP32(u, MVFR1, SIMDINT, 0); 1339 u = FIELD_DP32(u, MVFR1, SIMDSP, 0); 1340 u = FIELD_DP32(u, MVFR1, SIMDHP, 0); 1341 u = FIELD_DP32(u, MVFR1, SIMDFMAC, 0); 1342 cpu->isar.mvfr1 = u; 1343 1344 u = cpu->isar.mvfr2; 1345 u = FIELD_DP32(u, MVFR2, SIMDMISC, 0); 1346 cpu->isar.mvfr2 = u; 1347 } 1348 1349 if (!cpu->has_neon && !cpu->has_vfp) { 1350 uint64_t t; 1351 uint32_t u; 1352 1353 t = cpu->isar.id_aa64isar0; 1354 t = FIELD_DP64(t, ID_AA64ISAR0, FHM, 0); 1355 cpu->isar.id_aa64isar0 = t; 1356 1357 t = cpu->isar.id_aa64isar1; 1358 t = FIELD_DP64(t, ID_AA64ISAR1, FRINTTS, 0); 1359 cpu->isar.id_aa64isar1 = t; 1360 1361 u = cpu->isar.mvfr0; 1362 u = FIELD_DP32(u, MVFR0, SIMDREG, 0); 1363 cpu->isar.mvfr0 = u; 1364 } 1365 1366 if (arm_feature(env, ARM_FEATURE_M) && !cpu->has_dsp) { 1367 uint32_t u; 1368 1369 unset_feature(env, ARM_FEATURE_THUMB_DSP); 1370 1371 u = cpu->isar.id_isar1; 1372 u = FIELD_DP32(u, ID_ISAR1, EXTEND, 1); 1373 cpu->isar.id_isar1 = u; 1374 1375 u = cpu->isar.id_isar2; 1376 u = FIELD_DP32(u, ID_ISAR2, MULTU, 1); 1377 u = FIELD_DP32(u, ID_ISAR2, MULTS, 1); 1378 cpu->isar.id_isar2 = u; 1379 1380 u = cpu->isar.id_isar3; 1381 u = FIELD_DP32(u, ID_ISAR3, SIMD, 1); 1382 u = FIELD_DP32(u, ID_ISAR3, SATURATE, 0); 1383 cpu->isar.id_isar3 = u; 1384 } 1385 1386 /* Some features automatically imply others: */ 1387 if (arm_feature(env, ARM_FEATURE_V8)) { 1388 if (arm_feature(env, ARM_FEATURE_M)) { 1389 set_feature(env, ARM_FEATURE_V7); 1390 } else { 1391 set_feature(env, ARM_FEATURE_V7VE); 1392 } 1393 } 1394 1395 /* 1396 * There exist AArch64 cpus without AArch32 support. When KVM 1397 * queries ID_ISAR0_EL1 on such a host, the value is UNKNOWN. 1398 * Similarly, we cannot check ID_AA64PFR0 without AArch64 support. 1399 * As a general principle, we also do not make ID register 1400 * consistency checks anywhere unless using TCG, because only 1401 * for TCG would a consistency-check failure be a QEMU bug. 1402 */ 1403 if (arm_feature(&cpu->env, ARM_FEATURE_AARCH64)) { 1404 no_aa32 = !cpu_isar_feature(aa64_aa32, cpu); 1405 } 1406 1407 if (arm_feature(env, ARM_FEATURE_V7VE)) { 1408 /* v7 Virtualization Extensions. In real hardware this implies 1409 * EL2 and also the presence of the Security Extensions. 1410 * For QEMU, for backwards-compatibility we implement some 1411 * CPUs or CPU configs which have no actual EL2 or EL3 but do 1412 * include the various other features that V7VE implies. 1413 * Presence of EL2 itself is ARM_FEATURE_EL2, and of the 1414 * Security Extensions is ARM_FEATURE_EL3. 1415 */ 1416 assert(!tcg_enabled() || no_aa32 || cpu_isar_feature(arm_div, cpu)); 1417 set_feature(env, ARM_FEATURE_LPAE); 1418 set_feature(env, ARM_FEATURE_V7); 1419 } 1420 if (arm_feature(env, ARM_FEATURE_V7)) { 1421 set_feature(env, ARM_FEATURE_VAPA); 1422 set_feature(env, ARM_FEATURE_THUMB2); 1423 set_feature(env, ARM_FEATURE_MPIDR); 1424 if (!arm_feature(env, ARM_FEATURE_M)) { 1425 set_feature(env, ARM_FEATURE_V6K); 1426 } else { 1427 set_feature(env, ARM_FEATURE_V6); 1428 } 1429 1430 /* Always define VBAR for V7 CPUs even if it doesn't exist in 1431 * non-EL3 configs. This is needed by some legacy boards. 1432 */ 1433 set_feature(env, ARM_FEATURE_VBAR); 1434 } 1435 if (arm_feature(env, ARM_FEATURE_V6K)) { 1436 set_feature(env, ARM_FEATURE_V6); 1437 set_feature(env, ARM_FEATURE_MVFR); 1438 } 1439 if (arm_feature(env, ARM_FEATURE_V6)) { 1440 set_feature(env, ARM_FEATURE_V5); 1441 if (!arm_feature(env, ARM_FEATURE_M)) { 1442 assert(!tcg_enabled() || no_aa32 || cpu_isar_feature(jazelle, cpu)); 1443 set_feature(env, ARM_FEATURE_AUXCR); 1444 } 1445 } 1446 if (arm_feature(env, ARM_FEATURE_V5)) { 1447 set_feature(env, ARM_FEATURE_V4T); 1448 } 1449 if (arm_feature(env, ARM_FEATURE_LPAE)) { 1450 set_feature(env, ARM_FEATURE_V7MP); 1451 set_feature(env, ARM_FEATURE_PXN); 1452 } 1453 if (arm_feature(env, ARM_FEATURE_CBAR_RO)) { 1454 set_feature(env, ARM_FEATURE_CBAR); 1455 } 1456 if (arm_feature(env, ARM_FEATURE_THUMB2) && 1457 !arm_feature(env, ARM_FEATURE_M)) { 1458 set_feature(env, ARM_FEATURE_THUMB_DSP); 1459 } 1460 1461 /* 1462 * We rely on no XScale CPU having VFP so we can use the same bits in the 1463 * TB flags field for VECSTRIDE and XSCALE_CPAR. 1464 */ 1465 assert(!(arm_feature(env, ARM_FEATURE_VFP) && 1466 arm_feature(env, ARM_FEATURE_XSCALE))); 1467 1468 if (arm_feature(env, ARM_FEATURE_V7) && 1469 !arm_feature(env, ARM_FEATURE_M) && 1470 !arm_feature(env, ARM_FEATURE_PMSA)) { 1471 /* v7VMSA drops support for the old ARMv5 tiny pages, so we 1472 * can use 4K pages. 1473 */ 1474 pagebits = 12; 1475 } else { 1476 /* For CPUs which might have tiny 1K pages, or which have an 1477 * MPU and might have small region sizes, stick with 1K pages. 1478 */ 1479 pagebits = 10; 1480 } 1481 if (!set_preferred_target_page_bits(pagebits)) { 1482 /* This can only ever happen for hotplugging a CPU, or if 1483 * the board code incorrectly creates a CPU which it has 1484 * promised via minimum_page_size that it will not. 1485 */ 1486 error_setg(errp, "This CPU requires a smaller page size than the " 1487 "system is using"); 1488 return; 1489 } 1490 1491 /* This cpu-id-to-MPIDR affinity is used only for TCG; KVM will override it. 1492 * We don't support setting cluster ID ([16..23]) (known as Aff2 1493 * in later ARM ARM versions), or any of the higher affinity level fields, 1494 * so these bits always RAZ. 1495 */ 1496 if (cpu->mp_affinity == ARM64_AFFINITY_INVALID) { 1497 cpu->mp_affinity = arm_cpu_mp_affinity(cs->cpu_index, 1498 ARM_DEFAULT_CPUS_PER_CLUSTER); 1499 } 1500 1501 if (cpu->reset_hivecs) { 1502 cpu->reset_sctlr |= (1 << 13); 1503 } 1504 1505 if (cpu->cfgend) { 1506 if (arm_feature(&cpu->env, ARM_FEATURE_V7)) { 1507 cpu->reset_sctlr |= SCTLR_EE; 1508 } else { 1509 cpu->reset_sctlr |= SCTLR_B; 1510 } 1511 } 1512 1513 if (!cpu->has_el3) { 1514 /* If the has_el3 CPU property is disabled then we need to disable the 1515 * feature. 1516 */ 1517 unset_feature(env, ARM_FEATURE_EL3); 1518 1519 /* Disable the security extension feature bits in the processor feature 1520 * registers as well. These are id_pfr1[7:4] and id_aa64pfr0[15:12]. 1521 */ 1522 cpu->id_pfr1 &= ~0xf0; 1523 cpu->isar.id_aa64pfr0 &= ~0xf000; 1524 } 1525 1526 if (!cpu->has_el2) { 1527 unset_feature(env, ARM_FEATURE_EL2); 1528 } 1529 1530 if (!cpu->has_pmu) { 1531 unset_feature(env, ARM_FEATURE_PMU); 1532 } 1533 if (arm_feature(env, ARM_FEATURE_PMU)) { 1534 pmu_init(cpu); 1535 1536 if (!kvm_enabled()) { 1537 arm_register_pre_el_change_hook(cpu, &pmu_pre_el_change, 0); 1538 arm_register_el_change_hook(cpu, &pmu_post_el_change, 0); 1539 } 1540 1541 #ifndef CONFIG_USER_ONLY 1542 cpu->pmu_timer = timer_new_ns(QEMU_CLOCK_VIRTUAL, arm_pmu_timer_cb, 1543 cpu); 1544 #endif 1545 } else { 1546 cpu->id_aa64dfr0 &= ~0xf00; 1547 cpu->id_dfr0 &= ~(0xf << 24); 1548 cpu->pmceid0 = 0; 1549 cpu->pmceid1 = 0; 1550 } 1551 1552 if (!arm_feature(env, ARM_FEATURE_EL2)) { 1553 /* Disable the hypervisor feature bits in the processor feature 1554 * registers if we don't have EL2. These are id_pfr1[15:12] and 1555 * id_aa64pfr0_el1[11:8]. 1556 */ 1557 cpu->isar.id_aa64pfr0 &= ~0xf00; 1558 cpu->id_pfr1 &= ~0xf000; 1559 } 1560 1561 /* MPU can be configured out of a PMSA CPU either by setting has-mpu 1562 * to false or by setting pmsav7-dregion to 0. 1563 */ 1564 if (!cpu->has_mpu) { 1565 cpu->pmsav7_dregion = 0; 1566 } 1567 if (cpu->pmsav7_dregion == 0) { 1568 cpu->has_mpu = false; 1569 } 1570 1571 if (arm_feature(env, ARM_FEATURE_PMSA) && 1572 arm_feature(env, ARM_FEATURE_V7)) { 1573 uint32_t nr = cpu->pmsav7_dregion; 1574 1575 if (nr > 0xff) { 1576 error_setg(errp, "PMSAv7 MPU #regions invalid %" PRIu32, nr); 1577 return; 1578 } 1579 1580 if (nr) { 1581 if (arm_feature(env, ARM_FEATURE_V8)) { 1582 /* PMSAv8 */ 1583 env->pmsav8.rbar[M_REG_NS] = g_new0(uint32_t, nr); 1584 env->pmsav8.rlar[M_REG_NS] = g_new0(uint32_t, nr); 1585 if (arm_feature(env, ARM_FEATURE_M_SECURITY)) { 1586 env->pmsav8.rbar[M_REG_S] = g_new0(uint32_t, nr); 1587 env->pmsav8.rlar[M_REG_S] = g_new0(uint32_t, nr); 1588 } 1589 } else { 1590 env->pmsav7.drbar = g_new0(uint32_t, nr); 1591 env->pmsav7.drsr = g_new0(uint32_t, nr); 1592 env->pmsav7.dracr = g_new0(uint32_t, nr); 1593 } 1594 } 1595 } 1596 1597 if (arm_feature(env, ARM_FEATURE_M_SECURITY)) { 1598 uint32_t nr = cpu->sau_sregion; 1599 1600 if (nr > 0xff) { 1601 error_setg(errp, "v8M SAU #regions invalid %" PRIu32, nr); 1602 return; 1603 } 1604 1605 if (nr) { 1606 env->sau.rbar = g_new0(uint32_t, nr); 1607 env->sau.rlar = g_new0(uint32_t, nr); 1608 } 1609 } 1610 1611 if (arm_feature(env, ARM_FEATURE_EL3)) { 1612 set_feature(env, ARM_FEATURE_VBAR); 1613 } 1614 1615 register_cp_regs_for_features(cpu); 1616 arm_cpu_register_gdb_regs_for_features(cpu); 1617 1618 init_cpreg_list(cpu); 1619 1620 #ifndef CONFIG_USER_ONLY 1621 MachineState *ms = MACHINE(qdev_get_machine()); 1622 unsigned int smp_cpus = ms->smp.cpus; 1623 1624 if (cpu->has_el3 || arm_feature(env, ARM_FEATURE_M_SECURITY)) { 1625 cs->num_ases = 2; 1626 1627 if (!cpu->secure_memory) { 1628 cpu->secure_memory = cs->memory; 1629 } 1630 cpu_address_space_init(cs, ARMASIdx_S, "cpu-secure-memory", 1631 cpu->secure_memory); 1632 } else { 1633 cs->num_ases = 1; 1634 } 1635 cpu_address_space_init(cs, ARMASIdx_NS, "cpu-memory", cs->memory); 1636 1637 /* No core_count specified, default to smp_cpus. */ 1638 if (cpu->core_count == -1) { 1639 cpu->core_count = smp_cpus; 1640 } 1641 #endif 1642 1643 qemu_init_vcpu(cs); 1644 cpu_reset(cs); 1645 1646 acc->parent_realize(dev, errp); 1647 } 1648 1649 static ObjectClass *arm_cpu_class_by_name(const char *cpu_model) 1650 { 1651 ObjectClass *oc; 1652 char *typename; 1653 char **cpuname; 1654 const char *cpunamestr; 1655 1656 cpuname = g_strsplit(cpu_model, ",", 1); 1657 cpunamestr = cpuname[0]; 1658 #ifdef CONFIG_USER_ONLY 1659 /* For backwards compatibility usermode emulation allows "-cpu any", 1660 * which has the same semantics as "-cpu max". 1661 */ 1662 if (!strcmp(cpunamestr, "any")) { 1663 cpunamestr = "max"; 1664 } 1665 #endif 1666 typename = g_strdup_printf(ARM_CPU_TYPE_NAME("%s"), cpunamestr); 1667 oc = object_class_by_name(typename); 1668 g_strfreev(cpuname); 1669 g_free(typename); 1670 if (!oc || !object_class_dynamic_cast(oc, TYPE_ARM_CPU) || 1671 object_class_is_abstract(oc)) { 1672 return NULL; 1673 } 1674 return oc; 1675 } 1676 1677 /* CPU models. These are not needed for the AArch64 linux-user build. */ 1678 #if !defined(CONFIG_USER_ONLY) || !defined(TARGET_AARCH64) 1679 1680 static void arm926_initfn(Object *obj) 1681 { 1682 ARMCPU *cpu = ARM_CPU(obj); 1683 1684 cpu->dtb_compatible = "arm,arm926"; 1685 set_feature(&cpu->env, ARM_FEATURE_V5); 1686 set_feature(&cpu->env, ARM_FEATURE_VFP); 1687 set_feature(&cpu->env, ARM_FEATURE_DUMMY_C15_REGS); 1688 set_feature(&cpu->env, ARM_FEATURE_CACHE_TEST_CLEAN); 1689 cpu->midr = 0x41069265; 1690 cpu->reset_fpsid = 0x41011090; 1691 cpu->ctr = 0x1dd20d2; 1692 cpu->reset_sctlr = 0x00090078; 1693 1694 /* 1695 * ARMv5 does not have the ID_ISAR registers, but we can still 1696 * set the field to indicate Jazelle support within QEMU. 1697 */ 1698 cpu->isar.id_isar1 = FIELD_DP32(cpu->isar.id_isar1, ID_ISAR1, JAZELLE, 1); 1699 /* 1700 * Similarly, we need to set MVFR0 fields to enable double precision 1701 * and short vector support even though ARMv5 doesn't have this register. 1702 */ 1703 cpu->isar.mvfr0 = FIELD_DP32(cpu->isar.mvfr0, MVFR0, FPSHVEC, 1); 1704 cpu->isar.mvfr0 = FIELD_DP32(cpu->isar.mvfr0, MVFR0, FPDP, 1); 1705 } 1706 1707 static void arm946_initfn(Object *obj) 1708 { 1709 ARMCPU *cpu = ARM_CPU(obj); 1710 1711 cpu->dtb_compatible = "arm,arm946"; 1712 set_feature(&cpu->env, ARM_FEATURE_V5); 1713 set_feature(&cpu->env, ARM_FEATURE_PMSA); 1714 set_feature(&cpu->env, ARM_FEATURE_DUMMY_C15_REGS); 1715 cpu->midr = 0x41059461; 1716 cpu->ctr = 0x0f004006; 1717 cpu->reset_sctlr = 0x00000078; 1718 } 1719 1720 static void arm1026_initfn(Object *obj) 1721 { 1722 ARMCPU *cpu = ARM_CPU(obj); 1723 1724 cpu->dtb_compatible = "arm,arm1026"; 1725 set_feature(&cpu->env, ARM_FEATURE_V5); 1726 set_feature(&cpu->env, ARM_FEATURE_VFP); 1727 set_feature(&cpu->env, ARM_FEATURE_AUXCR); 1728 set_feature(&cpu->env, ARM_FEATURE_DUMMY_C15_REGS); 1729 set_feature(&cpu->env, ARM_FEATURE_CACHE_TEST_CLEAN); 1730 cpu->midr = 0x4106a262; 1731 cpu->reset_fpsid = 0x410110a0; 1732 cpu->ctr = 0x1dd20d2; 1733 cpu->reset_sctlr = 0x00090078; 1734 cpu->reset_auxcr = 1; 1735 1736 /* 1737 * ARMv5 does not have the ID_ISAR registers, but we can still 1738 * set the field to indicate Jazelle support within QEMU. 1739 */ 1740 cpu->isar.id_isar1 = FIELD_DP32(cpu->isar.id_isar1, ID_ISAR1, JAZELLE, 1); 1741 /* 1742 * Similarly, we need to set MVFR0 fields to enable double precision 1743 * and short vector support even though ARMv5 doesn't have this register. 1744 */ 1745 cpu->isar.mvfr0 = FIELD_DP32(cpu->isar.mvfr0, MVFR0, FPSHVEC, 1); 1746 cpu->isar.mvfr0 = FIELD_DP32(cpu->isar.mvfr0, MVFR0, FPDP, 1); 1747 1748 { 1749 /* The 1026 had an IFAR at c6,c0,0,1 rather than the ARMv6 c6,c0,0,2 */ 1750 ARMCPRegInfo ifar = { 1751 .name = "IFAR", .cp = 15, .crn = 6, .crm = 0, .opc1 = 0, .opc2 = 1, 1752 .access = PL1_RW, 1753 .fieldoffset = offsetof(CPUARMState, cp15.ifar_ns), 1754 .resetvalue = 0 1755 }; 1756 define_one_arm_cp_reg(cpu, &ifar); 1757 } 1758 } 1759 1760 static void arm1136_r2_initfn(Object *obj) 1761 { 1762 ARMCPU *cpu = ARM_CPU(obj); 1763 /* What qemu calls "arm1136_r2" is actually the 1136 r0p2, ie an 1764 * older core than plain "arm1136". In particular this does not 1765 * have the v6K features. 1766 * These ID register values are correct for 1136 but may be wrong 1767 * for 1136_r2 (in particular r0p2 does not actually implement most 1768 * of the ID registers). 1769 */ 1770 1771 cpu->dtb_compatible = "arm,arm1136"; 1772 set_feature(&cpu->env, ARM_FEATURE_V6); 1773 set_feature(&cpu->env, ARM_FEATURE_VFP); 1774 set_feature(&cpu->env, ARM_FEATURE_DUMMY_C15_REGS); 1775 set_feature(&cpu->env, ARM_FEATURE_CACHE_DIRTY_REG); 1776 set_feature(&cpu->env, ARM_FEATURE_CACHE_BLOCK_OPS); 1777 cpu->midr = 0x4107b362; 1778 cpu->reset_fpsid = 0x410120b4; 1779 cpu->isar.mvfr0 = 0x11111111; 1780 cpu->isar.mvfr1 = 0x00000000; 1781 cpu->ctr = 0x1dd20d2; 1782 cpu->reset_sctlr = 0x00050078; 1783 cpu->id_pfr0 = 0x111; 1784 cpu->id_pfr1 = 0x1; 1785 cpu->id_dfr0 = 0x2; 1786 cpu->id_afr0 = 0x3; 1787 cpu->id_mmfr0 = 0x01130003; 1788 cpu->id_mmfr1 = 0x10030302; 1789 cpu->id_mmfr2 = 0x01222110; 1790 cpu->isar.id_isar0 = 0x00140011; 1791 cpu->isar.id_isar1 = 0x12002111; 1792 cpu->isar.id_isar2 = 0x11231111; 1793 cpu->isar.id_isar3 = 0x01102131; 1794 cpu->isar.id_isar4 = 0x141; 1795 cpu->reset_auxcr = 7; 1796 } 1797 1798 static void arm1136_initfn(Object *obj) 1799 { 1800 ARMCPU *cpu = ARM_CPU(obj); 1801 1802 cpu->dtb_compatible = "arm,arm1136"; 1803 set_feature(&cpu->env, ARM_FEATURE_V6K); 1804 set_feature(&cpu->env, ARM_FEATURE_V6); 1805 set_feature(&cpu->env, ARM_FEATURE_VFP); 1806 set_feature(&cpu->env, ARM_FEATURE_DUMMY_C15_REGS); 1807 set_feature(&cpu->env, ARM_FEATURE_CACHE_DIRTY_REG); 1808 set_feature(&cpu->env, ARM_FEATURE_CACHE_BLOCK_OPS); 1809 cpu->midr = 0x4117b363; 1810 cpu->reset_fpsid = 0x410120b4; 1811 cpu->isar.mvfr0 = 0x11111111; 1812 cpu->isar.mvfr1 = 0x00000000; 1813 cpu->ctr = 0x1dd20d2; 1814 cpu->reset_sctlr = 0x00050078; 1815 cpu->id_pfr0 = 0x111; 1816 cpu->id_pfr1 = 0x1; 1817 cpu->id_dfr0 = 0x2; 1818 cpu->id_afr0 = 0x3; 1819 cpu->id_mmfr0 = 0x01130003; 1820 cpu->id_mmfr1 = 0x10030302; 1821 cpu->id_mmfr2 = 0x01222110; 1822 cpu->isar.id_isar0 = 0x00140011; 1823 cpu->isar.id_isar1 = 0x12002111; 1824 cpu->isar.id_isar2 = 0x11231111; 1825 cpu->isar.id_isar3 = 0x01102131; 1826 cpu->isar.id_isar4 = 0x141; 1827 cpu->reset_auxcr = 7; 1828 } 1829 1830 static void arm1176_initfn(Object *obj) 1831 { 1832 ARMCPU *cpu = ARM_CPU(obj); 1833 1834 cpu->dtb_compatible = "arm,arm1176"; 1835 set_feature(&cpu->env, ARM_FEATURE_V6K); 1836 set_feature(&cpu->env, ARM_FEATURE_VFP); 1837 set_feature(&cpu->env, ARM_FEATURE_VAPA); 1838 set_feature(&cpu->env, ARM_FEATURE_DUMMY_C15_REGS); 1839 set_feature(&cpu->env, ARM_FEATURE_CACHE_DIRTY_REG); 1840 set_feature(&cpu->env, ARM_FEATURE_CACHE_BLOCK_OPS); 1841 set_feature(&cpu->env, ARM_FEATURE_EL3); 1842 cpu->midr = 0x410fb767; 1843 cpu->reset_fpsid = 0x410120b5; 1844 cpu->isar.mvfr0 = 0x11111111; 1845 cpu->isar.mvfr1 = 0x00000000; 1846 cpu->ctr = 0x1dd20d2; 1847 cpu->reset_sctlr = 0x00050078; 1848 cpu->id_pfr0 = 0x111; 1849 cpu->id_pfr1 = 0x11; 1850 cpu->id_dfr0 = 0x33; 1851 cpu->id_afr0 = 0; 1852 cpu->id_mmfr0 = 0x01130003; 1853 cpu->id_mmfr1 = 0x10030302; 1854 cpu->id_mmfr2 = 0x01222100; 1855 cpu->isar.id_isar0 = 0x0140011; 1856 cpu->isar.id_isar1 = 0x12002111; 1857 cpu->isar.id_isar2 = 0x11231121; 1858 cpu->isar.id_isar3 = 0x01102131; 1859 cpu->isar.id_isar4 = 0x01141; 1860 cpu->reset_auxcr = 7; 1861 } 1862 1863 static void arm11mpcore_initfn(Object *obj) 1864 { 1865 ARMCPU *cpu = ARM_CPU(obj); 1866 1867 cpu->dtb_compatible = "arm,arm11mpcore"; 1868 set_feature(&cpu->env, ARM_FEATURE_V6K); 1869 set_feature(&cpu->env, ARM_FEATURE_VFP); 1870 set_feature(&cpu->env, ARM_FEATURE_VAPA); 1871 set_feature(&cpu->env, ARM_FEATURE_MPIDR); 1872 set_feature(&cpu->env, ARM_FEATURE_DUMMY_C15_REGS); 1873 cpu->midr = 0x410fb022; 1874 cpu->reset_fpsid = 0x410120b4; 1875 cpu->isar.mvfr0 = 0x11111111; 1876 cpu->isar.mvfr1 = 0x00000000; 1877 cpu->ctr = 0x1d192992; /* 32K icache 32K dcache */ 1878 cpu->id_pfr0 = 0x111; 1879 cpu->id_pfr1 = 0x1; 1880 cpu->id_dfr0 = 0; 1881 cpu->id_afr0 = 0x2; 1882 cpu->id_mmfr0 = 0x01100103; 1883 cpu->id_mmfr1 = 0x10020302; 1884 cpu->id_mmfr2 = 0x01222000; 1885 cpu->isar.id_isar0 = 0x00100011; 1886 cpu->isar.id_isar1 = 0x12002111; 1887 cpu->isar.id_isar2 = 0x11221011; 1888 cpu->isar.id_isar3 = 0x01102131; 1889 cpu->isar.id_isar4 = 0x141; 1890 cpu->reset_auxcr = 1; 1891 } 1892 1893 static void cortex_m0_initfn(Object *obj) 1894 { 1895 ARMCPU *cpu = ARM_CPU(obj); 1896 set_feature(&cpu->env, ARM_FEATURE_V6); 1897 set_feature(&cpu->env, ARM_FEATURE_M); 1898 1899 cpu->midr = 0x410cc200; 1900 } 1901 1902 static void cortex_m3_initfn(Object *obj) 1903 { 1904 ARMCPU *cpu = ARM_CPU(obj); 1905 set_feature(&cpu->env, ARM_FEATURE_V7); 1906 set_feature(&cpu->env, ARM_FEATURE_M); 1907 set_feature(&cpu->env, ARM_FEATURE_M_MAIN); 1908 cpu->midr = 0x410fc231; 1909 cpu->pmsav7_dregion = 8; 1910 cpu->id_pfr0 = 0x00000030; 1911 cpu->id_pfr1 = 0x00000200; 1912 cpu->id_dfr0 = 0x00100000; 1913 cpu->id_afr0 = 0x00000000; 1914 cpu->id_mmfr0 = 0x00000030; 1915 cpu->id_mmfr1 = 0x00000000; 1916 cpu->id_mmfr2 = 0x00000000; 1917 cpu->id_mmfr3 = 0x00000000; 1918 cpu->isar.id_isar0 = 0x01141110; 1919 cpu->isar.id_isar1 = 0x02111000; 1920 cpu->isar.id_isar2 = 0x21112231; 1921 cpu->isar.id_isar3 = 0x01111110; 1922 cpu->isar.id_isar4 = 0x01310102; 1923 cpu->isar.id_isar5 = 0x00000000; 1924 cpu->isar.id_isar6 = 0x00000000; 1925 } 1926 1927 static void cortex_m4_initfn(Object *obj) 1928 { 1929 ARMCPU *cpu = ARM_CPU(obj); 1930 1931 set_feature(&cpu->env, ARM_FEATURE_V7); 1932 set_feature(&cpu->env, ARM_FEATURE_M); 1933 set_feature(&cpu->env, ARM_FEATURE_M_MAIN); 1934 set_feature(&cpu->env, ARM_FEATURE_THUMB_DSP); 1935 set_feature(&cpu->env, ARM_FEATURE_VFP4); 1936 cpu->midr = 0x410fc240; /* r0p0 */ 1937 cpu->pmsav7_dregion = 8; 1938 cpu->isar.mvfr0 = 0x10110021; 1939 cpu->isar.mvfr1 = 0x11000011; 1940 cpu->isar.mvfr2 = 0x00000000; 1941 cpu->id_pfr0 = 0x00000030; 1942 cpu->id_pfr1 = 0x00000200; 1943 cpu->id_dfr0 = 0x00100000; 1944 cpu->id_afr0 = 0x00000000; 1945 cpu->id_mmfr0 = 0x00000030; 1946 cpu->id_mmfr1 = 0x00000000; 1947 cpu->id_mmfr2 = 0x00000000; 1948 cpu->id_mmfr3 = 0x00000000; 1949 cpu->isar.id_isar0 = 0x01141110; 1950 cpu->isar.id_isar1 = 0x02111000; 1951 cpu->isar.id_isar2 = 0x21112231; 1952 cpu->isar.id_isar3 = 0x01111110; 1953 cpu->isar.id_isar4 = 0x01310102; 1954 cpu->isar.id_isar5 = 0x00000000; 1955 cpu->isar.id_isar6 = 0x00000000; 1956 } 1957 1958 static void cortex_m33_initfn(Object *obj) 1959 { 1960 ARMCPU *cpu = ARM_CPU(obj); 1961 1962 set_feature(&cpu->env, ARM_FEATURE_V8); 1963 set_feature(&cpu->env, ARM_FEATURE_M); 1964 set_feature(&cpu->env, ARM_FEATURE_M_MAIN); 1965 set_feature(&cpu->env, ARM_FEATURE_M_SECURITY); 1966 set_feature(&cpu->env, ARM_FEATURE_THUMB_DSP); 1967 set_feature(&cpu->env, ARM_FEATURE_VFP4); 1968 cpu->midr = 0x410fd213; /* r0p3 */ 1969 cpu->pmsav7_dregion = 16; 1970 cpu->sau_sregion = 8; 1971 cpu->isar.mvfr0 = 0x10110021; 1972 cpu->isar.mvfr1 = 0x11000011; 1973 cpu->isar.mvfr2 = 0x00000040; 1974 cpu->id_pfr0 = 0x00000030; 1975 cpu->id_pfr1 = 0x00000210; 1976 cpu->id_dfr0 = 0x00200000; 1977 cpu->id_afr0 = 0x00000000; 1978 cpu->id_mmfr0 = 0x00101F40; 1979 cpu->id_mmfr1 = 0x00000000; 1980 cpu->id_mmfr2 = 0x01000000; 1981 cpu->id_mmfr3 = 0x00000000; 1982 cpu->isar.id_isar0 = 0x01101110; 1983 cpu->isar.id_isar1 = 0x02212000; 1984 cpu->isar.id_isar2 = 0x20232232; 1985 cpu->isar.id_isar3 = 0x01111131; 1986 cpu->isar.id_isar4 = 0x01310132; 1987 cpu->isar.id_isar5 = 0x00000000; 1988 cpu->isar.id_isar6 = 0x00000000; 1989 cpu->clidr = 0x00000000; 1990 cpu->ctr = 0x8000c000; 1991 } 1992 1993 static void arm_v7m_class_init(ObjectClass *oc, void *data) 1994 { 1995 ARMCPUClass *acc = ARM_CPU_CLASS(oc); 1996 CPUClass *cc = CPU_CLASS(oc); 1997 1998 acc->info = data; 1999 #ifndef CONFIG_USER_ONLY 2000 cc->do_interrupt = arm_v7m_cpu_do_interrupt; 2001 #endif 2002 2003 cc->cpu_exec_interrupt = arm_v7m_cpu_exec_interrupt; 2004 } 2005 2006 static const ARMCPRegInfo cortexr5_cp_reginfo[] = { 2007 /* Dummy the TCM region regs for the moment */ 2008 { .name = "ATCM", .cp = 15, .opc1 = 0, .crn = 9, .crm = 1, .opc2 = 0, 2009 .access = PL1_RW, .type = ARM_CP_CONST }, 2010 { .name = "BTCM", .cp = 15, .opc1 = 0, .crn = 9, .crm = 1, .opc2 = 1, 2011 .access = PL1_RW, .type = ARM_CP_CONST }, 2012 { .name = "DCACHE_INVAL", .cp = 15, .opc1 = 0, .crn = 15, .crm = 5, 2013 .opc2 = 0, .access = PL1_W, .type = ARM_CP_NOP }, 2014 REGINFO_SENTINEL 2015 }; 2016 2017 static void cortex_r5_initfn(Object *obj) 2018 { 2019 ARMCPU *cpu = ARM_CPU(obj); 2020 2021 set_feature(&cpu->env, ARM_FEATURE_V7); 2022 set_feature(&cpu->env, ARM_FEATURE_V7MP); 2023 set_feature(&cpu->env, ARM_FEATURE_PMSA); 2024 cpu->midr = 0x411fc153; /* r1p3 */ 2025 cpu->id_pfr0 = 0x0131; 2026 cpu->id_pfr1 = 0x001; 2027 cpu->id_dfr0 = 0x010400; 2028 cpu->id_afr0 = 0x0; 2029 cpu->id_mmfr0 = 0x0210030; 2030 cpu->id_mmfr1 = 0x00000000; 2031 cpu->id_mmfr2 = 0x01200000; 2032 cpu->id_mmfr3 = 0x0211; 2033 cpu->isar.id_isar0 = 0x02101111; 2034 cpu->isar.id_isar1 = 0x13112111; 2035 cpu->isar.id_isar2 = 0x21232141; 2036 cpu->isar.id_isar3 = 0x01112131; 2037 cpu->isar.id_isar4 = 0x0010142; 2038 cpu->isar.id_isar5 = 0x0; 2039 cpu->isar.id_isar6 = 0x0; 2040 cpu->mp_is_up = true; 2041 cpu->pmsav7_dregion = 16; 2042 define_arm_cp_regs(cpu, cortexr5_cp_reginfo); 2043 } 2044 2045 static void cortex_r5f_initfn(Object *obj) 2046 { 2047 ARMCPU *cpu = ARM_CPU(obj); 2048 2049 cortex_r5_initfn(obj); 2050 set_feature(&cpu->env, ARM_FEATURE_VFP3); 2051 cpu->isar.mvfr0 = 0x10110221; 2052 cpu->isar.mvfr1 = 0x00000011; 2053 } 2054 2055 static const ARMCPRegInfo cortexa8_cp_reginfo[] = { 2056 { .name = "L2LOCKDOWN", .cp = 15, .crn = 9, .crm = 0, .opc1 = 1, .opc2 = 0, 2057 .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0 }, 2058 { .name = "L2AUXCR", .cp = 15, .crn = 9, .crm = 0, .opc1 = 1, .opc2 = 2, 2059 .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0 }, 2060 REGINFO_SENTINEL 2061 }; 2062 2063 static void cortex_a8_initfn(Object *obj) 2064 { 2065 ARMCPU *cpu = ARM_CPU(obj); 2066 2067 cpu->dtb_compatible = "arm,cortex-a8"; 2068 set_feature(&cpu->env, ARM_FEATURE_V7); 2069 set_feature(&cpu->env, ARM_FEATURE_VFP3); 2070 set_feature(&cpu->env, ARM_FEATURE_NEON); 2071 set_feature(&cpu->env, ARM_FEATURE_THUMB2EE); 2072 set_feature(&cpu->env, ARM_FEATURE_DUMMY_C15_REGS); 2073 set_feature(&cpu->env, ARM_FEATURE_EL3); 2074 cpu->midr = 0x410fc080; 2075 cpu->reset_fpsid = 0x410330c0; 2076 cpu->isar.mvfr0 = 0x11110222; 2077 cpu->isar.mvfr1 = 0x00011111; 2078 cpu->ctr = 0x82048004; 2079 cpu->reset_sctlr = 0x00c50078; 2080 cpu->id_pfr0 = 0x1031; 2081 cpu->id_pfr1 = 0x11; 2082 cpu->id_dfr0 = 0x400; 2083 cpu->id_afr0 = 0; 2084 cpu->id_mmfr0 = 0x31100003; 2085 cpu->id_mmfr1 = 0x20000000; 2086 cpu->id_mmfr2 = 0x01202000; 2087 cpu->id_mmfr3 = 0x11; 2088 cpu->isar.id_isar0 = 0x00101111; 2089 cpu->isar.id_isar1 = 0x12112111; 2090 cpu->isar.id_isar2 = 0x21232031; 2091 cpu->isar.id_isar3 = 0x11112131; 2092 cpu->isar.id_isar4 = 0x00111142; 2093 cpu->dbgdidr = 0x15141000; 2094 cpu->clidr = (1 << 27) | (2 << 24) | 3; 2095 cpu->ccsidr[0] = 0xe007e01a; /* 16k L1 dcache. */ 2096 cpu->ccsidr[1] = 0x2007e01a; /* 16k L1 icache. */ 2097 cpu->ccsidr[2] = 0xf0000000; /* No L2 icache. */ 2098 cpu->reset_auxcr = 2; 2099 define_arm_cp_regs(cpu, cortexa8_cp_reginfo); 2100 } 2101 2102 static const ARMCPRegInfo cortexa9_cp_reginfo[] = { 2103 /* power_control should be set to maximum latency. Again, 2104 * default to 0 and set by private hook 2105 */ 2106 { .name = "A9_PWRCTL", .cp = 15, .crn = 15, .crm = 0, .opc1 = 0, .opc2 = 0, 2107 .access = PL1_RW, .resetvalue = 0, 2108 .fieldoffset = offsetof(CPUARMState, cp15.c15_power_control) }, 2109 { .name = "A9_DIAG", .cp = 15, .crn = 15, .crm = 0, .opc1 = 0, .opc2 = 1, 2110 .access = PL1_RW, .resetvalue = 0, 2111 .fieldoffset = offsetof(CPUARMState, cp15.c15_diagnostic) }, 2112 { .name = "A9_PWRDIAG", .cp = 15, .crn = 15, .crm = 0, .opc1 = 0, .opc2 = 2, 2113 .access = PL1_RW, .resetvalue = 0, 2114 .fieldoffset = offsetof(CPUARMState, cp15.c15_power_diagnostic) }, 2115 { .name = "NEONBUSY", .cp = 15, .crn = 15, .crm = 1, .opc1 = 0, .opc2 = 0, 2116 .access = PL1_RW, .resetvalue = 0, .type = ARM_CP_CONST }, 2117 /* TLB lockdown control */ 2118 { .name = "TLB_LOCKR", .cp = 15, .crn = 15, .crm = 4, .opc1 = 5, .opc2 = 2, 2119 .access = PL1_W, .resetvalue = 0, .type = ARM_CP_NOP }, 2120 { .name = "TLB_LOCKW", .cp = 15, .crn = 15, .crm = 4, .opc1 = 5, .opc2 = 4, 2121 .access = PL1_W, .resetvalue = 0, .type = ARM_CP_NOP }, 2122 { .name = "TLB_VA", .cp = 15, .crn = 15, .crm = 5, .opc1 = 5, .opc2 = 2, 2123 .access = PL1_RW, .resetvalue = 0, .type = ARM_CP_CONST }, 2124 { .name = "TLB_PA", .cp = 15, .crn = 15, .crm = 6, .opc1 = 5, .opc2 = 2, 2125 .access = PL1_RW, .resetvalue = 0, .type = ARM_CP_CONST }, 2126 { .name = "TLB_ATTR", .cp = 15, .crn = 15, .crm = 7, .opc1 = 5, .opc2 = 2, 2127 .access = PL1_RW, .resetvalue = 0, .type = ARM_CP_CONST }, 2128 REGINFO_SENTINEL 2129 }; 2130 2131 static void cortex_a9_initfn(Object *obj) 2132 { 2133 ARMCPU *cpu = ARM_CPU(obj); 2134 2135 cpu->dtb_compatible = "arm,cortex-a9"; 2136 set_feature(&cpu->env, ARM_FEATURE_V7); 2137 set_feature(&cpu->env, ARM_FEATURE_VFP3); 2138 set_feature(&cpu->env, ARM_FEATURE_NEON); 2139 set_feature(&cpu->env, ARM_FEATURE_THUMB2EE); 2140 set_feature(&cpu->env, ARM_FEATURE_EL3); 2141 /* Note that A9 supports the MP extensions even for 2142 * A9UP and single-core A9MP (which are both different 2143 * and valid configurations; we don't model A9UP). 2144 */ 2145 set_feature(&cpu->env, ARM_FEATURE_V7MP); 2146 set_feature(&cpu->env, ARM_FEATURE_CBAR); 2147 cpu->midr = 0x410fc090; 2148 cpu->reset_fpsid = 0x41033090; 2149 cpu->isar.mvfr0 = 0x11110222; 2150 cpu->isar.mvfr1 = 0x01111111; 2151 cpu->ctr = 0x80038003; 2152 cpu->reset_sctlr = 0x00c50078; 2153 cpu->id_pfr0 = 0x1031; 2154 cpu->id_pfr1 = 0x11; 2155 cpu->id_dfr0 = 0x000; 2156 cpu->id_afr0 = 0; 2157 cpu->id_mmfr0 = 0x00100103; 2158 cpu->id_mmfr1 = 0x20000000; 2159 cpu->id_mmfr2 = 0x01230000; 2160 cpu->id_mmfr3 = 0x00002111; 2161 cpu->isar.id_isar0 = 0x00101111; 2162 cpu->isar.id_isar1 = 0x13112111; 2163 cpu->isar.id_isar2 = 0x21232041; 2164 cpu->isar.id_isar3 = 0x11112131; 2165 cpu->isar.id_isar4 = 0x00111142; 2166 cpu->dbgdidr = 0x35141000; 2167 cpu->clidr = (1 << 27) | (1 << 24) | 3; 2168 cpu->ccsidr[0] = 0xe00fe019; /* 16k L1 dcache. */ 2169 cpu->ccsidr[1] = 0x200fe019; /* 16k L1 icache. */ 2170 define_arm_cp_regs(cpu, cortexa9_cp_reginfo); 2171 } 2172 2173 #ifndef CONFIG_USER_ONLY 2174 static uint64_t a15_l2ctlr_read(CPUARMState *env, const ARMCPRegInfo *ri) 2175 { 2176 MachineState *ms = MACHINE(qdev_get_machine()); 2177 2178 /* Linux wants the number of processors from here. 2179 * Might as well set the interrupt-controller bit too. 2180 */ 2181 return ((ms->smp.cpus - 1) << 24) | (1 << 23); 2182 } 2183 #endif 2184 2185 static const ARMCPRegInfo cortexa15_cp_reginfo[] = { 2186 #ifndef CONFIG_USER_ONLY 2187 { .name = "L2CTLR", .cp = 15, .crn = 9, .crm = 0, .opc1 = 1, .opc2 = 2, 2188 .access = PL1_RW, .resetvalue = 0, .readfn = a15_l2ctlr_read, 2189 .writefn = arm_cp_write_ignore, }, 2190 #endif 2191 { .name = "L2ECTLR", .cp = 15, .crn = 9, .crm = 0, .opc1 = 1, .opc2 = 3, 2192 .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0 }, 2193 REGINFO_SENTINEL 2194 }; 2195 2196 static void cortex_a7_initfn(Object *obj) 2197 { 2198 ARMCPU *cpu = ARM_CPU(obj); 2199 2200 cpu->dtb_compatible = "arm,cortex-a7"; 2201 set_feature(&cpu->env, ARM_FEATURE_V7VE); 2202 set_feature(&cpu->env, ARM_FEATURE_VFP4); 2203 set_feature(&cpu->env, ARM_FEATURE_NEON); 2204 set_feature(&cpu->env, ARM_FEATURE_THUMB2EE); 2205 set_feature(&cpu->env, ARM_FEATURE_GENERIC_TIMER); 2206 set_feature(&cpu->env, ARM_FEATURE_DUMMY_C15_REGS); 2207 set_feature(&cpu->env, ARM_FEATURE_CBAR_RO); 2208 set_feature(&cpu->env, ARM_FEATURE_EL2); 2209 set_feature(&cpu->env, ARM_FEATURE_EL3); 2210 set_feature(&cpu->env, ARM_FEATURE_PMU); 2211 cpu->kvm_target = QEMU_KVM_ARM_TARGET_CORTEX_A7; 2212 cpu->midr = 0x410fc075; 2213 cpu->reset_fpsid = 0x41023075; 2214 cpu->isar.mvfr0 = 0x10110222; 2215 cpu->isar.mvfr1 = 0x11111111; 2216 cpu->ctr = 0x84448003; 2217 cpu->reset_sctlr = 0x00c50078; 2218 cpu->id_pfr0 = 0x00001131; 2219 cpu->id_pfr1 = 0x00011011; 2220 cpu->id_dfr0 = 0x02010555; 2221 cpu->id_afr0 = 0x00000000; 2222 cpu->id_mmfr0 = 0x10101105; 2223 cpu->id_mmfr1 = 0x40000000; 2224 cpu->id_mmfr2 = 0x01240000; 2225 cpu->id_mmfr3 = 0x02102211; 2226 /* a7_mpcore_r0p5_trm, page 4-4 gives 0x01101110; but 2227 * table 4-41 gives 0x02101110, which includes the arm div insns. 2228 */ 2229 cpu->isar.id_isar0 = 0x02101110; 2230 cpu->isar.id_isar1 = 0x13112111; 2231 cpu->isar.id_isar2 = 0x21232041; 2232 cpu->isar.id_isar3 = 0x11112131; 2233 cpu->isar.id_isar4 = 0x10011142; 2234 cpu->dbgdidr = 0x3515f005; 2235 cpu->clidr = 0x0a200023; 2236 cpu->ccsidr[0] = 0x701fe00a; /* 32K L1 dcache */ 2237 cpu->ccsidr[1] = 0x201fe00a; /* 32K L1 icache */ 2238 cpu->ccsidr[2] = 0x711fe07a; /* 4096K L2 unified cache */ 2239 define_arm_cp_regs(cpu, cortexa15_cp_reginfo); /* Same as A15 */ 2240 } 2241 2242 static void cortex_a15_initfn(Object *obj) 2243 { 2244 ARMCPU *cpu = ARM_CPU(obj); 2245 2246 cpu->dtb_compatible = "arm,cortex-a15"; 2247 set_feature(&cpu->env, ARM_FEATURE_V7VE); 2248 set_feature(&cpu->env, ARM_FEATURE_VFP4); 2249 set_feature(&cpu->env, ARM_FEATURE_NEON); 2250 set_feature(&cpu->env, ARM_FEATURE_THUMB2EE); 2251 set_feature(&cpu->env, ARM_FEATURE_GENERIC_TIMER); 2252 set_feature(&cpu->env, ARM_FEATURE_DUMMY_C15_REGS); 2253 set_feature(&cpu->env, ARM_FEATURE_CBAR_RO); 2254 set_feature(&cpu->env, ARM_FEATURE_EL2); 2255 set_feature(&cpu->env, ARM_FEATURE_EL3); 2256 set_feature(&cpu->env, ARM_FEATURE_PMU); 2257 cpu->kvm_target = QEMU_KVM_ARM_TARGET_CORTEX_A15; 2258 cpu->midr = 0x412fc0f1; 2259 cpu->reset_fpsid = 0x410430f0; 2260 cpu->isar.mvfr0 = 0x10110222; 2261 cpu->isar.mvfr1 = 0x11111111; 2262 cpu->ctr = 0x8444c004; 2263 cpu->reset_sctlr = 0x00c50078; 2264 cpu->id_pfr0 = 0x00001131; 2265 cpu->id_pfr1 = 0x00011011; 2266 cpu->id_dfr0 = 0x02010555; 2267 cpu->id_afr0 = 0x00000000; 2268 cpu->id_mmfr0 = 0x10201105; 2269 cpu->id_mmfr1 = 0x20000000; 2270 cpu->id_mmfr2 = 0x01240000; 2271 cpu->id_mmfr3 = 0x02102211; 2272 cpu->isar.id_isar0 = 0x02101110; 2273 cpu->isar.id_isar1 = 0x13112111; 2274 cpu->isar.id_isar2 = 0x21232041; 2275 cpu->isar.id_isar3 = 0x11112131; 2276 cpu->isar.id_isar4 = 0x10011142; 2277 cpu->dbgdidr = 0x3515f021; 2278 cpu->clidr = 0x0a200023; 2279 cpu->ccsidr[0] = 0x701fe00a; /* 32K L1 dcache */ 2280 cpu->ccsidr[1] = 0x201fe00a; /* 32K L1 icache */ 2281 cpu->ccsidr[2] = 0x711fe07a; /* 4096K L2 unified cache */ 2282 define_arm_cp_regs(cpu, cortexa15_cp_reginfo); 2283 } 2284 2285 static void ti925t_initfn(Object *obj) 2286 { 2287 ARMCPU *cpu = ARM_CPU(obj); 2288 set_feature(&cpu->env, ARM_FEATURE_V4T); 2289 set_feature(&cpu->env, ARM_FEATURE_OMAPCP); 2290 cpu->midr = ARM_CPUID_TI925T; 2291 cpu->ctr = 0x5109149; 2292 cpu->reset_sctlr = 0x00000070; 2293 } 2294 2295 static void sa1100_initfn(Object *obj) 2296 { 2297 ARMCPU *cpu = ARM_CPU(obj); 2298 2299 cpu->dtb_compatible = "intel,sa1100"; 2300 set_feature(&cpu->env, ARM_FEATURE_STRONGARM); 2301 set_feature(&cpu->env, ARM_FEATURE_DUMMY_C15_REGS); 2302 cpu->midr = 0x4401A11B; 2303 cpu->reset_sctlr = 0x00000070; 2304 } 2305 2306 static void sa1110_initfn(Object *obj) 2307 { 2308 ARMCPU *cpu = ARM_CPU(obj); 2309 set_feature(&cpu->env, ARM_FEATURE_STRONGARM); 2310 set_feature(&cpu->env, ARM_FEATURE_DUMMY_C15_REGS); 2311 cpu->midr = 0x6901B119; 2312 cpu->reset_sctlr = 0x00000070; 2313 } 2314 2315 static void pxa250_initfn(Object *obj) 2316 { 2317 ARMCPU *cpu = ARM_CPU(obj); 2318 2319 cpu->dtb_compatible = "marvell,xscale"; 2320 set_feature(&cpu->env, ARM_FEATURE_V5); 2321 set_feature(&cpu->env, ARM_FEATURE_XSCALE); 2322 cpu->midr = 0x69052100; 2323 cpu->ctr = 0xd172172; 2324 cpu->reset_sctlr = 0x00000078; 2325 } 2326 2327 static void pxa255_initfn(Object *obj) 2328 { 2329 ARMCPU *cpu = ARM_CPU(obj); 2330 2331 cpu->dtb_compatible = "marvell,xscale"; 2332 set_feature(&cpu->env, ARM_FEATURE_V5); 2333 set_feature(&cpu->env, ARM_FEATURE_XSCALE); 2334 cpu->midr = 0x69052d00; 2335 cpu->ctr = 0xd172172; 2336 cpu->reset_sctlr = 0x00000078; 2337 } 2338 2339 static void pxa260_initfn(Object *obj) 2340 { 2341 ARMCPU *cpu = ARM_CPU(obj); 2342 2343 cpu->dtb_compatible = "marvell,xscale"; 2344 set_feature(&cpu->env, ARM_FEATURE_V5); 2345 set_feature(&cpu->env, ARM_FEATURE_XSCALE); 2346 cpu->midr = 0x69052903; 2347 cpu->ctr = 0xd172172; 2348 cpu->reset_sctlr = 0x00000078; 2349 } 2350 2351 static void pxa261_initfn(Object *obj) 2352 { 2353 ARMCPU *cpu = ARM_CPU(obj); 2354 2355 cpu->dtb_compatible = "marvell,xscale"; 2356 set_feature(&cpu->env, ARM_FEATURE_V5); 2357 set_feature(&cpu->env, ARM_FEATURE_XSCALE); 2358 cpu->midr = 0x69052d05; 2359 cpu->ctr = 0xd172172; 2360 cpu->reset_sctlr = 0x00000078; 2361 } 2362 2363 static void pxa262_initfn(Object *obj) 2364 { 2365 ARMCPU *cpu = ARM_CPU(obj); 2366 2367 cpu->dtb_compatible = "marvell,xscale"; 2368 set_feature(&cpu->env, ARM_FEATURE_V5); 2369 set_feature(&cpu->env, ARM_FEATURE_XSCALE); 2370 cpu->midr = 0x69052d06; 2371 cpu->ctr = 0xd172172; 2372 cpu->reset_sctlr = 0x00000078; 2373 } 2374 2375 static void pxa270a0_initfn(Object *obj) 2376 { 2377 ARMCPU *cpu = ARM_CPU(obj); 2378 2379 cpu->dtb_compatible = "marvell,xscale"; 2380 set_feature(&cpu->env, ARM_FEATURE_V5); 2381 set_feature(&cpu->env, ARM_FEATURE_XSCALE); 2382 set_feature(&cpu->env, ARM_FEATURE_IWMMXT); 2383 cpu->midr = 0x69054110; 2384 cpu->ctr = 0xd172172; 2385 cpu->reset_sctlr = 0x00000078; 2386 } 2387 2388 static void pxa270a1_initfn(Object *obj) 2389 { 2390 ARMCPU *cpu = ARM_CPU(obj); 2391 2392 cpu->dtb_compatible = "marvell,xscale"; 2393 set_feature(&cpu->env, ARM_FEATURE_V5); 2394 set_feature(&cpu->env, ARM_FEATURE_XSCALE); 2395 set_feature(&cpu->env, ARM_FEATURE_IWMMXT); 2396 cpu->midr = 0x69054111; 2397 cpu->ctr = 0xd172172; 2398 cpu->reset_sctlr = 0x00000078; 2399 } 2400 2401 static void pxa270b0_initfn(Object *obj) 2402 { 2403 ARMCPU *cpu = ARM_CPU(obj); 2404 2405 cpu->dtb_compatible = "marvell,xscale"; 2406 set_feature(&cpu->env, ARM_FEATURE_V5); 2407 set_feature(&cpu->env, ARM_FEATURE_XSCALE); 2408 set_feature(&cpu->env, ARM_FEATURE_IWMMXT); 2409 cpu->midr = 0x69054112; 2410 cpu->ctr = 0xd172172; 2411 cpu->reset_sctlr = 0x00000078; 2412 } 2413 2414 static void pxa270b1_initfn(Object *obj) 2415 { 2416 ARMCPU *cpu = ARM_CPU(obj); 2417 2418 cpu->dtb_compatible = "marvell,xscale"; 2419 set_feature(&cpu->env, ARM_FEATURE_V5); 2420 set_feature(&cpu->env, ARM_FEATURE_XSCALE); 2421 set_feature(&cpu->env, ARM_FEATURE_IWMMXT); 2422 cpu->midr = 0x69054113; 2423 cpu->ctr = 0xd172172; 2424 cpu->reset_sctlr = 0x00000078; 2425 } 2426 2427 static void pxa270c0_initfn(Object *obj) 2428 { 2429 ARMCPU *cpu = ARM_CPU(obj); 2430 2431 cpu->dtb_compatible = "marvell,xscale"; 2432 set_feature(&cpu->env, ARM_FEATURE_V5); 2433 set_feature(&cpu->env, ARM_FEATURE_XSCALE); 2434 set_feature(&cpu->env, ARM_FEATURE_IWMMXT); 2435 cpu->midr = 0x69054114; 2436 cpu->ctr = 0xd172172; 2437 cpu->reset_sctlr = 0x00000078; 2438 } 2439 2440 static void pxa270c5_initfn(Object *obj) 2441 { 2442 ARMCPU *cpu = ARM_CPU(obj); 2443 2444 cpu->dtb_compatible = "marvell,xscale"; 2445 set_feature(&cpu->env, ARM_FEATURE_V5); 2446 set_feature(&cpu->env, ARM_FEATURE_XSCALE); 2447 set_feature(&cpu->env, ARM_FEATURE_IWMMXT); 2448 cpu->midr = 0x69054117; 2449 cpu->ctr = 0xd172172; 2450 cpu->reset_sctlr = 0x00000078; 2451 } 2452 2453 #ifndef TARGET_AARCH64 2454 /* -cpu max: if KVM is enabled, like -cpu host (best possible with this host); 2455 * otherwise, a CPU with as many features enabled as our emulation supports. 2456 * The version of '-cpu max' for qemu-system-aarch64 is defined in cpu64.c; 2457 * this only needs to handle 32 bits. 2458 */ 2459 static void arm_max_initfn(Object *obj) 2460 { 2461 ARMCPU *cpu = ARM_CPU(obj); 2462 2463 if (kvm_enabled()) { 2464 kvm_arm_set_cpu_features_from_host(cpu); 2465 } else { 2466 cortex_a15_initfn(obj); 2467 2468 /* old-style VFP short-vector support */ 2469 cpu->isar.mvfr0 = FIELD_DP32(cpu->isar.mvfr0, MVFR0, FPSHVEC, 1); 2470 2471 #ifdef CONFIG_USER_ONLY 2472 /* We don't set these in system emulation mode for the moment, 2473 * since we don't correctly set (all of) the ID registers to 2474 * advertise them. 2475 */ 2476 set_feature(&cpu->env, ARM_FEATURE_V8); 2477 { 2478 uint32_t t; 2479 2480 t = cpu->isar.id_isar5; 2481 t = FIELD_DP32(t, ID_ISAR5, AES, 2); 2482 t = FIELD_DP32(t, ID_ISAR5, SHA1, 1); 2483 t = FIELD_DP32(t, ID_ISAR5, SHA2, 1); 2484 t = FIELD_DP32(t, ID_ISAR5, CRC32, 1); 2485 t = FIELD_DP32(t, ID_ISAR5, RDM, 1); 2486 t = FIELD_DP32(t, ID_ISAR5, VCMA, 1); 2487 cpu->isar.id_isar5 = t; 2488 2489 t = cpu->isar.id_isar6; 2490 t = FIELD_DP32(t, ID_ISAR6, JSCVT, 1); 2491 t = FIELD_DP32(t, ID_ISAR6, DP, 1); 2492 t = FIELD_DP32(t, ID_ISAR6, FHM, 1); 2493 t = FIELD_DP32(t, ID_ISAR6, SB, 1); 2494 t = FIELD_DP32(t, ID_ISAR6, SPECRES, 1); 2495 cpu->isar.id_isar6 = t; 2496 2497 t = cpu->isar.mvfr1; 2498 t = FIELD_DP32(t, MVFR1, FPHP, 2); /* v8.0 FP support */ 2499 cpu->isar.mvfr1 = t; 2500 2501 t = cpu->isar.mvfr2; 2502 t = FIELD_DP32(t, MVFR2, SIMDMISC, 3); /* SIMD MaxNum */ 2503 t = FIELD_DP32(t, MVFR2, FPMISC, 4); /* FP MaxNum */ 2504 cpu->isar.mvfr2 = t; 2505 2506 t = cpu->id_mmfr4; 2507 t = FIELD_DP32(t, ID_MMFR4, HPDS, 1); /* AA32HPD */ 2508 cpu->id_mmfr4 = t; 2509 } 2510 #endif 2511 } 2512 } 2513 #endif 2514 2515 #endif /* !defined(CONFIG_USER_ONLY) || !defined(TARGET_AARCH64) */ 2516 2517 struct ARMCPUInfo { 2518 const char *name; 2519 void (*initfn)(Object *obj); 2520 void (*class_init)(ObjectClass *oc, void *data); 2521 }; 2522 2523 static const ARMCPUInfo arm_cpus[] = { 2524 #if !defined(CONFIG_USER_ONLY) || !defined(TARGET_AARCH64) 2525 { .name = "arm926", .initfn = arm926_initfn }, 2526 { .name = "arm946", .initfn = arm946_initfn }, 2527 { .name = "arm1026", .initfn = arm1026_initfn }, 2528 /* What QEMU calls "arm1136-r2" is actually the 1136 r0p2, i.e. an 2529 * older core than plain "arm1136". In particular this does not 2530 * have the v6K features. 2531 */ 2532 { .name = "arm1136-r2", .initfn = arm1136_r2_initfn }, 2533 { .name = "arm1136", .initfn = arm1136_initfn }, 2534 { .name = "arm1176", .initfn = arm1176_initfn }, 2535 { .name = "arm11mpcore", .initfn = arm11mpcore_initfn }, 2536 { .name = "cortex-m0", .initfn = cortex_m0_initfn, 2537 .class_init = arm_v7m_class_init }, 2538 { .name = "cortex-m3", .initfn = cortex_m3_initfn, 2539 .class_init = arm_v7m_class_init }, 2540 { .name = "cortex-m4", .initfn = cortex_m4_initfn, 2541 .class_init = arm_v7m_class_init }, 2542 { .name = "cortex-m33", .initfn = cortex_m33_initfn, 2543 .class_init = arm_v7m_class_init }, 2544 { .name = "cortex-r5", .initfn = cortex_r5_initfn }, 2545 { .name = "cortex-r5f", .initfn = cortex_r5f_initfn }, 2546 { .name = "cortex-a7", .initfn = cortex_a7_initfn }, 2547 { .name = "cortex-a8", .initfn = cortex_a8_initfn }, 2548 { .name = "cortex-a9", .initfn = cortex_a9_initfn }, 2549 { .name = "cortex-a15", .initfn = cortex_a15_initfn }, 2550 { .name = "ti925t", .initfn = ti925t_initfn }, 2551 { .name = "sa1100", .initfn = sa1100_initfn }, 2552 { .name = "sa1110", .initfn = sa1110_initfn }, 2553 { .name = "pxa250", .initfn = pxa250_initfn }, 2554 { .name = "pxa255", .initfn = pxa255_initfn }, 2555 { .name = "pxa260", .initfn = pxa260_initfn }, 2556 { .name = "pxa261", .initfn = pxa261_initfn }, 2557 { .name = "pxa262", .initfn = pxa262_initfn }, 2558 /* "pxa270" is an alias for "pxa270-a0" */ 2559 { .name = "pxa270", .initfn = pxa270a0_initfn }, 2560 { .name = "pxa270-a0", .initfn = pxa270a0_initfn }, 2561 { .name = "pxa270-a1", .initfn = pxa270a1_initfn }, 2562 { .name = "pxa270-b0", .initfn = pxa270b0_initfn }, 2563 { .name = "pxa270-b1", .initfn = pxa270b1_initfn }, 2564 { .name = "pxa270-c0", .initfn = pxa270c0_initfn }, 2565 { .name = "pxa270-c5", .initfn = pxa270c5_initfn }, 2566 #ifndef TARGET_AARCH64 2567 { .name = "max", .initfn = arm_max_initfn }, 2568 #endif 2569 #ifdef CONFIG_USER_ONLY 2570 { .name = "any", .initfn = arm_max_initfn }, 2571 #endif 2572 #endif 2573 { .name = NULL } 2574 }; 2575 2576 static Property arm_cpu_properties[] = { 2577 DEFINE_PROP_BOOL("start-powered-off", ARMCPU, start_powered_off, false), 2578 DEFINE_PROP_UINT32("psci-conduit", ARMCPU, psci_conduit, 0), 2579 DEFINE_PROP_UINT32("midr", ARMCPU, midr, 0), 2580 DEFINE_PROP_UINT64("mp-affinity", ARMCPU, 2581 mp_affinity, ARM64_AFFINITY_INVALID), 2582 DEFINE_PROP_INT32("node-id", ARMCPU, node_id, CPU_UNSET_NUMA_NODE_ID), 2583 DEFINE_PROP_INT32("core-count", ARMCPU, core_count, -1), 2584 DEFINE_PROP_END_OF_LIST() 2585 }; 2586 2587 static gchar *arm_gdb_arch_name(CPUState *cs) 2588 { 2589 ARMCPU *cpu = ARM_CPU(cs); 2590 CPUARMState *env = &cpu->env; 2591 2592 if (arm_feature(env, ARM_FEATURE_IWMMXT)) { 2593 return g_strdup("iwmmxt"); 2594 } 2595 return g_strdup("arm"); 2596 } 2597 2598 static void arm_cpu_class_init(ObjectClass *oc, void *data) 2599 { 2600 ARMCPUClass *acc = ARM_CPU_CLASS(oc); 2601 CPUClass *cc = CPU_CLASS(acc); 2602 DeviceClass *dc = DEVICE_CLASS(oc); 2603 2604 device_class_set_parent_realize(dc, arm_cpu_realizefn, 2605 &acc->parent_realize); 2606 dc->props = arm_cpu_properties; 2607 2608 acc->parent_reset = cc->reset; 2609 cc->reset = arm_cpu_reset; 2610 2611 cc->class_by_name = arm_cpu_class_by_name; 2612 cc->has_work = arm_cpu_has_work; 2613 cc->cpu_exec_interrupt = arm_cpu_exec_interrupt; 2614 cc->dump_state = arm_cpu_dump_state; 2615 cc->set_pc = arm_cpu_set_pc; 2616 cc->synchronize_from_tb = arm_cpu_synchronize_from_tb; 2617 cc->gdb_read_register = arm_cpu_gdb_read_register; 2618 cc->gdb_write_register = arm_cpu_gdb_write_register; 2619 #ifndef CONFIG_USER_ONLY 2620 cc->do_interrupt = arm_cpu_do_interrupt; 2621 cc->get_phys_page_attrs_debug = arm_cpu_get_phys_page_attrs_debug; 2622 cc->asidx_from_attrs = arm_asidx_from_attrs; 2623 cc->vmsd = &vmstate_arm_cpu; 2624 cc->virtio_is_big_endian = arm_cpu_virtio_is_big_endian; 2625 cc->write_elf64_note = arm_cpu_write_elf64_note; 2626 cc->write_elf32_note = arm_cpu_write_elf32_note; 2627 #endif 2628 cc->gdb_num_core_regs = 26; 2629 cc->gdb_core_xml_file = "arm-core.xml"; 2630 cc->gdb_arch_name = arm_gdb_arch_name; 2631 cc->gdb_get_dynamic_xml = arm_gdb_get_dynamic_xml; 2632 cc->gdb_stop_before_watchpoint = true; 2633 cc->disas_set_info = arm_disas_set_info; 2634 #ifdef CONFIG_TCG 2635 cc->tcg_initialize = arm_translate_init; 2636 cc->tlb_fill = arm_cpu_tlb_fill; 2637 cc->debug_excp_handler = arm_debug_excp_handler; 2638 cc->debug_check_watchpoint = arm_debug_check_watchpoint; 2639 #if !defined(CONFIG_USER_ONLY) 2640 cc->do_unaligned_access = arm_cpu_do_unaligned_access; 2641 cc->do_transaction_failed = arm_cpu_do_transaction_failed; 2642 cc->adjust_watchpoint_address = arm_adjust_watchpoint_address; 2643 #endif /* CONFIG_TCG && !CONFIG_USER_ONLY */ 2644 #endif 2645 } 2646 2647 #ifdef CONFIG_KVM 2648 static void arm_host_initfn(Object *obj) 2649 { 2650 ARMCPU *cpu = ARM_CPU(obj); 2651 2652 kvm_arm_set_cpu_features_from_host(cpu); 2653 arm_cpu_post_init(obj); 2654 } 2655 2656 static const TypeInfo host_arm_cpu_type_info = { 2657 .name = TYPE_ARM_HOST_CPU, 2658 #ifdef TARGET_AARCH64 2659 .parent = TYPE_AARCH64_CPU, 2660 #else 2661 .parent = TYPE_ARM_CPU, 2662 #endif 2663 .instance_init = arm_host_initfn, 2664 }; 2665 2666 #endif 2667 2668 static void arm_cpu_instance_init(Object *obj) 2669 { 2670 ARMCPUClass *acc = ARM_CPU_GET_CLASS(obj); 2671 2672 acc->info->initfn(obj); 2673 arm_cpu_post_init(obj); 2674 } 2675 2676 static void cpu_register_class_init(ObjectClass *oc, void *data) 2677 { 2678 ARMCPUClass *acc = ARM_CPU_CLASS(oc); 2679 2680 acc->info = data; 2681 } 2682 2683 static void cpu_register(const ARMCPUInfo *info) 2684 { 2685 TypeInfo type_info = { 2686 .parent = TYPE_ARM_CPU, 2687 .instance_size = sizeof(ARMCPU), 2688 .instance_init = arm_cpu_instance_init, 2689 .class_size = sizeof(ARMCPUClass), 2690 .class_init = info->class_init ?: cpu_register_class_init, 2691 .class_data = (void *)info, 2692 }; 2693 2694 type_info.name = g_strdup_printf("%s-" TYPE_ARM_CPU, info->name); 2695 type_register(&type_info); 2696 g_free((void *)type_info.name); 2697 } 2698 2699 static const TypeInfo arm_cpu_type_info = { 2700 .name = TYPE_ARM_CPU, 2701 .parent = TYPE_CPU, 2702 .instance_size = sizeof(ARMCPU), 2703 .instance_init = arm_cpu_initfn, 2704 .instance_finalize = arm_cpu_finalizefn, 2705 .abstract = true, 2706 .class_size = sizeof(ARMCPUClass), 2707 .class_init = arm_cpu_class_init, 2708 }; 2709 2710 static const TypeInfo idau_interface_type_info = { 2711 .name = TYPE_IDAU_INTERFACE, 2712 .parent = TYPE_INTERFACE, 2713 .class_size = sizeof(IDAUInterfaceClass), 2714 }; 2715 2716 static void arm_cpu_register_types(void) 2717 { 2718 const ARMCPUInfo *info = arm_cpus; 2719 2720 type_register_static(&arm_cpu_type_info); 2721 type_register_static(&idau_interface_type_info); 2722 2723 while (info->name) { 2724 cpu_register(info); 2725 info++; 2726 } 2727 2728 #ifdef CONFIG_KVM 2729 type_register_static(&host_arm_cpu_type_info); 2730 #endif 2731 } 2732 2733 type_init(arm_cpu_register_types) 2734