1 /* 2 * QEMU ARM CPU 3 * 4 * Copyright (c) 2012 SUSE LINUX Products GmbH 5 * 6 * This program is free software; you can redistribute it and/or 7 * modify it under the terms of the GNU General Public License 8 * as published by the Free Software Foundation; either version 2 9 * of the License, or (at your option) any later version. 10 * 11 * This program is distributed in the hope that it will be useful, 12 * but WITHOUT ANY WARRANTY; without even the implied warranty of 13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 14 * GNU General Public License for more details. 15 * 16 * You should have received a copy of the GNU General Public License 17 * along with this program; if not, see 18 * <http://www.gnu.org/licenses/gpl-2.0.html> 19 */ 20 21 #include "qemu/osdep.h" 22 #include "qemu/error-report.h" 23 #include "qapi/error.h" 24 #include "cpu.h" 25 #include "internals.h" 26 #include "qemu-common.h" 27 #include "exec/exec-all.h" 28 #include "hw/qdev-properties.h" 29 #if !defined(CONFIG_USER_ONLY) 30 #include "hw/loader.h" 31 #endif 32 #include "hw/arm/arm.h" 33 #include "sysemu/sysemu.h" 34 #include "sysemu/hw_accel.h" 35 #include "kvm_arm.h" 36 37 static void arm_cpu_set_pc(CPUState *cs, vaddr value) 38 { 39 ARMCPU *cpu = ARM_CPU(cs); 40 41 cpu->env.regs[15] = value; 42 } 43 44 static bool arm_cpu_has_work(CPUState *cs) 45 { 46 ARMCPU *cpu = ARM_CPU(cs); 47 48 return (cpu->power_state != PSCI_OFF) 49 && cs->interrupt_request & 50 (CPU_INTERRUPT_FIQ | CPU_INTERRUPT_HARD 51 | CPU_INTERRUPT_VFIQ | CPU_INTERRUPT_VIRQ 52 | CPU_INTERRUPT_EXITTB); 53 } 54 55 void arm_register_el_change_hook(ARMCPU *cpu, ARMELChangeHook *hook, 56 void *opaque) 57 { 58 /* We currently only support registering a single hook function */ 59 assert(!cpu->el_change_hook); 60 cpu->el_change_hook = hook; 61 cpu->el_change_hook_opaque = opaque; 62 } 63 64 static void cp_reg_reset(gpointer key, gpointer value, gpointer opaque) 65 { 66 /* Reset a single ARMCPRegInfo register */ 67 ARMCPRegInfo *ri = value; 68 ARMCPU *cpu = opaque; 69 70 if (ri->type & (ARM_CP_SPECIAL | ARM_CP_ALIAS)) { 71 return; 72 } 73 74 if (ri->resetfn) { 75 ri->resetfn(&cpu->env, ri); 76 return; 77 } 78 79 /* A zero offset is never possible as it would be regs[0] 80 * so we use it to indicate that reset is being handled elsewhere. 81 * This is basically only used for fields in non-core coprocessors 82 * (like the pxa2xx ones). 83 */ 84 if (!ri->fieldoffset) { 85 return; 86 } 87 88 if (cpreg_field_is_64bit(ri)) { 89 CPREG_FIELD64(&cpu->env, ri) = ri->resetvalue; 90 } else { 91 CPREG_FIELD32(&cpu->env, ri) = ri->resetvalue; 92 } 93 } 94 95 static void cp_reg_check_reset(gpointer key, gpointer value, gpointer opaque) 96 { 97 /* Purely an assertion check: we've already done reset once, 98 * so now check that running the reset for the cpreg doesn't 99 * change its value. This traps bugs where two different cpregs 100 * both try to reset the same state field but to different values. 101 */ 102 ARMCPRegInfo *ri = value; 103 ARMCPU *cpu = opaque; 104 uint64_t oldvalue, newvalue; 105 106 if (ri->type & (ARM_CP_SPECIAL | ARM_CP_ALIAS | ARM_CP_NO_RAW)) { 107 return; 108 } 109 110 oldvalue = read_raw_cp_reg(&cpu->env, ri); 111 cp_reg_reset(key, value, opaque); 112 newvalue = read_raw_cp_reg(&cpu->env, ri); 113 assert(oldvalue == newvalue); 114 } 115 116 /* CPUClass::reset() */ 117 static void arm_cpu_reset(CPUState *s) 118 { 119 ARMCPU *cpu = ARM_CPU(s); 120 ARMCPUClass *acc = ARM_CPU_GET_CLASS(cpu); 121 CPUARMState *env = &cpu->env; 122 123 acc->parent_reset(s); 124 125 memset(env, 0, offsetof(CPUARMState, end_reset_fields)); 126 127 g_hash_table_foreach(cpu->cp_regs, cp_reg_reset, cpu); 128 g_hash_table_foreach(cpu->cp_regs, cp_reg_check_reset, cpu); 129 130 env->vfp.xregs[ARM_VFP_FPSID] = cpu->reset_fpsid; 131 env->vfp.xregs[ARM_VFP_MVFR0] = cpu->mvfr0; 132 env->vfp.xregs[ARM_VFP_MVFR1] = cpu->mvfr1; 133 env->vfp.xregs[ARM_VFP_MVFR2] = cpu->mvfr2; 134 135 cpu->power_state = cpu->start_powered_off ? PSCI_OFF : PSCI_ON; 136 s->halted = cpu->start_powered_off; 137 138 if (arm_feature(env, ARM_FEATURE_IWMMXT)) { 139 env->iwmmxt.cregs[ARM_IWMMXT_wCID] = 0x69051000 | 'Q'; 140 } 141 142 if (arm_feature(env, ARM_FEATURE_AARCH64)) { 143 /* 64 bit CPUs always start in 64 bit mode */ 144 env->aarch64 = 1; 145 #if defined(CONFIG_USER_ONLY) 146 env->pstate = PSTATE_MODE_EL0t; 147 /* Userspace expects access to DC ZVA, CTL_EL0 and the cache ops */ 148 env->cp15.sctlr_el[1] |= SCTLR_UCT | SCTLR_UCI | SCTLR_DZE; 149 /* and to the FP/Neon instructions */ 150 env->cp15.cpacr_el1 = deposit64(env->cp15.cpacr_el1, 20, 2, 3); 151 #else 152 /* Reset into the highest available EL */ 153 if (arm_feature(env, ARM_FEATURE_EL3)) { 154 env->pstate = PSTATE_MODE_EL3h; 155 } else if (arm_feature(env, ARM_FEATURE_EL2)) { 156 env->pstate = PSTATE_MODE_EL2h; 157 } else { 158 env->pstate = PSTATE_MODE_EL1h; 159 } 160 env->pc = cpu->rvbar; 161 #endif 162 } else { 163 #if defined(CONFIG_USER_ONLY) 164 /* Userspace expects access to cp10 and cp11 for FP/Neon */ 165 env->cp15.cpacr_el1 = deposit64(env->cp15.cpacr_el1, 20, 4, 0xf); 166 #endif 167 } 168 169 #if defined(CONFIG_USER_ONLY) 170 env->uncached_cpsr = ARM_CPU_MODE_USR; 171 /* For user mode we must enable access to coprocessors */ 172 env->vfp.xregs[ARM_VFP_FPEXC] = 1 << 30; 173 if (arm_feature(env, ARM_FEATURE_IWMMXT)) { 174 env->cp15.c15_cpar = 3; 175 } else if (arm_feature(env, ARM_FEATURE_XSCALE)) { 176 env->cp15.c15_cpar = 1; 177 } 178 #else 179 /* SVC mode with interrupts disabled. */ 180 env->uncached_cpsr = ARM_CPU_MODE_SVC; 181 env->daif = PSTATE_D | PSTATE_A | PSTATE_I | PSTATE_F; 182 183 if (arm_feature(env, ARM_FEATURE_M)) { 184 uint32_t initial_msp; /* Loaded from 0x0 */ 185 uint32_t initial_pc; /* Loaded from 0x4 */ 186 uint8_t *rom; 187 188 /* The reset value of this bit is IMPDEF, but ARM recommends 189 * that it resets to 1, so QEMU always does that rather than making 190 * it dependent on CPU model. 191 */ 192 env->v7m.ccr = R_V7M_CCR_STKALIGN_MASK; 193 194 /* Unlike A/R profile, M profile defines the reset LR value */ 195 env->regs[14] = 0xffffffff; 196 197 /* Load the initial SP and PC from the vector table at address 0 */ 198 rom = rom_ptr(0); 199 if (rom) { 200 /* Address zero is covered by ROM which hasn't yet been 201 * copied into physical memory. 202 */ 203 initial_msp = ldl_p(rom); 204 initial_pc = ldl_p(rom + 4); 205 } else { 206 /* Address zero not covered by a ROM blob, or the ROM blob 207 * is in non-modifiable memory and this is a second reset after 208 * it got copied into memory. In the latter case, rom_ptr 209 * will return a NULL pointer and we should use ldl_phys instead. 210 */ 211 initial_msp = ldl_phys(s->as, 0); 212 initial_pc = ldl_phys(s->as, 4); 213 } 214 215 env->regs[13] = initial_msp & 0xFFFFFFFC; 216 env->regs[15] = initial_pc & ~1; 217 env->thumb = initial_pc & 1; 218 } 219 220 /* AArch32 has a hard highvec setting of 0xFFFF0000. If we are currently 221 * executing as AArch32 then check if highvecs are enabled and 222 * adjust the PC accordingly. 223 */ 224 if (A32_BANKED_CURRENT_REG_GET(env, sctlr) & SCTLR_V) { 225 env->regs[15] = 0xFFFF0000; 226 } 227 228 env->vfp.xregs[ARM_VFP_FPEXC] = 0; 229 #endif 230 231 if (arm_feature(env, ARM_FEATURE_PMSA) && 232 arm_feature(env, ARM_FEATURE_V7)) { 233 if (cpu->pmsav7_dregion > 0) { 234 memset(env->pmsav7.drbar, 0, 235 sizeof(*env->pmsav7.drbar) * cpu->pmsav7_dregion); 236 memset(env->pmsav7.drsr, 0, 237 sizeof(*env->pmsav7.drsr) * cpu->pmsav7_dregion); 238 memset(env->pmsav7.dracr, 0, 239 sizeof(*env->pmsav7.dracr) * cpu->pmsav7_dregion); 240 } 241 env->pmsav7.rnr = 0; 242 } 243 244 set_flush_to_zero(1, &env->vfp.standard_fp_status); 245 set_flush_inputs_to_zero(1, &env->vfp.standard_fp_status); 246 set_default_nan_mode(1, &env->vfp.standard_fp_status); 247 set_float_detect_tininess(float_tininess_before_rounding, 248 &env->vfp.fp_status); 249 set_float_detect_tininess(float_tininess_before_rounding, 250 &env->vfp.standard_fp_status); 251 #ifndef CONFIG_USER_ONLY 252 if (kvm_enabled()) { 253 kvm_arm_reset_vcpu(cpu); 254 } 255 #endif 256 257 hw_breakpoint_update_all(cpu); 258 hw_watchpoint_update_all(cpu); 259 } 260 261 bool arm_cpu_exec_interrupt(CPUState *cs, int interrupt_request) 262 { 263 CPUClass *cc = CPU_GET_CLASS(cs); 264 CPUARMState *env = cs->env_ptr; 265 uint32_t cur_el = arm_current_el(env); 266 bool secure = arm_is_secure(env); 267 uint32_t target_el; 268 uint32_t excp_idx; 269 bool ret = false; 270 271 if (interrupt_request & CPU_INTERRUPT_FIQ) { 272 excp_idx = EXCP_FIQ; 273 target_el = arm_phys_excp_target_el(cs, excp_idx, cur_el, secure); 274 if (arm_excp_unmasked(cs, excp_idx, target_el)) { 275 cs->exception_index = excp_idx; 276 env->exception.target_el = target_el; 277 cc->do_interrupt(cs); 278 ret = true; 279 } 280 } 281 if (interrupt_request & CPU_INTERRUPT_HARD) { 282 excp_idx = EXCP_IRQ; 283 target_el = arm_phys_excp_target_el(cs, excp_idx, cur_el, secure); 284 if (arm_excp_unmasked(cs, excp_idx, target_el)) { 285 cs->exception_index = excp_idx; 286 env->exception.target_el = target_el; 287 cc->do_interrupt(cs); 288 ret = true; 289 } 290 } 291 if (interrupt_request & CPU_INTERRUPT_VIRQ) { 292 excp_idx = EXCP_VIRQ; 293 target_el = 1; 294 if (arm_excp_unmasked(cs, excp_idx, target_el)) { 295 cs->exception_index = excp_idx; 296 env->exception.target_el = target_el; 297 cc->do_interrupt(cs); 298 ret = true; 299 } 300 } 301 if (interrupt_request & CPU_INTERRUPT_VFIQ) { 302 excp_idx = EXCP_VFIQ; 303 target_el = 1; 304 if (arm_excp_unmasked(cs, excp_idx, target_el)) { 305 cs->exception_index = excp_idx; 306 env->exception.target_el = target_el; 307 cc->do_interrupt(cs); 308 ret = true; 309 } 310 } 311 312 return ret; 313 } 314 315 #if !defined(CONFIG_USER_ONLY) || !defined(TARGET_AARCH64) 316 static bool arm_v7m_cpu_exec_interrupt(CPUState *cs, int interrupt_request) 317 { 318 CPUClass *cc = CPU_GET_CLASS(cs); 319 ARMCPU *cpu = ARM_CPU(cs); 320 CPUARMState *env = &cpu->env; 321 bool ret = false; 322 323 /* ARMv7-M interrupt masking works differently than -A or -R. 324 * There is no FIQ/IRQ distinction. Instead of I and F bits 325 * masking FIQ and IRQ interrupts, an exception is taken only 326 * if it is higher priority than the current execution priority 327 * (which depends on state like BASEPRI, FAULTMASK and the 328 * currently active exception). 329 */ 330 if (interrupt_request & CPU_INTERRUPT_HARD 331 && (armv7m_nvic_can_take_pending_exception(env->nvic))) { 332 cs->exception_index = EXCP_IRQ; 333 cc->do_interrupt(cs); 334 ret = true; 335 } 336 return ret; 337 } 338 #endif 339 340 #ifndef CONFIG_USER_ONLY 341 static void arm_cpu_set_irq(void *opaque, int irq, int level) 342 { 343 ARMCPU *cpu = opaque; 344 CPUARMState *env = &cpu->env; 345 CPUState *cs = CPU(cpu); 346 static const int mask[] = { 347 [ARM_CPU_IRQ] = CPU_INTERRUPT_HARD, 348 [ARM_CPU_FIQ] = CPU_INTERRUPT_FIQ, 349 [ARM_CPU_VIRQ] = CPU_INTERRUPT_VIRQ, 350 [ARM_CPU_VFIQ] = CPU_INTERRUPT_VFIQ 351 }; 352 353 switch (irq) { 354 case ARM_CPU_VIRQ: 355 case ARM_CPU_VFIQ: 356 assert(arm_feature(env, ARM_FEATURE_EL2)); 357 /* fall through */ 358 case ARM_CPU_IRQ: 359 case ARM_CPU_FIQ: 360 if (level) { 361 cpu_interrupt(cs, mask[irq]); 362 } else { 363 cpu_reset_interrupt(cs, mask[irq]); 364 } 365 break; 366 default: 367 g_assert_not_reached(); 368 } 369 } 370 371 static void arm_cpu_kvm_set_irq(void *opaque, int irq, int level) 372 { 373 #ifdef CONFIG_KVM 374 ARMCPU *cpu = opaque; 375 CPUState *cs = CPU(cpu); 376 int kvm_irq = KVM_ARM_IRQ_TYPE_CPU << KVM_ARM_IRQ_TYPE_SHIFT; 377 378 switch (irq) { 379 case ARM_CPU_IRQ: 380 kvm_irq |= KVM_ARM_IRQ_CPU_IRQ; 381 break; 382 case ARM_CPU_FIQ: 383 kvm_irq |= KVM_ARM_IRQ_CPU_FIQ; 384 break; 385 default: 386 g_assert_not_reached(); 387 } 388 kvm_irq |= cs->cpu_index << KVM_ARM_IRQ_VCPU_SHIFT; 389 kvm_set_irq(kvm_state, kvm_irq, level ? 1 : 0); 390 #endif 391 } 392 393 static bool arm_cpu_virtio_is_big_endian(CPUState *cs) 394 { 395 ARMCPU *cpu = ARM_CPU(cs); 396 CPUARMState *env = &cpu->env; 397 398 cpu_synchronize_state(cs); 399 return arm_cpu_data_is_big_endian(env); 400 } 401 402 #endif 403 404 static inline void set_feature(CPUARMState *env, int feature) 405 { 406 env->features |= 1ULL << feature; 407 } 408 409 static inline void unset_feature(CPUARMState *env, int feature) 410 { 411 env->features &= ~(1ULL << feature); 412 } 413 414 static int 415 print_insn_thumb1(bfd_vma pc, disassemble_info *info) 416 { 417 return print_insn_arm(pc | 1, info); 418 } 419 420 static int arm_read_memory_func(bfd_vma memaddr, bfd_byte *b, 421 int length, struct disassemble_info *info) 422 { 423 assert(info->read_memory_inner_func); 424 assert((info->flags & INSN_ARM_BE32) == 0 || length == 2 || length == 4); 425 426 if ((info->flags & INSN_ARM_BE32) != 0 && length == 2) { 427 assert(info->endian == BFD_ENDIAN_LITTLE); 428 return info->read_memory_inner_func(memaddr ^ 2, (bfd_byte *)b, 2, 429 info); 430 } else { 431 return info->read_memory_inner_func(memaddr, b, length, info); 432 } 433 } 434 435 static void arm_disas_set_info(CPUState *cpu, disassemble_info *info) 436 { 437 ARMCPU *ac = ARM_CPU(cpu); 438 CPUARMState *env = &ac->env; 439 440 if (is_a64(env)) { 441 /* We might not be compiled with the A64 disassembler 442 * because it needs a C++ compiler. Leave print_insn 443 * unset in this case to use the caller default behaviour. 444 */ 445 #if defined(CONFIG_ARM_A64_DIS) 446 info->print_insn = print_insn_arm_a64; 447 #endif 448 } else if (env->thumb) { 449 info->print_insn = print_insn_thumb1; 450 } else { 451 info->print_insn = print_insn_arm; 452 } 453 if (bswap_code(arm_sctlr_b(env))) { 454 #ifdef TARGET_WORDS_BIGENDIAN 455 info->endian = BFD_ENDIAN_LITTLE; 456 #else 457 info->endian = BFD_ENDIAN_BIG; 458 #endif 459 } 460 if (info->read_memory_inner_func == NULL) { 461 info->read_memory_inner_func = info->read_memory_func; 462 info->read_memory_func = arm_read_memory_func; 463 } 464 info->flags &= ~INSN_ARM_BE32; 465 if (arm_sctlr_b(env)) { 466 info->flags |= INSN_ARM_BE32; 467 } 468 } 469 470 uint64_t arm_cpu_mp_affinity(int idx, uint8_t clustersz) 471 { 472 uint32_t Aff1 = idx / clustersz; 473 uint32_t Aff0 = idx % clustersz; 474 return (Aff1 << ARM_AFF1_SHIFT) | Aff0; 475 } 476 477 static void arm_cpu_initfn(Object *obj) 478 { 479 CPUState *cs = CPU(obj); 480 ARMCPU *cpu = ARM_CPU(obj); 481 static bool inited; 482 483 cs->env_ptr = &cpu->env; 484 cpu->cp_regs = g_hash_table_new_full(g_int_hash, g_int_equal, 485 g_free, g_free); 486 487 #ifndef CONFIG_USER_ONLY 488 /* Our inbound IRQ and FIQ lines */ 489 if (kvm_enabled()) { 490 /* VIRQ and VFIQ are unused with KVM but we add them to maintain 491 * the same interface as non-KVM CPUs. 492 */ 493 qdev_init_gpio_in(DEVICE(cpu), arm_cpu_kvm_set_irq, 4); 494 } else { 495 qdev_init_gpio_in(DEVICE(cpu), arm_cpu_set_irq, 4); 496 } 497 498 cpu->gt_timer[GTIMER_PHYS] = timer_new(QEMU_CLOCK_VIRTUAL, GTIMER_SCALE, 499 arm_gt_ptimer_cb, cpu); 500 cpu->gt_timer[GTIMER_VIRT] = timer_new(QEMU_CLOCK_VIRTUAL, GTIMER_SCALE, 501 arm_gt_vtimer_cb, cpu); 502 cpu->gt_timer[GTIMER_HYP] = timer_new(QEMU_CLOCK_VIRTUAL, GTIMER_SCALE, 503 arm_gt_htimer_cb, cpu); 504 cpu->gt_timer[GTIMER_SEC] = timer_new(QEMU_CLOCK_VIRTUAL, GTIMER_SCALE, 505 arm_gt_stimer_cb, cpu); 506 qdev_init_gpio_out(DEVICE(cpu), cpu->gt_timer_outputs, 507 ARRAY_SIZE(cpu->gt_timer_outputs)); 508 509 qdev_init_gpio_out_named(DEVICE(cpu), &cpu->gicv3_maintenance_interrupt, 510 "gicv3-maintenance-interrupt", 1); 511 #endif 512 513 /* DTB consumers generally don't in fact care what the 'compatible' 514 * string is, so always provide some string and trust that a hypothetical 515 * picky DTB consumer will also provide a helpful error message. 516 */ 517 cpu->dtb_compatible = "qemu,unknown"; 518 cpu->psci_version = 1; /* By default assume PSCI v0.1 */ 519 cpu->kvm_target = QEMU_KVM_ARM_TARGET_NONE; 520 521 if (tcg_enabled()) { 522 cpu->psci_version = 2; /* TCG implements PSCI 0.2 */ 523 if (!inited) { 524 inited = true; 525 arm_translate_init(); 526 } 527 } 528 } 529 530 static Property arm_cpu_reset_cbar_property = 531 DEFINE_PROP_UINT64("reset-cbar", ARMCPU, reset_cbar, 0); 532 533 static Property arm_cpu_reset_hivecs_property = 534 DEFINE_PROP_BOOL("reset-hivecs", ARMCPU, reset_hivecs, false); 535 536 static Property arm_cpu_rvbar_property = 537 DEFINE_PROP_UINT64("rvbar", ARMCPU, rvbar, 0); 538 539 static Property arm_cpu_has_el2_property = 540 DEFINE_PROP_BOOL("has_el2", ARMCPU, has_el2, true); 541 542 static Property arm_cpu_has_el3_property = 543 DEFINE_PROP_BOOL("has_el3", ARMCPU, has_el3, true); 544 545 static Property arm_cpu_cfgend_property = 546 DEFINE_PROP_BOOL("cfgend", ARMCPU, cfgend, false); 547 548 /* use property name "pmu" to match other archs and virt tools */ 549 static Property arm_cpu_has_pmu_property = 550 DEFINE_PROP_BOOL("pmu", ARMCPU, has_pmu, true); 551 552 static Property arm_cpu_has_mpu_property = 553 DEFINE_PROP_BOOL("has-mpu", ARMCPU, has_mpu, true); 554 555 /* This is like DEFINE_PROP_UINT32 but it doesn't set the default value, 556 * because the CPU initfn will have already set cpu->pmsav7_dregion to 557 * the right value for that particular CPU type, and we don't want 558 * to override that with an incorrect constant value. 559 */ 560 static Property arm_cpu_pmsav7_dregion_property = 561 DEFINE_PROP_UNSIGNED_NODEFAULT("pmsav7-dregion", ARMCPU, 562 pmsav7_dregion, 563 qdev_prop_uint32, uint32_t); 564 565 static void arm_cpu_post_init(Object *obj) 566 { 567 ARMCPU *cpu = ARM_CPU(obj); 568 569 /* M profile implies PMSA. We have to do this here rather than 570 * in realize with the other feature-implication checks because 571 * we look at the PMSA bit to see if we should add some properties. 572 */ 573 if (arm_feature(&cpu->env, ARM_FEATURE_M)) { 574 set_feature(&cpu->env, ARM_FEATURE_PMSA); 575 } 576 577 if (arm_feature(&cpu->env, ARM_FEATURE_CBAR) || 578 arm_feature(&cpu->env, ARM_FEATURE_CBAR_RO)) { 579 qdev_property_add_static(DEVICE(obj), &arm_cpu_reset_cbar_property, 580 &error_abort); 581 } 582 583 if (!arm_feature(&cpu->env, ARM_FEATURE_M)) { 584 qdev_property_add_static(DEVICE(obj), &arm_cpu_reset_hivecs_property, 585 &error_abort); 586 } 587 588 if (arm_feature(&cpu->env, ARM_FEATURE_AARCH64)) { 589 qdev_property_add_static(DEVICE(obj), &arm_cpu_rvbar_property, 590 &error_abort); 591 } 592 593 if (arm_feature(&cpu->env, ARM_FEATURE_EL3)) { 594 /* Add the has_el3 state CPU property only if EL3 is allowed. This will 595 * prevent "has_el3" from existing on CPUs which cannot support EL3. 596 */ 597 qdev_property_add_static(DEVICE(obj), &arm_cpu_has_el3_property, 598 &error_abort); 599 600 #ifndef CONFIG_USER_ONLY 601 object_property_add_link(obj, "secure-memory", 602 TYPE_MEMORY_REGION, 603 (Object **)&cpu->secure_memory, 604 qdev_prop_allow_set_link_before_realize, 605 OBJ_PROP_LINK_UNREF_ON_RELEASE, 606 &error_abort); 607 #endif 608 } 609 610 if (arm_feature(&cpu->env, ARM_FEATURE_EL2)) { 611 qdev_property_add_static(DEVICE(obj), &arm_cpu_has_el2_property, 612 &error_abort); 613 } 614 615 if (arm_feature(&cpu->env, ARM_FEATURE_PMU)) { 616 qdev_property_add_static(DEVICE(obj), &arm_cpu_has_pmu_property, 617 &error_abort); 618 } 619 620 if (arm_feature(&cpu->env, ARM_FEATURE_PMSA)) { 621 qdev_property_add_static(DEVICE(obj), &arm_cpu_has_mpu_property, 622 &error_abort); 623 if (arm_feature(&cpu->env, ARM_FEATURE_V7)) { 624 qdev_property_add_static(DEVICE(obj), 625 &arm_cpu_pmsav7_dregion_property, 626 &error_abort); 627 } 628 } 629 630 qdev_property_add_static(DEVICE(obj), &arm_cpu_cfgend_property, 631 &error_abort); 632 } 633 634 static void arm_cpu_finalizefn(Object *obj) 635 { 636 ARMCPU *cpu = ARM_CPU(obj); 637 g_hash_table_destroy(cpu->cp_regs); 638 } 639 640 static void arm_cpu_realizefn(DeviceState *dev, Error **errp) 641 { 642 CPUState *cs = CPU(dev); 643 ARMCPU *cpu = ARM_CPU(dev); 644 ARMCPUClass *acc = ARM_CPU_GET_CLASS(dev); 645 CPUARMState *env = &cpu->env; 646 int pagebits; 647 Error *local_err = NULL; 648 649 cpu_exec_realizefn(cs, &local_err); 650 if (local_err != NULL) { 651 error_propagate(errp, local_err); 652 return; 653 } 654 655 /* Some features automatically imply others: */ 656 if (arm_feature(env, ARM_FEATURE_V8)) { 657 set_feature(env, ARM_FEATURE_V7); 658 set_feature(env, ARM_FEATURE_ARM_DIV); 659 set_feature(env, ARM_FEATURE_LPAE); 660 } 661 if (arm_feature(env, ARM_FEATURE_V7)) { 662 set_feature(env, ARM_FEATURE_VAPA); 663 set_feature(env, ARM_FEATURE_THUMB2); 664 set_feature(env, ARM_FEATURE_MPIDR); 665 if (!arm_feature(env, ARM_FEATURE_M)) { 666 set_feature(env, ARM_FEATURE_V6K); 667 } else { 668 set_feature(env, ARM_FEATURE_V6); 669 } 670 671 /* Always define VBAR for V7 CPUs even if it doesn't exist in 672 * non-EL3 configs. This is needed by some legacy boards. 673 */ 674 set_feature(env, ARM_FEATURE_VBAR); 675 } 676 if (arm_feature(env, ARM_FEATURE_V6K)) { 677 set_feature(env, ARM_FEATURE_V6); 678 set_feature(env, ARM_FEATURE_MVFR); 679 } 680 if (arm_feature(env, ARM_FEATURE_V6)) { 681 set_feature(env, ARM_FEATURE_V5); 682 if (!arm_feature(env, ARM_FEATURE_M)) { 683 set_feature(env, ARM_FEATURE_AUXCR); 684 } 685 } 686 if (arm_feature(env, ARM_FEATURE_V5)) { 687 set_feature(env, ARM_FEATURE_V4T); 688 } 689 if (arm_feature(env, ARM_FEATURE_M)) { 690 set_feature(env, ARM_FEATURE_THUMB_DIV); 691 } 692 if (arm_feature(env, ARM_FEATURE_ARM_DIV)) { 693 set_feature(env, ARM_FEATURE_THUMB_DIV); 694 } 695 if (arm_feature(env, ARM_FEATURE_VFP4)) { 696 set_feature(env, ARM_FEATURE_VFP3); 697 set_feature(env, ARM_FEATURE_VFP_FP16); 698 } 699 if (arm_feature(env, ARM_FEATURE_VFP3)) { 700 set_feature(env, ARM_FEATURE_VFP); 701 } 702 if (arm_feature(env, ARM_FEATURE_LPAE)) { 703 set_feature(env, ARM_FEATURE_V7MP); 704 set_feature(env, ARM_FEATURE_PXN); 705 } 706 if (arm_feature(env, ARM_FEATURE_CBAR_RO)) { 707 set_feature(env, ARM_FEATURE_CBAR); 708 } 709 if (arm_feature(env, ARM_FEATURE_THUMB2) && 710 !arm_feature(env, ARM_FEATURE_M)) { 711 set_feature(env, ARM_FEATURE_THUMB_DSP); 712 } 713 714 if (arm_feature(env, ARM_FEATURE_V7) && 715 !arm_feature(env, ARM_FEATURE_M) && 716 !arm_feature(env, ARM_FEATURE_PMSA)) { 717 /* v7VMSA drops support for the old ARMv5 tiny pages, so we 718 * can use 4K pages. 719 */ 720 pagebits = 12; 721 } else { 722 /* For CPUs which might have tiny 1K pages, or which have an 723 * MPU and might have small region sizes, stick with 1K pages. 724 */ 725 pagebits = 10; 726 } 727 if (!set_preferred_target_page_bits(pagebits)) { 728 /* This can only ever happen for hotplugging a CPU, or if 729 * the board code incorrectly creates a CPU which it has 730 * promised via minimum_page_size that it will not. 731 */ 732 error_setg(errp, "This CPU requires a smaller page size than the " 733 "system is using"); 734 return; 735 } 736 737 /* This cpu-id-to-MPIDR affinity is used only for TCG; KVM will override it. 738 * We don't support setting cluster ID ([16..23]) (known as Aff2 739 * in later ARM ARM versions), or any of the higher affinity level fields, 740 * so these bits always RAZ. 741 */ 742 if (cpu->mp_affinity == ARM64_AFFINITY_INVALID) { 743 cpu->mp_affinity = arm_cpu_mp_affinity(cs->cpu_index, 744 ARM_DEFAULT_CPUS_PER_CLUSTER); 745 } 746 747 if (cpu->reset_hivecs) { 748 cpu->reset_sctlr |= (1 << 13); 749 } 750 751 if (cpu->cfgend) { 752 if (arm_feature(&cpu->env, ARM_FEATURE_V7)) { 753 cpu->reset_sctlr |= SCTLR_EE; 754 } else { 755 cpu->reset_sctlr |= SCTLR_B; 756 } 757 } 758 759 if (!cpu->has_el3) { 760 /* If the has_el3 CPU property is disabled then we need to disable the 761 * feature. 762 */ 763 unset_feature(env, ARM_FEATURE_EL3); 764 765 /* Disable the security extension feature bits in the processor feature 766 * registers as well. These are id_pfr1[7:4] and id_aa64pfr0[15:12]. 767 */ 768 cpu->id_pfr1 &= ~0xf0; 769 cpu->id_aa64pfr0 &= ~0xf000; 770 } 771 772 if (!cpu->has_el2) { 773 unset_feature(env, ARM_FEATURE_EL2); 774 } 775 776 if (!cpu->has_pmu) { 777 unset_feature(env, ARM_FEATURE_PMU); 778 cpu->id_aa64dfr0 &= ~0xf00; 779 } 780 781 if (!arm_feature(env, ARM_FEATURE_EL2)) { 782 /* Disable the hypervisor feature bits in the processor feature 783 * registers if we don't have EL2. These are id_pfr1[15:12] and 784 * id_aa64pfr0_el1[11:8]. 785 */ 786 cpu->id_aa64pfr0 &= ~0xf00; 787 cpu->id_pfr1 &= ~0xf000; 788 } 789 790 /* MPU can be configured out of a PMSA CPU either by setting has-mpu 791 * to false or by setting pmsav7-dregion to 0. 792 */ 793 if (!cpu->has_mpu) { 794 cpu->pmsav7_dregion = 0; 795 } 796 if (cpu->pmsav7_dregion == 0) { 797 cpu->has_mpu = false; 798 } 799 800 if (arm_feature(env, ARM_FEATURE_PMSA) && 801 arm_feature(env, ARM_FEATURE_V7)) { 802 uint32_t nr = cpu->pmsav7_dregion; 803 804 if (nr > 0xff) { 805 error_setg(errp, "PMSAv7 MPU #regions invalid %" PRIu32, nr); 806 return; 807 } 808 809 if (nr) { 810 env->pmsav7.drbar = g_new0(uint32_t, nr); 811 env->pmsav7.drsr = g_new0(uint32_t, nr); 812 env->pmsav7.dracr = g_new0(uint32_t, nr); 813 } 814 } 815 816 if (arm_feature(env, ARM_FEATURE_EL3)) { 817 set_feature(env, ARM_FEATURE_VBAR); 818 } 819 820 register_cp_regs_for_features(cpu); 821 arm_cpu_register_gdb_regs_for_features(cpu); 822 823 init_cpreg_list(cpu); 824 825 #ifndef CONFIG_USER_ONLY 826 if (cpu->has_el3) { 827 cs->num_ases = 2; 828 } else { 829 cs->num_ases = 1; 830 } 831 832 if (cpu->has_el3) { 833 AddressSpace *as; 834 835 if (!cpu->secure_memory) { 836 cpu->secure_memory = cs->memory; 837 } 838 as = address_space_init_shareable(cpu->secure_memory, 839 "cpu-secure-memory"); 840 cpu_address_space_init(cs, as, ARMASIdx_S); 841 } 842 cpu_address_space_init(cs, 843 address_space_init_shareable(cs->memory, 844 "cpu-memory"), 845 ARMASIdx_NS); 846 #endif 847 848 qemu_init_vcpu(cs); 849 cpu_reset(cs); 850 851 acc->parent_realize(dev, errp); 852 } 853 854 static ObjectClass *arm_cpu_class_by_name(const char *cpu_model) 855 { 856 ObjectClass *oc; 857 char *typename; 858 char **cpuname; 859 860 if (!cpu_model) { 861 return NULL; 862 } 863 864 cpuname = g_strsplit(cpu_model, ",", 1); 865 typename = g_strdup_printf("%s-" TYPE_ARM_CPU, cpuname[0]); 866 oc = object_class_by_name(typename); 867 g_strfreev(cpuname); 868 g_free(typename); 869 if (!oc || !object_class_dynamic_cast(oc, TYPE_ARM_CPU) || 870 object_class_is_abstract(oc)) { 871 return NULL; 872 } 873 return oc; 874 } 875 876 /* CPU models. These are not needed for the AArch64 linux-user build. */ 877 #if !defined(CONFIG_USER_ONLY) || !defined(TARGET_AARCH64) 878 879 static void arm926_initfn(Object *obj) 880 { 881 ARMCPU *cpu = ARM_CPU(obj); 882 883 cpu->dtb_compatible = "arm,arm926"; 884 set_feature(&cpu->env, ARM_FEATURE_V5); 885 set_feature(&cpu->env, ARM_FEATURE_VFP); 886 set_feature(&cpu->env, ARM_FEATURE_DUMMY_C15_REGS); 887 set_feature(&cpu->env, ARM_FEATURE_CACHE_TEST_CLEAN); 888 cpu->midr = 0x41069265; 889 cpu->reset_fpsid = 0x41011090; 890 cpu->ctr = 0x1dd20d2; 891 cpu->reset_sctlr = 0x00090078; 892 } 893 894 static void arm946_initfn(Object *obj) 895 { 896 ARMCPU *cpu = ARM_CPU(obj); 897 898 cpu->dtb_compatible = "arm,arm946"; 899 set_feature(&cpu->env, ARM_FEATURE_V5); 900 set_feature(&cpu->env, ARM_FEATURE_PMSA); 901 set_feature(&cpu->env, ARM_FEATURE_DUMMY_C15_REGS); 902 cpu->midr = 0x41059461; 903 cpu->ctr = 0x0f004006; 904 cpu->reset_sctlr = 0x00000078; 905 } 906 907 static void arm1026_initfn(Object *obj) 908 { 909 ARMCPU *cpu = ARM_CPU(obj); 910 911 cpu->dtb_compatible = "arm,arm1026"; 912 set_feature(&cpu->env, ARM_FEATURE_V5); 913 set_feature(&cpu->env, ARM_FEATURE_VFP); 914 set_feature(&cpu->env, ARM_FEATURE_AUXCR); 915 set_feature(&cpu->env, ARM_FEATURE_DUMMY_C15_REGS); 916 set_feature(&cpu->env, ARM_FEATURE_CACHE_TEST_CLEAN); 917 cpu->midr = 0x4106a262; 918 cpu->reset_fpsid = 0x410110a0; 919 cpu->ctr = 0x1dd20d2; 920 cpu->reset_sctlr = 0x00090078; 921 cpu->reset_auxcr = 1; 922 { 923 /* The 1026 had an IFAR at c6,c0,0,1 rather than the ARMv6 c6,c0,0,2 */ 924 ARMCPRegInfo ifar = { 925 .name = "IFAR", .cp = 15, .crn = 6, .crm = 0, .opc1 = 0, .opc2 = 1, 926 .access = PL1_RW, 927 .fieldoffset = offsetof(CPUARMState, cp15.ifar_ns), 928 .resetvalue = 0 929 }; 930 define_one_arm_cp_reg(cpu, &ifar); 931 } 932 } 933 934 static void arm1136_r2_initfn(Object *obj) 935 { 936 ARMCPU *cpu = ARM_CPU(obj); 937 /* What qemu calls "arm1136_r2" is actually the 1136 r0p2, ie an 938 * older core than plain "arm1136". In particular this does not 939 * have the v6K features. 940 * These ID register values are correct for 1136 but may be wrong 941 * for 1136_r2 (in particular r0p2 does not actually implement most 942 * of the ID registers). 943 */ 944 945 cpu->dtb_compatible = "arm,arm1136"; 946 set_feature(&cpu->env, ARM_FEATURE_V6); 947 set_feature(&cpu->env, ARM_FEATURE_VFP); 948 set_feature(&cpu->env, ARM_FEATURE_DUMMY_C15_REGS); 949 set_feature(&cpu->env, ARM_FEATURE_CACHE_DIRTY_REG); 950 set_feature(&cpu->env, ARM_FEATURE_CACHE_BLOCK_OPS); 951 cpu->midr = 0x4107b362; 952 cpu->reset_fpsid = 0x410120b4; 953 cpu->mvfr0 = 0x11111111; 954 cpu->mvfr1 = 0x00000000; 955 cpu->ctr = 0x1dd20d2; 956 cpu->reset_sctlr = 0x00050078; 957 cpu->id_pfr0 = 0x111; 958 cpu->id_pfr1 = 0x1; 959 cpu->id_dfr0 = 0x2; 960 cpu->id_afr0 = 0x3; 961 cpu->id_mmfr0 = 0x01130003; 962 cpu->id_mmfr1 = 0x10030302; 963 cpu->id_mmfr2 = 0x01222110; 964 cpu->id_isar0 = 0x00140011; 965 cpu->id_isar1 = 0x12002111; 966 cpu->id_isar2 = 0x11231111; 967 cpu->id_isar3 = 0x01102131; 968 cpu->id_isar4 = 0x141; 969 cpu->reset_auxcr = 7; 970 } 971 972 static void arm1136_initfn(Object *obj) 973 { 974 ARMCPU *cpu = ARM_CPU(obj); 975 976 cpu->dtb_compatible = "arm,arm1136"; 977 set_feature(&cpu->env, ARM_FEATURE_V6K); 978 set_feature(&cpu->env, ARM_FEATURE_V6); 979 set_feature(&cpu->env, ARM_FEATURE_VFP); 980 set_feature(&cpu->env, ARM_FEATURE_DUMMY_C15_REGS); 981 set_feature(&cpu->env, ARM_FEATURE_CACHE_DIRTY_REG); 982 set_feature(&cpu->env, ARM_FEATURE_CACHE_BLOCK_OPS); 983 cpu->midr = 0x4117b363; 984 cpu->reset_fpsid = 0x410120b4; 985 cpu->mvfr0 = 0x11111111; 986 cpu->mvfr1 = 0x00000000; 987 cpu->ctr = 0x1dd20d2; 988 cpu->reset_sctlr = 0x00050078; 989 cpu->id_pfr0 = 0x111; 990 cpu->id_pfr1 = 0x1; 991 cpu->id_dfr0 = 0x2; 992 cpu->id_afr0 = 0x3; 993 cpu->id_mmfr0 = 0x01130003; 994 cpu->id_mmfr1 = 0x10030302; 995 cpu->id_mmfr2 = 0x01222110; 996 cpu->id_isar0 = 0x00140011; 997 cpu->id_isar1 = 0x12002111; 998 cpu->id_isar2 = 0x11231111; 999 cpu->id_isar3 = 0x01102131; 1000 cpu->id_isar4 = 0x141; 1001 cpu->reset_auxcr = 7; 1002 } 1003 1004 static void arm1176_initfn(Object *obj) 1005 { 1006 ARMCPU *cpu = ARM_CPU(obj); 1007 1008 cpu->dtb_compatible = "arm,arm1176"; 1009 set_feature(&cpu->env, ARM_FEATURE_V6K); 1010 set_feature(&cpu->env, ARM_FEATURE_VFP); 1011 set_feature(&cpu->env, ARM_FEATURE_VAPA); 1012 set_feature(&cpu->env, ARM_FEATURE_DUMMY_C15_REGS); 1013 set_feature(&cpu->env, ARM_FEATURE_CACHE_DIRTY_REG); 1014 set_feature(&cpu->env, ARM_FEATURE_CACHE_BLOCK_OPS); 1015 set_feature(&cpu->env, ARM_FEATURE_EL3); 1016 cpu->midr = 0x410fb767; 1017 cpu->reset_fpsid = 0x410120b5; 1018 cpu->mvfr0 = 0x11111111; 1019 cpu->mvfr1 = 0x00000000; 1020 cpu->ctr = 0x1dd20d2; 1021 cpu->reset_sctlr = 0x00050078; 1022 cpu->id_pfr0 = 0x111; 1023 cpu->id_pfr1 = 0x11; 1024 cpu->id_dfr0 = 0x33; 1025 cpu->id_afr0 = 0; 1026 cpu->id_mmfr0 = 0x01130003; 1027 cpu->id_mmfr1 = 0x10030302; 1028 cpu->id_mmfr2 = 0x01222100; 1029 cpu->id_isar0 = 0x0140011; 1030 cpu->id_isar1 = 0x12002111; 1031 cpu->id_isar2 = 0x11231121; 1032 cpu->id_isar3 = 0x01102131; 1033 cpu->id_isar4 = 0x01141; 1034 cpu->reset_auxcr = 7; 1035 } 1036 1037 static void arm11mpcore_initfn(Object *obj) 1038 { 1039 ARMCPU *cpu = ARM_CPU(obj); 1040 1041 cpu->dtb_compatible = "arm,arm11mpcore"; 1042 set_feature(&cpu->env, ARM_FEATURE_V6K); 1043 set_feature(&cpu->env, ARM_FEATURE_VFP); 1044 set_feature(&cpu->env, ARM_FEATURE_VAPA); 1045 set_feature(&cpu->env, ARM_FEATURE_MPIDR); 1046 set_feature(&cpu->env, ARM_FEATURE_DUMMY_C15_REGS); 1047 cpu->midr = 0x410fb022; 1048 cpu->reset_fpsid = 0x410120b4; 1049 cpu->mvfr0 = 0x11111111; 1050 cpu->mvfr1 = 0x00000000; 1051 cpu->ctr = 0x1d192992; /* 32K icache 32K dcache */ 1052 cpu->id_pfr0 = 0x111; 1053 cpu->id_pfr1 = 0x1; 1054 cpu->id_dfr0 = 0; 1055 cpu->id_afr0 = 0x2; 1056 cpu->id_mmfr0 = 0x01100103; 1057 cpu->id_mmfr1 = 0x10020302; 1058 cpu->id_mmfr2 = 0x01222000; 1059 cpu->id_isar0 = 0x00100011; 1060 cpu->id_isar1 = 0x12002111; 1061 cpu->id_isar2 = 0x11221011; 1062 cpu->id_isar3 = 0x01102131; 1063 cpu->id_isar4 = 0x141; 1064 cpu->reset_auxcr = 1; 1065 } 1066 1067 static void cortex_m3_initfn(Object *obj) 1068 { 1069 ARMCPU *cpu = ARM_CPU(obj); 1070 set_feature(&cpu->env, ARM_FEATURE_V7); 1071 set_feature(&cpu->env, ARM_FEATURE_M); 1072 cpu->midr = 0x410fc231; 1073 cpu->pmsav7_dregion = 8; 1074 } 1075 1076 static void cortex_m4_initfn(Object *obj) 1077 { 1078 ARMCPU *cpu = ARM_CPU(obj); 1079 1080 set_feature(&cpu->env, ARM_FEATURE_V7); 1081 set_feature(&cpu->env, ARM_FEATURE_M); 1082 set_feature(&cpu->env, ARM_FEATURE_THUMB_DSP); 1083 cpu->midr = 0x410fc240; /* r0p0 */ 1084 cpu->pmsav7_dregion = 8; 1085 } 1086 static void arm_v7m_class_init(ObjectClass *oc, void *data) 1087 { 1088 CPUClass *cc = CPU_CLASS(oc); 1089 1090 #ifndef CONFIG_USER_ONLY 1091 cc->do_interrupt = arm_v7m_cpu_do_interrupt; 1092 #endif 1093 1094 cc->cpu_exec_interrupt = arm_v7m_cpu_exec_interrupt; 1095 } 1096 1097 static const ARMCPRegInfo cortexr5_cp_reginfo[] = { 1098 /* Dummy the TCM region regs for the moment */ 1099 { .name = "ATCM", .cp = 15, .opc1 = 0, .crn = 9, .crm = 1, .opc2 = 0, 1100 .access = PL1_RW, .type = ARM_CP_CONST }, 1101 { .name = "BTCM", .cp = 15, .opc1 = 0, .crn = 9, .crm = 1, .opc2 = 1, 1102 .access = PL1_RW, .type = ARM_CP_CONST }, 1103 { .name = "DCACHE_INVAL", .cp = 15, .opc1 = 0, .crn = 15, .crm = 5, 1104 .opc2 = 0, .access = PL1_W, .type = ARM_CP_NOP }, 1105 REGINFO_SENTINEL 1106 }; 1107 1108 static void cortex_r5_initfn(Object *obj) 1109 { 1110 ARMCPU *cpu = ARM_CPU(obj); 1111 1112 set_feature(&cpu->env, ARM_FEATURE_V7); 1113 set_feature(&cpu->env, ARM_FEATURE_THUMB_DIV); 1114 set_feature(&cpu->env, ARM_FEATURE_ARM_DIV); 1115 set_feature(&cpu->env, ARM_FEATURE_V7MP); 1116 set_feature(&cpu->env, ARM_FEATURE_PMSA); 1117 cpu->midr = 0x411fc153; /* r1p3 */ 1118 cpu->id_pfr0 = 0x0131; 1119 cpu->id_pfr1 = 0x001; 1120 cpu->id_dfr0 = 0x010400; 1121 cpu->id_afr0 = 0x0; 1122 cpu->id_mmfr0 = 0x0210030; 1123 cpu->id_mmfr1 = 0x00000000; 1124 cpu->id_mmfr2 = 0x01200000; 1125 cpu->id_mmfr3 = 0x0211; 1126 cpu->id_isar0 = 0x2101111; 1127 cpu->id_isar1 = 0x13112111; 1128 cpu->id_isar2 = 0x21232141; 1129 cpu->id_isar3 = 0x01112131; 1130 cpu->id_isar4 = 0x0010142; 1131 cpu->id_isar5 = 0x0; 1132 cpu->mp_is_up = true; 1133 cpu->pmsav7_dregion = 16; 1134 define_arm_cp_regs(cpu, cortexr5_cp_reginfo); 1135 } 1136 1137 static const ARMCPRegInfo cortexa8_cp_reginfo[] = { 1138 { .name = "L2LOCKDOWN", .cp = 15, .crn = 9, .crm = 0, .opc1 = 1, .opc2 = 0, 1139 .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0 }, 1140 { .name = "L2AUXCR", .cp = 15, .crn = 9, .crm = 0, .opc1 = 1, .opc2 = 2, 1141 .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0 }, 1142 REGINFO_SENTINEL 1143 }; 1144 1145 static void cortex_a8_initfn(Object *obj) 1146 { 1147 ARMCPU *cpu = ARM_CPU(obj); 1148 1149 cpu->dtb_compatible = "arm,cortex-a8"; 1150 set_feature(&cpu->env, ARM_FEATURE_V7); 1151 set_feature(&cpu->env, ARM_FEATURE_VFP3); 1152 set_feature(&cpu->env, ARM_FEATURE_NEON); 1153 set_feature(&cpu->env, ARM_FEATURE_THUMB2EE); 1154 set_feature(&cpu->env, ARM_FEATURE_DUMMY_C15_REGS); 1155 set_feature(&cpu->env, ARM_FEATURE_EL3); 1156 cpu->midr = 0x410fc080; 1157 cpu->reset_fpsid = 0x410330c0; 1158 cpu->mvfr0 = 0x11110222; 1159 cpu->mvfr1 = 0x00011111; 1160 cpu->ctr = 0x82048004; 1161 cpu->reset_sctlr = 0x00c50078; 1162 cpu->id_pfr0 = 0x1031; 1163 cpu->id_pfr1 = 0x11; 1164 cpu->id_dfr0 = 0x400; 1165 cpu->id_afr0 = 0; 1166 cpu->id_mmfr0 = 0x31100003; 1167 cpu->id_mmfr1 = 0x20000000; 1168 cpu->id_mmfr2 = 0x01202000; 1169 cpu->id_mmfr3 = 0x11; 1170 cpu->id_isar0 = 0x00101111; 1171 cpu->id_isar1 = 0x12112111; 1172 cpu->id_isar2 = 0x21232031; 1173 cpu->id_isar3 = 0x11112131; 1174 cpu->id_isar4 = 0x00111142; 1175 cpu->dbgdidr = 0x15141000; 1176 cpu->clidr = (1 << 27) | (2 << 24) | 3; 1177 cpu->ccsidr[0] = 0xe007e01a; /* 16k L1 dcache. */ 1178 cpu->ccsidr[1] = 0x2007e01a; /* 16k L1 icache. */ 1179 cpu->ccsidr[2] = 0xf0000000; /* No L2 icache. */ 1180 cpu->reset_auxcr = 2; 1181 define_arm_cp_regs(cpu, cortexa8_cp_reginfo); 1182 } 1183 1184 static const ARMCPRegInfo cortexa9_cp_reginfo[] = { 1185 /* power_control should be set to maximum latency. Again, 1186 * default to 0 and set by private hook 1187 */ 1188 { .name = "A9_PWRCTL", .cp = 15, .crn = 15, .crm = 0, .opc1 = 0, .opc2 = 0, 1189 .access = PL1_RW, .resetvalue = 0, 1190 .fieldoffset = offsetof(CPUARMState, cp15.c15_power_control) }, 1191 { .name = "A9_DIAG", .cp = 15, .crn = 15, .crm = 0, .opc1 = 0, .opc2 = 1, 1192 .access = PL1_RW, .resetvalue = 0, 1193 .fieldoffset = offsetof(CPUARMState, cp15.c15_diagnostic) }, 1194 { .name = "A9_PWRDIAG", .cp = 15, .crn = 15, .crm = 0, .opc1 = 0, .opc2 = 2, 1195 .access = PL1_RW, .resetvalue = 0, 1196 .fieldoffset = offsetof(CPUARMState, cp15.c15_power_diagnostic) }, 1197 { .name = "NEONBUSY", .cp = 15, .crn = 15, .crm = 1, .opc1 = 0, .opc2 = 0, 1198 .access = PL1_RW, .resetvalue = 0, .type = ARM_CP_CONST }, 1199 /* TLB lockdown control */ 1200 { .name = "TLB_LOCKR", .cp = 15, .crn = 15, .crm = 4, .opc1 = 5, .opc2 = 2, 1201 .access = PL1_W, .resetvalue = 0, .type = ARM_CP_NOP }, 1202 { .name = "TLB_LOCKW", .cp = 15, .crn = 15, .crm = 4, .opc1 = 5, .opc2 = 4, 1203 .access = PL1_W, .resetvalue = 0, .type = ARM_CP_NOP }, 1204 { .name = "TLB_VA", .cp = 15, .crn = 15, .crm = 5, .opc1 = 5, .opc2 = 2, 1205 .access = PL1_RW, .resetvalue = 0, .type = ARM_CP_CONST }, 1206 { .name = "TLB_PA", .cp = 15, .crn = 15, .crm = 6, .opc1 = 5, .opc2 = 2, 1207 .access = PL1_RW, .resetvalue = 0, .type = ARM_CP_CONST }, 1208 { .name = "TLB_ATTR", .cp = 15, .crn = 15, .crm = 7, .opc1 = 5, .opc2 = 2, 1209 .access = PL1_RW, .resetvalue = 0, .type = ARM_CP_CONST }, 1210 REGINFO_SENTINEL 1211 }; 1212 1213 static void cortex_a9_initfn(Object *obj) 1214 { 1215 ARMCPU *cpu = ARM_CPU(obj); 1216 1217 cpu->dtb_compatible = "arm,cortex-a9"; 1218 set_feature(&cpu->env, ARM_FEATURE_V7); 1219 set_feature(&cpu->env, ARM_FEATURE_VFP3); 1220 set_feature(&cpu->env, ARM_FEATURE_VFP_FP16); 1221 set_feature(&cpu->env, ARM_FEATURE_NEON); 1222 set_feature(&cpu->env, ARM_FEATURE_THUMB2EE); 1223 set_feature(&cpu->env, ARM_FEATURE_EL3); 1224 /* Note that A9 supports the MP extensions even for 1225 * A9UP and single-core A9MP (which are both different 1226 * and valid configurations; we don't model A9UP). 1227 */ 1228 set_feature(&cpu->env, ARM_FEATURE_V7MP); 1229 set_feature(&cpu->env, ARM_FEATURE_CBAR); 1230 cpu->midr = 0x410fc090; 1231 cpu->reset_fpsid = 0x41033090; 1232 cpu->mvfr0 = 0x11110222; 1233 cpu->mvfr1 = 0x01111111; 1234 cpu->ctr = 0x80038003; 1235 cpu->reset_sctlr = 0x00c50078; 1236 cpu->id_pfr0 = 0x1031; 1237 cpu->id_pfr1 = 0x11; 1238 cpu->id_dfr0 = 0x000; 1239 cpu->id_afr0 = 0; 1240 cpu->id_mmfr0 = 0x00100103; 1241 cpu->id_mmfr1 = 0x20000000; 1242 cpu->id_mmfr2 = 0x01230000; 1243 cpu->id_mmfr3 = 0x00002111; 1244 cpu->id_isar0 = 0x00101111; 1245 cpu->id_isar1 = 0x13112111; 1246 cpu->id_isar2 = 0x21232041; 1247 cpu->id_isar3 = 0x11112131; 1248 cpu->id_isar4 = 0x00111142; 1249 cpu->dbgdidr = 0x35141000; 1250 cpu->clidr = (1 << 27) | (1 << 24) | 3; 1251 cpu->ccsidr[0] = 0xe00fe019; /* 16k L1 dcache. */ 1252 cpu->ccsidr[1] = 0x200fe019; /* 16k L1 icache. */ 1253 define_arm_cp_regs(cpu, cortexa9_cp_reginfo); 1254 } 1255 1256 #ifndef CONFIG_USER_ONLY 1257 static uint64_t a15_l2ctlr_read(CPUARMState *env, const ARMCPRegInfo *ri) 1258 { 1259 /* Linux wants the number of processors from here. 1260 * Might as well set the interrupt-controller bit too. 1261 */ 1262 return ((smp_cpus - 1) << 24) | (1 << 23); 1263 } 1264 #endif 1265 1266 static const ARMCPRegInfo cortexa15_cp_reginfo[] = { 1267 #ifndef CONFIG_USER_ONLY 1268 { .name = "L2CTLR", .cp = 15, .crn = 9, .crm = 0, .opc1 = 1, .opc2 = 2, 1269 .access = PL1_RW, .resetvalue = 0, .readfn = a15_l2ctlr_read, 1270 .writefn = arm_cp_write_ignore, }, 1271 #endif 1272 { .name = "L2ECTLR", .cp = 15, .crn = 9, .crm = 0, .opc1 = 1, .opc2 = 3, 1273 .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0 }, 1274 REGINFO_SENTINEL 1275 }; 1276 1277 static void cortex_a7_initfn(Object *obj) 1278 { 1279 ARMCPU *cpu = ARM_CPU(obj); 1280 1281 cpu->dtb_compatible = "arm,cortex-a7"; 1282 set_feature(&cpu->env, ARM_FEATURE_V7); 1283 set_feature(&cpu->env, ARM_FEATURE_VFP4); 1284 set_feature(&cpu->env, ARM_FEATURE_NEON); 1285 set_feature(&cpu->env, ARM_FEATURE_THUMB2EE); 1286 set_feature(&cpu->env, ARM_FEATURE_ARM_DIV); 1287 set_feature(&cpu->env, ARM_FEATURE_GENERIC_TIMER); 1288 set_feature(&cpu->env, ARM_FEATURE_DUMMY_C15_REGS); 1289 set_feature(&cpu->env, ARM_FEATURE_CBAR_RO); 1290 set_feature(&cpu->env, ARM_FEATURE_LPAE); 1291 set_feature(&cpu->env, ARM_FEATURE_EL3); 1292 cpu->kvm_target = QEMU_KVM_ARM_TARGET_CORTEX_A7; 1293 cpu->midr = 0x410fc075; 1294 cpu->reset_fpsid = 0x41023075; 1295 cpu->mvfr0 = 0x10110222; 1296 cpu->mvfr1 = 0x11111111; 1297 cpu->ctr = 0x84448003; 1298 cpu->reset_sctlr = 0x00c50078; 1299 cpu->id_pfr0 = 0x00001131; 1300 cpu->id_pfr1 = 0x00011011; 1301 cpu->id_dfr0 = 0x02010555; 1302 cpu->pmceid0 = 0x00000000; 1303 cpu->pmceid1 = 0x00000000; 1304 cpu->id_afr0 = 0x00000000; 1305 cpu->id_mmfr0 = 0x10101105; 1306 cpu->id_mmfr1 = 0x40000000; 1307 cpu->id_mmfr2 = 0x01240000; 1308 cpu->id_mmfr3 = 0x02102211; 1309 cpu->id_isar0 = 0x01101110; 1310 cpu->id_isar1 = 0x13112111; 1311 cpu->id_isar2 = 0x21232041; 1312 cpu->id_isar3 = 0x11112131; 1313 cpu->id_isar4 = 0x10011142; 1314 cpu->dbgdidr = 0x3515f005; 1315 cpu->clidr = 0x0a200023; 1316 cpu->ccsidr[0] = 0x701fe00a; /* 32K L1 dcache */ 1317 cpu->ccsidr[1] = 0x201fe00a; /* 32K L1 icache */ 1318 cpu->ccsidr[2] = 0x711fe07a; /* 4096K L2 unified cache */ 1319 define_arm_cp_regs(cpu, cortexa15_cp_reginfo); /* Same as A15 */ 1320 } 1321 1322 static void cortex_a15_initfn(Object *obj) 1323 { 1324 ARMCPU *cpu = ARM_CPU(obj); 1325 1326 cpu->dtb_compatible = "arm,cortex-a15"; 1327 set_feature(&cpu->env, ARM_FEATURE_V7); 1328 set_feature(&cpu->env, ARM_FEATURE_VFP4); 1329 set_feature(&cpu->env, ARM_FEATURE_NEON); 1330 set_feature(&cpu->env, ARM_FEATURE_THUMB2EE); 1331 set_feature(&cpu->env, ARM_FEATURE_ARM_DIV); 1332 set_feature(&cpu->env, ARM_FEATURE_GENERIC_TIMER); 1333 set_feature(&cpu->env, ARM_FEATURE_DUMMY_C15_REGS); 1334 set_feature(&cpu->env, ARM_FEATURE_CBAR_RO); 1335 set_feature(&cpu->env, ARM_FEATURE_LPAE); 1336 set_feature(&cpu->env, ARM_FEATURE_EL3); 1337 cpu->kvm_target = QEMU_KVM_ARM_TARGET_CORTEX_A15; 1338 cpu->midr = 0x412fc0f1; 1339 cpu->reset_fpsid = 0x410430f0; 1340 cpu->mvfr0 = 0x10110222; 1341 cpu->mvfr1 = 0x11111111; 1342 cpu->ctr = 0x8444c004; 1343 cpu->reset_sctlr = 0x00c50078; 1344 cpu->id_pfr0 = 0x00001131; 1345 cpu->id_pfr1 = 0x00011011; 1346 cpu->id_dfr0 = 0x02010555; 1347 cpu->pmceid0 = 0x0000000; 1348 cpu->pmceid1 = 0x00000000; 1349 cpu->id_afr0 = 0x00000000; 1350 cpu->id_mmfr0 = 0x10201105; 1351 cpu->id_mmfr1 = 0x20000000; 1352 cpu->id_mmfr2 = 0x01240000; 1353 cpu->id_mmfr3 = 0x02102211; 1354 cpu->id_isar0 = 0x02101110; 1355 cpu->id_isar1 = 0x13112111; 1356 cpu->id_isar2 = 0x21232041; 1357 cpu->id_isar3 = 0x11112131; 1358 cpu->id_isar4 = 0x10011142; 1359 cpu->dbgdidr = 0x3515f021; 1360 cpu->clidr = 0x0a200023; 1361 cpu->ccsidr[0] = 0x701fe00a; /* 32K L1 dcache */ 1362 cpu->ccsidr[1] = 0x201fe00a; /* 32K L1 icache */ 1363 cpu->ccsidr[2] = 0x711fe07a; /* 4096K L2 unified cache */ 1364 define_arm_cp_regs(cpu, cortexa15_cp_reginfo); 1365 } 1366 1367 static void ti925t_initfn(Object *obj) 1368 { 1369 ARMCPU *cpu = ARM_CPU(obj); 1370 set_feature(&cpu->env, ARM_FEATURE_V4T); 1371 set_feature(&cpu->env, ARM_FEATURE_OMAPCP); 1372 cpu->midr = ARM_CPUID_TI925T; 1373 cpu->ctr = 0x5109149; 1374 cpu->reset_sctlr = 0x00000070; 1375 } 1376 1377 static void sa1100_initfn(Object *obj) 1378 { 1379 ARMCPU *cpu = ARM_CPU(obj); 1380 1381 cpu->dtb_compatible = "intel,sa1100"; 1382 set_feature(&cpu->env, ARM_FEATURE_STRONGARM); 1383 set_feature(&cpu->env, ARM_FEATURE_DUMMY_C15_REGS); 1384 cpu->midr = 0x4401A11B; 1385 cpu->reset_sctlr = 0x00000070; 1386 } 1387 1388 static void sa1110_initfn(Object *obj) 1389 { 1390 ARMCPU *cpu = ARM_CPU(obj); 1391 set_feature(&cpu->env, ARM_FEATURE_STRONGARM); 1392 set_feature(&cpu->env, ARM_FEATURE_DUMMY_C15_REGS); 1393 cpu->midr = 0x6901B119; 1394 cpu->reset_sctlr = 0x00000070; 1395 } 1396 1397 static void pxa250_initfn(Object *obj) 1398 { 1399 ARMCPU *cpu = ARM_CPU(obj); 1400 1401 cpu->dtb_compatible = "marvell,xscale"; 1402 set_feature(&cpu->env, ARM_FEATURE_V5); 1403 set_feature(&cpu->env, ARM_FEATURE_XSCALE); 1404 cpu->midr = 0x69052100; 1405 cpu->ctr = 0xd172172; 1406 cpu->reset_sctlr = 0x00000078; 1407 } 1408 1409 static void pxa255_initfn(Object *obj) 1410 { 1411 ARMCPU *cpu = ARM_CPU(obj); 1412 1413 cpu->dtb_compatible = "marvell,xscale"; 1414 set_feature(&cpu->env, ARM_FEATURE_V5); 1415 set_feature(&cpu->env, ARM_FEATURE_XSCALE); 1416 cpu->midr = 0x69052d00; 1417 cpu->ctr = 0xd172172; 1418 cpu->reset_sctlr = 0x00000078; 1419 } 1420 1421 static void pxa260_initfn(Object *obj) 1422 { 1423 ARMCPU *cpu = ARM_CPU(obj); 1424 1425 cpu->dtb_compatible = "marvell,xscale"; 1426 set_feature(&cpu->env, ARM_FEATURE_V5); 1427 set_feature(&cpu->env, ARM_FEATURE_XSCALE); 1428 cpu->midr = 0x69052903; 1429 cpu->ctr = 0xd172172; 1430 cpu->reset_sctlr = 0x00000078; 1431 } 1432 1433 static void pxa261_initfn(Object *obj) 1434 { 1435 ARMCPU *cpu = ARM_CPU(obj); 1436 1437 cpu->dtb_compatible = "marvell,xscale"; 1438 set_feature(&cpu->env, ARM_FEATURE_V5); 1439 set_feature(&cpu->env, ARM_FEATURE_XSCALE); 1440 cpu->midr = 0x69052d05; 1441 cpu->ctr = 0xd172172; 1442 cpu->reset_sctlr = 0x00000078; 1443 } 1444 1445 static void pxa262_initfn(Object *obj) 1446 { 1447 ARMCPU *cpu = ARM_CPU(obj); 1448 1449 cpu->dtb_compatible = "marvell,xscale"; 1450 set_feature(&cpu->env, ARM_FEATURE_V5); 1451 set_feature(&cpu->env, ARM_FEATURE_XSCALE); 1452 cpu->midr = 0x69052d06; 1453 cpu->ctr = 0xd172172; 1454 cpu->reset_sctlr = 0x00000078; 1455 } 1456 1457 static void pxa270a0_initfn(Object *obj) 1458 { 1459 ARMCPU *cpu = ARM_CPU(obj); 1460 1461 cpu->dtb_compatible = "marvell,xscale"; 1462 set_feature(&cpu->env, ARM_FEATURE_V5); 1463 set_feature(&cpu->env, ARM_FEATURE_XSCALE); 1464 set_feature(&cpu->env, ARM_FEATURE_IWMMXT); 1465 cpu->midr = 0x69054110; 1466 cpu->ctr = 0xd172172; 1467 cpu->reset_sctlr = 0x00000078; 1468 } 1469 1470 static void pxa270a1_initfn(Object *obj) 1471 { 1472 ARMCPU *cpu = ARM_CPU(obj); 1473 1474 cpu->dtb_compatible = "marvell,xscale"; 1475 set_feature(&cpu->env, ARM_FEATURE_V5); 1476 set_feature(&cpu->env, ARM_FEATURE_XSCALE); 1477 set_feature(&cpu->env, ARM_FEATURE_IWMMXT); 1478 cpu->midr = 0x69054111; 1479 cpu->ctr = 0xd172172; 1480 cpu->reset_sctlr = 0x00000078; 1481 } 1482 1483 static void pxa270b0_initfn(Object *obj) 1484 { 1485 ARMCPU *cpu = ARM_CPU(obj); 1486 1487 cpu->dtb_compatible = "marvell,xscale"; 1488 set_feature(&cpu->env, ARM_FEATURE_V5); 1489 set_feature(&cpu->env, ARM_FEATURE_XSCALE); 1490 set_feature(&cpu->env, ARM_FEATURE_IWMMXT); 1491 cpu->midr = 0x69054112; 1492 cpu->ctr = 0xd172172; 1493 cpu->reset_sctlr = 0x00000078; 1494 } 1495 1496 static void pxa270b1_initfn(Object *obj) 1497 { 1498 ARMCPU *cpu = ARM_CPU(obj); 1499 1500 cpu->dtb_compatible = "marvell,xscale"; 1501 set_feature(&cpu->env, ARM_FEATURE_V5); 1502 set_feature(&cpu->env, ARM_FEATURE_XSCALE); 1503 set_feature(&cpu->env, ARM_FEATURE_IWMMXT); 1504 cpu->midr = 0x69054113; 1505 cpu->ctr = 0xd172172; 1506 cpu->reset_sctlr = 0x00000078; 1507 } 1508 1509 static void pxa270c0_initfn(Object *obj) 1510 { 1511 ARMCPU *cpu = ARM_CPU(obj); 1512 1513 cpu->dtb_compatible = "marvell,xscale"; 1514 set_feature(&cpu->env, ARM_FEATURE_V5); 1515 set_feature(&cpu->env, ARM_FEATURE_XSCALE); 1516 set_feature(&cpu->env, ARM_FEATURE_IWMMXT); 1517 cpu->midr = 0x69054114; 1518 cpu->ctr = 0xd172172; 1519 cpu->reset_sctlr = 0x00000078; 1520 } 1521 1522 static void pxa270c5_initfn(Object *obj) 1523 { 1524 ARMCPU *cpu = ARM_CPU(obj); 1525 1526 cpu->dtb_compatible = "marvell,xscale"; 1527 set_feature(&cpu->env, ARM_FEATURE_V5); 1528 set_feature(&cpu->env, ARM_FEATURE_XSCALE); 1529 set_feature(&cpu->env, ARM_FEATURE_IWMMXT); 1530 cpu->midr = 0x69054117; 1531 cpu->ctr = 0xd172172; 1532 cpu->reset_sctlr = 0x00000078; 1533 } 1534 1535 #ifdef CONFIG_USER_ONLY 1536 static void arm_any_initfn(Object *obj) 1537 { 1538 ARMCPU *cpu = ARM_CPU(obj); 1539 set_feature(&cpu->env, ARM_FEATURE_V8); 1540 set_feature(&cpu->env, ARM_FEATURE_VFP4); 1541 set_feature(&cpu->env, ARM_FEATURE_NEON); 1542 set_feature(&cpu->env, ARM_FEATURE_THUMB2EE); 1543 set_feature(&cpu->env, ARM_FEATURE_V8_AES); 1544 set_feature(&cpu->env, ARM_FEATURE_V8_SHA1); 1545 set_feature(&cpu->env, ARM_FEATURE_V8_SHA256); 1546 set_feature(&cpu->env, ARM_FEATURE_V8_PMULL); 1547 set_feature(&cpu->env, ARM_FEATURE_CRC); 1548 cpu->midr = 0xffffffff; 1549 } 1550 #endif 1551 1552 #endif /* !defined(CONFIG_USER_ONLY) || !defined(TARGET_AARCH64) */ 1553 1554 typedef struct ARMCPUInfo { 1555 const char *name; 1556 void (*initfn)(Object *obj); 1557 void (*class_init)(ObjectClass *oc, void *data); 1558 } ARMCPUInfo; 1559 1560 static const ARMCPUInfo arm_cpus[] = { 1561 #if !defined(CONFIG_USER_ONLY) || !defined(TARGET_AARCH64) 1562 { .name = "arm926", .initfn = arm926_initfn }, 1563 { .name = "arm946", .initfn = arm946_initfn }, 1564 { .name = "arm1026", .initfn = arm1026_initfn }, 1565 /* What QEMU calls "arm1136-r2" is actually the 1136 r0p2, i.e. an 1566 * older core than plain "arm1136". In particular this does not 1567 * have the v6K features. 1568 */ 1569 { .name = "arm1136-r2", .initfn = arm1136_r2_initfn }, 1570 { .name = "arm1136", .initfn = arm1136_initfn }, 1571 { .name = "arm1176", .initfn = arm1176_initfn }, 1572 { .name = "arm11mpcore", .initfn = arm11mpcore_initfn }, 1573 { .name = "cortex-m3", .initfn = cortex_m3_initfn, 1574 .class_init = arm_v7m_class_init }, 1575 { .name = "cortex-m4", .initfn = cortex_m4_initfn, 1576 .class_init = arm_v7m_class_init }, 1577 { .name = "cortex-r5", .initfn = cortex_r5_initfn }, 1578 { .name = "cortex-a7", .initfn = cortex_a7_initfn }, 1579 { .name = "cortex-a8", .initfn = cortex_a8_initfn }, 1580 { .name = "cortex-a9", .initfn = cortex_a9_initfn }, 1581 { .name = "cortex-a15", .initfn = cortex_a15_initfn }, 1582 { .name = "ti925t", .initfn = ti925t_initfn }, 1583 { .name = "sa1100", .initfn = sa1100_initfn }, 1584 { .name = "sa1110", .initfn = sa1110_initfn }, 1585 { .name = "pxa250", .initfn = pxa250_initfn }, 1586 { .name = "pxa255", .initfn = pxa255_initfn }, 1587 { .name = "pxa260", .initfn = pxa260_initfn }, 1588 { .name = "pxa261", .initfn = pxa261_initfn }, 1589 { .name = "pxa262", .initfn = pxa262_initfn }, 1590 /* "pxa270" is an alias for "pxa270-a0" */ 1591 { .name = "pxa270", .initfn = pxa270a0_initfn }, 1592 { .name = "pxa270-a0", .initfn = pxa270a0_initfn }, 1593 { .name = "pxa270-a1", .initfn = pxa270a1_initfn }, 1594 { .name = "pxa270-b0", .initfn = pxa270b0_initfn }, 1595 { .name = "pxa270-b1", .initfn = pxa270b1_initfn }, 1596 { .name = "pxa270-c0", .initfn = pxa270c0_initfn }, 1597 { .name = "pxa270-c5", .initfn = pxa270c5_initfn }, 1598 #ifdef CONFIG_USER_ONLY 1599 { .name = "any", .initfn = arm_any_initfn }, 1600 #endif 1601 #endif 1602 { .name = NULL } 1603 }; 1604 1605 static Property arm_cpu_properties[] = { 1606 DEFINE_PROP_BOOL("start-powered-off", ARMCPU, start_powered_off, false), 1607 DEFINE_PROP_UINT32("psci-conduit", ARMCPU, psci_conduit, 0), 1608 DEFINE_PROP_UINT32("midr", ARMCPU, midr, 0), 1609 DEFINE_PROP_UINT64("mp-affinity", ARMCPU, 1610 mp_affinity, ARM64_AFFINITY_INVALID), 1611 DEFINE_PROP_INT32("node-id", ARMCPU, node_id, CPU_UNSET_NUMA_NODE_ID), 1612 DEFINE_PROP_END_OF_LIST() 1613 }; 1614 1615 #ifdef CONFIG_USER_ONLY 1616 static int arm_cpu_handle_mmu_fault(CPUState *cs, vaddr address, int rw, 1617 int mmu_idx) 1618 { 1619 ARMCPU *cpu = ARM_CPU(cs); 1620 CPUARMState *env = &cpu->env; 1621 1622 env->exception.vaddress = address; 1623 if (rw == 2) { 1624 cs->exception_index = EXCP_PREFETCH_ABORT; 1625 } else { 1626 cs->exception_index = EXCP_DATA_ABORT; 1627 } 1628 return 1; 1629 } 1630 #endif 1631 1632 static gchar *arm_gdb_arch_name(CPUState *cs) 1633 { 1634 ARMCPU *cpu = ARM_CPU(cs); 1635 CPUARMState *env = &cpu->env; 1636 1637 if (arm_feature(env, ARM_FEATURE_IWMMXT)) { 1638 return g_strdup("iwmmxt"); 1639 } 1640 return g_strdup("arm"); 1641 } 1642 1643 static void arm_cpu_class_init(ObjectClass *oc, void *data) 1644 { 1645 ARMCPUClass *acc = ARM_CPU_CLASS(oc); 1646 CPUClass *cc = CPU_CLASS(acc); 1647 DeviceClass *dc = DEVICE_CLASS(oc); 1648 1649 acc->parent_realize = dc->realize; 1650 dc->realize = arm_cpu_realizefn; 1651 dc->props = arm_cpu_properties; 1652 1653 acc->parent_reset = cc->reset; 1654 cc->reset = arm_cpu_reset; 1655 1656 cc->class_by_name = arm_cpu_class_by_name; 1657 cc->has_work = arm_cpu_has_work; 1658 cc->cpu_exec_interrupt = arm_cpu_exec_interrupt; 1659 cc->dump_state = arm_cpu_dump_state; 1660 cc->set_pc = arm_cpu_set_pc; 1661 cc->gdb_read_register = arm_cpu_gdb_read_register; 1662 cc->gdb_write_register = arm_cpu_gdb_write_register; 1663 #ifdef CONFIG_USER_ONLY 1664 cc->handle_mmu_fault = arm_cpu_handle_mmu_fault; 1665 #else 1666 cc->do_interrupt = arm_cpu_do_interrupt; 1667 cc->do_unaligned_access = arm_cpu_do_unaligned_access; 1668 cc->get_phys_page_attrs_debug = arm_cpu_get_phys_page_attrs_debug; 1669 cc->asidx_from_attrs = arm_asidx_from_attrs; 1670 cc->vmsd = &vmstate_arm_cpu; 1671 cc->virtio_is_big_endian = arm_cpu_virtio_is_big_endian; 1672 cc->write_elf64_note = arm_cpu_write_elf64_note; 1673 cc->write_elf32_note = arm_cpu_write_elf32_note; 1674 #endif 1675 cc->gdb_num_core_regs = 26; 1676 cc->gdb_core_xml_file = "arm-core.xml"; 1677 cc->gdb_arch_name = arm_gdb_arch_name; 1678 cc->gdb_stop_before_watchpoint = true; 1679 cc->debug_excp_handler = arm_debug_excp_handler; 1680 cc->debug_check_watchpoint = arm_debug_check_watchpoint; 1681 #if !defined(CONFIG_USER_ONLY) 1682 cc->adjust_watchpoint_address = arm_adjust_watchpoint_address; 1683 #endif 1684 1685 cc->disas_set_info = arm_disas_set_info; 1686 } 1687 1688 static void cpu_register(const ARMCPUInfo *info) 1689 { 1690 TypeInfo type_info = { 1691 .parent = TYPE_ARM_CPU, 1692 .instance_size = sizeof(ARMCPU), 1693 .instance_init = info->initfn, 1694 .class_size = sizeof(ARMCPUClass), 1695 .class_init = info->class_init, 1696 }; 1697 1698 type_info.name = g_strdup_printf("%s-" TYPE_ARM_CPU, info->name); 1699 type_register(&type_info); 1700 g_free((void *)type_info.name); 1701 } 1702 1703 static const TypeInfo arm_cpu_type_info = { 1704 .name = TYPE_ARM_CPU, 1705 .parent = TYPE_CPU, 1706 .instance_size = sizeof(ARMCPU), 1707 .instance_init = arm_cpu_initfn, 1708 .instance_post_init = arm_cpu_post_init, 1709 .instance_finalize = arm_cpu_finalizefn, 1710 .abstract = true, 1711 .class_size = sizeof(ARMCPUClass), 1712 .class_init = arm_cpu_class_init, 1713 }; 1714 1715 static void arm_cpu_register_types(void) 1716 { 1717 const ARMCPUInfo *info = arm_cpus; 1718 1719 type_register_static(&arm_cpu_type_info); 1720 1721 while (info->name) { 1722 cpu_register(info); 1723 info++; 1724 } 1725 } 1726 1727 type_init(arm_cpu_register_types) 1728