1 /* 2 * QEMU ARM CPU 3 * 4 * Copyright (c) 2012 SUSE LINUX Products GmbH 5 * 6 * This program is free software; you can redistribute it and/or 7 * modify it under the terms of the GNU General Public License 8 * as published by the Free Software Foundation; either version 2 9 * of the License, or (at your option) any later version. 10 * 11 * This program is distributed in the hope that it will be useful, 12 * but WITHOUT ANY WARRANTY; without even the implied warranty of 13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 14 * GNU General Public License for more details. 15 * 16 * You should have received a copy of the GNU General Public License 17 * along with this program; if not, see 18 * <http://www.gnu.org/licenses/gpl-2.0.html> 19 */ 20 21 #include "qemu/osdep.h" 22 #include "qemu/qemu-print.h" 23 #include "qemu-common.h" 24 #include "target/arm/idau.h" 25 #include "qemu/module.h" 26 #include "qapi/error.h" 27 #include "qapi/visitor.h" 28 #include "cpu.h" 29 #include "internals.h" 30 #include "exec/exec-all.h" 31 #include "hw/qdev-properties.h" 32 #if !defined(CONFIG_USER_ONLY) 33 #include "hw/loader.h" 34 #include "hw/boards.h" 35 #endif 36 #include "sysemu/sysemu.h" 37 #include "sysemu/tcg.h" 38 #include "sysemu/hw_accel.h" 39 #include "kvm_arm.h" 40 #include "disas/capstone.h" 41 #include "fpu/softfloat.h" 42 43 static void arm_cpu_set_pc(CPUState *cs, vaddr value) 44 { 45 ARMCPU *cpu = ARM_CPU(cs); 46 CPUARMState *env = &cpu->env; 47 48 if (is_a64(env)) { 49 env->pc = value; 50 env->thumb = 0; 51 } else { 52 env->regs[15] = value & ~1; 53 env->thumb = value & 1; 54 } 55 } 56 57 static void arm_cpu_synchronize_from_tb(CPUState *cs, TranslationBlock *tb) 58 { 59 ARMCPU *cpu = ARM_CPU(cs); 60 CPUARMState *env = &cpu->env; 61 62 /* 63 * It's OK to look at env for the current mode here, because it's 64 * never possible for an AArch64 TB to chain to an AArch32 TB. 65 */ 66 if (is_a64(env)) { 67 env->pc = tb->pc; 68 } else { 69 env->regs[15] = tb->pc; 70 } 71 } 72 73 static bool arm_cpu_has_work(CPUState *cs) 74 { 75 ARMCPU *cpu = ARM_CPU(cs); 76 77 return (cpu->power_state != PSCI_OFF) 78 && cs->interrupt_request & 79 (CPU_INTERRUPT_FIQ | CPU_INTERRUPT_HARD 80 | CPU_INTERRUPT_VFIQ | CPU_INTERRUPT_VIRQ 81 | CPU_INTERRUPT_EXITTB); 82 } 83 84 void arm_register_pre_el_change_hook(ARMCPU *cpu, ARMELChangeHookFn *hook, 85 void *opaque) 86 { 87 ARMELChangeHook *entry = g_new0(ARMELChangeHook, 1); 88 89 entry->hook = hook; 90 entry->opaque = opaque; 91 92 QLIST_INSERT_HEAD(&cpu->pre_el_change_hooks, entry, node); 93 } 94 95 void arm_register_el_change_hook(ARMCPU *cpu, ARMELChangeHookFn *hook, 96 void *opaque) 97 { 98 ARMELChangeHook *entry = g_new0(ARMELChangeHook, 1); 99 100 entry->hook = hook; 101 entry->opaque = opaque; 102 103 QLIST_INSERT_HEAD(&cpu->el_change_hooks, entry, node); 104 } 105 106 static void cp_reg_reset(gpointer key, gpointer value, gpointer opaque) 107 { 108 /* Reset a single ARMCPRegInfo register */ 109 ARMCPRegInfo *ri = value; 110 ARMCPU *cpu = opaque; 111 112 if (ri->type & (ARM_CP_SPECIAL | ARM_CP_ALIAS)) { 113 return; 114 } 115 116 if (ri->resetfn) { 117 ri->resetfn(&cpu->env, ri); 118 return; 119 } 120 121 /* A zero offset is never possible as it would be regs[0] 122 * so we use it to indicate that reset is being handled elsewhere. 123 * This is basically only used for fields in non-core coprocessors 124 * (like the pxa2xx ones). 125 */ 126 if (!ri->fieldoffset) { 127 return; 128 } 129 130 if (cpreg_field_is_64bit(ri)) { 131 CPREG_FIELD64(&cpu->env, ri) = ri->resetvalue; 132 } else { 133 CPREG_FIELD32(&cpu->env, ri) = ri->resetvalue; 134 } 135 } 136 137 static void cp_reg_check_reset(gpointer key, gpointer value, gpointer opaque) 138 { 139 /* Purely an assertion check: we've already done reset once, 140 * so now check that running the reset for the cpreg doesn't 141 * change its value. This traps bugs where two different cpregs 142 * both try to reset the same state field but to different values. 143 */ 144 ARMCPRegInfo *ri = value; 145 ARMCPU *cpu = opaque; 146 uint64_t oldvalue, newvalue; 147 148 if (ri->type & (ARM_CP_SPECIAL | ARM_CP_ALIAS | ARM_CP_NO_RAW)) { 149 return; 150 } 151 152 oldvalue = read_raw_cp_reg(&cpu->env, ri); 153 cp_reg_reset(key, value, opaque); 154 newvalue = read_raw_cp_reg(&cpu->env, ri); 155 assert(oldvalue == newvalue); 156 } 157 158 static void arm_cpu_reset(DeviceState *dev) 159 { 160 CPUState *s = CPU(dev); 161 ARMCPU *cpu = ARM_CPU(s); 162 ARMCPUClass *acc = ARM_CPU_GET_CLASS(cpu); 163 CPUARMState *env = &cpu->env; 164 165 acc->parent_reset(dev); 166 167 memset(env, 0, offsetof(CPUARMState, end_reset_fields)); 168 169 g_hash_table_foreach(cpu->cp_regs, cp_reg_reset, cpu); 170 g_hash_table_foreach(cpu->cp_regs, cp_reg_check_reset, cpu); 171 172 env->vfp.xregs[ARM_VFP_FPSID] = cpu->reset_fpsid; 173 env->vfp.xregs[ARM_VFP_MVFR0] = cpu->isar.mvfr0; 174 env->vfp.xregs[ARM_VFP_MVFR1] = cpu->isar.mvfr1; 175 env->vfp.xregs[ARM_VFP_MVFR2] = cpu->isar.mvfr2; 176 177 cpu->power_state = cpu->start_powered_off ? PSCI_OFF : PSCI_ON; 178 s->halted = cpu->start_powered_off; 179 180 if (arm_feature(env, ARM_FEATURE_IWMMXT)) { 181 env->iwmmxt.cregs[ARM_IWMMXT_wCID] = 0x69051000 | 'Q'; 182 } 183 184 if (arm_feature(env, ARM_FEATURE_AARCH64)) { 185 /* 64 bit CPUs always start in 64 bit mode */ 186 env->aarch64 = 1; 187 #if defined(CONFIG_USER_ONLY) 188 env->pstate = PSTATE_MODE_EL0t; 189 /* Userspace expects access to DC ZVA, CTL_EL0 and the cache ops */ 190 env->cp15.sctlr_el[1] |= SCTLR_UCT | SCTLR_UCI | SCTLR_DZE; 191 /* Enable all PAC keys. */ 192 env->cp15.sctlr_el[1] |= (SCTLR_EnIA | SCTLR_EnIB | 193 SCTLR_EnDA | SCTLR_EnDB); 194 /* and to the FP/Neon instructions */ 195 env->cp15.cpacr_el1 = deposit64(env->cp15.cpacr_el1, 20, 2, 3); 196 /* and to the SVE instructions */ 197 env->cp15.cpacr_el1 = deposit64(env->cp15.cpacr_el1, 16, 2, 3); 198 /* with reasonable vector length */ 199 if (cpu_isar_feature(aa64_sve, cpu)) { 200 env->vfp.zcr_el[1] = MIN(cpu->sve_max_vq - 1, 3); 201 } 202 /* 203 * Enable TBI0 and TBI1. While the real kernel only enables TBI0, 204 * turning on both here will produce smaller code and otherwise 205 * make no difference to the user-level emulation. 206 */ 207 env->cp15.tcr_el[1].raw_tcr = (3ULL << 37); 208 #else 209 /* Reset into the highest available EL */ 210 if (arm_feature(env, ARM_FEATURE_EL3)) { 211 env->pstate = PSTATE_MODE_EL3h; 212 } else if (arm_feature(env, ARM_FEATURE_EL2)) { 213 env->pstate = PSTATE_MODE_EL2h; 214 } else { 215 env->pstate = PSTATE_MODE_EL1h; 216 } 217 env->pc = cpu->rvbar; 218 #endif 219 } else { 220 #if defined(CONFIG_USER_ONLY) 221 /* Userspace expects access to cp10 and cp11 for FP/Neon */ 222 env->cp15.cpacr_el1 = deposit64(env->cp15.cpacr_el1, 20, 4, 0xf); 223 #endif 224 } 225 226 #if defined(CONFIG_USER_ONLY) 227 env->uncached_cpsr = ARM_CPU_MODE_USR; 228 /* For user mode we must enable access to coprocessors */ 229 env->vfp.xregs[ARM_VFP_FPEXC] = 1 << 30; 230 if (arm_feature(env, ARM_FEATURE_IWMMXT)) { 231 env->cp15.c15_cpar = 3; 232 } else if (arm_feature(env, ARM_FEATURE_XSCALE)) { 233 env->cp15.c15_cpar = 1; 234 } 235 #else 236 237 /* 238 * If the highest available EL is EL2, AArch32 will start in Hyp 239 * mode; otherwise it starts in SVC. Note that if we start in 240 * AArch64 then these values in the uncached_cpsr will be ignored. 241 */ 242 if (arm_feature(env, ARM_FEATURE_EL2) && 243 !arm_feature(env, ARM_FEATURE_EL3)) { 244 env->uncached_cpsr = ARM_CPU_MODE_HYP; 245 } else { 246 env->uncached_cpsr = ARM_CPU_MODE_SVC; 247 } 248 env->daif = PSTATE_D | PSTATE_A | PSTATE_I | PSTATE_F; 249 250 if (arm_feature(env, ARM_FEATURE_M)) { 251 uint32_t initial_msp; /* Loaded from 0x0 */ 252 uint32_t initial_pc; /* Loaded from 0x4 */ 253 uint8_t *rom; 254 uint32_t vecbase; 255 256 if (arm_feature(env, ARM_FEATURE_M_SECURITY)) { 257 env->v7m.secure = true; 258 } else { 259 /* This bit resets to 0 if security is supported, but 1 if 260 * it is not. The bit is not present in v7M, but we set it 261 * here so we can avoid having to make checks on it conditional 262 * on ARM_FEATURE_V8 (we don't let the guest see the bit). 263 */ 264 env->v7m.aircr = R_V7M_AIRCR_BFHFNMINS_MASK; 265 /* 266 * Set NSACR to indicate "NS access permitted to everything"; 267 * this avoids having to have all the tests of it being 268 * conditional on ARM_FEATURE_M_SECURITY. Note also that from 269 * v8.1M the guest-visible value of NSACR in a CPU without the 270 * Security Extension is 0xcff. 271 */ 272 env->v7m.nsacr = 0xcff; 273 } 274 275 /* In v7M the reset value of this bit is IMPDEF, but ARM recommends 276 * that it resets to 1, so QEMU always does that rather than making 277 * it dependent on CPU model. In v8M it is RES1. 278 */ 279 env->v7m.ccr[M_REG_NS] = R_V7M_CCR_STKALIGN_MASK; 280 env->v7m.ccr[M_REG_S] = R_V7M_CCR_STKALIGN_MASK; 281 if (arm_feature(env, ARM_FEATURE_V8)) { 282 /* in v8M the NONBASETHRDENA bit [0] is RES1 */ 283 env->v7m.ccr[M_REG_NS] |= R_V7M_CCR_NONBASETHRDENA_MASK; 284 env->v7m.ccr[M_REG_S] |= R_V7M_CCR_NONBASETHRDENA_MASK; 285 } 286 if (!arm_feature(env, ARM_FEATURE_M_MAIN)) { 287 env->v7m.ccr[M_REG_NS] |= R_V7M_CCR_UNALIGN_TRP_MASK; 288 env->v7m.ccr[M_REG_S] |= R_V7M_CCR_UNALIGN_TRP_MASK; 289 } 290 291 if (cpu_isar_feature(aa32_vfp_simd, cpu)) { 292 env->v7m.fpccr[M_REG_NS] = R_V7M_FPCCR_ASPEN_MASK; 293 env->v7m.fpccr[M_REG_S] = R_V7M_FPCCR_ASPEN_MASK | 294 R_V7M_FPCCR_LSPEN_MASK | R_V7M_FPCCR_S_MASK; 295 } 296 /* Unlike A/R profile, M profile defines the reset LR value */ 297 env->regs[14] = 0xffffffff; 298 299 env->v7m.vecbase[M_REG_S] = cpu->init_svtor & 0xffffff80; 300 301 /* Load the initial SP and PC from offset 0 and 4 in the vector table */ 302 vecbase = env->v7m.vecbase[env->v7m.secure]; 303 rom = rom_ptr(vecbase, 8); 304 if (rom) { 305 /* Address zero is covered by ROM which hasn't yet been 306 * copied into physical memory. 307 */ 308 initial_msp = ldl_p(rom); 309 initial_pc = ldl_p(rom + 4); 310 } else { 311 /* Address zero not covered by a ROM blob, or the ROM blob 312 * is in non-modifiable memory and this is a second reset after 313 * it got copied into memory. In the latter case, rom_ptr 314 * will return a NULL pointer and we should use ldl_phys instead. 315 */ 316 initial_msp = ldl_phys(s->as, vecbase); 317 initial_pc = ldl_phys(s->as, vecbase + 4); 318 } 319 320 env->regs[13] = initial_msp & 0xFFFFFFFC; 321 env->regs[15] = initial_pc & ~1; 322 env->thumb = initial_pc & 1; 323 } 324 325 /* AArch32 has a hard highvec setting of 0xFFFF0000. If we are currently 326 * executing as AArch32 then check if highvecs are enabled and 327 * adjust the PC accordingly. 328 */ 329 if (A32_BANKED_CURRENT_REG_GET(env, sctlr) & SCTLR_V) { 330 env->regs[15] = 0xFFFF0000; 331 } 332 333 /* M profile requires that reset clears the exclusive monitor; 334 * A profile does not, but clearing it makes more sense than having it 335 * set with an exclusive access on address zero. 336 */ 337 arm_clear_exclusive(env); 338 339 env->vfp.xregs[ARM_VFP_FPEXC] = 0; 340 #endif 341 342 if (arm_feature(env, ARM_FEATURE_PMSA)) { 343 if (cpu->pmsav7_dregion > 0) { 344 if (arm_feature(env, ARM_FEATURE_V8)) { 345 memset(env->pmsav8.rbar[M_REG_NS], 0, 346 sizeof(*env->pmsav8.rbar[M_REG_NS]) 347 * cpu->pmsav7_dregion); 348 memset(env->pmsav8.rlar[M_REG_NS], 0, 349 sizeof(*env->pmsav8.rlar[M_REG_NS]) 350 * cpu->pmsav7_dregion); 351 if (arm_feature(env, ARM_FEATURE_M_SECURITY)) { 352 memset(env->pmsav8.rbar[M_REG_S], 0, 353 sizeof(*env->pmsav8.rbar[M_REG_S]) 354 * cpu->pmsav7_dregion); 355 memset(env->pmsav8.rlar[M_REG_S], 0, 356 sizeof(*env->pmsav8.rlar[M_REG_S]) 357 * cpu->pmsav7_dregion); 358 } 359 } else if (arm_feature(env, ARM_FEATURE_V7)) { 360 memset(env->pmsav7.drbar, 0, 361 sizeof(*env->pmsav7.drbar) * cpu->pmsav7_dregion); 362 memset(env->pmsav7.drsr, 0, 363 sizeof(*env->pmsav7.drsr) * cpu->pmsav7_dregion); 364 memset(env->pmsav7.dracr, 0, 365 sizeof(*env->pmsav7.dracr) * cpu->pmsav7_dregion); 366 } 367 } 368 env->pmsav7.rnr[M_REG_NS] = 0; 369 env->pmsav7.rnr[M_REG_S] = 0; 370 env->pmsav8.mair0[M_REG_NS] = 0; 371 env->pmsav8.mair0[M_REG_S] = 0; 372 env->pmsav8.mair1[M_REG_NS] = 0; 373 env->pmsav8.mair1[M_REG_S] = 0; 374 } 375 376 if (arm_feature(env, ARM_FEATURE_M_SECURITY)) { 377 if (cpu->sau_sregion > 0) { 378 memset(env->sau.rbar, 0, sizeof(*env->sau.rbar) * cpu->sau_sregion); 379 memset(env->sau.rlar, 0, sizeof(*env->sau.rlar) * cpu->sau_sregion); 380 } 381 env->sau.rnr = 0; 382 /* SAU_CTRL reset value is IMPDEF; we choose 0, which is what 383 * the Cortex-M33 does. 384 */ 385 env->sau.ctrl = 0; 386 } 387 388 set_flush_to_zero(1, &env->vfp.standard_fp_status); 389 set_flush_inputs_to_zero(1, &env->vfp.standard_fp_status); 390 set_default_nan_mode(1, &env->vfp.standard_fp_status); 391 set_float_detect_tininess(float_tininess_before_rounding, 392 &env->vfp.fp_status); 393 set_float_detect_tininess(float_tininess_before_rounding, 394 &env->vfp.standard_fp_status); 395 set_float_detect_tininess(float_tininess_before_rounding, 396 &env->vfp.fp_status_f16); 397 #ifndef CONFIG_USER_ONLY 398 if (kvm_enabled()) { 399 kvm_arm_reset_vcpu(cpu); 400 } 401 #endif 402 403 hw_breakpoint_update_all(cpu); 404 hw_watchpoint_update_all(cpu); 405 arm_rebuild_hflags(env); 406 } 407 408 static inline bool arm_excp_unmasked(CPUState *cs, unsigned int excp_idx, 409 unsigned int target_el, 410 unsigned int cur_el, bool secure, 411 uint64_t hcr_el2) 412 { 413 CPUARMState *env = cs->env_ptr; 414 bool pstate_unmasked; 415 bool unmasked = false; 416 417 /* 418 * Don't take exceptions if they target a lower EL. 419 * This check should catch any exceptions that would not be taken 420 * but left pending. 421 */ 422 if (cur_el > target_el) { 423 return false; 424 } 425 426 switch (excp_idx) { 427 case EXCP_FIQ: 428 pstate_unmasked = !(env->daif & PSTATE_F); 429 break; 430 431 case EXCP_IRQ: 432 pstate_unmasked = !(env->daif & PSTATE_I); 433 break; 434 435 case EXCP_VFIQ: 436 if (secure || !(hcr_el2 & HCR_FMO) || (hcr_el2 & HCR_TGE)) { 437 /* VFIQs are only taken when hypervized and non-secure. */ 438 return false; 439 } 440 return !(env->daif & PSTATE_F); 441 case EXCP_VIRQ: 442 if (secure || !(hcr_el2 & HCR_IMO) || (hcr_el2 & HCR_TGE)) { 443 /* VIRQs are only taken when hypervized and non-secure. */ 444 return false; 445 } 446 return !(env->daif & PSTATE_I); 447 default: 448 g_assert_not_reached(); 449 } 450 451 /* 452 * Use the target EL, current execution state and SCR/HCR settings to 453 * determine whether the corresponding CPSR bit is used to mask the 454 * interrupt. 455 */ 456 if ((target_el > cur_el) && (target_el != 1)) { 457 /* Exceptions targeting a higher EL may not be maskable */ 458 if (arm_feature(env, ARM_FEATURE_AARCH64)) { 459 /* 460 * 64-bit masking rules are simple: exceptions to EL3 461 * can't be masked, and exceptions to EL2 can only be 462 * masked from Secure state. The HCR and SCR settings 463 * don't affect the masking logic, only the interrupt routing. 464 */ 465 if (target_el == 3 || !secure) { 466 unmasked = true; 467 } 468 } else { 469 /* 470 * The old 32-bit-only environment has a more complicated 471 * masking setup. HCR and SCR bits not only affect interrupt 472 * routing but also change the behaviour of masking. 473 */ 474 bool hcr, scr; 475 476 switch (excp_idx) { 477 case EXCP_FIQ: 478 /* 479 * If FIQs are routed to EL3 or EL2 then there are cases where 480 * we override the CPSR.F in determining if the exception is 481 * masked or not. If neither of these are set then we fall back 482 * to the CPSR.F setting otherwise we further assess the state 483 * below. 484 */ 485 hcr = hcr_el2 & HCR_FMO; 486 scr = (env->cp15.scr_el3 & SCR_FIQ); 487 488 /* 489 * When EL3 is 32-bit, the SCR.FW bit controls whether the 490 * CPSR.F bit masks FIQ interrupts when taken in non-secure 491 * state. If SCR.FW is set then FIQs can be masked by CPSR.F 492 * when non-secure but only when FIQs are only routed to EL3. 493 */ 494 scr = scr && !((env->cp15.scr_el3 & SCR_FW) && !hcr); 495 break; 496 case EXCP_IRQ: 497 /* 498 * When EL3 execution state is 32-bit, if HCR.IMO is set then 499 * we may override the CPSR.I masking when in non-secure state. 500 * The SCR.IRQ setting has already been taken into consideration 501 * when setting the target EL, so it does not have a further 502 * affect here. 503 */ 504 hcr = hcr_el2 & HCR_IMO; 505 scr = false; 506 break; 507 default: 508 g_assert_not_reached(); 509 } 510 511 if ((scr || hcr) && !secure) { 512 unmasked = true; 513 } 514 } 515 } 516 517 /* 518 * The PSTATE bits only mask the interrupt if we have not overriden the 519 * ability above. 520 */ 521 return unmasked || pstate_unmasked; 522 } 523 524 bool arm_cpu_exec_interrupt(CPUState *cs, int interrupt_request) 525 { 526 CPUClass *cc = CPU_GET_CLASS(cs); 527 CPUARMState *env = cs->env_ptr; 528 uint32_t cur_el = arm_current_el(env); 529 bool secure = arm_is_secure(env); 530 uint64_t hcr_el2 = arm_hcr_el2_eff(env); 531 uint32_t target_el; 532 uint32_t excp_idx; 533 534 /* The prioritization of interrupts is IMPLEMENTATION DEFINED. */ 535 536 if (interrupt_request & CPU_INTERRUPT_FIQ) { 537 excp_idx = EXCP_FIQ; 538 target_el = arm_phys_excp_target_el(cs, excp_idx, cur_el, secure); 539 if (arm_excp_unmasked(cs, excp_idx, target_el, 540 cur_el, secure, hcr_el2)) { 541 goto found; 542 } 543 } 544 if (interrupt_request & CPU_INTERRUPT_HARD) { 545 excp_idx = EXCP_IRQ; 546 target_el = arm_phys_excp_target_el(cs, excp_idx, cur_el, secure); 547 if (arm_excp_unmasked(cs, excp_idx, target_el, 548 cur_el, secure, hcr_el2)) { 549 goto found; 550 } 551 } 552 if (interrupt_request & CPU_INTERRUPT_VIRQ) { 553 excp_idx = EXCP_VIRQ; 554 target_el = 1; 555 if (arm_excp_unmasked(cs, excp_idx, target_el, 556 cur_el, secure, hcr_el2)) { 557 goto found; 558 } 559 } 560 if (interrupt_request & CPU_INTERRUPT_VFIQ) { 561 excp_idx = EXCP_VFIQ; 562 target_el = 1; 563 if (arm_excp_unmasked(cs, excp_idx, target_el, 564 cur_el, secure, hcr_el2)) { 565 goto found; 566 } 567 } 568 return false; 569 570 found: 571 cs->exception_index = excp_idx; 572 env->exception.target_el = target_el; 573 cc->do_interrupt(cs); 574 return true; 575 } 576 577 #if !defined(CONFIG_USER_ONLY) || !defined(TARGET_AARCH64) 578 static bool arm_v7m_cpu_exec_interrupt(CPUState *cs, int interrupt_request) 579 { 580 CPUClass *cc = CPU_GET_CLASS(cs); 581 ARMCPU *cpu = ARM_CPU(cs); 582 CPUARMState *env = &cpu->env; 583 bool ret = false; 584 585 /* 586 * ARMv7-M interrupt masking works differently than -A or -R. 587 * There is no FIQ/IRQ distinction. Instead of I and F bits 588 * masking FIQ and IRQ interrupts, an exception is taken only 589 * if it is higher priority than the current execution priority 590 * (which depends on state like BASEPRI, FAULTMASK and the 591 * currently active exception). 592 */ 593 if (interrupt_request & CPU_INTERRUPT_HARD 594 && (armv7m_nvic_can_take_pending_exception(env->nvic))) { 595 cs->exception_index = EXCP_IRQ; 596 cc->do_interrupt(cs); 597 ret = true; 598 } 599 return ret; 600 } 601 #endif 602 603 void arm_cpu_update_virq(ARMCPU *cpu) 604 { 605 /* 606 * Update the interrupt level for VIRQ, which is the logical OR of 607 * the HCR_EL2.VI bit and the input line level from the GIC. 608 */ 609 CPUARMState *env = &cpu->env; 610 CPUState *cs = CPU(cpu); 611 612 bool new_state = (env->cp15.hcr_el2 & HCR_VI) || 613 (env->irq_line_state & CPU_INTERRUPT_VIRQ); 614 615 if (new_state != ((cs->interrupt_request & CPU_INTERRUPT_VIRQ) != 0)) { 616 if (new_state) { 617 cpu_interrupt(cs, CPU_INTERRUPT_VIRQ); 618 } else { 619 cpu_reset_interrupt(cs, CPU_INTERRUPT_VIRQ); 620 } 621 } 622 } 623 624 void arm_cpu_update_vfiq(ARMCPU *cpu) 625 { 626 /* 627 * Update the interrupt level for VFIQ, which is the logical OR of 628 * the HCR_EL2.VF bit and the input line level from the GIC. 629 */ 630 CPUARMState *env = &cpu->env; 631 CPUState *cs = CPU(cpu); 632 633 bool new_state = (env->cp15.hcr_el2 & HCR_VF) || 634 (env->irq_line_state & CPU_INTERRUPT_VFIQ); 635 636 if (new_state != ((cs->interrupt_request & CPU_INTERRUPT_VFIQ) != 0)) { 637 if (new_state) { 638 cpu_interrupt(cs, CPU_INTERRUPT_VFIQ); 639 } else { 640 cpu_reset_interrupt(cs, CPU_INTERRUPT_VFIQ); 641 } 642 } 643 } 644 645 #ifndef CONFIG_USER_ONLY 646 static void arm_cpu_set_irq(void *opaque, int irq, int level) 647 { 648 ARMCPU *cpu = opaque; 649 CPUARMState *env = &cpu->env; 650 CPUState *cs = CPU(cpu); 651 static const int mask[] = { 652 [ARM_CPU_IRQ] = CPU_INTERRUPT_HARD, 653 [ARM_CPU_FIQ] = CPU_INTERRUPT_FIQ, 654 [ARM_CPU_VIRQ] = CPU_INTERRUPT_VIRQ, 655 [ARM_CPU_VFIQ] = CPU_INTERRUPT_VFIQ 656 }; 657 658 if (level) { 659 env->irq_line_state |= mask[irq]; 660 } else { 661 env->irq_line_state &= ~mask[irq]; 662 } 663 664 switch (irq) { 665 case ARM_CPU_VIRQ: 666 assert(arm_feature(env, ARM_FEATURE_EL2)); 667 arm_cpu_update_virq(cpu); 668 break; 669 case ARM_CPU_VFIQ: 670 assert(arm_feature(env, ARM_FEATURE_EL2)); 671 arm_cpu_update_vfiq(cpu); 672 break; 673 case ARM_CPU_IRQ: 674 case ARM_CPU_FIQ: 675 if (level) { 676 cpu_interrupt(cs, mask[irq]); 677 } else { 678 cpu_reset_interrupt(cs, mask[irq]); 679 } 680 break; 681 default: 682 g_assert_not_reached(); 683 } 684 } 685 686 static void arm_cpu_kvm_set_irq(void *opaque, int irq, int level) 687 { 688 #ifdef CONFIG_KVM 689 ARMCPU *cpu = opaque; 690 CPUARMState *env = &cpu->env; 691 CPUState *cs = CPU(cpu); 692 uint32_t linestate_bit; 693 int irq_id; 694 695 switch (irq) { 696 case ARM_CPU_IRQ: 697 irq_id = KVM_ARM_IRQ_CPU_IRQ; 698 linestate_bit = CPU_INTERRUPT_HARD; 699 break; 700 case ARM_CPU_FIQ: 701 irq_id = KVM_ARM_IRQ_CPU_FIQ; 702 linestate_bit = CPU_INTERRUPT_FIQ; 703 break; 704 default: 705 g_assert_not_reached(); 706 } 707 708 if (level) { 709 env->irq_line_state |= linestate_bit; 710 } else { 711 env->irq_line_state &= ~linestate_bit; 712 } 713 kvm_arm_set_irq(cs->cpu_index, KVM_ARM_IRQ_TYPE_CPU, irq_id, !!level); 714 #endif 715 } 716 717 static bool arm_cpu_virtio_is_big_endian(CPUState *cs) 718 { 719 ARMCPU *cpu = ARM_CPU(cs); 720 CPUARMState *env = &cpu->env; 721 722 cpu_synchronize_state(cs); 723 return arm_cpu_data_is_big_endian(env); 724 } 725 726 #endif 727 728 static inline void set_feature(CPUARMState *env, int feature) 729 { 730 env->features |= 1ULL << feature; 731 } 732 733 static inline void unset_feature(CPUARMState *env, int feature) 734 { 735 env->features &= ~(1ULL << feature); 736 } 737 738 static int 739 print_insn_thumb1(bfd_vma pc, disassemble_info *info) 740 { 741 return print_insn_arm(pc | 1, info); 742 } 743 744 static void arm_disas_set_info(CPUState *cpu, disassemble_info *info) 745 { 746 ARMCPU *ac = ARM_CPU(cpu); 747 CPUARMState *env = &ac->env; 748 bool sctlr_b; 749 750 if (is_a64(env)) { 751 /* We might not be compiled with the A64 disassembler 752 * because it needs a C++ compiler. Leave print_insn 753 * unset in this case to use the caller default behaviour. 754 */ 755 #if defined(CONFIG_ARM_A64_DIS) 756 info->print_insn = print_insn_arm_a64; 757 #endif 758 info->cap_arch = CS_ARCH_ARM64; 759 info->cap_insn_unit = 4; 760 info->cap_insn_split = 4; 761 } else { 762 int cap_mode; 763 if (env->thumb) { 764 info->print_insn = print_insn_thumb1; 765 info->cap_insn_unit = 2; 766 info->cap_insn_split = 4; 767 cap_mode = CS_MODE_THUMB; 768 } else { 769 info->print_insn = print_insn_arm; 770 info->cap_insn_unit = 4; 771 info->cap_insn_split = 4; 772 cap_mode = CS_MODE_ARM; 773 } 774 if (arm_feature(env, ARM_FEATURE_V8)) { 775 cap_mode |= CS_MODE_V8; 776 } 777 if (arm_feature(env, ARM_FEATURE_M)) { 778 cap_mode |= CS_MODE_MCLASS; 779 } 780 info->cap_arch = CS_ARCH_ARM; 781 info->cap_mode = cap_mode; 782 } 783 784 sctlr_b = arm_sctlr_b(env); 785 if (bswap_code(sctlr_b)) { 786 #ifdef TARGET_WORDS_BIGENDIAN 787 info->endian = BFD_ENDIAN_LITTLE; 788 #else 789 info->endian = BFD_ENDIAN_BIG; 790 #endif 791 } 792 info->flags &= ~INSN_ARM_BE32; 793 #ifndef CONFIG_USER_ONLY 794 if (sctlr_b) { 795 info->flags |= INSN_ARM_BE32; 796 } 797 #endif 798 } 799 800 #ifdef TARGET_AARCH64 801 802 static void aarch64_cpu_dump_state(CPUState *cs, FILE *f, int flags) 803 { 804 ARMCPU *cpu = ARM_CPU(cs); 805 CPUARMState *env = &cpu->env; 806 uint32_t psr = pstate_read(env); 807 int i; 808 int el = arm_current_el(env); 809 const char *ns_status; 810 811 qemu_fprintf(f, " PC=%016" PRIx64 " ", env->pc); 812 for (i = 0; i < 32; i++) { 813 if (i == 31) { 814 qemu_fprintf(f, " SP=%016" PRIx64 "\n", env->xregs[i]); 815 } else { 816 qemu_fprintf(f, "X%02d=%016" PRIx64 "%s", i, env->xregs[i], 817 (i + 2) % 3 ? " " : "\n"); 818 } 819 } 820 821 if (arm_feature(env, ARM_FEATURE_EL3) && el != 3) { 822 ns_status = env->cp15.scr_el3 & SCR_NS ? "NS " : "S "; 823 } else { 824 ns_status = ""; 825 } 826 qemu_fprintf(f, "PSTATE=%08x %c%c%c%c %sEL%d%c", 827 psr, 828 psr & PSTATE_N ? 'N' : '-', 829 psr & PSTATE_Z ? 'Z' : '-', 830 psr & PSTATE_C ? 'C' : '-', 831 psr & PSTATE_V ? 'V' : '-', 832 ns_status, 833 el, 834 psr & PSTATE_SP ? 'h' : 't'); 835 836 if (cpu_isar_feature(aa64_bti, cpu)) { 837 qemu_fprintf(f, " BTYPE=%d", (psr & PSTATE_BTYPE) >> 10); 838 } 839 if (!(flags & CPU_DUMP_FPU)) { 840 qemu_fprintf(f, "\n"); 841 return; 842 } 843 if (fp_exception_el(env, el) != 0) { 844 qemu_fprintf(f, " FPU disabled\n"); 845 return; 846 } 847 qemu_fprintf(f, " FPCR=%08x FPSR=%08x\n", 848 vfp_get_fpcr(env), vfp_get_fpsr(env)); 849 850 if (cpu_isar_feature(aa64_sve, cpu) && sve_exception_el(env, el) == 0) { 851 int j, zcr_len = sve_zcr_len_for_el(env, el); 852 853 for (i = 0; i <= FFR_PRED_NUM; i++) { 854 bool eol; 855 if (i == FFR_PRED_NUM) { 856 qemu_fprintf(f, "FFR="); 857 /* It's last, so end the line. */ 858 eol = true; 859 } else { 860 qemu_fprintf(f, "P%02d=", i); 861 switch (zcr_len) { 862 case 0: 863 eol = i % 8 == 7; 864 break; 865 case 1: 866 eol = i % 6 == 5; 867 break; 868 case 2: 869 case 3: 870 eol = i % 3 == 2; 871 break; 872 default: 873 /* More than one quadword per predicate. */ 874 eol = true; 875 break; 876 } 877 } 878 for (j = zcr_len / 4; j >= 0; j--) { 879 int digits; 880 if (j * 4 + 4 <= zcr_len + 1) { 881 digits = 16; 882 } else { 883 digits = (zcr_len % 4 + 1) * 4; 884 } 885 qemu_fprintf(f, "%0*" PRIx64 "%s", digits, 886 env->vfp.pregs[i].p[j], 887 j ? ":" : eol ? "\n" : " "); 888 } 889 } 890 891 for (i = 0; i < 32; i++) { 892 if (zcr_len == 0) { 893 qemu_fprintf(f, "Z%02d=%016" PRIx64 ":%016" PRIx64 "%s", 894 i, env->vfp.zregs[i].d[1], 895 env->vfp.zregs[i].d[0], i & 1 ? "\n" : " "); 896 } else if (zcr_len == 1) { 897 qemu_fprintf(f, "Z%02d=%016" PRIx64 ":%016" PRIx64 898 ":%016" PRIx64 ":%016" PRIx64 "\n", 899 i, env->vfp.zregs[i].d[3], env->vfp.zregs[i].d[2], 900 env->vfp.zregs[i].d[1], env->vfp.zregs[i].d[0]); 901 } else { 902 for (j = zcr_len; j >= 0; j--) { 903 bool odd = (zcr_len - j) % 2 != 0; 904 if (j == zcr_len) { 905 qemu_fprintf(f, "Z%02d[%x-%x]=", i, j, j - 1); 906 } else if (!odd) { 907 if (j > 0) { 908 qemu_fprintf(f, " [%x-%x]=", j, j - 1); 909 } else { 910 qemu_fprintf(f, " [%x]=", j); 911 } 912 } 913 qemu_fprintf(f, "%016" PRIx64 ":%016" PRIx64 "%s", 914 env->vfp.zregs[i].d[j * 2 + 1], 915 env->vfp.zregs[i].d[j * 2], 916 odd || j == 0 ? "\n" : ":"); 917 } 918 } 919 } 920 } else { 921 for (i = 0; i < 32; i++) { 922 uint64_t *q = aa64_vfp_qreg(env, i); 923 qemu_fprintf(f, "Q%02d=%016" PRIx64 ":%016" PRIx64 "%s", 924 i, q[1], q[0], (i & 1 ? "\n" : " ")); 925 } 926 } 927 } 928 929 #else 930 931 static inline void aarch64_cpu_dump_state(CPUState *cs, FILE *f, int flags) 932 { 933 g_assert_not_reached(); 934 } 935 936 #endif 937 938 static void arm_cpu_dump_state(CPUState *cs, FILE *f, int flags) 939 { 940 ARMCPU *cpu = ARM_CPU(cs); 941 CPUARMState *env = &cpu->env; 942 int i; 943 944 if (is_a64(env)) { 945 aarch64_cpu_dump_state(cs, f, flags); 946 return; 947 } 948 949 for (i = 0; i < 16; i++) { 950 qemu_fprintf(f, "R%02d=%08x", i, env->regs[i]); 951 if ((i % 4) == 3) { 952 qemu_fprintf(f, "\n"); 953 } else { 954 qemu_fprintf(f, " "); 955 } 956 } 957 958 if (arm_feature(env, ARM_FEATURE_M)) { 959 uint32_t xpsr = xpsr_read(env); 960 const char *mode; 961 const char *ns_status = ""; 962 963 if (arm_feature(env, ARM_FEATURE_M_SECURITY)) { 964 ns_status = env->v7m.secure ? "S " : "NS "; 965 } 966 967 if (xpsr & XPSR_EXCP) { 968 mode = "handler"; 969 } else { 970 if (env->v7m.control[env->v7m.secure] & R_V7M_CONTROL_NPRIV_MASK) { 971 mode = "unpriv-thread"; 972 } else { 973 mode = "priv-thread"; 974 } 975 } 976 977 qemu_fprintf(f, "XPSR=%08x %c%c%c%c %c %s%s\n", 978 xpsr, 979 xpsr & XPSR_N ? 'N' : '-', 980 xpsr & XPSR_Z ? 'Z' : '-', 981 xpsr & XPSR_C ? 'C' : '-', 982 xpsr & XPSR_V ? 'V' : '-', 983 xpsr & XPSR_T ? 'T' : 'A', 984 ns_status, 985 mode); 986 } else { 987 uint32_t psr = cpsr_read(env); 988 const char *ns_status = ""; 989 990 if (arm_feature(env, ARM_FEATURE_EL3) && 991 (psr & CPSR_M) != ARM_CPU_MODE_MON) { 992 ns_status = env->cp15.scr_el3 & SCR_NS ? "NS " : "S "; 993 } 994 995 qemu_fprintf(f, "PSR=%08x %c%c%c%c %c %s%s%d\n", 996 psr, 997 psr & CPSR_N ? 'N' : '-', 998 psr & CPSR_Z ? 'Z' : '-', 999 psr & CPSR_C ? 'C' : '-', 1000 psr & CPSR_V ? 'V' : '-', 1001 psr & CPSR_T ? 'T' : 'A', 1002 ns_status, 1003 aarch32_mode_name(psr), (psr & 0x10) ? 32 : 26); 1004 } 1005 1006 if (flags & CPU_DUMP_FPU) { 1007 int numvfpregs = 0; 1008 if (cpu_isar_feature(aa32_simd_r32, cpu)) { 1009 numvfpregs = 32; 1010 } else if (cpu_isar_feature(aa32_vfp_simd, cpu)) { 1011 numvfpregs = 16; 1012 } 1013 for (i = 0; i < numvfpregs; i++) { 1014 uint64_t v = *aa32_vfp_dreg(env, i); 1015 qemu_fprintf(f, "s%02d=%08x s%02d=%08x d%02d=%016" PRIx64 "\n", 1016 i * 2, (uint32_t)v, 1017 i * 2 + 1, (uint32_t)(v >> 32), 1018 i, v); 1019 } 1020 qemu_fprintf(f, "FPSCR: %08x\n", vfp_get_fpscr(env)); 1021 } 1022 } 1023 1024 uint64_t arm_cpu_mp_affinity(int idx, uint8_t clustersz) 1025 { 1026 uint32_t Aff1 = idx / clustersz; 1027 uint32_t Aff0 = idx % clustersz; 1028 return (Aff1 << ARM_AFF1_SHIFT) | Aff0; 1029 } 1030 1031 static void cpreg_hashtable_data_destroy(gpointer data) 1032 { 1033 /* 1034 * Destroy function for cpu->cp_regs hashtable data entries. 1035 * We must free the name string because it was g_strdup()ed in 1036 * add_cpreg_to_hashtable(). It's OK to cast away the 'const' 1037 * from r->name because we know we definitely allocated it. 1038 */ 1039 ARMCPRegInfo *r = data; 1040 1041 g_free((void *)r->name); 1042 g_free(r); 1043 } 1044 1045 static void arm_cpu_initfn(Object *obj) 1046 { 1047 ARMCPU *cpu = ARM_CPU(obj); 1048 1049 cpu_set_cpustate_pointers(cpu); 1050 cpu->cp_regs = g_hash_table_new_full(g_int_hash, g_int_equal, 1051 g_free, cpreg_hashtable_data_destroy); 1052 1053 QLIST_INIT(&cpu->pre_el_change_hooks); 1054 QLIST_INIT(&cpu->el_change_hooks); 1055 1056 #ifndef CONFIG_USER_ONLY 1057 /* Our inbound IRQ and FIQ lines */ 1058 if (kvm_enabled()) { 1059 /* VIRQ and VFIQ are unused with KVM but we add them to maintain 1060 * the same interface as non-KVM CPUs. 1061 */ 1062 qdev_init_gpio_in(DEVICE(cpu), arm_cpu_kvm_set_irq, 4); 1063 } else { 1064 qdev_init_gpio_in(DEVICE(cpu), arm_cpu_set_irq, 4); 1065 } 1066 1067 qdev_init_gpio_out(DEVICE(cpu), cpu->gt_timer_outputs, 1068 ARRAY_SIZE(cpu->gt_timer_outputs)); 1069 1070 qdev_init_gpio_out_named(DEVICE(cpu), &cpu->gicv3_maintenance_interrupt, 1071 "gicv3-maintenance-interrupt", 1); 1072 qdev_init_gpio_out_named(DEVICE(cpu), &cpu->pmu_interrupt, 1073 "pmu-interrupt", 1); 1074 #endif 1075 1076 /* DTB consumers generally don't in fact care what the 'compatible' 1077 * string is, so always provide some string and trust that a hypothetical 1078 * picky DTB consumer will also provide a helpful error message. 1079 */ 1080 cpu->dtb_compatible = "qemu,unknown"; 1081 cpu->psci_version = 1; /* By default assume PSCI v0.1 */ 1082 cpu->kvm_target = QEMU_KVM_ARM_TARGET_NONE; 1083 1084 if (tcg_enabled()) { 1085 cpu->psci_version = 2; /* TCG implements PSCI 0.2 */ 1086 } 1087 } 1088 1089 static Property arm_cpu_gt_cntfrq_property = 1090 DEFINE_PROP_UINT64("cntfrq", ARMCPU, gt_cntfrq_hz, 1091 NANOSECONDS_PER_SECOND / GTIMER_SCALE); 1092 1093 static Property arm_cpu_reset_cbar_property = 1094 DEFINE_PROP_UINT64("reset-cbar", ARMCPU, reset_cbar, 0); 1095 1096 static Property arm_cpu_reset_hivecs_property = 1097 DEFINE_PROP_BOOL("reset-hivecs", ARMCPU, reset_hivecs, false); 1098 1099 static Property arm_cpu_rvbar_property = 1100 DEFINE_PROP_UINT64("rvbar", ARMCPU, rvbar, 0); 1101 1102 #ifndef CONFIG_USER_ONLY 1103 static Property arm_cpu_has_el2_property = 1104 DEFINE_PROP_BOOL("has_el2", ARMCPU, has_el2, true); 1105 1106 static Property arm_cpu_has_el3_property = 1107 DEFINE_PROP_BOOL("has_el3", ARMCPU, has_el3, true); 1108 #endif 1109 1110 static Property arm_cpu_cfgend_property = 1111 DEFINE_PROP_BOOL("cfgend", ARMCPU, cfgend, false); 1112 1113 static Property arm_cpu_has_vfp_property = 1114 DEFINE_PROP_BOOL("vfp", ARMCPU, has_vfp, true); 1115 1116 static Property arm_cpu_has_neon_property = 1117 DEFINE_PROP_BOOL("neon", ARMCPU, has_neon, true); 1118 1119 static Property arm_cpu_has_dsp_property = 1120 DEFINE_PROP_BOOL("dsp", ARMCPU, has_dsp, true); 1121 1122 static Property arm_cpu_has_mpu_property = 1123 DEFINE_PROP_BOOL("has-mpu", ARMCPU, has_mpu, true); 1124 1125 /* This is like DEFINE_PROP_UINT32 but it doesn't set the default value, 1126 * because the CPU initfn will have already set cpu->pmsav7_dregion to 1127 * the right value for that particular CPU type, and we don't want 1128 * to override that with an incorrect constant value. 1129 */ 1130 static Property arm_cpu_pmsav7_dregion_property = 1131 DEFINE_PROP_UNSIGNED_NODEFAULT("pmsav7-dregion", ARMCPU, 1132 pmsav7_dregion, 1133 qdev_prop_uint32, uint32_t); 1134 1135 static bool arm_get_pmu(Object *obj, Error **errp) 1136 { 1137 ARMCPU *cpu = ARM_CPU(obj); 1138 1139 return cpu->has_pmu; 1140 } 1141 1142 static void arm_set_pmu(Object *obj, bool value, Error **errp) 1143 { 1144 ARMCPU *cpu = ARM_CPU(obj); 1145 1146 if (value) { 1147 if (kvm_enabled() && !kvm_arm_pmu_supported(CPU(cpu))) { 1148 error_setg(errp, "'pmu' feature not supported by KVM on this host"); 1149 return; 1150 } 1151 set_feature(&cpu->env, ARM_FEATURE_PMU); 1152 } else { 1153 unset_feature(&cpu->env, ARM_FEATURE_PMU); 1154 } 1155 cpu->has_pmu = value; 1156 } 1157 1158 unsigned int gt_cntfrq_period_ns(ARMCPU *cpu) 1159 { 1160 /* 1161 * The exact approach to calculating guest ticks is: 1162 * 1163 * muldiv64(qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL), cpu->gt_cntfrq_hz, 1164 * NANOSECONDS_PER_SECOND); 1165 * 1166 * We don't do that. Rather we intentionally use integer division 1167 * truncation below and in the caller for the conversion of host monotonic 1168 * time to guest ticks to provide the exact inverse for the semantics of 1169 * the QEMUTimer scale factor. QEMUTimer's scale facter is an integer, so 1170 * it loses precision when representing frequencies where 1171 * `(NANOSECONDS_PER_SECOND % cpu->gt_cntfrq) > 0` holds. Failing to 1172 * provide an exact inverse leads to scheduling timers with negative 1173 * periods, which in turn leads to sticky behaviour in the guest. 1174 * 1175 * Finally, CNTFRQ is effectively capped at 1GHz to ensure our scale factor 1176 * cannot become zero. 1177 */ 1178 return NANOSECONDS_PER_SECOND > cpu->gt_cntfrq_hz ? 1179 NANOSECONDS_PER_SECOND / cpu->gt_cntfrq_hz : 1; 1180 } 1181 1182 void arm_cpu_post_init(Object *obj) 1183 { 1184 ARMCPU *cpu = ARM_CPU(obj); 1185 1186 /* M profile implies PMSA. We have to do this here rather than 1187 * in realize with the other feature-implication checks because 1188 * we look at the PMSA bit to see if we should add some properties. 1189 */ 1190 if (arm_feature(&cpu->env, ARM_FEATURE_M)) { 1191 set_feature(&cpu->env, ARM_FEATURE_PMSA); 1192 } 1193 1194 if (arm_feature(&cpu->env, ARM_FEATURE_CBAR) || 1195 arm_feature(&cpu->env, ARM_FEATURE_CBAR_RO)) { 1196 qdev_property_add_static(DEVICE(obj), &arm_cpu_reset_cbar_property); 1197 } 1198 1199 if (!arm_feature(&cpu->env, ARM_FEATURE_M)) { 1200 qdev_property_add_static(DEVICE(obj), &arm_cpu_reset_hivecs_property); 1201 } 1202 1203 if (arm_feature(&cpu->env, ARM_FEATURE_AARCH64)) { 1204 qdev_property_add_static(DEVICE(obj), &arm_cpu_rvbar_property); 1205 } 1206 1207 #ifndef CONFIG_USER_ONLY 1208 if (arm_feature(&cpu->env, ARM_FEATURE_EL3)) { 1209 /* Add the has_el3 state CPU property only if EL3 is allowed. This will 1210 * prevent "has_el3" from existing on CPUs which cannot support EL3. 1211 */ 1212 qdev_property_add_static(DEVICE(obj), &arm_cpu_has_el3_property); 1213 1214 object_property_add_link(obj, "secure-memory", 1215 TYPE_MEMORY_REGION, 1216 (Object **)&cpu->secure_memory, 1217 qdev_prop_allow_set_link_before_realize, 1218 OBJ_PROP_LINK_STRONG, 1219 &error_abort); 1220 } 1221 1222 if (arm_feature(&cpu->env, ARM_FEATURE_EL2)) { 1223 qdev_property_add_static(DEVICE(obj), &arm_cpu_has_el2_property); 1224 } 1225 #endif 1226 1227 if (arm_feature(&cpu->env, ARM_FEATURE_PMU)) { 1228 cpu->has_pmu = true; 1229 object_property_add_bool(obj, "pmu", arm_get_pmu, arm_set_pmu, 1230 &error_abort); 1231 } 1232 1233 /* 1234 * Allow user to turn off VFP and Neon support, but only for TCG -- 1235 * KVM does not currently allow us to lie to the guest about its 1236 * ID/feature registers, so the guest always sees what the host has. 1237 */ 1238 if (arm_feature(&cpu->env, ARM_FEATURE_AARCH64) 1239 ? cpu_isar_feature(aa64_fp_simd, cpu) 1240 : cpu_isar_feature(aa32_vfp, cpu)) { 1241 cpu->has_vfp = true; 1242 if (!kvm_enabled()) { 1243 qdev_property_add_static(DEVICE(obj), &arm_cpu_has_vfp_property); 1244 } 1245 } 1246 1247 if (arm_feature(&cpu->env, ARM_FEATURE_NEON)) { 1248 cpu->has_neon = true; 1249 if (!kvm_enabled()) { 1250 qdev_property_add_static(DEVICE(obj), &arm_cpu_has_neon_property); 1251 } 1252 } 1253 1254 if (arm_feature(&cpu->env, ARM_FEATURE_M) && 1255 arm_feature(&cpu->env, ARM_FEATURE_THUMB_DSP)) { 1256 qdev_property_add_static(DEVICE(obj), &arm_cpu_has_dsp_property); 1257 } 1258 1259 if (arm_feature(&cpu->env, ARM_FEATURE_PMSA)) { 1260 qdev_property_add_static(DEVICE(obj), &arm_cpu_has_mpu_property); 1261 if (arm_feature(&cpu->env, ARM_FEATURE_V7)) { 1262 qdev_property_add_static(DEVICE(obj), 1263 &arm_cpu_pmsav7_dregion_property); 1264 } 1265 } 1266 1267 if (arm_feature(&cpu->env, ARM_FEATURE_M_SECURITY)) { 1268 object_property_add_link(obj, "idau", TYPE_IDAU_INTERFACE, &cpu->idau, 1269 qdev_prop_allow_set_link_before_realize, 1270 OBJ_PROP_LINK_STRONG, 1271 &error_abort); 1272 /* 1273 * M profile: initial value of the Secure VTOR. We can't just use 1274 * a simple DEFINE_PROP_UINT32 for this because we want to permit 1275 * the property to be set after realize. 1276 */ 1277 object_property_add_uint32_ptr(obj, "init-svtor", 1278 &cpu->init_svtor, 1279 OBJ_PROP_FLAG_READWRITE, &error_abort); 1280 } 1281 1282 qdev_property_add_static(DEVICE(obj), &arm_cpu_cfgend_property); 1283 1284 if (arm_feature(&cpu->env, ARM_FEATURE_GENERIC_TIMER)) { 1285 qdev_property_add_static(DEVICE(cpu), &arm_cpu_gt_cntfrq_property); 1286 } 1287 } 1288 1289 static void arm_cpu_finalizefn(Object *obj) 1290 { 1291 ARMCPU *cpu = ARM_CPU(obj); 1292 ARMELChangeHook *hook, *next; 1293 1294 g_hash_table_destroy(cpu->cp_regs); 1295 1296 QLIST_FOREACH_SAFE(hook, &cpu->pre_el_change_hooks, node, next) { 1297 QLIST_REMOVE(hook, node); 1298 g_free(hook); 1299 } 1300 QLIST_FOREACH_SAFE(hook, &cpu->el_change_hooks, node, next) { 1301 QLIST_REMOVE(hook, node); 1302 g_free(hook); 1303 } 1304 #ifndef CONFIG_USER_ONLY 1305 if (cpu->pmu_timer) { 1306 timer_del(cpu->pmu_timer); 1307 timer_deinit(cpu->pmu_timer); 1308 timer_free(cpu->pmu_timer); 1309 } 1310 #endif 1311 } 1312 1313 void arm_cpu_finalize_features(ARMCPU *cpu, Error **errp) 1314 { 1315 Error *local_err = NULL; 1316 1317 if (arm_feature(&cpu->env, ARM_FEATURE_AARCH64)) { 1318 arm_cpu_sve_finalize(cpu, &local_err); 1319 if (local_err != NULL) { 1320 error_propagate(errp, local_err); 1321 return; 1322 } 1323 } 1324 } 1325 1326 static void arm_cpu_realizefn(DeviceState *dev, Error **errp) 1327 { 1328 CPUState *cs = CPU(dev); 1329 ARMCPU *cpu = ARM_CPU(dev); 1330 ARMCPUClass *acc = ARM_CPU_GET_CLASS(dev); 1331 CPUARMState *env = &cpu->env; 1332 int pagebits; 1333 Error *local_err = NULL; 1334 bool no_aa32 = false; 1335 1336 /* If we needed to query the host kernel for the CPU features 1337 * then it's possible that might have failed in the initfn, but 1338 * this is the first point where we can report it. 1339 */ 1340 if (cpu->host_cpu_probe_failed) { 1341 if (!kvm_enabled()) { 1342 error_setg(errp, "The 'host' CPU type can only be used with KVM"); 1343 } else { 1344 error_setg(errp, "Failed to retrieve host CPU features"); 1345 } 1346 return; 1347 } 1348 1349 #ifndef CONFIG_USER_ONLY 1350 /* The NVIC and M-profile CPU are two halves of a single piece of 1351 * hardware; trying to use one without the other is a command line 1352 * error and will result in segfaults if not caught here. 1353 */ 1354 if (arm_feature(env, ARM_FEATURE_M)) { 1355 if (!env->nvic) { 1356 error_setg(errp, "This board cannot be used with Cortex-M CPUs"); 1357 return; 1358 } 1359 } else { 1360 if (env->nvic) { 1361 error_setg(errp, "This board can only be used with Cortex-M CPUs"); 1362 return; 1363 } 1364 } 1365 1366 { 1367 uint64_t scale; 1368 1369 if (arm_feature(env, ARM_FEATURE_GENERIC_TIMER)) { 1370 if (!cpu->gt_cntfrq_hz) { 1371 error_setg(errp, "Invalid CNTFRQ: %"PRId64"Hz", 1372 cpu->gt_cntfrq_hz); 1373 return; 1374 } 1375 scale = gt_cntfrq_period_ns(cpu); 1376 } else { 1377 scale = GTIMER_SCALE; 1378 } 1379 1380 cpu->gt_timer[GTIMER_PHYS] = timer_new(QEMU_CLOCK_VIRTUAL, scale, 1381 arm_gt_ptimer_cb, cpu); 1382 cpu->gt_timer[GTIMER_VIRT] = timer_new(QEMU_CLOCK_VIRTUAL, scale, 1383 arm_gt_vtimer_cb, cpu); 1384 cpu->gt_timer[GTIMER_HYP] = timer_new(QEMU_CLOCK_VIRTUAL, scale, 1385 arm_gt_htimer_cb, cpu); 1386 cpu->gt_timer[GTIMER_SEC] = timer_new(QEMU_CLOCK_VIRTUAL, scale, 1387 arm_gt_stimer_cb, cpu); 1388 cpu->gt_timer[GTIMER_HYPVIRT] = timer_new(QEMU_CLOCK_VIRTUAL, scale, 1389 arm_gt_hvtimer_cb, cpu); 1390 } 1391 #endif 1392 1393 cpu_exec_realizefn(cs, &local_err); 1394 if (local_err != NULL) { 1395 error_propagate(errp, local_err); 1396 return; 1397 } 1398 1399 arm_cpu_finalize_features(cpu, &local_err); 1400 if (local_err != NULL) { 1401 error_propagate(errp, local_err); 1402 return; 1403 } 1404 1405 if (arm_feature(env, ARM_FEATURE_AARCH64) && 1406 cpu->has_vfp != cpu->has_neon) { 1407 /* 1408 * This is an architectural requirement for AArch64; AArch32 is 1409 * more flexible and permits VFP-no-Neon and Neon-no-VFP. 1410 */ 1411 error_setg(errp, 1412 "AArch64 CPUs must have both VFP and Neon or neither"); 1413 return; 1414 } 1415 1416 if (!cpu->has_vfp) { 1417 uint64_t t; 1418 uint32_t u; 1419 1420 t = cpu->isar.id_aa64isar1; 1421 t = FIELD_DP64(t, ID_AA64ISAR1, JSCVT, 0); 1422 cpu->isar.id_aa64isar1 = t; 1423 1424 t = cpu->isar.id_aa64pfr0; 1425 t = FIELD_DP64(t, ID_AA64PFR0, FP, 0xf); 1426 cpu->isar.id_aa64pfr0 = t; 1427 1428 u = cpu->isar.id_isar6; 1429 u = FIELD_DP32(u, ID_ISAR6, JSCVT, 0); 1430 cpu->isar.id_isar6 = u; 1431 1432 u = cpu->isar.mvfr0; 1433 u = FIELD_DP32(u, MVFR0, FPSP, 0); 1434 u = FIELD_DP32(u, MVFR0, FPDP, 0); 1435 u = FIELD_DP32(u, MVFR0, FPTRAP, 0); 1436 u = FIELD_DP32(u, MVFR0, FPDIVIDE, 0); 1437 u = FIELD_DP32(u, MVFR0, FPSQRT, 0); 1438 u = FIELD_DP32(u, MVFR0, FPSHVEC, 0); 1439 u = FIELD_DP32(u, MVFR0, FPROUND, 0); 1440 cpu->isar.mvfr0 = u; 1441 1442 u = cpu->isar.mvfr1; 1443 u = FIELD_DP32(u, MVFR1, FPFTZ, 0); 1444 u = FIELD_DP32(u, MVFR1, FPDNAN, 0); 1445 u = FIELD_DP32(u, MVFR1, FPHP, 0); 1446 cpu->isar.mvfr1 = u; 1447 1448 u = cpu->isar.mvfr2; 1449 u = FIELD_DP32(u, MVFR2, FPMISC, 0); 1450 cpu->isar.mvfr2 = u; 1451 } 1452 1453 if (!cpu->has_neon) { 1454 uint64_t t; 1455 uint32_t u; 1456 1457 unset_feature(env, ARM_FEATURE_NEON); 1458 1459 t = cpu->isar.id_aa64isar0; 1460 t = FIELD_DP64(t, ID_AA64ISAR0, DP, 0); 1461 cpu->isar.id_aa64isar0 = t; 1462 1463 t = cpu->isar.id_aa64isar1; 1464 t = FIELD_DP64(t, ID_AA64ISAR1, FCMA, 0); 1465 cpu->isar.id_aa64isar1 = t; 1466 1467 t = cpu->isar.id_aa64pfr0; 1468 t = FIELD_DP64(t, ID_AA64PFR0, ADVSIMD, 0xf); 1469 cpu->isar.id_aa64pfr0 = t; 1470 1471 u = cpu->isar.id_isar5; 1472 u = FIELD_DP32(u, ID_ISAR5, RDM, 0); 1473 u = FIELD_DP32(u, ID_ISAR5, VCMA, 0); 1474 cpu->isar.id_isar5 = u; 1475 1476 u = cpu->isar.id_isar6; 1477 u = FIELD_DP32(u, ID_ISAR6, DP, 0); 1478 u = FIELD_DP32(u, ID_ISAR6, FHM, 0); 1479 cpu->isar.id_isar6 = u; 1480 1481 u = cpu->isar.mvfr1; 1482 u = FIELD_DP32(u, MVFR1, SIMDLS, 0); 1483 u = FIELD_DP32(u, MVFR1, SIMDINT, 0); 1484 u = FIELD_DP32(u, MVFR1, SIMDSP, 0); 1485 u = FIELD_DP32(u, MVFR1, SIMDHP, 0); 1486 cpu->isar.mvfr1 = u; 1487 1488 u = cpu->isar.mvfr2; 1489 u = FIELD_DP32(u, MVFR2, SIMDMISC, 0); 1490 cpu->isar.mvfr2 = u; 1491 } 1492 1493 if (!cpu->has_neon && !cpu->has_vfp) { 1494 uint64_t t; 1495 uint32_t u; 1496 1497 t = cpu->isar.id_aa64isar0; 1498 t = FIELD_DP64(t, ID_AA64ISAR0, FHM, 0); 1499 cpu->isar.id_aa64isar0 = t; 1500 1501 t = cpu->isar.id_aa64isar1; 1502 t = FIELD_DP64(t, ID_AA64ISAR1, FRINTTS, 0); 1503 cpu->isar.id_aa64isar1 = t; 1504 1505 u = cpu->isar.mvfr0; 1506 u = FIELD_DP32(u, MVFR0, SIMDREG, 0); 1507 cpu->isar.mvfr0 = u; 1508 1509 /* Despite the name, this field covers both VFP and Neon */ 1510 u = cpu->isar.mvfr1; 1511 u = FIELD_DP32(u, MVFR1, SIMDFMAC, 0); 1512 cpu->isar.mvfr1 = u; 1513 } 1514 1515 if (arm_feature(env, ARM_FEATURE_M) && !cpu->has_dsp) { 1516 uint32_t u; 1517 1518 unset_feature(env, ARM_FEATURE_THUMB_DSP); 1519 1520 u = cpu->isar.id_isar1; 1521 u = FIELD_DP32(u, ID_ISAR1, EXTEND, 1); 1522 cpu->isar.id_isar1 = u; 1523 1524 u = cpu->isar.id_isar2; 1525 u = FIELD_DP32(u, ID_ISAR2, MULTU, 1); 1526 u = FIELD_DP32(u, ID_ISAR2, MULTS, 1); 1527 cpu->isar.id_isar2 = u; 1528 1529 u = cpu->isar.id_isar3; 1530 u = FIELD_DP32(u, ID_ISAR3, SIMD, 1); 1531 u = FIELD_DP32(u, ID_ISAR3, SATURATE, 0); 1532 cpu->isar.id_isar3 = u; 1533 } 1534 1535 /* Some features automatically imply others: */ 1536 if (arm_feature(env, ARM_FEATURE_V8)) { 1537 if (arm_feature(env, ARM_FEATURE_M)) { 1538 set_feature(env, ARM_FEATURE_V7); 1539 } else { 1540 set_feature(env, ARM_FEATURE_V7VE); 1541 } 1542 } 1543 1544 /* 1545 * There exist AArch64 cpus without AArch32 support. When KVM 1546 * queries ID_ISAR0_EL1 on such a host, the value is UNKNOWN. 1547 * Similarly, we cannot check ID_AA64PFR0 without AArch64 support. 1548 * As a general principle, we also do not make ID register 1549 * consistency checks anywhere unless using TCG, because only 1550 * for TCG would a consistency-check failure be a QEMU bug. 1551 */ 1552 if (arm_feature(&cpu->env, ARM_FEATURE_AARCH64)) { 1553 no_aa32 = !cpu_isar_feature(aa64_aa32, cpu); 1554 } 1555 1556 if (arm_feature(env, ARM_FEATURE_V7VE)) { 1557 /* v7 Virtualization Extensions. In real hardware this implies 1558 * EL2 and also the presence of the Security Extensions. 1559 * For QEMU, for backwards-compatibility we implement some 1560 * CPUs or CPU configs which have no actual EL2 or EL3 but do 1561 * include the various other features that V7VE implies. 1562 * Presence of EL2 itself is ARM_FEATURE_EL2, and of the 1563 * Security Extensions is ARM_FEATURE_EL3. 1564 */ 1565 assert(!tcg_enabled() || no_aa32 || 1566 cpu_isar_feature(aa32_arm_div, cpu)); 1567 set_feature(env, ARM_FEATURE_LPAE); 1568 set_feature(env, ARM_FEATURE_V7); 1569 } 1570 if (arm_feature(env, ARM_FEATURE_V7)) { 1571 set_feature(env, ARM_FEATURE_VAPA); 1572 set_feature(env, ARM_FEATURE_THUMB2); 1573 set_feature(env, ARM_FEATURE_MPIDR); 1574 if (!arm_feature(env, ARM_FEATURE_M)) { 1575 set_feature(env, ARM_FEATURE_V6K); 1576 } else { 1577 set_feature(env, ARM_FEATURE_V6); 1578 } 1579 1580 /* Always define VBAR for V7 CPUs even if it doesn't exist in 1581 * non-EL3 configs. This is needed by some legacy boards. 1582 */ 1583 set_feature(env, ARM_FEATURE_VBAR); 1584 } 1585 if (arm_feature(env, ARM_FEATURE_V6K)) { 1586 set_feature(env, ARM_FEATURE_V6); 1587 set_feature(env, ARM_FEATURE_MVFR); 1588 } 1589 if (arm_feature(env, ARM_FEATURE_V6)) { 1590 set_feature(env, ARM_FEATURE_V5); 1591 if (!arm_feature(env, ARM_FEATURE_M)) { 1592 assert(!tcg_enabled() || no_aa32 || 1593 cpu_isar_feature(aa32_jazelle, cpu)); 1594 set_feature(env, ARM_FEATURE_AUXCR); 1595 } 1596 } 1597 if (arm_feature(env, ARM_FEATURE_V5)) { 1598 set_feature(env, ARM_FEATURE_V4T); 1599 } 1600 if (arm_feature(env, ARM_FEATURE_LPAE)) { 1601 set_feature(env, ARM_FEATURE_V7MP); 1602 set_feature(env, ARM_FEATURE_PXN); 1603 } 1604 if (arm_feature(env, ARM_FEATURE_CBAR_RO)) { 1605 set_feature(env, ARM_FEATURE_CBAR); 1606 } 1607 if (arm_feature(env, ARM_FEATURE_THUMB2) && 1608 !arm_feature(env, ARM_FEATURE_M)) { 1609 set_feature(env, ARM_FEATURE_THUMB_DSP); 1610 } 1611 1612 /* 1613 * We rely on no XScale CPU having VFP so we can use the same bits in the 1614 * TB flags field for VECSTRIDE and XSCALE_CPAR. 1615 */ 1616 assert(arm_feature(&cpu->env, ARM_FEATURE_AARCH64) || 1617 !cpu_isar_feature(aa32_vfp_simd, cpu) || 1618 !arm_feature(env, ARM_FEATURE_XSCALE)); 1619 1620 if (arm_feature(env, ARM_FEATURE_V7) && 1621 !arm_feature(env, ARM_FEATURE_M) && 1622 !arm_feature(env, ARM_FEATURE_PMSA)) { 1623 /* v7VMSA drops support for the old ARMv5 tiny pages, so we 1624 * can use 4K pages. 1625 */ 1626 pagebits = 12; 1627 } else { 1628 /* For CPUs which might have tiny 1K pages, or which have an 1629 * MPU and might have small region sizes, stick with 1K pages. 1630 */ 1631 pagebits = 10; 1632 } 1633 if (!set_preferred_target_page_bits(pagebits)) { 1634 /* This can only ever happen for hotplugging a CPU, or if 1635 * the board code incorrectly creates a CPU which it has 1636 * promised via minimum_page_size that it will not. 1637 */ 1638 error_setg(errp, "This CPU requires a smaller page size than the " 1639 "system is using"); 1640 return; 1641 } 1642 1643 /* This cpu-id-to-MPIDR affinity is used only for TCG; KVM will override it. 1644 * We don't support setting cluster ID ([16..23]) (known as Aff2 1645 * in later ARM ARM versions), or any of the higher affinity level fields, 1646 * so these bits always RAZ. 1647 */ 1648 if (cpu->mp_affinity == ARM64_AFFINITY_INVALID) { 1649 cpu->mp_affinity = arm_cpu_mp_affinity(cs->cpu_index, 1650 ARM_DEFAULT_CPUS_PER_CLUSTER); 1651 } 1652 1653 if (cpu->reset_hivecs) { 1654 cpu->reset_sctlr |= (1 << 13); 1655 } 1656 1657 if (cpu->cfgend) { 1658 if (arm_feature(&cpu->env, ARM_FEATURE_V7)) { 1659 cpu->reset_sctlr |= SCTLR_EE; 1660 } else { 1661 cpu->reset_sctlr |= SCTLR_B; 1662 } 1663 } 1664 1665 if (!cpu->has_el3) { 1666 /* If the has_el3 CPU property is disabled then we need to disable the 1667 * feature. 1668 */ 1669 unset_feature(env, ARM_FEATURE_EL3); 1670 1671 /* Disable the security extension feature bits in the processor feature 1672 * registers as well. These are id_pfr1[7:4] and id_aa64pfr0[15:12]. 1673 */ 1674 cpu->id_pfr1 &= ~0xf0; 1675 cpu->isar.id_aa64pfr0 &= ~0xf000; 1676 } 1677 1678 if (!cpu->has_el2) { 1679 unset_feature(env, ARM_FEATURE_EL2); 1680 } 1681 1682 if (!cpu->has_pmu) { 1683 unset_feature(env, ARM_FEATURE_PMU); 1684 } 1685 if (arm_feature(env, ARM_FEATURE_PMU)) { 1686 pmu_init(cpu); 1687 1688 if (!kvm_enabled()) { 1689 arm_register_pre_el_change_hook(cpu, &pmu_pre_el_change, 0); 1690 arm_register_el_change_hook(cpu, &pmu_post_el_change, 0); 1691 } 1692 1693 #ifndef CONFIG_USER_ONLY 1694 cpu->pmu_timer = timer_new_ns(QEMU_CLOCK_VIRTUAL, arm_pmu_timer_cb, 1695 cpu); 1696 #endif 1697 } else { 1698 cpu->isar.id_aa64dfr0 = 1699 FIELD_DP64(cpu->isar.id_aa64dfr0, ID_AA64DFR0, PMUVER, 0); 1700 cpu->isar.id_dfr0 = FIELD_DP32(cpu->isar.id_dfr0, ID_DFR0, PERFMON, 0); 1701 cpu->pmceid0 = 0; 1702 cpu->pmceid1 = 0; 1703 } 1704 1705 if (!arm_feature(env, ARM_FEATURE_EL2)) { 1706 /* Disable the hypervisor feature bits in the processor feature 1707 * registers if we don't have EL2. These are id_pfr1[15:12] and 1708 * id_aa64pfr0_el1[11:8]. 1709 */ 1710 cpu->isar.id_aa64pfr0 &= ~0xf00; 1711 cpu->id_pfr1 &= ~0xf000; 1712 } 1713 1714 /* MPU can be configured out of a PMSA CPU either by setting has-mpu 1715 * to false or by setting pmsav7-dregion to 0. 1716 */ 1717 if (!cpu->has_mpu) { 1718 cpu->pmsav7_dregion = 0; 1719 } 1720 if (cpu->pmsav7_dregion == 0) { 1721 cpu->has_mpu = false; 1722 } 1723 1724 if (arm_feature(env, ARM_FEATURE_PMSA) && 1725 arm_feature(env, ARM_FEATURE_V7)) { 1726 uint32_t nr = cpu->pmsav7_dregion; 1727 1728 if (nr > 0xff) { 1729 error_setg(errp, "PMSAv7 MPU #regions invalid %" PRIu32, nr); 1730 return; 1731 } 1732 1733 if (nr) { 1734 if (arm_feature(env, ARM_FEATURE_V8)) { 1735 /* PMSAv8 */ 1736 env->pmsav8.rbar[M_REG_NS] = g_new0(uint32_t, nr); 1737 env->pmsav8.rlar[M_REG_NS] = g_new0(uint32_t, nr); 1738 if (arm_feature(env, ARM_FEATURE_M_SECURITY)) { 1739 env->pmsav8.rbar[M_REG_S] = g_new0(uint32_t, nr); 1740 env->pmsav8.rlar[M_REG_S] = g_new0(uint32_t, nr); 1741 } 1742 } else { 1743 env->pmsav7.drbar = g_new0(uint32_t, nr); 1744 env->pmsav7.drsr = g_new0(uint32_t, nr); 1745 env->pmsav7.dracr = g_new0(uint32_t, nr); 1746 } 1747 } 1748 } 1749 1750 if (arm_feature(env, ARM_FEATURE_M_SECURITY)) { 1751 uint32_t nr = cpu->sau_sregion; 1752 1753 if (nr > 0xff) { 1754 error_setg(errp, "v8M SAU #regions invalid %" PRIu32, nr); 1755 return; 1756 } 1757 1758 if (nr) { 1759 env->sau.rbar = g_new0(uint32_t, nr); 1760 env->sau.rlar = g_new0(uint32_t, nr); 1761 } 1762 } 1763 1764 if (arm_feature(env, ARM_FEATURE_EL3)) { 1765 set_feature(env, ARM_FEATURE_VBAR); 1766 } 1767 1768 register_cp_regs_for_features(cpu); 1769 arm_cpu_register_gdb_regs_for_features(cpu); 1770 1771 init_cpreg_list(cpu); 1772 1773 #ifndef CONFIG_USER_ONLY 1774 MachineState *ms = MACHINE(qdev_get_machine()); 1775 unsigned int smp_cpus = ms->smp.cpus; 1776 1777 if (cpu->has_el3 || arm_feature(env, ARM_FEATURE_M_SECURITY)) { 1778 cs->num_ases = 2; 1779 1780 if (!cpu->secure_memory) { 1781 cpu->secure_memory = cs->memory; 1782 } 1783 cpu_address_space_init(cs, ARMASIdx_S, "cpu-secure-memory", 1784 cpu->secure_memory); 1785 } else { 1786 cs->num_ases = 1; 1787 } 1788 cpu_address_space_init(cs, ARMASIdx_NS, "cpu-memory", cs->memory); 1789 1790 /* No core_count specified, default to smp_cpus. */ 1791 if (cpu->core_count == -1) { 1792 cpu->core_count = smp_cpus; 1793 } 1794 #endif 1795 1796 qemu_init_vcpu(cs); 1797 cpu_reset(cs); 1798 1799 acc->parent_realize(dev, errp); 1800 } 1801 1802 static ObjectClass *arm_cpu_class_by_name(const char *cpu_model) 1803 { 1804 ObjectClass *oc; 1805 char *typename; 1806 char **cpuname; 1807 const char *cpunamestr; 1808 1809 cpuname = g_strsplit(cpu_model, ",", 1); 1810 cpunamestr = cpuname[0]; 1811 #ifdef CONFIG_USER_ONLY 1812 /* For backwards compatibility usermode emulation allows "-cpu any", 1813 * which has the same semantics as "-cpu max". 1814 */ 1815 if (!strcmp(cpunamestr, "any")) { 1816 cpunamestr = "max"; 1817 } 1818 #endif 1819 typename = g_strdup_printf(ARM_CPU_TYPE_NAME("%s"), cpunamestr); 1820 oc = object_class_by_name(typename); 1821 g_strfreev(cpuname); 1822 g_free(typename); 1823 if (!oc || !object_class_dynamic_cast(oc, TYPE_ARM_CPU) || 1824 object_class_is_abstract(oc)) { 1825 return NULL; 1826 } 1827 return oc; 1828 } 1829 1830 /* CPU models. These are not needed for the AArch64 linux-user build. */ 1831 #if !defined(CONFIG_USER_ONLY) || !defined(TARGET_AARCH64) 1832 1833 static void arm926_initfn(Object *obj) 1834 { 1835 ARMCPU *cpu = ARM_CPU(obj); 1836 1837 cpu->dtb_compatible = "arm,arm926"; 1838 set_feature(&cpu->env, ARM_FEATURE_V5); 1839 set_feature(&cpu->env, ARM_FEATURE_DUMMY_C15_REGS); 1840 set_feature(&cpu->env, ARM_FEATURE_CACHE_TEST_CLEAN); 1841 cpu->midr = 0x41069265; 1842 cpu->reset_fpsid = 0x41011090; 1843 cpu->ctr = 0x1dd20d2; 1844 cpu->reset_sctlr = 0x00090078; 1845 1846 /* 1847 * ARMv5 does not have the ID_ISAR registers, but we can still 1848 * set the field to indicate Jazelle support within QEMU. 1849 */ 1850 cpu->isar.id_isar1 = FIELD_DP32(cpu->isar.id_isar1, ID_ISAR1, JAZELLE, 1); 1851 /* 1852 * Similarly, we need to set MVFR0 fields to enable vfp and short vector 1853 * support even though ARMv5 doesn't have this register. 1854 */ 1855 cpu->isar.mvfr0 = FIELD_DP32(cpu->isar.mvfr0, MVFR0, FPSHVEC, 1); 1856 cpu->isar.mvfr0 = FIELD_DP32(cpu->isar.mvfr0, MVFR0, FPSP, 1); 1857 cpu->isar.mvfr0 = FIELD_DP32(cpu->isar.mvfr0, MVFR0, FPDP, 1); 1858 } 1859 1860 static void arm946_initfn(Object *obj) 1861 { 1862 ARMCPU *cpu = ARM_CPU(obj); 1863 1864 cpu->dtb_compatible = "arm,arm946"; 1865 set_feature(&cpu->env, ARM_FEATURE_V5); 1866 set_feature(&cpu->env, ARM_FEATURE_PMSA); 1867 set_feature(&cpu->env, ARM_FEATURE_DUMMY_C15_REGS); 1868 cpu->midr = 0x41059461; 1869 cpu->ctr = 0x0f004006; 1870 cpu->reset_sctlr = 0x00000078; 1871 } 1872 1873 static void arm1026_initfn(Object *obj) 1874 { 1875 ARMCPU *cpu = ARM_CPU(obj); 1876 1877 cpu->dtb_compatible = "arm,arm1026"; 1878 set_feature(&cpu->env, ARM_FEATURE_V5); 1879 set_feature(&cpu->env, ARM_FEATURE_AUXCR); 1880 set_feature(&cpu->env, ARM_FEATURE_DUMMY_C15_REGS); 1881 set_feature(&cpu->env, ARM_FEATURE_CACHE_TEST_CLEAN); 1882 cpu->midr = 0x4106a262; 1883 cpu->reset_fpsid = 0x410110a0; 1884 cpu->ctr = 0x1dd20d2; 1885 cpu->reset_sctlr = 0x00090078; 1886 cpu->reset_auxcr = 1; 1887 1888 /* 1889 * ARMv5 does not have the ID_ISAR registers, but we can still 1890 * set the field to indicate Jazelle support within QEMU. 1891 */ 1892 cpu->isar.id_isar1 = FIELD_DP32(cpu->isar.id_isar1, ID_ISAR1, JAZELLE, 1); 1893 /* 1894 * Similarly, we need to set MVFR0 fields to enable vfp and short vector 1895 * support even though ARMv5 doesn't have this register. 1896 */ 1897 cpu->isar.mvfr0 = FIELD_DP32(cpu->isar.mvfr0, MVFR0, FPSHVEC, 1); 1898 cpu->isar.mvfr0 = FIELD_DP32(cpu->isar.mvfr0, MVFR0, FPSP, 1); 1899 cpu->isar.mvfr0 = FIELD_DP32(cpu->isar.mvfr0, MVFR0, FPDP, 1); 1900 1901 { 1902 /* The 1026 had an IFAR at c6,c0,0,1 rather than the ARMv6 c6,c0,0,2 */ 1903 ARMCPRegInfo ifar = { 1904 .name = "IFAR", .cp = 15, .crn = 6, .crm = 0, .opc1 = 0, .opc2 = 1, 1905 .access = PL1_RW, 1906 .fieldoffset = offsetof(CPUARMState, cp15.ifar_ns), 1907 .resetvalue = 0 1908 }; 1909 define_one_arm_cp_reg(cpu, &ifar); 1910 } 1911 } 1912 1913 static void arm1136_r2_initfn(Object *obj) 1914 { 1915 ARMCPU *cpu = ARM_CPU(obj); 1916 /* 1917 * What qemu calls "arm1136_r2" is actually the 1136 r0p2, ie an 1918 * older core than plain "arm1136". In particular this does not 1919 * have the v6K features. 1920 * These ID register values are correct for 1136 but may be wrong 1921 * for 1136_r2 (in particular r0p2 does not actually implement most 1922 * of the ID registers). 1923 */ 1924 1925 cpu->dtb_compatible = "arm,arm1136"; 1926 set_feature(&cpu->env, ARM_FEATURE_V6); 1927 set_feature(&cpu->env, ARM_FEATURE_DUMMY_C15_REGS); 1928 set_feature(&cpu->env, ARM_FEATURE_CACHE_DIRTY_REG); 1929 set_feature(&cpu->env, ARM_FEATURE_CACHE_BLOCK_OPS); 1930 cpu->midr = 0x4107b362; 1931 cpu->reset_fpsid = 0x410120b4; 1932 cpu->isar.mvfr0 = 0x11111111; 1933 cpu->isar.mvfr1 = 0x00000000; 1934 cpu->ctr = 0x1dd20d2; 1935 cpu->reset_sctlr = 0x00050078; 1936 cpu->id_pfr0 = 0x111; 1937 cpu->id_pfr1 = 0x1; 1938 cpu->isar.id_dfr0 = 0x2; 1939 cpu->id_afr0 = 0x3; 1940 cpu->isar.id_mmfr0 = 0x01130003; 1941 cpu->isar.id_mmfr1 = 0x10030302; 1942 cpu->isar.id_mmfr2 = 0x01222110; 1943 cpu->isar.id_isar0 = 0x00140011; 1944 cpu->isar.id_isar1 = 0x12002111; 1945 cpu->isar.id_isar2 = 0x11231111; 1946 cpu->isar.id_isar3 = 0x01102131; 1947 cpu->isar.id_isar4 = 0x141; 1948 cpu->reset_auxcr = 7; 1949 } 1950 1951 static void arm1136_initfn(Object *obj) 1952 { 1953 ARMCPU *cpu = ARM_CPU(obj); 1954 1955 cpu->dtb_compatible = "arm,arm1136"; 1956 set_feature(&cpu->env, ARM_FEATURE_V6K); 1957 set_feature(&cpu->env, ARM_FEATURE_V6); 1958 set_feature(&cpu->env, ARM_FEATURE_DUMMY_C15_REGS); 1959 set_feature(&cpu->env, ARM_FEATURE_CACHE_DIRTY_REG); 1960 set_feature(&cpu->env, ARM_FEATURE_CACHE_BLOCK_OPS); 1961 cpu->midr = 0x4117b363; 1962 cpu->reset_fpsid = 0x410120b4; 1963 cpu->isar.mvfr0 = 0x11111111; 1964 cpu->isar.mvfr1 = 0x00000000; 1965 cpu->ctr = 0x1dd20d2; 1966 cpu->reset_sctlr = 0x00050078; 1967 cpu->id_pfr0 = 0x111; 1968 cpu->id_pfr1 = 0x1; 1969 cpu->isar.id_dfr0 = 0x2; 1970 cpu->id_afr0 = 0x3; 1971 cpu->isar.id_mmfr0 = 0x01130003; 1972 cpu->isar.id_mmfr1 = 0x10030302; 1973 cpu->isar.id_mmfr2 = 0x01222110; 1974 cpu->isar.id_isar0 = 0x00140011; 1975 cpu->isar.id_isar1 = 0x12002111; 1976 cpu->isar.id_isar2 = 0x11231111; 1977 cpu->isar.id_isar3 = 0x01102131; 1978 cpu->isar.id_isar4 = 0x141; 1979 cpu->reset_auxcr = 7; 1980 } 1981 1982 static void arm1176_initfn(Object *obj) 1983 { 1984 ARMCPU *cpu = ARM_CPU(obj); 1985 1986 cpu->dtb_compatible = "arm,arm1176"; 1987 set_feature(&cpu->env, ARM_FEATURE_V6K); 1988 set_feature(&cpu->env, ARM_FEATURE_VAPA); 1989 set_feature(&cpu->env, ARM_FEATURE_DUMMY_C15_REGS); 1990 set_feature(&cpu->env, ARM_FEATURE_CACHE_DIRTY_REG); 1991 set_feature(&cpu->env, ARM_FEATURE_CACHE_BLOCK_OPS); 1992 set_feature(&cpu->env, ARM_FEATURE_EL3); 1993 cpu->midr = 0x410fb767; 1994 cpu->reset_fpsid = 0x410120b5; 1995 cpu->isar.mvfr0 = 0x11111111; 1996 cpu->isar.mvfr1 = 0x00000000; 1997 cpu->ctr = 0x1dd20d2; 1998 cpu->reset_sctlr = 0x00050078; 1999 cpu->id_pfr0 = 0x111; 2000 cpu->id_pfr1 = 0x11; 2001 cpu->isar.id_dfr0 = 0x33; 2002 cpu->id_afr0 = 0; 2003 cpu->isar.id_mmfr0 = 0x01130003; 2004 cpu->isar.id_mmfr1 = 0x10030302; 2005 cpu->isar.id_mmfr2 = 0x01222100; 2006 cpu->isar.id_isar0 = 0x0140011; 2007 cpu->isar.id_isar1 = 0x12002111; 2008 cpu->isar.id_isar2 = 0x11231121; 2009 cpu->isar.id_isar3 = 0x01102131; 2010 cpu->isar.id_isar4 = 0x01141; 2011 cpu->reset_auxcr = 7; 2012 } 2013 2014 static void arm11mpcore_initfn(Object *obj) 2015 { 2016 ARMCPU *cpu = ARM_CPU(obj); 2017 2018 cpu->dtb_compatible = "arm,arm11mpcore"; 2019 set_feature(&cpu->env, ARM_FEATURE_V6K); 2020 set_feature(&cpu->env, ARM_FEATURE_VAPA); 2021 set_feature(&cpu->env, ARM_FEATURE_MPIDR); 2022 set_feature(&cpu->env, ARM_FEATURE_DUMMY_C15_REGS); 2023 cpu->midr = 0x410fb022; 2024 cpu->reset_fpsid = 0x410120b4; 2025 cpu->isar.mvfr0 = 0x11111111; 2026 cpu->isar.mvfr1 = 0x00000000; 2027 cpu->ctr = 0x1d192992; /* 32K icache 32K dcache */ 2028 cpu->id_pfr0 = 0x111; 2029 cpu->id_pfr1 = 0x1; 2030 cpu->isar.id_dfr0 = 0; 2031 cpu->id_afr0 = 0x2; 2032 cpu->isar.id_mmfr0 = 0x01100103; 2033 cpu->isar.id_mmfr1 = 0x10020302; 2034 cpu->isar.id_mmfr2 = 0x01222000; 2035 cpu->isar.id_isar0 = 0x00100011; 2036 cpu->isar.id_isar1 = 0x12002111; 2037 cpu->isar.id_isar2 = 0x11221011; 2038 cpu->isar.id_isar3 = 0x01102131; 2039 cpu->isar.id_isar4 = 0x141; 2040 cpu->reset_auxcr = 1; 2041 } 2042 2043 static void cortex_m0_initfn(Object *obj) 2044 { 2045 ARMCPU *cpu = ARM_CPU(obj); 2046 set_feature(&cpu->env, ARM_FEATURE_V6); 2047 set_feature(&cpu->env, ARM_FEATURE_M); 2048 2049 cpu->midr = 0x410cc200; 2050 } 2051 2052 static void cortex_m3_initfn(Object *obj) 2053 { 2054 ARMCPU *cpu = ARM_CPU(obj); 2055 set_feature(&cpu->env, ARM_FEATURE_V7); 2056 set_feature(&cpu->env, ARM_FEATURE_M); 2057 set_feature(&cpu->env, ARM_FEATURE_M_MAIN); 2058 cpu->midr = 0x410fc231; 2059 cpu->pmsav7_dregion = 8; 2060 cpu->id_pfr0 = 0x00000030; 2061 cpu->id_pfr1 = 0x00000200; 2062 cpu->isar.id_dfr0 = 0x00100000; 2063 cpu->id_afr0 = 0x00000000; 2064 cpu->isar.id_mmfr0 = 0x00000030; 2065 cpu->isar.id_mmfr1 = 0x00000000; 2066 cpu->isar.id_mmfr2 = 0x00000000; 2067 cpu->isar.id_mmfr3 = 0x00000000; 2068 cpu->isar.id_isar0 = 0x01141110; 2069 cpu->isar.id_isar1 = 0x02111000; 2070 cpu->isar.id_isar2 = 0x21112231; 2071 cpu->isar.id_isar3 = 0x01111110; 2072 cpu->isar.id_isar4 = 0x01310102; 2073 cpu->isar.id_isar5 = 0x00000000; 2074 cpu->isar.id_isar6 = 0x00000000; 2075 } 2076 2077 static void cortex_m4_initfn(Object *obj) 2078 { 2079 ARMCPU *cpu = ARM_CPU(obj); 2080 2081 set_feature(&cpu->env, ARM_FEATURE_V7); 2082 set_feature(&cpu->env, ARM_FEATURE_M); 2083 set_feature(&cpu->env, ARM_FEATURE_M_MAIN); 2084 set_feature(&cpu->env, ARM_FEATURE_THUMB_DSP); 2085 cpu->midr = 0x410fc240; /* r0p0 */ 2086 cpu->pmsav7_dregion = 8; 2087 cpu->isar.mvfr0 = 0x10110021; 2088 cpu->isar.mvfr1 = 0x11000011; 2089 cpu->isar.mvfr2 = 0x00000000; 2090 cpu->id_pfr0 = 0x00000030; 2091 cpu->id_pfr1 = 0x00000200; 2092 cpu->isar.id_dfr0 = 0x00100000; 2093 cpu->id_afr0 = 0x00000000; 2094 cpu->isar.id_mmfr0 = 0x00000030; 2095 cpu->isar.id_mmfr1 = 0x00000000; 2096 cpu->isar.id_mmfr2 = 0x00000000; 2097 cpu->isar.id_mmfr3 = 0x00000000; 2098 cpu->isar.id_isar0 = 0x01141110; 2099 cpu->isar.id_isar1 = 0x02111000; 2100 cpu->isar.id_isar2 = 0x21112231; 2101 cpu->isar.id_isar3 = 0x01111110; 2102 cpu->isar.id_isar4 = 0x01310102; 2103 cpu->isar.id_isar5 = 0x00000000; 2104 cpu->isar.id_isar6 = 0x00000000; 2105 } 2106 2107 static void cortex_m7_initfn(Object *obj) 2108 { 2109 ARMCPU *cpu = ARM_CPU(obj); 2110 2111 set_feature(&cpu->env, ARM_FEATURE_V7); 2112 set_feature(&cpu->env, ARM_FEATURE_M); 2113 set_feature(&cpu->env, ARM_FEATURE_M_MAIN); 2114 set_feature(&cpu->env, ARM_FEATURE_THUMB_DSP); 2115 cpu->midr = 0x411fc272; /* r1p2 */ 2116 cpu->pmsav7_dregion = 8; 2117 cpu->isar.mvfr0 = 0x10110221; 2118 cpu->isar.mvfr1 = 0x12000011; 2119 cpu->isar.mvfr2 = 0x00000040; 2120 cpu->id_pfr0 = 0x00000030; 2121 cpu->id_pfr1 = 0x00000200; 2122 cpu->isar.id_dfr0 = 0x00100000; 2123 cpu->id_afr0 = 0x00000000; 2124 cpu->isar.id_mmfr0 = 0x00100030; 2125 cpu->isar.id_mmfr1 = 0x00000000; 2126 cpu->isar.id_mmfr2 = 0x01000000; 2127 cpu->isar.id_mmfr3 = 0x00000000; 2128 cpu->isar.id_isar0 = 0x01101110; 2129 cpu->isar.id_isar1 = 0x02112000; 2130 cpu->isar.id_isar2 = 0x20232231; 2131 cpu->isar.id_isar3 = 0x01111131; 2132 cpu->isar.id_isar4 = 0x01310132; 2133 cpu->isar.id_isar5 = 0x00000000; 2134 cpu->isar.id_isar6 = 0x00000000; 2135 } 2136 2137 static void cortex_m33_initfn(Object *obj) 2138 { 2139 ARMCPU *cpu = ARM_CPU(obj); 2140 2141 set_feature(&cpu->env, ARM_FEATURE_V8); 2142 set_feature(&cpu->env, ARM_FEATURE_M); 2143 set_feature(&cpu->env, ARM_FEATURE_M_MAIN); 2144 set_feature(&cpu->env, ARM_FEATURE_M_SECURITY); 2145 set_feature(&cpu->env, ARM_FEATURE_THUMB_DSP); 2146 cpu->midr = 0x410fd213; /* r0p3 */ 2147 cpu->pmsav7_dregion = 16; 2148 cpu->sau_sregion = 8; 2149 cpu->isar.mvfr0 = 0x10110021; 2150 cpu->isar.mvfr1 = 0x11000011; 2151 cpu->isar.mvfr2 = 0x00000040; 2152 cpu->id_pfr0 = 0x00000030; 2153 cpu->id_pfr1 = 0x00000210; 2154 cpu->isar.id_dfr0 = 0x00200000; 2155 cpu->id_afr0 = 0x00000000; 2156 cpu->isar.id_mmfr0 = 0x00101F40; 2157 cpu->isar.id_mmfr1 = 0x00000000; 2158 cpu->isar.id_mmfr2 = 0x01000000; 2159 cpu->isar.id_mmfr3 = 0x00000000; 2160 cpu->isar.id_isar0 = 0x01101110; 2161 cpu->isar.id_isar1 = 0x02212000; 2162 cpu->isar.id_isar2 = 0x20232232; 2163 cpu->isar.id_isar3 = 0x01111131; 2164 cpu->isar.id_isar4 = 0x01310132; 2165 cpu->isar.id_isar5 = 0x00000000; 2166 cpu->isar.id_isar6 = 0x00000000; 2167 cpu->clidr = 0x00000000; 2168 cpu->ctr = 0x8000c000; 2169 } 2170 2171 static void arm_v7m_class_init(ObjectClass *oc, void *data) 2172 { 2173 ARMCPUClass *acc = ARM_CPU_CLASS(oc); 2174 CPUClass *cc = CPU_CLASS(oc); 2175 2176 acc->info = data; 2177 #ifndef CONFIG_USER_ONLY 2178 cc->do_interrupt = arm_v7m_cpu_do_interrupt; 2179 #endif 2180 2181 cc->cpu_exec_interrupt = arm_v7m_cpu_exec_interrupt; 2182 } 2183 2184 static const ARMCPRegInfo cortexr5_cp_reginfo[] = { 2185 /* Dummy the TCM region regs for the moment */ 2186 { .name = "ATCM", .cp = 15, .opc1 = 0, .crn = 9, .crm = 1, .opc2 = 0, 2187 .access = PL1_RW, .type = ARM_CP_CONST }, 2188 { .name = "BTCM", .cp = 15, .opc1 = 0, .crn = 9, .crm = 1, .opc2 = 1, 2189 .access = PL1_RW, .type = ARM_CP_CONST }, 2190 { .name = "DCACHE_INVAL", .cp = 15, .opc1 = 0, .crn = 15, .crm = 5, 2191 .opc2 = 0, .access = PL1_W, .type = ARM_CP_NOP }, 2192 REGINFO_SENTINEL 2193 }; 2194 2195 static void cortex_r5_initfn(Object *obj) 2196 { 2197 ARMCPU *cpu = ARM_CPU(obj); 2198 2199 set_feature(&cpu->env, ARM_FEATURE_V7); 2200 set_feature(&cpu->env, ARM_FEATURE_V7MP); 2201 set_feature(&cpu->env, ARM_FEATURE_PMSA); 2202 set_feature(&cpu->env, ARM_FEATURE_PMU); 2203 cpu->midr = 0x411fc153; /* r1p3 */ 2204 cpu->id_pfr0 = 0x0131; 2205 cpu->id_pfr1 = 0x001; 2206 cpu->isar.id_dfr0 = 0x010400; 2207 cpu->id_afr0 = 0x0; 2208 cpu->isar.id_mmfr0 = 0x0210030; 2209 cpu->isar.id_mmfr1 = 0x00000000; 2210 cpu->isar.id_mmfr2 = 0x01200000; 2211 cpu->isar.id_mmfr3 = 0x0211; 2212 cpu->isar.id_isar0 = 0x02101111; 2213 cpu->isar.id_isar1 = 0x13112111; 2214 cpu->isar.id_isar2 = 0x21232141; 2215 cpu->isar.id_isar3 = 0x01112131; 2216 cpu->isar.id_isar4 = 0x0010142; 2217 cpu->isar.id_isar5 = 0x0; 2218 cpu->isar.id_isar6 = 0x0; 2219 cpu->mp_is_up = true; 2220 cpu->pmsav7_dregion = 16; 2221 define_arm_cp_regs(cpu, cortexr5_cp_reginfo); 2222 } 2223 2224 static void cortex_r5f_initfn(Object *obj) 2225 { 2226 ARMCPU *cpu = ARM_CPU(obj); 2227 2228 cortex_r5_initfn(obj); 2229 cpu->isar.mvfr0 = 0x10110221; 2230 cpu->isar.mvfr1 = 0x00000011; 2231 } 2232 2233 static const ARMCPRegInfo cortexa8_cp_reginfo[] = { 2234 { .name = "L2LOCKDOWN", .cp = 15, .crn = 9, .crm = 0, .opc1 = 1, .opc2 = 0, 2235 .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0 }, 2236 { .name = "L2AUXCR", .cp = 15, .crn = 9, .crm = 0, .opc1 = 1, .opc2 = 2, 2237 .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0 }, 2238 REGINFO_SENTINEL 2239 }; 2240 2241 static void cortex_a8_initfn(Object *obj) 2242 { 2243 ARMCPU *cpu = ARM_CPU(obj); 2244 2245 cpu->dtb_compatible = "arm,cortex-a8"; 2246 set_feature(&cpu->env, ARM_FEATURE_V7); 2247 set_feature(&cpu->env, ARM_FEATURE_NEON); 2248 set_feature(&cpu->env, ARM_FEATURE_THUMB2EE); 2249 set_feature(&cpu->env, ARM_FEATURE_DUMMY_C15_REGS); 2250 set_feature(&cpu->env, ARM_FEATURE_EL3); 2251 cpu->midr = 0x410fc080; 2252 cpu->reset_fpsid = 0x410330c0; 2253 cpu->isar.mvfr0 = 0x11110222; 2254 cpu->isar.mvfr1 = 0x00011111; 2255 cpu->ctr = 0x82048004; 2256 cpu->reset_sctlr = 0x00c50078; 2257 cpu->id_pfr0 = 0x1031; 2258 cpu->id_pfr1 = 0x11; 2259 cpu->isar.id_dfr0 = 0x400; 2260 cpu->id_afr0 = 0; 2261 cpu->isar.id_mmfr0 = 0x31100003; 2262 cpu->isar.id_mmfr1 = 0x20000000; 2263 cpu->isar.id_mmfr2 = 0x01202000; 2264 cpu->isar.id_mmfr3 = 0x11; 2265 cpu->isar.id_isar0 = 0x00101111; 2266 cpu->isar.id_isar1 = 0x12112111; 2267 cpu->isar.id_isar2 = 0x21232031; 2268 cpu->isar.id_isar3 = 0x11112131; 2269 cpu->isar.id_isar4 = 0x00111142; 2270 cpu->isar.dbgdidr = 0x15141000; 2271 cpu->clidr = (1 << 27) | (2 << 24) | 3; 2272 cpu->ccsidr[0] = 0xe007e01a; /* 16k L1 dcache. */ 2273 cpu->ccsidr[1] = 0x2007e01a; /* 16k L1 icache. */ 2274 cpu->ccsidr[2] = 0xf0000000; /* No L2 icache. */ 2275 cpu->reset_auxcr = 2; 2276 define_arm_cp_regs(cpu, cortexa8_cp_reginfo); 2277 } 2278 2279 static const ARMCPRegInfo cortexa9_cp_reginfo[] = { 2280 /* power_control should be set to maximum latency. Again, 2281 * default to 0 and set by private hook 2282 */ 2283 { .name = "A9_PWRCTL", .cp = 15, .crn = 15, .crm = 0, .opc1 = 0, .opc2 = 0, 2284 .access = PL1_RW, .resetvalue = 0, 2285 .fieldoffset = offsetof(CPUARMState, cp15.c15_power_control) }, 2286 { .name = "A9_DIAG", .cp = 15, .crn = 15, .crm = 0, .opc1 = 0, .opc2 = 1, 2287 .access = PL1_RW, .resetvalue = 0, 2288 .fieldoffset = offsetof(CPUARMState, cp15.c15_diagnostic) }, 2289 { .name = "A9_PWRDIAG", .cp = 15, .crn = 15, .crm = 0, .opc1 = 0, .opc2 = 2, 2290 .access = PL1_RW, .resetvalue = 0, 2291 .fieldoffset = offsetof(CPUARMState, cp15.c15_power_diagnostic) }, 2292 { .name = "NEONBUSY", .cp = 15, .crn = 15, .crm = 1, .opc1 = 0, .opc2 = 0, 2293 .access = PL1_RW, .resetvalue = 0, .type = ARM_CP_CONST }, 2294 /* TLB lockdown control */ 2295 { .name = "TLB_LOCKR", .cp = 15, .crn = 15, .crm = 4, .opc1 = 5, .opc2 = 2, 2296 .access = PL1_W, .resetvalue = 0, .type = ARM_CP_NOP }, 2297 { .name = "TLB_LOCKW", .cp = 15, .crn = 15, .crm = 4, .opc1 = 5, .opc2 = 4, 2298 .access = PL1_W, .resetvalue = 0, .type = ARM_CP_NOP }, 2299 { .name = "TLB_VA", .cp = 15, .crn = 15, .crm = 5, .opc1 = 5, .opc2 = 2, 2300 .access = PL1_RW, .resetvalue = 0, .type = ARM_CP_CONST }, 2301 { .name = "TLB_PA", .cp = 15, .crn = 15, .crm = 6, .opc1 = 5, .opc2 = 2, 2302 .access = PL1_RW, .resetvalue = 0, .type = ARM_CP_CONST }, 2303 { .name = "TLB_ATTR", .cp = 15, .crn = 15, .crm = 7, .opc1 = 5, .opc2 = 2, 2304 .access = PL1_RW, .resetvalue = 0, .type = ARM_CP_CONST }, 2305 REGINFO_SENTINEL 2306 }; 2307 2308 static void cortex_a9_initfn(Object *obj) 2309 { 2310 ARMCPU *cpu = ARM_CPU(obj); 2311 2312 cpu->dtb_compatible = "arm,cortex-a9"; 2313 set_feature(&cpu->env, ARM_FEATURE_V7); 2314 set_feature(&cpu->env, ARM_FEATURE_NEON); 2315 set_feature(&cpu->env, ARM_FEATURE_THUMB2EE); 2316 set_feature(&cpu->env, ARM_FEATURE_EL3); 2317 /* Note that A9 supports the MP extensions even for 2318 * A9UP and single-core A9MP (which are both different 2319 * and valid configurations; we don't model A9UP). 2320 */ 2321 set_feature(&cpu->env, ARM_FEATURE_V7MP); 2322 set_feature(&cpu->env, ARM_FEATURE_CBAR); 2323 cpu->midr = 0x410fc090; 2324 cpu->reset_fpsid = 0x41033090; 2325 cpu->isar.mvfr0 = 0x11110222; 2326 cpu->isar.mvfr1 = 0x01111111; 2327 cpu->ctr = 0x80038003; 2328 cpu->reset_sctlr = 0x00c50078; 2329 cpu->id_pfr0 = 0x1031; 2330 cpu->id_pfr1 = 0x11; 2331 cpu->isar.id_dfr0 = 0x000; 2332 cpu->id_afr0 = 0; 2333 cpu->isar.id_mmfr0 = 0x00100103; 2334 cpu->isar.id_mmfr1 = 0x20000000; 2335 cpu->isar.id_mmfr2 = 0x01230000; 2336 cpu->isar.id_mmfr3 = 0x00002111; 2337 cpu->isar.id_isar0 = 0x00101111; 2338 cpu->isar.id_isar1 = 0x13112111; 2339 cpu->isar.id_isar2 = 0x21232041; 2340 cpu->isar.id_isar3 = 0x11112131; 2341 cpu->isar.id_isar4 = 0x00111142; 2342 cpu->isar.dbgdidr = 0x35141000; 2343 cpu->clidr = (1 << 27) | (1 << 24) | 3; 2344 cpu->ccsidr[0] = 0xe00fe019; /* 16k L1 dcache. */ 2345 cpu->ccsidr[1] = 0x200fe019; /* 16k L1 icache. */ 2346 define_arm_cp_regs(cpu, cortexa9_cp_reginfo); 2347 } 2348 2349 #ifndef CONFIG_USER_ONLY 2350 static uint64_t a15_l2ctlr_read(CPUARMState *env, const ARMCPRegInfo *ri) 2351 { 2352 MachineState *ms = MACHINE(qdev_get_machine()); 2353 2354 /* Linux wants the number of processors from here. 2355 * Might as well set the interrupt-controller bit too. 2356 */ 2357 return ((ms->smp.cpus - 1) << 24) | (1 << 23); 2358 } 2359 #endif 2360 2361 static const ARMCPRegInfo cortexa15_cp_reginfo[] = { 2362 #ifndef CONFIG_USER_ONLY 2363 { .name = "L2CTLR", .cp = 15, .crn = 9, .crm = 0, .opc1 = 1, .opc2 = 2, 2364 .access = PL1_RW, .resetvalue = 0, .readfn = a15_l2ctlr_read, 2365 .writefn = arm_cp_write_ignore, }, 2366 #endif 2367 { .name = "L2ECTLR", .cp = 15, .crn = 9, .crm = 0, .opc1 = 1, .opc2 = 3, 2368 .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0 }, 2369 REGINFO_SENTINEL 2370 }; 2371 2372 static void cortex_a7_initfn(Object *obj) 2373 { 2374 ARMCPU *cpu = ARM_CPU(obj); 2375 2376 cpu->dtb_compatible = "arm,cortex-a7"; 2377 set_feature(&cpu->env, ARM_FEATURE_V7VE); 2378 set_feature(&cpu->env, ARM_FEATURE_NEON); 2379 set_feature(&cpu->env, ARM_FEATURE_THUMB2EE); 2380 set_feature(&cpu->env, ARM_FEATURE_GENERIC_TIMER); 2381 set_feature(&cpu->env, ARM_FEATURE_DUMMY_C15_REGS); 2382 set_feature(&cpu->env, ARM_FEATURE_CBAR_RO); 2383 set_feature(&cpu->env, ARM_FEATURE_EL2); 2384 set_feature(&cpu->env, ARM_FEATURE_EL3); 2385 set_feature(&cpu->env, ARM_FEATURE_PMU); 2386 cpu->kvm_target = QEMU_KVM_ARM_TARGET_CORTEX_A7; 2387 cpu->midr = 0x410fc075; 2388 cpu->reset_fpsid = 0x41023075; 2389 cpu->isar.mvfr0 = 0x10110222; 2390 cpu->isar.mvfr1 = 0x11111111; 2391 cpu->ctr = 0x84448003; 2392 cpu->reset_sctlr = 0x00c50078; 2393 cpu->id_pfr0 = 0x00001131; 2394 cpu->id_pfr1 = 0x00011011; 2395 cpu->isar.id_dfr0 = 0x02010555; 2396 cpu->id_afr0 = 0x00000000; 2397 cpu->isar.id_mmfr0 = 0x10101105; 2398 cpu->isar.id_mmfr1 = 0x40000000; 2399 cpu->isar.id_mmfr2 = 0x01240000; 2400 cpu->isar.id_mmfr3 = 0x02102211; 2401 /* a7_mpcore_r0p5_trm, page 4-4 gives 0x01101110; but 2402 * table 4-41 gives 0x02101110, which includes the arm div insns. 2403 */ 2404 cpu->isar.id_isar0 = 0x02101110; 2405 cpu->isar.id_isar1 = 0x13112111; 2406 cpu->isar.id_isar2 = 0x21232041; 2407 cpu->isar.id_isar3 = 0x11112131; 2408 cpu->isar.id_isar4 = 0x10011142; 2409 cpu->isar.dbgdidr = 0x3515f005; 2410 cpu->clidr = 0x0a200023; 2411 cpu->ccsidr[0] = 0x701fe00a; /* 32K L1 dcache */ 2412 cpu->ccsidr[1] = 0x201fe00a; /* 32K L1 icache */ 2413 cpu->ccsidr[2] = 0x711fe07a; /* 4096K L2 unified cache */ 2414 define_arm_cp_regs(cpu, cortexa15_cp_reginfo); /* Same as A15 */ 2415 } 2416 2417 static void cortex_a15_initfn(Object *obj) 2418 { 2419 ARMCPU *cpu = ARM_CPU(obj); 2420 2421 cpu->dtb_compatible = "arm,cortex-a15"; 2422 set_feature(&cpu->env, ARM_FEATURE_V7VE); 2423 set_feature(&cpu->env, ARM_FEATURE_NEON); 2424 set_feature(&cpu->env, ARM_FEATURE_THUMB2EE); 2425 set_feature(&cpu->env, ARM_FEATURE_GENERIC_TIMER); 2426 set_feature(&cpu->env, ARM_FEATURE_DUMMY_C15_REGS); 2427 set_feature(&cpu->env, ARM_FEATURE_CBAR_RO); 2428 set_feature(&cpu->env, ARM_FEATURE_EL2); 2429 set_feature(&cpu->env, ARM_FEATURE_EL3); 2430 set_feature(&cpu->env, ARM_FEATURE_PMU); 2431 cpu->kvm_target = QEMU_KVM_ARM_TARGET_CORTEX_A15; 2432 cpu->midr = 0x412fc0f1; 2433 cpu->reset_fpsid = 0x410430f0; 2434 cpu->isar.mvfr0 = 0x10110222; 2435 cpu->isar.mvfr1 = 0x11111111; 2436 cpu->ctr = 0x8444c004; 2437 cpu->reset_sctlr = 0x00c50078; 2438 cpu->id_pfr0 = 0x00001131; 2439 cpu->id_pfr1 = 0x00011011; 2440 cpu->isar.id_dfr0 = 0x02010555; 2441 cpu->id_afr0 = 0x00000000; 2442 cpu->isar.id_mmfr0 = 0x10201105; 2443 cpu->isar.id_mmfr1 = 0x20000000; 2444 cpu->isar.id_mmfr2 = 0x01240000; 2445 cpu->isar.id_mmfr3 = 0x02102211; 2446 cpu->isar.id_isar0 = 0x02101110; 2447 cpu->isar.id_isar1 = 0x13112111; 2448 cpu->isar.id_isar2 = 0x21232041; 2449 cpu->isar.id_isar3 = 0x11112131; 2450 cpu->isar.id_isar4 = 0x10011142; 2451 cpu->isar.dbgdidr = 0x3515f021; 2452 cpu->clidr = 0x0a200023; 2453 cpu->ccsidr[0] = 0x701fe00a; /* 32K L1 dcache */ 2454 cpu->ccsidr[1] = 0x201fe00a; /* 32K L1 icache */ 2455 cpu->ccsidr[2] = 0x711fe07a; /* 4096K L2 unified cache */ 2456 define_arm_cp_regs(cpu, cortexa15_cp_reginfo); 2457 } 2458 2459 static void ti925t_initfn(Object *obj) 2460 { 2461 ARMCPU *cpu = ARM_CPU(obj); 2462 set_feature(&cpu->env, ARM_FEATURE_V4T); 2463 set_feature(&cpu->env, ARM_FEATURE_OMAPCP); 2464 cpu->midr = ARM_CPUID_TI925T; 2465 cpu->ctr = 0x5109149; 2466 cpu->reset_sctlr = 0x00000070; 2467 } 2468 2469 static void sa1100_initfn(Object *obj) 2470 { 2471 ARMCPU *cpu = ARM_CPU(obj); 2472 2473 cpu->dtb_compatible = "intel,sa1100"; 2474 set_feature(&cpu->env, ARM_FEATURE_STRONGARM); 2475 set_feature(&cpu->env, ARM_FEATURE_DUMMY_C15_REGS); 2476 cpu->midr = 0x4401A11B; 2477 cpu->reset_sctlr = 0x00000070; 2478 } 2479 2480 static void sa1110_initfn(Object *obj) 2481 { 2482 ARMCPU *cpu = ARM_CPU(obj); 2483 set_feature(&cpu->env, ARM_FEATURE_STRONGARM); 2484 set_feature(&cpu->env, ARM_FEATURE_DUMMY_C15_REGS); 2485 cpu->midr = 0x6901B119; 2486 cpu->reset_sctlr = 0x00000070; 2487 } 2488 2489 static void pxa250_initfn(Object *obj) 2490 { 2491 ARMCPU *cpu = ARM_CPU(obj); 2492 2493 cpu->dtb_compatible = "marvell,xscale"; 2494 set_feature(&cpu->env, ARM_FEATURE_V5); 2495 set_feature(&cpu->env, ARM_FEATURE_XSCALE); 2496 cpu->midr = 0x69052100; 2497 cpu->ctr = 0xd172172; 2498 cpu->reset_sctlr = 0x00000078; 2499 } 2500 2501 static void pxa255_initfn(Object *obj) 2502 { 2503 ARMCPU *cpu = ARM_CPU(obj); 2504 2505 cpu->dtb_compatible = "marvell,xscale"; 2506 set_feature(&cpu->env, ARM_FEATURE_V5); 2507 set_feature(&cpu->env, ARM_FEATURE_XSCALE); 2508 cpu->midr = 0x69052d00; 2509 cpu->ctr = 0xd172172; 2510 cpu->reset_sctlr = 0x00000078; 2511 } 2512 2513 static void pxa260_initfn(Object *obj) 2514 { 2515 ARMCPU *cpu = ARM_CPU(obj); 2516 2517 cpu->dtb_compatible = "marvell,xscale"; 2518 set_feature(&cpu->env, ARM_FEATURE_V5); 2519 set_feature(&cpu->env, ARM_FEATURE_XSCALE); 2520 cpu->midr = 0x69052903; 2521 cpu->ctr = 0xd172172; 2522 cpu->reset_sctlr = 0x00000078; 2523 } 2524 2525 static void pxa261_initfn(Object *obj) 2526 { 2527 ARMCPU *cpu = ARM_CPU(obj); 2528 2529 cpu->dtb_compatible = "marvell,xscale"; 2530 set_feature(&cpu->env, ARM_FEATURE_V5); 2531 set_feature(&cpu->env, ARM_FEATURE_XSCALE); 2532 cpu->midr = 0x69052d05; 2533 cpu->ctr = 0xd172172; 2534 cpu->reset_sctlr = 0x00000078; 2535 } 2536 2537 static void pxa262_initfn(Object *obj) 2538 { 2539 ARMCPU *cpu = ARM_CPU(obj); 2540 2541 cpu->dtb_compatible = "marvell,xscale"; 2542 set_feature(&cpu->env, ARM_FEATURE_V5); 2543 set_feature(&cpu->env, ARM_FEATURE_XSCALE); 2544 cpu->midr = 0x69052d06; 2545 cpu->ctr = 0xd172172; 2546 cpu->reset_sctlr = 0x00000078; 2547 } 2548 2549 static void pxa270a0_initfn(Object *obj) 2550 { 2551 ARMCPU *cpu = ARM_CPU(obj); 2552 2553 cpu->dtb_compatible = "marvell,xscale"; 2554 set_feature(&cpu->env, ARM_FEATURE_V5); 2555 set_feature(&cpu->env, ARM_FEATURE_XSCALE); 2556 set_feature(&cpu->env, ARM_FEATURE_IWMMXT); 2557 cpu->midr = 0x69054110; 2558 cpu->ctr = 0xd172172; 2559 cpu->reset_sctlr = 0x00000078; 2560 } 2561 2562 static void pxa270a1_initfn(Object *obj) 2563 { 2564 ARMCPU *cpu = ARM_CPU(obj); 2565 2566 cpu->dtb_compatible = "marvell,xscale"; 2567 set_feature(&cpu->env, ARM_FEATURE_V5); 2568 set_feature(&cpu->env, ARM_FEATURE_XSCALE); 2569 set_feature(&cpu->env, ARM_FEATURE_IWMMXT); 2570 cpu->midr = 0x69054111; 2571 cpu->ctr = 0xd172172; 2572 cpu->reset_sctlr = 0x00000078; 2573 } 2574 2575 static void pxa270b0_initfn(Object *obj) 2576 { 2577 ARMCPU *cpu = ARM_CPU(obj); 2578 2579 cpu->dtb_compatible = "marvell,xscale"; 2580 set_feature(&cpu->env, ARM_FEATURE_V5); 2581 set_feature(&cpu->env, ARM_FEATURE_XSCALE); 2582 set_feature(&cpu->env, ARM_FEATURE_IWMMXT); 2583 cpu->midr = 0x69054112; 2584 cpu->ctr = 0xd172172; 2585 cpu->reset_sctlr = 0x00000078; 2586 } 2587 2588 static void pxa270b1_initfn(Object *obj) 2589 { 2590 ARMCPU *cpu = ARM_CPU(obj); 2591 2592 cpu->dtb_compatible = "marvell,xscale"; 2593 set_feature(&cpu->env, ARM_FEATURE_V5); 2594 set_feature(&cpu->env, ARM_FEATURE_XSCALE); 2595 set_feature(&cpu->env, ARM_FEATURE_IWMMXT); 2596 cpu->midr = 0x69054113; 2597 cpu->ctr = 0xd172172; 2598 cpu->reset_sctlr = 0x00000078; 2599 } 2600 2601 static void pxa270c0_initfn(Object *obj) 2602 { 2603 ARMCPU *cpu = ARM_CPU(obj); 2604 2605 cpu->dtb_compatible = "marvell,xscale"; 2606 set_feature(&cpu->env, ARM_FEATURE_V5); 2607 set_feature(&cpu->env, ARM_FEATURE_XSCALE); 2608 set_feature(&cpu->env, ARM_FEATURE_IWMMXT); 2609 cpu->midr = 0x69054114; 2610 cpu->ctr = 0xd172172; 2611 cpu->reset_sctlr = 0x00000078; 2612 } 2613 2614 static void pxa270c5_initfn(Object *obj) 2615 { 2616 ARMCPU *cpu = ARM_CPU(obj); 2617 2618 cpu->dtb_compatible = "marvell,xscale"; 2619 set_feature(&cpu->env, ARM_FEATURE_V5); 2620 set_feature(&cpu->env, ARM_FEATURE_XSCALE); 2621 set_feature(&cpu->env, ARM_FEATURE_IWMMXT); 2622 cpu->midr = 0x69054117; 2623 cpu->ctr = 0xd172172; 2624 cpu->reset_sctlr = 0x00000078; 2625 } 2626 2627 #ifndef TARGET_AARCH64 2628 /* -cpu max: if KVM is enabled, like -cpu host (best possible with this host); 2629 * otherwise, a CPU with as many features enabled as our emulation supports. 2630 * The version of '-cpu max' for qemu-system-aarch64 is defined in cpu64.c; 2631 * this only needs to handle 32 bits. 2632 */ 2633 static void arm_max_initfn(Object *obj) 2634 { 2635 ARMCPU *cpu = ARM_CPU(obj); 2636 2637 if (kvm_enabled()) { 2638 kvm_arm_set_cpu_features_from_host(cpu); 2639 kvm_arm_add_vcpu_properties(obj); 2640 } else { 2641 cortex_a15_initfn(obj); 2642 2643 /* old-style VFP short-vector support */ 2644 cpu->isar.mvfr0 = FIELD_DP32(cpu->isar.mvfr0, MVFR0, FPSHVEC, 1); 2645 2646 #ifdef CONFIG_USER_ONLY 2647 /* We don't set these in system emulation mode for the moment, 2648 * since we don't correctly set (all of) the ID registers to 2649 * advertise them. 2650 */ 2651 set_feature(&cpu->env, ARM_FEATURE_V8); 2652 { 2653 uint32_t t; 2654 2655 t = cpu->isar.id_isar5; 2656 t = FIELD_DP32(t, ID_ISAR5, AES, 2); 2657 t = FIELD_DP32(t, ID_ISAR5, SHA1, 1); 2658 t = FIELD_DP32(t, ID_ISAR5, SHA2, 1); 2659 t = FIELD_DP32(t, ID_ISAR5, CRC32, 1); 2660 t = FIELD_DP32(t, ID_ISAR5, RDM, 1); 2661 t = FIELD_DP32(t, ID_ISAR5, VCMA, 1); 2662 cpu->isar.id_isar5 = t; 2663 2664 t = cpu->isar.id_isar6; 2665 t = FIELD_DP32(t, ID_ISAR6, JSCVT, 1); 2666 t = FIELD_DP32(t, ID_ISAR6, DP, 1); 2667 t = FIELD_DP32(t, ID_ISAR6, FHM, 1); 2668 t = FIELD_DP32(t, ID_ISAR6, SB, 1); 2669 t = FIELD_DP32(t, ID_ISAR6, SPECRES, 1); 2670 cpu->isar.id_isar6 = t; 2671 2672 t = cpu->isar.mvfr1; 2673 t = FIELD_DP32(t, MVFR1, FPHP, 2); /* v8.0 FP support */ 2674 cpu->isar.mvfr1 = t; 2675 2676 t = cpu->isar.mvfr2; 2677 t = FIELD_DP32(t, MVFR2, SIMDMISC, 3); /* SIMD MaxNum */ 2678 t = FIELD_DP32(t, MVFR2, FPMISC, 4); /* FP MaxNum */ 2679 cpu->isar.mvfr2 = t; 2680 2681 t = cpu->isar.id_mmfr3; 2682 t = FIELD_DP32(t, ID_MMFR3, PAN, 2); /* ATS1E1 */ 2683 cpu->isar.id_mmfr3 = t; 2684 2685 t = cpu->isar.id_mmfr4; 2686 t = FIELD_DP32(t, ID_MMFR4, HPDS, 1); /* AA32HPD */ 2687 t = FIELD_DP32(t, ID_MMFR4, AC2, 1); /* ACTLR2, HACTLR2 */ 2688 t = FIELD_DP32(t, ID_MMFR4, CNP, 1); /* TTCNP */ 2689 t = FIELD_DP32(t, ID_MMFR4, XNX, 1); /* TTS2UXN */ 2690 cpu->isar.id_mmfr4 = t; 2691 } 2692 #endif 2693 } 2694 } 2695 #endif 2696 2697 #endif /* !defined(CONFIG_USER_ONLY) || !defined(TARGET_AARCH64) */ 2698 2699 static const ARMCPUInfo arm_cpus[] = { 2700 #if !defined(CONFIG_USER_ONLY) || !defined(TARGET_AARCH64) 2701 { .name = "arm926", .initfn = arm926_initfn }, 2702 { .name = "arm946", .initfn = arm946_initfn }, 2703 { .name = "arm1026", .initfn = arm1026_initfn }, 2704 /* 2705 * What QEMU calls "arm1136-r2" is actually the 1136 r0p2, i.e. an 2706 * older core than plain "arm1136". In particular this does not 2707 * have the v6K features. 2708 */ 2709 { .name = "arm1136-r2", .initfn = arm1136_r2_initfn }, 2710 { .name = "arm1136", .initfn = arm1136_initfn }, 2711 { .name = "arm1176", .initfn = arm1176_initfn }, 2712 { .name = "arm11mpcore", .initfn = arm11mpcore_initfn }, 2713 { .name = "cortex-m0", .initfn = cortex_m0_initfn, 2714 .class_init = arm_v7m_class_init }, 2715 { .name = "cortex-m3", .initfn = cortex_m3_initfn, 2716 .class_init = arm_v7m_class_init }, 2717 { .name = "cortex-m4", .initfn = cortex_m4_initfn, 2718 .class_init = arm_v7m_class_init }, 2719 { .name = "cortex-m7", .initfn = cortex_m7_initfn, 2720 .class_init = arm_v7m_class_init }, 2721 { .name = "cortex-m33", .initfn = cortex_m33_initfn, 2722 .class_init = arm_v7m_class_init }, 2723 { .name = "cortex-r5", .initfn = cortex_r5_initfn }, 2724 { .name = "cortex-r5f", .initfn = cortex_r5f_initfn }, 2725 { .name = "cortex-a7", .initfn = cortex_a7_initfn }, 2726 { .name = "cortex-a8", .initfn = cortex_a8_initfn }, 2727 { .name = "cortex-a9", .initfn = cortex_a9_initfn }, 2728 { .name = "cortex-a15", .initfn = cortex_a15_initfn }, 2729 { .name = "ti925t", .initfn = ti925t_initfn }, 2730 { .name = "sa1100", .initfn = sa1100_initfn }, 2731 { .name = "sa1110", .initfn = sa1110_initfn }, 2732 { .name = "pxa250", .initfn = pxa250_initfn }, 2733 { .name = "pxa255", .initfn = pxa255_initfn }, 2734 { .name = "pxa260", .initfn = pxa260_initfn }, 2735 { .name = "pxa261", .initfn = pxa261_initfn }, 2736 { .name = "pxa262", .initfn = pxa262_initfn }, 2737 /* "pxa270" is an alias for "pxa270-a0" */ 2738 { .name = "pxa270", .initfn = pxa270a0_initfn }, 2739 { .name = "pxa270-a0", .initfn = pxa270a0_initfn }, 2740 { .name = "pxa270-a1", .initfn = pxa270a1_initfn }, 2741 { .name = "pxa270-b0", .initfn = pxa270b0_initfn }, 2742 { .name = "pxa270-b1", .initfn = pxa270b1_initfn }, 2743 { .name = "pxa270-c0", .initfn = pxa270c0_initfn }, 2744 { .name = "pxa270-c5", .initfn = pxa270c5_initfn }, 2745 #ifndef TARGET_AARCH64 2746 { .name = "max", .initfn = arm_max_initfn }, 2747 #endif 2748 #ifdef CONFIG_USER_ONLY 2749 { .name = "any", .initfn = arm_max_initfn }, 2750 #endif 2751 #endif 2752 { .name = NULL } 2753 }; 2754 2755 static Property arm_cpu_properties[] = { 2756 DEFINE_PROP_BOOL("start-powered-off", ARMCPU, start_powered_off, false), 2757 DEFINE_PROP_UINT32("psci-conduit", ARMCPU, psci_conduit, 0), 2758 DEFINE_PROP_UINT64("midr", ARMCPU, midr, 0), 2759 DEFINE_PROP_UINT64("mp-affinity", ARMCPU, 2760 mp_affinity, ARM64_AFFINITY_INVALID), 2761 DEFINE_PROP_INT32("node-id", ARMCPU, node_id, CPU_UNSET_NUMA_NODE_ID), 2762 DEFINE_PROP_INT32("core-count", ARMCPU, core_count, -1), 2763 DEFINE_PROP_END_OF_LIST() 2764 }; 2765 2766 static gchar *arm_gdb_arch_name(CPUState *cs) 2767 { 2768 ARMCPU *cpu = ARM_CPU(cs); 2769 CPUARMState *env = &cpu->env; 2770 2771 if (arm_feature(env, ARM_FEATURE_IWMMXT)) { 2772 return g_strdup("iwmmxt"); 2773 } 2774 return g_strdup("arm"); 2775 } 2776 2777 static void arm_cpu_class_init(ObjectClass *oc, void *data) 2778 { 2779 ARMCPUClass *acc = ARM_CPU_CLASS(oc); 2780 CPUClass *cc = CPU_CLASS(acc); 2781 DeviceClass *dc = DEVICE_CLASS(oc); 2782 2783 device_class_set_parent_realize(dc, arm_cpu_realizefn, 2784 &acc->parent_realize); 2785 2786 device_class_set_props(dc, arm_cpu_properties); 2787 device_class_set_parent_reset(dc, arm_cpu_reset, &acc->parent_reset); 2788 2789 cc->class_by_name = arm_cpu_class_by_name; 2790 cc->has_work = arm_cpu_has_work; 2791 cc->cpu_exec_interrupt = arm_cpu_exec_interrupt; 2792 cc->dump_state = arm_cpu_dump_state; 2793 cc->set_pc = arm_cpu_set_pc; 2794 cc->synchronize_from_tb = arm_cpu_synchronize_from_tb; 2795 cc->gdb_read_register = arm_cpu_gdb_read_register; 2796 cc->gdb_write_register = arm_cpu_gdb_write_register; 2797 #ifndef CONFIG_USER_ONLY 2798 cc->do_interrupt = arm_cpu_do_interrupt; 2799 cc->get_phys_page_attrs_debug = arm_cpu_get_phys_page_attrs_debug; 2800 cc->asidx_from_attrs = arm_asidx_from_attrs; 2801 cc->vmsd = &vmstate_arm_cpu; 2802 cc->virtio_is_big_endian = arm_cpu_virtio_is_big_endian; 2803 cc->write_elf64_note = arm_cpu_write_elf64_note; 2804 cc->write_elf32_note = arm_cpu_write_elf32_note; 2805 #endif 2806 cc->gdb_num_core_regs = 26; 2807 cc->gdb_core_xml_file = "arm-core.xml"; 2808 cc->gdb_arch_name = arm_gdb_arch_name; 2809 cc->gdb_get_dynamic_xml = arm_gdb_get_dynamic_xml; 2810 cc->gdb_stop_before_watchpoint = true; 2811 cc->disas_set_info = arm_disas_set_info; 2812 #ifdef CONFIG_TCG 2813 cc->tcg_initialize = arm_translate_init; 2814 cc->tlb_fill = arm_cpu_tlb_fill; 2815 cc->debug_excp_handler = arm_debug_excp_handler; 2816 cc->debug_check_watchpoint = arm_debug_check_watchpoint; 2817 #if !defined(CONFIG_USER_ONLY) 2818 cc->do_unaligned_access = arm_cpu_do_unaligned_access; 2819 cc->do_transaction_failed = arm_cpu_do_transaction_failed; 2820 cc->adjust_watchpoint_address = arm_adjust_watchpoint_address; 2821 #endif /* CONFIG_TCG && !CONFIG_USER_ONLY */ 2822 #endif 2823 } 2824 2825 #ifdef CONFIG_KVM 2826 static void arm_host_initfn(Object *obj) 2827 { 2828 ARMCPU *cpu = ARM_CPU(obj); 2829 2830 kvm_arm_set_cpu_features_from_host(cpu); 2831 if (arm_feature(&cpu->env, ARM_FEATURE_AARCH64)) { 2832 aarch64_add_sve_properties(obj); 2833 } 2834 kvm_arm_add_vcpu_properties(obj); 2835 arm_cpu_post_init(obj); 2836 } 2837 2838 static const TypeInfo host_arm_cpu_type_info = { 2839 .name = TYPE_ARM_HOST_CPU, 2840 #ifdef TARGET_AARCH64 2841 .parent = TYPE_AARCH64_CPU, 2842 #else 2843 .parent = TYPE_ARM_CPU, 2844 #endif 2845 .instance_init = arm_host_initfn, 2846 }; 2847 2848 #endif 2849 2850 static void arm_cpu_instance_init(Object *obj) 2851 { 2852 ARMCPUClass *acc = ARM_CPU_GET_CLASS(obj); 2853 2854 acc->info->initfn(obj); 2855 arm_cpu_post_init(obj); 2856 } 2857 2858 static void cpu_register_class_init(ObjectClass *oc, void *data) 2859 { 2860 ARMCPUClass *acc = ARM_CPU_CLASS(oc); 2861 2862 acc->info = data; 2863 } 2864 2865 void arm_cpu_register(const ARMCPUInfo *info) 2866 { 2867 TypeInfo type_info = { 2868 .parent = TYPE_ARM_CPU, 2869 .instance_size = sizeof(ARMCPU), 2870 .instance_init = arm_cpu_instance_init, 2871 .class_size = sizeof(ARMCPUClass), 2872 .class_init = info->class_init ?: cpu_register_class_init, 2873 .class_data = (void *)info, 2874 }; 2875 2876 type_info.name = g_strdup_printf("%s-" TYPE_ARM_CPU, info->name); 2877 type_register(&type_info); 2878 g_free((void *)type_info.name); 2879 } 2880 2881 static const TypeInfo arm_cpu_type_info = { 2882 .name = TYPE_ARM_CPU, 2883 .parent = TYPE_CPU, 2884 .instance_size = sizeof(ARMCPU), 2885 .instance_init = arm_cpu_initfn, 2886 .instance_finalize = arm_cpu_finalizefn, 2887 .abstract = true, 2888 .class_size = sizeof(ARMCPUClass), 2889 .class_init = arm_cpu_class_init, 2890 }; 2891 2892 static const TypeInfo idau_interface_type_info = { 2893 .name = TYPE_IDAU_INTERFACE, 2894 .parent = TYPE_INTERFACE, 2895 .class_size = sizeof(IDAUInterfaceClass), 2896 }; 2897 2898 static void arm_cpu_register_types(void) 2899 { 2900 const ARMCPUInfo *info = arm_cpus; 2901 2902 type_register_static(&arm_cpu_type_info); 2903 type_register_static(&idau_interface_type_info); 2904 2905 while (info->name) { 2906 arm_cpu_register(info); 2907 info++; 2908 } 2909 2910 #ifdef CONFIG_KVM 2911 type_register_static(&host_arm_cpu_type_info); 2912 #endif 2913 } 2914 2915 type_init(arm_cpu_register_types) 2916