1 /* 2 * QEMU ARM CPU 3 * 4 * Copyright (c) 2012 SUSE LINUX Products GmbH 5 * 6 * This program is free software; you can redistribute it and/or 7 * modify it under the terms of the GNU General Public License 8 * as published by the Free Software Foundation; either version 2 9 * of the License, or (at your option) any later version. 10 * 11 * This program is distributed in the hope that it will be useful, 12 * but WITHOUT ANY WARRANTY; without even the implied warranty of 13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 14 * GNU General Public License for more details. 15 * 16 * You should have received a copy of the GNU General Public License 17 * along with this program; if not, see 18 * <http://www.gnu.org/licenses/gpl-2.0.html> 19 */ 20 21 #include "qemu/osdep.h" 22 #include "qemu-common.h" 23 #include "target/arm/idau.h" 24 #include "qemu/module.h" 25 #include "qapi/error.h" 26 #include "qapi/visitor.h" 27 #include "cpu.h" 28 #include "internals.h" 29 #include "exec/exec-all.h" 30 #include "hw/qdev-properties.h" 31 #if !defined(CONFIG_USER_ONLY) 32 #include "hw/loader.h" 33 #endif 34 #include "sysemu/sysemu.h" 35 #include "sysemu/tcg.h" 36 #include "sysemu/hw_accel.h" 37 #include "kvm_arm.h" 38 #include "disas/capstone.h" 39 #include "fpu/softfloat.h" 40 41 static void arm_cpu_set_pc(CPUState *cs, vaddr value) 42 { 43 ARMCPU *cpu = ARM_CPU(cs); 44 CPUARMState *env = &cpu->env; 45 46 if (is_a64(env)) { 47 env->pc = value; 48 env->thumb = 0; 49 } else { 50 env->regs[15] = value & ~1; 51 env->thumb = value & 1; 52 } 53 } 54 55 static void arm_cpu_synchronize_from_tb(CPUState *cs, TranslationBlock *tb) 56 { 57 ARMCPU *cpu = ARM_CPU(cs); 58 CPUARMState *env = &cpu->env; 59 60 /* 61 * It's OK to look at env for the current mode here, because it's 62 * never possible for an AArch64 TB to chain to an AArch32 TB. 63 */ 64 if (is_a64(env)) { 65 env->pc = tb->pc; 66 } else { 67 env->regs[15] = tb->pc; 68 } 69 } 70 71 static bool arm_cpu_has_work(CPUState *cs) 72 { 73 ARMCPU *cpu = ARM_CPU(cs); 74 75 return (cpu->power_state != PSCI_OFF) 76 && cs->interrupt_request & 77 (CPU_INTERRUPT_FIQ | CPU_INTERRUPT_HARD 78 | CPU_INTERRUPT_VFIQ | CPU_INTERRUPT_VIRQ 79 | CPU_INTERRUPT_EXITTB); 80 } 81 82 void arm_register_pre_el_change_hook(ARMCPU *cpu, ARMELChangeHookFn *hook, 83 void *opaque) 84 { 85 ARMELChangeHook *entry = g_new0(ARMELChangeHook, 1); 86 87 entry->hook = hook; 88 entry->opaque = opaque; 89 90 QLIST_INSERT_HEAD(&cpu->pre_el_change_hooks, entry, node); 91 } 92 93 void arm_register_el_change_hook(ARMCPU *cpu, ARMELChangeHookFn *hook, 94 void *opaque) 95 { 96 ARMELChangeHook *entry = g_new0(ARMELChangeHook, 1); 97 98 entry->hook = hook; 99 entry->opaque = opaque; 100 101 QLIST_INSERT_HEAD(&cpu->el_change_hooks, entry, node); 102 } 103 104 static void cp_reg_reset(gpointer key, gpointer value, gpointer opaque) 105 { 106 /* Reset a single ARMCPRegInfo register */ 107 ARMCPRegInfo *ri = value; 108 ARMCPU *cpu = opaque; 109 110 if (ri->type & (ARM_CP_SPECIAL | ARM_CP_ALIAS)) { 111 return; 112 } 113 114 if (ri->resetfn) { 115 ri->resetfn(&cpu->env, ri); 116 return; 117 } 118 119 /* A zero offset is never possible as it would be regs[0] 120 * so we use it to indicate that reset is being handled elsewhere. 121 * This is basically only used for fields in non-core coprocessors 122 * (like the pxa2xx ones). 123 */ 124 if (!ri->fieldoffset) { 125 return; 126 } 127 128 if (cpreg_field_is_64bit(ri)) { 129 CPREG_FIELD64(&cpu->env, ri) = ri->resetvalue; 130 } else { 131 CPREG_FIELD32(&cpu->env, ri) = ri->resetvalue; 132 } 133 } 134 135 static void cp_reg_check_reset(gpointer key, gpointer value, gpointer opaque) 136 { 137 /* Purely an assertion check: we've already done reset once, 138 * so now check that running the reset for the cpreg doesn't 139 * change its value. This traps bugs where two different cpregs 140 * both try to reset the same state field but to different values. 141 */ 142 ARMCPRegInfo *ri = value; 143 ARMCPU *cpu = opaque; 144 uint64_t oldvalue, newvalue; 145 146 if (ri->type & (ARM_CP_SPECIAL | ARM_CP_ALIAS | ARM_CP_NO_RAW)) { 147 return; 148 } 149 150 oldvalue = read_raw_cp_reg(&cpu->env, ri); 151 cp_reg_reset(key, value, opaque); 152 newvalue = read_raw_cp_reg(&cpu->env, ri); 153 assert(oldvalue == newvalue); 154 } 155 156 /* CPUClass::reset() */ 157 static void arm_cpu_reset(CPUState *s) 158 { 159 ARMCPU *cpu = ARM_CPU(s); 160 ARMCPUClass *acc = ARM_CPU_GET_CLASS(cpu); 161 CPUARMState *env = &cpu->env; 162 163 acc->parent_reset(s); 164 165 memset(env, 0, offsetof(CPUARMState, end_reset_fields)); 166 167 g_hash_table_foreach(cpu->cp_regs, cp_reg_reset, cpu); 168 g_hash_table_foreach(cpu->cp_regs, cp_reg_check_reset, cpu); 169 170 env->vfp.xregs[ARM_VFP_FPSID] = cpu->reset_fpsid; 171 env->vfp.xregs[ARM_VFP_MVFR0] = cpu->isar.mvfr0; 172 env->vfp.xregs[ARM_VFP_MVFR1] = cpu->isar.mvfr1; 173 env->vfp.xregs[ARM_VFP_MVFR2] = cpu->isar.mvfr2; 174 175 cpu->power_state = cpu->start_powered_off ? PSCI_OFF : PSCI_ON; 176 s->halted = cpu->start_powered_off; 177 178 if (arm_feature(env, ARM_FEATURE_IWMMXT)) { 179 env->iwmmxt.cregs[ARM_IWMMXT_wCID] = 0x69051000 | 'Q'; 180 } 181 182 if (arm_feature(env, ARM_FEATURE_AARCH64)) { 183 /* 64 bit CPUs always start in 64 bit mode */ 184 env->aarch64 = 1; 185 #if defined(CONFIG_USER_ONLY) 186 env->pstate = PSTATE_MODE_EL0t; 187 /* Userspace expects access to DC ZVA, CTL_EL0 and the cache ops */ 188 env->cp15.sctlr_el[1] |= SCTLR_UCT | SCTLR_UCI | SCTLR_DZE; 189 /* Enable all PAC keys. */ 190 env->cp15.sctlr_el[1] |= (SCTLR_EnIA | SCTLR_EnIB | 191 SCTLR_EnDA | SCTLR_EnDB); 192 /* Enable all PAC instructions */ 193 env->cp15.hcr_el2 |= HCR_API; 194 env->cp15.scr_el3 |= SCR_API; 195 /* and to the FP/Neon instructions */ 196 env->cp15.cpacr_el1 = deposit64(env->cp15.cpacr_el1, 20, 2, 3); 197 /* and to the SVE instructions */ 198 env->cp15.cpacr_el1 = deposit64(env->cp15.cpacr_el1, 16, 2, 3); 199 env->cp15.cptr_el[3] |= CPTR_EZ; 200 /* with maximum vector length */ 201 env->vfp.zcr_el[1] = cpu->sve_max_vq - 1; 202 env->vfp.zcr_el[2] = env->vfp.zcr_el[1]; 203 env->vfp.zcr_el[3] = env->vfp.zcr_el[1]; 204 /* 205 * Enable TBI0 and TBI1. While the real kernel only enables TBI0, 206 * turning on both here will produce smaller code and otherwise 207 * make no difference to the user-level emulation. 208 */ 209 env->cp15.tcr_el[1].raw_tcr = (3ULL << 37); 210 #else 211 /* Reset into the highest available EL */ 212 if (arm_feature(env, ARM_FEATURE_EL3)) { 213 env->pstate = PSTATE_MODE_EL3h; 214 } else if (arm_feature(env, ARM_FEATURE_EL2)) { 215 env->pstate = PSTATE_MODE_EL2h; 216 } else { 217 env->pstate = PSTATE_MODE_EL1h; 218 } 219 env->pc = cpu->rvbar; 220 #endif 221 } else { 222 #if defined(CONFIG_USER_ONLY) 223 /* Userspace expects access to cp10 and cp11 for FP/Neon */ 224 env->cp15.cpacr_el1 = deposit64(env->cp15.cpacr_el1, 20, 4, 0xf); 225 #endif 226 } 227 228 #if defined(CONFIG_USER_ONLY) 229 env->uncached_cpsr = ARM_CPU_MODE_USR; 230 /* For user mode we must enable access to coprocessors */ 231 env->vfp.xregs[ARM_VFP_FPEXC] = 1 << 30; 232 if (arm_feature(env, ARM_FEATURE_IWMMXT)) { 233 env->cp15.c15_cpar = 3; 234 } else if (arm_feature(env, ARM_FEATURE_XSCALE)) { 235 env->cp15.c15_cpar = 1; 236 } 237 #else 238 239 /* 240 * If the highest available EL is EL2, AArch32 will start in Hyp 241 * mode; otherwise it starts in SVC. Note that if we start in 242 * AArch64 then these values in the uncached_cpsr will be ignored. 243 */ 244 if (arm_feature(env, ARM_FEATURE_EL2) && 245 !arm_feature(env, ARM_FEATURE_EL3)) { 246 env->uncached_cpsr = ARM_CPU_MODE_HYP; 247 } else { 248 env->uncached_cpsr = ARM_CPU_MODE_SVC; 249 } 250 env->daif = PSTATE_D | PSTATE_A | PSTATE_I | PSTATE_F; 251 252 if (arm_feature(env, ARM_FEATURE_M)) { 253 uint32_t initial_msp; /* Loaded from 0x0 */ 254 uint32_t initial_pc; /* Loaded from 0x4 */ 255 uint8_t *rom; 256 uint32_t vecbase; 257 258 if (arm_feature(env, ARM_FEATURE_M_SECURITY)) { 259 env->v7m.secure = true; 260 } else { 261 /* This bit resets to 0 if security is supported, but 1 if 262 * it is not. The bit is not present in v7M, but we set it 263 * here so we can avoid having to make checks on it conditional 264 * on ARM_FEATURE_V8 (we don't let the guest see the bit). 265 */ 266 env->v7m.aircr = R_V7M_AIRCR_BFHFNMINS_MASK; 267 } 268 269 /* In v7M the reset value of this bit is IMPDEF, but ARM recommends 270 * that it resets to 1, so QEMU always does that rather than making 271 * it dependent on CPU model. In v8M it is RES1. 272 */ 273 env->v7m.ccr[M_REG_NS] = R_V7M_CCR_STKALIGN_MASK; 274 env->v7m.ccr[M_REG_S] = R_V7M_CCR_STKALIGN_MASK; 275 if (arm_feature(env, ARM_FEATURE_V8)) { 276 /* in v8M the NONBASETHRDENA bit [0] is RES1 */ 277 env->v7m.ccr[M_REG_NS] |= R_V7M_CCR_NONBASETHRDENA_MASK; 278 env->v7m.ccr[M_REG_S] |= R_V7M_CCR_NONBASETHRDENA_MASK; 279 } 280 if (!arm_feature(env, ARM_FEATURE_M_MAIN)) { 281 env->v7m.ccr[M_REG_NS] |= R_V7M_CCR_UNALIGN_TRP_MASK; 282 env->v7m.ccr[M_REG_S] |= R_V7M_CCR_UNALIGN_TRP_MASK; 283 } 284 285 if (arm_feature(env, ARM_FEATURE_VFP)) { 286 env->v7m.fpccr[M_REG_NS] = R_V7M_FPCCR_ASPEN_MASK; 287 env->v7m.fpccr[M_REG_S] = R_V7M_FPCCR_ASPEN_MASK | 288 R_V7M_FPCCR_LSPEN_MASK | R_V7M_FPCCR_S_MASK; 289 } 290 /* Unlike A/R profile, M profile defines the reset LR value */ 291 env->regs[14] = 0xffffffff; 292 293 env->v7m.vecbase[M_REG_S] = cpu->init_svtor & 0xffffff80; 294 295 /* Load the initial SP and PC from offset 0 and 4 in the vector table */ 296 vecbase = env->v7m.vecbase[env->v7m.secure]; 297 rom = rom_ptr(vecbase, 8); 298 if (rom) { 299 /* Address zero is covered by ROM which hasn't yet been 300 * copied into physical memory. 301 */ 302 initial_msp = ldl_p(rom); 303 initial_pc = ldl_p(rom + 4); 304 } else { 305 /* Address zero not covered by a ROM blob, or the ROM blob 306 * is in non-modifiable memory and this is a second reset after 307 * it got copied into memory. In the latter case, rom_ptr 308 * will return a NULL pointer and we should use ldl_phys instead. 309 */ 310 initial_msp = ldl_phys(s->as, vecbase); 311 initial_pc = ldl_phys(s->as, vecbase + 4); 312 } 313 314 env->regs[13] = initial_msp & 0xFFFFFFFC; 315 env->regs[15] = initial_pc & ~1; 316 env->thumb = initial_pc & 1; 317 } 318 319 /* AArch32 has a hard highvec setting of 0xFFFF0000. If we are currently 320 * executing as AArch32 then check if highvecs are enabled and 321 * adjust the PC accordingly. 322 */ 323 if (A32_BANKED_CURRENT_REG_GET(env, sctlr) & SCTLR_V) { 324 env->regs[15] = 0xFFFF0000; 325 } 326 327 /* M profile requires that reset clears the exclusive monitor; 328 * A profile does not, but clearing it makes more sense than having it 329 * set with an exclusive access on address zero. 330 */ 331 arm_clear_exclusive(env); 332 333 env->vfp.xregs[ARM_VFP_FPEXC] = 0; 334 #endif 335 336 if (arm_feature(env, ARM_FEATURE_PMSA)) { 337 if (cpu->pmsav7_dregion > 0) { 338 if (arm_feature(env, ARM_FEATURE_V8)) { 339 memset(env->pmsav8.rbar[M_REG_NS], 0, 340 sizeof(*env->pmsav8.rbar[M_REG_NS]) 341 * cpu->pmsav7_dregion); 342 memset(env->pmsav8.rlar[M_REG_NS], 0, 343 sizeof(*env->pmsav8.rlar[M_REG_NS]) 344 * cpu->pmsav7_dregion); 345 if (arm_feature(env, ARM_FEATURE_M_SECURITY)) { 346 memset(env->pmsav8.rbar[M_REG_S], 0, 347 sizeof(*env->pmsav8.rbar[M_REG_S]) 348 * cpu->pmsav7_dregion); 349 memset(env->pmsav8.rlar[M_REG_S], 0, 350 sizeof(*env->pmsav8.rlar[M_REG_S]) 351 * cpu->pmsav7_dregion); 352 } 353 } else if (arm_feature(env, ARM_FEATURE_V7)) { 354 memset(env->pmsav7.drbar, 0, 355 sizeof(*env->pmsav7.drbar) * cpu->pmsav7_dregion); 356 memset(env->pmsav7.drsr, 0, 357 sizeof(*env->pmsav7.drsr) * cpu->pmsav7_dregion); 358 memset(env->pmsav7.dracr, 0, 359 sizeof(*env->pmsav7.dracr) * cpu->pmsav7_dregion); 360 } 361 } 362 env->pmsav7.rnr[M_REG_NS] = 0; 363 env->pmsav7.rnr[M_REG_S] = 0; 364 env->pmsav8.mair0[M_REG_NS] = 0; 365 env->pmsav8.mair0[M_REG_S] = 0; 366 env->pmsav8.mair1[M_REG_NS] = 0; 367 env->pmsav8.mair1[M_REG_S] = 0; 368 } 369 370 if (arm_feature(env, ARM_FEATURE_M_SECURITY)) { 371 if (cpu->sau_sregion > 0) { 372 memset(env->sau.rbar, 0, sizeof(*env->sau.rbar) * cpu->sau_sregion); 373 memset(env->sau.rlar, 0, sizeof(*env->sau.rlar) * cpu->sau_sregion); 374 } 375 env->sau.rnr = 0; 376 /* SAU_CTRL reset value is IMPDEF; we choose 0, which is what 377 * the Cortex-M33 does. 378 */ 379 env->sau.ctrl = 0; 380 } 381 382 set_flush_to_zero(1, &env->vfp.standard_fp_status); 383 set_flush_inputs_to_zero(1, &env->vfp.standard_fp_status); 384 set_default_nan_mode(1, &env->vfp.standard_fp_status); 385 set_float_detect_tininess(float_tininess_before_rounding, 386 &env->vfp.fp_status); 387 set_float_detect_tininess(float_tininess_before_rounding, 388 &env->vfp.standard_fp_status); 389 set_float_detect_tininess(float_tininess_before_rounding, 390 &env->vfp.fp_status_f16); 391 #ifndef CONFIG_USER_ONLY 392 if (kvm_enabled()) { 393 kvm_arm_reset_vcpu(cpu); 394 } 395 #endif 396 397 hw_breakpoint_update_all(cpu); 398 hw_watchpoint_update_all(cpu); 399 } 400 401 bool arm_cpu_exec_interrupt(CPUState *cs, int interrupt_request) 402 { 403 CPUClass *cc = CPU_GET_CLASS(cs); 404 CPUARMState *env = cs->env_ptr; 405 uint32_t cur_el = arm_current_el(env); 406 bool secure = arm_is_secure(env); 407 uint32_t target_el; 408 uint32_t excp_idx; 409 bool ret = false; 410 411 if (interrupt_request & CPU_INTERRUPT_FIQ) { 412 excp_idx = EXCP_FIQ; 413 target_el = arm_phys_excp_target_el(cs, excp_idx, cur_el, secure); 414 if (arm_excp_unmasked(cs, excp_idx, target_el)) { 415 cs->exception_index = excp_idx; 416 env->exception.target_el = target_el; 417 cc->do_interrupt(cs); 418 ret = true; 419 } 420 } 421 if (interrupt_request & CPU_INTERRUPT_HARD) { 422 excp_idx = EXCP_IRQ; 423 target_el = arm_phys_excp_target_el(cs, excp_idx, cur_el, secure); 424 if (arm_excp_unmasked(cs, excp_idx, target_el)) { 425 cs->exception_index = excp_idx; 426 env->exception.target_el = target_el; 427 cc->do_interrupt(cs); 428 ret = true; 429 } 430 } 431 if (interrupt_request & CPU_INTERRUPT_VIRQ) { 432 excp_idx = EXCP_VIRQ; 433 target_el = 1; 434 if (arm_excp_unmasked(cs, excp_idx, target_el)) { 435 cs->exception_index = excp_idx; 436 env->exception.target_el = target_el; 437 cc->do_interrupt(cs); 438 ret = true; 439 } 440 } 441 if (interrupt_request & CPU_INTERRUPT_VFIQ) { 442 excp_idx = EXCP_VFIQ; 443 target_el = 1; 444 if (arm_excp_unmasked(cs, excp_idx, target_el)) { 445 cs->exception_index = excp_idx; 446 env->exception.target_el = target_el; 447 cc->do_interrupt(cs); 448 ret = true; 449 } 450 } 451 452 return ret; 453 } 454 455 #if !defined(CONFIG_USER_ONLY) || !defined(TARGET_AARCH64) 456 static bool arm_v7m_cpu_exec_interrupt(CPUState *cs, int interrupt_request) 457 { 458 CPUClass *cc = CPU_GET_CLASS(cs); 459 ARMCPU *cpu = ARM_CPU(cs); 460 CPUARMState *env = &cpu->env; 461 bool ret = false; 462 463 /* ARMv7-M interrupt masking works differently than -A or -R. 464 * There is no FIQ/IRQ distinction. Instead of I and F bits 465 * masking FIQ and IRQ interrupts, an exception is taken only 466 * if it is higher priority than the current execution priority 467 * (which depends on state like BASEPRI, FAULTMASK and the 468 * currently active exception). 469 */ 470 if (interrupt_request & CPU_INTERRUPT_HARD 471 && (armv7m_nvic_can_take_pending_exception(env->nvic))) { 472 cs->exception_index = EXCP_IRQ; 473 cc->do_interrupt(cs); 474 ret = true; 475 } 476 return ret; 477 } 478 #endif 479 480 void arm_cpu_update_virq(ARMCPU *cpu) 481 { 482 /* 483 * Update the interrupt level for VIRQ, which is the logical OR of 484 * the HCR_EL2.VI bit and the input line level from the GIC. 485 */ 486 CPUARMState *env = &cpu->env; 487 CPUState *cs = CPU(cpu); 488 489 bool new_state = (env->cp15.hcr_el2 & HCR_VI) || 490 (env->irq_line_state & CPU_INTERRUPT_VIRQ); 491 492 if (new_state != ((cs->interrupt_request & CPU_INTERRUPT_VIRQ) != 0)) { 493 if (new_state) { 494 cpu_interrupt(cs, CPU_INTERRUPT_VIRQ); 495 } else { 496 cpu_reset_interrupt(cs, CPU_INTERRUPT_VIRQ); 497 } 498 } 499 } 500 501 void arm_cpu_update_vfiq(ARMCPU *cpu) 502 { 503 /* 504 * Update the interrupt level for VFIQ, which is the logical OR of 505 * the HCR_EL2.VF bit and the input line level from the GIC. 506 */ 507 CPUARMState *env = &cpu->env; 508 CPUState *cs = CPU(cpu); 509 510 bool new_state = (env->cp15.hcr_el2 & HCR_VF) || 511 (env->irq_line_state & CPU_INTERRUPT_VFIQ); 512 513 if (new_state != ((cs->interrupt_request & CPU_INTERRUPT_VFIQ) != 0)) { 514 if (new_state) { 515 cpu_interrupt(cs, CPU_INTERRUPT_VFIQ); 516 } else { 517 cpu_reset_interrupt(cs, CPU_INTERRUPT_VFIQ); 518 } 519 } 520 } 521 522 #ifndef CONFIG_USER_ONLY 523 static void arm_cpu_set_irq(void *opaque, int irq, int level) 524 { 525 ARMCPU *cpu = opaque; 526 CPUARMState *env = &cpu->env; 527 CPUState *cs = CPU(cpu); 528 static const int mask[] = { 529 [ARM_CPU_IRQ] = CPU_INTERRUPT_HARD, 530 [ARM_CPU_FIQ] = CPU_INTERRUPT_FIQ, 531 [ARM_CPU_VIRQ] = CPU_INTERRUPT_VIRQ, 532 [ARM_CPU_VFIQ] = CPU_INTERRUPT_VFIQ 533 }; 534 535 if (level) { 536 env->irq_line_state |= mask[irq]; 537 } else { 538 env->irq_line_state &= ~mask[irq]; 539 } 540 541 switch (irq) { 542 case ARM_CPU_VIRQ: 543 assert(arm_feature(env, ARM_FEATURE_EL2)); 544 arm_cpu_update_virq(cpu); 545 break; 546 case ARM_CPU_VFIQ: 547 assert(arm_feature(env, ARM_FEATURE_EL2)); 548 arm_cpu_update_vfiq(cpu); 549 break; 550 case ARM_CPU_IRQ: 551 case ARM_CPU_FIQ: 552 if (level) { 553 cpu_interrupt(cs, mask[irq]); 554 } else { 555 cpu_reset_interrupt(cs, mask[irq]); 556 } 557 break; 558 default: 559 g_assert_not_reached(); 560 } 561 } 562 563 static void arm_cpu_kvm_set_irq(void *opaque, int irq, int level) 564 { 565 #ifdef CONFIG_KVM 566 ARMCPU *cpu = opaque; 567 CPUARMState *env = &cpu->env; 568 CPUState *cs = CPU(cpu); 569 int kvm_irq = KVM_ARM_IRQ_TYPE_CPU << KVM_ARM_IRQ_TYPE_SHIFT; 570 uint32_t linestate_bit; 571 572 switch (irq) { 573 case ARM_CPU_IRQ: 574 kvm_irq |= KVM_ARM_IRQ_CPU_IRQ; 575 linestate_bit = CPU_INTERRUPT_HARD; 576 break; 577 case ARM_CPU_FIQ: 578 kvm_irq |= KVM_ARM_IRQ_CPU_FIQ; 579 linestate_bit = CPU_INTERRUPT_FIQ; 580 break; 581 default: 582 g_assert_not_reached(); 583 } 584 585 if (level) { 586 env->irq_line_state |= linestate_bit; 587 } else { 588 env->irq_line_state &= ~linestate_bit; 589 } 590 591 kvm_irq |= cs->cpu_index << KVM_ARM_IRQ_VCPU_SHIFT; 592 kvm_set_irq(kvm_state, kvm_irq, level ? 1 : 0); 593 #endif 594 } 595 596 static bool arm_cpu_virtio_is_big_endian(CPUState *cs) 597 { 598 ARMCPU *cpu = ARM_CPU(cs); 599 CPUARMState *env = &cpu->env; 600 601 cpu_synchronize_state(cs); 602 return arm_cpu_data_is_big_endian(env); 603 } 604 605 #endif 606 607 static inline void set_feature(CPUARMState *env, int feature) 608 { 609 env->features |= 1ULL << feature; 610 } 611 612 static inline void unset_feature(CPUARMState *env, int feature) 613 { 614 env->features &= ~(1ULL << feature); 615 } 616 617 static int 618 print_insn_thumb1(bfd_vma pc, disassemble_info *info) 619 { 620 return print_insn_arm(pc | 1, info); 621 } 622 623 static void arm_disas_set_info(CPUState *cpu, disassemble_info *info) 624 { 625 ARMCPU *ac = ARM_CPU(cpu); 626 CPUARMState *env = &ac->env; 627 bool sctlr_b; 628 629 if (is_a64(env)) { 630 /* We might not be compiled with the A64 disassembler 631 * because it needs a C++ compiler. Leave print_insn 632 * unset in this case to use the caller default behaviour. 633 */ 634 #if defined(CONFIG_ARM_A64_DIS) 635 info->print_insn = print_insn_arm_a64; 636 #endif 637 info->cap_arch = CS_ARCH_ARM64; 638 info->cap_insn_unit = 4; 639 info->cap_insn_split = 4; 640 } else { 641 int cap_mode; 642 if (env->thumb) { 643 info->print_insn = print_insn_thumb1; 644 info->cap_insn_unit = 2; 645 info->cap_insn_split = 4; 646 cap_mode = CS_MODE_THUMB; 647 } else { 648 info->print_insn = print_insn_arm; 649 info->cap_insn_unit = 4; 650 info->cap_insn_split = 4; 651 cap_mode = CS_MODE_ARM; 652 } 653 if (arm_feature(env, ARM_FEATURE_V8)) { 654 cap_mode |= CS_MODE_V8; 655 } 656 if (arm_feature(env, ARM_FEATURE_M)) { 657 cap_mode |= CS_MODE_MCLASS; 658 } 659 info->cap_arch = CS_ARCH_ARM; 660 info->cap_mode = cap_mode; 661 } 662 663 sctlr_b = arm_sctlr_b(env); 664 if (bswap_code(sctlr_b)) { 665 #ifdef TARGET_WORDS_BIGENDIAN 666 info->endian = BFD_ENDIAN_LITTLE; 667 #else 668 info->endian = BFD_ENDIAN_BIG; 669 #endif 670 } 671 info->flags &= ~INSN_ARM_BE32; 672 #ifndef CONFIG_USER_ONLY 673 if (sctlr_b) { 674 info->flags |= INSN_ARM_BE32; 675 } 676 #endif 677 } 678 679 uint64_t arm_cpu_mp_affinity(int idx, uint8_t clustersz) 680 { 681 uint32_t Aff1 = idx / clustersz; 682 uint32_t Aff0 = idx % clustersz; 683 return (Aff1 << ARM_AFF1_SHIFT) | Aff0; 684 } 685 686 static void cpreg_hashtable_data_destroy(gpointer data) 687 { 688 /* 689 * Destroy function for cpu->cp_regs hashtable data entries. 690 * We must free the name string because it was g_strdup()ed in 691 * add_cpreg_to_hashtable(). It's OK to cast away the 'const' 692 * from r->name because we know we definitely allocated it. 693 */ 694 ARMCPRegInfo *r = data; 695 696 g_free((void *)r->name); 697 g_free(r); 698 } 699 700 static void arm_cpu_initfn(Object *obj) 701 { 702 ARMCPU *cpu = ARM_CPU(obj); 703 704 cpu_set_cpustate_pointers(cpu); 705 cpu->cp_regs = g_hash_table_new_full(g_int_hash, g_int_equal, 706 g_free, cpreg_hashtable_data_destroy); 707 708 QLIST_INIT(&cpu->pre_el_change_hooks); 709 QLIST_INIT(&cpu->el_change_hooks); 710 711 #ifndef CONFIG_USER_ONLY 712 /* Our inbound IRQ and FIQ lines */ 713 if (kvm_enabled()) { 714 /* VIRQ and VFIQ are unused with KVM but we add them to maintain 715 * the same interface as non-KVM CPUs. 716 */ 717 qdev_init_gpio_in(DEVICE(cpu), arm_cpu_kvm_set_irq, 4); 718 } else { 719 qdev_init_gpio_in(DEVICE(cpu), arm_cpu_set_irq, 4); 720 } 721 722 qdev_init_gpio_out(DEVICE(cpu), cpu->gt_timer_outputs, 723 ARRAY_SIZE(cpu->gt_timer_outputs)); 724 725 qdev_init_gpio_out_named(DEVICE(cpu), &cpu->gicv3_maintenance_interrupt, 726 "gicv3-maintenance-interrupt", 1); 727 qdev_init_gpio_out_named(DEVICE(cpu), &cpu->pmu_interrupt, 728 "pmu-interrupt", 1); 729 #endif 730 731 /* DTB consumers generally don't in fact care what the 'compatible' 732 * string is, so always provide some string and trust that a hypothetical 733 * picky DTB consumer will also provide a helpful error message. 734 */ 735 cpu->dtb_compatible = "qemu,unknown"; 736 cpu->psci_version = 1; /* By default assume PSCI v0.1 */ 737 cpu->kvm_target = QEMU_KVM_ARM_TARGET_NONE; 738 739 if (tcg_enabled()) { 740 cpu->psci_version = 2; /* TCG implements PSCI 0.2 */ 741 } 742 } 743 744 static Property arm_cpu_reset_cbar_property = 745 DEFINE_PROP_UINT64("reset-cbar", ARMCPU, reset_cbar, 0); 746 747 static Property arm_cpu_reset_hivecs_property = 748 DEFINE_PROP_BOOL("reset-hivecs", ARMCPU, reset_hivecs, false); 749 750 static Property arm_cpu_rvbar_property = 751 DEFINE_PROP_UINT64("rvbar", ARMCPU, rvbar, 0); 752 753 static Property arm_cpu_has_el2_property = 754 DEFINE_PROP_BOOL("has_el2", ARMCPU, has_el2, true); 755 756 static Property arm_cpu_has_el3_property = 757 DEFINE_PROP_BOOL("has_el3", ARMCPU, has_el3, true); 758 759 static Property arm_cpu_cfgend_property = 760 DEFINE_PROP_BOOL("cfgend", ARMCPU, cfgend, false); 761 762 /* use property name "pmu" to match other archs and virt tools */ 763 static Property arm_cpu_has_pmu_property = 764 DEFINE_PROP_BOOL("pmu", ARMCPU, has_pmu, true); 765 766 static Property arm_cpu_has_vfp_property = 767 DEFINE_PROP_BOOL("vfp", ARMCPU, has_vfp, true); 768 769 static Property arm_cpu_has_neon_property = 770 DEFINE_PROP_BOOL("neon", ARMCPU, has_neon, true); 771 772 static Property arm_cpu_has_dsp_property = 773 DEFINE_PROP_BOOL("dsp", ARMCPU, has_dsp, true); 774 775 static Property arm_cpu_has_mpu_property = 776 DEFINE_PROP_BOOL("has-mpu", ARMCPU, has_mpu, true); 777 778 /* This is like DEFINE_PROP_UINT32 but it doesn't set the default value, 779 * because the CPU initfn will have already set cpu->pmsav7_dregion to 780 * the right value for that particular CPU type, and we don't want 781 * to override that with an incorrect constant value. 782 */ 783 static Property arm_cpu_pmsav7_dregion_property = 784 DEFINE_PROP_UNSIGNED_NODEFAULT("pmsav7-dregion", ARMCPU, 785 pmsav7_dregion, 786 qdev_prop_uint32, uint32_t); 787 788 static void arm_get_init_svtor(Object *obj, Visitor *v, const char *name, 789 void *opaque, Error **errp) 790 { 791 ARMCPU *cpu = ARM_CPU(obj); 792 793 visit_type_uint32(v, name, &cpu->init_svtor, errp); 794 } 795 796 static void arm_set_init_svtor(Object *obj, Visitor *v, const char *name, 797 void *opaque, Error **errp) 798 { 799 ARMCPU *cpu = ARM_CPU(obj); 800 801 visit_type_uint32(v, name, &cpu->init_svtor, errp); 802 } 803 804 void arm_cpu_post_init(Object *obj) 805 { 806 ARMCPU *cpu = ARM_CPU(obj); 807 808 /* M profile implies PMSA. We have to do this here rather than 809 * in realize with the other feature-implication checks because 810 * we look at the PMSA bit to see if we should add some properties. 811 */ 812 if (arm_feature(&cpu->env, ARM_FEATURE_M)) { 813 set_feature(&cpu->env, ARM_FEATURE_PMSA); 814 } 815 /* Similarly for the VFP feature bits */ 816 if (arm_feature(&cpu->env, ARM_FEATURE_VFP4)) { 817 set_feature(&cpu->env, ARM_FEATURE_VFP3); 818 } 819 if (arm_feature(&cpu->env, ARM_FEATURE_VFP3)) { 820 set_feature(&cpu->env, ARM_FEATURE_VFP); 821 } 822 823 if (arm_feature(&cpu->env, ARM_FEATURE_CBAR) || 824 arm_feature(&cpu->env, ARM_FEATURE_CBAR_RO)) { 825 qdev_property_add_static(DEVICE(obj), &arm_cpu_reset_cbar_property, 826 &error_abort); 827 } 828 829 if (!arm_feature(&cpu->env, ARM_FEATURE_M)) { 830 qdev_property_add_static(DEVICE(obj), &arm_cpu_reset_hivecs_property, 831 &error_abort); 832 } 833 834 if (arm_feature(&cpu->env, ARM_FEATURE_AARCH64)) { 835 qdev_property_add_static(DEVICE(obj), &arm_cpu_rvbar_property, 836 &error_abort); 837 } 838 839 if (arm_feature(&cpu->env, ARM_FEATURE_EL3)) { 840 /* Add the has_el3 state CPU property only if EL3 is allowed. This will 841 * prevent "has_el3" from existing on CPUs which cannot support EL3. 842 */ 843 qdev_property_add_static(DEVICE(obj), &arm_cpu_has_el3_property, 844 &error_abort); 845 846 #ifndef CONFIG_USER_ONLY 847 object_property_add_link(obj, "secure-memory", 848 TYPE_MEMORY_REGION, 849 (Object **)&cpu->secure_memory, 850 qdev_prop_allow_set_link_before_realize, 851 OBJ_PROP_LINK_STRONG, 852 &error_abort); 853 #endif 854 } 855 856 if (arm_feature(&cpu->env, ARM_FEATURE_EL2)) { 857 qdev_property_add_static(DEVICE(obj), &arm_cpu_has_el2_property, 858 &error_abort); 859 } 860 861 if (arm_feature(&cpu->env, ARM_FEATURE_PMU)) { 862 qdev_property_add_static(DEVICE(obj), &arm_cpu_has_pmu_property, 863 &error_abort); 864 } 865 866 /* 867 * Allow user to turn off VFP and Neon support, but only for TCG -- 868 * KVM does not currently allow us to lie to the guest about its 869 * ID/feature registers, so the guest always sees what the host has. 870 */ 871 if (arm_feature(&cpu->env, ARM_FEATURE_VFP)) { 872 cpu->has_vfp = true; 873 if (!kvm_enabled()) { 874 qdev_property_add_static(DEVICE(obj), &arm_cpu_has_vfp_property, 875 &error_abort); 876 } 877 } 878 879 if (arm_feature(&cpu->env, ARM_FEATURE_NEON)) { 880 cpu->has_neon = true; 881 if (!kvm_enabled()) { 882 qdev_property_add_static(DEVICE(obj), &arm_cpu_has_neon_property, 883 &error_abort); 884 } 885 } 886 887 if (arm_feature(&cpu->env, ARM_FEATURE_M) && 888 arm_feature(&cpu->env, ARM_FEATURE_THUMB_DSP)) { 889 qdev_property_add_static(DEVICE(obj), &arm_cpu_has_dsp_property, 890 &error_abort); 891 } 892 893 if (arm_feature(&cpu->env, ARM_FEATURE_PMSA)) { 894 qdev_property_add_static(DEVICE(obj), &arm_cpu_has_mpu_property, 895 &error_abort); 896 if (arm_feature(&cpu->env, ARM_FEATURE_V7)) { 897 qdev_property_add_static(DEVICE(obj), 898 &arm_cpu_pmsav7_dregion_property, 899 &error_abort); 900 } 901 } 902 903 if (arm_feature(&cpu->env, ARM_FEATURE_M_SECURITY)) { 904 object_property_add_link(obj, "idau", TYPE_IDAU_INTERFACE, &cpu->idau, 905 qdev_prop_allow_set_link_before_realize, 906 OBJ_PROP_LINK_STRONG, 907 &error_abort); 908 /* 909 * M profile: initial value of the Secure VTOR. We can't just use 910 * a simple DEFINE_PROP_UINT32 for this because we want to permit 911 * the property to be set after realize. 912 */ 913 object_property_add(obj, "init-svtor", "uint32", 914 arm_get_init_svtor, arm_set_init_svtor, 915 NULL, NULL, &error_abort); 916 } 917 918 qdev_property_add_static(DEVICE(obj), &arm_cpu_cfgend_property, 919 &error_abort); 920 } 921 922 static void arm_cpu_finalizefn(Object *obj) 923 { 924 ARMCPU *cpu = ARM_CPU(obj); 925 ARMELChangeHook *hook, *next; 926 927 g_hash_table_destroy(cpu->cp_regs); 928 929 QLIST_FOREACH_SAFE(hook, &cpu->pre_el_change_hooks, node, next) { 930 QLIST_REMOVE(hook, node); 931 g_free(hook); 932 } 933 QLIST_FOREACH_SAFE(hook, &cpu->el_change_hooks, node, next) { 934 QLIST_REMOVE(hook, node); 935 g_free(hook); 936 } 937 #ifndef CONFIG_USER_ONLY 938 if (cpu->pmu_timer) { 939 timer_del(cpu->pmu_timer); 940 timer_deinit(cpu->pmu_timer); 941 timer_free(cpu->pmu_timer); 942 } 943 #endif 944 } 945 946 static void arm_cpu_realizefn(DeviceState *dev, Error **errp) 947 { 948 CPUState *cs = CPU(dev); 949 ARMCPU *cpu = ARM_CPU(dev); 950 ARMCPUClass *acc = ARM_CPU_GET_CLASS(dev); 951 CPUARMState *env = &cpu->env; 952 int pagebits; 953 Error *local_err = NULL; 954 bool no_aa32 = false; 955 956 /* If we needed to query the host kernel for the CPU features 957 * then it's possible that might have failed in the initfn, but 958 * this is the first point where we can report it. 959 */ 960 if (cpu->host_cpu_probe_failed) { 961 if (!kvm_enabled()) { 962 error_setg(errp, "The 'host' CPU type can only be used with KVM"); 963 } else { 964 error_setg(errp, "Failed to retrieve host CPU features"); 965 } 966 return; 967 } 968 969 #ifndef CONFIG_USER_ONLY 970 /* The NVIC and M-profile CPU are two halves of a single piece of 971 * hardware; trying to use one without the other is a command line 972 * error and will result in segfaults if not caught here. 973 */ 974 if (arm_feature(env, ARM_FEATURE_M)) { 975 if (!env->nvic) { 976 error_setg(errp, "This board cannot be used with Cortex-M CPUs"); 977 return; 978 } 979 } else { 980 if (env->nvic) { 981 error_setg(errp, "This board can only be used with Cortex-M CPUs"); 982 return; 983 } 984 } 985 986 cpu->gt_timer[GTIMER_PHYS] = timer_new(QEMU_CLOCK_VIRTUAL, GTIMER_SCALE, 987 arm_gt_ptimer_cb, cpu); 988 cpu->gt_timer[GTIMER_VIRT] = timer_new(QEMU_CLOCK_VIRTUAL, GTIMER_SCALE, 989 arm_gt_vtimer_cb, cpu); 990 cpu->gt_timer[GTIMER_HYP] = timer_new(QEMU_CLOCK_VIRTUAL, GTIMER_SCALE, 991 arm_gt_htimer_cb, cpu); 992 cpu->gt_timer[GTIMER_SEC] = timer_new(QEMU_CLOCK_VIRTUAL, GTIMER_SCALE, 993 arm_gt_stimer_cb, cpu); 994 #endif 995 996 cpu_exec_realizefn(cs, &local_err); 997 if (local_err != NULL) { 998 error_propagate(errp, local_err); 999 return; 1000 } 1001 1002 if (arm_feature(env, ARM_FEATURE_AARCH64) && 1003 cpu->has_vfp != cpu->has_neon) { 1004 /* 1005 * This is an architectural requirement for AArch64; AArch32 is 1006 * more flexible and permits VFP-no-Neon and Neon-no-VFP. 1007 */ 1008 error_setg(errp, 1009 "AArch64 CPUs must have both VFP and Neon or neither"); 1010 return; 1011 } 1012 1013 if (!cpu->has_vfp) { 1014 uint64_t t; 1015 uint32_t u; 1016 1017 unset_feature(env, ARM_FEATURE_VFP); 1018 unset_feature(env, ARM_FEATURE_VFP3); 1019 unset_feature(env, ARM_FEATURE_VFP4); 1020 1021 t = cpu->isar.id_aa64isar1; 1022 t = FIELD_DP64(t, ID_AA64ISAR1, JSCVT, 0); 1023 cpu->isar.id_aa64isar1 = t; 1024 1025 t = cpu->isar.id_aa64pfr0; 1026 t = FIELD_DP64(t, ID_AA64PFR0, FP, 0xf); 1027 cpu->isar.id_aa64pfr0 = t; 1028 1029 u = cpu->isar.id_isar6; 1030 u = FIELD_DP32(u, ID_ISAR6, JSCVT, 0); 1031 cpu->isar.id_isar6 = u; 1032 1033 u = cpu->isar.mvfr0; 1034 u = FIELD_DP32(u, MVFR0, FPSP, 0); 1035 u = FIELD_DP32(u, MVFR0, FPDP, 0); 1036 u = FIELD_DP32(u, MVFR0, FPTRAP, 0); 1037 u = FIELD_DP32(u, MVFR0, FPDIVIDE, 0); 1038 u = FIELD_DP32(u, MVFR0, FPSQRT, 0); 1039 u = FIELD_DP32(u, MVFR0, FPSHVEC, 0); 1040 u = FIELD_DP32(u, MVFR0, FPROUND, 0); 1041 cpu->isar.mvfr0 = u; 1042 1043 u = cpu->isar.mvfr1; 1044 u = FIELD_DP32(u, MVFR1, FPFTZ, 0); 1045 u = FIELD_DP32(u, MVFR1, FPDNAN, 0); 1046 u = FIELD_DP32(u, MVFR1, FPHP, 0); 1047 cpu->isar.mvfr1 = u; 1048 1049 u = cpu->isar.mvfr2; 1050 u = FIELD_DP32(u, MVFR2, FPMISC, 0); 1051 cpu->isar.mvfr2 = u; 1052 } 1053 1054 if (!cpu->has_neon) { 1055 uint64_t t; 1056 uint32_t u; 1057 1058 unset_feature(env, ARM_FEATURE_NEON); 1059 1060 t = cpu->isar.id_aa64isar0; 1061 t = FIELD_DP64(t, ID_AA64ISAR0, DP, 0); 1062 cpu->isar.id_aa64isar0 = t; 1063 1064 t = cpu->isar.id_aa64isar1; 1065 t = FIELD_DP64(t, ID_AA64ISAR1, FCMA, 0); 1066 cpu->isar.id_aa64isar1 = t; 1067 1068 t = cpu->isar.id_aa64pfr0; 1069 t = FIELD_DP64(t, ID_AA64PFR0, ADVSIMD, 0xf); 1070 cpu->isar.id_aa64pfr0 = t; 1071 1072 u = cpu->isar.id_isar5; 1073 u = FIELD_DP32(u, ID_ISAR5, RDM, 0); 1074 u = FIELD_DP32(u, ID_ISAR5, VCMA, 0); 1075 cpu->isar.id_isar5 = u; 1076 1077 u = cpu->isar.id_isar6; 1078 u = FIELD_DP32(u, ID_ISAR6, DP, 0); 1079 u = FIELD_DP32(u, ID_ISAR6, FHM, 0); 1080 cpu->isar.id_isar6 = u; 1081 1082 u = cpu->isar.mvfr1; 1083 u = FIELD_DP32(u, MVFR1, SIMDLS, 0); 1084 u = FIELD_DP32(u, MVFR1, SIMDINT, 0); 1085 u = FIELD_DP32(u, MVFR1, SIMDSP, 0); 1086 u = FIELD_DP32(u, MVFR1, SIMDHP, 0); 1087 u = FIELD_DP32(u, MVFR1, SIMDFMAC, 0); 1088 cpu->isar.mvfr1 = u; 1089 1090 u = cpu->isar.mvfr2; 1091 u = FIELD_DP32(u, MVFR2, SIMDMISC, 0); 1092 cpu->isar.mvfr2 = u; 1093 } 1094 1095 if (!cpu->has_neon && !cpu->has_vfp) { 1096 uint64_t t; 1097 uint32_t u; 1098 1099 t = cpu->isar.id_aa64isar0; 1100 t = FIELD_DP64(t, ID_AA64ISAR0, FHM, 0); 1101 cpu->isar.id_aa64isar0 = t; 1102 1103 t = cpu->isar.id_aa64isar1; 1104 t = FIELD_DP64(t, ID_AA64ISAR1, FRINTTS, 0); 1105 cpu->isar.id_aa64isar1 = t; 1106 1107 u = cpu->isar.mvfr0; 1108 u = FIELD_DP32(u, MVFR0, SIMDREG, 0); 1109 cpu->isar.mvfr0 = u; 1110 } 1111 1112 if (arm_feature(env, ARM_FEATURE_M) && !cpu->has_dsp) { 1113 uint32_t u; 1114 1115 unset_feature(env, ARM_FEATURE_THUMB_DSP); 1116 1117 u = cpu->isar.id_isar1; 1118 u = FIELD_DP32(u, ID_ISAR1, EXTEND, 1); 1119 cpu->isar.id_isar1 = u; 1120 1121 u = cpu->isar.id_isar2; 1122 u = FIELD_DP32(u, ID_ISAR2, MULTU, 1); 1123 u = FIELD_DP32(u, ID_ISAR2, MULTS, 1); 1124 cpu->isar.id_isar2 = u; 1125 1126 u = cpu->isar.id_isar3; 1127 u = FIELD_DP32(u, ID_ISAR3, SIMD, 1); 1128 u = FIELD_DP32(u, ID_ISAR3, SATURATE, 0); 1129 cpu->isar.id_isar3 = u; 1130 } 1131 1132 /* Some features automatically imply others: */ 1133 if (arm_feature(env, ARM_FEATURE_V8)) { 1134 if (arm_feature(env, ARM_FEATURE_M)) { 1135 set_feature(env, ARM_FEATURE_V7); 1136 } else { 1137 set_feature(env, ARM_FEATURE_V7VE); 1138 } 1139 } 1140 1141 /* 1142 * There exist AArch64 cpus without AArch32 support. When KVM 1143 * queries ID_ISAR0_EL1 on such a host, the value is UNKNOWN. 1144 * Similarly, we cannot check ID_AA64PFR0 without AArch64 support. 1145 */ 1146 if (arm_feature(&cpu->env, ARM_FEATURE_AARCH64)) { 1147 no_aa32 = !cpu_isar_feature(aa64_aa32, cpu); 1148 } 1149 1150 if (arm_feature(env, ARM_FEATURE_V7VE)) { 1151 /* v7 Virtualization Extensions. In real hardware this implies 1152 * EL2 and also the presence of the Security Extensions. 1153 * For QEMU, for backwards-compatibility we implement some 1154 * CPUs or CPU configs which have no actual EL2 or EL3 but do 1155 * include the various other features that V7VE implies. 1156 * Presence of EL2 itself is ARM_FEATURE_EL2, and of the 1157 * Security Extensions is ARM_FEATURE_EL3. 1158 */ 1159 assert(no_aa32 || cpu_isar_feature(arm_div, cpu)); 1160 set_feature(env, ARM_FEATURE_LPAE); 1161 set_feature(env, ARM_FEATURE_V7); 1162 } 1163 if (arm_feature(env, ARM_FEATURE_V7)) { 1164 set_feature(env, ARM_FEATURE_VAPA); 1165 set_feature(env, ARM_FEATURE_THUMB2); 1166 set_feature(env, ARM_FEATURE_MPIDR); 1167 if (!arm_feature(env, ARM_FEATURE_M)) { 1168 set_feature(env, ARM_FEATURE_V6K); 1169 } else { 1170 set_feature(env, ARM_FEATURE_V6); 1171 } 1172 1173 /* Always define VBAR for V7 CPUs even if it doesn't exist in 1174 * non-EL3 configs. This is needed by some legacy boards. 1175 */ 1176 set_feature(env, ARM_FEATURE_VBAR); 1177 } 1178 if (arm_feature(env, ARM_FEATURE_V6K)) { 1179 set_feature(env, ARM_FEATURE_V6); 1180 set_feature(env, ARM_FEATURE_MVFR); 1181 } 1182 if (arm_feature(env, ARM_FEATURE_V6)) { 1183 set_feature(env, ARM_FEATURE_V5); 1184 if (!arm_feature(env, ARM_FEATURE_M)) { 1185 assert(no_aa32 || cpu_isar_feature(jazelle, cpu)); 1186 set_feature(env, ARM_FEATURE_AUXCR); 1187 } 1188 } 1189 if (arm_feature(env, ARM_FEATURE_V5)) { 1190 set_feature(env, ARM_FEATURE_V4T); 1191 } 1192 if (arm_feature(env, ARM_FEATURE_LPAE)) { 1193 set_feature(env, ARM_FEATURE_V7MP); 1194 set_feature(env, ARM_FEATURE_PXN); 1195 } 1196 if (arm_feature(env, ARM_FEATURE_CBAR_RO)) { 1197 set_feature(env, ARM_FEATURE_CBAR); 1198 } 1199 if (arm_feature(env, ARM_FEATURE_THUMB2) && 1200 !arm_feature(env, ARM_FEATURE_M)) { 1201 set_feature(env, ARM_FEATURE_THUMB_DSP); 1202 } 1203 1204 /* 1205 * We rely on no XScale CPU having VFP so we can use the same bits in the 1206 * TB flags field for VECSTRIDE and XSCALE_CPAR. 1207 */ 1208 assert(!(arm_feature(env, ARM_FEATURE_VFP) && 1209 arm_feature(env, ARM_FEATURE_XSCALE))); 1210 1211 if (arm_feature(env, ARM_FEATURE_V7) && 1212 !arm_feature(env, ARM_FEATURE_M) && 1213 !arm_feature(env, ARM_FEATURE_PMSA)) { 1214 /* v7VMSA drops support for the old ARMv5 tiny pages, so we 1215 * can use 4K pages. 1216 */ 1217 pagebits = 12; 1218 } else { 1219 /* For CPUs which might have tiny 1K pages, or which have an 1220 * MPU and might have small region sizes, stick with 1K pages. 1221 */ 1222 pagebits = 10; 1223 } 1224 if (!set_preferred_target_page_bits(pagebits)) { 1225 /* This can only ever happen for hotplugging a CPU, or if 1226 * the board code incorrectly creates a CPU which it has 1227 * promised via minimum_page_size that it will not. 1228 */ 1229 error_setg(errp, "This CPU requires a smaller page size than the " 1230 "system is using"); 1231 return; 1232 } 1233 1234 /* This cpu-id-to-MPIDR affinity is used only for TCG; KVM will override it. 1235 * We don't support setting cluster ID ([16..23]) (known as Aff2 1236 * in later ARM ARM versions), or any of the higher affinity level fields, 1237 * so these bits always RAZ. 1238 */ 1239 if (cpu->mp_affinity == ARM64_AFFINITY_INVALID) { 1240 cpu->mp_affinity = arm_cpu_mp_affinity(cs->cpu_index, 1241 ARM_DEFAULT_CPUS_PER_CLUSTER); 1242 } 1243 1244 if (cpu->reset_hivecs) { 1245 cpu->reset_sctlr |= (1 << 13); 1246 } 1247 1248 if (cpu->cfgend) { 1249 if (arm_feature(&cpu->env, ARM_FEATURE_V7)) { 1250 cpu->reset_sctlr |= SCTLR_EE; 1251 } else { 1252 cpu->reset_sctlr |= SCTLR_B; 1253 } 1254 } 1255 1256 if (!cpu->has_el3) { 1257 /* If the has_el3 CPU property is disabled then we need to disable the 1258 * feature. 1259 */ 1260 unset_feature(env, ARM_FEATURE_EL3); 1261 1262 /* Disable the security extension feature bits in the processor feature 1263 * registers as well. These are id_pfr1[7:4] and id_aa64pfr0[15:12]. 1264 */ 1265 cpu->id_pfr1 &= ~0xf0; 1266 cpu->isar.id_aa64pfr0 &= ~0xf000; 1267 } 1268 1269 if (!cpu->has_el2) { 1270 unset_feature(env, ARM_FEATURE_EL2); 1271 } 1272 1273 if (!cpu->has_pmu) { 1274 unset_feature(env, ARM_FEATURE_PMU); 1275 } 1276 if (arm_feature(env, ARM_FEATURE_PMU)) { 1277 pmu_init(cpu); 1278 1279 if (!kvm_enabled()) { 1280 arm_register_pre_el_change_hook(cpu, &pmu_pre_el_change, 0); 1281 arm_register_el_change_hook(cpu, &pmu_post_el_change, 0); 1282 } 1283 1284 #ifndef CONFIG_USER_ONLY 1285 cpu->pmu_timer = timer_new_ns(QEMU_CLOCK_VIRTUAL, arm_pmu_timer_cb, 1286 cpu); 1287 #endif 1288 } else { 1289 cpu->id_aa64dfr0 &= ~0xf00; 1290 cpu->id_dfr0 &= ~(0xf << 24); 1291 cpu->pmceid0 = 0; 1292 cpu->pmceid1 = 0; 1293 } 1294 1295 if (!arm_feature(env, ARM_FEATURE_EL2)) { 1296 /* Disable the hypervisor feature bits in the processor feature 1297 * registers if we don't have EL2. These are id_pfr1[15:12] and 1298 * id_aa64pfr0_el1[11:8]. 1299 */ 1300 cpu->isar.id_aa64pfr0 &= ~0xf00; 1301 cpu->id_pfr1 &= ~0xf000; 1302 } 1303 1304 /* MPU can be configured out of a PMSA CPU either by setting has-mpu 1305 * to false or by setting pmsav7-dregion to 0. 1306 */ 1307 if (!cpu->has_mpu) { 1308 cpu->pmsav7_dregion = 0; 1309 } 1310 if (cpu->pmsav7_dregion == 0) { 1311 cpu->has_mpu = false; 1312 } 1313 1314 if (arm_feature(env, ARM_FEATURE_PMSA) && 1315 arm_feature(env, ARM_FEATURE_V7)) { 1316 uint32_t nr = cpu->pmsav7_dregion; 1317 1318 if (nr > 0xff) { 1319 error_setg(errp, "PMSAv7 MPU #regions invalid %" PRIu32, nr); 1320 return; 1321 } 1322 1323 if (nr) { 1324 if (arm_feature(env, ARM_FEATURE_V8)) { 1325 /* PMSAv8 */ 1326 env->pmsav8.rbar[M_REG_NS] = g_new0(uint32_t, nr); 1327 env->pmsav8.rlar[M_REG_NS] = g_new0(uint32_t, nr); 1328 if (arm_feature(env, ARM_FEATURE_M_SECURITY)) { 1329 env->pmsav8.rbar[M_REG_S] = g_new0(uint32_t, nr); 1330 env->pmsav8.rlar[M_REG_S] = g_new0(uint32_t, nr); 1331 } 1332 } else { 1333 env->pmsav7.drbar = g_new0(uint32_t, nr); 1334 env->pmsav7.drsr = g_new0(uint32_t, nr); 1335 env->pmsav7.dracr = g_new0(uint32_t, nr); 1336 } 1337 } 1338 } 1339 1340 if (arm_feature(env, ARM_FEATURE_M_SECURITY)) { 1341 uint32_t nr = cpu->sau_sregion; 1342 1343 if (nr > 0xff) { 1344 error_setg(errp, "v8M SAU #regions invalid %" PRIu32, nr); 1345 return; 1346 } 1347 1348 if (nr) { 1349 env->sau.rbar = g_new0(uint32_t, nr); 1350 env->sau.rlar = g_new0(uint32_t, nr); 1351 } 1352 } 1353 1354 if (arm_feature(env, ARM_FEATURE_EL3)) { 1355 set_feature(env, ARM_FEATURE_VBAR); 1356 } 1357 1358 register_cp_regs_for_features(cpu); 1359 arm_cpu_register_gdb_regs_for_features(cpu); 1360 1361 init_cpreg_list(cpu); 1362 1363 #ifndef CONFIG_USER_ONLY 1364 if (cpu->has_el3 || arm_feature(env, ARM_FEATURE_M_SECURITY)) { 1365 cs->num_ases = 2; 1366 1367 if (!cpu->secure_memory) { 1368 cpu->secure_memory = cs->memory; 1369 } 1370 cpu_address_space_init(cs, ARMASIdx_S, "cpu-secure-memory", 1371 cpu->secure_memory); 1372 } else { 1373 cs->num_ases = 1; 1374 } 1375 cpu_address_space_init(cs, ARMASIdx_NS, "cpu-memory", cs->memory); 1376 1377 /* No core_count specified, default to smp_cpus. */ 1378 if (cpu->core_count == -1) { 1379 cpu->core_count = smp_cpus; 1380 } 1381 #endif 1382 1383 qemu_init_vcpu(cs); 1384 cpu_reset(cs); 1385 1386 acc->parent_realize(dev, errp); 1387 } 1388 1389 static ObjectClass *arm_cpu_class_by_name(const char *cpu_model) 1390 { 1391 ObjectClass *oc; 1392 char *typename; 1393 char **cpuname; 1394 const char *cpunamestr; 1395 1396 cpuname = g_strsplit(cpu_model, ",", 1); 1397 cpunamestr = cpuname[0]; 1398 #ifdef CONFIG_USER_ONLY 1399 /* For backwards compatibility usermode emulation allows "-cpu any", 1400 * which has the same semantics as "-cpu max". 1401 */ 1402 if (!strcmp(cpunamestr, "any")) { 1403 cpunamestr = "max"; 1404 } 1405 #endif 1406 typename = g_strdup_printf(ARM_CPU_TYPE_NAME("%s"), cpunamestr); 1407 oc = object_class_by_name(typename); 1408 g_strfreev(cpuname); 1409 g_free(typename); 1410 if (!oc || !object_class_dynamic_cast(oc, TYPE_ARM_CPU) || 1411 object_class_is_abstract(oc)) { 1412 return NULL; 1413 } 1414 return oc; 1415 } 1416 1417 /* CPU models. These are not needed for the AArch64 linux-user build. */ 1418 #if !defined(CONFIG_USER_ONLY) || !defined(TARGET_AARCH64) 1419 1420 static void arm926_initfn(Object *obj) 1421 { 1422 ARMCPU *cpu = ARM_CPU(obj); 1423 1424 cpu->dtb_compatible = "arm,arm926"; 1425 set_feature(&cpu->env, ARM_FEATURE_V5); 1426 set_feature(&cpu->env, ARM_FEATURE_VFP); 1427 set_feature(&cpu->env, ARM_FEATURE_DUMMY_C15_REGS); 1428 set_feature(&cpu->env, ARM_FEATURE_CACHE_TEST_CLEAN); 1429 cpu->midr = 0x41069265; 1430 cpu->reset_fpsid = 0x41011090; 1431 cpu->ctr = 0x1dd20d2; 1432 cpu->reset_sctlr = 0x00090078; 1433 1434 /* 1435 * ARMv5 does not have the ID_ISAR registers, but we can still 1436 * set the field to indicate Jazelle support within QEMU. 1437 */ 1438 cpu->isar.id_isar1 = FIELD_DP32(cpu->isar.id_isar1, ID_ISAR1, JAZELLE, 1); 1439 } 1440 1441 static void arm946_initfn(Object *obj) 1442 { 1443 ARMCPU *cpu = ARM_CPU(obj); 1444 1445 cpu->dtb_compatible = "arm,arm946"; 1446 set_feature(&cpu->env, ARM_FEATURE_V5); 1447 set_feature(&cpu->env, ARM_FEATURE_PMSA); 1448 set_feature(&cpu->env, ARM_FEATURE_DUMMY_C15_REGS); 1449 cpu->midr = 0x41059461; 1450 cpu->ctr = 0x0f004006; 1451 cpu->reset_sctlr = 0x00000078; 1452 } 1453 1454 static void arm1026_initfn(Object *obj) 1455 { 1456 ARMCPU *cpu = ARM_CPU(obj); 1457 1458 cpu->dtb_compatible = "arm,arm1026"; 1459 set_feature(&cpu->env, ARM_FEATURE_V5); 1460 set_feature(&cpu->env, ARM_FEATURE_VFP); 1461 set_feature(&cpu->env, ARM_FEATURE_AUXCR); 1462 set_feature(&cpu->env, ARM_FEATURE_DUMMY_C15_REGS); 1463 set_feature(&cpu->env, ARM_FEATURE_CACHE_TEST_CLEAN); 1464 cpu->midr = 0x4106a262; 1465 cpu->reset_fpsid = 0x410110a0; 1466 cpu->ctr = 0x1dd20d2; 1467 cpu->reset_sctlr = 0x00090078; 1468 cpu->reset_auxcr = 1; 1469 1470 /* 1471 * ARMv5 does not have the ID_ISAR registers, but we can still 1472 * set the field to indicate Jazelle support within QEMU. 1473 */ 1474 cpu->isar.id_isar1 = FIELD_DP32(cpu->isar.id_isar1, ID_ISAR1, JAZELLE, 1); 1475 1476 { 1477 /* The 1026 had an IFAR at c6,c0,0,1 rather than the ARMv6 c6,c0,0,2 */ 1478 ARMCPRegInfo ifar = { 1479 .name = "IFAR", .cp = 15, .crn = 6, .crm = 0, .opc1 = 0, .opc2 = 1, 1480 .access = PL1_RW, 1481 .fieldoffset = offsetof(CPUARMState, cp15.ifar_ns), 1482 .resetvalue = 0 1483 }; 1484 define_one_arm_cp_reg(cpu, &ifar); 1485 } 1486 } 1487 1488 static void arm1136_r2_initfn(Object *obj) 1489 { 1490 ARMCPU *cpu = ARM_CPU(obj); 1491 /* What qemu calls "arm1136_r2" is actually the 1136 r0p2, ie an 1492 * older core than plain "arm1136". In particular this does not 1493 * have the v6K features. 1494 * These ID register values are correct for 1136 but may be wrong 1495 * for 1136_r2 (in particular r0p2 does not actually implement most 1496 * of the ID registers). 1497 */ 1498 1499 cpu->dtb_compatible = "arm,arm1136"; 1500 set_feature(&cpu->env, ARM_FEATURE_V6); 1501 set_feature(&cpu->env, ARM_FEATURE_VFP); 1502 set_feature(&cpu->env, ARM_FEATURE_DUMMY_C15_REGS); 1503 set_feature(&cpu->env, ARM_FEATURE_CACHE_DIRTY_REG); 1504 set_feature(&cpu->env, ARM_FEATURE_CACHE_BLOCK_OPS); 1505 cpu->midr = 0x4107b362; 1506 cpu->reset_fpsid = 0x410120b4; 1507 cpu->isar.mvfr0 = 0x11111111; 1508 cpu->isar.mvfr1 = 0x00000000; 1509 cpu->ctr = 0x1dd20d2; 1510 cpu->reset_sctlr = 0x00050078; 1511 cpu->id_pfr0 = 0x111; 1512 cpu->id_pfr1 = 0x1; 1513 cpu->id_dfr0 = 0x2; 1514 cpu->id_afr0 = 0x3; 1515 cpu->id_mmfr0 = 0x01130003; 1516 cpu->id_mmfr1 = 0x10030302; 1517 cpu->id_mmfr2 = 0x01222110; 1518 cpu->isar.id_isar0 = 0x00140011; 1519 cpu->isar.id_isar1 = 0x12002111; 1520 cpu->isar.id_isar2 = 0x11231111; 1521 cpu->isar.id_isar3 = 0x01102131; 1522 cpu->isar.id_isar4 = 0x141; 1523 cpu->reset_auxcr = 7; 1524 } 1525 1526 static void arm1136_initfn(Object *obj) 1527 { 1528 ARMCPU *cpu = ARM_CPU(obj); 1529 1530 cpu->dtb_compatible = "arm,arm1136"; 1531 set_feature(&cpu->env, ARM_FEATURE_V6K); 1532 set_feature(&cpu->env, ARM_FEATURE_V6); 1533 set_feature(&cpu->env, ARM_FEATURE_VFP); 1534 set_feature(&cpu->env, ARM_FEATURE_DUMMY_C15_REGS); 1535 set_feature(&cpu->env, ARM_FEATURE_CACHE_DIRTY_REG); 1536 set_feature(&cpu->env, ARM_FEATURE_CACHE_BLOCK_OPS); 1537 cpu->midr = 0x4117b363; 1538 cpu->reset_fpsid = 0x410120b4; 1539 cpu->isar.mvfr0 = 0x11111111; 1540 cpu->isar.mvfr1 = 0x00000000; 1541 cpu->ctr = 0x1dd20d2; 1542 cpu->reset_sctlr = 0x00050078; 1543 cpu->id_pfr0 = 0x111; 1544 cpu->id_pfr1 = 0x1; 1545 cpu->id_dfr0 = 0x2; 1546 cpu->id_afr0 = 0x3; 1547 cpu->id_mmfr0 = 0x01130003; 1548 cpu->id_mmfr1 = 0x10030302; 1549 cpu->id_mmfr2 = 0x01222110; 1550 cpu->isar.id_isar0 = 0x00140011; 1551 cpu->isar.id_isar1 = 0x12002111; 1552 cpu->isar.id_isar2 = 0x11231111; 1553 cpu->isar.id_isar3 = 0x01102131; 1554 cpu->isar.id_isar4 = 0x141; 1555 cpu->reset_auxcr = 7; 1556 } 1557 1558 static void arm1176_initfn(Object *obj) 1559 { 1560 ARMCPU *cpu = ARM_CPU(obj); 1561 1562 cpu->dtb_compatible = "arm,arm1176"; 1563 set_feature(&cpu->env, ARM_FEATURE_V6K); 1564 set_feature(&cpu->env, ARM_FEATURE_VFP); 1565 set_feature(&cpu->env, ARM_FEATURE_VAPA); 1566 set_feature(&cpu->env, ARM_FEATURE_DUMMY_C15_REGS); 1567 set_feature(&cpu->env, ARM_FEATURE_CACHE_DIRTY_REG); 1568 set_feature(&cpu->env, ARM_FEATURE_CACHE_BLOCK_OPS); 1569 set_feature(&cpu->env, ARM_FEATURE_EL3); 1570 cpu->midr = 0x410fb767; 1571 cpu->reset_fpsid = 0x410120b5; 1572 cpu->isar.mvfr0 = 0x11111111; 1573 cpu->isar.mvfr1 = 0x00000000; 1574 cpu->ctr = 0x1dd20d2; 1575 cpu->reset_sctlr = 0x00050078; 1576 cpu->id_pfr0 = 0x111; 1577 cpu->id_pfr1 = 0x11; 1578 cpu->id_dfr0 = 0x33; 1579 cpu->id_afr0 = 0; 1580 cpu->id_mmfr0 = 0x01130003; 1581 cpu->id_mmfr1 = 0x10030302; 1582 cpu->id_mmfr2 = 0x01222100; 1583 cpu->isar.id_isar0 = 0x0140011; 1584 cpu->isar.id_isar1 = 0x12002111; 1585 cpu->isar.id_isar2 = 0x11231121; 1586 cpu->isar.id_isar3 = 0x01102131; 1587 cpu->isar.id_isar4 = 0x01141; 1588 cpu->reset_auxcr = 7; 1589 } 1590 1591 static void arm11mpcore_initfn(Object *obj) 1592 { 1593 ARMCPU *cpu = ARM_CPU(obj); 1594 1595 cpu->dtb_compatible = "arm,arm11mpcore"; 1596 set_feature(&cpu->env, ARM_FEATURE_V6K); 1597 set_feature(&cpu->env, ARM_FEATURE_VFP); 1598 set_feature(&cpu->env, ARM_FEATURE_VAPA); 1599 set_feature(&cpu->env, ARM_FEATURE_MPIDR); 1600 set_feature(&cpu->env, ARM_FEATURE_DUMMY_C15_REGS); 1601 cpu->midr = 0x410fb022; 1602 cpu->reset_fpsid = 0x410120b4; 1603 cpu->isar.mvfr0 = 0x11111111; 1604 cpu->isar.mvfr1 = 0x00000000; 1605 cpu->ctr = 0x1d192992; /* 32K icache 32K dcache */ 1606 cpu->id_pfr0 = 0x111; 1607 cpu->id_pfr1 = 0x1; 1608 cpu->id_dfr0 = 0; 1609 cpu->id_afr0 = 0x2; 1610 cpu->id_mmfr0 = 0x01100103; 1611 cpu->id_mmfr1 = 0x10020302; 1612 cpu->id_mmfr2 = 0x01222000; 1613 cpu->isar.id_isar0 = 0x00100011; 1614 cpu->isar.id_isar1 = 0x12002111; 1615 cpu->isar.id_isar2 = 0x11221011; 1616 cpu->isar.id_isar3 = 0x01102131; 1617 cpu->isar.id_isar4 = 0x141; 1618 cpu->reset_auxcr = 1; 1619 } 1620 1621 static void cortex_m0_initfn(Object *obj) 1622 { 1623 ARMCPU *cpu = ARM_CPU(obj); 1624 set_feature(&cpu->env, ARM_FEATURE_V6); 1625 set_feature(&cpu->env, ARM_FEATURE_M); 1626 1627 cpu->midr = 0x410cc200; 1628 } 1629 1630 static void cortex_m3_initfn(Object *obj) 1631 { 1632 ARMCPU *cpu = ARM_CPU(obj); 1633 set_feature(&cpu->env, ARM_FEATURE_V7); 1634 set_feature(&cpu->env, ARM_FEATURE_M); 1635 set_feature(&cpu->env, ARM_FEATURE_M_MAIN); 1636 cpu->midr = 0x410fc231; 1637 cpu->pmsav7_dregion = 8; 1638 cpu->id_pfr0 = 0x00000030; 1639 cpu->id_pfr1 = 0x00000200; 1640 cpu->id_dfr0 = 0x00100000; 1641 cpu->id_afr0 = 0x00000000; 1642 cpu->id_mmfr0 = 0x00000030; 1643 cpu->id_mmfr1 = 0x00000000; 1644 cpu->id_mmfr2 = 0x00000000; 1645 cpu->id_mmfr3 = 0x00000000; 1646 cpu->isar.id_isar0 = 0x01141110; 1647 cpu->isar.id_isar1 = 0x02111000; 1648 cpu->isar.id_isar2 = 0x21112231; 1649 cpu->isar.id_isar3 = 0x01111110; 1650 cpu->isar.id_isar4 = 0x01310102; 1651 cpu->isar.id_isar5 = 0x00000000; 1652 cpu->isar.id_isar6 = 0x00000000; 1653 } 1654 1655 static void cortex_m4_initfn(Object *obj) 1656 { 1657 ARMCPU *cpu = ARM_CPU(obj); 1658 1659 set_feature(&cpu->env, ARM_FEATURE_V7); 1660 set_feature(&cpu->env, ARM_FEATURE_M); 1661 set_feature(&cpu->env, ARM_FEATURE_M_MAIN); 1662 set_feature(&cpu->env, ARM_FEATURE_THUMB_DSP); 1663 set_feature(&cpu->env, ARM_FEATURE_VFP4); 1664 cpu->midr = 0x410fc240; /* r0p0 */ 1665 cpu->pmsav7_dregion = 8; 1666 cpu->isar.mvfr0 = 0x10110021; 1667 cpu->isar.mvfr1 = 0x11000011; 1668 cpu->isar.mvfr2 = 0x00000000; 1669 cpu->id_pfr0 = 0x00000030; 1670 cpu->id_pfr1 = 0x00000200; 1671 cpu->id_dfr0 = 0x00100000; 1672 cpu->id_afr0 = 0x00000000; 1673 cpu->id_mmfr0 = 0x00000030; 1674 cpu->id_mmfr1 = 0x00000000; 1675 cpu->id_mmfr2 = 0x00000000; 1676 cpu->id_mmfr3 = 0x00000000; 1677 cpu->isar.id_isar0 = 0x01141110; 1678 cpu->isar.id_isar1 = 0x02111000; 1679 cpu->isar.id_isar2 = 0x21112231; 1680 cpu->isar.id_isar3 = 0x01111110; 1681 cpu->isar.id_isar4 = 0x01310102; 1682 cpu->isar.id_isar5 = 0x00000000; 1683 cpu->isar.id_isar6 = 0x00000000; 1684 } 1685 1686 static void cortex_m33_initfn(Object *obj) 1687 { 1688 ARMCPU *cpu = ARM_CPU(obj); 1689 1690 set_feature(&cpu->env, ARM_FEATURE_V8); 1691 set_feature(&cpu->env, ARM_FEATURE_M); 1692 set_feature(&cpu->env, ARM_FEATURE_M_MAIN); 1693 set_feature(&cpu->env, ARM_FEATURE_M_SECURITY); 1694 set_feature(&cpu->env, ARM_FEATURE_THUMB_DSP); 1695 set_feature(&cpu->env, ARM_FEATURE_VFP4); 1696 cpu->midr = 0x410fd213; /* r0p3 */ 1697 cpu->pmsav7_dregion = 16; 1698 cpu->sau_sregion = 8; 1699 cpu->isar.mvfr0 = 0x10110021; 1700 cpu->isar.mvfr1 = 0x11000011; 1701 cpu->isar.mvfr2 = 0x00000040; 1702 cpu->id_pfr0 = 0x00000030; 1703 cpu->id_pfr1 = 0x00000210; 1704 cpu->id_dfr0 = 0x00200000; 1705 cpu->id_afr0 = 0x00000000; 1706 cpu->id_mmfr0 = 0x00101F40; 1707 cpu->id_mmfr1 = 0x00000000; 1708 cpu->id_mmfr2 = 0x01000000; 1709 cpu->id_mmfr3 = 0x00000000; 1710 cpu->isar.id_isar0 = 0x01101110; 1711 cpu->isar.id_isar1 = 0x02212000; 1712 cpu->isar.id_isar2 = 0x20232232; 1713 cpu->isar.id_isar3 = 0x01111131; 1714 cpu->isar.id_isar4 = 0x01310132; 1715 cpu->isar.id_isar5 = 0x00000000; 1716 cpu->isar.id_isar6 = 0x00000000; 1717 cpu->clidr = 0x00000000; 1718 cpu->ctr = 0x8000c000; 1719 } 1720 1721 static void arm_v7m_class_init(ObjectClass *oc, void *data) 1722 { 1723 ARMCPUClass *acc = ARM_CPU_CLASS(oc); 1724 CPUClass *cc = CPU_CLASS(oc); 1725 1726 acc->info = data; 1727 #ifndef CONFIG_USER_ONLY 1728 cc->do_interrupt = arm_v7m_cpu_do_interrupt; 1729 #endif 1730 1731 cc->cpu_exec_interrupt = arm_v7m_cpu_exec_interrupt; 1732 } 1733 1734 static const ARMCPRegInfo cortexr5_cp_reginfo[] = { 1735 /* Dummy the TCM region regs for the moment */ 1736 { .name = "ATCM", .cp = 15, .opc1 = 0, .crn = 9, .crm = 1, .opc2 = 0, 1737 .access = PL1_RW, .type = ARM_CP_CONST }, 1738 { .name = "BTCM", .cp = 15, .opc1 = 0, .crn = 9, .crm = 1, .opc2 = 1, 1739 .access = PL1_RW, .type = ARM_CP_CONST }, 1740 { .name = "DCACHE_INVAL", .cp = 15, .opc1 = 0, .crn = 15, .crm = 5, 1741 .opc2 = 0, .access = PL1_W, .type = ARM_CP_NOP }, 1742 REGINFO_SENTINEL 1743 }; 1744 1745 static void cortex_r5_initfn(Object *obj) 1746 { 1747 ARMCPU *cpu = ARM_CPU(obj); 1748 1749 set_feature(&cpu->env, ARM_FEATURE_V7); 1750 set_feature(&cpu->env, ARM_FEATURE_V7MP); 1751 set_feature(&cpu->env, ARM_FEATURE_PMSA); 1752 cpu->midr = 0x411fc153; /* r1p3 */ 1753 cpu->id_pfr0 = 0x0131; 1754 cpu->id_pfr1 = 0x001; 1755 cpu->id_dfr0 = 0x010400; 1756 cpu->id_afr0 = 0x0; 1757 cpu->id_mmfr0 = 0x0210030; 1758 cpu->id_mmfr1 = 0x00000000; 1759 cpu->id_mmfr2 = 0x01200000; 1760 cpu->id_mmfr3 = 0x0211; 1761 cpu->isar.id_isar0 = 0x02101111; 1762 cpu->isar.id_isar1 = 0x13112111; 1763 cpu->isar.id_isar2 = 0x21232141; 1764 cpu->isar.id_isar3 = 0x01112131; 1765 cpu->isar.id_isar4 = 0x0010142; 1766 cpu->isar.id_isar5 = 0x0; 1767 cpu->isar.id_isar6 = 0x0; 1768 cpu->mp_is_up = true; 1769 cpu->pmsav7_dregion = 16; 1770 define_arm_cp_regs(cpu, cortexr5_cp_reginfo); 1771 } 1772 1773 static void cortex_r5f_initfn(Object *obj) 1774 { 1775 ARMCPU *cpu = ARM_CPU(obj); 1776 1777 cortex_r5_initfn(obj); 1778 set_feature(&cpu->env, ARM_FEATURE_VFP3); 1779 cpu->isar.mvfr0 = 0x10110221; 1780 cpu->isar.mvfr1 = 0x00000011; 1781 } 1782 1783 static const ARMCPRegInfo cortexa8_cp_reginfo[] = { 1784 { .name = "L2LOCKDOWN", .cp = 15, .crn = 9, .crm = 0, .opc1 = 1, .opc2 = 0, 1785 .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0 }, 1786 { .name = "L2AUXCR", .cp = 15, .crn = 9, .crm = 0, .opc1 = 1, .opc2 = 2, 1787 .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0 }, 1788 REGINFO_SENTINEL 1789 }; 1790 1791 static void cortex_a8_initfn(Object *obj) 1792 { 1793 ARMCPU *cpu = ARM_CPU(obj); 1794 1795 cpu->dtb_compatible = "arm,cortex-a8"; 1796 set_feature(&cpu->env, ARM_FEATURE_V7); 1797 set_feature(&cpu->env, ARM_FEATURE_VFP3); 1798 set_feature(&cpu->env, ARM_FEATURE_NEON); 1799 set_feature(&cpu->env, ARM_FEATURE_THUMB2EE); 1800 set_feature(&cpu->env, ARM_FEATURE_DUMMY_C15_REGS); 1801 set_feature(&cpu->env, ARM_FEATURE_EL3); 1802 cpu->midr = 0x410fc080; 1803 cpu->reset_fpsid = 0x410330c0; 1804 cpu->isar.mvfr0 = 0x11110222; 1805 cpu->isar.mvfr1 = 0x00011111; 1806 cpu->ctr = 0x82048004; 1807 cpu->reset_sctlr = 0x00c50078; 1808 cpu->id_pfr0 = 0x1031; 1809 cpu->id_pfr1 = 0x11; 1810 cpu->id_dfr0 = 0x400; 1811 cpu->id_afr0 = 0; 1812 cpu->id_mmfr0 = 0x31100003; 1813 cpu->id_mmfr1 = 0x20000000; 1814 cpu->id_mmfr2 = 0x01202000; 1815 cpu->id_mmfr3 = 0x11; 1816 cpu->isar.id_isar0 = 0x00101111; 1817 cpu->isar.id_isar1 = 0x12112111; 1818 cpu->isar.id_isar2 = 0x21232031; 1819 cpu->isar.id_isar3 = 0x11112131; 1820 cpu->isar.id_isar4 = 0x00111142; 1821 cpu->dbgdidr = 0x15141000; 1822 cpu->clidr = (1 << 27) | (2 << 24) | 3; 1823 cpu->ccsidr[0] = 0xe007e01a; /* 16k L1 dcache. */ 1824 cpu->ccsidr[1] = 0x2007e01a; /* 16k L1 icache. */ 1825 cpu->ccsidr[2] = 0xf0000000; /* No L2 icache. */ 1826 cpu->reset_auxcr = 2; 1827 define_arm_cp_regs(cpu, cortexa8_cp_reginfo); 1828 } 1829 1830 static const ARMCPRegInfo cortexa9_cp_reginfo[] = { 1831 /* power_control should be set to maximum latency. Again, 1832 * default to 0 and set by private hook 1833 */ 1834 { .name = "A9_PWRCTL", .cp = 15, .crn = 15, .crm = 0, .opc1 = 0, .opc2 = 0, 1835 .access = PL1_RW, .resetvalue = 0, 1836 .fieldoffset = offsetof(CPUARMState, cp15.c15_power_control) }, 1837 { .name = "A9_DIAG", .cp = 15, .crn = 15, .crm = 0, .opc1 = 0, .opc2 = 1, 1838 .access = PL1_RW, .resetvalue = 0, 1839 .fieldoffset = offsetof(CPUARMState, cp15.c15_diagnostic) }, 1840 { .name = "A9_PWRDIAG", .cp = 15, .crn = 15, .crm = 0, .opc1 = 0, .opc2 = 2, 1841 .access = PL1_RW, .resetvalue = 0, 1842 .fieldoffset = offsetof(CPUARMState, cp15.c15_power_diagnostic) }, 1843 { .name = "NEONBUSY", .cp = 15, .crn = 15, .crm = 1, .opc1 = 0, .opc2 = 0, 1844 .access = PL1_RW, .resetvalue = 0, .type = ARM_CP_CONST }, 1845 /* TLB lockdown control */ 1846 { .name = "TLB_LOCKR", .cp = 15, .crn = 15, .crm = 4, .opc1 = 5, .opc2 = 2, 1847 .access = PL1_W, .resetvalue = 0, .type = ARM_CP_NOP }, 1848 { .name = "TLB_LOCKW", .cp = 15, .crn = 15, .crm = 4, .opc1 = 5, .opc2 = 4, 1849 .access = PL1_W, .resetvalue = 0, .type = ARM_CP_NOP }, 1850 { .name = "TLB_VA", .cp = 15, .crn = 15, .crm = 5, .opc1 = 5, .opc2 = 2, 1851 .access = PL1_RW, .resetvalue = 0, .type = ARM_CP_CONST }, 1852 { .name = "TLB_PA", .cp = 15, .crn = 15, .crm = 6, .opc1 = 5, .opc2 = 2, 1853 .access = PL1_RW, .resetvalue = 0, .type = ARM_CP_CONST }, 1854 { .name = "TLB_ATTR", .cp = 15, .crn = 15, .crm = 7, .opc1 = 5, .opc2 = 2, 1855 .access = PL1_RW, .resetvalue = 0, .type = ARM_CP_CONST }, 1856 REGINFO_SENTINEL 1857 }; 1858 1859 static void cortex_a9_initfn(Object *obj) 1860 { 1861 ARMCPU *cpu = ARM_CPU(obj); 1862 1863 cpu->dtb_compatible = "arm,cortex-a9"; 1864 set_feature(&cpu->env, ARM_FEATURE_V7); 1865 set_feature(&cpu->env, ARM_FEATURE_VFP3); 1866 set_feature(&cpu->env, ARM_FEATURE_NEON); 1867 set_feature(&cpu->env, ARM_FEATURE_THUMB2EE); 1868 set_feature(&cpu->env, ARM_FEATURE_EL3); 1869 /* Note that A9 supports the MP extensions even for 1870 * A9UP and single-core A9MP (which are both different 1871 * and valid configurations; we don't model A9UP). 1872 */ 1873 set_feature(&cpu->env, ARM_FEATURE_V7MP); 1874 set_feature(&cpu->env, ARM_FEATURE_CBAR); 1875 cpu->midr = 0x410fc090; 1876 cpu->reset_fpsid = 0x41033090; 1877 cpu->isar.mvfr0 = 0x11110222; 1878 cpu->isar.mvfr1 = 0x01111111; 1879 cpu->ctr = 0x80038003; 1880 cpu->reset_sctlr = 0x00c50078; 1881 cpu->id_pfr0 = 0x1031; 1882 cpu->id_pfr1 = 0x11; 1883 cpu->id_dfr0 = 0x000; 1884 cpu->id_afr0 = 0; 1885 cpu->id_mmfr0 = 0x00100103; 1886 cpu->id_mmfr1 = 0x20000000; 1887 cpu->id_mmfr2 = 0x01230000; 1888 cpu->id_mmfr3 = 0x00002111; 1889 cpu->isar.id_isar0 = 0x00101111; 1890 cpu->isar.id_isar1 = 0x13112111; 1891 cpu->isar.id_isar2 = 0x21232041; 1892 cpu->isar.id_isar3 = 0x11112131; 1893 cpu->isar.id_isar4 = 0x00111142; 1894 cpu->dbgdidr = 0x35141000; 1895 cpu->clidr = (1 << 27) | (1 << 24) | 3; 1896 cpu->ccsidr[0] = 0xe00fe019; /* 16k L1 dcache. */ 1897 cpu->ccsidr[1] = 0x200fe019; /* 16k L1 icache. */ 1898 define_arm_cp_regs(cpu, cortexa9_cp_reginfo); 1899 } 1900 1901 #ifndef CONFIG_USER_ONLY 1902 static uint64_t a15_l2ctlr_read(CPUARMState *env, const ARMCPRegInfo *ri) 1903 { 1904 /* Linux wants the number of processors from here. 1905 * Might as well set the interrupt-controller bit too. 1906 */ 1907 return ((smp_cpus - 1) << 24) | (1 << 23); 1908 } 1909 #endif 1910 1911 static const ARMCPRegInfo cortexa15_cp_reginfo[] = { 1912 #ifndef CONFIG_USER_ONLY 1913 { .name = "L2CTLR", .cp = 15, .crn = 9, .crm = 0, .opc1 = 1, .opc2 = 2, 1914 .access = PL1_RW, .resetvalue = 0, .readfn = a15_l2ctlr_read, 1915 .writefn = arm_cp_write_ignore, }, 1916 #endif 1917 { .name = "L2ECTLR", .cp = 15, .crn = 9, .crm = 0, .opc1 = 1, .opc2 = 3, 1918 .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0 }, 1919 REGINFO_SENTINEL 1920 }; 1921 1922 static void cortex_a7_initfn(Object *obj) 1923 { 1924 ARMCPU *cpu = ARM_CPU(obj); 1925 1926 cpu->dtb_compatible = "arm,cortex-a7"; 1927 set_feature(&cpu->env, ARM_FEATURE_V7VE); 1928 set_feature(&cpu->env, ARM_FEATURE_VFP4); 1929 set_feature(&cpu->env, ARM_FEATURE_NEON); 1930 set_feature(&cpu->env, ARM_FEATURE_THUMB2EE); 1931 set_feature(&cpu->env, ARM_FEATURE_GENERIC_TIMER); 1932 set_feature(&cpu->env, ARM_FEATURE_DUMMY_C15_REGS); 1933 set_feature(&cpu->env, ARM_FEATURE_CBAR_RO); 1934 set_feature(&cpu->env, ARM_FEATURE_EL2); 1935 set_feature(&cpu->env, ARM_FEATURE_EL3); 1936 set_feature(&cpu->env, ARM_FEATURE_PMU); 1937 cpu->kvm_target = QEMU_KVM_ARM_TARGET_CORTEX_A7; 1938 cpu->midr = 0x410fc075; 1939 cpu->reset_fpsid = 0x41023075; 1940 cpu->isar.mvfr0 = 0x10110222; 1941 cpu->isar.mvfr1 = 0x11111111; 1942 cpu->ctr = 0x84448003; 1943 cpu->reset_sctlr = 0x00c50078; 1944 cpu->id_pfr0 = 0x00001131; 1945 cpu->id_pfr1 = 0x00011011; 1946 cpu->id_dfr0 = 0x02010555; 1947 cpu->id_afr0 = 0x00000000; 1948 cpu->id_mmfr0 = 0x10101105; 1949 cpu->id_mmfr1 = 0x40000000; 1950 cpu->id_mmfr2 = 0x01240000; 1951 cpu->id_mmfr3 = 0x02102211; 1952 /* a7_mpcore_r0p5_trm, page 4-4 gives 0x01101110; but 1953 * table 4-41 gives 0x02101110, which includes the arm div insns. 1954 */ 1955 cpu->isar.id_isar0 = 0x02101110; 1956 cpu->isar.id_isar1 = 0x13112111; 1957 cpu->isar.id_isar2 = 0x21232041; 1958 cpu->isar.id_isar3 = 0x11112131; 1959 cpu->isar.id_isar4 = 0x10011142; 1960 cpu->dbgdidr = 0x3515f005; 1961 cpu->clidr = 0x0a200023; 1962 cpu->ccsidr[0] = 0x701fe00a; /* 32K L1 dcache */ 1963 cpu->ccsidr[1] = 0x201fe00a; /* 32K L1 icache */ 1964 cpu->ccsidr[2] = 0x711fe07a; /* 4096K L2 unified cache */ 1965 define_arm_cp_regs(cpu, cortexa15_cp_reginfo); /* Same as A15 */ 1966 } 1967 1968 static void cortex_a15_initfn(Object *obj) 1969 { 1970 ARMCPU *cpu = ARM_CPU(obj); 1971 1972 cpu->dtb_compatible = "arm,cortex-a15"; 1973 set_feature(&cpu->env, ARM_FEATURE_V7VE); 1974 set_feature(&cpu->env, ARM_FEATURE_VFP4); 1975 set_feature(&cpu->env, ARM_FEATURE_NEON); 1976 set_feature(&cpu->env, ARM_FEATURE_THUMB2EE); 1977 set_feature(&cpu->env, ARM_FEATURE_GENERIC_TIMER); 1978 set_feature(&cpu->env, ARM_FEATURE_DUMMY_C15_REGS); 1979 set_feature(&cpu->env, ARM_FEATURE_CBAR_RO); 1980 set_feature(&cpu->env, ARM_FEATURE_EL2); 1981 set_feature(&cpu->env, ARM_FEATURE_EL3); 1982 set_feature(&cpu->env, ARM_FEATURE_PMU); 1983 cpu->kvm_target = QEMU_KVM_ARM_TARGET_CORTEX_A15; 1984 cpu->midr = 0x412fc0f1; 1985 cpu->reset_fpsid = 0x410430f0; 1986 cpu->isar.mvfr0 = 0x10110222; 1987 cpu->isar.mvfr1 = 0x11111111; 1988 cpu->ctr = 0x8444c004; 1989 cpu->reset_sctlr = 0x00c50078; 1990 cpu->id_pfr0 = 0x00001131; 1991 cpu->id_pfr1 = 0x00011011; 1992 cpu->id_dfr0 = 0x02010555; 1993 cpu->id_afr0 = 0x00000000; 1994 cpu->id_mmfr0 = 0x10201105; 1995 cpu->id_mmfr1 = 0x20000000; 1996 cpu->id_mmfr2 = 0x01240000; 1997 cpu->id_mmfr3 = 0x02102211; 1998 cpu->isar.id_isar0 = 0x02101110; 1999 cpu->isar.id_isar1 = 0x13112111; 2000 cpu->isar.id_isar2 = 0x21232041; 2001 cpu->isar.id_isar3 = 0x11112131; 2002 cpu->isar.id_isar4 = 0x10011142; 2003 cpu->dbgdidr = 0x3515f021; 2004 cpu->clidr = 0x0a200023; 2005 cpu->ccsidr[0] = 0x701fe00a; /* 32K L1 dcache */ 2006 cpu->ccsidr[1] = 0x201fe00a; /* 32K L1 icache */ 2007 cpu->ccsidr[2] = 0x711fe07a; /* 4096K L2 unified cache */ 2008 define_arm_cp_regs(cpu, cortexa15_cp_reginfo); 2009 } 2010 2011 static void ti925t_initfn(Object *obj) 2012 { 2013 ARMCPU *cpu = ARM_CPU(obj); 2014 set_feature(&cpu->env, ARM_FEATURE_V4T); 2015 set_feature(&cpu->env, ARM_FEATURE_OMAPCP); 2016 cpu->midr = ARM_CPUID_TI925T; 2017 cpu->ctr = 0x5109149; 2018 cpu->reset_sctlr = 0x00000070; 2019 } 2020 2021 static void sa1100_initfn(Object *obj) 2022 { 2023 ARMCPU *cpu = ARM_CPU(obj); 2024 2025 cpu->dtb_compatible = "intel,sa1100"; 2026 set_feature(&cpu->env, ARM_FEATURE_STRONGARM); 2027 set_feature(&cpu->env, ARM_FEATURE_DUMMY_C15_REGS); 2028 cpu->midr = 0x4401A11B; 2029 cpu->reset_sctlr = 0x00000070; 2030 } 2031 2032 static void sa1110_initfn(Object *obj) 2033 { 2034 ARMCPU *cpu = ARM_CPU(obj); 2035 set_feature(&cpu->env, ARM_FEATURE_STRONGARM); 2036 set_feature(&cpu->env, ARM_FEATURE_DUMMY_C15_REGS); 2037 cpu->midr = 0x6901B119; 2038 cpu->reset_sctlr = 0x00000070; 2039 } 2040 2041 static void pxa250_initfn(Object *obj) 2042 { 2043 ARMCPU *cpu = ARM_CPU(obj); 2044 2045 cpu->dtb_compatible = "marvell,xscale"; 2046 set_feature(&cpu->env, ARM_FEATURE_V5); 2047 set_feature(&cpu->env, ARM_FEATURE_XSCALE); 2048 cpu->midr = 0x69052100; 2049 cpu->ctr = 0xd172172; 2050 cpu->reset_sctlr = 0x00000078; 2051 } 2052 2053 static void pxa255_initfn(Object *obj) 2054 { 2055 ARMCPU *cpu = ARM_CPU(obj); 2056 2057 cpu->dtb_compatible = "marvell,xscale"; 2058 set_feature(&cpu->env, ARM_FEATURE_V5); 2059 set_feature(&cpu->env, ARM_FEATURE_XSCALE); 2060 cpu->midr = 0x69052d00; 2061 cpu->ctr = 0xd172172; 2062 cpu->reset_sctlr = 0x00000078; 2063 } 2064 2065 static void pxa260_initfn(Object *obj) 2066 { 2067 ARMCPU *cpu = ARM_CPU(obj); 2068 2069 cpu->dtb_compatible = "marvell,xscale"; 2070 set_feature(&cpu->env, ARM_FEATURE_V5); 2071 set_feature(&cpu->env, ARM_FEATURE_XSCALE); 2072 cpu->midr = 0x69052903; 2073 cpu->ctr = 0xd172172; 2074 cpu->reset_sctlr = 0x00000078; 2075 } 2076 2077 static void pxa261_initfn(Object *obj) 2078 { 2079 ARMCPU *cpu = ARM_CPU(obj); 2080 2081 cpu->dtb_compatible = "marvell,xscale"; 2082 set_feature(&cpu->env, ARM_FEATURE_V5); 2083 set_feature(&cpu->env, ARM_FEATURE_XSCALE); 2084 cpu->midr = 0x69052d05; 2085 cpu->ctr = 0xd172172; 2086 cpu->reset_sctlr = 0x00000078; 2087 } 2088 2089 static void pxa262_initfn(Object *obj) 2090 { 2091 ARMCPU *cpu = ARM_CPU(obj); 2092 2093 cpu->dtb_compatible = "marvell,xscale"; 2094 set_feature(&cpu->env, ARM_FEATURE_V5); 2095 set_feature(&cpu->env, ARM_FEATURE_XSCALE); 2096 cpu->midr = 0x69052d06; 2097 cpu->ctr = 0xd172172; 2098 cpu->reset_sctlr = 0x00000078; 2099 } 2100 2101 static void pxa270a0_initfn(Object *obj) 2102 { 2103 ARMCPU *cpu = ARM_CPU(obj); 2104 2105 cpu->dtb_compatible = "marvell,xscale"; 2106 set_feature(&cpu->env, ARM_FEATURE_V5); 2107 set_feature(&cpu->env, ARM_FEATURE_XSCALE); 2108 set_feature(&cpu->env, ARM_FEATURE_IWMMXT); 2109 cpu->midr = 0x69054110; 2110 cpu->ctr = 0xd172172; 2111 cpu->reset_sctlr = 0x00000078; 2112 } 2113 2114 static void pxa270a1_initfn(Object *obj) 2115 { 2116 ARMCPU *cpu = ARM_CPU(obj); 2117 2118 cpu->dtb_compatible = "marvell,xscale"; 2119 set_feature(&cpu->env, ARM_FEATURE_V5); 2120 set_feature(&cpu->env, ARM_FEATURE_XSCALE); 2121 set_feature(&cpu->env, ARM_FEATURE_IWMMXT); 2122 cpu->midr = 0x69054111; 2123 cpu->ctr = 0xd172172; 2124 cpu->reset_sctlr = 0x00000078; 2125 } 2126 2127 static void pxa270b0_initfn(Object *obj) 2128 { 2129 ARMCPU *cpu = ARM_CPU(obj); 2130 2131 cpu->dtb_compatible = "marvell,xscale"; 2132 set_feature(&cpu->env, ARM_FEATURE_V5); 2133 set_feature(&cpu->env, ARM_FEATURE_XSCALE); 2134 set_feature(&cpu->env, ARM_FEATURE_IWMMXT); 2135 cpu->midr = 0x69054112; 2136 cpu->ctr = 0xd172172; 2137 cpu->reset_sctlr = 0x00000078; 2138 } 2139 2140 static void pxa270b1_initfn(Object *obj) 2141 { 2142 ARMCPU *cpu = ARM_CPU(obj); 2143 2144 cpu->dtb_compatible = "marvell,xscale"; 2145 set_feature(&cpu->env, ARM_FEATURE_V5); 2146 set_feature(&cpu->env, ARM_FEATURE_XSCALE); 2147 set_feature(&cpu->env, ARM_FEATURE_IWMMXT); 2148 cpu->midr = 0x69054113; 2149 cpu->ctr = 0xd172172; 2150 cpu->reset_sctlr = 0x00000078; 2151 } 2152 2153 static void pxa270c0_initfn(Object *obj) 2154 { 2155 ARMCPU *cpu = ARM_CPU(obj); 2156 2157 cpu->dtb_compatible = "marvell,xscale"; 2158 set_feature(&cpu->env, ARM_FEATURE_V5); 2159 set_feature(&cpu->env, ARM_FEATURE_XSCALE); 2160 set_feature(&cpu->env, ARM_FEATURE_IWMMXT); 2161 cpu->midr = 0x69054114; 2162 cpu->ctr = 0xd172172; 2163 cpu->reset_sctlr = 0x00000078; 2164 } 2165 2166 static void pxa270c5_initfn(Object *obj) 2167 { 2168 ARMCPU *cpu = ARM_CPU(obj); 2169 2170 cpu->dtb_compatible = "marvell,xscale"; 2171 set_feature(&cpu->env, ARM_FEATURE_V5); 2172 set_feature(&cpu->env, ARM_FEATURE_XSCALE); 2173 set_feature(&cpu->env, ARM_FEATURE_IWMMXT); 2174 cpu->midr = 0x69054117; 2175 cpu->ctr = 0xd172172; 2176 cpu->reset_sctlr = 0x00000078; 2177 } 2178 2179 #ifndef TARGET_AARCH64 2180 /* -cpu max: if KVM is enabled, like -cpu host (best possible with this host); 2181 * otherwise, a CPU with as many features enabled as our emulation supports. 2182 * The version of '-cpu max' for qemu-system-aarch64 is defined in cpu64.c; 2183 * this only needs to handle 32 bits. 2184 */ 2185 static void arm_max_initfn(Object *obj) 2186 { 2187 ARMCPU *cpu = ARM_CPU(obj); 2188 2189 if (kvm_enabled()) { 2190 kvm_arm_set_cpu_features_from_host(cpu); 2191 } else { 2192 cortex_a15_initfn(obj); 2193 2194 /* old-style VFP short-vector support */ 2195 cpu->isar.mvfr0 = FIELD_DP32(cpu->isar.mvfr0, MVFR0, FPSHVEC, 1); 2196 2197 #ifdef CONFIG_USER_ONLY 2198 /* We don't set these in system emulation mode for the moment, 2199 * since we don't correctly set (all of) the ID registers to 2200 * advertise them. 2201 */ 2202 set_feature(&cpu->env, ARM_FEATURE_V8); 2203 { 2204 uint32_t t; 2205 2206 t = cpu->isar.id_isar5; 2207 t = FIELD_DP32(t, ID_ISAR5, AES, 2); 2208 t = FIELD_DP32(t, ID_ISAR5, SHA1, 1); 2209 t = FIELD_DP32(t, ID_ISAR5, SHA2, 1); 2210 t = FIELD_DP32(t, ID_ISAR5, CRC32, 1); 2211 t = FIELD_DP32(t, ID_ISAR5, RDM, 1); 2212 t = FIELD_DP32(t, ID_ISAR5, VCMA, 1); 2213 cpu->isar.id_isar5 = t; 2214 2215 t = cpu->isar.id_isar6; 2216 t = FIELD_DP32(t, ID_ISAR6, JSCVT, 1); 2217 t = FIELD_DP32(t, ID_ISAR6, DP, 1); 2218 t = FIELD_DP32(t, ID_ISAR6, FHM, 1); 2219 t = FIELD_DP32(t, ID_ISAR6, SB, 1); 2220 t = FIELD_DP32(t, ID_ISAR6, SPECRES, 1); 2221 cpu->isar.id_isar6 = t; 2222 2223 t = cpu->isar.mvfr2; 2224 t = FIELD_DP32(t, MVFR2, SIMDMISC, 3); /* SIMD MaxNum */ 2225 t = FIELD_DP32(t, MVFR2, FPMISC, 4); /* FP MaxNum */ 2226 cpu->isar.mvfr2 = t; 2227 2228 t = cpu->id_mmfr4; 2229 t = FIELD_DP32(t, ID_MMFR4, HPDS, 1); /* AA32HPD */ 2230 cpu->id_mmfr4 = t; 2231 } 2232 #endif 2233 } 2234 } 2235 #endif 2236 2237 #endif /* !defined(CONFIG_USER_ONLY) || !defined(TARGET_AARCH64) */ 2238 2239 struct ARMCPUInfo { 2240 const char *name; 2241 void (*initfn)(Object *obj); 2242 void (*class_init)(ObjectClass *oc, void *data); 2243 }; 2244 2245 static const ARMCPUInfo arm_cpus[] = { 2246 #if !defined(CONFIG_USER_ONLY) || !defined(TARGET_AARCH64) 2247 { .name = "arm926", .initfn = arm926_initfn }, 2248 { .name = "arm946", .initfn = arm946_initfn }, 2249 { .name = "arm1026", .initfn = arm1026_initfn }, 2250 /* What QEMU calls "arm1136-r2" is actually the 1136 r0p2, i.e. an 2251 * older core than plain "arm1136". In particular this does not 2252 * have the v6K features. 2253 */ 2254 { .name = "arm1136-r2", .initfn = arm1136_r2_initfn }, 2255 { .name = "arm1136", .initfn = arm1136_initfn }, 2256 { .name = "arm1176", .initfn = arm1176_initfn }, 2257 { .name = "arm11mpcore", .initfn = arm11mpcore_initfn }, 2258 { .name = "cortex-m0", .initfn = cortex_m0_initfn, 2259 .class_init = arm_v7m_class_init }, 2260 { .name = "cortex-m3", .initfn = cortex_m3_initfn, 2261 .class_init = arm_v7m_class_init }, 2262 { .name = "cortex-m4", .initfn = cortex_m4_initfn, 2263 .class_init = arm_v7m_class_init }, 2264 { .name = "cortex-m33", .initfn = cortex_m33_initfn, 2265 .class_init = arm_v7m_class_init }, 2266 { .name = "cortex-r5", .initfn = cortex_r5_initfn }, 2267 { .name = "cortex-r5f", .initfn = cortex_r5f_initfn }, 2268 { .name = "cortex-a7", .initfn = cortex_a7_initfn }, 2269 { .name = "cortex-a8", .initfn = cortex_a8_initfn }, 2270 { .name = "cortex-a9", .initfn = cortex_a9_initfn }, 2271 { .name = "cortex-a15", .initfn = cortex_a15_initfn }, 2272 { .name = "ti925t", .initfn = ti925t_initfn }, 2273 { .name = "sa1100", .initfn = sa1100_initfn }, 2274 { .name = "sa1110", .initfn = sa1110_initfn }, 2275 { .name = "pxa250", .initfn = pxa250_initfn }, 2276 { .name = "pxa255", .initfn = pxa255_initfn }, 2277 { .name = "pxa260", .initfn = pxa260_initfn }, 2278 { .name = "pxa261", .initfn = pxa261_initfn }, 2279 { .name = "pxa262", .initfn = pxa262_initfn }, 2280 /* "pxa270" is an alias for "pxa270-a0" */ 2281 { .name = "pxa270", .initfn = pxa270a0_initfn }, 2282 { .name = "pxa270-a0", .initfn = pxa270a0_initfn }, 2283 { .name = "pxa270-a1", .initfn = pxa270a1_initfn }, 2284 { .name = "pxa270-b0", .initfn = pxa270b0_initfn }, 2285 { .name = "pxa270-b1", .initfn = pxa270b1_initfn }, 2286 { .name = "pxa270-c0", .initfn = pxa270c0_initfn }, 2287 { .name = "pxa270-c5", .initfn = pxa270c5_initfn }, 2288 #ifndef TARGET_AARCH64 2289 { .name = "max", .initfn = arm_max_initfn }, 2290 #endif 2291 #ifdef CONFIG_USER_ONLY 2292 { .name = "any", .initfn = arm_max_initfn }, 2293 #endif 2294 #endif 2295 { .name = NULL } 2296 }; 2297 2298 static Property arm_cpu_properties[] = { 2299 DEFINE_PROP_BOOL("start-powered-off", ARMCPU, start_powered_off, false), 2300 DEFINE_PROP_UINT32("psci-conduit", ARMCPU, psci_conduit, 0), 2301 DEFINE_PROP_UINT32("midr", ARMCPU, midr, 0), 2302 DEFINE_PROP_UINT64("mp-affinity", ARMCPU, 2303 mp_affinity, ARM64_AFFINITY_INVALID), 2304 DEFINE_PROP_INT32("node-id", ARMCPU, node_id, CPU_UNSET_NUMA_NODE_ID), 2305 DEFINE_PROP_INT32("core-count", ARMCPU, core_count, -1), 2306 DEFINE_PROP_END_OF_LIST() 2307 }; 2308 2309 static gchar *arm_gdb_arch_name(CPUState *cs) 2310 { 2311 ARMCPU *cpu = ARM_CPU(cs); 2312 CPUARMState *env = &cpu->env; 2313 2314 if (arm_feature(env, ARM_FEATURE_IWMMXT)) { 2315 return g_strdup("iwmmxt"); 2316 } 2317 return g_strdup("arm"); 2318 } 2319 2320 static void arm_cpu_class_init(ObjectClass *oc, void *data) 2321 { 2322 ARMCPUClass *acc = ARM_CPU_CLASS(oc); 2323 CPUClass *cc = CPU_CLASS(acc); 2324 DeviceClass *dc = DEVICE_CLASS(oc); 2325 2326 device_class_set_parent_realize(dc, arm_cpu_realizefn, 2327 &acc->parent_realize); 2328 dc->props = arm_cpu_properties; 2329 2330 acc->parent_reset = cc->reset; 2331 cc->reset = arm_cpu_reset; 2332 2333 cc->class_by_name = arm_cpu_class_by_name; 2334 cc->has_work = arm_cpu_has_work; 2335 cc->cpu_exec_interrupt = arm_cpu_exec_interrupt; 2336 cc->dump_state = arm_cpu_dump_state; 2337 cc->set_pc = arm_cpu_set_pc; 2338 cc->synchronize_from_tb = arm_cpu_synchronize_from_tb; 2339 cc->gdb_read_register = arm_cpu_gdb_read_register; 2340 cc->gdb_write_register = arm_cpu_gdb_write_register; 2341 #ifndef CONFIG_USER_ONLY 2342 cc->do_interrupt = arm_cpu_do_interrupt; 2343 cc->do_unaligned_access = arm_cpu_do_unaligned_access; 2344 cc->do_transaction_failed = arm_cpu_do_transaction_failed; 2345 cc->get_phys_page_attrs_debug = arm_cpu_get_phys_page_attrs_debug; 2346 cc->asidx_from_attrs = arm_asidx_from_attrs; 2347 cc->vmsd = &vmstate_arm_cpu; 2348 cc->virtio_is_big_endian = arm_cpu_virtio_is_big_endian; 2349 cc->write_elf64_note = arm_cpu_write_elf64_note; 2350 cc->write_elf32_note = arm_cpu_write_elf32_note; 2351 #endif 2352 cc->gdb_num_core_regs = 26; 2353 cc->gdb_core_xml_file = "arm-core.xml"; 2354 cc->gdb_arch_name = arm_gdb_arch_name; 2355 cc->gdb_get_dynamic_xml = arm_gdb_get_dynamic_xml; 2356 cc->gdb_stop_before_watchpoint = true; 2357 cc->debug_excp_handler = arm_debug_excp_handler; 2358 cc->debug_check_watchpoint = arm_debug_check_watchpoint; 2359 #if !defined(CONFIG_USER_ONLY) 2360 cc->adjust_watchpoint_address = arm_adjust_watchpoint_address; 2361 #endif 2362 2363 cc->disas_set_info = arm_disas_set_info; 2364 #ifdef CONFIG_TCG 2365 cc->tcg_initialize = arm_translate_init; 2366 cc->tlb_fill = arm_cpu_tlb_fill; 2367 #endif 2368 } 2369 2370 #ifdef CONFIG_KVM 2371 static void arm_host_initfn(Object *obj) 2372 { 2373 ARMCPU *cpu = ARM_CPU(obj); 2374 2375 kvm_arm_set_cpu_features_from_host(cpu); 2376 arm_cpu_post_init(obj); 2377 } 2378 2379 static const TypeInfo host_arm_cpu_type_info = { 2380 .name = TYPE_ARM_HOST_CPU, 2381 #ifdef TARGET_AARCH64 2382 .parent = TYPE_AARCH64_CPU, 2383 #else 2384 .parent = TYPE_ARM_CPU, 2385 #endif 2386 .instance_init = arm_host_initfn, 2387 }; 2388 2389 #endif 2390 2391 static void arm_cpu_instance_init(Object *obj) 2392 { 2393 ARMCPUClass *acc = ARM_CPU_GET_CLASS(obj); 2394 2395 acc->info->initfn(obj); 2396 arm_cpu_post_init(obj); 2397 } 2398 2399 static void cpu_register_class_init(ObjectClass *oc, void *data) 2400 { 2401 ARMCPUClass *acc = ARM_CPU_CLASS(oc); 2402 2403 acc->info = data; 2404 } 2405 2406 static void cpu_register(const ARMCPUInfo *info) 2407 { 2408 TypeInfo type_info = { 2409 .parent = TYPE_ARM_CPU, 2410 .instance_size = sizeof(ARMCPU), 2411 .instance_init = arm_cpu_instance_init, 2412 .class_size = sizeof(ARMCPUClass), 2413 .class_init = info->class_init ?: cpu_register_class_init, 2414 .class_data = (void *)info, 2415 }; 2416 2417 type_info.name = g_strdup_printf("%s-" TYPE_ARM_CPU, info->name); 2418 type_register(&type_info); 2419 g_free((void *)type_info.name); 2420 } 2421 2422 static const TypeInfo arm_cpu_type_info = { 2423 .name = TYPE_ARM_CPU, 2424 .parent = TYPE_CPU, 2425 .instance_size = sizeof(ARMCPU), 2426 .instance_init = arm_cpu_initfn, 2427 .instance_finalize = arm_cpu_finalizefn, 2428 .abstract = true, 2429 .class_size = sizeof(ARMCPUClass), 2430 .class_init = arm_cpu_class_init, 2431 }; 2432 2433 static const TypeInfo idau_interface_type_info = { 2434 .name = TYPE_IDAU_INTERFACE, 2435 .parent = TYPE_INTERFACE, 2436 .class_size = sizeof(IDAUInterfaceClass), 2437 }; 2438 2439 static void arm_cpu_register_types(void) 2440 { 2441 const ARMCPUInfo *info = arm_cpus; 2442 2443 type_register_static(&arm_cpu_type_info); 2444 type_register_static(&idau_interface_type_info); 2445 2446 while (info->name) { 2447 cpu_register(info); 2448 info++; 2449 } 2450 2451 #ifdef CONFIG_KVM 2452 type_register_static(&host_arm_cpu_type_info); 2453 #endif 2454 } 2455 2456 type_init(arm_cpu_register_types) 2457