1 /* 2 * QEMU ARM CPU 3 * 4 * Copyright (c) 2012 SUSE LINUX Products GmbH 5 * 6 * This program is free software; you can redistribute it and/or 7 * modify it under the terms of the GNU General Public License 8 * as published by the Free Software Foundation; either version 2 9 * of the License, or (at your option) any later version. 10 * 11 * This program is distributed in the hope that it will be useful, 12 * but WITHOUT ANY WARRANTY; without even the implied warranty of 13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 14 * GNU General Public License for more details. 15 * 16 * You should have received a copy of the GNU General Public License 17 * along with this program; if not, see 18 * <http://www.gnu.org/licenses/gpl-2.0.html> 19 */ 20 21 #include "qemu/osdep.h" 22 #include "qemu/qemu-print.h" 23 #include "qemu/timer.h" 24 #include "qemu/log.h" 25 #include "exec/page-vary.h" 26 #include "target/arm/idau.h" 27 #include "qemu/module.h" 28 #include "qapi/error.h" 29 #include "cpu.h" 30 #ifdef CONFIG_TCG 31 #include "hw/core/tcg-cpu-ops.h" 32 #endif /* CONFIG_TCG */ 33 #include "internals.h" 34 #include "cpu-features.h" 35 #include "exec/exec-all.h" 36 #include "hw/qdev-properties.h" 37 #if !defined(CONFIG_USER_ONLY) 38 #include "hw/loader.h" 39 #include "hw/boards.h" 40 #ifdef CONFIG_TCG 41 #include "hw/intc/armv7m_nvic.h" 42 #endif /* CONFIG_TCG */ 43 #endif /* !CONFIG_USER_ONLY */ 44 #include "sysemu/tcg.h" 45 #include "sysemu/qtest.h" 46 #include "sysemu/hw_accel.h" 47 #include "kvm_arm.h" 48 #include "disas/capstone.h" 49 #include "fpu/softfloat.h" 50 #include "cpregs.h" 51 52 static void arm_cpu_set_pc(CPUState *cs, vaddr value) 53 { 54 ARMCPU *cpu = ARM_CPU(cs); 55 CPUARMState *env = &cpu->env; 56 57 if (is_a64(env)) { 58 env->pc = value; 59 env->thumb = false; 60 } else { 61 env->regs[15] = value & ~1; 62 env->thumb = value & 1; 63 } 64 } 65 66 static vaddr arm_cpu_get_pc(CPUState *cs) 67 { 68 ARMCPU *cpu = ARM_CPU(cs); 69 CPUARMState *env = &cpu->env; 70 71 if (is_a64(env)) { 72 return env->pc; 73 } else { 74 return env->regs[15]; 75 } 76 } 77 78 #ifdef CONFIG_TCG 79 void arm_cpu_synchronize_from_tb(CPUState *cs, 80 const TranslationBlock *tb) 81 { 82 /* The program counter is always up to date with CF_PCREL. */ 83 if (!(tb_cflags(tb) & CF_PCREL)) { 84 CPUARMState *env = cpu_env(cs); 85 /* 86 * It's OK to look at env for the current mode here, because it's 87 * never possible for an AArch64 TB to chain to an AArch32 TB. 88 */ 89 if (is_a64(env)) { 90 env->pc = tb->pc; 91 } else { 92 env->regs[15] = tb->pc; 93 } 94 } 95 } 96 97 void arm_restore_state_to_opc(CPUState *cs, 98 const TranslationBlock *tb, 99 const uint64_t *data) 100 { 101 CPUARMState *env = cpu_env(cs); 102 103 if (is_a64(env)) { 104 if (tb_cflags(tb) & CF_PCREL) { 105 env->pc = (env->pc & TARGET_PAGE_MASK) | data[0]; 106 } else { 107 env->pc = data[0]; 108 } 109 env->condexec_bits = 0; 110 env->exception.syndrome = data[2] << ARM_INSN_START_WORD2_SHIFT; 111 } else { 112 if (tb_cflags(tb) & CF_PCREL) { 113 env->regs[15] = (env->regs[15] & TARGET_PAGE_MASK) | data[0]; 114 } else { 115 env->regs[15] = data[0]; 116 } 117 env->condexec_bits = data[1]; 118 env->exception.syndrome = data[2] << ARM_INSN_START_WORD2_SHIFT; 119 } 120 } 121 #endif /* CONFIG_TCG */ 122 123 static bool arm_cpu_has_work(CPUState *cs) 124 { 125 ARMCPU *cpu = ARM_CPU(cs); 126 127 return (cpu->power_state != PSCI_OFF) 128 && cs->interrupt_request & 129 (CPU_INTERRUPT_FIQ | CPU_INTERRUPT_HARD 130 | CPU_INTERRUPT_VFIQ | CPU_INTERRUPT_VIRQ | CPU_INTERRUPT_VSERR 131 | CPU_INTERRUPT_EXITTB); 132 } 133 134 void arm_register_pre_el_change_hook(ARMCPU *cpu, ARMELChangeHookFn *hook, 135 void *opaque) 136 { 137 ARMELChangeHook *entry = g_new0(ARMELChangeHook, 1); 138 139 entry->hook = hook; 140 entry->opaque = opaque; 141 142 QLIST_INSERT_HEAD(&cpu->pre_el_change_hooks, entry, node); 143 } 144 145 void arm_register_el_change_hook(ARMCPU *cpu, ARMELChangeHookFn *hook, 146 void *opaque) 147 { 148 ARMELChangeHook *entry = g_new0(ARMELChangeHook, 1); 149 150 entry->hook = hook; 151 entry->opaque = opaque; 152 153 QLIST_INSERT_HEAD(&cpu->el_change_hooks, entry, node); 154 } 155 156 static void cp_reg_reset(gpointer key, gpointer value, gpointer opaque) 157 { 158 /* Reset a single ARMCPRegInfo register */ 159 ARMCPRegInfo *ri = value; 160 ARMCPU *cpu = opaque; 161 162 if (ri->type & (ARM_CP_SPECIAL_MASK | ARM_CP_ALIAS)) { 163 return; 164 } 165 166 if (ri->resetfn) { 167 ri->resetfn(&cpu->env, ri); 168 return; 169 } 170 171 /* A zero offset is never possible as it would be regs[0] 172 * so we use it to indicate that reset is being handled elsewhere. 173 * This is basically only used for fields in non-core coprocessors 174 * (like the pxa2xx ones). 175 */ 176 if (!ri->fieldoffset) { 177 return; 178 } 179 180 if (cpreg_field_is_64bit(ri)) { 181 CPREG_FIELD64(&cpu->env, ri) = ri->resetvalue; 182 } else { 183 CPREG_FIELD32(&cpu->env, ri) = ri->resetvalue; 184 } 185 } 186 187 static void cp_reg_check_reset(gpointer key, gpointer value, gpointer opaque) 188 { 189 /* Purely an assertion check: we've already done reset once, 190 * so now check that running the reset for the cpreg doesn't 191 * change its value. This traps bugs where two different cpregs 192 * both try to reset the same state field but to different values. 193 */ 194 ARMCPRegInfo *ri = value; 195 ARMCPU *cpu = opaque; 196 uint64_t oldvalue, newvalue; 197 198 if (ri->type & (ARM_CP_SPECIAL_MASK | ARM_CP_ALIAS | ARM_CP_NO_RAW)) { 199 return; 200 } 201 202 oldvalue = read_raw_cp_reg(&cpu->env, ri); 203 cp_reg_reset(key, value, opaque); 204 newvalue = read_raw_cp_reg(&cpu->env, ri); 205 assert(oldvalue == newvalue); 206 } 207 208 static void arm_cpu_reset_hold(Object *obj) 209 { 210 CPUState *s = CPU(obj); 211 ARMCPU *cpu = ARM_CPU(s); 212 ARMCPUClass *acc = ARM_CPU_GET_CLASS(cpu); 213 CPUARMState *env = &cpu->env; 214 215 if (acc->parent_phases.hold) { 216 acc->parent_phases.hold(obj); 217 } 218 219 memset(env, 0, offsetof(CPUARMState, end_reset_fields)); 220 221 g_hash_table_foreach(cpu->cp_regs, cp_reg_reset, cpu); 222 g_hash_table_foreach(cpu->cp_regs, cp_reg_check_reset, cpu); 223 224 env->vfp.xregs[ARM_VFP_FPSID] = cpu->reset_fpsid; 225 env->vfp.xregs[ARM_VFP_MVFR0] = cpu->isar.mvfr0; 226 env->vfp.xregs[ARM_VFP_MVFR1] = cpu->isar.mvfr1; 227 env->vfp.xregs[ARM_VFP_MVFR2] = cpu->isar.mvfr2; 228 229 cpu->power_state = s->start_powered_off ? PSCI_OFF : PSCI_ON; 230 231 if (arm_feature(env, ARM_FEATURE_IWMMXT)) { 232 env->iwmmxt.cregs[ARM_IWMMXT_wCID] = 0x69051000 | 'Q'; 233 } 234 235 if (arm_feature(env, ARM_FEATURE_AARCH64)) { 236 /* 64 bit CPUs always start in 64 bit mode */ 237 env->aarch64 = true; 238 #if defined(CONFIG_USER_ONLY) 239 env->pstate = PSTATE_MODE_EL0t; 240 /* Userspace expects access to DC ZVA, CTL_EL0 and the cache ops */ 241 env->cp15.sctlr_el[1] |= SCTLR_UCT | SCTLR_UCI | SCTLR_DZE; 242 /* Enable all PAC keys. */ 243 env->cp15.sctlr_el[1] |= (SCTLR_EnIA | SCTLR_EnIB | 244 SCTLR_EnDA | SCTLR_EnDB); 245 /* Trap on btype=3 for PACIxSP. */ 246 env->cp15.sctlr_el[1] |= SCTLR_BT0; 247 /* Trap on implementation defined registers. */ 248 if (cpu_isar_feature(aa64_tidcp1, cpu)) { 249 env->cp15.sctlr_el[1] |= SCTLR_TIDCP; 250 } 251 /* and to the FP/Neon instructions */ 252 env->cp15.cpacr_el1 = FIELD_DP64(env->cp15.cpacr_el1, 253 CPACR_EL1, FPEN, 3); 254 /* and to the SVE instructions, with default vector length */ 255 if (cpu_isar_feature(aa64_sve, cpu)) { 256 env->cp15.cpacr_el1 = FIELD_DP64(env->cp15.cpacr_el1, 257 CPACR_EL1, ZEN, 3); 258 env->vfp.zcr_el[1] = cpu->sve_default_vq - 1; 259 } 260 /* and for SME instructions, with default vector length, and TPIDR2 */ 261 if (cpu_isar_feature(aa64_sme, cpu)) { 262 env->cp15.sctlr_el[1] |= SCTLR_EnTP2; 263 env->cp15.cpacr_el1 = FIELD_DP64(env->cp15.cpacr_el1, 264 CPACR_EL1, SMEN, 3); 265 env->vfp.smcr_el[1] = cpu->sme_default_vq - 1; 266 if (cpu_isar_feature(aa64_sme_fa64, cpu)) { 267 env->vfp.smcr_el[1] = FIELD_DP64(env->vfp.smcr_el[1], 268 SMCR, FA64, 1); 269 } 270 } 271 /* 272 * Enable 48-bit address space (TODO: take reserved_va into account). 273 * Enable TBI0 but not TBI1. 274 * Note that this must match useronly_clean_ptr. 275 */ 276 env->cp15.tcr_el[1] = 5 | (1ULL << 37); 277 278 /* Enable MTE */ 279 if (cpu_isar_feature(aa64_mte, cpu)) { 280 /* Enable tag access, but leave TCF0 as No Effect (0). */ 281 env->cp15.sctlr_el[1] |= SCTLR_ATA0; 282 /* 283 * Exclude all tags, so that tag 0 is always used. 284 * This corresponds to Linux current->thread.gcr_incl = 0. 285 * 286 * Set RRND, so that helper_irg() will generate a seed later. 287 * Here in cpu_reset(), the crypto subsystem has not yet been 288 * initialized. 289 */ 290 env->cp15.gcr_el1 = 0x1ffff; 291 } 292 /* 293 * Disable access to SCXTNUM_EL0 from CSV2_1p2. 294 * This is not yet exposed from the Linux kernel in any way. 295 */ 296 env->cp15.sctlr_el[1] |= SCTLR_TSCXT; 297 /* Disable access to Debug Communication Channel (DCC). */ 298 env->cp15.mdscr_el1 |= 1 << 12; 299 /* Enable FEAT_MOPS */ 300 env->cp15.sctlr_el[1] |= SCTLR_MSCEN; 301 #else 302 /* Reset into the highest available EL */ 303 if (arm_feature(env, ARM_FEATURE_EL3)) { 304 env->pstate = PSTATE_MODE_EL3h; 305 } else if (arm_feature(env, ARM_FEATURE_EL2)) { 306 env->pstate = PSTATE_MODE_EL2h; 307 } else { 308 env->pstate = PSTATE_MODE_EL1h; 309 } 310 311 /* Sample rvbar at reset. */ 312 env->cp15.rvbar = cpu->rvbar_prop; 313 env->pc = env->cp15.rvbar; 314 #endif 315 } else { 316 #if defined(CONFIG_USER_ONLY) 317 /* Userspace expects access to cp10 and cp11 for FP/Neon */ 318 env->cp15.cpacr_el1 = FIELD_DP64(env->cp15.cpacr_el1, 319 CPACR, CP10, 3); 320 env->cp15.cpacr_el1 = FIELD_DP64(env->cp15.cpacr_el1, 321 CPACR, CP11, 3); 322 #endif 323 if (arm_feature(env, ARM_FEATURE_V8)) { 324 env->cp15.rvbar = cpu->rvbar_prop; 325 env->regs[15] = cpu->rvbar_prop; 326 } 327 } 328 329 #if defined(CONFIG_USER_ONLY) 330 env->uncached_cpsr = ARM_CPU_MODE_USR; 331 /* For user mode we must enable access to coprocessors */ 332 env->vfp.xregs[ARM_VFP_FPEXC] = 1 << 30; 333 if (arm_feature(env, ARM_FEATURE_IWMMXT)) { 334 env->cp15.c15_cpar = 3; 335 } else if (arm_feature(env, ARM_FEATURE_XSCALE)) { 336 env->cp15.c15_cpar = 1; 337 } 338 #else 339 340 /* 341 * If the highest available EL is EL2, AArch32 will start in Hyp 342 * mode; otherwise it starts in SVC. Note that if we start in 343 * AArch64 then these values in the uncached_cpsr will be ignored. 344 */ 345 if (arm_feature(env, ARM_FEATURE_EL2) && 346 !arm_feature(env, ARM_FEATURE_EL3)) { 347 env->uncached_cpsr = ARM_CPU_MODE_HYP; 348 } else { 349 env->uncached_cpsr = ARM_CPU_MODE_SVC; 350 } 351 env->daif = PSTATE_D | PSTATE_A | PSTATE_I | PSTATE_F; 352 353 /* AArch32 has a hard highvec setting of 0xFFFF0000. If we are currently 354 * executing as AArch32 then check if highvecs are enabled and 355 * adjust the PC accordingly. 356 */ 357 if (A32_BANKED_CURRENT_REG_GET(env, sctlr) & SCTLR_V) { 358 env->regs[15] = 0xFFFF0000; 359 } 360 361 env->vfp.xregs[ARM_VFP_FPEXC] = 0; 362 #endif 363 364 if (arm_feature(env, ARM_FEATURE_M)) { 365 #ifndef CONFIG_USER_ONLY 366 uint32_t initial_msp; /* Loaded from 0x0 */ 367 uint32_t initial_pc; /* Loaded from 0x4 */ 368 uint8_t *rom; 369 uint32_t vecbase; 370 #endif 371 372 if (cpu_isar_feature(aa32_lob, cpu)) { 373 /* 374 * LTPSIZE is constant 4 if MVE not implemented, and resets 375 * to an UNKNOWN value if MVE is implemented. We choose to 376 * always reset to 4. 377 */ 378 env->v7m.ltpsize = 4; 379 /* The LTPSIZE field in FPDSCR is constant and reads as 4. */ 380 env->v7m.fpdscr[M_REG_NS] = 4 << FPCR_LTPSIZE_SHIFT; 381 env->v7m.fpdscr[M_REG_S] = 4 << FPCR_LTPSIZE_SHIFT; 382 } 383 384 if (arm_feature(env, ARM_FEATURE_M_SECURITY)) { 385 env->v7m.secure = true; 386 } else { 387 /* This bit resets to 0 if security is supported, but 1 if 388 * it is not. The bit is not present in v7M, but we set it 389 * here so we can avoid having to make checks on it conditional 390 * on ARM_FEATURE_V8 (we don't let the guest see the bit). 391 */ 392 env->v7m.aircr = R_V7M_AIRCR_BFHFNMINS_MASK; 393 /* 394 * Set NSACR to indicate "NS access permitted to everything"; 395 * this avoids having to have all the tests of it being 396 * conditional on ARM_FEATURE_M_SECURITY. Note also that from 397 * v8.1M the guest-visible value of NSACR in a CPU without the 398 * Security Extension is 0xcff. 399 */ 400 env->v7m.nsacr = 0xcff; 401 } 402 403 /* In v7M the reset value of this bit is IMPDEF, but ARM recommends 404 * that it resets to 1, so QEMU always does that rather than making 405 * it dependent on CPU model. In v8M it is RES1. 406 */ 407 env->v7m.ccr[M_REG_NS] = R_V7M_CCR_STKALIGN_MASK; 408 env->v7m.ccr[M_REG_S] = R_V7M_CCR_STKALIGN_MASK; 409 if (arm_feature(env, ARM_FEATURE_V8)) { 410 /* in v8M the NONBASETHRDENA bit [0] is RES1 */ 411 env->v7m.ccr[M_REG_NS] |= R_V7M_CCR_NONBASETHRDENA_MASK; 412 env->v7m.ccr[M_REG_S] |= R_V7M_CCR_NONBASETHRDENA_MASK; 413 } 414 if (!arm_feature(env, ARM_FEATURE_M_MAIN)) { 415 env->v7m.ccr[M_REG_NS] |= R_V7M_CCR_UNALIGN_TRP_MASK; 416 env->v7m.ccr[M_REG_S] |= R_V7M_CCR_UNALIGN_TRP_MASK; 417 } 418 419 if (cpu_isar_feature(aa32_vfp_simd, cpu)) { 420 env->v7m.fpccr[M_REG_NS] = R_V7M_FPCCR_ASPEN_MASK; 421 env->v7m.fpccr[M_REG_S] = R_V7M_FPCCR_ASPEN_MASK | 422 R_V7M_FPCCR_LSPEN_MASK | R_V7M_FPCCR_S_MASK; 423 } 424 425 #ifndef CONFIG_USER_ONLY 426 /* Unlike A/R profile, M profile defines the reset LR value */ 427 env->regs[14] = 0xffffffff; 428 429 env->v7m.vecbase[M_REG_S] = cpu->init_svtor & 0xffffff80; 430 env->v7m.vecbase[M_REG_NS] = cpu->init_nsvtor & 0xffffff80; 431 432 /* Load the initial SP and PC from offset 0 and 4 in the vector table */ 433 vecbase = env->v7m.vecbase[env->v7m.secure]; 434 rom = rom_ptr_for_as(s->as, vecbase, 8); 435 if (rom) { 436 /* Address zero is covered by ROM which hasn't yet been 437 * copied into physical memory. 438 */ 439 initial_msp = ldl_p(rom); 440 initial_pc = ldl_p(rom + 4); 441 } else { 442 /* Address zero not covered by a ROM blob, or the ROM blob 443 * is in non-modifiable memory and this is a second reset after 444 * it got copied into memory. In the latter case, rom_ptr 445 * will return a NULL pointer and we should use ldl_phys instead. 446 */ 447 initial_msp = ldl_phys(s->as, vecbase); 448 initial_pc = ldl_phys(s->as, vecbase + 4); 449 } 450 451 qemu_log_mask(CPU_LOG_INT, 452 "Loaded reset SP 0x%x PC 0x%x from vector table\n", 453 initial_msp, initial_pc); 454 455 env->regs[13] = initial_msp & 0xFFFFFFFC; 456 env->regs[15] = initial_pc & ~1; 457 env->thumb = initial_pc & 1; 458 #else 459 /* 460 * For user mode we run non-secure and with access to the FPU. 461 * The FPU context is active (ie does not need further setup) 462 * and is owned by non-secure. 463 */ 464 env->v7m.secure = false; 465 env->v7m.nsacr = 0xcff; 466 env->v7m.cpacr[M_REG_NS] = 0xf0ffff; 467 env->v7m.fpccr[M_REG_S] &= 468 ~(R_V7M_FPCCR_LSPEN_MASK | R_V7M_FPCCR_S_MASK); 469 env->v7m.control[M_REG_S] |= R_V7M_CONTROL_FPCA_MASK; 470 #endif 471 } 472 473 /* M profile requires that reset clears the exclusive monitor; 474 * A profile does not, but clearing it makes more sense than having it 475 * set with an exclusive access on address zero. 476 */ 477 arm_clear_exclusive(env); 478 479 if (arm_feature(env, ARM_FEATURE_PMSA)) { 480 if (cpu->pmsav7_dregion > 0) { 481 if (arm_feature(env, ARM_FEATURE_V8)) { 482 memset(env->pmsav8.rbar[M_REG_NS], 0, 483 sizeof(*env->pmsav8.rbar[M_REG_NS]) 484 * cpu->pmsav7_dregion); 485 memset(env->pmsav8.rlar[M_REG_NS], 0, 486 sizeof(*env->pmsav8.rlar[M_REG_NS]) 487 * cpu->pmsav7_dregion); 488 if (arm_feature(env, ARM_FEATURE_M_SECURITY)) { 489 memset(env->pmsav8.rbar[M_REG_S], 0, 490 sizeof(*env->pmsav8.rbar[M_REG_S]) 491 * cpu->pmsav7_dregion); 492 memset(env->pmsav8.rlar[M_REG_S], 0, 493 sizeof(*env->pmsav8.rlar[M_REG_S]) 494 * cpu->pmsav7_dregion); 495 } 496 } else if (arm_feature(env, ARM_FEATURE_V7)) { 497 memset(env->pmsav7.drbar, 0, 498 sizeof(*env->pmsav7.drbar) * cpu->pmsav7_dregion); 499 memset(env->pmsav7.drsr, 0, 500 sizeof(*env->pmsav7.drsr) * cpu->pmsav7_dregion); 501 memset(env->pmsav7.dracr, 0, 502 sizeof(*env->pmsav7.dracr) * cpu->pmsav7_dregion); 503 } 504 } 505 506 if (cpu->pmsav8r_hdregion > 0) { 507 memset(env->pmsav8.hprbar, 0, 508 sizeof(*env->pmsav8.hprbar) * cpu->pmsav8r_hdregion); 509 memset(env->pmsav8.hprlar, 0, 510 sizeof(*env->pmsav8.hprlar) * cpu->pmsav8r_hdregion); 511 } 512 513 env->pmsav7.rnr[M_REG_NS] = 0; 514 env->pmsav7.rnr[M_REG_S] = 0; 515 env->pmsav8.mair0[M_REG_NS] = 0; 516 env->pmsav8.mair0[M_REG_S] = 0; 517 env->pmsav8.mair1[M_REG_NS] = 0; 518 env->pmsav8.mair1[M_REG_S] = 0; 519 } 520 521 if (arm_feature(env, ARM_FEATURE_M_SECURITY)) { 522 if (cpu->sau_sregion > 0) { 523 memset(env->sau.rbar, 0, sizeof(*env->sau.rbar) * cpu->sau_sregion); 524 memset(env->sau.rlar, 0, sizeof(*env->sau.rlar) * cpu->sau_sregion); 525 } 526 env->sau.rnr = 0; 527 /* SAU_CTRL reset value is IMPDEF; we choose 0, which is what 528 * the Cortex-M33 does. 529 */ 530 env->sau.ctrl = 0; 531 } 532 533 set_flush_to_zero(1, &env->vfp.standard_fp_status); 534 set_flush_inputs_to_zero(1, &env->vfp.standard_fp_status); 535 set_default_nan_mode(1, &env->vfp.standard_fp_status); 536 set_default_nan_mode(1, &env->vfp.standard_fp_status_f16); 537 set_float_detect_tininess(float_tininess_before_rounding, 538 &env->vfp.fp_status); 539 set_float_detect_tininess(float_tininess_before_rounding, 540 &env->vfp.standard_fp_status); 541 set_float_detect_tininess(float_tininess_before_rounding, 542 &env->vfp.fp_status_f16); 543 set_float_detect_tininess(float_tininess_before_rounding, 544 &env->vfp.standard_fp_status_f16); 545 #ifndef CONFIG_USER_ONLY 546 if (kvm_enabled()) { 547 kvm_arm_reset_vcpu(cpu); 548 } 549 #endif 550 551 if (tcg_enabled()) { 552 hw_breakpoint_update_all(cpu); 553 hw_watchpoint_update_all(cpu); 554 555 arm_rebuild_hflags(env); 556 } 557 } 558 559 void arm_emulate_firmware_reset(CPUState *cpustate, int target_el) 560 { 561 ARMCPU *cpu = ARM_CPU(cpustate); 562 CPUARMState *env = &cpu->env; 563 bool have_el3 = arm_feature(env, ARM_FEATURE_EL3); 564 bool have_el2 = arm_feature(env, ARM_FEATURE_EL2); 565 566 /* 567 * Check we have the EL we're aiming for. If that is the 568 * highest implemented EL, then cpu_reset has already done 569 * all the work. 570 */ 571 switch (target_el) { 572 case 3: 573 assert(have_el3); 574 return; 575 case 2: 576 assert(have_el2); 577 if (!have_el3) { 578 return; 579 } 580 break; 581 case 1: 582 if (!have_el3 && !have_el2) { 583 return; 584 } 585 break; 586 default: 587 g_assert_not_reached(); 588 } 589 590 if (have_el3) { 591 /* 592 * Set the EL3 state so code can run at EL2. This should match 593 * the requirements set by Linux in its booting spec. 594 */ 595 if (env->aarch64) { 596 env->cp15.scr_el3 |= SCR_RW; 597 if (cpu_isar_feature(aa64_pauth, cpu)) { 598 env->cp15.scr_el3 |= SCR_API | SCR_APK; 599 } 600 if (cpu_isar_feature(aa64_mte, cpu)) { 601 env->cp15.scr_el3 |= SCR_ATA; 602 } 603 if (cpu_isar_feature(aa64_sve, cpu)) { 604 env->cp15.cptr_el[3] |= R_CPTR_EL3_EZ_MASK; 605 env->vfp.zcr_el[3] = 0xf; 606 } 607 if (cpu_isar_feature(aa64_sme, cpu)) { 608 env->cp15.cptr_el[3] |= R_CPTR_EL3_ESM_MASK; 609 env->cp15.scr_el3 |= SCR_ENTP2; 610 env->vfp.smcr_el[3] = 0xf; 611 } 612 if (cpu_isar_feature(aa64_hcx, cpu)) { 613 env->cp15.scr_el3 |= SCR_HXEN; 614 } 615 if (cpu_isar_feature(aa64_fgt, cpu)) { 616 env->cp15.scr_el3 |= SCR_FGTEN; 617 } 618 } 619 620 if (target_el == 2) { 621 /* If the guest is at EL2 then Linux expects the HVC insn to work */ 622 env->cp15.scr_el3 |= SCR_HCE; 623 } 624 625 /* Put CPU into non-secure state */ 626 env->cp15.scr_el3 |= SCR_NS; 627 /* Set NSACR.{CP11,CP10} so NS can access the FPU */ 628 env->cp15.nsacr |= 3 << 10; 629 } 630 631 if (have_el2 && target_el < 2) { 632 /* Set EL2 state so code can run at EL1. */ 633 if (env->aarch64) { 634 env->cp15.hcr_el2 |= HCR_RW; 635 } 636 } 637 638 /* Set the CPU to the desired state */ 639 if (env->aarch64) { 640 env->pstate = aarch64_pstate_mode(target_el, true); 641 } else { 642 static const uint32_t mode_for_el[] = { 643 0, 644 ARM_CPU_MODE_SVC, 645 ARM_CPU_MODE_HYP, 646 ARM_CPU_MODE_SVC, 647 }; 648 649 cpsr_write(env, mode_for_el[target_el], CPSR_M, CPSRWriteRaw); 650 } 651 } 652 653 654 #if defined(CONFIG_TCG) && !defined(CONFIG_USER_ONLY) 655 656 static inline bool arm_excp_unmasked(CPUState *cs, unsigned int excp_idx, 657 unsigned int target_el, 658 unsigned int cur_el, bool secure, 659 uint64_t hcr_el2) 660 { 661 CPUARMState *env = cpu_env(cs); 662 bool pstate_unmasked; 663 bool unmasked = false; 664 665 /* 666 * Don't take exceptions if they target a lower EL. 667 * This check should catch any exceptions that would not be taken 668 * but left pending. 669 */ 670 if (cur_el > target_el) { 671 return false; 672 } 673 674 switch (excp_idx) { 675 case EXCP_FIQ: 676 pstate_unmasked = !(env->daif & PSTATE_F); 677 break; 678 679 case EXCP_IRQ: 680 pstate_unmasked = !(env->daif & PSTATE_I); 681 break; 682 683 case EXCP_VFIQ: 684 if (!(hcr_el2 & HCR_FMO) || (hcr_el2 & HCR_TGE)) { 685 /* VFIQs are only taken when hypervized. */ 686 return false; 687 } 688 return !(env->daif & PSTATE_F); 689 case EXCP_VIRQ: 690 if (!(hcr_el2 & HCR_IMO) || (hcr_el2 & HCR_TGE)) { 691 /* VIRQs are only taken when hypervized. */ 692 return false; 693 } 694 return !(env->daif & PSTATE_I); 695 case EXCP_VSERR: 696 if (!(hcr_el2 & HCR_AMO) || (hcr_el2 & HCR_TGE)) { 697 /* VIRQs are only taken when hypervized. */ 698 return false; 699 } 700 return !(env->daif & PSTATE_A); 701 default: 702 g_assert_not_reached(); 703 } 704 705 /* 706 * Use the target EL, current execution state and SCR/HCR settings to 707 * determine whether the corresponding CPSR bit is used to mask the 708 * interrupt. 709 */ 710 if ((target_el > cur_el) && (target_el != 1)) { 711 /* Exceptions targeting a higher EL may not be maskable */ 712 if (arm_feature(env, ARM_FEATURE_AARCH64)) { 713 switch (target_el) { 714 case 2: 715 /* 716 * According to ARM DDI 0487H.a, an interrupt can be masked 717 * when HCR_E2H and HCR_TGE are both set regardless of the 718 * current Security state. Note that we need to revisit this 719 * part again once we need to support NMI. 720 */ 721 if ((hcr_el2 & (HCR_E2H | HCR_TGE)) != (HCR_E2H | HCR_TGE)) { 722 unmasked = true; 723 } 724 break; 725 case 3: 726 /* Interrupt cannot be masked when the target EL is 3 */ 727 unmasked = true; 728 break; 729 default: 730 g_assert_not_reached(); 731 } 732 } else { 733 /* 734 * The old 32-bit-only environment has a more complicated 735 * masking setup. HCR and SCR bits not only affect interrupt 736 * routing but also change the behaviour of masking. 737 */ 738 bool hcr, scr; 739 740 switch (excp_idx) { 741 case EXCP_FIQ: 742 /* 743 * If FIQs are routed to EL3 or EL2 then there are cases where 744 * we override the CPSR.F in determining if the exception is 745 * masked or not. If neither of these are set then we fall back 746 * to the CPSR.F setting otherwise we further assess the state 747 * below. 748 */ 749 hcr = hcr_el2 & HCR_FMO; 750 scr = (env->cp15.scr_el3 & SCR_FIQ); 751 752 /* 753 * When EL3 is 32-bit, the SCR.FW bit controls whether the 754 * CPSR.F bit masks FIQ interrupts when taken in non-secure 755 * state. If SCR.FW is set then FIQs can be masked by CPSR.F 756 * when non-secure but only when FIQs are only routed to EL3. 757 */ 758 scr = scr && !((env->cp15.scr_el3 & SCR_FW) && !hcr); 759 break; 760 case EXCP_IRQ: 761 /* 762 * When EL3 execution state is 32-bit, if HCR.IMO is set then 763 * we may override the CPSR.I masking when in non-secure state. 764 * The SCR.IRQ setting has already been taken into consideration 765 * when setting the target EL, so it does not have a further 766 * affect here. 767 */ 768 hcr = hcr_el2 & HCR_IMO; 769 scr = false; 770 break; 771 default: 772 g_assert_not_reached(); 773 } 774 775 if ((scr || hcr) && !secure) { 776 unmasked = true; 777 } 778 } 779 } 780 781 /* 782 * The PSTATE bits only mask the interrupt if we have not overridden the 783 * ability above. 784 */ 785 return unmasked || pstate_unmasked; 786 } 787 788 static bool arm_cpu_exec_interrupt(CPUState *cs, int interrupt_request) 789 { 790 CPUClass *cc = CPU_GET_CLASS(cs); 791 CPUARMState *env = cpu_env(cs); 792 uint32_t cur_el = arm_current_el(env); 793 bool secure = arm_is_secure(env); 794 uint64_t hcr_el2 = arm_hcr_el2_eff(env); 795 uint32_t target_el; 796 uint32_t excp_idx; 797 798 /* The prioritization of interrupts is IMPLEMENTATION DEFINED. */ 799 800 if (interrupt_request & CPU_INTERRUPT_FIQ) { 801 excp_idx = EXCP_FIQ; 802 target_el = arm_phys_excp_target_el(cs, excp_idx, cur_el, secure); 803 if (arm_excp_unmasked(cs, excp_idx, target_el, 804 cur_el, secure, hcr_el2)) { 805 goto found; 806 } 807 } 808 if (interrupt_request & CPU_INTERRUPT_HARD) { 809 excp_idx = EXCP_IRQ; 810 target_el = arm_phys_excp_target_el(cs, excp_idx, cur_el, secure); 811 if (arm_excp_unmasked(cs, excp_idx, target_el, 812 cur_el, secure, hcr_el2)) { 813 goto found; 814 } 815 } 816 if (interrupt_request & CPU_INTERRUPT_VIRQ) { 817 excp_idx = EXCP_VIRQ; 818 target_el = 1; 819 if (arm_excp_unmasked(cs, excp_idx, target_el, 820 cur_el, secure, hcr_el2)) { 821 goto found; 822 } 823 } 824 if (interrupt_request & CPU_INTERRUPT_VFIQ) { 825 excp_idx = EXCP_VFIQ; 826 target_el = 1; 827 if (arm_excp_unmasked(cs, excp_idx, target_el, 828 cur_el, secure, hcr_el2)) { 829 goto found; 830 } 831 } 832 if (interrupt_request & CPU_INTERRUPT_VSERR) { 833 excp_idx = EXCP_VSERR; 834 target_el = 1; 835 if (arm_excp_unmasked(cs, excp_idx, target_el, 836 cur_el, secure, hcr_el2)) { 837 /* Taking a virtual abort clears HCR_EL2.VSE */ 838 env->cp15.hcr_el2 &= ~HCR_VSE; 839 cpu_reset_interrupt(cs, CPU_INTERRUPT_VSERR); 840 goto found; 841 } 842 } 843 return false; 844 845 found: 846 cs->exception_index = excp_idx; 847 env->exception.target_el = target_el; 848 cc->tcg_ops->do_interrupt(cs); 849 return true; 850 } 851 852 #endif /* CONFIG_TCG && !CONFIG_USER_ONLY */ 853 854 void arm_cpu_update_virq(ARMCPU *cpu) 855 { 856 /* 857 * Update the interrupt level for VIRQ, which is the logical OR of 858 * the HCR_EL2.VI bit and the input line level from the GIC. 859 */ 860 CPUARMState *env = &cpu->env; 861 CPUState *cs = CPU(cpu); 862 863 bool new_state = (env->cp15.hcr_el2 & HCR_VI) || 864 (env->irq_line_state & CPU_INTERRUPT_VIRQ); 865 866 if (new_state != ((cs->interrupt_request & CPU_INTERRUPT_VIRQ) != 0)) { 867 if (new_state) { 868 cpu_interrupt(cs, CPU_INTERRUPT_VIRQ); 869 } else { 870 cpu_reset_interrupt(cs, CPU_INTERRUPT_VIRQ); 871 } 872 } 873 } 874 875 void arm_cpu_update_vfiq(ARMCPU *cpu) 876 { 877 /* 878 * Update the interrupt level for VFIQ, which is the logical OR of 879 * the HCR_EL2.VF bit and the input line level from the GIC. 880 */ 881 CPUARMState *env = &cpu->env; 882 CPUState *cs = CPU(cpu); 883 884 bool new_state = (env->cp15.hcr_el2 & HCR_VF) || 885 (env->irq_line_state & CPU_INTERRUPT_VFIQ); 886 887 if (new_state != ((cs->interrupt_request & CPU_INTERRUPT_VFIQ) != 0)) { 888 if (new_state) { 889 cpu_interrupt(cs, CPU_INTERRUPT_VFIQ); 890 } else { 891 cpu_reset_interrupt(cs, CPU_INTERRUPT_VFIQ); 892 } 893 } 894 } 895 896 void arm_cpu_update_vserr(ARMCPU *cpu) 897 { 898 /* 899 * Update the interrupt level for VSERR, which is the HCR_EL2.VSE bit. 900 */ 901 CPUARMState *env = &cpu->env; 902 CPUState *cs = CPU(cpu); 903 904 bool new_state = env->cp15.hcr_el2 & HCR_VSE; 905 906 if (new_state != ((cs->interrupt_request & CPU_INTERRUPT_VSERR) != 0)) { 907 if (new_state) { 908 cpu_interrupt(cs, CPU_INTERRUPT_VSERR); 909 } else { 910 cpu_reset_interrupt(cs, CPU_INTERRUPT_VSERR); 911 } 912 } 913 } 914 915 #ifndef CONFIG_USER_ONLY 916 static void arm_cpu_set_irq(void *opaque, int irq, int level) 917 { 918 ARMCPU *cpu = opaque; 919 CPUARMState *env = &cpu->env; 920 CPUState *cs = CPU(cpu); 921 static const int mask[] = { 922 [ARM_CPU_IRQ] = CPU_INTERRUPT_HARD, 923 [ARM_CPU_FIQ] = CPU_INTERRUPT_FIQ, 924 [ARM_CPU_VIRQ] = CPU_INTERRUPT_VIRQ, 925 [ARM_CPU_VFIQ] = CPU_INTERRUPT_VFIQ 926 }; 927 928 if (!arm_feature(env, ARM_FEATURE_EL2) && 929 (irq == ARM_CPU_VIRQ || irq == ARM_CPU_VFIQ)) { 930 /* 931 * The GIC might tell us about VIRQ and VFIQ state, but if we don't 932 * have EL2 support we don't care. (Unless the guest is doing something 933 * silly this will only be calls saying "level is still 0".) 934 */ 935 return; 936 } 937 938 if (level) { 939 env->irq_line_state |= mask[irq]; 940 } else { 941 env->irq_line_state &= ~mask[irq]; 942 } 943 944 switch (irq) { 945 case ARM_CPU_VIRQ: 946 arm_cpu_update_virq(cpu); 947 break; 948 case ARM_CPU_VFIQ: 949 arm_cpu_update_vfiq(cpu); 950 break; 951 case ARM_CPU_IRQ: 952 case ARM_CPU_FIQ: 953 if (level) { 954 cpu_interrupt(cs, mask[irq]); 955 } else { 956 cpu_reset_interrupt(cs, mask[irq]); 957 } 958 break; 959 default: 960 g_assert_not_reached(); 961 } 962 } 963 964 static void arm_cpu_kvm_set_irq(void *opaque, int irq, int level) 965 { 966 #ifdef CONFIG_KVM 967 ARMCPU *cpu = opaque; 968 CPUARMState *env = &cpu->env; 969 CPUState *cs = CPU(cpu); 970 uint32_t linestate_bit; 971 int irq_id; 972 973 switch (irq) { 974 case ARM_CPU_IRQ: 975 irq_id = KVM_ARM_IRQ_CPU_IRQ; 976 linestate_bit = CPU_INTERRUPT_HARD; 977 break; 978 case ARM_CPU_FIQ: 979 irq_id = KVM_ARM_IRQ_CPU_FIQ; 980 linestate_bit = CPU_INTERRUPT_FIQ; 981 break; 982 default: 983 g_assert_not_reached(); 984 } 985 986 if (level) { 987 env->irq_line_state |= linestate_bit; 988 } else { 989 env->irq_line_state &= ~linestate_bit; 990 } 991 kvm_arm_set_irq(cs->cpu_index, KVM_ARM_IRQ_TYPE_CPU, irq_id, !!level); 992 #endif 993 } 994 995 static bool arm_cpu_virtio_is_big_endian(CPUState *cs) 996 { 997 ARMCPU *cpu = ARM_CPU(cs); 998 CPUARMState *env = &cpu->env; 999 1000 cpu_synchronize_state(cs); 1001 return arm_cpu_data_is_big_endian(env); 1002 } 1003 1004 #endif 1005 1006 static void arm_disas_set_info(CPUState *cpu, disassemble_info *info) 1007 { 1008 ARMCPU *ac = ARM_CPU(cpu); 1009 CPUARMState *env = &ac->env; 1010 bool sctlr_b; 1011 1012 if (is_a64(env)) { 1013 info->cap_arch = CS_ARCH_ARM64; 1014 info->cap_insn_unit = 4; 1015 info->cap_insn_split = 4; 1016 } else { 1017 int cap_mode; 1018 if (env->thumb) { 1019 info->cap_insn_unit = 2; 1020 info->cap_insn_split = 4; 1021 cap_mode = CS_MODE_THUMB; 1022 } else { 1023 info->cap_insn_unit = 4; 1024 info->cap_insn_split = 4; 1025 cap_mode = CS_MODE_ARM; 1026 } 1027 if (arm_feature(env, ARM_FEATURE_V8)) { 1028 cap_mode |= CS_MODE_V8; 1029 } 1030 if (arm_feature(env, ARM_FEATURE_M)) { 1031 cap_mode |= CS_MODE_MCLASS; 1032 } 1033 info->cap_arch = CS_ARCH_ARM; 1034 info->cap_mode = cap_mode; 1035 } 1036 1037 sctlr_b = arm_sctlr_b(env); 1038 if (bswap_code(sctlr_b)) { 1039 #if TARGET_BIG_ENDIAN 1040 info->endian = BFD_ENDIAN_LITTLE; 1041 #else 1042 info->endian = BFD_ENDIAN_BIG; 1043 #endif 1044 } 1045 info->flags &= ~INSN_ARM_BE32; 1046 #ifndef CONFIG_USER_ONLY 1047 if (sctlr_b) { 1048 info->flags |= INSN_ARM_BE32; 1049 } 1050 #endif 1051 } 1052 1053 #ifdef TARGET_AARCH64 1054 1055 static void aarch64_cpu_dump_state(CPUState *cs, FILE *f, int flags) 1056 { 1057 ARMCPU *cpu = ARM_CPU(cs); 1058 CPUARMState *env = &cpu->env; 1059 uint32_t psr = pstate_read(env); 1060 int i, j; 1061 int el = arm_current_el(env); 1062 uint64_t hcr = arm_hcr_el2_eff(env); 1063 const char *ns_status; 1064 bool sve; 1065 1066 qemu_fprintf(f, " PC=%016" PRIx64 " ", env->pc); 1067 for (i = 0; i < 32; i++) { 1068 if (i == 31) { 1069 qemu_fprintf(f, " SP=%016" PRIx64 "\n", env->xregs[i]); 1070 } else { 1071 qemu_fprintf(f, "X%02d=%016" PRIx64 "%s", i, env->xregs[i], 1072 (i + 2) % 3 ? " " : "\n"); 1073 } 1074 } 1075 1076 if (arm_feature(env, ARM_FEATURE_EL3) && el != 3) { 1077 ns_status = env->cp15.scr_el3 & SCR_NS ? "NS " : "S "; 1078 } else { 1079 ns_status = ""; 1080 } 1081 qemu_fprintf(f, "PSTATE=%08x %c%c%c%c %sEL%d%c", 1082 psr, 1083 psr & PSTATE_N ? 'N' : '-', 1084 psr & PSTATE_Z ? 'Z' : '-', 1085 psr & PSTATE_C ? 'C' : '-', 1086 psr & PSTATE_V ? 'V' : '-', 1087 ns_status, 1088 el, 1089 psr & PSTATE_SP ? 'h' : 't'); 1090 1091 if (cpu_isar_feature(aa64_sme, cpu)) { 1092 qemu_fprintf(f, " SVCR=%08" PRIx64 " %c%c", 1093 env->svcr, 1094 (FIELD_EX64(env->svcr, SVCR, ZA) ? 'Z' : '-'), 1095 (FIELD_EX64(env->svcr, SVCR, SM) ? 'S' : '-')); 1096 } 1097 if (cpu_isar_feature(aa64_bti, cpu)) { 1098 qemu_fprintf(f, " BTYPE=%d", (psr & PSTATE_BTYPE) >> 10); 1099 } 1100 qemu_fprintf(f, "%s%s%s", 1101 (hcr & HCR_NV) ? " NV" : "", 1102 (hcr & HCR_NV1) ? " NV1" : "", 1103 (hcr & HCR_NV2) ? " NV2" : ""); 1104 if (!(flags & CPU_DUMP_FPU)) { 1105 qemu_fprintf(f, "\n"); 1106 return; 1107 } 1108 if (fp_exception_el(env, el) != 0) { 1109 qemu_fprintf(f, " FPU disabled\n"); 1110 return; 1111 } 1112 qemu_fprintf(f, " FPCR=%08x FPSR=%08x\n", 1113 vfp_get_fpcr(env), vfp_get_fpsr(env)); 1114 1115 if (cpu_isar_feature(aa64_sme, cpu) && FIELD_EX64(env->svcr, SVCR, SM)) { 1116 sve = sme_exception_el(env, el) == 0; 1117 } else if (cpu_isar_feature(aa64_sve, cpu)) { 1118 sve = sve_exception_el(env, el) == 0; 1119 } else { 1120 sve = false; 1121 } 1122 1123 if (sve) { 1124 int zcr_len = sve_vqm1_for_el(env, el); 1125 1126 for (i = 0; i <= FFR_PRED_NUM; i++) { 1127 bool eol; 1128 if (i == FFR_PRED_NUM) { 1129 qemu_fprintf(f, "FFR="); 1130 /* It's last, so end the line. */ 1131 eol = true; 1132 } else { 1133 qemu_fprintf(f, "P%02d=", i); 1134 switch (zcr_len) { 1135 case 0: 1136 eol = i % 8 == 7; 1137 break; 1138 case 1: 1139 eol = i % 6 == 5; 1140 break; 1141 case 2: 1142 case 3: 1143 eol = i % 3 == 2; 1144 break; 1145 default: 1146 /* More than one quadword per predicate. */ 1147 eol = true; 1148 break; 1149 } 1150 } 1151 for (j = zcr_len / 4; j >= 0; j--) { 1152 int digits; 1153 if (j * 4 + 4 <= zcr_len + 1) { 1154 digits = 16; 1155 } else { 1156 digits = (zcr_len % 4 + 1) * 4; 1157 } 1158 qemu_fprintf(f, "%0*" PRIx64 "%s", digits, 1159 env->vfp.pregs[i].p[j], 1160 j ? ":" : eol ? "\n" : " "); 1161 } 1162 } 1163 1164 if (zcr_len == 0) { 1165 /* 1166 * With vl=16, there are only 37 columns per register, 1167 * so output two registers per line. 1168 */ 1169 for (i = 0; i < 32; i++) { 1170 qemu_fprintf(f, "Z%02d=%016" PRIx64 ":%016" PRIx64 "%s", 1171 i, env->vfp.zregs[i].d[1], 1172 env->vfp.zregs[i].d[0], i & 1 ? "\n" : " "); 1173 } 1174 } else { 1175 for (i = 0; i < 32; i++) { 1176 qemu_fprintf(f, "Z%02d=", i); 1177 for (j = zcr_len; j >= 0; j--) { 1178 qemu_fprintf(f, "%016" PRIx64 ":%016" PRIx64 "%s", 1179 env->vfp.zregs[i].d[j * 2 + 1], 1180 env->vfp.zregs[i].d[j * 2 + 0], 1181 j ? ":" : "\n"); 1182 } 1183 } 1184 } 1185 } else { 1186 for (i = 0; i < 32; i++) { 1187 uint64_t *q = aa64_vfp_qreg(env, i); 1188 qemu_fprintf(f, "Q%02d=%016" PRIx64 ":%016" PRIx64 "%s", 1189 i, q[1], q[0], (i & 1 ? "\n" : " ")); 1190 } 1191 } 1192 1193 if (cpu_isar_feature(aa64_sme, cpu) && 1194 FIELD_EX64(env->svcr, SVCR, ZA) && 1195 sme_exception_el(env, el) == 0) { 1196 int zcr_len = sve_vqm1_for_el_sm(env, el, true); 1197 int svl = (zcr_len + 1) * 16; 1198 int svl_lg10 = svl < 100 ? 2 : 3; 1199 1200 for (i = 0; i < svl; i++) { 1201 qemu_fprintf(f, "ZA[%0*d]=", svl_lg10, i); 1202 for (j = zcr_len; j >= 0; --j) { 1203 qemu_fprintf(f, "%016" PRIx64 ":%016" PRIx64 "%c", 1204 env->zarray[i].d[2 * j + 1], 1205 env->zarray[i].d[2 * j], 1206 j ? ':' : '\n'); 1207 } 1208 } 1209 } 1210 } 1211 1212 #else 1213 1214 static inline void aarch64_cpu_dump_state(CPUState *cs, FILE *f, int flags) 1215 { 1216 g_assert_not_reached(); 1217 } 1218 1219 #endif 1220 1221 static void arm_cpu_dump_state(CPUState *cs, FILE *f, int flags) 1222 { 1223 ARMCPU *cpu = ARM_CPU(cs); 1224 CPUARMState *env = &cpu->env; 1225 int i; 1226 1227 if (is_a64(env)) { 1228 aarch64_cpu_dump_state(cs, f, flags); 1229 return; 1230 } 1231 1232 for (i = 0; i < 16; i++) { 1233 qemu_fprintf(f, "R%02d=%08x", i, env->regs[i]); 1234 if ((i % 4) == 3) { 1235 qemu_fprintf(f, "\n"); 1236 } else { 1237 qemu_fprintf(f, " "); 1238 } 1239 } 1240 1241 if (arm_feature(env, ARM_FEATURE_M)) { 1242 uint32_t xpsr = xpsr_read(env); 1243 const char *mode; 1244 const char *ns_status = ""; 1245 1246 if (arm_feature(env, ARM_FEATURE_M_SECURITY)) { 1247 ns_status = env->v7m.secure ? "S " : "NS "; 1248 } 1249 1250 if (xpsr & XPSR_EXCP) { 1251 mode = "handler"; 1252 } else { 1253 if (env->v7m.control[env->v7m.secure] & R_V7M_CONTROL_NPRIV_MASK) { 1254 mode = "unpriv-thread"; 1255 } else { 1256 mode = "priv-thread"; 1257 } 1258 } 1259 1260 qemu_fprintf(f, "XPSR=%08x %c%c%c%c %c %s%s\n", 1261 xpsr, 1262 xpsr & XPSR_N ? 'N' : '-', 1263 xpsr & XPSR_Z ? 'Z' : '-', 1264 xpsr & XPSR_C ? 'C' : '-', 1265 xpsr & XPSR_V ? 'V' : '-', 1266 xpsr & XPSR_T ? 'T' : 'A', 1267 ns_status, 1268 mode); 1269 } else { 1270 uint32_t psr = cpsr_read(env); 1271 const char *ns_status = ""; 1272 1273 if (arm_feature(env, ARM_FEATURE_EL3) && 1274 (psr & CPSR_M) != ARM_CPU_MODE_MON) { 1275 ns_status = env->cp15.scr_el3 & SCR_NS ? "NS " : "S "; 1276 } 1277 1278 qemu_fprintf(f, "PSR=%08x %c%c%c%c %c %s%s%d\n", 1279 psr, 1280 psr & CPSR_N ? 'N' : '-', 1281 psr & CPSR_Z ? 'Z' : '-', 1282 psr & CPSR_C ? 'C' : '-', 1283 psr & CPSR_V ? 'V' : '-', 1284 psr & CPSR_T ? 'T' : 'A', 1285 ns_status, 1286 aarch32_mode_name(psr), (psr & 0x10) ? 32 : 26); 1287 } 1288 1289 if (flags & CPU_DUMP_FPU) { 1290 int numvfpregs = 0; 1291 if (cpu_isar_feature(aa32_simd_r32, cpu)) { 1292 numvfpregs = 32; 1293 } else if (cpu_isar_feature(aa32_vfp_simd, cpu)) { 1294 numvfpregs = 16; 1295 } 1296 for (i = 0; i < numvfpregs; i++) { 1297 uint64_t v = *aa32_vfp_dreg(env, i); 1298 qemu_fprintf(f, "s%02d=%08x s%02d=%08x d%02d=%016" PRIx64 "\n", 1299 i * 2, (uint32_t)v, 1300 i * 2 + 1, (uint32_t)(v >> 32), 1301 i, v); 1302 } 1303 qemu_fprintf(f, "FPSCR: %08x\n", vfp_get_fpscr(env)); 1304 if (cpu_isar_feature(aa32_mve, cpu)) { 1305 qemu_fprintf(f, "VPR: %08x\n", env->v7m.vpr); 1306 } 1307 } 1308 } 1309 1310 uint64_t arm_build_mp_affinity(int idx, uint8_t clustersz) 1311 { 1312 uint32_t Aff1 = idx / clustersz; 1313 uint32_t Aff0 = idx % clustersz; 1314 return (Aff1 << ARM_AFF1_SHIFT) | Aff0; 1315 } 1316 1317 uint64_t arm_cpu_mp_affinity(ARMCPU *cpu) 1318 { 1319 return cpu->mp_affinity; 1320 } 1321 1322 static void arm_cpu_initfn(Object *obj) 1323 { 1324 ARMCPU *cpu = ARM_CPU(obj); 1325 1326 cpu->cp_regs = g_hash_table_new_full(g_direct_hash, g_direct_equal, 1327 NULL, g_free); 1328 1329 QLIST_INIT(&cpu->pre_el_change_hooks); 1330 QLIST_INIT(&cpu->el_change_hooks); 1331 1332 #ifdef CONFIG_USER_ONLY 1333 # ifdef TARGET_AARCH64 1334 /* 1335 * The linux kernel defaults to 512-bit for SVE, and 256-bit for SME. 1336 * These values were chosen to fit within the default signal frame. 1337 * See documentation for /proc/sys/abi/{sve,sme}_default_vector_length, 1338 * and our corresponding cpu property. 1339 */ 1340 cpu->sve_default_vq = 4; 1341 cpu->sme_default_vq = 2; 1342 # endif 1343 #else 1344 /* Our inbound IRQ and FIQ lines */ 1345 if (kvm_enabled()) { 1346 /* VIRQ and VFIQ are unused with KVM but we add them to maintain 1347 * the same interface as non-KVM CPUs. 1348 */ 1349 qdev_init_gpio_in(DEVICE(cpu), arm_cpu_kvm_set_irq, 4); 1350 } else { 1351 qdev_init_gpio_in(DEVICE(cpu), arm_cpu_set_irq, 4); 1352 } 1353 1354 qdev_init_gpio_out(DEVICE(cpu), cpu->gt_timer_outputs, 1355 ARRAY_SIZE(cpu->gt_timer_outputs)); 1356 1357 qdev_init_gpio_out_named(DEVICE(cpu), &cpu->gicv3_maintenance_interrupt, 1358 "gicv3-maintenance-interrupt", 1); 1359 qdev_init_gpio_out_named(DEVICE(cpu), &cpu->pmu_interrupt, 1360 "pmu-interrupt", 1); 1361 #endif 1362 1363 /* DTB consumers generally don't in fact care what the 'compatible' 1364 * string is, so always provide some string and trust that a hypothetical 1365 * picky DTB consumer will also provide a helpful error message. 1366 */ 1367 cpu->dtb_compatible = "qemu,unknown"; 1368 cpu->psci_version = QEMU_PSCI_VERSION_0_1; /* By default assume PSCI v0.1 */ 1369 cpu->kvm_target = QEMU_KVM_ARM_TARGET_NONE; 1370 1371 if (tcg_enabled() || hvf_enabled()) { 1372 /* TCG and HVF implement PSCI 1.1 */ 1373 cpu->psci_version = QEMU_PSCI_VERSION_1_1; 1374 } 1375 } 1376 1377 static Property arm_cpu_gt_cntfrq_property = 1378 DEFINE_PROP_UINT64("cntfrq", ARMCPU, gt_cntfrq_hz, 1379 NANOSECONDS_PER_SECOND / GTIMER_SCALE); 1380 1381 static Property arm_cpu_reset_cbar_property = 1382 DEFINE_PROP_UINT64("reset-cbar", ARMCPU, reset_cbar, 0); 1383 1384 static Property arm_cpu_reset_hivecs_property = 1385 DEFINE_PROP_BOOL("reset-hivecs", ARMCPU, reset_hivecs, false); 1386 1387 #ifndef CONFIG_USER_ONLY 1388 static Property arm_cpu_has_el2_property = 1389 DEFINE_PROP_BOOL("has_el2", ARMCPU, has_el2, true); 1390 1391 static Property arm_cpu_has_el3_property = 1392 DEFINE_PROP_BOOL("has_el3", ARMCPU, has_el3, true); 1393 #endif 1394 1395 static Property arm_cpu_cfgend_property = 1396 DEFINE_PROP_BOOL("cfgend", ARMCPU, cfgend, false); 1397 1398 static Property arm_cpu_has_vfp_property = 1399 DEFINE_PROP_BOOL("vfp", ARMCPU, has_vfp, true); 1400 1401 static Property arm_cpu_has_vfp_d32_property = 1402 DEFINE_PROP_BOOL("vfp-d32", ARMCPU, has_vfp_d32, true); 1403 1404 static Property arm_cpu_has_neon_property = 1405 DEFINE_PROP_BOOL("neon", ARMCPU, has_neon, true); 1406 1407 static Property arm_cpu_has_dsp_property = 1408 DEFINE_PROP_BOOL("dsp", ARMCPU, has_dsp, true); 1409 1410 static Property arm_cpu_has_mpu_property = 1411 DEFINE_PROP_BOOL("has-mpu", ARMCPU, has_mpu, true); 1412 1413 /* This is like DEFINE_PROP_UINT32 but it doesn't set the default value, 1414 * because the CPU initfn will have already set cpu->pmsav7_dregion to 1415 * the right value for that particular CPU type, and we don't want 1416 * to override that with an incorrect constant value. 1417 */ 1418 static Property arm_cpu_pmsav7_dregion_property = 1419 DEFINE_PROP_UNSIGNED_NODEFAULT("pmsav7-dregion", ARMCPU, 1420 pmsav7_dregion, 1421 qdev_prop_uint32, uint32_t); 1422 1423 static bool arm_get_pmu(Object *obj, Error **errp) 1424 { 1425 ARMCPU *cpu = ARM_CPU(obj); 1426 1427 return cpu->has_pmu; 1428 } 1429 1430 static void arm_set_pmu(Object *obj, bool value, Error **errp) 1431 { 1432 ARMCPU *cpu = ARM_CPU(obj); 1433 1434 if (value) { 1435 if (kvm_enabled() && !kvm_arm_pmu_supported()) { 1436 error_setg(errp, "'pmu' feature not supported by KVM on this host"); 1437 return; 1438 } 1439 set_feature(&cpu->env, ARM_FEATURE_PMU); 1440 } else { 1441 unset_feature(&cpu->env, ARM_FEATURE_PMU); 1442 } 1443 cpu->has_pmu = value; 1444 } 1445 1446 unsigned int gt_cntfrq_period_ns(ARMCPU *cpu) 1447 { 1448 /* 1449 * The exact approach to calculating guest ticks is: 1450 * 1451 * muldiv64(qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL), cpu->gt_cntfrq_hz, 1452 * NANOSECONDS_PER_SECOND); 1453 * 1454 * We don't do that. Rather we intentionally use integer division 1455 * truncation below and in the caller for the conversion of host monotonic 1456 * time to guest ticks to provide the exact inverse for the semantics of 1457 * the QEMUTimer scale factor. QEMUTimer's scale facter is an integer, so 1458 * it loses precision when representing frequencies where 1459 * `(NANOSECONDS_PER_SECOND % cpu->gt_cntfrq) > 0` holds. Failing to 1460 * provide an exact inverse leads to scheduling timers with negative 1461 * periods, which in turn leads to sticky behaviour in the guest. 1462 * 1463 * Finally, CNTFRQ is effectively capped at 1GHz to ensure our scale factor 1464 * cannot become zero. 1465 */ 1466 return NANOSECONDS_PER_SECOND > cpu->gt_cntfrq_hz ? 1467 NANOSECONDS_PER_SECOND / cpu->gt_cntfrq_hz : 1; 1468 } 1469 1470 static void arm_cpu_propagate_feature_implications(ARMCPU *cpu) 1471 { 1472 CPUARMState *env = &cpu->env; 1473 bool no_aa32 = false; 1474 1475 /* 1476 * Some features automatically imply others: set the feature 1477 * bits explicitly for these cases. 1478 */ 1479 1480 if (arm_feature(env, ARM_FEATURE_M)) { 1481 set_feature(env, ARM_FEATURE_PMSA); 1482 } 1483 1484 if (arm_feature(env, ARM_FEATURE_V8)) { 1485 if (arm_feature(env, ARM_FEATURE_M)) { 1486 set_feature(env, ARM_FEATURE_V7); 1487 } else { 1488 set_feature(env, ARM_FEATURE_V7VE); 1489 } 1490 } 1491 1492 /* 1493 * There exist AArch64 cpus without AArch32 support. When KVM 1494 * queries ID_ISAR0_EL1 on such a host, the value is UNKNOWN. 1495 * Similarly, we cannot check ID_AA64PFR0 without AArch64 support. 1496 * As a general principle, we also do not make ID register 1497 * consistency checks anywhere unless using TCG, because only 1498 * for TCG would a consistency-check failure be a QEMU bug. 1499 */ 1500 if (arm_feature(&cpu->env, ARM_FEATURE_AARCH64)) { 1501 no_aa32 = !cpu_isar_feature(aa64_aa32, cpu); 1502 } 1503 1504 if (arm_feature(env, ARM_FEATURE_V7VE)) { 1505 /* 1506 * v7 Virtualization Extensions. In real hardware this implies 1507 * EL2 and also the presence of the Security Extensions. 1508 * For QEMU, for backwards-compatibility we implement some 1509 * CPUs or CPU configs which have no actual EL2 or EL3 but do 1510 * include the various other features that V7VE implies. 1511 * Presence of EL2 itself is ARM_FEATURE_EL2, and of the 1512 * Security Extensions is ARM_FEATURE_EL3. 1513 */ 1514 assert(!tcg_enabled() || no_aa32 || 1515 cpu_isar_feature(aa32_arm_div, cpu)); 1516 set_feature(env, ARM_FEATURE_LPAE); 1517 set_feature(env, ARM_FEATURE_V7); 1518 } 1519 if (arm_feature(env, ARM_FEATURE_V7)) { 1520 set_feature(env, ARM_FEATURE_VAPA); 1521 set_feature(env, ARM_FEATURE_THUMB2); 1522 set_feature(env, ARM_FEATURE_MPIDR); 1523 if (!arm_feature(env, ARM_FEATURE_M)) { 1524 set_feature(env, ARM_FEATURE_V6K); 1525 } else { 1526 set_feature(env, ARM_FEATURE_V6); 1527 } 1528 1529 /* 1530 * Always define VBAR for V7 CPUs even if it doesn't exist in 1531 * non-EL3 configs. This is needed by some legacy boards. 1532 */ 1533 set_feature(env, ARM_FEATURE_VBAR); 1534 } 1535 if (arm_feature(env, ARM_FEATURE_V6K)) { 1536 set_feature(env, ARM_FEATURE_V6); 1537 set_feature(env, ARM_FEATURE_MVFR); 1538 } 1539 if (arm_feature(env, ARM_FEATURE_V6)) { 1540 set_feature(env, ARM_FEATURE_V5); 1541 if (!arm_feature(env, ARM_FEATURE_M)) { 1542 assert(!tcg_enabled() || no_aa32 || 1543 cpu_isar_feature(aa32_jazelle, cpu)); 1544 set_feature(env, ARM_FEATURE_AUXCR); 1545 } 1546 } 1547 if (arm_feature(env, ARM_FEATURE_V5)) { 1548 set_feature(env, ARM_FEATURE_V4T); 1549 } 1550 if (arm_feature(env, ARM_FEATURE_LPAE)) { 1551 set_feature(env, ARM_FEATURE_V7MP); 1552 } 1553 if (arm_feature(env, ARM_FEATURE_CBAR_RO)) { 1554 set_feature(env, ARM_FEATURE_CBAR); 1555 } 1556 if (arm_feature(env, ARM_FEATURE_THUMB2) && 1557 !arm_feature(env, ARM_FEATURE_M)) { 1558 set_feature(env, ARM_FEATURE_THUMB_DSP); 1559 } 1560 } 1561 1562 void arm_cpu_post_init(Object *obj) 1563 { 1564 ARMCPU *cpu = ARM_CPU(obj); 1565 1566 /* 1567 * Some features imply others. Figure this out now, because we 1568 * are going to look at the feature bits in deciding which 1569 * properties to add. 1570 */ 1571 arm_cpu_propagate_feature_implications(cpu); 1572 1573 if (arm_feature(&cpu->env, ARM_FEATURE_CBAR) || 1574 arm_feature(&cpu->env, ARM_FEATURE_CBAR_RO)) { 1575 qdev_property_add_static(DEVICE(obj), &arm_cpu_reset_cbar_property); 1576 } 1577 1578 if (!arm_feature(&cpu->env, ARM_FEATURE_M)) { 1579 qdev_property_add_static(DEVICE(obj), &arm_cpu_reset_hivecs_property); 1580 } 1581 1582 if (arm_feature(&cpu->env, ARM_FEATURE_V8)) { 1583 object_property_add_uint64_ptr(obj, "rvbar", 1584 &cpu->rvbar_prop, 1585 OBJ_PROP_FLAG_READWRITE); 1586 } 1587 1588 #ifndef CONFIG_USER_ONLY 1589 if (arm_feature(&cpu->env, ARM_FEATURE_EL3)) { 1590 /* Add the has_el3 state CPU property only if EL3 is allowed. This will 1591 * prevent "has_el3" from existing on CPUs which cannot support EL3. 1592 */ 1593 qdev_property_add_static(DEVICE(obj), &arm_cpu_has_el3_property); 1594 1595 object_property_add_link(obj, "secure-memory", 1596 TYPE_MEMORY_REGION, 1597 (Object **)&cpu->secure_memory, 1598 qdev_prop_allow_set_link_before_realize, 1599 OBJ_PROP_LINK_STRONG); 1600 } 1601 1602 if (arm_feature(&cpu->env, ARM_FEATURE_EL2)) { 1603 qdev_property_add_static(DEVICE(obj), &arm_cpu_has_el2_property); 1604 } 1605 #endif 1606 1607 if (arm_feature(&cpu->env, ARM_FEATURE_PMU)) { 1608 cpu->has_pmu = true; 1609 object_property_add_bool(obj, "pmu", arm_get_pmu, arm_set_pmu); 1610 } 1611 1612 /* 1613 * Allow user to turn off VFP and Neon support, but only for TCG -- 1614 * KVM does not currently allow us to lie to the guest about its 1615 * ID/feature registers, so the guest always sees what the host has. 1616 */ 1617 if (arm_feature(&cpu->env, ARM_FEATURE_AARCH64)) { 1618 if (cpu_isar_feature(aa64_fp_simd, cpu)) { 1619 cpu->has_vfp = true; 1620 cpu->has_vfp_d32 = true; 1621 if (tcg_enabled() || qtest_enabled()) { 1622 qdev_property_add_static(DEVICE(obj), 1623 &arm_cpu_has_vfp_property); 1624 } 1625 } 1626 } else if (cpu_isar_feature(aa32_vfp, cpu)) { 1627 cpu->has_vfp = true; 1628 if (cpu_isar_feature(aa32_simd_r32, cpu)) { 1629 cpu->has_vfp_d32 = true; 1630 /* 1631 * The permitted values of the SIMDReg bits [3:0] on 1632 * Armv8-A are either 0b0000 and 0b0010. On such CPUs, 1633 * make sure that has_vfp_d32 can not be set to false. 1634 */ 1635 if ((tcg_enabled() || qtest_enabled()) 1636 && !(arm_feature(&cpu->env, ARM_FEATURE_V8) 1637 && !arm_feature(&cpu->env, ARM_FEATURE_M))) { 1638 qdev_property_add_static(DEVICE(obj), 1639 &arm_cpu_has_vfp_d32_property); 1640 } 1641 } 1642 } 1643 1644 if (arm_feature(&cpu->env, ARM_FEATURE_NEON)) { 1645 cpu->has_neon = true; 1646 if (!kvm_enabled()) { 1647 qdev_property_add_static(DEVICE(obj), &arm_cpu_has_neon_property); 1648 } 1649 } 1650 1651 if (arm_feature(&cpu->env, ARM_FEATURE_M) && 1652 arm_feature(&cpu->env, ARM_FEATURE_THUMB_DSP)) { 1653 qdev_property_add_static(DEVICE(obj), &arm_cpu_has_dsp_property); 1654 } 1655 1656 if (arm_feature(&cpu->env, ARM_FEATURE_PMSA)) { 1657 qdev_property_add_static(DEVICE(obj), &arm_cpu_has_mpu_property); 1658 if (arm_feature(&cpu->env, ARM_FEATURE_V7)) { 1659 qdev_property_add_static(DEVICE(obj), 1660 &arm_cpu_pmsav7_dregion_property); 1661 } 1662 } 1663 1664 if (arm_feature(&cpu->env, ARM_FEATURE_M_SECURITY)) { 1665 object_property_add_link(obj, "idau", TYPE_IDAU_INTERFACE, &cpu->idau, 1666 qdev_prop_allow_set_link_before_realize, 1667 OBJ_PROP_LINK_STRONG); 1668 /* 1669 * M profile: initial value of the Secure VTOR. We can't just use 1670 * a simple DEFINE_PROP_UINT32 for this because we want to permit 1671 * the property to be set after realize. 1672 */ 1673 object_property_add_uint32_ptr(obj, "init-svtor", 1674 &cpu->init_svtor, 1675 OBJ_PROP_FLAG_READWRITE); 1676 } 1677 if (arm_feature(&cpu->env, ARM_FEATURE_M)) { 1678 /* 1679 * Initial value of the NS VTOR (for cores without the Security 1680 * extension, this is the only VTOR) 1681 */ 1682 object_property_add_uint32_ptr(obj, "init-nsvtor", 1683 &cpu->init_nsvtor, 1684 OBJ_PROP_FLAG_READWRITE); 1685 } 1686 1687 /* Not DEFINE_PROP_UINT32: we want this to be settable after realize */ 1688 object_property_add_uint32_ptr(obj, "psci-conduit", 1689 &cpu->psci_conduit, 1690 OBJ_PROP_FLAG_READWRITE); 1691 1692 qdev_property_add_static(DEVICE(obj), &arm_cpu_cfgend_property); 1693 1694 if (arm_feature(&cpu->env, ARM_FEATURE_GENERIC_TIMER)) { 1695 qdev_property_add_static(DEVICE(cpu), &arm_cpu_gt_cntfrq_property); 1696 } 1697 1698 if (kvm_enabled()) { 1699 kvm_arm_add_vcpu_properties(cpu); 1700 } 1701 1702 #ifndef CONFIG_USER_ONLY 1703 if (arm_feature(&cpu->env, ARM_FEATURE_AARCH64) && 1704 cpu_isar_feature(aa64_mte, cpu)) { 1705 object_property_add_link(obj, "tag-memory", 1706 TYPE_MEMORY_REGION, 1707 (Object **)&cpu->tag_memory, 1708 qdev_prop_allow_set_link_before_realize, 1709 OBJ_PROP_LINK_STRONG); 1710 1711 if (arm_feature(&cpu->env, ARM_FEATURE_EL3)) { 1712 object_property_add_link(obj, "secure-tag-memory", 1713 TYPE_MEMORY_REGION, 1714 (Object **)&cpu->secure_tag_memory, 1715 qdev_prop_allow_set_link_before_realize, 1716 OBJ_PROP_LINK_STRONG); 1717 } 1718 } 1719 #endif 1720 } 1721 1722 static void arm_cpu_finalizefn(Object *obj) 1723 { 1724 ARMCPU *cpu = ARM_CPU(obj); 1725 ARMELChangeHook *hook, *next; 1726 1727 g_hash_table_destroy(cpu->cp_regs); 1728 1729 QLIST_FOREACH_SAFE(hook, &cpu->pre_el_change_hooks, node, next) { 1730 QLIST_REMOVE(hook, node); 1731 g_free(hook); 1732 } 1733 QLIST_FOREACH_SAFE(hook, &cpu->el_change_hooks, node, next) { 1734 QLIST_REMOVE(hook, node); 1735 g_free(hook); 1736 } 1737 #ifndef CONFIG_USER_ONLY 1738 if (cpu->pmu_timer) { 1739 timer_free(cpu->pmu_timer); 1740 } 1741 #endif 1742 } 1743 1744 void arm_cpu_finalize_features(ARMCPU *cpu, Error **errp) 1745 { 1746 Error *local_err = NULL; 1747 1748 #ifdef TARGET_AARCH64 1749 if (arm_feature(&cpu->env, ARM_FEATURE_AARCH64)) { 1750 arm_cpu_sve_finalize(cpu, &local_err); 1751 if (local_err != NULL) { 1752 error_propagate(errp, local_err); 1753 return; 1754 } 1755 1756 /* 1757 * FEAT_SME is not architecturally dependent on FEAT_SVE (unless 1758 * FEAT_SME_FA64 is present). However our implementation currently 1759 * assumes it, so if the user asked for sve=off then turn off SME also. 1760 * (KVM doesn't currently support SME at all.) 1761 */ 1762 if (cpu_isar_feature(aa64_sme, cpu) && !cpu_isar_feature(aa64_sve, cpu)) { 1763 object_property_set_bool(OBJECT(cpu), "sme", false, &error_abort); 1764 } 1765 1766 arm_cpu_sme_finalize(cpu, &local_err); 1767 if (local_err != NULL) { 1768 error_propagate(errp, local_err); 1769 return; 1770 } 1771 1772 arm_cpu_pauth_finalize(cpu, &local_err); 1773 if (local_err != NULL) { 1774 error_propagate(errp, local_err); 1775 return; 1776 } 1777 1778 arm_cpu_lpa2_finalize(cpu, &local_err); 1779 if (local_err != NULL) { 1780 error_propagate(errp, local_err); 1781 return; 1782 } 1783 } 1784 #endif 1785 1786 if (kvm_enabled()) { 1787 kvm_arm_steal_time_finalize(cpu, &local_err); 1788 if (local_err != NULL) { 1789 error_propagate(errp, local_err); 1790 return; 1791 } 1792 } 1793 } 1794 1795 static void arm_cpu_realizefn(DeviceState *dev, Error **errp) 1796 { 1797 CPUState *cs = CPU(dev); 1798 ARMCPU *cpu = ARM_CPU(dev); 1799 ARMCPUClass *acc = ARM_CPU_GET_CLASS(dev); 1800 CPUARMState *env = &cpu->env; 1801 int pagebits; 1802 Error *local_err = NULL; 1803 1804 #if defined(CONFIG_TCG) && !defined(CONFIG_USER_ONLY) 1805 /* Use pc-relative instructions in system-mode */ 1806 cs->tcg_cflags |= CF_PCREL; 1807 #endif 1808 1809 /* If we needed to query the host kernel for the CPU features 1810 * then it's possible that might have failed in the initfn, but 1811 * this is the first point where we can report it. 1812 */ 1813 if (cpu->host_cpu_probe_failed) { 1814 if (!kvm_enabled() && !hvf_enabled()) { 1815 error_setg(errp, "The 'host' CPU type can only be used with KVM or HVF"); 1816 } else { 1817 error_setg(errp, "Failed to retrieve host CPU features"); 1818 } 1819 return; 1820 } 1821 1822 #ifndef CONFIG_USER_ONLY 1823 /* The NVIC and M-profile CPU are two halves of a single piece of 1824 * hardware; trying to use one without the other is a command line 1825 * error and will result in segfaults if not caught here. 1826 */ 1827 if (arm_feature(env, ARM_FEATURE_M)) { 1828 if (!env->nvic) { 1829 error_setg(errp, "This board cannot be used with Cortex-M CPUs"); 1830 return; 1831 } 1832 } else { 1833 if (env->nvic) { 1834 error_setg(errp, "This board can only be used with Cortex-M CPUs"); 1835 return; 1836 } 1837 } 1838 1839 if (!tcg_enabled() && !qtest_enabled()) { 1840 /* 1841 * We assume that no accelerator except TCG (and the "not really an 1842 * accelerator" qtest) can handle these features, because Arm hardware 1843 * virtualization can't virtualize them. 1844 * 1845 * Catch all the cases which might cause us to create more than one 1846 * address space for the CPU (otherwise we will assert() later in 1847 * cpu_address_space_init()). 1848 */ 1849 if (arm_feature(env, ARM_FEATURE_M)) { 1850 error_setg(errp, 1851 "Cannot enable %s when using an M-profile guest CPU", 1852 current_accel_name()); 1853 return; 1854 } 1855 if (cpu->has_el3) { 1856 error_setg(errp, 1857 "Cannot enable %s when guest CPU has EL3 enabled", 1858 current_accel_name()); 1859 return; 1860 } 1861 if (cpu->tag_memory) { 1862 error_setg(errp, 1863 "Cannot enable %s when guest CPUs has MTE enabled", 1864 current_accel_name()); 1865 return; 1866 } 1867 } 1868 1869 { 1870 uint64_t scale; 1871 1872 if (arm_feature(env, ARM_FEATURE_GENERIC_TIMER)) { 1873 if (!cpu->gt_cntfrq_hz) { 1874 error_setg(errp, "Invalid CNTFRQ: %"PRId64"Hz", 1875 cpu->gt_cntfrq_hz); 1876 return; 1877 } 1878 scale = gt_cntfrq_period_ns(cpu); 1879 } else { 1880 scale = GTIMER_SCALE; 1881 } 1882 1883 cpu->gt_timer[GTIMER_PHYS] = timer_new(QEMU_CLOCK_VIRTUAL, scale, 1884 arm_gt_ptimer_cb, cpu); 1885 cpu->gt_timer[GTIMER_VIRT] = timer_new(QEMU_CLOCK_VIRTUAL, scale, 1886 arm_gt_vtimer_cb, cpu); 1887 cpu->gt_timer[GTIMER_HYP] = timer_new(QEMU_CLOCK_VIRTUAL, scale, 1888 arm_gt_htimer_cb, cpu); 1889 cpu->gt_timer[GTIMER_SEC] = timer_new(QEMU_CLOCK_VIRTUAL, scale, 1890 arm_gt_stimer_cb, cpu); 1891 cpu->gt_timer[GTIMER_HYPVIRT] = timer_new(QEMU_CLOCK_VIRTUAL, scale, 1892 arm_gt_hvtimer_cb, cpu); 1893 } 1894 #endif 1895 1896 cpu_exec_realizefn(cs, &local_err); 1897 if (local_err != NULL) { 1898 error_propagate(errp, local_err); 1899 return; 1900 } 1901 1902 arm_cpu_finalize_features(cpu, &local_err); 1903 if (local_err != NULL) { 1904 error_propagate(errp, local_err); 1905 return; 1906 } 1907 1908 #ifdef CONFIG_USER_ONLY 1909 /* 1910 * User mode relies on IC IVAU instructions to catch modification of 1911 * dual-mapped code. 1912 * 1913 * Clear CTR_EL0.DIC to ensure that software that honors these flags uses 1914 * IC IVAU even if the emulated processor does not normally require it. 1915 */ 1916 cpu->ctr = FIELD_DP64(cpu->ctr, CTR_EL0, DIC, 0); 1917 #endif 1918 1919 if (arm_feature(env, ARM_FEATURE_AARCH64) && 1920 cpu->has_vfp != cpu->has_neon) { 1921 /* 1922 * This is an architectural requirement for AArch64; AArch32 is 1923 * more flexible and permits VFP-no-Neon and Neon-no-VFP. 1924 */ 1925 error_setg(errp, 1926 "AArch64 CPUs must have both VFP and Neon or neither"); 1927 return; 1928 } 1929 1930 if (cpu->has_vfp_d32 != cpu->has_neon) { 1931 error_setg(errp, "ARM CPUs must have both VFP-D32 and Neon or neither"); 1932 return; 1933 } 1934 1935 if (!cpu->has_vfp_d32) { 1936 uint32_t u; 1937 1938 u = cpu->isar.mvfr0; 1939 u = FIELD_DP32(u, MVFR0, SIMDREG, 1); /* 16 registers */ 1940 cpu->isar.mvfr0 = u; 1941 } 1942 1943 if (!cpu->has_vfp) { 1944 uint64_t t; 1945 uint32_t u; 1946 1947 t = cpu->isar.id_aa64isar1; 1948 t = FIELD_DP64(t, ID_AA64ISAR1, JSCVT, 0); 1949 cpu->isar.id_aa64isar1 = t; 1950 1951 t = cpu->isar.id_aa64pfr0; 1952 t = FIELD_DP64(t, ID_AA64PFR0, FP, 0xf); 1953 cpu->isar.id_aa64pfr0 = t; 1954 1955 u = cpu->isar.id_isar6; 1956 u = FIELD_DP32(u, ID_ISAR6, JSCVT, 0); 1957 u = FIELD_DP32(u, ID_ISAR6, BF16, 0); 1958 cpu->isar.id_isar6 = u; 1959 1960 u = cpu->isar.mvfr0; 1961 u = FIELD_DP32(u, MVFR0, FPSP, 0); 1962 u = FIELD_DP32(u, MVFR0, FPDP, 0); 1963 u = FIELD_DP32(u, MVFR0, FPDIVIDE, 0); 1964 u = FIELD_DP32(u, MVFR0, FPSQRT, 0); 1965 u = FIELD_DP32(u, MVFR0, FPROUND, 0); 1966 if (!arm_feature(env, ARM_FEATURE_M)) { 1967 u = FIELD_DP32(u, MVFR0, FPTRAP, 0); 1968 u = FIELD_DP32(u, MVFR0, FPSHVEC, 0); 1969 } 1970 cpu->isar.mvfr0 = u; 1971 1972 u = cpu->isar.mvfr1; 1973 u = FIELD_DP32(u, MVFR1, FPFTZ, 0); 1974 u = FIELD_DP32(u, MVFR1, FPDNAN, 0); 1975 u = FIELD_DP32(u, MVFR1, FPHP, 0); 1976 if (arm_feature(env, ARM_FEATURE_M)) { 1977 u = FIELD_DP32(u, MVFR1, FP16, 0); 1978 } 1979 cpu->isar.mvfr1 = u; 1980 1981 u = cpu->isar.mvfr2; 1982 u = FIELD_DP32(u, MVFR2, FPMISC, 0); 1983 cpu->isar.mvfr2 = u; 1984 } 1985 1986 if (!cpu->has_neon) { 1987 uint64_t t; 1988 uint32_t u; 1989 1990 unset_feature(env, ARM_FEATURE_NEON); 1991 1992 t = cpu->isar.id_aa64isar0; 1993 t = FIELD_DP64(t, ID_AA64ISAR0, AES, 0); 1994 t = FIELD_DP64(t, ID_AA64ISAR0, SHA1, 0); 1995 t = FIELD_DP64(t, ID_AA64ISAR0, SHA2, 0); 1996 t = FIELD_DP64(t, ID_AA64ISAR0, SHA3, 0); 1997 t = FIELD_DP64(t, ID_AA64ISAR0, SM3, 0); 1998 t = FIELD_DP64(t, ID_AA64ISAR0, SM4, 0); 1999 t = FIELD_DP64(t, ID_AA64ISAR0, DP, 0); 2000 cpu->isar.id_aa64isar0 = t; 2001 2002 t = cpu->isar.id_aa64isar1; 2003 t = FIELD_DP64(t, ID_AA64ISAR1, FCMA, 0); 2004 t = FIELD_DP64(t, ID_AA64ISAR1, BF16, 0); 2005 t = FIELD_DP64(t, ID_AA64ISAR1, I8MM, 0); 2006 cpu->isar.id_aa64isar1 = t; 2007 2008 t = cpu->isar.id_aa64pfr0; 2009 t = FIELD_DP64(t, ID_AA64PFR0, ADVSIMD, 0xf); 2010 cpu->isar.id_aa64pfr0 = t; 2011 2012 u = cpu->isar.id_isar5; 2013 u = FIELD_DP32(u, ID_ISAR5, AES, 0); 2014 u = FIELD_DP32(u, ID_ISAR5, SHA1, 0); 2015 u = FIELD_DP32(u, ID_ISAR5, SHA2, 0); 2016 u = FIELD_DP32(u, ID_ISAR5, RDM, 0); 2017 u = FIELD_DP32(u, ID_ISAR5, VCMA, 0); 2018 cpu->isar.id_isar5 = u; 2019 2020 u = cpu->isar.id_isar6; 2021 u = FIELD_DP32(u, ID_ISAR6, DP, 0); 2022 u = FIELD_DP32(u, ID_ISAR6, FHM, 0); 2023 u = FIELD_DP32(u, ID_ISAR6, BF16, 0); 2024 u = FIELD_DP32(u, ID_ISAR6, I8MM, 0); 2025 cpu->isar.id_isar6 = u; 2026 2027 if (!arm_feature(env, ARM_FEATURE_M)) { 2028 u = cpu->isar.mvfr1; 2029 u = FIELD_DP32(u, MVFR1, SIMDLS, 0); 2030 u = FIELD_DP32(u, MVFR1, SIMDINT, 0); 2031 u = FIELD_DP32(u, MVFR1, SIMDSP, 0); 2032 u = FIELD_DP32(u, MVFR1, SIMDHP, 0); 2033 cpu->isar.mvfr1 = u; 2034 2035 u = cpu->isar.mvfr2; 2036 u = FIELD_DP32(u, MVFR2, SIMDMISC, 0); 2037 cpu->isar.mvfr2 = u; 2038 } 2039 } 2040 2041 if (!cpu->has_neon && !cpu->has_vfp) { 2042 uint64_t t; 2043 uint32_t u; 2044 2045 t = cpu->isar.id_aa64isar0; 2046 t = FIELD_DP64(t, ID_AA64ISAR0, FHM, 0); 2047 cpu->isar.id_aa64isar0 = t; 2048 2049 t = cpu->isar.id_aa64isar1; 2050 t = FIELD_DP64(t, ID_AA64ISAR1, FRINTTS, 0); 2051 cpu->isar.id_aa64isar1 = t; 2052 2053 u = cpu->isar.mvfr0; 2054 u = FIELD_DP32(u, MVFR0, SIMDREG, 0); 2055 cpu->isar.mvfr0 = u; 2056 2057 /* Despite the name, this field covers both VFP and Neon */ 2058 u = cpu->isar.mvfr1; 2059 u = FIELD_DP32(u, MVFR1, SIMDFMAC, 0); 2060 cpu->isar.mvfr1 = u; 2061 } 2062 2063 if (arm_feature(env, ARM_FEATURE_M) && !cpu->has_dsp) { 2064 uint32_t u; 2065 2066 unset_feature(env, ARM_FEATURE_THUMB_DSP); 2067 2068 u = cpu->isar.id_isar1; 2069 u = FIELD_DP32(u, ID_ISAR1, EXTEND, 1); 2070 cpu->isar.id_isar1 = u; 2071 2072 u = cpu->isar.id_isar2; 2073 u = FIELD_DP32(u, ID_ISAR2, MULTU, 1); 2074 u = FIELD_DP32(u, ID_ISAR2, MULTS, 1); 2075 cpu->isar.id_isar2 = u; 2076 2077 u = cpu->isar.id_isar3; 2078 u = FIELD_DP32(u, ID_ISAR3, SIMD, 1); 2079 u = FIELD_DP32(u, ID_ISAR3, SATURATE, 0); 2080 cpu->isar.id_isar3 = u; 2081 } 2082 2083 2084 /* 2085 * We rely on no XScale CPU having VFP so we can use the same bits in the 2086 * TB flags field for VECSTRIDE and XSCALE_CPAR. 2087 */ 2088 assert(arm_feature(&cpu->env, ARM_FEATURE_AARCH64) || 2089 !cpu_isar_feature(aa32_vfp_simd, cpu) || 2090 !arm_feature(env, ARM_FEATURE_XSCALE)); 2091 2092 if (arm_feature(env, ARM_FEATURE_V7) && 2093 !arm_feature(env, ARM_FEATURE_M) && 2094 !arm_feature(env, ARM_FEATURE_PMSA)) { 2095 /* v7VMSA drops support for the old ARMv5 tiny pages, so we 2096 * can use 4K pages. 2097 */ 2098 pagebits = 12; 2099 } else { 2100 /* For CPUs which might have tiny 1K pages, or which have an 2101 * MPU and might have small region sizes, stick with 1K pages. 2102 */ 2103 pagebits = 10; 2104 } 2105 if (!set_preferred_target_page_bits(pagebits)) { 2106 /* This can only ever happen for hotplugging a CPU, or if 2107 * the board code incorrectly creates a CPU which it has 2108 * promised via minimum_page_size that it will not. 2109 */ 2110 error_setg(errp, "This CPU requires a smaller page size than the " 2111 "system is using"); 2112 return; 2113 } 2114 2115 /* This cpu-id-to-MPIDR affinity is used only for TCG; KVM will override it. 2116 * We don't support setting cluster ID ([16..23]) (known as Aff2 2117 * in later ARM ARM versions), or any of the higher affinity level fields, 2118 * so these bits always RAZ. 2119 */ 2120 if (cpu->mp_affinity == ARM64_AFFINITY_INVALID) { 2121 cpu->mp_affinity = arm_build_mp_affinity(cs->cpu_index, 2122 ARM_DEFAULT_CPUS_PER_CLUSTER); 2123 } 2124 2125 if (cpu->reset_hivecs) { 2126 cpu->reset_sctlr |= (1 << 13); 2127 } 2128 2129 if (cpu->cfgend) { 2130 if (arm_feature(&cpu->env, ARM_FEATURE_V7)) { 2131 cpu->reset_sctlr |= SCTLR_EE; 2132 } else { 2133 cpu->reset_sctlr |= SCTLR_B; 2134 } 2135 } 2136 2137 if (!arm_feature(env, ARM_FEATURE_M) && !cpu->has_el3) { 2138 /* If the has_el3 CPU property is disabled then we need to disable the 2139 * feature. 2140 */ 2141 unset_feature(env, ARM_FEATURE_EL3); 2142 2143 /* 2144 * Disable the security extension feature bits in the processor 2145 * feature registers as well. 2146 */ 2147 cpu->isar.id_pfr1 = FIELD_DP32(cpu->isar.id_pfr1, ID_PFR1, SECURITY, 0); 2148 cpu->isar.id_dfr0 = FIELD_DP32(cpu->isar.id_dfr0, ID_DFR0, COPSDBG, 0); 2149 cpu->isar.id_aa64pfr0 = FIELD_DP64(cpu->isar.id_aa64pfr0, 2150 ID_AA64PFR0, EL3, 0); 2151 2152 /* Disable the realm management extension, which requires EL3. */ 2153 cpu->isar.id_aa64pfr0 = FIELD_DP64(cpu->isar.id_aa64pfr0, 2154 ID_AA64PFR0, RME, 0); 2155 } 2156 2157 if (!cpu->has_el2) { 2158 unset_feature(env, ARM_FEATURE_EL2); 2159 } 2160 2161 if (!cpu->has_pmu) { 2162 unset_feature(env, ARM_FEATURE_PMU); 2163 } 2164 if (arm_feature(env, ARM_FEATURE_PMU)) { 2165 pmu_init(cpu); 2166 2167 if (!kvm_enabled()) { 2168 arm_register_pre_el_change_hook(cpu, &pmu_pre_el_change, 0); 2169 arm_register_el_change_hook(cpu, &pmu_post_el_change, 0); 2170 } 2171 2172 #ifndef CONFIG_USER_ONLY 2173 cpu->pmu_timer = timer_new_ns(QEMU_CLOCK_VIRTUAL, arm_pmu_timer_cb, 2174 cpu); 2175 #endif 2176 } else { 2177 cpu->isar.id_aa64dfr0 = 2178 FIELD_DP64(cpu->isar.id_aa64dfr0, ID_AA64DFR0, PMUVER, 0); 2179 cpu->isar.id_dfr0 = FIELD_DP32(cpu->isar.id_dfr0, ID_DFR0, PERFMON, 0); 2180 cpu->pmceid0 = 0; 2181 cpu->pmceid1 = 0; 2182 } 2183 2184 if (!arm_feature(env, ARM_FEATURE_EL2)) { 2185 /* 2186 * Disable the hypervisor feature bits in the processor feature 2187 * registers if we don't have EL2. 2188 */ 2189 cpu->isar.id_aa64pfr0 = FIELD_DP64(cpu->isar.id_aa64pfr0, 2190 ID_AA64PFR0, EL2, 0); 2191 cpu->isar.id_pfr1 = FIELD_DP32(cpu->isar.id_pfr1, 2192 ID_PFR1, VIRTUALIZATION, 0); 2193 } 2194 2195 if (cpu_isar_feature(aa64_mte, cpu)) { 2196 /* 2197 * The architectural range of GM blocksize is 2-6, however qemu 2198 * doesn't support blocksize of 2 (see HELPER(ldgm)). 2199 */ 2200 if (tcg_enabled()) { 2201 assert(cpu->gm_blocksize >= 3 && cpu->gm_blocksize <= 6); 2202 } 2203 2204 #ifndef CONFIG_USER_ONLY 2205 /* 2206 * If we do not have tag-memory provided by the machine, 2207 * reduce MTE support to instructions enabled at EL0. 2208 * This matches Cortex-A710 BROADCASTMTE input being LOW. 2209 */ 2210 if (cpu->tag_memory == NULL) { 2211 cpu->isar.id_aa64pfr1 = 2212 FIELD_DP64(cpu->isar.id_aa64pfr1, ID_AA64PFR1, MTE, 1); 2213 } 2214 #endif 2215 } 2216 2217 if (tcg_enabled()) { 2218 /* 2219 * Don't report some architectural features in the ID registers 2220 * where TCG does not yet implement it (not even a minimal 2221 * stub version). This avoids guests falling over when they 2222 * try to access the non-existent system registers for them. 2223 */ 2224 /* FEAT_SPE (Statistical Profiling Extension) */ 2225 cpu->isar.id_aa64dfr0 = 2226 FIELD_DP64(cpu->isar.id_aa64dfr0, ID_AA64DFR0, PMSVER, 0); 2227 /* FEAT_TRBE (Trace Buffer Extension) */ 2228 cpu->isar.id_aa64dfr0 = 2229 FIELD_DP64(cpu->isar.id_aa64dfr0, ID_AA64DFR0, TRACEBUFFER, 0); 2230 /* FEAT_TRF (Self-hosted Trace Extension) */ 2231 cpu->isar.id_aa64dfr0 = 2232 FIELD_DP64(cpu->isar.id_aa64dfr0, ID_AA64DFR0, TRACEFILT, 0); 2233 cpu->isar.id_dfr0 = 2234 FIELD_DP32(cpu->isar.id_dfr0, ID_DFR0, TRACEFILT, 0); 2235 /* Trace Macrocell system register access */ 2236 cpu->isar.id_aa64dfr0 = 2237 FIELD_DP64(cpu->isar.id_aa64dfr0, ID_AA64DFR0, TRACEVER, 0); 2238 cpu->isar.id_dfr0 = 2239 FIELD_DP32(cpu->isar.id_dfr0, ID_DFR0, COPTRC, 0); 2240 /* Memory mapped trace */ 2241 cpu->isar.id_dfr0 = 2242 FIELD_DP32(cpu->isar.id_dfr0, ID_DFR0, MMAPTRC, 0); 2243 /* FEAT_AMU (Activity Monitors Extension) */ 2244 cpu->isar.id_aa64pfr0 = 2245 FIELD_DP64(cpu->isar.id_aa64pfr0, ID_AA64PFR0, AMU, 0); 2246 cpu->isar.id_pfr0 = 2247 FIELD_DP32(cpu->isar.id_pfr0, ID_PFR0, AMU, 0); 2248 /* FEAT_MPAM (Memory Partitioning and Monitoring Extension) */ 2249 cpu->isar.id_aa64pfr0 = 2250 FIELD_DP64(cpu->isar.id_aa64pfr0, ID_AA64PFR0, MPAM, 0); 2251 } 2252 2253 /* MPU can be configured out of a PMSA CPU either by setting has-mpu 2254 * to false or by setting pmsav7-dregion to 0. 2255 */ 2256 if (!cpu->has_mpu || cpu->pmsav7_dregion == 0) { 2257 cpu->has_mpu = false; 2258 cpu->pmsav7_dregion = 0; 2259 cpu->pmsav8r_hdregion = 0; 2260 } 2261 2262 if (arm_feature(env, ARM_FEATURE_PMSA) && 2263 arm_feature(env, ARM_FEATURE_V7)) { 2264 uint32_t nr = cpu->pmsav7_dregion; 2265 2266 if (nr > 0xff) { 2267 error_setg(errp, "PMSAv7 MPU #regions invalid %" PRIu32, nr); 2268 return; 2269 } 2270 2271 if (nr) { 2272 if (arm_feature(env, ARM_FEATURE_V8)) { 2273 /* PMSAv8 */ 2274 env->pmsav8.rbar[M_REG_NS] = g_new0(uint32_t, nr); 2275 env->pmsav8.rlar[M_REG_NS] = g_new0(uint32_t, nr); 2276 if (arm_feature(env, ARM_FEATURE_M_SECURITY)) { 2277 env->pmsav8.rbar[M_REG_S] = g_new0(uint32_t, nr); 2278 env->pmsav8.rlar[M_REG_S] = g_new0(uint32_t, nr); 2279 } 2280 } else { 2281 env->pmsav7.drbar = g_new0(uint32_t, nr); 2282 env->pmsav7.drsr = g_new0(uint32_t, nr); 2283 env->pmsav7.dracr = g_new0(uint32_t, nr); 2284 } 2285 } 2286 2287 if (cpu->pmsav8r_hdregion > 0xff) { 2288 error_setg(errp, "PMSAv8 MPU EL2 #regions invalid %" PRIu32, 2289 cpu->pmsav8r_hdregion); 2290 return; 2291 } 2292 2293 if (cpu->pmsav8r_hdregion) { 2294 env->pmsav8.hprbar = g_new0(uint32_t, 2295 cpu->pmsav8r_hdregion); 2296 env->pmsav8.hprlar = g_new0(uint32_t, 2297 cpu->pmsav8r_hdregion); 2298 } 2299 } 2300 2301 if (arm_feature(env, ARM_FEATURE_M_SECURITY)) { 2302 uint32_t nr = cpu->sau_sregion; 2303 2304 if (nr > 0xff) { 2305 error_setg(errp, "v8M SAU #regions invalid %" PRIu32, nr); 2306 return; 2307 } 2308 2309 if (nr) { 2310 env->sau.rbar = g_new0(uint32_t, nr); 2311 env->sau.rlar = g_new0(uint32_t, nr); 2312 } 2313 } 2314 2315 if (arm_feature(env, ARM_FEATURE_EL3)) { 2316 set_feature(env, ARM_FEATURE_VBAR); 2317 } 2318 2319 #ifndef CONFIG_USER_ONLY 2320 if (tcg_enabled() && cpu_isar_feature(aa64_rme, cpu)) { 2321 arm_register_el_change_hook(cpu, >_rme_post_el_change, 0); 2322 } 2323 #endif 2324 2325 register_cp_regs_for_features(cpu); 2326 arm_cpu_register_gdb_regs_for_features(cpu); 2327 2328 init_cpreg_list(cpu); 2329 2330 #ifndef CONFIG_USER_ONLY 2331 MachineState *ms = MACHINE(qdev_get_machine()); 2332 unsigned int smp_cpus = ms->smp.cpus; 2333 bool has_secure = cpu->has_el3 || arm_feature(env, ARM_FEATURE_M_SECURITY); 2334 2335 /* 2336 * We must set cs->num_ases to the final value before 2337 * the first call to cpu_address_space_init. 2338 */ 2339 if (cpu->tag_memory != NULL) { 2340 cs->num_ases = 3 + has_secure; 2341 } else { 2342 cs->num_ases = 1 + has_secure; 2343 } 2344 2345 if (has_secure) { 2346 if (!cpu->secure_memory) { 2347 cpu->secure_memory = cs->memory; 2348 } 2349 cpu_address_space_init(cs, ARMASIdx_S, "cpu-secure-memory", 2350 cpu->secure_memory); 2351 } 2352 2353 if (cpu->tag_memory != NULL) { 2354 cpu_address_space_init(cs, ARMASIdx_TagNS, "cpu-tag-memory", 2355 cpu->tag_memory); 2356 if (has_secure) { 2357 cpu_address_space_init(cs, ARMASIdx_TagS, "cpu-tag-memory", 2358 cpu->secure_tag_memory); 2359 } 2360 } 2361 2362 cpu_address_space_init(cs, ARMASIdx_NS, "cpu-memory", cs->memory); 2363 2364 /* No core_count specified, default to smp_cpus. */ 2365 if (cpu->core_count == -1) { 2366 cpu->core_count = smp_cpus; 2367 } 2368 #endif 2369 2370 if (tcg_enabled()) { 2371 int dcz_blocklen = 4 << cpu->dcz_blocksize; 2372 2373 /* 2374 * We only support DCZ blocklen that fits on one page. 2375 * 2376 * Architectually this is always true. However TARGET_PAGE_SIZE 2377 * is variable and, for compatibility with -machine virt-2.7, 2378 * is only 1KiB, as an artifact of legacy ARMv5 subpage support. 2379 * But even then, while the largest architectural DCZ blocklen 2380 * is 2KiB, no cpu actually uses such a large blocklen. 2381 */ 2382 assert(dcz_blocklen <= TARGET_PAGE_SIZE); 2383 2384 /* 2385 * We only support DCZ blocksize >= 2*TAG_GRANULE, which is to say 2386 * both nibbles of each byte storing tag data may be written at once. 2387 * Since TAG_GRANULE is 16, this means that blocklen must be >= 32. 2388 */ 2389 if (cpu_isar_feature(aa64_mte, cpu)) { 2390 assert(dcz_blocklen >= 2 * TAG_GRANULE); 2391 } 2392 } 2393 2394 qemu_init_vcpu(cs); 2395 cpu_reset(cs); 2396 2397 acc->parent_realize(dev, errp); 2398 } 2399 2400 static ObjectClass *arm_cpu_class_by_name(const char *cpu_model) 2401 { 2402 ObjectClass *oc; 2403 char *typename; 2404 char **cpuname; 2405 const char *cpunamestr; 2406 2407 cpuname = g_strsplit(cpu_model, ",", 1); 2408 cpunamestr = cpuname[0]; 2409 #ifdef CONFIG_USER_ONLY 2410 /* For backwards compatibility usermode emulation allows "-cpu any", 2411 * which has the same semantics as "-cpu max". 2412 */ 2413 if (!strcmp(cpunamestr, "any")) { 2414 cpunamestr = "max"; 2415 } 2416 #endif 2417 typename = g_strdup_printf(ARM_CPU_TYPE_NAME("%s"), cpunamestr); 2418 oc = object_class_by_name(typename); 2419 g_strfreev(cpuname); 2420 g_free(typename); 2421 2422 return oc; 2423 } 2424 2425 static Property arm_cpu_properties[] = { 2426 DEFINE_PROP_UINT64("midr", ARMCPU, midr, 0), 2427 DEFINE_PROP_UINT64("mp-affinity", ARMCPU, 2428 mp_affinity, ARM64_AFFINITY_INVALID), 2429 DEFINE_PROP_INT32("node-id", ARMCPU, node_id, CPU_UNSET_NUMA_NODE_ID), 2430 DEFINE_PROP_INT32("core-count", ARMCPU, core_count, -1), 2431 DEFINE_PROP_END_OF_LIST() 2432 }; 2433 2434 static const gchar *arm_gdb_arch_name(CPUState *cs) 2435 { 2436 ARMCPU *cpu = ARM_CPU(cs); 2437 CPUARMState *env = &cpu->env; 2438 2439 if (arm_feature(env, ARM_FEATURE_IWMMXT)) { 2440 return "iwmmxt"; 2441 } 2442 return "arm"; 2443 } 2444 2445 #ifndef CONFIG_USER_ONLY 2446 #include "hw/core/sysemu-cpu-ops.h" 2447 2448 static const struct SysemuCPUOps arm_sysemu_ops = { 2449 .get_phys_page_attrs_debug = arm_cpu_get_phys_page_attrs_debug, 2450 .asidx_from_attrs = arm_asidx_from_attrs, 2451 .write_elf32_note = arm_cpu_write_elf32_note, 2452 .write_elf64_note = arm_cpu_write_elf64_note, 2453 .virtio_is_big_endian = arm_cpu_virtio_is_big_endian, 2454 .legacy_vmsd = &vmstate_arm_cpu, 2455 }; 2456 #endif 2457 2458 #ifdef CONFIG_TCG 2459 static const struct TCGCPUOps arm_tcg_ops = { 2460 .initialize = arm_translate_init, 2461 .synchronize_from_tb = arm_cpu_synchronize_from_tb, 2462 .debug_excp_handler = arm_debug_excp_handler, 2463 .restore_state_to_opc = arm_restore_state_to_opc, 2464 2465 #ifdef CONFIG_USER_ONLY 2466 .record_sigsegv = arm_cpu_record_sigsegv, 2467 .record_sigbus = arm_cpu_record_sigbus, 2468 #else 2469 .tlb_fill = arm_cpu_tlb_fill, 2470 .cpu_exec_interrupt = arm_cpu_exec_interrupt, 2471 .do_interrupt = arm_cpu_do_interrupt, 2472 .do_transaction_failed = arm_cpu_do_transaction_failed, 2473 .do_unaligned_access = arm_cpu_do_unaligned_access, 2474 .adjust_watchpoint_address = arm_adjust_watchpoint_address, 2475 .debug_check_watchpoint = arm_debug_check_watchpoint, 2476 .debug_check_breakpoint = arm_debug_check_breakpoint, 2477 #endif /* !CONFIG_USER_ONLY */ 2478 }; 2479 #endif /* CONFIG_TCG */ 2480 2481 static void arm_cpu_class_init(ObjectClass *oc, void *data) 2482 { 2483 ARMCPUClass *acc = ARM_CPU_CLASS(oc); 2484 CPUClass *cc = CPU_CLASS(acc); 2485 DeviceClass *dc = DEVICE_CLASS(oc); 2486 ResettableClass *rc = RESETTABLE_CLASS(oc); 2487 2488 device_class_set_parent_realize(dc, arm_cpu_realizefn, 2489 &acc->parent_realize); 2490 2491 device_class_set_props(dc, arm_cpu_properties); 2492 2493 resettable_class_set_parent_phases(rc, NULL, arm_cpu_reset_hold, NULL, 2494 &acc->parent_phases); 2495 2496 cc->class_by_name = arm_cpu_class_by_name; 2497 cc->has_work = arm_cpu_has_work; 2498 cc->dump_state = arm_cpu_dump_state; 2499 cc->set_pc = arm_cpu_set_pc; 2500 cc->get_pc = arm_cpu_get_pc; 2501 cc->gdb_read_register = arm_cpu_gdb_read_register; 2502 cc->gdb_write_register = arm_cpu_gdb_write_register; 2503 #ifndef CONFIG_USER_ONLY 2504 cc->sysemu_ops = &arm_sysemu_ops; 2505 #endif 2506 cc->gdb_num_core_regs = 26; 2507 cc->gdb_arch_name = arm_gdb_arch_name; 2508 cc->gdb_get_dynamic_xml = arm_gdb_get_dynamic_xml; 2509 cc->gdb_stop_before_watchpoint = true; 2510 cc->disas_set_info = arm_disas_set_info; 2511 2512 #ifdef CONFIG_TCG 2513 cc->tcg_ops = &arm_tcg_ops; 2514 #endif /* CONFIG_TCG */ 2515 } 2516 2517 static void arm_cpu_instance_init(Object *obj) 2518 { 2519 ARMCPUClass *acc = ARM_CPU_GET_CLASS(obj); 2520 2521 acc->info->initfn(obj); 2522 arm_cpu_post_init(obj); 2523 } 2524 2525 static void cpu_register_class_init(ObjectClass *oc, void *data) 2526 { 2527 ARMCPUClass *acc = ARM_CPU_CLASS(oc); 2528 CPUClass *cc = CPU_CLASS(acc); 2529 2530 acc->info = data; 2531 cc->gdb_core_xml_file = "arm-core.xml"; 2532 } 2533 2534 void arm_cpu_register(const ARMCPUInfo *info) 2535 { 2536 TypeInfo type_info = { 2537 .parent = TYPE_ARM_CPU, 2538 .instance_init = arm_cpu_instance_init, 2539 .class_init = info->class_init ?: cpu_register_class_init, 2540 .class_data = (void *)info, 2541 }; 2542 2543 type_info.name = g_strdup_printf("%s-" TYPE_ARM_CPU, info->name); 2544 type_register(&type_info); 2545 g_free((void *)type_info.name); 2546 } 2547 2548 static const TypeInfo arm_cpu_type_info = { 2549 .name = TYPE_ARM_CPU, 2550 .parent = TYPE_CPU, 2551 .instance_size = sizeof(ARMCPU), 2552 .instance_align = __alignof__(ARMCPU), 2553 .instance_init = arm_cpu_initfn, 2554 .instance_finalize = arm_cpu_finalizefn, 2555 .abstract = true, 2556 .class_size = sizeof(ARMCPUClass), 2557 .class_init = arm_cpu_class_init, 2558 }; 2559 2560 static void arm_cpu_register_types(void) 2561 { 2562 type_register_static(&arm_cpu_type_info); 2563 } 2564 2565 type_init(arm_cpu_register_types) 2566