1 /* 2 * QEMU ARM CPU 3 * 4 * Copyright (c) 2012 SUSE LINUX Products GmbH 5 * 6 * This program is free software; you can redistribute it and/or 7 * modify it under the terms of the GNU General Public License 8 * as published by the Free Software Foundation; either version 2 9 * of the License, or (at your option) any later version. 10 * 11 * This program is distributed in the hope that it will be useful, 12 * but WITHOUT ANY WARRANTY; without even the implied warranty of 13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 14 * GNU General Public License for more details. 15 * 16 * You should have received a copy of the GNU General Public License 17 * along with this program; if not, see 18 * <http://www.gnu.org/licenses/gpl-2.0.html> 19 */ 20 21 #include "qemu/osdep.h" 22 #include "qemu/error-report.h" 23 #include "qapi/error.h" 24 #include "cpu.h" 25 #include "internals.h" 26 #include "qemu-common.h" 27 #include "exec/exec-all.h" 28 #include "hw/qdev-properties.h" 29 #if !defined(CONFIG_USER_ONLY) 30 #include "hw/loader.h" 31 #endif 32 #include "hw/arm/arm.h" 33 #include "sysemu/sysemu.h" 34 #include "sysemu/hw_accel.h" 35 #include "kvm_arm.h" 36 #include "disas/capstone.h" 37 38 static void arm_cpu_set_pc(CPUState *cs, vaddr value) 39 { 40 ARMCPU *cpu = ARM_CPU(cs); 41 42 cpu->env.regs[15] = value; 43 } 44 45 static bool arm_cpu_has_work(CPUState *cs) 46 { 47 ARMCPU *cpu = ARM_CPU(cs); 48 49 return (cpu->power_state != PSCI_OFF) 50 && cs->interrupt_request & 51 (CPU_INTERRUPT_FIQ | CPU_INTERRUPT_HARD 52 | CPU_INTERRUPT_VFIQ | CPU_INTERRUPT_VIRQ 53 | CPU_INTERRUPT_EXITTB); 54 } 55 56 void arm_register_el_change_hook(ARMCPU *cpu, ARMELChangeHook *hook, 57 void *opaque) 58 { 59 /* We currently only support registering a single hook function */ 60 assert(!cpu->el_change_hook); 61 cpu->el_change_hook = hook; 62 cpu->el_change_hook_opaque = opaque; 63 } 64 65 static void cp_reg_reset(gpointer key, gpointer value, gpointer opaque) 66 { 67 /* Reset a single ARMCPRegInfo register */ 68 ARMCPRegInfo *ri = value; 69 ARMCPU *cpu = opaque; 70 71 if (ri->type & (ARM_CP_SPECIAL | ARM_CP_ALIAS)) { 72 return; 73 } 74 75 if (ri->resetfn) { 76 ri->resetfn(&cpu->env, ri); 77 return; 78 } 79 80 /* A zero offset is never possible as it would be regs[0] 81 * so we use it to indicate that reset is being handled elsewhere. 82 * This is basically only used for fields in non-core coprocessors 83 * (like the pxa2xx ones). 84 */ 85 if (!ri->fieldoffset) { 86 return; 87 } 88 89 if (cpreg_field_is_64bit(ri)) { 90 CPREG_FIELD64(&cpu->env, ri) = ri->resetvalue; 91 } else { 92 CPREG_FIELD32(&cpu->env, ri) = ri->resetvalue; 93 } 94 } 95 96 static void cp_reg_check_reset(gpointer key, gpointer value, gpointer opaque) 97 { 98 /* Purely an assertion check: we've already done reset once, 99 * so now check that running the reset for the cpreg doesn't 100 * change its value. This traps bugs where two different cpregs 101 * both try to reset the same state field but to different values. 102 */ 103 ARMCPRegInfo *ri = value; 104 ARMCPU *cpu = opaque; 105 uint64_t oldvalue, newvalue; 106 107 if (ri->type & (ARM_CP_SPECIAL | ARM_CP_ALIAS | ARM_CP_NO_RAW)) { 108 return; 109 } 110 111 oldvalue = read_raw_cp_reg(&cpu->env, ri); 112 cp_reg_reset(key, value, opaque); 113 newvalue = read_raw_cp_reg(&cpu->env, ri); 114 assert(oldvalue == newvalue); 115 } 116 117 /* CPUClass::reset() */ 118 static void arm_cpu_reset(CPUState *s) 119 { 120 ARMCPU *cpu = ARM_CPU(s); 121 ARMCPUClass *acc = ARM_CPU_GET_CLASS(cpu); 122 CPUARMState *env = &cpu->env; 123 124 acc->parent_reset(s); 125 126 memset(env, 0, offsetof(CPUARMState, end_reset_fields)); 127 128 g_hash_table_foreach(cpu->cp_regs, cp_reg_reset, cpu); 129 g_hash_table_foreach(cpu->cp_regs, cp_reg_check_reset, cpu); 130 131 env->vfp.xregs[ARM_VFP_FPSID] = cpu->reset_fpsid; 132 env->vfp.xregs[ARM_VFP_MVFR0] = cpu->mvfr0; 133 env->vfp.xregs[ARM_VFP_MVFR1] = cpu->mvfr1; 134 env->vfp.xregs[ARM_VFP_MVFR2] = cpu->mvfr2; 135 136 cpu->power_state = cpu->start_powered_off ? PSCI_OFF : PSCI_ON; 137 s->halted = cpu->start_powered_off; 138 139 if (arm_feature(env, ARM_FEATURE_IWMMXT)) { 140 env->iwmmxt.cregs[ARM_IWMMXT_wCID] = 0x69051000 | 'Q'; 141 } 142 143 if (arm_feature(env, ARM_FEATURE_AARCH64)) { 144 /* 64 bit CPUs always start in 64 bit mode */ 145 env->aarch64 = 1; 146 #if defined(CONFIG_USER_ONLY) 147 env->pstate = PSTATE_MODE_EL0t; 148 /* Userspace expects access to DC ZVA, CTL_EL0 and the cache ops */ 149 env->cp15.sctlr_el[1] |= SCTLR_UCT | SCTLR_UCI | SCTLR_DZE; 150 /* and to the FP/Neon instructions */ 151 env->cp15.cpacr_el1 = deposit64(env->cp15.cpacr_el1, 20, 2, 3); 152 #else 153 /* Reset into the highest available EL */ 154 if (arm_feature(env, ARM_FEATURE_EL3)) { 155 env->pstate = PSTATE_MODE_EL3h; 156 } else if (arm_feature(env, ARM_FEATURE_EL2)) { 157 env->pstate = PSTATE_MODE_EL2h; 158 } else { 159 env->pstate = PSTATE_MODE_EL1h; 160 } 161 env->pc = cpu->rvbar; 162 #endif 163 } else { 164 #if defined(CONFIG_USER_ONLY) 165 /* Userspace expects access to cp10 and cp11 for FP/Neon */ 166 env->cp15.cpacr_el1 = deposit64(env->cp15.cpacr_el1, 20, 4, 0xf); 167 #endif 168 } 169 170 #if defined(CONFIG_USER_ONLY) 171 env->uncached_cpsr = ARM_CPU_MODE_USR; 172 /* For user mode we must enable access to coprocessors */ 173 env->vfp.xregs[ARM_VFP_FPEXC] = 1 << 30; 174 if (arm_feature(env, ARM_FEATURE_IWMMXT)) { 175 env->cp15.c15_cpar = 3; 176 } else if (arm_feature(env, ARM_FEATURE_XSCALE)) { 177 env->cp15.c15_cpar = 1; 178 } 179 #else 180 /* SVC mode with interrupts disabled. */ 181 env->uncached_cpsr = ARM_CPU_MODE_SVC; 182 env->daif = PSTATE_D | PSTATE_A | PSTATE_I | PSTATE_F; 183 184 if (arm_feature(env, ARM_FEATURE_M)) { 185 uint32_t initial_msp; /* Loaded from 0x0 */ 186 uint32_t initial_pc; /* Loaded from 0x4 */ 187 uint8_t *rom; 188 189 if (arm_feature(env, ARM_FEATURE_M_SECURITY)) { 190 env->v7m.secure = true; 191 } else { 192 /* This bit resets to 0 if security is supported, but 1 if 193 * it is not. The bit is not present in v7M, but we set it 194 * here so we can avoid having to make checks on it conditional 195 * on ARM_FEATURE_V8 (we don't let the guest see the bit). 196 */ 197 env->v7m.aircr = R_V7M_AIRCR_BFHFNMINS_MASK; 198 } 199 200 /* In v7M the reset value of this bit is IMPDEF, but ARM recommends 201 * that it resets to 1, so QEMU always does that rather than making 202 * it dependent on CPU model. In v8M it is RES1. 203 */ 204 env->v7m.ccr[M_REG_NS] = R_V7M_CCR_STKALIGN_MASK; 205 env->v7m.ccr[M_REG_S] = R_V7M_CCR_STKALIGN_MASK; 206 if (arm_feature(env, ARM_FEATURE_V8)) { 207 /* in v8M the NONBASETHRDENA bit [0] is RES1 */ 208 env->v7m.ccr[M_REG_NS] |= R_V7M_CCR_NONBASETHRDENA_MASK; 209 env->v7m.ccr[M_REG_S] |= R_V7M_CCR_NONBASETHRDENA_MASK; 210 } 211 212 /* Unlike A/R profile, M profile defines the reset LR value */ 213 env->regs[14] = 0xffffffff; 214 215 /* Load the initial SP and PC from the vector table at address 0 */ 216 rom = rom_ptr(0); 217 if (rom) { 218 /* Address zero is covered by ROM which hasn't yet been 219 * copied into physical memory. 220 */ 221 initial_msp = ldl_p(rom); 222 initial_pc = ldl_p(rom + 4); 223 } else { 224 /* Address zero not covered by a ROM blob, or the ROM blob 225 * is in non-modifiable memory and this is a second reset after 226 * it got copied into memory. In the latter case, rom_ptr 227 * will return a NULL pointer and we should use ldl_phys instead. 228 */ 229 initial_msp = ldl_phys(s->as, 0); 230 initial_pc = ldl_phys(s->as, 4); 231 } 232 233 env->regs[13] = initial_msp & 0xFFFFFFFC; 234 env->regs[15] = initial_pc & ~1; 235 env->thumb = initial_pc & 1; 236 } 237 238 /* AArch32 has a hard highvec setting of 0xFFFF0000. If we are currently 239 * executing as AArch32 then check if highvecs are enabled and 240 * adjust the PC accordingly. 241 */ 242 if (A32_BANKED_CURRENT_REG_GET(env, sctlr) & SCTLR_V) { 243 env->regs[15] = 0xFFFF0000; 244 } 245 246 /* M profile requires that reset clears the exclusive monitor; 247 * A profile does not, but clearing it makes more sense than having it 248 * set with an exclusive access on address zero. 249 */ 250 arm_clear_exclusive(env); 251 252 env->vfp.xregs[ARM_VFP_FPEXC] = 0; 253 #endif 254 255 if (arm_feature(env, ARM_FEATURE_PMSA)) { 256 if (cpu->pmsav7_dregion > 0) { 257 if (arm_feature(env, ARM_FEATURE_V8)) { 258 memset(env->pmsav8.rbar[M_REG_NS], 0, 259 sizeof(*env->pmsav8.rbar[M_REG_NS]) 260 * cpu->pmsav7_dregion); 261 memset(env->pmsav8.rlar[M_REG_NS], 0, 262 sizeof(*env->pmsav8.rlar[M_REG_NS]) 263 * cpu->pmsav7_dregion); 264 if (arm_feature(env, ARM_FEATURE_M_SECURITY)) { 265 memset(env->pmsav8.rbar[M_REG_S], 0, 266 sizeof(*env->pmsav8.rbar[M_REG_S]) 267 * cpu->pmsav7_dregion); 268 memset(env->pmsav8.rlar[M_REG_S], 0, 269 sizeof(*env->pmsav8.rlar[M_REG_S]) 270 * cpu->pmsav7_dregion); 271 } 272 } else if (arm_feature(env, ARM_FEATURE_V7)) { 273 memset(env->pmsav7.drbar, 0, 274 sizeof(*env->pmsav7.drbar) * cpu->pmsav7_dregion); 275 memset(env->pmsav7.drsr, 0, 276 sizeof(*env->pmsav7.drsr) * cpu->pmsav7_dregion); 277 memset(env->pmsav7.dracr, 0, 278 sizeof(*env->pmsav7.dracr) * cpu->pmsav7_dregion); 279 } 280 } 281 env->pmsav7.rnr[M_REG_NS] = 0; 282 env->pmsav7.rnr[M_REG_S] = 0; 283 env->pmsav8.mair0[M_REG_NS] = 0; 284 env->pmsav8.mair0[M_REG_S] = 0; 285 env->pmsav8.mair1[M_REG_NS] = 0; 286 env->pmsav8.mair1[M_REG_S] = 0; 287 } 288 289 if (arm_feature(env, ARM_FEATURE_M_SECURITY)) { 290 if (cpu->sau_sregion > 0) { 291 memset(env->sau.rbar, 0, sizeof(*env->sau.rbar) * cpu->sau_sregion); 292 memset(env->sau.rlar, 0, sizeof(*env->sau.rlar) * cpu->sau_sregion); 293 } 294 env->sau.rnr = 0; 295 /* SAU_CTRL reset value is IMPDEF; we choose 0, which is what 296 * the Cortex-M33 does. 297 */ 298 env->sau.ctrl = 0; 299 } 300 301 set_flush_to_zero(1, &env->vfp.standard_fp_status); 302 set_flush_inputs_to_zero(1, &env->vfp.standard_fp_status); 303 set_default_nan_mode(1, &env->vfp.standard_fp_status); 304 set_float_detect_tininess(float_tininess_before_rounding, 305 &env->vfp.fp_status); 306 set_float_detect_tininess(float_tininess_before_rounding, 307 &env->vfp.standard_fp_status); 308 #ifndef CONFIG_USER_ONLY 309 if (kvm_enabled()) { 310 kvm_arm_reset_vcpu(cpu); 311 } 312 #endif 313 314 hw_breakpoint_update_all(cpu); 315 hw_watchpoint_update_all(cpu); 316 } 317 318 bool arm_cpu_exec_interrupt(CPUState *cs, int interrupt_request) 319 { 320 CPUClass *cc = CPU_GET_CLASS(cs); 321 CPUARMState *env = cs->env_ptr; 322 uint32_t cur_el = arm_current_el(env); 323 bool secure = arm_is_secure(env); 324 uint32_t target_el; 325 uint32_t excp_idx; 326 bool ret = false; 327 328 if (interrupt_request & CPU_INTERRUPT_FIQ) { 329 excp_idx = EXCP_FIQ; 330 target_el = arm_phys_excp_target_el(cs, excp_idx, cur_el, secure); 331 if (arm_excp_unmasked(cs, excp_idx, target_el)) { 332 cs->exception_index = excp_idx; 333 env->exception.target_el = target_el; 334 cc->do_interrupt(cs); 335 ret = true; 336 } 337 } 338 if (interrupt_request & CPU_INTERRUPT_HARD) { 339 excp_idx = EXCP_IRQ; 340 target_el = arm_phys_excp_target_el(cs, excp_idx, cur_el, secure); 341 if (arm_excp_unmasked(cs, excp_idx, target_el)) { 342 cs->exception_index = excp_idx; 343 env->exception.target_el = target_el; 344 cc->do_interrupt(cs); 345 ret = true; 346 } 347 } 348 if (interrupt_request & CPU_INTERRUPT_VIRQ) { 349 excp_idx = EXCP_VIRQ; 350 target_el = 1; 351 if (arm_excp_unmasked(cs, excp_idx, target_el)) { 352 cs->exception_index = excp_idx; 353 env->exception.target_el = target_el; 354 cc->do_interrupt(cs); 355 ret = true; 356 } 357 } 358 if (interrupt_request & CPU_INTERRUPT_VFIQ) { 359 excp_idx = EXCP_VFIQ; 360 target_el = 1; 361 if (arm_excp_unmasked(cs, excp_idx, target_el)) { 362 cs->exception_index = excp_idx; 363 env->exception.target_el = target_el; 364 cc->do_interrupt(cs); 365 ret = true; 366 } 367 } 368 369 return ret; 370 } 371 372 #if !defined(CONFIG_USER_ONLY) || !defined(TARGET_AARCH64) 373 static bool arm_v7m_cpu_exec_interrupt(CPUState *cs, int interrupt_request) 374 { 375 CPUClass *cc = CPU_GET_CLASS(cs); 376 ARMCPU *cpu = ARM_CPU(cs); 377 CPUARMState *env = &cpu->env; 378 bool ret = false; 379 380 /* ARMv7-M interrupt masking works differently than -A or -R. 381 * There is no FIQ/IRQ distinction. Instead of I and F bits 382 * masking FIQ and IRQ interrupts, an exception is taken only 383 * if it is higher priority than the current execution priority 384 * (which depends on state like BASEPRI, FAULTMASK and the 385 * currently active exception). 386 */ 387 if (interrupt_request & CPU_INTERRUPT_HARD 388 && (armv7m_nvic_can_take_pending_exception(env->nvic))) { 389 cs->exception_index = EXCP_IRQ; 390 cc->do_interrupt(cs); 391 ret = true; 392 } 393 return ret; 394 } 395 #endif 396 397 #ifndef CONFIG_USER_ONLY 398 static void arm_cpu_set_irq(void *opaque, int irq, int level) 399 { 400 ARMCPU *cpu = opaque; 401 CPUARMState *env = &cpu->env; 402 CPUState *cs = CPU(cpu); 403 static const int mask[] = { 404 [ARM_CPU_IRQ] = CPU_INTERRUPT_HARD, 405 [ARM_CPU_FIQ] = CPU_INTERRUPT_FIQ, 406 [ARM_CPU_VIRQ] = CPU_INTERRUPT_VIRQ, 407 [ARM_CPU_VFIQ] = CPU_INTERRUPT_VFIQ 408 }; 409 410 switch (irq) { 411 case ARM_CPU_VIRQ: 412 case ARM_CPU_VFIQ: 413 assert(arm_feature(env, ARM_FEATURE_EL2)); 414 /* fall through */ 415 case ARM_CPU_IRQ: 416 case ARM_CPU_FIQ: 417 if (level) { 418 cpu_interrupt(cs, mask[irq]); 419 } else { 420 cpu_reset_interrupt(cs, mask[irq]); 421 } 422 break; 423 default: 424 g_assert_not_reached(); 425 } 426 } 427 428 static void arm_cpu_kvm_set_irq(void *opaque, int irq, int level) 429 { 430 #ifdef CONFIG_KVM 431 ARMCPU *cpu = opaque; 432 CPUState *cs = CPU(cpu); 433 int kvm_irq = KVM_ARM_IRQ_TYPE_CPU << KVM_ARM_IRQ_TYPE_SHIFT; 434 435 switch (irq) { 436 case ARM_CPU_IRQ: 437 kvm_irq |= KVM_ARM_IRQ_CPU_IRQ; 438 break; 439 case ARM_CPU_FIQ: 440 kvm_irq |= KVM_ARM_IRQ_CPU_FIQ; 441 break; 442 default: 443 g_assert_not_reached(); 444 } 445 kvm_irq |= cs->cpu_index << KVM_ARM_IRQ_VCPU_SHIFT; 446 kvm_set_irq(kvm_state, kvm_irq, level ? 1 : 0); 447 #endif 448 } 449 450 static bool arm_cpu_virtio_is_big_endian(CPUState *cs) 451 { 452 ARMCPU *cpu = ARM_CPU(cs); 453 CPUARMState *env = &cpu->env; 454 455 cpu_synchronize_state(cs); 456 return arm_cpu_data_is_big_endian(env); 457 } 458 459 #endif 460 461 static inline void set_feature(CPUARMState *env, int feature) 462 { 463 env->features |= 1ULL << feature; 464 } 465 466 static inline void unset_feature(CPUARMState *env, int feature) 467 { 468 env->features &= ~(1ULL << feature); 469 } 470 471 static int 472 print_insn_thumb1(bfd_vma pc, disassemble_info *info) 473 { 474 return print_insn_arm(pc | 1, info); 475 } 476 477 static void arm_disas_set_info(CPUState *cpu, disassemble_info *info) 478 { 479 ARMCPU *ac = ARM_CPU(cpu); 480 CPUARMState *env = &ac->env; 481 bool sctlr_b; 482 483 if (is_a64(env)) { 484 /* We might not be compiled with the A64 disassembler 485 * because it needs a C++ compiler. Leave print_insn 486 * unset in this case to use the caller default behaviour. 487 */ 488 #if defined(CONFIG_ARM_A64_DIS) 489 info->print_insn = print_insn_arm_a64; 490 #endif 491 info->cap_arch = CS_ARCH_ARM64; 492 info->cap_insn_unit = 4; 493 info->cap_insn_split = 4; 494 } else { 495 int cap_mode; 496 if (env->thumb) { 497 info->print_insn = print_insn_thumb1; 498 info->cap_insn_unit = 2; 499 info->cap_insn_split = 4; 500 cap_mode = CS_MODE_THUMB; 501 } else { 502 info->print_insn = print_insn_arm; 503 info->cap_insn_unit = 4; 504 info->cap_insn_split = 4; 505 cap_mode = CS_MODE_ARM; 506 } 507 if (arm_feature(env, ARM_FEATURE_V8)) { 508 cap_mode |= CS_MODE_V8; 509 } 510 if (arm_feature(env, ARM_FEATURE_M)) { 511 cap_mode |= CS_MODE_MCLASS; 512 } 513 info->cap_arch = CS_ARCH_ARM; 514 info->cap_mode = cap_mode; 515 } 516 517 sctlr_b = arm_sctlr_b(env); 518 if (bswap_code(sctlr_b)) { 519 #ifdef TARGET_WORDS_BIGENDIAN 520 info->endian = BFD_ENDIAN_LITTLE; 521 #else 522 info->endian = BFD_ENDIAN_BIG; 523 #endif 524 } 525 info->flags &= ~INSN_ARM_BE32; 526 #ifndef CONFIG_USER_ONLY 527 if (sctlr_b) { 528 info->flags |= INSN_ARM_BE32; 529 } 530 #endif 531 } 532 533 uint64_t arm_cpu_mp_affinity(int idx, uint8_t clustersz) 534 { 535 uint32_t Aff1 = idx / clustersz; 536 uint32_t Aff0 = idx % clustersz; 537 return (Aff1 << ARM_AFF1_SHIFT) | Aff0; 538 } 539 540 static void arm_cpu_initfn(Object *obj) 541 { 542 CPUState *cs = CPU(obj); 543 ARMCPU *cpu = ARM_CPU(obj); 544 545 cs->env_ptr = &cpu->env; 546 cpu->cp_regs = g_hash_table_new_full(g_int_hash, g_int_equal, 547 g_free, g_free); 548 549 #ifndef CONFIG_USER_ONLY 550 /* Our inbound IRQ and FIQ lines */ 551 if (kvm_enabled()) { 552 /* VIRQ and VFIQ are unused with KVM but we add them to maintain 553 * the same interface as non-KVM CPUs. 554 */ 555 qdev_init_gpio_in(DEVICE(cpu), arm_cpu_kvm_set_irq, 4); 556 } else { 557 qdev_init_gpio_in(DEVICE(cpu), arm_cpu_set_irq, 4); 558 } 559 560 cpu->gt_timer[GTIMER_PHYS] = timer_new(QEMU_CLOCK_VIRTUAL, GTIMER_SCALE, 561 arm_gt_ptimer_cb, cpu); 562 cpu->gt_timer[GTIMER_VIRT] = timer_new(QEMU_CLOCK_VIRTUAL, GTIMER_SCALE, 563 arm_gt_vtimer_cb, cpu); 564 cpu->gt_timer[GTIMER_HYP] = timer_new(QEMU_CLOCK_VIRTUAL, GTIMER_SCALE, 565 arm_gt_htimer_cb, cpu); 566 cpu->gt_timer[GTIMER_SEC] = timer_new(QEMU_CLOCK_VIRTUAL, GTIMER_SCALE, 567 arm_gt_stimer_cb, cpu); 568 qdev_init_gpio_out(DEVICE(cpu), cpu->gt_timer_outputs, 569 ARRAY_SIZE(cpu->gt_timer_outputs)); 570 571 qdev_init_gpio_out_named(DEVICE(cpu), &cpu->gicv3_maintenance_interrupt, 572 "gicv3-maintenance-interrupt", 1); 573 qdev_init_gpio_out_named(DEVICE(cpu), &cpu->pmu_interrupt, 574 "pmu-interrupt", 1); 575 #endif 576 577 /* DTB consumers generally don't in fact care what the 'compatible' 578 * string is, so always provide some string and trust that a hypothetical 579 * picky DTB consumer will also provide a helpful error message. 580 */ 581 cpu->dtb_compatible = "qemu,unknown"; 582 cpu->psci_version = 1; /* By default assume PSCI v0.1 */ 583 cpu->kvm_target = QEMU_KVM_ARM_TARGET_NONE; 584 585 if (tcg_enabled()) { 586 cpu->psci_version = 2; /* TCG implements PSCI 0.2 */ 587 } 588 } 589 590 static Property arm_cpu_reset_cbar_property = 591 DEFINE_PROP_UINT64("reset-cbar", ARMCPU, reset_cbar, 0); 592 593 static Property arm_cpu_reset_hivecs_property = 594 DEFINE_PROP_BOOL("reset-hivecs", ARMCPU, reset_hivecs, false); 595 596 static Property arm_cpu_rvbar_property = 597 DEFINE_PROP_UINT64("rvbar", ARMCPU, rvbar, 0); 598 599 static Property arm_cpu_has_el2_property = 600 DEFINE_PROP_BOOL("has_el2", ARMCPU, has_el2, true); 601 602 static Property arm_cpu_has_el3_property = 603 DEFINE_PROP_BOOL("has_el3", ARMCPU, has_el3, true); 604 605 static Property arm_cpu_cfgend_property = 606 DEFINE_PROP_BOOL("cfgend", ARMCPU, cfgend, false); 607 608 /* use property name "pmu" to match other archs and virt tools */ 609 static Property arm_cpu_has_pmu_property = 610 DEFINE_PROP_BOOL("pmu", ARMCPU, has_pmu, true); 611 612 static Property arm_cpu_has_mpu_property = 613 DEFINE_PROP_BOOL("has-mpu", ARMCPU, has_mpu, true); 614 615 /* This is like DEFINE_PROP_UINT32 but it doesn't set the default value, 616 * because the CPU initfn will have already set cpu->pmsav7_dregion to 617 * the right value for that particular CPU type, and we don't want 618 * to override that with an incorrect constant value. 619 */ 620 static Property arm_cpu_pmsav7_dregion_property = 621 DEFINE_PROP_UNSIGNED_NODEFAULT("pmsav7-dregion", ARMCPU, 622 pmsav7_dregion, 623 qdev_prop_uint32, uint32_t); 624 625 static void arm_cpu_post_init(Object *obj) 626 { 627 ARMCPU *cpu = ARM_CPU(obj); 628 629 /* M profile implies PMSA. We have to do this here rather than 630 * in realize with the other feature-implication checks because 631 * we look at the PMSA bit to see if we should add some properties. 632 */ 633 if (arm_feature(&cpu->env, ARM_FEATURE_M)) { 634 set_feature(&cpu->env, ARM_FEATURE_PMSA); 635 } 636 637 if (arm_feature(&cpu->env, ARM_FEATURE_CBAR) || 638 arm_feature(&cpu->env, ARM_FEATURE_CBAR_RO)) { 639 qdev_property_add_static(DEVICE(obj), &arm_cpu_reset_cbar_property, 640 &error_abort); 641 } 642 643 if (!arm_feature(&cpu->env, ARM_FEATURE_M)) { 644 qdev_property_add_static(DEVICE(obj), &arm_cpu_reset_hivecs_property, 645 &error_abort); 646 } 647 648 if (arm_feature(&cpu->env, ARM_FEATURE_AARCH64)) { 649 qdev_property_add_static(DEVICE(obj), &arm_cpu_rvbar_property, 650 &error_abort); 651 } 652 653 if (arm_feature(&cpu->env, ARM_FEATURE_EL3)) { 654 /* Add the has_el3 state CPU property only if EL3 is allowed. This will 655 * prevent "has_el3" from existing on CPUs which cannot support EL3. 656 */ 657 qdev_property_add_static(DEVICE(obj), &arm_cpu_has_el3_property, 658 &error_abort); 659 660 #ifndef CONFIG_USER_ONLY 661 object_property_add_link(obj, "secure-memory", 662 TYPE_MEMORY_REGION, 663 (Object **)&cpu->secure_memory, 664 qdev_prop_allow_set_link_before_realize, 665 OBJ_PROP_LINK_UNREF_ON_RELEASE, 666 &error_abort); 667 #endif 668 } 669 670 if (arm_feature(&cpu->env, ARM_FEATURE_EL2)) { 671 qdev_property_add_static(DEVICE(obj), &arm_cpu_has_el2_property, 672 &error_abort); 673 } 674 675 if (arm_feature(&cpu->env, ARM_FEATURE_PMU)) { 676 qdev_property_add_static(DEVICE(obj), &arm_cpu_has_pmu_property, 677 &error_abort); 678 } 679 680 if (arm_feature(&cpu->env, ARM_FEATURE_PMSA)) { 681 qdev_property_add_static(DEVICE(obj), &arm_cpu_has_mpu_property, 682 &error_abort); 683 if (arm_feature(&cpu->env, ARM_FEATURE_V7)) { 684 qdev_property_add_static(DEVICE(obj), 685 &arm_cpu_pmsav7_dregion_property, 686 &error_abort); 687 } 688 } 689 690 qdev_property_add_static(DEVICE(obj), &arm_cpu_cfgend_property, 691 &error_abort); 692 } 693 694 static void arm_cpu_finalizefn(Object *obj) 695 { 696 ARMCPU *cpu = ARM_CPU(obj); 697 g_hash_table_destroy(cpu->cp_regs); 698 } 699 700 static void arm_cpu_realizefn(DeviceState *dev, Error **errp) 701 { 702 CPUState *cs = CPU(dev); 703 ARMCPU *cpu = ARM_CPU(dev); 704 ARMCPUClass *acc = ARM_CPU_GET_CLASS(dev); 705 CPUARMState *env = &cpu->env; 706 int pagebits; 707 Error *local_err = NULL; 708 #ifndef CONFIG_USER_ONLY 709 AddressSpace *as; 710 #endif 711 712 cpu_exec_realizefn(cs, &local_err); 713 if (local_err != NULL) { 714 error_propagate(errp, local_err); 715 return; 716 } 717 718 /* Some features automatically imply others: */ 719 if (arm_feature(env, ARM_FEATURE_V8)) { 720 set_feature(env, ARM_FEATURE_V7); 721 set_feature(env, ARM_FEATURE_ARM_DIV); 722 set_feature(env, ARM_FEATURE_LPAE); 723 } 724 if (arm_feature(env, ARM_FEATURE_V7)) { 725 set_feature(env, ARM_FEATURE_VAPA); 726 set_feature(env, ARM_FEATURE_THUMB2); 727 set_feature(env, ARM_FEATURE_MPIDR); 728 if (!arm_feature(env, ARM_FEATURE_M)) { 729 set_feature(env, ARM_FEATURE_V6K); 730 } else { 731 set_feature(env, ARM_FEATURE_V6); 732 } 733 734 /* Always define VBAR for V7 CPUs even if it doesn't exist in 735 * non-EL3 configs. This is needed by some legacy boards. 736 */ 737 set_feature(env, ARM_FEATURE_VBAR); 738 } 739 if (arm_feature(env, ARM_FEATURE_V6K)) { 740 set_feature(env, ARM_FEATURE_V6); 741 set_feature(env, ARM_FEATURE_MVFR); 742 } 743 if (arm_feature(env, ARM_FEATURE_V6)) { 744 set_feature(env, ARM_FEATURE_V5); 745 set_feature(env, ARM_FEATURE_JAZELLE); 746 if (!arm_feature(env, ARM_FEATURE_M)) { 747 set_feature(env, ARM_FEATURE_AUXCR); 748 } 749 } 750 if (arm_feature(env, ARM_FEATURE_V5)) { 751 set_feature(env, ARM_FEATURE_V4T); 752 } 753 if (arm_feature(env, ARM_FEATURE_M)) { 754 set_feature(env, ARM_FEATURE_THUMB_DIV); 755 } 756 if (arm_feature(env, ARM_FEATURE_ARM_DIV)) { 757 set_feature(env, ARM_FEATURE_THUMB_DIV); 758 } 759 if (arm_feature(env, ARM_FEATURE_VFP4)) { 760 set_feature(env, ARM_FEATURE_VFP3); 761 set_feature(env, ARM_FEATURE_VFP_FP16); 762 } 763 if (arm_feature(env, ARM_FEATURE_VFP3)) { 764 set_feature(env, ARM_FEATURE_VFP); 765 } 766 if (arm_feature(env, ARM_FEATURE_LPAE)) { 767 set_feature(env, ARM_FEATURE_V7MP); 768 set_feature(env, ARM_FEATURE_PXN); 769 } 770 if (arm_feature(env, ARM_FEATURE_CBAR_RO)) { 771 set_feature(env, ARM_FEATURE_CBAR); 772 } 773 if (arm_feature(env, ARM_FEATURE_THUMB2) && 774 !arm_feature(env, ARM_FEATURE_M)) { 775 set_feature(env, ARM_FEATURE_THUMB_DSP); 776 } 777 778 if (arm_feature(env, ARM_FEATURE_V7) && 779 !arm_feature(env, ARM_FEATURE_M) && 780 !arm_feature(env, ARM_FEATURE_PMSA)) { 781 /* v7VMSA drops support for the old ARMv5 tiny pages, so we 782 * can use 4K pages. 783 */ 784 pagebits = 12; 785 } else { 786 /* For CPUs which might have tiny 1K pages, or which have an 787 * MPU and might have small region sizes, stick with 1K pages. 788 */ 789 pagebits = 10; 790 } 791 if (!set_preferred_target_page_bits(pagebits)) { 792 /* This can only ever happen for hotplugging a CPU, or if 793 * the board code incorrectly creates a CPU which it has 794 * promised via minimum_page_size that it will not. 795 */ 796 error_setg(errp, "This CPU requires a smaller page size than the " 797 "system is using"); 798 return; 799 } 800 801 /* This cpu-id-to-MPIDR affinity is used only for TCG; KVM will override it. 802 * We don't support setting cluster ID ([16..23]) (known as Aff2 803 * in later ARM ARM versions), or any of the higher affinity level fields, 804 * so these bits always RAZ. 805 */ 806 if (cpu->mp_affinity == ARM64_AFFINITY_INVALID) { 807 cpu->mp_affinity = arm_cpu_mp_affinity(cs->cpu_index, 808 ARM_DEFAULT_CPUS_PER_CLUSTER); 809 } 810 811 if (cpu->reset_hivecs) { 812 cpu->reset_sctlr |= (1 << 13); 813 } 814 815 if (cpu->cfgend) { 816 if (arm_feature(&cpu->env, ARM_FEATURE_V7)) { 817 cpu->reset_sctlr |= SCTLR_EE; 818 } else { 819 cpu->reset_sctlr |= SCTLR_B; 820 } 821 } 822 823 if (!cpu->has_el3) { 824 /* If the has_el3 CPU property is disabled then we need to disable the 825 * feature. 826 */ 827 unset_feature(env, ARM_FEATURE_EL3); 828 829 /* Disable the security extension feature bits in the processor feature 830 * registers as well. These are id_pfr1[7:4] and id_aa64pfr0[15:12]. 831 */ 832 cpu->id_pfr1 &= ~0xf0; 833 cpu->id_aa64pfr0 &= ~0xf000; 834 } 835 836 if (!cpu->has_el2) { 837 unset_feature(env, ARM_FEATURE_EL2); 838 } 839 840 if (!cpu->has_pmu) { 841 unset_feature(env, ARM_FEATURE_PMU); 842 cpu->id_aa64dfr0 &= ~0xf00; 843 } 844 845 if (!arm_feature(env, ARM_FEATURE_EL2)) { 846 /* Disable the hypervisor feature bits in the processor feature 847 * registers if we don't have EL2. These are id_pfr1[15:12] and 848 * id_aa64pfr0_el1[11:8]. 849 */ 850 cpu->id_aa64pfr0 &= ~0xf00; 851 cpu->id_pfr1 &= ~0xf000; 852 } 853 854 /* MPU can be configured out of a PMSA CPU either by setting has-mpu 855 * to false or by setting pmsav7-dregion to 0. 856 */ 857 if (!cpu->has_mpu) { 858 cpu->pmsav7_dregion = 0; 859 } 860 if (cpu->pmsav7_dregion == 0) { 861 cpu->has_mpu = false; 862 } 863 864 if (arm_feature(env, ARM_FEATURE_PMSA) && 865 arm_feature(env, ARM_FEATURE_V7)) { 866 uint32_t nr = cpu->pmsav7_dregion; 867 868 if (nr > 0xff) { 869 error_setg(errp, "PMSAv7 MPU #regions invalid %" PRIu32, nr); 870 return; 871 } 872 873 if (nr) { 874 if (arm_feature(env, ARM_FEATURE_V8)) { 875 /* PMSAv8 */ 876 env->pmsav8.rbar[M_REG_NS] = g_new0(uint32_t, nr); 877 env->pmsav8.rlar[M_REG_NS] = g_new0(uint32_t, nr); 878 if (arm_feature(env, ARM_FEATURE_M_SECURITY)) { 879 env->pmsav8.rbar[M_REG_S] = g_new0(uint32_t, nr); 880 env->pmsav8.rlar[M_REG_S] = g_new0(uint32_t, nr); 881 } 882 } else { 883 env->pmsav7.drbar = g_new0(uint32_t, nr); 884 env->pmsav7.drsr = g_new0(uint32_t, nr); 885 env->pmsav7.dracr = g_new0(uint32_t, nr); 886 } 887 } 888 } 889 890 if (arm_feature(env, ARM_FEATURE_M_SECURITY)) { 891 uint32_t nr = cpu->sau_sregion; 892 893 if (nr > 0xff) { 894 error_setg(errp, "v8M SAU #regions invalid %" PRIu32, nr); 895 return; 896 } 897 898 if (nr) { 899 env->sau.rbar = g_new0(uint32_t, nr); 900 env->sau.rlar = g_new0(uint32_t, nr); 901 } 902 } 903 904 if (arm_feature(env, ARM_FEATURE_EL3)) { 905 set_feature(env, ARM_FEATURE_VBAR); 906 } 907 908 register_cp_regs_for_features(cpu); 909 arm_cpu_register_gdb_regs_for_features(cpu); 910 911 init_cpreg_list(cpu); 912 913 #ifndef CONFIG_USER_ONLY 914 if (cpu->has_el3 || arm_feature(env, ARM_FEATURE_M_SECURITY)) { 915 as = g_new0(AddressSpace, 1); 916 917 cs->num_ases = 2; 918 919 if (!cpu->secure_memory) { 920 cpu->secure_memory = cs->memory; 921 } 922 address_space_init(as, cpu->secure_memory, "cpu-secure-memory"); 923 cpu_address_space_init(cs, as, ARMASIdx_S); 924 } else { 925 cs->num_ases = 1; 926 } 927 as = g_new0(AddressSpace, 1); 928 address_space_init(as, cs->memory, "cpu-memory"); 929 cpu_address_space_init(cs, as, ARMASIdx_NS); 930 #endif 931 932 qemu_init_vcpu(cs); 933 cpu_reset(cs); 934 935 acc->parent_realize(dev, errp); 936 } 937 938 static ObjectClass *arm_cpu_class_by_name(const char *cpu_model) 939 { 940 ObjectClass *oc; 941 char *typename; 942 char **cpuname; 943 944 cpuname = g_strsplit(cpu_model, ",", 1); 945 typename = g_strdup_printf(ARM_CPU_TYPE_NAME("%s"), cpuname[0]); 946 oc = object_class_by_name(typename); 947 g_strfreev(cpuname); 948 g_free(typename); 949 if (!oc || !object_class_dynamic_cast(oc, TYPE_ARM_CPU) || 950 object_class_is_abstract(oc)) { 951 return NULL; 952 } 953 return oc; 954 } 955 956 /* CPU models. These are not needed for the AArch64 linux-user build. */ 957 #if !defined(CONFIG_USER_ONLY) || !defined(TARGET_AARCH64) 958 959 static void arm926_initfn(Object *obj) 960 { 961 ARMCPU *cpu = ARM_CPU(obj); 962 963 cpu->dtb_compatible = "arm,arm926"; 964 set_feature(&cpu->env, ARM_FEATURE_V5); 965 set_feature(&cpu->env, ARM_FEATURE_VFP); 966 set_feature(&cpu->env, ARM_FEATURE_DUMMY_C15_REGS); 967 set_feature(&cpu->env, ARM_FEATURE_CACHE_TEST_CLEAN); 968 set_feature(&cpu->env, ARM_FEATURE_JAZELLE); 969 cpu->midr = 0x41069265; 970 cpu->reset_fpsid = 0x41011090; 971 cpu->ctr = 0x1dd20d2; 972 cpu->reset_sctlr = 0x00090078; 973 } 974 975 static void arm946_initfn(Object *obj) 976 { 977 ARMCPU *cpu = ARM_CPU(obj); 978 979 cpu->dtb_compatible = "arm,arm946"; 980 set_feature(&cpu->env, ARM_FEATURE_V5); 981 set_feature(&cpu->env, ARM_FEATURE_PMSA); 982 set_feature(&cpu->env, ARM_FEATURE_DUMMY_C15_REGS); 983 cpu->midr = 0x41059461; 984 cpu->ctr = 0x0f004006; 985 cpu->reset_sctlr = 0x00000078; 986 } 987 988 static void arm1026_initfn(Object *obj) 989 { 990 ARMCPU *cpu = ARM_CPU(obj); 991 992 cpu->dtb_compatible = "arm,arm1026"; 993 set_feature(&cpu->env, ARM_FEATURE_V5); 994 set_feature(&cpu->env, ARM_FEATURE_VFP); 995 set_feature(&cpu->env, ARM_FEATURE_AUXCR); 996 set_feature(&cpu->env, ARM_FEATURE_DUMMY_C15_REGS); 997 set_feature(&cpu->env, ARM_FEATURE_CACHE_TEST_CLEAN); 998 set_feature(&cpu->env, ARM_FEATURE_JAZELLE); 999 cpu->midr = 0x4106a262; 1000 cpu->reset_fpsid = 0x410110a0; 1001 cpu->ctr = 0x1dd20d2; 1002 cpu->reset_sctlr = 0x00090078; 1003 cpu->reset_auxcr = 1; 1004 { 1005 /* The 1026 had an IFAR at c6,c0,0,1 rather than the ARMv6 c6,c0,0,2 */ 1006 ARMCPRegInfo ifar = { 1007 .name = "IFAR", .cp = 15, .crn = 6, .crm = 0, .opc1 = 0, .opc2 = 1, 1008 .access = PL1_RW, 1009 .fieldoffset = offsetof(CPUARMState, cp15.ifar_ns), 1010 .resetvalue = 0 1011 }; 1012 define_one_arm_cp_reg(cpu, &ifar); 1013 } 1014 } 1015 1016 static void arm1136_r2_initfn(Object *obj) 1017 { 1018 ARMCPU *cpu = ARM_CPU(obj); 1019 /* What qemu calls "arm1136_r2" is actually the 1136 r0p2, ie an 1020 * older core than plain "arm1136". In particular this does not 1021 * have the v6K features. 1022 * These ID register values are correct for 1136 but may be wrong 1023 * for 1136_r2 (in particular r0p2 does not actually implement most 1024 * of the ID registers). 1025 */ 1026 1027 cpu->dtb_compatible = "arm,arm1136"; 1028 set_feature(&cpu->env, ARM_FEATURE_V6); 1029 set_feature(&cpu->env, ARM_FEATURE_VFP); 1030 set_feature(&cpu->env, ARM_FEATURE_DUMMY_C15_REGS); 1031 set_feature(&cpu->env, ARM_FEATURE_CACHE_DIRTY_REG); 1032 set_feature(&cpu->env, ARM_FEATURE_CACHE_BLOCK_OPS); 1033 cpu->midr = 0x4107b362; 1034 cpu->reset_fpsid = 0x410120b4; 1035 cpu->mvfr0 = 0x11111111; 1036 cpu->mvfr1 = 0x00000000; 1037 cpu->ctr = 0x1dd20d2; 1038 cpu->reset_sctlr = 0x00050078; 1039 cpu->id_pfr0 = 0x111; 1040 cpu->id_pfr1 = 0x1; 1041 cpu->id_dfr0 = 0x2; 1042 cpu->id_afr0 = 0x3; 1043 cpu->id_mmfr0 = 0x01130003; 1044 cpu->id_mmfr1 = 0x10030302; 1045 cpu->id_mmfr2 = 0x01222110; 1046 cpu->id_isar0 = 0x00140011; 1047 cpu->id_isar1 = 0x12002111; 1048 cpu->id_isar2 = 0x11231111; 1049 cpu->id_isar3 = 0x01102131; 1050 cpu->id_isar4 = 0x141; 1051 cpu->reset_auxcr = 7; 1052 } 1053 1054 static void arm1136_initfn(Object *obj) 1055 { 1056 ARMCPU *cpu = ARM_CPU(obj); 1057 1058 cpu->dtb_compatible = "arm,arm1136"; 1059 set_feature(&cpu->env, ARM_FEATURE_V6K); 1060 set_feature(&cpu->env, ARM_FEATURE_V6); 1061 set_feature(&cpu->env, ARM_FEATURE_VFP); 1062 set_feature(&cpu->env, ARM_FEATURE_DUMMY_C15_REGS); 1063 set_feature(&cpu->env, ARM_FEATURE_CACHE_DIRTY_REG); 1064 set_feature(&cpu->env, ARM_FEATURE_CACHE_BLOCK_OPS); 1065 cpu->midr = 0x4117b363; 1066 cpu->reset_fpsid = 0x410120b4; 1067 cpu->mvfr0 = 0x11111111; 1068 cpu->mvfr1 = 0x00000000; 1069 cpu->ctr = 0x1dd20d2; 1070 cpu->reset_sctlr = 0x00050078; 1071 cpu->id_pfr0 = 0x111; 1072 cpu->id_pfr1 = 0x1; 1073 cpu->id_dfr0 = 0x2; 1074 cpu->id_afr0 = 0x3; 1075 cpu->id_mmfr0 = 0x01130003; 1076 cpu->id_mmfr1 = 0x10030302; 1077 cpu->id_mmfr2 = 0x01222110; 1078 cpu->id_isar0 = 0x00140011; 1079 cpu->id_isar1 = 0x12002111; 1080 cpu->id_isar2 = 0x11231111; 1081 cpu->id_isar3 = 0x01102131; 1082 cpu->id_isar4 = 0x141; 1083 cpu->reset_auxcr = 7; 1084 } 1085 1086 static void arm1176_initfn(Object *obj) 1087 { 1088 ARMCPU *cpu = ARM_CPU(obj); 1089 1090 cpu->dtb_compatible = "arm,arm1176"; 1091 set_feature(&cpu->env, ARM_FEATURE_V6K); 1092 set_feature(&cpu->env, ARM_FEATURE_VFP); 1093 set_feature(&cpu->env, ARM_FEATURE_VAPA); 1094 set_feature(&cpu->env, ARM_FEATURE_DUMMY_C15_REGS); 1095 set_feature(&cpu->env, ARM_FEATURE_CACHE_DIRTY_REG); 1096 set_feature(&cpu->env, ARM_FEATURE_CACHE_BLOCK_OPS); 1097 set_feature(&cpu->env, ARM_FEATURE_EL3); 1098 cpu->midr = 0x410fb767; 1099 cpu->reset_fpsid = 0x410120b5; 1100 cpu->mvfr0 = 0x11111111; 1101 cpu->mvfr1 = 0x00000000; 1102 cpu->ctr = 0x1dd20d2; 1103 cpu->reset_sctlr = 0x00050078; 1104 cpu->id_pfr0 = 0x111; 1105 cpu->id_pfr1 = 0x11; 1106 cpu->id_dfr0 = 0x33; 1107 cpu->id_afr0 = 0; 1108 cpu->id_mmfr0 = 0x01130003; 1109 cpu->id_mmfr1 = 0x10030302; 1110 cpu->id_mmfr2 = 0x01222100; 1111 cpu->id_isar0 = 0x0140011; 1112 cpu->id_isar1 = 0x12002111; 1113 cpu->id_isar2 = 0x11231121; 1114 cpu->id_isar3 = 0x01102131; 1115 cpu->id_isar4 = 0x01141; 1116 cpu->reset_auxcr = 7; 1117 } 1118 1119 static void arm11mpcore_initfn(Object *obj) 1120 { 1121 ARMCPU *cpu = ARM_CPU(obj); 1122 1123 cpu->dtb_compatible = "arm,arm11mpcore"; 1124 set_feature(&cpu->env, ARM_FEATURE_V6K); 1125 set_feature(&cpu->env, ARM_FEATURE_VFP); 1126 set_feature(&cpu->env, ARM_FEATURE_VAPA); 1127 set_feature(&cpu->env, ARM_FEATURE_MPIDR); 1128 set_feature(&cpu->env, ARM_FEATURE_DUMMY_C15_REGS); 1129 cpu->midr = 0x410fb022; 1130 cpu->reset_fpsid = 0x410120b4; 1131 cpu->mvfr0 = 0x11111111; 1132 cpu->mvfr1 = 0x00000000; 1133 cpu->ctr = 0x1d192992; /* 32K icache 32K dcache */ 1134 cpu->id_pfr0 = 0x111; 1135 cpu->id_pfr1 = 0x1; 1136 cpu->id_dfr0 = 0; 1137 cpu->id_afr0 = 0x2; 1138 cpu->id_mmfr0 = 0x01100103; 1139 cpu->id_mmfr1 = 0x10020302; 1140 cpu->id_mmfr2 = 0x01222000; 1141 cpu->id_isar0 = 0x00100011; 1142 cpu->id_isar1 = 0x12002111; 1143 cpu->id_isar2 = 0x11221011; 1144 cpu->id_isar3 = 0x01102131; 1145 cpu->id_isar4 = 0x141; 1146 cpu->reset_auxcr = 1; 1147 } 1148 1149 static void cortex_m3_initfn(Object *obj) 1150 { 1151 ARMCPU *cpu = ARM_CPU(obj); 1152 set_feature(&cpu->env, ARM_FEATURE_V7); 1153 set_feature(&cpu->env, ARM_FEATURE_M); 1154 cpu->midr = 0x410fc231; 1155 cpu->pmsav7_dregion = 8; 1156 } 1157 1158 static void cortex_m4_initfn(Object *obj) 1159 { 1160 ARMCPU *cpu = ARM_CPU(obj); 1161 1162 set_feature(&cpu->env, ARM_FEATURE_V7); 1163 set_feature(&cpu->env, ARM_FEATURE_M); 1164 set_feature(&cpu->env, ARM_FEATURE_THUMB_DSP); 1165 cpu->midr = 0x410fc240; /* r0p0 */ 1166 cpu->pmsav7_dregion = 8; 1167 } 1168 1169 static void arm_v7m_class_init(ObjectClass *oc, void *data) 1170 { 1171 CPUClass *cc = CPU_CLASS(oc); 1172 1173 #ifndef CONFIG_USER_ONLY 1174 cc->do_interrupt = arm_v7m_cpu_do_interrupt; 1175 #endif 1176 1177 cc->cpu_exec_interrupt = arm_v7m_cpu_exec_interrupt; 1178 } 1179 1180 static const ARMCPRegInfo cortexr5_cp_reginfo[] = { 1181 /* Dummy the TCM region regs for the moment */ 1182 { .name = "ATCM", .cp = 15, .opc1 = 0, .crn = 9, .crm = 1, .opc2 = 0, 1183 .access = PL1_RW, .type = ARM_CP_CONST }, 1184 { .name = "BTCM", .cp = 15, .opc1 = 0, .crn = 9, .crm = 1, .opc2 = 1, 1185 .access = PL1_RW, .type = ARM_CP_CONST }, 1186 { .name = "DCACHE_INVAL", .cp = 15, .opc1 = 0, .crn = 15, .crm = 5, 1187 .opc2 = 0, .access = PL1_W, .type = ARM_CP_NOP }, 1188 REGINFO_SENTINEL 1189 }; 1190 1191 static void cortex_r5_initfn(Object *obj) 1192 { 1193 ARMCPU *cpu = ARM_CPU(obj); 1194 1195 set_feature(&cpu->env, ARM_FEATURE_V7); 1196 set_feature(&cpu->env, ARM_FEATURE_THUMB_DIV); 1197 set_feature(&cpu->env, ARM_FEATURE_ARM_DIV); 1198 set_feature(&cpu->env, ARM_FEATURE_V7MP); 1199 set_feature(&cpu->env, ARM_FEATURE_PMSA); 1200 cpu->midr = 0x411fc153; /* r1p3 */ 1201 cpu->id_pfr0 = 0x0131; 1202 cpu->id_pfr1 = 0x001; 1203 cpu->id_dfr0 = 0x010400; 1204 cpu->id_afr0 = 0x0; 1205 cpu->id_mmfr0 = 0x0210030; 1206 cpu->id_mmfr1 = 0x00000000; 1207 cpu->id_mmfr2 = 0x01200000; 1208 cpu->id_mmfr3 = 0x0211; 1209 cpu->id_isar0 = 0x2101111; 1210 cpu->id_isar1 = 0x13112111; 1211 cpu->id_isar2 = 0x21232141; 1212 cpu->id_isar3 = 0x01112131; 1213 cpu->id_isar4 = 0x0010142; 1214 cpu->id_isar5 = 0x0; 1215 cpu->mp_is_up = true; 1216 cpu->pmsav7_dregion = 16; 1217 define_arm_cp_regs(cpu, cortexr5_cp_reginfo); 1218 } 1219 1220 static const ARMCPRegInfo cortexa8_cp_reginfo[] = { 1221 { .name = "L2LOCKDOWN", .cp = 15, .crn = 9, .crm = 0, .opc1 = 1, .opc2 = 0, 1222 .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0 }, 1223 { .name = "L2AUXCR", .cp = 15, .crn = 9, .crm = 0, .opc1 = 1, .opc2 = 2, 1224 .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0 }, 1225 REGINFO_SENTINEL 1226 }; 1227 1228 static void cortex_a8_initfn(Object *obj) 1229 { 1230 ARMCPU *cpu = ARM_CPU(obj); 1231 1232 cpu->dtb_compatible = "arm,cortex-a8"; 1233 set_feature(&cpu->env, ARM_FEATURE_V7); 1234 set_feature(&cpu->env, ARM_FEATURE_VFP3); 1235 set_feature(&cpu->env, ARM_FEATURE_NEON); 1236 set_feature(&cpu->env, ARM_FEATURE_THUMB2EE); 1237 set_feature(&cpu->env, ARM_FEATURE_DUMMY_C15_REGS); 1238 set_feature(&cpu->env, ARM_FEATURE_EL3); 1239 cpu->midr = 0x410fc080; 1240 cpu->reset_fpsid = 0x410330c0; 1241 cpu->mvfr0 = 0x11110222; 1242 cpu->mvfr1 = 0x00011111; 1243 cpu->ctr = 0x82048004; 1244 cpu->reset_sctlr = 0x00c50078; 1245 cpu->id_pfr0 = 0x1031; 1246 cpu->id_pfr1 = 0x11; 1247 cpu->id_dfr0 = 0x400; 1248 cpu->id_afr0 = 0; 1249 cpu->id_mmfr0 = 0x31100003; 1250 cpu->id_mmfr1 = 0x20000000; 1251 cpu->id_mmfr2 = 0x01202000; 1252 cpu->id_mmfr3 = 0x11; 1253 cpu->id_isar0 = 0x00101111; 1254 cpu->id_isar1 = 0x12112111; 1255 cpu->id_isar2 = 0x21232031; 1256 cpu->id_isar3 = 0x11112131; 1257 cpu->id_isar4 = 0x00111142; 1258 cpu->dbgdidr = 0x15141000; 1259 cpu->clidr = (1 << 27) | (2 << 24) | 3; 1260 cpu->ccsidr[0] = 0xe007e01a; /* 16k L1 dcache. */ 1261 cpu->ccsidr[1] = 0x2007e01a; /* 16k L1 icache. */ 1262 cpu->ccsidr[2] = 0xf0000000; /* No L2 icache. */ 1263 cpu->reset_auxcr = 2; 1264 define_arm_cp_regs(cpu, cortexa8_cp_reginfo); 1265 } 1266 1267 static const ARMCPRegInfo cortexa9_cp_reginfo[] = { 1268 /* power_control should be set to maximum latency. Again, 1269 * default to 0 and set by private hook 1270 */ 1271 { .name = "A9_PWRCTL", .cp = 15, .crn = 15, .crm = 0, .opc1 = 0, .opc2 = 0, 1272 .access = PL1_RW, .resetvalue = 0, 1273 .fieldoffset = offsetof(CPUARMState, cp15.c15_power_control) }, 1274 { .name = "A9_DIAG", .cp = 15, .crn = 15, .crm = 0, .opc1 = 0, .opc2 = 1, 1275 .access = PL1_RW, .resetvalue = 0, 1276 .fieldoffset = offsetof(CPUARMState, cp15.c15_diagnostic) }, 1277 { .name = "A9_PWRDIAG", .cp = 15, .crn = 15, .crm = 0, .opc1 = 0, .opc2 = 2, 1278 .access = PL1_RW, .resetvalue = 0, 1279 .fieldoffset = offsetof(CPUARMState, cp15.c15_power_diagnostic) }, 1280 { .name = "NEONBUSY", .cp = 15, .crn = 15, .crm = 1, .opc1 = 0, .opc2 = 0, 1281 .access = PL1_RW, .resetvalue = 0, .type = ARM_CP_CONST }, 1282 /* TLB lockdown control */ 1283 { .name = "TLB_LOCKR", .cp = 15, .crn = 15, .crm = 4, .opc1 = 5, .opc2 = 2, 1284 .access = PL1_W, .resetvalue = 0, .type = ARM_CP_NOP }, 1285 { .name = "TLB_LOCKW", .cp = 15, .crn = 15, .crm = 4, .opc1 = 5, .opc2 = 4, 1286 .access = PL1_W, .resetvalue = 0, .type = ARM_CP_NOP }, 1287 { .name = "TLB_VA", .cp = 15, .crn = 15, .crm = 5, .opc1 = 5, .opc2 = 2, 1288 .access = PL1_RW, .resetvalue = 0, .type = ARM_CP_CONST }, 1289 { .name = "TLB_PA", .cp = 15, .crn = 15, .crm = 6, .opc1 = 5, .opc2 = 2, 1290 .access = PL1_RW, .resetvalue = 0, .type = ARM_CP_CONST }, 1291 { .name = "TLB_ATTR", .cp = 15, .crn = 15, .crm = 7, .opc1 = 5, .opc2 = 2, 1292 .access = PL1_RW, .resetvalue = 0, .type = ARM_CP_CONST }, 1293 REGINFO_SENTINEL 1294 }; 1295 1296 static void cortex_a9_initfn(Object *obj) 1297 { 1298 ARMCPU *cpu = ARM_CPU(obj); 1299 1300 cpu->dtb_compatible = "arm,cortex-a9"; 1301 set_feature(&cpu->env, ARM_FEATURE_V7); 1302 set_feature(&cpu->env, ARM_FEATURE_VFP3); 1303 set_feature(&cpu->env, ARM_FEATURE_VFP_FP16); 1304 set_feature(&cpu->env, ARM_FEATURE_NEON); 1305 set_feature(&cpu->env, ARM_FEATURE_THUMB2EE); 1306 set_feature(&cpu->env, ARM_FEATURE_EL3); 1307 /* Note that A9 supports the MP extensions even for 1308 * A9UP and single-core A9MP (which are both different 1309 * and valid configurations; we don't model A9UP). 1310 */ 1311 set_feature(&cpu->env, ARM_FEATURE_V7MP); 1312 set_feature(&cpu->env, ARM_FEATURE_CBAR); 1313 cpu->midr = 0x410fc090; 1314 cpu->reset_fpsid = 0x41033090; 1315 cpu->mvfr0 = 0x11110222; 1316 cpu->mvfr1 = 0x01111111; 1317 cpu->ctr = 0x80038003; 1318 cpu->reset_sctlr = 0x00c50078; 1319 cpu->id_pfr0 = 0x1031; 1320 cpu->id_pfr1 = 0x11; 1321 cpu->id_dfr0 = 0x000; 1322 cpu->id_afr0 = 0; 1323 cpu->id_mmfr0 = 0x00100103; 1324 cpu->id_mmfr1 = 0x20000000; 1325 cpu->id_mmfr2 = 0x01230000; 1326 cpu->id_mmfr3 = 0x00002111; 1327 cpu->id_isar0 = 0x00101111; 1328 cpu->id_isar1 = 0x13112111; 1329 cpu->id_isar2 = 0x21232041; 1330 cpu->id_isar3 = 0x11112131; 1331 cpu->id_isar4 = 0x00111142; 1332 cpu->dbgdidr = 0x35141000; 1333 cpu->clidr = (1 << 27) | (1 << 24) | 3; 1334 cpu->ccsidr[0] = 0xe00fe019; /* 16k L1 dcache. */ 1335 cpu->ccsidr[1] = 0x200fe019; /* 16k L1 icache. */ 1336 define_arm_cp_regs(cpu, cortexa9_cp_reginfo); 1337 } 1338 1339 #ifndef CONFIG_USER_ONLY 1340 static uint64_t a15_l2ctlr_read(CPUARMState *env, const ARMCPRegInfo *ri) 1341 { 1342 /* Linux wants the number of processors from here. 1343 * Might as well set the interrupt-controller bit too. 1344 */ 1345 return ((smp_cpus - 1) << 24) | (1 << 23); 1346 } 1347 #endif 1348 1349 static const ARMCPRegInfo cortexa15_cp_reginfo[] = { 1350 #ifndef CONFIG_USER_ONLY 1351 { .name = "L2CTLR", .cp = 15, .crn = 9, .crm = 0, .opc1 = 1, .opc2 = 2, 1352 .access = PL1_RW, .resetvalue = 0, .readfn = a15_l2ctlr_read, 1353 .writefn = arm_cp_write_ignore, }, 1354 #endif 1355 { .name = "L2ECTLR", .cp = 15, .crn = 9, .crm = 0, .opc1 = 1, .opc2 = 3, 1356 .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0 }, 1357 REGINFO_SENTINEL 1358 }; 1359 1360 static void cortex_a7_initfn(Object *obj) 1361 { 1362 ARMCPU *cpu = ARM_CPU(obj); 1363 1364 cpu->dtb_compatible = "arm,cortex-a7"; 1365 set_feature(&cpu->env, ARM_FEATURE_V7); 1366 set_feature(&cpu->env, ARM_FEATURE_VFP4); 1367 set_feature(&cpu->env, ARM_FEATURE_NEON); 1368 set_feature(&cpu->env, ARM_FEATURE_THUMB2EE); 1369 set_feature(&cpu->env, ARM_FEATURE_ARM_DIV); 1370 set_feature(&cpu->env, ARM_FEATURE_GENERIC_TIMER); 1371 set_feature(&cpu->env, ARM_FEATURE_DUMMY_C15_REGS); 1372 set_feature(&cpu->env, ARM_FEATURE_CBAR_RO); 1373 set_feature(&cpu->env, ARM_FEATURE_LPAE); 1374 set_feature(&cpu->env, ARM_FEATURE_EL3); 1375 cpu->kvm_target = QEMU_KVM_ARM_TARGET_CORTEX_A7; 1376 cpu->midr = 0x410fc075; 1377 cpu->reset_fpsid = 0x41023075; 1378 cpu->mvfr0 = 0x10110222; 1379 cpu->mvfr1 = 0x11111111; 1380 cpu->ctr = 0x84448003; 1381 cpu->reset_sctlr = 0x00c50078; 1382 cpu->id_pfr0 = 0x00001131; 1383 cpu->id_pfr1 = 0x00011011; 1384 cpu->id_dfr0 = 0x02010555; 1385 cpu->pmceid0 = 0x00000000; 1386 cpu->pmceid1 = 0x00000000; 1387 cpu->id_afr0 = 0x00000000; 1388 cpu->id_mmfr0 = 0x10101105; 1389 cpu->id_mmfr1 = 0x40000000; 1390 cpu->id_mmfr2 = 0x01240000; 1391 cpu->id_mmfr3 = 0x02102211; 1392 cpu->id_isar0 = 0x01101110; 1393 cpu->id_isar1 = 0x13112111; 1394 cpu->id_isar2 = 0x21232041; 1395 cpu->id_isar3 = 0x11112131; 1396 cpu->id_isar4 = 0x10011142; 1397 cpu->dbgdidr = 0x3515f005; 1398 cpu->clidr = 0x0a200023; 1399 cpu->ccsidr[0] = 0x701fe00a; /* 32K L1 dcache */ 1400 cpu->ccsidr[1] = 0x201fe00a; /* 32K L1 icache */ 1401 cpu->ccsidr[2] = 0x711fe07a; /* 4096K L2 unified cache */ 1402 define_arm_cp_regs(cpu, cortexa15_cp_reginfo); /* Same as A15 */ 1403 } 1404 1405 static void cortex_a15_initfn(Object *obj) 1406 { 1407 ARMCPU *cpu = ARM_CPU(obj); 1408 1409 cpu->dtb_compatible = "arm,cortex-a15"; 1410 set_feature(&cpu->env, ARM_FEATURE_V7); 1411 set_feature(&cpu->env, ARM_FEATURE_VFP4); 1412 set_feature(&cpu->env, ARM_FEATURE_NEON); 1413 set_feature(&cpu->env, ARM_FEATURE_THUMB2EE); 1414 set_feature(&cpu->env, ARM_FEATURE_ARM_DIV); 1415 set_feature(&cpu->env, ARM_FEATURE_GENERIC_TIMER); 1416 set_feature(&cpu->env, ARM_FEATURE_DUMMY_C15_REGS); 1417 set_feature(&cpu->env, ARM_FEATURE_CBAR_RO); 1418 set_feature(&cpu->env, ARM_FEATURE_LPAE); 1419 set_feature(&cpu->env, ARM_FEATURE_EL3); 1420 cpu->kvm_target = QEMU_KVM_ARM_TARGET_CORTEX_A15; 1421 cpu->midr = 0x412fc0f1; 1422 cpu->reset_fpsid = 0x410430f0; 1423 cpu->mvfr0 = 0x10110222; 1424 cpu->mvfr1 = 0x11111111; 1425 cpu->ctr = 0x8444c004; 1426 cpu->reset_sctlr = 0x00c50078; 1427 cpu->id_pfr0 = 0x00001131; 1428 cpu->id_pfr1 = 0x00011011; 1429 cpu->id_dfr0 = 0x02010555; 1430 cpu->pmceid0 = 0x0000000; 1431 cpu->pmceid1 = 0x00000000; 1432 cpu->id_afr0 = 0x00000000; 1433 cpu->id_mmfr0 = 0x10201105; 1434 cpu->id_mmfr1 = 0x20000000; 1435 cpu->id_mmfr2 = 0x01240000; 1436 cpu->id_mmfr3 = 0x02102211; 1437 cpu->id_isar0 = 0x02101110; 1438 cpu->id_isar1 = 0x13112111; 1439 cpu->id_isar2 = 0x21232041; 1440 cpu->id_isar3 = 0x11112131; 1441 cpu->id_isar4 = 0x10011142; 1442 cpu->dbgdidr = 0x3515f021; 1443 cpu->clidr = 0x0a200023; 1444 cpu->ccsidr[0] = 0x701fe00a; /* 32K L1 dcache */ 1445 cpu->ccsidr[1] = 0x201fe00a; /* 32K L1 icache */ 1446 cpu->ccsidr[2] = 0x711fe07a; /* 4096K L2 unified cache */ 1447 define_arm_cp_regs(cpu, cortexa15_cp_reginfo); 1448 } 1449 1450 static void ti925t_initfn(Object *obj) 1451 { 1452 ARMCPU *cpu = ARM_CPU(obj); 1453 set_feature(&cpu->env, ARM_FEATURE_V4T); 1454 set_feature(&cpu->env, ARM_FEATURE_OMAPCP); 1455 cpu->midr = ARM_CPUID_TI925T; 1456 cpu->ctr = 0x5109149; 1457 cpu->reset_sctlr = 0x00000070; 1458 } 1459 1460 static void sa1100_initfn(Object *obj) 1461 { 1462 ARMCPU *cpu = ARM_CPU(obj); 1463 1464 cpu->dtb_compatible = "intel,sa1100"; 1465 set_feature(&cpu->env, ARM_FEATURE_STRONGARM); 1466 set_feature(&cpu->env, ARM_FEATURE_DUMMY_C15_REGS); 1467 cpu->midr = 0x4401A11B; 1468 cpu->reset_sctlr = 0x00000070; 1469 } 1470 1471 static void sa1110_initfn(Object *obj) 1472 { 1473 ARMCPU *cpu = ARM_CPU(obj); 1474 set_feature(&cpu->env, ARM_FEATURE_STRONGARM); 1475 set_feature(&cpu->env, ARM_FEATURE_DUMMY_C15_REGS); 1476 cpu->midr = 0x6901B119; 1477 cpu->reset_sctlr = 0x00000070; 1478 } 1479 1480 static void pxa250_initfn(Object *obj) 1481 { 1482 ARMCPU *cpu = ARM_CPU(obj); 1483 1484 cpu->dtb_compatible = "marvell,xscale"; 1485 set_feature(&cpu->env, ARM_FEATURE_V5); 1486 set_feature(&cpu->env, ARM_FEATURE_XSCALE); 1487 cpu->midr = 0x69052100; 1488 cpu->ctr = 0xd172172; 1489 cpu->reset_sctlr = 0x00000078; 1490 } 1491 1492 static void pxa255_initfn(Object *obj) 1493 { 1494 ARMCPU *cpu = ARM_CPU(obj); 1495 1496 cpu->dtb_compatible = "marvell,xscale"; 1497 set_feature(&cpu->env, ARM_FEATURE_V5); 1498 set_feature(&cpu->env, ARM_FEATURE_XSCALE); 1499 cpu->midr = 0x69052d00; 1500 cpu->ctr = 0xd172172; 1501 cpu->reset_sctlr = 0x00000078; 1502 } 1503 1504 static void pxa260_initfn(Object *obj) 1505 { 1506 ARMCPU *cpu = ARM_CPU(obj); 1507 1508 cpu->dtb_compatible = "marvell,xscale"; 1509 set_feature(&cpu->env, ARM_FEATURE_V5); 1510 set_feature(&cpu->env, ARM_FEATURE_XSCALE); 1511 cpu->midr = 0x69052903; 1512 cpu->ctr = 0xd172172; 1513 cpu->reset_sctlr = 0x00000078; 1514 } 1515 1516 static void pxa261_initfn(Object *obj) 1517 { 1518 ARMCPU *cpu = ARM_CPU(obj); 1519 1520 cpu->dtb_compatible = "marvell,xscale"; 1521 set_feature(&cpu->env, ARM_FEATURE_V5); 1522 set_feature(&cpu->env, ARM_FEATURE_XSCALE); 1523 cpu->midr = 0x69052d05; 1524 cpu->ctr = 0xd172172; 1525 cpu->reset_sctlr = 0x00000078; 1526 } 1527 1528 static void pxa262_initfn(Object *obj) 1529 { 1530 ARMCPU *cpu = ARM_CPU(obj); 1531 1532 cpu->dtb_compatible = "marvell,xscale"; 1533 set_feature(&cpu->env, ARM_FEATURE_V5); 1534 set_feature(&cpu->env, ARM_FEATURE_XSCALE); 1535 cpu->midr = 0x69052d06; 1536 cpu->ctr = 0xd172172; 1537 cpu->reset_sctlr = 0x00000078; 1538 } 1539 1540 static void pxa270a0_initfn(Object *obj) 1541 { 1542 ARMCPU *cpu = ARM_CPU(obj); 1543 1544 cpu->dtb_compatible = "marvell,xscale"; 1545 set_feature(&cpu->env, ARM_FEATURE_V5); 1546 set_feature(&cpu->env, ARM_FEATURE_XSCALE); 1547 set_feature(&cpu->env, ARM_FEATURE_IWMMXT); 1548 cpu->midr = 0x69054110; 1549 cpu->ctr = 0xd172172; 1550 cpu->reset_sctlr = 0x00000078; 1551 } 1552 1553 static void pxa270a1_initfn(Object *obj) 1554 { 1555 ARMCPU *cpu = ARM_CPU(obj); 1556 1557 cpu->dtb_compatible = "marvell,xscale"; 1558 set_feature(&cpu->env, ARM_FEATURE_V5); 1559 set_feature(&cpu->env, ARM_FEATURE_XSCALE); 1560 set_feature(&cpu->env, ARM_FEATURE_IWMMXT); 1561 cpu->midr = 0x69054111; 1562 cpu->ctr = 0xd172172; 1563 cpu->reset_sctlr = 0x00000078; 1564 } 1565 1566 static void pxa270b0_initfn(Object *obj) 1567 { 1568 ARMCPU *cpu = ARM_CPU(obj); 1569 1570 cpu->dtb_compatible = "marvell,xscale"; 1571 set_feature(&cpu->env, ARM_FEATURE_V5); 1572 set_feature(&cpu->env, ARM_FEATURE_XSCALE); 1573 set_feature(&cpu->env, ARM_FEATURE_IWMMXT); 1574 cpu->midr = 0x69054112; 1575 cpu->ctr = 0xd172172; 1576 cpu->reset_sctlr = 0x00000078; 1577 } 1578 1579 static void pxa270b1_initfn(Object *obj) 1580 { 1581 ARMCPU *cpu = ARM_CPU(obj); 1582 1583 cpu->dtb_compatible = "marvell,xscale"; 1584 set_feature(&cpu->env, ARM_FEATURE_V5); 1585 set_feature(&cpu->env, ARM_FEATURE_XSCALE); 1586 set_feature(&cpu->env, ARM_FEATURE_IWMMXT); 1587 cpu->midr = 0x69054113; 1588 cpu->ctr = 0xd172172; 1589 cpu->reset_sctlr = 0x00000078; 1590 } 1591 1592 static void pxa270c0_initfn(Object *obj) 1593 { 1594 ARMCPU *cpu = ARM_CPU(obj); 1595 1596 cpu->dtb_compatible = "marvell,xscale"; 1597 set_feature(&cpu->env, ARM_FEATURE_V5); 1598 set_feature(&cpu->env, ARM_FEATURE_XSCALE); 1599 set_feature(&cpu->env, ARM_FEATURE_IWMMXT); 1600 cpu->midr = 0x69054114; 1601 cpu->ctr = 0xd172172; 1602 cpu->reset_sctlr = 0x00000078; 1603 } 1604 1605 static void pxa270c5_initfn(Object *obj) 1606 { 1607 ARMCPU *cpu = ARM_CPU(obj); 1608 1609 cpu->dtb_compatible = "marvell,xscale"; 1610 set_feature(&cpu->env, ARM_FEATURE_V5); 1611 set_feature(&cpu->env, ARM_FEATURE_XSCALE); 1612 set_feature(&cpu->env, ARM_FEATURE_IWMMXT); 1613 cpu->midr = 0x69054117; 1614 cpu->ctr = 0xd172172; 1615 cpu->reset_sctlr = 0x00000078; 1616 } 1617 1618 #ifdef CONFIG_USER_ONLY 1619 static void arm_any_initfn(Object *obj) 1620 { 1621 ARMCPU *cpu = ARM_CPU(obj); 1622 set_feature(&cpu->env, ARM_FEATURE_V8); 1623 set_feature(&cpu->env, ARM_FEATURE_VFP4); 1624 set_feature(&cpu->env, ARM_FEATURE_NEON); 1625 set_feature(&cpu->env, ARM_FEATURE_THUMB2EE); 1626 set_feature(&cpu->env, ARM_FEATURE_V8_AES); 1627 set_feature(&cpu->env, ARM_FEATURE_V8_SHA1); 1628 set_feature(&cpu->env, ARM_FEATURE_V8_SHA256); 1629 set_feature(&cpu->env, ARM_FEATURE_V8_PMULL); 1630 set_feature(&cpu->env, ARM_FEATURE_CRC); 1631 cpu->midr = 0xffffffff; 1632 } 1633 #endif 1634 1635 #endif /* !defined(CONFIG_USER_ONLY) || !defined(TARGET_AARCH64) */ 1636 1637 typedef struct ARMCPUInfo { 1638 const char *name; 1639 void (*initfn)(Object *obj); 1640 void (*class_init)(ObjectClass *oc, void *data); 1641 } ARMCPUInfo; 1642 1643 static const ARMCPUInfo arm_cpus[] = { 1644 #if !defined(CONFIG_USER_ONLY) || !defined(TARGET_AARCH64) 1645 { .name = "arm926", .initfn = arm926_initfn }, 1646 { .name = "arm946", .initfn = arm946_initfn }, 1647 { .name = "arm1026", .initfn = arm1026_initfn }, 1648 /* What QEMU calls "arm1136-r2" is actually the 1136 r0p2, i.e. an 1649 * older core than plain "arm1136". In particular this does not 1650 * have the v6K features. 1651 */ 1652 { .name = "arm1136-r2", .initfn = arm1136_r2_initfn }, 1653 { .name = "arm1136", .initfn = arm1136_initfn }, 1654 { .name = "arm1176", .initfn = arm1176_initfn }, 1655 { .name = "arm11mpcore", .initfn = arm11mpcore_initfn }, 1656 { .name = "cortex-m3", .initfn = cortex_m3_initfn, 1657 .class_init = arm_v7m_class_init }, 1658 { .name = "cortex-m4", .initfn = cortex_m4_initfn, 1659 .class_init = arm_v7m_class_init }, 1660 { .name = "cortex-r5", .initfn = cortex_r5_initfn }, 1661 { .name = "cortex-a7", .initfn = cortex_a7_initfn }, 1662 { .name = "cortex-a8", .initfn = cortex_a8_initfn }, 1663 { .name = "cortex-a9", .initfn = cortex_a9_initfn }, 1664 { .name = "cortex-a15", .initfn = cortex_a15_initfn }, 1665 { .name = "ti925t", .initfn = ti925t_initfn }, 1666 { .name = "sa1100", .initfn = sa1100_initfn }, 1667 { .name = "sa1110", .initfn = sa1110_initfn }, 1668 { .name = "pxa250", .initfn = pxa250_initfn }, 1669 { .name = "pxa255", .initfn = pxa255_initfn }, 1670 { .name = "pxa260", .initfn = pxa260_initfn }, 1671 { .name = "pxa261", .initfn = pxa261_initfn }, 1672 { .name = "pxa262", .initfn = pxa262_initfn }, 1673 /* "pxa270" is an alias for "pxa270-a0" */ 1674 { .name = "pxa270", .initfn = pxa270a0_initfn }, 1675 { .name = "pxa270-a0", .initfn = pxa270a0_initfn }, 1676 { .name = "pxa270-a1", .initfn = pxa270a1_initfn }, 1677 { .name = "pxa270-b0", .initfn = pxa270b0_initfn }, 1678 { .name = "pxa270-b1", .initfn = pxa270b1_initfn }, 1679 { .name = "pxa270-c0", .initfn = pxa270c0_initfn }, 1680 { .name = "pxa270-c5", .initfn = pxa270c5_initfn }, 1681 #ifdef CONFIG_USER_ONLY 1682 { .name = "any", .initfn = arm_any_initfn }, 1683 #endif 1684 #endif 1685 { .name = NULL } 1686 }; 1687 1688 static Property arm_cpu_properties[] = { 1689 DEFINE_PROP_BOOL("start-powered-off", ARMCPU, start_powered_off, false), 1690 DEFINE_PROP_UINT32("psci-conduit", ARMCPU, psci_conduit, 0), 1691 DEFINE_PROP_UINT32("midr", ARMCPU, midr, 0), 1692 DEFINE_PROP_UINT64("mp-affinity", ARMCPU, 1693 mp_affinity, ARM64_AFFINITY_INVALID), 1694 DEFINE_PROP_INT32("node-id", ARMCPU, node_id, CPU_UNSET_NUMA_NODE_ID), 1695 DEFINE_PROP_END_OF_LIST() 1696 }; 1697 1698 #ifdef CONFIG_USER_ONLY 1699 static int arm_cpu_handle_mmu_fault(CPUState *cs, vaddr address, int rw, 1700 int mmu_idx) 1701 { 1702 ARMCPU *cpu = ARM_CPU(cs); 1703 CPUARMState *env = &cpu->env; 1704 1705 env->exception.vaddress = address; 1706 if (rw == 2) { 1707 cs->exception_index = EXCP_PREFETCH_ABORT; 1708 } else { 1709 cs->exception_index = EXCP_DATA_ABORT; 1710 } 1711 return 1; 1712 } 1713 #endif 1714 1715 static gchar *arm_gdb_arch_name(CPUState *cs) 1716 { 1717 ARMCPU *cpu = ARM_CPU(cs); 1718 CPUARMState *env = &cpu->env; 1719 1720 if (arm_feature(env, ARM_FEATURE_IWMMXT)) { 1721 return g_strdup("iwmmxt"); 1722 } 1723 return g_strdup("arm"); 1724 } 1725 1726 static void arm_cpu_class_init(ObjectClass *oc, void *data) 1727 { 1728 ARMCPUClass *acc = ARM_CPU_CLASS(oc); 1729 CPUClass *cc = CPU_CLASS(acc); 1730 DeviceClass *dc = DEVICE_CLASS(oc); 1731 1732 acc->parent_realize = dc->realize; 1733 dc->realize = arm_cpu_realizefn; 1734 dc->props = arm_cpu_properties; 1735 1736 acc->parent_reset = cc->reset; 1737 cc->reset = arm_cpu_reset; 1738 1739 cc->class_by_name = arm_cpu_class_by_name; 1740 cc->has_work = arm_cpu_has_work; 1741 cc->cpu_exec_interrupt = arm_cpu_exec_interrupt; 1742 cc->dump_state = arm_cpu_dump_state; 1743 cc->set_pc = arm_cpu_set_pc; 1744 cc->gdb_read_register = arm_cpu_gdb_read_register; 1745 cc->gdb_write_register = arm_cpu_gdb_write_register; 1746 #ifdef CONFIG_USER_ONLY 1747 cc->handle_mmu_fault = arm_cpu_handle_mmu_fault; 1748 #else 1749 cc->do_interrupt = arm_cpu_do_interrupt; 1750 cc->do_unaligned_access = arm_cpu_do_unaligned_access; 1751 cc->do_transaction_failed = arm_cpu_do_transaction_failed; 1752 cc->get_phys_page_attrs_debug = arm_cpu_get_phys_page_attrs_debug; 1753 cc->asidx_from_attrs = arm_asidx_from_attrs; 1754 cc->vmsd = &vmstate_arm_cpu; 1755 cc->virtio_is_big_endian = arm_cpu_virtio_is_big_endian; 1756 cc->write_elf64_note = arm_cpu_write_elf64_note; 1757 cc->write_elf32_note = arm_cpu_write_elf32_note; 1758 #endif 1759 cc->gdb_num_core_regs = 26; 1760 cc->gdb_core_xml_file = "arm-core.xml"; 1761 cc->gdb_arch_name = arm_gdb_arch_name; 1762 cc->gdb_stop_before_watchpoint = true; 1763 cc->debug_excp_handler = arm_debug_excp_handler; 1764 cc->debug_check_watchpoint = arm_debug_check_watchpoint; 1765 #if !defined(CONFIG_USER_ONLY) 1766 cc->adjust_watchpoint_address = arm_adjust_watchpoint_address; 1767 #endif 1768 1769 cc->disas_set_info = arm_disas_set_info; 1770 #ifdef CONFIG_TCG 1771 cc->tcg_initialize = arm_translate_init; 1772 #endif 1773 } 1774 1775 static void cpu_register(const ARMCPUInfo *info) 1776 { 1777 TypeInfo type_info = { 1778 .parent = TYPE_ARM_CPU, 1779 .instance_size = sizeof(ARMCPU), 1780 .instance_init = info->initfn, 1781 .class_size = sizeof(ARMCPUClass), 1782 .class_init = info->class_init, 1783 }; 1784 1785 type_info.name = g_strdup_printf("%s-" TYPE_ARM_CPU, info->name); 1786 type_register(&type_info); 1787 g_free((void *)type_info.name); 1788 } 1789 1790 static const TypeInfo arm_cpu_type_info = { 1791 .name = TYPE_ARM_CPU, 1792 .parent = TYPE_CPU, 1793 .instance_size = sizeof(ARMCPU), 1794 .instance_init = arm_cpu_initfn, 1795 .instance_post_init = arm_cpu_post_init, 1796 .instance_finalize = arm_cpu_finalizefn, 1797 .abstract = true, 1798 .class_size = sizeof(ARMCPUClass), 1799 .class_init = arm_cpu_class_init, 1800 }; 1801 1802 static void arm_cpu_register_types(void) 1803 { 1804 const ARMCPUInfo *info = arm_cpus; 1805 1806 type_register_static(&arm_cpu_type_info); 1807 1808 while (info->name) { 1809 cpu_register(info); 1810 info++; 1811 } 1812 } 1813 1814 type_init(arm_cpu_register_types) 1815