1 /* 2 * QEMU ARM CPU 3 * 4 * Copyright (c) 2012 SUSE LINUX Products GmbH 5 * 6 * This program is free software; you can redistribute it and/or 7 * modify it under the terms of the GNU General Public License 8 * as published by the Free Software Foundation; either version 2 9 * of the License, or (at your option) any later version. 10 * 11 * This program is distributed in the hope that it will be useful, 12 * but WITHOUT ANY WARRANTY; without even the implied warranty of 13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 14 * GNU General Public License for more details. 15 * 16 * You should have received a copy of the GNU General Public License 17 * along with this program; if not, see 18 * <http://www.gnu.org/licenses/gpl-2.0.html> 19 */ 20 21 #include "qemu/osdep.h" 22 #include "qemu/qemu-print.h" 23 #include "qemu/timer.h" 24 #include "qemu/log.h" 25 #include "exec/page-vary.h" 26 #include "target/arm/idau.h" 27 #include "qemu/module.h" 28 #include "qapi/error.h" 29 #include "cpu.h" 30 #ifdef CONFIG_TCG 31 #include "hw/core/tcg-cpu-ops.h" 32 #endif /* CONFIG_TCG */ 33 #include "internals.h" 34 #include "exec/exec-all.h" 35 #include "hw/qdev-properties.h" 36 #if !defined(CONFIG_USER_ONLY) 37 #include "hw/loader.h" 38 #include "hw/boards.h" 39 #endif 40 #include "sysemu/tcg.h" 41 #include "sysemu/qtest.h" 42 #include "sysemu/hw_accel.h" 43 #include "kvm_arm.h" 44 #include "disas/capstone.h" 45 #include "fpu/softfloat.h" 46 #include "cpregs.h" 47 48 static void arm_cpu_set_pc(CPUState *cs, vaddr value) 49 { 50 ARMCPU *cpu = ARM_CPU(cs); 51 CPUARMState *env = &cpu->env; 52 53 if (is_a64(env)) { 54 env->pc = value; 55 env->thumb = false; 56 } else { 57 env->regs[15] = value & ~1; 58 env->thumb = value & 1; 59 } 60 } 61 62 static vaddr arm_cpu_get_pc(CPUState *cs) 63 { 64 ARMCPU *cpu = ARM_CPU(cs); 65 CPUARMState *env = &cpu->env; 66 67 if (is_a64(env)) { 68 return env->pc; 69 } else { 70 return env->regs[15]; 71 } 72 } 73 74 #ifdef CONFIG_TCG 75 void arm_cpu_synchronize_from_tb(CPUState *cs, 76 const TranslationBlock *tb) 77 { 78 /* The program counter is always up to date with TARGET_TB_PCREL. */ 79 if (!TARGET_TB_PCREL) { 80 CPUARMState *env = cs->env_ptr; 81 /* 82 * It's OK to look at env for the current mode here, because it's 83 * never possible for an AArch64 TB to chain to an AArch32 TB. 84 */ 85 if (is_a64(env)) { 86 env->pc = tb_pc(tb); 87 } else { 88 env->regs[15] = tb_pc(tb); 89 } 90 } 91 } 92 93 void arm_restore_state_to_opc(CPUState *cs, 94 const TranslationBlock *tb, 95 const uint64_t *data) 96 { 97 CPUARMState *env = cs->env_ptr; 98 99 if (is_a64(env)) { 100 if (TARGET_TB_PCREL) { 101 env->pc = (env->pc & TARGET_PAGE_MASK) | data[0]; 102 } else { 103 env->pc = data[0]; 104 } 105 env->condexec_bits = 0; 106 env->exception.syndrome = data[2] << ARM_INSN_START_WORD2_SHIFT; 107 } else { 108 if (TARGET_TB_PCREL) { 109 env->regs[15] = (env->regs[15] & TARGET_PAGE_MASK) | data[0]; 110 } else { 111 env->regs[15] = data[0]; 112 } 113 env->condexec_bits = data[1]; 114 env->exception.syndrome = data[2] << ARM_INSN_START_WORD2_SHIFT; 115 } 116 } 117 #endif /* CONFIG_TCG */ 118 119 static bool arm_cpu_has_work(CPUState *cs) 120 { 121 ARMCPU *cpu = ARM_CPU(cs); 122 123 return (cpu->power_state != PSCI_OFF) 124 && cs->interrupt_request & 125 (CPU_INTERRUPT_FIQ | CPU_INTERRUPT_HARD 126 | CPU_INTERRUPT_VFIQ | CPU_INTERRUPT_VIRQ | CPU_INTERRUPT_VSERR 127 | CPU_INTERRUPT_EXITTB); 128 } 129 130 void arm_register_pre_el_change_hook(ARMCPU *cpu, ARMELChangeHookFn *hook, 131 void *opaque) 132 { 133 ARMELChangeHook *entry = g_new0(ARMELChangeHook, 1); 134 135 entry->hook = hook; 136 entry->opaque = opaque; 137 138 QLIST_INSERT_HEAD(&cpu->pre_el_change_hooks, entry, node); 139 } 140 141 void arm_register_el_change_hook(ARMCPU *cpu, ARMELChangeHookFn *hook, 142 void *opaque) 143 { 144 ARMELChangeHook *entry = g_new0(ARMELChangeHook, 1); 145 146 entry->hook = hook; 147 entry->opaque = opaque; 148 149 QLIST_INSERT_HEAD(&cpu->el_change_hooks, entry, node); 150 } 151 152 static void cp_reg_reset(gpointer key, gpointer value, gpointer opaque) 153 { 154 /* Reset a single ARMCPRegInfo register */ 155 ARMCPRegInfo *ri = value; 156 ARMCPU *cpu = opaque; 157 158 if (ri->type & (ARM_CP_SPECIAL_MASK | ARM_CP_ALIAS)) { 159 return; 160 } 161 162 if (ri->resetfn) { 163 ri->resetfn(&cpu->env, ri); 164 return; 165 } 166 167 /* A zero offset is never possible as it would be regs[0] 168 * so we use it to indicate that reset is being handled elsewhere. 169 * This is basically only used for fields in non-core coprocessors 170 * (like the pxa2xx ones). 171 */ 172 if (!ri->fieldoffset) { 173 return; 174 } 175 176 if (cpreg_field_is_64bit(ri)) { 177 CPREG_FIELD64(&cpu->env, ri) = ri->resetvalue; 178 } else { 179 CPREG_FIELD32(&cpu->env, ri) = ri->resetvalue; 180 } 181 } 182 183 static void cp_reg_check_reset(gpointer key, gpointer value, gpointer opaque) 184 { 185 /* Purely an assertion check: we've already done reset once, 186 * so now check that running the reset for the cpreg doesn't 187 * change its value. This traps bugs where two different cpregs 188 * both try to reset the same state field but to different values. 189 */ 190 ARMCPRegInfo *ri = value; 191 ARMCPU *cpu = opaque; 192 uint64_t oldvalue, newvalue; 193 194 if (ri->type & (ARM_CP_SPECIAL_MASK | ARM_CP_ALIAS | ARM_CP_NO_RAW)) { 195 return; 196 } 197 198 oldvalue = read_raw_cp_reg(&cpu->env, ri); 199 cp_reg_reset(key, value, opaque); 200 newvalue = read_raw_cp_reg(&cpu->env, ri); 201 assert(oldvalue == newvalue); 202 } 203 204 static void arm_cpu_reset_hold(Object *obj) 205 { 206 CPUState *s = CPU(obj); 207 ARMCPU *cpu = ARM_CPU(s); 208 ARMCPUClass *acc = ARM_CPU_GET_CLASS(cpu); 209 CPUARMState *env = &cpu->env; 210 211 if (acc->parent_phases.hold) { 212 acc->parent_phases.hold(obj); 213 } 214 215 memset(env, 0, offsetof(CPUARMState, end_reset_fields)); 216 217 g_hash_table_foreach(cpu->cp_regs, cp_reg_reset, cpu); 218 g_hash_table_foreach(cpu->cp_regs, cp_reg_check_reset, cpu); 219 220 env->vfp.xregs[ARM_VFP_FPSID] = cpu->reset_fpsid; 221 env->vfp.xregs[ARM_VFP_MVFR0] = cpu->isar.mvfr0; 222 env->vfp.xregs[ARM_VFP_MVFR1] = cpu->isar.mvfr1; 223 env->vfp.xregs[ARM_VFP_MVFR2] = cpu->isar.mvfr2; 224 225 cpu->power_state = s->start_powered_off ? PSCI_OFF : PSCI_ON; 226 227 if (arm_feature(env, ARM_FEATURE_IWMMXT)) { 228 env->iwmmxt.cregs[ARM_IWMMXT_wCID] = 0x69051000 | 'Q'; 229 } 230 231 if (arm_feature(env, ARM_FEATURE_AARCH64)) { 232 /* 64 bit CPUs always start in 64 bit mode */ 233 env->aarch64 = true; 234 #if defined(CONFIG_USER_ONLY) 235 env->pstate = PSTATE_MODE_EL0t; 236 /* Userspace expects access to DC ZVA, CTL_EL0 and the cache ops */ 237 env->cp15.sctlr_el[1] |= SCTLR_UCT | SCTLR_UCI | SCTLR_DZE; 238 /* Enable all PAC keys. */ 239 env->cp15.sctlr_el[1] |= (SCTLR_EnIA | SCTLR_EnIB | 240 SCTLR_EnDA | SCTLR_EnDB); 241 /* Trap on btype=3 for PACIxSP. */ 242 env->cp15.sctlr_el[1] |= SCTLR_BT0; 243 /* and to the FP/Neon instructions */ 244 env->cp15.cpacr_el1 = FIELD_DP64(env->cp15.cpacr_el1, 245 CPACR_EL1, FPEN, 3); 246 /* and to the SVE instructions, with default vector length */ 247 if (cpu_isar_feature(aa64_sve, cpu)) { 248 env->cp15.cpacr_el1 = FIELD_DP64(env->cp15.cpacr_el1, 249 CPACR_EL1, ZEN, 3); 250 env->vfp.zcr_el[1] = cpu->sve_default_vq - 1; 251 } 252 /* and for SME instructions, with default vector length, and TPIDR2 */ 253 if (cpu_isar_feature(aa64_sme, cpu)) { 254 env->cp15.sctlr_el[1] |= SCTLR_EnTP2; 255 env->cp15.cpacr_el1 = FIELD_DP64(env->cp15.cpacr_el1, 256 CPACR_EL1, SMEN, 3); 257 env->vfp.smcr_el[1] = cpu->sme_default_vq - 1; 258 if (cpu_isar_feature(aa64_sme_fa64, cpu)) { 259 env->vfp.smcr_el[1] = FIELD_DP64(env->vfp.smcr_el[1], 260 SMCR, FA64, 1); 261 } 262 } 263 /* 264 * Enable 48-bit address space (TODO: take reserved_va into account). 265 * Enable TBI0 but not TBI1. 266 * Note that this must match useronly_clean_ptr. 267 */ 268 env->cp15.tcr_el[1] = 5 | (1ULL << 37); 269 270 /* Enable MTE */ 271 if (cpu_isar_feature(aa64_mte, cpu)) { 272 /* Enable tag access, but leave TCF0 as No Effect (0). */ 273 env->cp15.sctlr_el[1] |= SCTLR_ATA0; 274 /* 275 * Exclude all tags, so that tag 0 is always used. 276 * This corresponds to Linux current->thread.gcr_incl = 0. 277 * 278 * Set RRND, so that helper_irg() will generate a seed later. 279 * Here in cpu_reset(), the crypto subsystem has not yet been 280 * initialized. 281 */ 282 env->cp15.gcr_el1 = 0x1ffff; 283 } 284 /* 285 * Disable access to SCXTNUM_EL0 from CSV2_1p2. 286 * This is not yet exposed from the Linux kernel in any way. 287 */ 288 env->cp15.sctlr_el[1] |= SCTLR_TSCXT; 289 #else 290 /* Reset into the highest available EL */ 291 if (arm_feature(env, ARM_FEATURE_EL3)) { 292 env->pstate = PSTATE_MODE_EL3h; 293 } else if (arm_feature(env, ARM_FEATURE_EL2)) { 294 env->pstate = PSTATE_MODE_EL2h; 295 } else { 296 env->pstate = PSTATE_MODE_EL1h; 297 } 298 299 /* Sample rvbar at reset. */ 300 env->cp15.rvbar = cpu->rvbar_prop; 301 env->pc = env->cp15.rvbar; 302 #endif 303 } else { 304 #if defined(CONFIG_USER_ONLY) 305 /* Userspace expects access to cp10 and cp11 for FP/Neon */ 306 env->cp15.cpacr_el1 = FIELD_DP64(env->cp15.cpacr_el1, 307 CPACR, CP10, 3); 308 env->cp15.cpacr_el1 = FIELD_DP64(env->cp15.cpacr_el1, 309 CPACR, CP11, 3); 310 #endif 311 if (arm_feature(env, ARM_FEATURE_V8)) { 312 env->cp15.rvbar = cpu->rvbar_prop; 313 env->regs[15] = cpu->rvbar_prop; 314 } 315 } 316 317 #if defined(CONFIG_USER_ONLY) 318 env->uncached_cpsr = ARM_CPU_MODE_USR; 319 /* For user mode we must enable access to coprocessors */ 320 env->vfp.xregs[ARM_VFP_FPEXC] = 1 << 30; 321 if (arm_feature(env, ARM_FEATURE_IWMMXT)) { 322 env->cp15.c15_cpar = 3; 323 } else if (arm_feature(env, ARM_FEATURE_XSCALE)) { 324 env->cp15.c15_cpar = 1; 325 } 326 #else 327 328 /* 329 * If the highest available EL is EL2, AArch32 will start in Hyp 330 * mode; otherwise it starts in SVC. Note that if we start in 331 * AArch64 then these values in the uncached_cpsr will be ignored. 332 */ 333 if (arm_feature(env, ARM_FEATURE_EL2) && 334 !arm_feature(env, ARM_FEATURE_EL3)) { 335 env->uncached_cpsr = ARM_CPU_MODE_HYP; 336 } else { 337 env->uncached_cpsr = ARM_CPU_MODE_SVC; 338 } 339 env->daif = PSTATE_D | PSTATE_A | PSTATE_I | PSTATE_F; 340 341 /* AArch32 has a hard highvec setting of 0xFFFF0000. If we are currently 342 * executing as AArch32 then check if highvecs are enabled and 343 * adjust the PC accordingly. 344 */ 345 if (A32_BANKED_CURRENT_REG_GET(env, sctlr) & SCTLR_V) { 346 env->regs[15] = 0xFFFF0000; 347 } 348 349 env->vfp.xregs[ARM_VFP_FPEXC] = 0; 350 #endif 351 352 if (arm_feature(env, ARM_FEATURE_M)) { 353 #ifndef CONFIG_USER_ONLY 354 uint32_t initial_msp; /* Loaded from 0x0 */ 355 uint32_t initial_pc; /* Loaded from 0x4 */ 356 uint8_t *rom; 357 uint32_t vecbase; 358 #endif 359 360 if (cpu_isar_feature(aa32_lob, cpu)) { 361 /* 362 * LTPSIZE is constant 4 if MVE not implemented, and resets 363 * to an UNKNOWN value if MVE is implemented. We choose to 364 * always reset to 4. 365 */ 366 env->v7m.ltpsize = 4; 367 /* The LTPSIZE field in FPDSCR is constant and reads as 4. */ 368 env->v7m.fpdscr[M_REG_NS] = 4 << FPCR_LTPSIZE_SHIFT; 369 env->v7m.fpdscr[M_REG_S] = 4 << FPCR_LTPSIZE_SHIFT; 370 } 371 372 if (arm_feature(env, ARM_FEATURE_M_SECURITY)) { 373 env->v7m.secure = true; 374 } else { 375 /* This bit resets to 0 if security is supported, but 1 if 376 * it is not. The bit is not present in v7M, but we set it 377 * here so we can avoid having to make checks on it conditional 378 * on ARM_FEATURE_V8 (we don't let the guest see the bit). 379 */ 380 env->v7m.aircr = R_V7M_AIRCR_BFHFNMINS_MASK; 381 /* 382 * Set NSACR to indicate "NS access permitted to everything"; 383 * this avoids having to have all the tests of it being 384 * conditional on ARM_FEATURE_M_SECURITY. Note also that from 385 * v8.1M the guest-visible value of NSACR in a CPU without the 386 * Security Extension is 0xcff. 387 */ 388 env->v7m.nsacr = 0xcff; 389 } 390 391 /* In v7M the reset value of this bit is IMPDEF, but ARM recommends 392 * that it resets to 1, so QEMU always does that rather than making 393 * it dependent on CPU model. In v8M it is RES1. 394 */ 395 env->v7m.ccr[M_REG_NS] = R_V7M_CCR_STKALIGN_MASK; 396 env->v7m.ccr[M_REG_S] = R_V7M_CCR_STKALIGN_MASK; 397 if (arm_feature(env, ARM_FEATURE_V8)) { 398 /* in v8M the NONBASETHRDENA bit [0] is RES1 */ 399 env->v7m.ccr[M_REG_NS] |= R_V7M_CCR_NONBASETHRDENA_MASK; 400 env->v7m.ccr[M_REG_S] |= R_V7M_CCR_NONBASETHRDENA_MASK; 401 } 402 if (!arm_feature(env, ARM_FEATURE_M_MAIN)) { 403 env->v7m.ccr[M_REG_NS] |= R_V7M_CCR_UNALIGN_TRP_MASK; 404 env->v7m.ccr[M_REG_S] |= R_V7M_CCR_UNALIGN_TRP_MASK; 405 } 406 407 if (cpu_isar_feature(aa32_vfp_simd, cpu)) { 408 env->v7m.fpccr[M_REG_NS] = R_V7M_FPCCR_ASPEN_MASK; 409 env->v7m.fpccr[M_REG_S] = R_V7M_FPCCR_ASPEN_MASK | 410 R_V7M_FPCCR_LSPEN_MASK | R_V7M_FPCCR_S_MASK; 411 } 412 413 #ifndef CONFIG_USER_ONLY 414 /* Unlike A/R profile, M profile defines the reset LR value */ 415 env->regs[14] = 0xffffffff; 416 417 env->v7m.vecbase[M_REG_S] = cpu->init_svtor & 0xffffff80; 418 env->v7m.vecbase[M_REG_NS] = cpu->init_nsvtor & 0xffffff80; 419 420 /* Load the initial SP and PC from offset 0 and 4 in the vector table */ 421 vecbase = env->v7m.vecbase[env->v7m.secure]; 422 rom = rom_ptr_for_as(s->as, vecbase, 8); 423 if (rom) { 424 /* Address zero is covered by ROM which hasn't yet been 425 * copied into physical memory. 426 */ 427 initial_msp = ldl_p(rom); 428 initial_pc = ldl_p(rom + 4); 429 } else { 430 /* Address zero not covered by a ROM blob, or the ROM blob 431 * is in non-modifiable memory and this is a second reset after 432 * it got copied into memory. In the latter case, rom_ptr 433 * will return a NULL pointer and we should use ldl_phys instead. 434 */ 435 initial_msp = ldl_phys(s->as, vecbase); 436 initial_pc = ldl_phys(s->as, vecbase + 4); 437 } 438 439 qemu_log_mask(CPU_LOG_INT, 440 "Loaded reset SP 0x%x PC 0x%x from vector table\n", 441 initial_msp, initial_pc); 442 443 env->regs[13] = initial_msp & 0xFFFFFFFC; 444 env->regs[15] = initial_pc & ~1; 445 env->thumb = initial_pc & 1; 446 #else 447 /* 448 * For user mode we run non-secure and with access to the FPU. 449 * The FPU context is active (ie does not need further setup) 450 * and is owned by non-secure. 451 */ 452 env->v7m.secure = false; 453 env->v7m.nsacr = 0xcff; 454 env->v7m.cpacr[M_REG_NS] = 0xf0ffff; 455 env->v7m.fpccr[M_REG_S] &= 456 ~(R_V7M_FPCCR_LSPEN_MASK | R_V7M_FPCCR_S_MASK); 457 env->v7m.control[M_REG_S] |= R_V7M_CONTROL_FPCA_MASK; 458 #endif 459 } 460 461 /* M profile requires that reset clears the exclusive monitor; 462 * A profile does not, but clearing it makes more sense than having it 463 * set with an exclusive access on address zero. 464 */ 465 arm_clear_exclusive(env); 466 467 if (arm_feature(env, ARM_FEATURE_PMSA)) { 468 if (cpu->pmsav7_dregion > 0) { 469 if (arm_feature(env, ARM_FEATURE_V8)) { 470 memset(env->pmsav8.rbar[M_REG_NS], 0, 471 sizeof(*env->pmsav8.rbar[M_REG_NS]) 472 * cpu->pmsav7_dregion); 473 memset(env->pmsav8.rlar[M_REG_NS], 0, 474 sizeof(*env->pmsav8.rlar[M_REG_NS]) 475 * cpu->pmsav7_dregion); 476 if (arm_feature(env, ARM_FEATURE_M_SECURITY)) { 477 memset(env->pmsav8.rbar[M_REG_S], 0, 478 sizeof(*env->pmsav8.rbar[M_REG_S]) 479 * cpu->pmsav7_dregion); 480 memset(env->pmsav8.rlar[M_REG_S], 0, 481 sizeof(*env->pmsav8.rlar[M_REG_S]) 482 * cpu->pmsav7_dregion); 483 } 484 } else if (arm_feature(env, ARM_FEATURE_V7)) { 485 memset(env->pmsav7.drbar, 0, 486 sizeof(*env->pmsav7.drbar) * cpu->pmsav7_dregion); 487 memset(env->pmsav7.drsr, 0, 488 sizeof(*env->pmsav7.drsr) * cpu->pmsav7_dregion); 489 memset(env->pmsav7.dracr, 0, 490 sizeof(*env->pmsav7.dracr) * cpu->pmsav7_dregion); 491 } 492 } 493 494 if (cpu->pmsav8r_hdregion > 0) { 495 memset(env->pmsav8.hprbar, 0, 496 sizeof(*env->pmsav8.hprbar) * cpu->pmsav8r_hdregion); 497 memset(env->pmsav8.hprlar, 0, 498 sizeof(*env->pmsav8.hprlar) * cpu->pmsav8r_hdregion); 499 } 500 501 env->pmsav7.rnr[M_REG_NS] = 0; 502 env->pmsav7.rnr[M_REG_S] = 0; 503 env->pmsav8.mair0[M_REG_NS] = 0; 504 env->pmsav8.mair0[M_REG_S] = 0; 505 env->pmsav8.mair1[M_REG_NS] = 0; 506 env->pmsav8.mair1[M_REG_S] = 0; 507 } 508 509 if (arm_feature(env, ARM_FEATURE_M_SECURITY)) { 510 if (cpu->sau_sregion > 0) { 511 memset(env->sau.rbar, 0, sizeof(*env->sau.rbar) * cpu->sau_sregion); 512 memset(env->sau.rlar, 0, sizeof(*env->sau.rlar) * cpu->sau_sregion); 513 } 514 env->sau.rnr = 0; 515 /* SAU_CTRL reset value is IMPDEF; we choose 0, which is what 516 * the Cortex-M33 does. 517 */ 518 env->sau.ctrl = 0; 519 } 520 521 set_flush_to_zero(1, &env->vfp.standard_fp_status); 522 set_flush_inputs_to_zero(1, &env->vfp.standard_fp_status); 523 set_default_nan_mode(1, &env->vfp.standard_fp_status); 524 set_default_nan_mode(1, &env->vfp.standard_fp_status_f16); 525 set_float_detect_tininess(float_tininess_before_rounding, 526 &env->vfp.fp_status); 527 set_float_detect_tininess(float_tininess_before_rounding, 528 &env->vfp.standard_fp_status); 529 set_float_detect_tininess(float_tininess_before_rounding, 530 &env->vfp.fp_status_f16); 531 set_float_detect_tininess(float_tininess_before_rounding, 532 &env->vfp.standard_fp_status_f16); 533 #ifndef CONFIG_USER_ONLY 534 if (kvm_enabled()) { 535 kvm_arm_reset_vcpu(cpu); 536 } 537 #endif 538 539 hw_breakpoint_update_all(cpu); 540 hw_watchpoint_update_all(cpu); 541 arm_rebuild_hflags(env); 542 } 543 544 #if defined(CONFIG_TCG) && !defined(CONFIG_USER_ONLY) 545 546 static inline bool arm_excp_unmasked(CPUState *cs, unsigned int excp_idx, 547 unsigned int target_el, 548 unsigned int cur_el, bool secure, 549 uint64_t hcr_el2) 550 { 551 CPUARMState *env = cs->env_ptr; 552 bool pstate_unmasked; 553 bool unmasked = false; 554 555 /* 556 * Don't take exceptions if they target a lower EL. 557 * This check should catch any exceptions that would not be taken 558 * but left pending. 559 */ 560 if (cur_el > target_el) { 561 return false; 562 } 563 564 switch (excp_idx) { 565 case EXCP_FIQ: 566 pstate_unmasked = !(env->daif & PSTATE_F); 567 break; 568 569 case EXCP_IRQ: 570 pstate_unmasked = !(env->daif & PSTATE_I); 571 break; 572 573 case EXCP_VFIQ: 574 if (!(hcr_el2 & HCR_FMO) || (hcr_el2 & HCR_TGE)) { 575 /* VFIQs are only taken when hypervized. */ 576 return false; 577 } 578 return !(env->daif & PSTATE_F); 579 case EXCP_VIRQ: 580 if (!(hcr_el2 & HCR_IMO) || (hcr_el2 & HCR_TGE)) { 581 /* VIRQs are only taken when hypervized. */ 582 return false; 583 } 584 return !(env->daif & PSTATE_I); 585 case EXCP_VSERR: 586 if (!(hcr_el2 & HCR_AMO) || (hcr_el2 & HCR_TGE)) { 587 /* VIRQs are only taken when hypervized. */ 588 return false; 589 } 590 return !(env->daif & PSTATE_A); 591 default: 592 g_assert_not_reached(); 593 } 594 595 /* 596 * Use the target EL, current execution state and SCR/HCR settings to 597 * determine whether the corresponding CPSR bit is used to mask the 598 * interrupt. 599 */ 600 if ((target_el > cur_el) && (target_el != 1)) { 601 /* Exceptions targeting a higher EL may not be maskable */ 602 if (arm_feature(env, ARM_FEATURE_AARCH64)) { 603 switch (target_el) { 604 case 2: 605 /* 606 * According to ARM DDI 0487H.a, an interrupt can be masked 607 * when HCR_E2H and HCR_TGE are both set regardless of the 608 * current Security state. Note that we need to revisit this 609 * part again once we need to support NMI. 610 */ 611 if ((hcr_el2 & (HCR_E2H | HCR_TGE)) != (HCR_E2H | HCR_TGE)) { 612 unmasked = true; 613 } 614 break; 615 case 3: 616 /* Interrupt cannot be masked when the target EL is 3 */ 617 unmasked = true; 618 break; 619 default: 620 g_assert_not_reached(); 621 } 622 } else { 623 /* 624 * The old 32-bit-only environment has a more complicated 625 * masking setup. HCR and SCR bits not only affect interrupt 626 * routing but also change the behaviour of masking. 627 */ 628 bool hcr, scr; 629 630 switch (excp_idx) { 631 case EXCP_FIQ: 632 /* 633 * If FIQs are routed to EL3 or EL2 then there are cases where 634 * we override the CPSR.F in determining if the exception is 635 * masked or not. If neither of these are set then we fall back 636 * to the CPSR.F setting otherwise we further assess the state 637 * below. 638 */ 639 hcr = hcr_el2 & HCR_FMO; 640 scr = (env->cp15.scr_el3 & SCR_FIQ); 641 642 /* 643 * When EL3 is 32-bit, the SCR.FW bit controls whether the 644 * CPSR.F bit masks FIQ interrupts when taken in non-secure 645 * state. If SCR.FW is set then FIQs can be masked by CPSR.F 646 * when non-secure but only when FIQs are only routed to EL3. 647 */ 648 scr = scr && !((env->cp15.scr_el3 & SCR_FW) && !hcr); 649 break; 650 case EXCP_IRQ: 651 /* 652 * When EL3 execution state is 32-bit, if HCR.IMO is set then 653 * we may override the CPSR.I masking when in non-secure state. 654 * The SCR.IRQ setting has already been taken into consideration 655 * when setting the target EL, so it does not have a further 656 * affect here. 657 */ 658 hcr = hcr_el2 & HCR_IMO; 659 scr = false; 660 break; 661 default: 662 g_assert_not_reached(); 663 } 664 665 if ((scr || hcr) && !secure) { 666 unmasked = true; 667 } 668 } 669 } 670 671 /* 672 * The PSTATE bits only mask the interrupt if we have not overriden the 673 * ability above. 674 */ 675 return unmasked || pstate_unmasked; 676 } 677 678 static bool arm_cpu_exec_interrupt(CPUState *cs, int interrupt_request) 679 { 680 CPUClass *cc = CPU_GET_CLASS(cs); 681 CPUARMState *env = cs->env_ptr; 682 uint32_t cur_el = arm_current_el(env); 683 bool secure = arm_is_secure(env); 684 uint64_t hcr_el2 = arm_hcr_el2_eff(env); 685 uint32_t target_el; 686 uint32_t excp_idx; 687 688 /* The prioritization of interrupts is IMPLEMENTATION DEFINED. */ 689 690 if (interrupt_request & CPU_INTERRUPT_FIQ) { 691 excp_idx = EXCP_FIQ; 692 target_el = arm_phys_excp_target_el(cs, excp_idx, cur_el, secure); 693 if (arm_excp_unmasked(cs, excp_idx, target_el, 694 cur_el, secure, hcr_el2)) { 695 goto found; 696 } 697 } 698 if (interrupt_request & CPU_INTERRUPT_HARD) { 699 excp_idx = EXCP_IRQ; 700 target_el = arm_phys_excp_target_el(cs, excp_idx, cur_el, secure); 701 if (arm_excp_unmasked(cs, excp_idx, target_el, 702 cur_el, secure, hcr_el2)) { 703 goto found; 704 } 705 } 706 if (interrupt_request & CPU_INTERRUPT_VIRQ) { 707 excp_idx = EXCP_VIRQ; 708 target_el = 1; 709 if (arm_excp_unmasked(cs, excp_idx, target_el, 710 cur_el, secure, hcr_el2)) { 711 goto found; 712 } 713 } 714 if (interrupt_request & CPU_INTERRUPT_VFIQ) { 715 excp_idx = EXCP_VFIQ; 716 target_el = 1; 717 if (arm_excp_unmasked(cs, excp_idx, target_el, 718 cur_el, secure, hcr_el2)) { 719 goto found; 720 } 721 } 722 if (interrupt_request & CPU_INTERRUPT_VSERR) { 723 excp_idx = EXCP_VSERR; 724 target_el = 1; 725 if (arm_excp_unmasked(cs, excp_idx, target_el, 726 cur_el, secure, hcr_el2)) { 727 /* Taking a virtual abort clears HCR_EL2.VSE */ 728 env->cp15.hcr_el2 &= ~HCR_VSE; 729 cpu_reset_interrupt(cs, CPU_INTERRUPT_VSERR); 730 goto found; 731 } 732 } 733 return false; 734 735 found: 736 cs->exception_index = excp_idx; 737 env->exception.target_el = target_el; 738 cc->tcg_ops->do_interrupt(cs); 739 return true; 740 } 741 742 #endif /* CONFIG_TCG && !CONFIG_USER_ONLY */ 743 744 void arm_cpu_update_virq(ARMCPU *cpu) 745 { 746 /* 747 * Update the interrupt level for VIRQ, which is the logical OR of 748 * the HCR_EL2.VI bit and the input line level from the GIC. 749 */ 750 CPUARMState *env = &cpu->env; 751 CPUState *cs = CPU(cpu); 752 753 bool new_state = (env->cp15.hcr_el2 & HCR_VI) || 754 (env->irq_line_state & CPU_INTERRUPT_VIRQ); 755 756 if (new_state != ((cs->interrupt_request & CPU_INTERRUPT_VIRQ) != 0)) { 757 if (new_state) { 758 cpu_interrupt(cs, CPU_INTERRUPT_VIRQ); 759 } else { 760 cpu_reset_interrupt(cs, CPU_INTERRUPT_VIRQ); 761 } 762 } 763 } 764 765 void arm_cpu_update_vfiq(ARMCPU *cpu) 766 { 767 /* 768 * Update the interrupt level for VFIQ, which is the logical OR of 769 * the HCR_EL2.VF bit and the input line level from the GIC. 770 */ 771 CPUARMState *env = &cpu->env; 772 CPUState *cs = CPU(cpu); 773 774 bool new_state = (env->cp15.hcr_el2 & HCR_VF) || 775 (env->irq_line_state & CPU_INTERRUPT_VFIQ); 776 777 if (new_state != ((cs->interrupt_request & CPU_INTERRUPT_VFIQ) != 0)) { 778 if (new_state) { 779 cpu_interrupt(cs, CPU_INTERRUPT_VFIQ); 780 } else { 781 cpu_reset_interrupt(cs, CPU_INTERRUPT_VFIQ); 782 } 783 } 784 } 785 786 void arm_cpu_update_vserr(ARMCPU *cpu) 787 { 788 /* 789 * Update the interrupt level for VSERR, which is the HCR_EL2.VSE bit. 790 */ 791 CPUARMState *env = &cpu->env; 792 CPUState *cs = CPU(cpu); 793 794 bool new_state = env->cp15.hcr_el2 & HCR_VSE; 795 796 if (new_state != ((cs->interrupt_request & CPU_INTERRUPT_VSERR) != 0)) { 797 if (new_state) { 798 cpu_interrupt(cs, CPU_INTERRUPT_VSERR); 799 } else { 800 cpu_reset_interrupt(cs, CPU_INTERRUPT_VSERR); 801 } 802 } 803 } 804 805 #ifndef CONFIG_USER_ONLY 806 static void arm_cpu_set_irq(void *opaque, int irq, int level) 807 { 808 ARMCPU *cpu = opaque; 809 CPUARMState *env = &cpu->env; 810 CPUState *cs = CPU(cpu); 811 static const int mask[] = { 812 [ARM_CPU_IRQ] = CPU_INTERRUPT_HARD, 813 [ARM_CPU_FIQ] = CPU_INTERRUPT_FIQ, 814 [ARM_CPU_VIRQ] = CPU_INTERRUPT_VIRQ, 815 [ARM_CPU_VFIQ] = CPU_INTERRUPT_VFIQ 816 }; 817 818 if (!arm_feature(env, ARM_FEATURE_EL2) && 819 (irq == ARM_CPU_VIRQ || irq == ARM_CPU_VFIQ)) { 820 /* 821 * The GIC might tell us about VIRQ and VFIQ state, but if we don't 822 * have EL2 support we don't care. (Unless the guest is doing something 823 * silly this will only be calls saying "level is still 0".) 824 */ 825 return; 826 } 827 828 if (level) { 829 env->irq_line_state |= mask[irq]; 830 } else { 831 env->irq_line_state &= ~mask[irq]; 832 } 833 834 switch (irq) { 835 case ARM_CPU_VIRQ: 836 arm_cpu_update_virq(cpu); 837 break; 838 case ARM_CPU_VFIQ: 839 arm_cpu_update_vfiq(cpu); 840 break; 841 case ARM_CPU_IRQ: 842 case ARM_CPU_FIQ: 843 if (level) { 844 cpu_interrupt(cs, mask[irq]); 845 } else { 846 cpu_reset_interrupt(cs, mask[irq]); 847 } 848 break; 849 default: 850 g_assert_not_reached(); 851 } 852 } 853 854 static void arm_cpu_kvm_set_irq(void *opaque, int irq, int level) 855 { 856 #ifdef CONFIG_KVM 857 ARMCPU *cpu = opaque; 858 CPUARMState *env = &cpu->env; 859 CPUState *cs = CPU(cpu); 860 uint32_t linestate_bit; 861 int irq_id; 862 863 switch (irq) { 864 case ARM_CPU_IRQ: 865 irq_id = KVM_ARM_IRQ_CPU_IRQ; 866 linestate_bit = CPU_INTERRUPT_HARD; 867 break; 868 case ARM_CPU_FIQ: 869 irq_id = KVM_ARM_IRQ_CPU_FIQ; 870 linestate_bit = CPU_INTERRUPT_FIQ; 871 break; 872 default: 873 g_assert_not_reached(); 874 } 875 876 if (level) { 877 env->irq_line_state |= linestate_bit; 878 } else { 879 env->irq_line_state &= ~linestate_bit; 880 } 881 kvm_arm_set_irq(cs->cpu_index, KVM_ARM_IRQ_TYPE_CPU, irq_id, !!level); 882 #endif 883 } 884 885 static bool arm_cpu_virtio_is_big_endian(CPUState *cs) 886 { 887 ARMCPU *cpu = ARM_CPU(cs); 888 CPUARMState *env = &cpu->env; 889 890 cpu_synchronize_state(cs); 891 return arm_cpu_data_is_big_endian(env); 892 } 893 894 #endif 895 896 static void arm_disas_set_info(CPUState *cpu, disassemble_info *info) 897 { 898 ARMCPU *ac = ARM_CPU(cpu); 899 CPUARMState *env = &ac->env; 900 bool sctlr_b; 901 902 if (is_a64(env)) { 903 info->cap_arch = CS_ARCH_ARM64; 904 info->cap_insn_unit = 4; 905 info->cap_insn_split = 4; 906 } else { 907 int cap_mode; 908 if (env->thumb) { 909 info->cap_insn_unit = 2; 910 info->cap_insn_split = 4; 911 cap_mode = CS_MODE_THUMB; 912 } else { 913 info->cap_insn_unit = 4; 914 info->cap_insn_split = 4; 915 cap_mode = CS_MODE_ARM; 916 } 917 if (arm_feature(env, ARM_FEATURE_V8)) { 918 cap_mode |= CS_MODE_V8; 919 } 920 if (arm_feature(env, ARM_FEATURE_M)) { 921 cap_mode |= CS_MODE_MCLASS; 922 } 923 info->cap_arch = CS_ARCH_ARM; 924 info->cap_mode = cap_mode; 925 } 926 927 sctlr_b = arm_sctlr_b(env); 928 if (bswap_code(sctlr_b)) { 929 #if TARGET_BIG_ENDIAN 930 info->endian = BFD_ENDIAN_LITTLE; 931 #else 932 info->endian = BFD_ENDIAN_BIG; 933 #endif 934 } 935 info->flags &= ~INSN_ARM_BE32; 936 #ifndef CONFIG_USER_ONLY 937 if (sctlr_b) { 938 info->flags |= INSN_ARM_BE32; 939 } 940 #endif 941 } 942 943 #ifdef TARGET_AARCH64 944 945 static void aarch64_cpu_dump_state(CPUState *cs, FILE *f, int flags) 946 { 947 ARMCPU *cpu = ARM_CPU(cs); 948 CPUARMState *env = &cpu->env; 949 uint32_t psr = pstate_read(env); 950 int i; 951 int el = arm_current_el(env); 952 const char *ns_status; 953 bool sve; 954 955 qemu_fprintf(f, " PC=%016" PRIx64 " ", env->pc); 956 for (i = 0; i < 32; i++) { 957 if (i == 31) { 958 qemu_fprintf(f, " SP=%016" PRIx64 "\n", env->xregs[i]); 959 } else { 960 qemu_fprintf(f, "X%02d=%016" PRIx64 "%s", i, env->xregs[i], 961 (i + 2) % 3 ? " " : "\n"); 962 } 963 } 964 965 if (arm_feature(env, ARM_FEATURE_EL3) && el != 3) { 966 ns_status = env->cp15.scr_el3 & SCR_NS ? "NS " : "S "; 967 } else { 968 ns_status = ""; 969 } 970 qemu_fprintf(f, "PSTATE=%08x %c%c%c%c %sEL%d%c", 971 psr, 972 psr & PSTATE_N ? 'N' : '-', 973 psr & PSTATE_Z ? 'Z' : '-', 974 psr & PSTATE_C ? 'C' : '-', 975 psr & PSTATE_V ? 'V' : '-', 976 ns_status, 977 el, 978 psr & PSTATE_SP ? 'h' : 't'); 979 980 if (cpu_isar_feature(aa64_sme, cpu)) { 981 qemu_fprintf(f, " SVCR=%08" PRIx64 " %c%c", 982 env->svcr, 983 (FIELD_EX64(env->svcr, SVCR, ZA) ? 'Z' : '-'), 984 (FIELD_EX64(env->svcr, SVCR, SM) ? 'S' : '-')); 985 } 986 if (cpu_isar_feature(aa64_bti, cpu)) { 987 qemu_fprintf(f, " BTYPE=%d", (psr & PSTATE_BTYPE) >> 10); 988 } 989 if (!(flags & CPU_DUMP_FPU)) { 990 qemu_fprintf(f, "\n"); 991 return; 992 } 993 if (fp_exception_el(env, el) != 0) { 994 qemu_fprintf(f, " FPU disabled\n"); 995 return; 996 } 997 qemu_fprintf(f, " FPCR=%08x FPSR=%08x\n", 998 vfp_get_fpcr(env), vfp_get_fpsr(env)); 999 1000 if (cpu_isar_feature(aa64_sme, cpu) && FIELD_EX64(env->svcr, SVCR, SM)) { 1001 sve = sme_exception_el(env, el) == 0; 1002 } else if (cpu_isar_feature(aa64_sve, cpu)) { 1003 sve = sve_exception_el(env, el) == 0; 1004 } else { 1005 sve = false; 1006 } 1007 1008 if (sve) { 1009 int j, zcr_len = sve_vqm1_for_el(env, el); 1010 1011 for (i = 0; i <= FFR_PRED_NUM; i++) { 1012 bool eol; 1013 if (i == FFR_PRED_NUM) { 1014 qemu_fprintf(f, "FFR="); 1015 /* It's last, so end the line. */ 1016 eol = true; 1017 } else { 1018 qemu_fprintf(f, "P%02d=", i); 1019 switch (zcr_len) { 1020 case 0: 1021 eol = i % 8 == 7; 1022 break; 1023 case 1: 1024 eol = i % 6 == 5; 1025 break; 1026 case 2: 1027 case 3: 1028 eol = i % 3 == 2; 1029 break; 1030 default: 1031 /* More than one quadword per predicate. */ 1032 eol = true; 1033 break; 1034 } 1035 } 1036 for (j = zcr_len / 4; j >= 0; j--) { 1037 int digits; 1038 if (j * 4 + 4 <= zcr_len + 1) { 1039 digits = 16; 1040 } else { 1041 digits = (zcr_len % 4 + 1) * 4; 1042 } 1043 qemu_fprintf(f, "%0*" PRIx64 "%s", digits, 1044 env->vfp.pregs[i].p[j], 1045 j ? ":" : eol ? "\n" : " "); 1046 } 1047 } 1048 1049 for (i = 0; i < 32; i++) { 1050 if (zcr_len == 0) { 1051 qemu_fprintf(f, "Z%02d=%016" PRIx64 ":%016" PRIx64 "%s", 1052 i, env->vfp.zregs[i].d[1], 1053 env->vfp.zregs[i].d[0], i & 1 ? "\n" : " "); 1054 } else if (zcr_len == 1) { 1055 qemu_fprintf(f, "Z%02d=%016" PRIx64 ":%016" PRIx64 1056 ":%016" PRIx64 ":%016" PRIx64 "\n", 1057 i, env->vfp.zregs[i].d[3], env->vfp.zregs[i].d[2], 1058 env->vfp.zregs[i].d[1], env->vfp.zregs[i].d[0]); 1059 } else { 1060 for (j = zcr_len; j >= 0; j--) { 1061 bool odd = (zcr_len - j) % 2 != 0; 1062 if (j == zcr_len) { 1063 qemu_fprintf(f, "Z%02d[%x-%x]=", i, j, j - 1); 1064 } else if (!odd) { 1065 if (j > 0) { 1066 qemu_fprintf(f, " [%x-%x]=", j, j - 1); 1067 } else { 1068 qemu_fprintf(f, " [%x]=", j); 1069 } 1070 } 1071 qemu_fprintf(f, "%016" PRIx64 ":%016" PRIx64 "%s", 1072 env->vfp.zregs[i].d[j * 2 + 1], 1073 env->vfp.zregs[i].d[j * 2], 1074 odd || j == 0 ? "\n" : ":"); 1075 } 1076 } 1077 } 1078 } else { 1079 for (i = 0; i < 32; i++) { 1080 uint64_t *q = aa64_vfp_qreg(env, i); 1081 qemu_fprintf(f, "Q%02d=%016" PRIx64 ":%016" PRIx64 "%s", 1082 i, q[1], q[0], (i & 1 ? "\n" : " ")); 1083 } 1084 } 1085 } 1086 1087 #else 1088 1089 static inline void aarch64_cpu_dump_state(CPUState *cs, FILE *f, int flags) 1090 { 1091 g_assert_not_reached(); 1092 } 1093 1094 #endif 1095 1096 static void arm_cpu_dump_state(CPUState *cs, FILE *f, int flags) 1097 { 1098 ARMCPU *cpu = ARM_CPU(cs); 1099 CPUARMState *env = &cpu->env; 1100 int i; 1101 1102 if (is_a64(env)) { 1103 aarch64_cpu_dump_state(cs, f, flags); 1104 return; 1105 } 1106 1107 for (i = 0; i < 16; i++) { 1108 qemu_fprintf(f, "R%02d=%08x", i, env->regs[i]); 1109 if ((i % 4) == 3) { 1110 qemu_fprintf(f, "\n"); 1111 } else { 1112 qemu_fprintf(f, " "); 1113 } 1114 } 1115 1116 if (arm_feature(env, ARM_FEATURE_M)) { 1117 uint32_t xpsr = xpsr_read(env); 1118 const char *mode; 1119 const char *ns_status = ""; 1120 1121 if (arm_feature(env, ARM_FEATURE_M_SECURITY)) { 1122 ns_status = env->v7m.secure ? "S " : "NS "; 1123 } 1124 1125 if (xpsr & XPSR_EXCP) { 1126 mode = "handler"; 1127 } else { 1128 if (env->v7m.control[env->v7m.secure] & R_V7M_CONTROL_NPRIV_MASK) { 1129 mode = "unpriv-thread"; 1130 } else { 1131 mode = "priv-thread"; 1132 } 1133 } 1134 1135 qemu_fprintf(f, "XPSR=%08x %c%c%c%c %c %s%s\n", 1136 xpsr, 1137 xpsr & XPSR_N ? 'N' : '-', 1138 xpsr & XPSR_Z ? 'Z' : '-', 1139 xpsr & XPSR_C ? 'C' : '-', 1140 xpsr & XPSR_V ? 'V' : '-', 1141 xpsr & XPSR_T ? 'T' : 'A', 1142 ns_status, 1143 mode); 1144 } else { 1145 uint32_t psr = cpsr_read(env); 1146 const char *ns_status = ""; 1147 1148 if (arm_feature(env, ARM_FEATURE_EL3) && 1149 (psr & CPSR_M) != ARM_CPU_MODE_MON) { 1150 ns_status = env->cp15.scr_el3 & SCR_NS ? "NS " : "S "; 1151 } 1152 1153 qemu_fprintf(f, "PSR=%08x %c%c%c%c %c %s%s%d\n", 1154 psr, 1155 psr & CPSR_N ? 'N' : '-', 1156 psr & CPSR_Z ? 'Z' : '-', 1157 psr & CPSR_C ? 'C' : '-', 1158 psr & CPSR_V ? 'V' : '-', 1159 psr & CPSR_T ? 'T' : 'A', 1160 ns_status, 1161 aarch32_mode_name(psr), (psr & 0x10) ? 32 : 26); 1162 } 1163 1164 if (flags & CPU_DUMP_FPU) { 1165 int numvfpregs = 0; 1166 if (cpu_isar_feature(aa32_simd_r32, cpu)) { 1167 numvfpregs = 32; 1168 } else if (cpu_isar_feature(aa32_vfp_simd, cpu)) { 1169 numvfpregs = 16; 1170 } 1171 for (i = 0; i < numvfpregs; i++) { 1172 uint64_t v = *aa32_vfp_dreg(env, i); 1173 qemu_fprintf(f, "s%02d=%08x s%02d=%08x d%02d=%016" PRIx64 "\n", 1174 i * 2, (uint32_t)v, 1175 i * 2 + 1, (uint32_t)(v >> 32), 1176 i, v); 1177 } 1178 qemu_fprintf(f, "FPSCR: %08x\n", vfp_get_fpscr(env)); 1179 if (cpu_isar_feature(aa32_mve, cpu)) { 1180 qemu_fprintf(f, "VPR: %08x\n", env->v7m.vpr); 1181 } 1182 } 1183 } 1184 1185 uint64_t arm_cpu_mp_affinity(int idx, uint8_t clustersz) 1186 { 1187 uint32_t Aff1 = idx / clustersz; 1188 uint32_t Aff0 = idx % clustersz; 1189 return (Aff1 << ARM_AFF1_SHIFT) | Aff0; 1190 } 1191 1192 static void arm_cpu_initfn(Object *obj) 1193 { 1194 ARMCPU *cpu = ARM_CPU(obj); 1195 1196 cpu_set_cpustate_pointers(cpu); 1197 cpu->cp_regs = g_hash_table_new_full(g_direct_hash, g_direct_equal, 1198 NULL, g_free); 1199 1200 QLIST_INIT(&cpu->pre_el_change_hooks); 1201 QLIST_INIT(&cpu->el_change_hooks); 1202 1203 #ifdef CONFIG_USER_ONLY 1204 # ifdef TARGET_AARCH64 1205 /* 1206 * The linux kernel defaults to 512-bit for SVE, and 256-bit for SME. 1207 * These values were chosen to fit within the default signal frame. 1208 * See documentation for /proc/sys/abi/{sve,sme}_default_vector_length, 1209 * and our corresponding cpu property. 1210 */ 1211 cpu->sve_default_vq = 4; 1212 cpu->sme_default_vq = 2; 1213 # endif 1214 #else 1215 /* Our inbound IRQ and FIQ lines */ 1216 if (kvm_enabled()) { 1217 /* VIRQ and VFIQ are unused with KVM but we add them to maintain 1218 * the same interface as non-KVM CPUs. 1219 */ 1220 qdev_init_gpio_in(DEVICE(cpu), arm_cpu_kvm_set_irq, 4); 1221 } else { 1222 qdev_init_gpio_in(DEVICE(cpu), arm_cpu_set_irq, 4); 1223 } 1224 1225 qdev_init_gpio_out(DEVICE(cpu), cpu->gt_timer_outputs, 1226 ARRAY_SIZE(cpu->gt_timer_outputs)); 1227 1228 qdev_init_gpio_out_named(DEVICE(cpu), &cpu->gicv3_maintenance_interrupt, 1229 "gicv3-maintenance-interrupt", 1); 1230 qdev_init_gpio_out_named(DEVICE(cpu), &cpu->pmu_interrupt, 1231 "pmu-interrupt", 1); 1232 #endif 1233 1234 /* DTB consumers generally don't in fact care what the 'compatible' 1235 * string is, so always provide some string and trust that a hypothetical 1236 * picky DTB consumer will also provide a helpful error message. 1237 */ 1238 cpu->dtb_compatible = "qemu,unknown"; 1239 cpu->psci_version = QEMU_PSCI_VERSION_0_1; /* By default assume PSCI v0.1 */ 1240 cpu->kvm_target = QEMU_KVM_ARM_TARGET_NONE; 1241 1242 if (tcg_enabled() || hvf_enabled()) { 1243 /* TCG and HVF implement PSCI 1.1 */ 1244 cpu->psci_version = QEMU_PSCI_VERSION_1_1; 1245 } 1246 } 1247 1248 static Property arm_cpu_gt_cntfrq_property = 1249 DEFINE_PROP_UINT64("cntfrq", ARMCPU, gt_cntfrq_hz, 1250 NANOSECONDS_PER_SECOND / GTIMER_SCALE); 1251 1252 static Property arm_cpu_reset_cbar_property = 1253 DEFINE_PROP_UINT64("reset-cbar", ARMCPU, reset_cbar, 0); 1254 1255 static Property arm_cpu_reset_hivecs_property = 1256 DEFINE_PROP_BOOL("reset-hivecs", ARMCPU, reset_hivecs, false); 1257 1258 #ifndef CONFIG_USER_ONLY 1259 static Property arm_cpu_has_el2_property = 1260 DEFINE_PROP_BOOL("has_el2", ARMCPU, has_el2, true); 1261 1262 static Property arm_cpu_has_el3_property = 1263 DEFINE_PROP_BOOL("has_el3", ARMCPU, has_el3, true); 1264 #endif 1265 1266 static Property arm_cpu_cfgend_property = 1267 DEFINE_PROP_BOOL("cfgend", ARMCPU, cfgend, false); 1268 1269 static Property arm_cpu_has_vfp_property = 1270 DEFINE_PROP_BOOL("vfp", ARMCPU, has_vfp, true); 1271 1272 static Property arm_cpu_has_neon_property = 1273 DEFINE_PROP_BOOL("neon", ARMCPU, has_neon, true); 1274 1275 static Property arm_cpu_has_dsp_property = 1276 DEFINE_PROP_BOOL("dsp", ARMCPU, has_dsp, true); 1277 1278 static Property arm_cpu_has_mpu_property = 1279 DEFINE_PROP_BOOL("has-mpu", ARMCPU, has_mpu, true); 1280 1281 /* This is like DEFINE_PROP_UINT32 but it doesn't set the default value, 1282 * because the CPU initfn will have already set cpu->pmsav7_dregion to 1283 * the right value for that particular CPU type, and we don't want 1284 * to override that with an incorrect constant value. 1285 */ 1286 static Property arm_cpu_pmsav7_dregion_property = 1287 DEFINE_PROP_UNSIGNED_NODEFAULT("pmsav7-dregion", ARMCPU, 1288 pmsav7_dregion, 1289 qdev_prop_uint32, uint32_t); 1290 1291 static bool arm_get_pmu(Object *obj, Error **errp) 1292 { 1293 ARMCPU *cpu = ARM_CPU(obj); 1294 1295 return cpu->has_pmu; 1296 } 1297 1298 static void arm_set_pmu(Object *obj, bool value, Error **errp) 1299 { 1300 ARMCPU *cpu = ARM_CPU(obj); 1301 1302 if (value) { 1303 if (kvm_enabled() && !kvm_arm_pmu_supported()) { 1304 error_setg(errp, "'pmu' feature not supported by KVM on this host"); 1305 return; 1306 } 1307 set_feature(&cpu->env, ARM_FEATURE_PMU); 1308 } else { 1309 unset_feature(&cpu->env, ARM_FEATURE_PMU); 1310 } 1311 cpu->has_pmu = value; 1312 } 1313 1314 unsigned int gt_cntfrq_period_ns(ARMCPU *cpu) 1315 { 1316 /* 1317 * The exact approach to calculating guest ticks is: 1318 * 1319 * muldiv64(qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL), cpu->gt_cntfrq_hz, 1320 * NANOSECONDS_PER_SECOND); 1321 * 1322 * We don't do that. Rather we intentionally use integer division 1323 * truncation below and in the caller for the conversion of host monotonic 1324 * time to guest ticks to provide the exact inverse for the semantics of 1325 * the QEMUTimer scale factor. QEMUTimer's scale facter is an integer, so 1326 * it loses precision when representing frequencies where 1327 * `(NANOSECONDS_PER_SECOND % cpu->gt_cntfrq) > 0` holds. Failing to 1328 * provide an exact inverse leads to scheduling timers with negative 1329 * periods, which in turn leads to sticky behaviour in the guest. 1330 * 1331 * Finally, CNTFRQ is effectively capped at 1GHz to ensure our scale factor 1332 * cannot become zero. 1333 */ 1334 return NANOSECONDS_PER_SECOND > cpu->gt_cntfrq_hz ? 1335 NANOSECONDS_PER_SECOND / cpu->gt_cntfrq_hz : 1; 1336 } 1337 1338 void arm_cpu_post_init(Object *obj) 1339 { 1340 ARMCPU *cpu = ARM_CPU(obj); 1341 1342 /* M profile implies PMSA. We have to do this here rather than 1343 * in realize with the other feature-implication checks because 1344 * we look at the PMSA bit to see if we should add some properties. 1345 */ 1346 if (arm_feature(&cpu->env, ARM_FEATURE_M)) { 1347 set_feature(&cpu->env, ARM_FEATURE_PMSA); 1348 } 1349 1350 if (arm_feature(&cpu->env, ARM_FEATURE_CBAR) || 1351 arm_feature(&cpu->env, ARM_FEATURE_CBAR_RO)) { 1352 qdev_property_add_static(DEVICE(obj), &arm_cpu_reset_cbar_property); 1353 } 1354 1355 if (!arm_feature(&cpu->env, ARM_FEATURE_M)) { 1356 qdev_property_add_static(DEVICE(obj), &arm_cpu_reset_hivecs_property); 1357 } 1358 1359 if (arm_feature(&cpu->env, ARM_FEATURE_V8)) { 1360 object_property_add_uint64_ptr(obj, "rvbar", 1361 &cpu->rvbar_prop, 1362 OBJ_PROP_FLAG_READWRITE); 1363 } 1364 1365 #ifndef CONFIG_USER_ONLY 1366 if (arm_feature(&cpu->env, ARM_FEATURE_EL3)) { 1367 /* Add the has_el3 state CPU property only if EL3 is allowed. This will 1368 * prevent "has_el3" from existing on CPUs which cannot support EL3. 1369 */ 1370 qdev_property_add_static(DEVICE(obj), &arm_cpu_has_el3_property); 1371 1372 object_property_add_link(obj, "secure-memory", 1373 TYPE_MEMORY_REGION, 1374 (Object **)&cpu->secure_memory, 1375 qdev_prop_allow_set_link_before_realize, 1376 OBJ_PROP_LINK_STRONG); 1377 } 1378 1379 if (arm_feature(&cpu->env, ARM_FEATURE_EL2)) { 1380 qdev_property_add_static(DEVICE(obj), &arm_cpu_has_el2_property); 1381 } 1382 #endif 1383 1384 if (arm_feature(&cpu->env, ARM_FEATURE_PMU)) { 1385 cpu->has_pmu = true; 1386 object_property_add_bool(obj, "pmu", arm_get_pmu, arm_set_pmu); 1387 } 1388 1389 /* 1390 * Allow user to turn off VFP and Neon support, but only for TCG -- 1391 * KVM does not currently allow us to lie to the guest about its 1392 * ID/feature registers, so the guest always sees what the host has. 1393 */ 1394 if (arm_feature(&cpu->env, ARM_FEATURE_AARCH64) 1395 ? cpu_isar_feature(aa64_fp_simd, cpu) 1396 : cpu_isar_feature(aa32_vfp, cpu)) { 1397 cpu->has_vfp = true; 1398 if (!kvm_enabled()) { 1399 qdev_property_add_static(DEVICE(obj), &arm_cpu_has_vfp_property); 1400 } 1401 } 1402 1403 if (arm_feature(&cpu->env, ARM_FEATURE_NEON)) { 1404 cpu->has_neon = true; 1405 if (!kvm_enabled()) { 1406 qdev_property_add_static(DEVICE(obj), &arm_cpu_has_neon_property); 1407 } 1408 } 1409 1410 if (arm_feature(&cpu->env, ARM_FEATURE_M) && 1411 arm_feature(&cpu->env, ARM_FEATURE_THUMB_DSP)) { 1412 qdev_property_add_static(DEVICE(obj), &arm_cpu_has_dsp_property); 1413 } 1414 1415 if (arm_feature(&cpu->env, ARM_FEATURE_PMSA)) { 1416 qdev_property_add_static(DEVICE(obj), &arm_cpu_has_mpu_property); 1417 if (arm_feature(&cpu->env, ARM_FEATURE_V7)) { 1418 qdev_property_add_static(DEVICE(obj), 1419 &arm_cpu_pmsav7_dregion_property); 1420 } 1421 } 1422 1423 if (arm_feature(&cpu->env, ARM_FEATURE_M_SECURITY)) { 1424 object_property_add_link(obj, "idau", TYPE_IDAU_INTERFACE, &cpu->idau, 1425 qdev_prop_allow_set_link_before_realize, 1426 OBJ_PROP_LINK_STRONG); 1427 /* 1428 * M profile: initial value of the Secure VTOR. We can't just use 1429 * a simple DEFINE_PROP_UINT32 for this because we want to permit 1430 * the property to be set after realize. 1431 */ 1432 object_property_add_uint32_ptr(obj, "init-svtor", 1433 &cpu->init_svtor, 1434 OBJ_PROP_FLAG_READWRITE); 1435 } 1436 if (arm_feature(&cpu->env, ARM_FEATURE_M)) { 1437 /* 1438 * Initial value of the NS VTOR (for cores without the Security 1439 * extension, this is the only VTOR) 1440 */ 1441 object_property_add_uint32_ptr(obj, "init-nsvtor", 1442 &cpu->init_nsvtor, 1443 OBJ_PROP_FLAG_READWRITE); 1444 } 1445 1446 /* Not DEFINE_PROP_UINT32: we want this to be settable after realize */ 1447 object_property_add_uint32_ptr(obj, "psci-conduit", 1448 &cpu->psci_conduit, 1449 OBJ_PROP_FLAG_READWRITE); 1450 1451 qdev_property_add_static(DEVICE(obj), &arm_cpu_cfgend_property); 1452 1453 if (arm_feature(&cpu->env, ARM_FEATURE_GENERIC_TIMER)) { 1454 qdev_property_add_static(DEVICE(cpu), &arm_cpu_gt_cntfrq_property); 1455 } 1456 1457 if (kvm_enabled()) { 1458 kvm_arm_add_vcpu_properties(obj); 1459 } 1460 1461 #ifndef CONFIG_USER_ONLY 1462 if (arm_feature(&cpu->env, ARM_FEATURE_AARCH64) && 1463 cpu_isar_feature(aa64_mte, cpu)) { 1464 object_property_add_link(obj, "tag-memory", 1465 TYPE_MEMORY_REGION, 1466 (Object **)&cpu->tag_memory, 1467 qdev_prop_allow_set_link_before_realize, 1468 OBJ_PROP_LINK_STRONG); 1469 1470 if (arm_feature(&cpu->env, ARM_FEATURE_EL3)) { 1471 object_property_add_link(obj, "secure-tag-memory", 1472 TYPE_MEMORY_REGION, 1473 (Object **)&cpu->secure_tag_memory, 1474 qdev_prop_allow_set_link_before_realize, 1475 OBJ_PROP_LINK_STRONG); 1476 } 1477 } 1478 #endif 1479 } 1480 1481 static void arm_cpu_finalizefn(Object *obj) 1482 { 1483 ARMCPU *cpu = ARM_CPU(obj); 1484 ARMELChangeHook *hook, *next; 1485 1486 g_hash_table_destroy(cpu->cp_regs); 1487 1488 QLIST_FOREACH_SAFE(hook, &cpu->pre_el_change_hooks, node, next) { 1489 QLIST_REMOVE(hook, node); 1490 g_free(hook); 1491 } 1492 QLIST_FOREACH_SAFE(hook, &cpu->el_change_hooks, node, next) { 1493 QLIST_REMOVE(hook, node); 1494 g_free(hook); 1495 } 1496 #ifndef CONFIG_USER_ONLY 1497 if (cpu->pmu_timer) { 1498 timer_free(cpu->pmu_timer); 1499 } 1500 #endif 1501 } 1502 1503 void arm_cpu_finalize_features(ARMCPU *cpu, Error **errp) 1504 { 1505 Error *local_err = NULL; 1506 1507 #ifdef TARGET_AARCH64 1508 if (arm_feature(&cpu->env, ARM_FEATURE_AARCH64)) { 1509 arm_cpu_sve_finalize(cpu, &local_err); 1510 if (local_err != NULL) { 1511 error_propagate(errp, local_err); 1512 return; 1513 } 1514 1515 arm_cpu_sme_finalize(cpu, &local_err); 1516 if (local_err != NULL) { 1517 error_propagate(errp, local_err); 1518 return; 1519 } 1520 1521 arm_cpu_pauth_finalize(cpu, &local_err); 1522 if (local_err != NULL) { 1523 error_propagate(errp, local_err); 1524 return; 1525 } 1526 1527 arm_cpu_lpa2_finalize(cpu, &local_err); 1528 if (local_err != NULL) { 1529 error_propagate(errp, local_err); 1530 return; 1531 } 1532 } 1533 #endif 1534 1535 if (kvm_enabled()) { 1536 kvm_arm_steal_time_finalize(cpu, &local_err); 1537 if (local_err != NULL) { 1538 error_propagate(errp, local_err); 1539 return; 1540 } 1541 } 1542 } 1543 1544 static void arm_cpu_realizefn(DeviceState *dev, Error **errp) 1545 { 1546 CPUState *cs = CPU(dev); 1547 ARMCPU *cpu = ARM_CPU(dev); 1548 ARMCPUClass *acc = ARM_CPU_GET_CLASS(dev); 1549 CPUARMState *env = &cpu->env; 1550 int pagebits; 1551 Error *local_err = NULL; 1552 bool no_aa32 = false; 1553 1554 /* If we needed to query the host kernel for the CPU features 1555 * then it's possible that might have failed in the initfn, but 1556 * this is the first point where we can report it. 1557 */ 1558 if (cpu->host_cpu_probe_failed) { 1559 if (!kvm_enabled() && !hvf_enabled()) { 1560 error_setg(errp, "The 'host' CPU type can only be used with KVM or HVF"); 1561 } else { 1562 error_setg(errp, "Failed to retrieve host CPU features"); 1563 } 1564 return; 1565 } 1566 1567 #ifndef CONFIG_USER_ONLY 1568 /* The NVIC and M-profile CPU are two halves of a single piece of 1569 * hardware; trying to use one without the other is a command line 1570 * error and will result in segfaults if not caught here. 1571 */ 1572 if (arm_feature(env, ARM_FEATURE_M)) { 1573 if (!env->nvic) { 1574 error_setg(errp, "This board cannot be used with Cortex-M CPUs"); 1575 return; 1576 } 1577 } else { 1578 if (env->nvic) { 1579 error_setg(errp, "This board can only be used with Cortex-M CPUs"); 1580 return; 1581 } 1582 } 1583 1584 if (!tcg_enabled() && !qtest_enabled()) { 1585 /* 1586 * We assume that no accelerator except TCG (and the "not really an 1587 * accelerator" qtest) can handle these features, because Arm hardware 1588 * virtualization can't virtualize them. 1589 * 1590 * Catch all the cases which might cause us to create more than one 1591 * address space for the CPU (otherwise we will assert() later in 1592 * cpu_address_space_init()). 1593 */ 1594 if (arm_feature(env, ARM_FEATURE_M)) { 1595 error_setg(errp, 1596 "Cannot enable %s when using an M-profile guest CPU", 1597 current_accel_name()); 1598 return; 1599 } 1600 if (cpu->has_el3) { 1601 error_setg(errp, 1602 "Cannot enable %s when guest CPU has EL3 enabled", 1603 current_accel_name()); 1604 return; 1605 } 1606 if (cpu->tag_memory) { 1607 error_setg(errp, 1608 "Cannot enable %s when guest CPUs has MTE enabled", 1609 current_accel_name()); 1610 return; 1611 } 1612 } 1613 1614 { 1615 uint64_t scale; 1616 1617 if (arm_feature(env, ARM_FEATURE_GENERIC_TIMER)) { 1618 if (!cpu->gt_cntfrq_hz) { 1619 error_setg(errp, "Invalid CNTFRQ: %"PRId64"Hz", 1620 cpu->gt_cntfrq_hz); 1621 return; 1622 } 1623 scale = gt_cntfrq_period_ns(cpu); 1624 } else { 1625 scale = GTIMER_SCALE; 1626 } 1627 1628 cpu->gt_timer[GTIMER_PHYS] = timer_new(QEMU_CLOCK_VIRTUAL, scale, 1629 arm_gt_ptimer_cb, cpu); 1630 cpu->gt_timer[GTIMER_VIRT] = timer_new(QEMU_CLOCK_VIRTUAL, scale, 1631 arm_gt_vtimer_cb, cpu); 1632 cpu->gt_timer[GTIMER_HYP] = timer_new(QEMU_CLOCK_VIRTUAL, scale, 1633 arm_gt_htimer_cb, cpu); 1634 cpu->gt_timer[GTIMER_SEC] = timer_new(QEMU_CLOCK_VIRTUAL, scale, 1635 arm_gt_stimer_cb, cpu); 1636 cpu->gt_timer[GTIMER_HYPVIRT] = timer_new(QEMU_CLOCK_VIRTUAL, scale, 1637 arm_gt_hvtimer_cb, cpu); 1638 } 1639 #endif 1640 1641 cpu_exec_realizefn(cs, &local_err); 1642 if (local_err != NULL) { 1643 error_propagate(errp, local_err); 1644 return; 1645 } 1646 1647 arm_cpu_finalize_features(cpu, &local_err); 1648 if (local_err != NULL) { 1649 error_propagate(errp, local_err); 1650 return; 1651 } 1652 1653 if (arm_feature(env, ARM_FEATURE_AARCH64) && 1654 cpu->has_vfp != cpu->has_neon) { 1655 /* 1656 * This is an architectural requirement for AArch64; AArch32 is 1657 * more flexible and permits VFP-no-Neon and Neon-no-VFP. 1658 */ 1659 error_setg(errp, 1660 "AArch64 CPUs must have both VFP and Neon or neither"); 1661 return; 1662 } 1663 1664 if (!cpu->has_vfp) { 1665 uint64_t t; 1666 uint32_t u; 1667 1668 t = cpu->isar.id_aa64isar1; 1669 t = FIELD_DP64(t, ID_AA64ISAR1, JSCVT, 0); 1670 cpu->isar.id_aa64isar1 = t; 1671 1672 t = cpu->isar.id_aa64pfr0; 1673 t = FIELD_DP64(t, ID_AA64PFR0, FP, 0xf); 1674 cpu->isar.id_aa64pfr0 = t; 1675 1676 u = cpu->isar.id_isar6; 1677 u = FIELD_DP32(u, ID_ISAR6, JSCVT, 0); 1678 u = FIELD_DP32(u, ID_ISAR6, BF16, 0); 1679 cpu->isar.id_isar6 = u; 1680 1681 u = cpu->isar.mvfr0; 1682 u = FIELD_DP32(u, MVFR0, FPSP, 0); 1683 u = FIELD_DP32(u, MVFR0, FPDP, 0); 1684 u = FIELD_DP32(u, MVFR0, FPDIVIDE, 0); 1685 u = FIELD_DP32(u, MVFR0, FPSQRT, 0); 1686 u = FIELD_DP32(u, MVFR0, FPROUND, 0); 1687 if (!arm_feature(env, ARM_FEATURE_M)) { 1688 u = FIELD_DP32(u, MVFR0, FPTRAP, 0); 1689 u = FIELD_DP32(u, MVFR0, FPSHVEC, 0); 1690 } 1691 cpu->isar.mvfr0 = u; 1692 1693 u = cpu->isar.mvfr1; 1694 u = FIELD_DP32(u, MVFR1, FPFTZ, 0); 1695 u = FIELD_DP32(u, MVFR1, FPDNAN, 0); 1696 u = FIELD_DP32(u, MVFR1, FPHP, 0); 1697 if (arm_feature(env, ARM_FEATURE_M)) { 1698 u = FIELD_DP32(u, MVFR1, FP16, 0); 1699 } 1700 cpu->isar.mvfr1 = u; 1701 1702 u = cpu->isar.mvfr2; 1703 u = FIELD_DP32(u, MVFR2, FPMISC, 0); 1704 cpu->isar.mvfr2 = u; 1705 } 1706 1707 if (!cpu->has_neon) { 1708 uint64_t t; 1709 uint32_t u; 1710 1711 unset_feature(env, ARM_FEATURE_NEON); 1712 1713 t = cpu->isar.id_aa64isar0; 1714 t = FIELD_DP64(t, ID_AA64ISAR0, AES, 0); 1715 t = FIELD_DP64(t, ID_AA64ISAR0, SHA1, 0); 1716 t = FIELD_DP64(t, ID_AA64ISAR0, SHA2, 0); 1717 t = FIELD_DP64(t, ID_AA64ISAR0, SHA3, 0); 1718 t = FIELD_DP64(t, ID_AA64ISAR0, SM3, 0); 1719 t = FIELD_DP64(t, ID_AA64ISAR0, SM4, 0); 1720 t = FIELD_DP64(t, ID_AA64ISAR0, DP, 0); 1721 cpu->isar.id_aa64isar0 = t; 1722 1723 t = cpu->isar.id_aa64isar1; 1724 t = FIELD_DP64(t, ID_AA64ISAR1, FCMA, 0); 1725 t = FIELD_DP64(t, ID_AA64ISAR1, BF16, 0); 1726 t = FIELD_DP64(t, ID_AA64ISAR1, I8MM, 0); 1727 cpu->isar.id_aa64isar1 = t; 1728 1729 t = cpu->isar.id_aa64pfr0; 1730 t = FIELD_DP64(t, ID_AA64PFR0, ADVSIMD, 0xf); 1731 cpu->isar.id_aa64pfr0 = t; 1732 1733 u = cpu->isar.id_isar5; 1734 u = FIELD_DP32(u, ID_ISAR5, AES, 0); 1735 u = FIELD_DP32(u, ID_ISAR5, SHA1, 0); 1736 u = FIELD_DP32(u, ID_ISAR5, SHA2, 0); 1737 u = FIELD_DP32(u, ID_ISAR5, RDM, 0); 1738 u = FIELD_DP32(u, ID_ISAR5, VCMA, 0); 1739 cpu->isar.id_isar5 = u; 1740 1741 u = cpu->isar.id_isar6; 1742 u = FIELD_DP32(u, ID_ISAR6, DP, 0); 1743 u = FIELD_DP32(u, ID_ISAR6, FHM, 0); 1744 u = FIELD_DP32(u, ID_ISAR6, BF16, 0); 1745 u = FIELD_DP32(u, ID_ISAR6, I8MM, 0); 1746 cpu->isar.id_isar6 = u; 1747 1748 if (!arm_feature(env, ARM_FEATURE_M)) { 1749 u = cpu->isar.mvfr1; 1750 u = FIELD_DP32(u, MVFR1, SIMDLS, 0); 1751 u = FIELD_DP32(u, MVFR1, SIMDINT, 0); 1752 u = FIELD_DP32(u, MVFR1, SIMDSP, 0); 1753 u = FIELD_DP32(u, MVFR1, SIMDHP, 0); 1754 cpu->isar.mvfr1 = u; 1755 1756 u = cpu->isar.mvfr2; 1757 u = FIELD_DP32(u, MVFR2, SIMDMISC, 0); 1758 cpu->isar.mvfr2 = u; 1759 } 1760 } 1761 1762 if (!cpu->has_neon && !cpu->has_vfp) { 1763 uint64_t t; 1764 uint32_t u; 1765 1766 t = cpu->isar.id_aa64isar0; 1767 t = FIELD_DP64(t, ID_AA64ISAR0, FHM, 0); 1768 cpu->isar.id_aa64isar0 = t; 1769 1770 t = cpu->isar.id_aa64isar1; 1771 t = FIELD_DP64(t, ID_AA64ISAR1, FRINTTS, 0); 1772 cpu->isar.id_aa64isar1 = t; 1773 1774 u = cpu->isar.mvfr0; 1775 u = FIELD_DP32(u, MVFR0, SIMDREG, 0); 1776 cpu->isar.mvfr0 = u; 1777 1778 /* Despite the name, this field covers both VFP and Neon */ 1779 u = cpu->isar.mvfr1; 1780 u = FIELD_DP32(u, MVFR1, SIMDFMAC, 0); 1781 cpu->isar.mvfr1 = u; 1782 } 1783 1784 if (arm_feature(env, ARM_FEATURE_M) && !cpu->has_dsp) { 1785 uint32_t u; 1786 1787 unset_feature(env, ARM_FEATURE_THUMB_DSP); 1788 1789 u = cpu->isar.id_isar1; 1790 u = FIELD_DP32(u, ID_ISAR1, EXTEND, 1); 1791 cpu->isar.id_isar1 = u; 1792 1793 u = cpu->isar.id_isar2; 1794 u = FIELD_DP32(u, ID_ISAR2, MULTU, 1); 1795 u = FIELD_DP32(u, ID_ISAR2, MULTS, 1); 1796 cpu->isar.id_isar2 = u; 1797 1798 u = cpu->isar.id_isar3; 1799 u = FIELD_DP32(u, ID_ISAR3, SIMD, 1); 1800 u = FIELD_DP32(u, ID_ISAR3, SATURATE, 0); 1801 cpu->isar.id_isar3 = u; 1802 } 1803 1804 /* Some features automatically imply others: */ 1805 if (arm_feature(env, ARM_FEATURE_V8)) { 1806 if (arm_feature(env, ARM_FEATURE_M)) { 1807 set_feature(env, ARM_FEATURE_V7); 1808 } else { 1809 set_feature(env, ARM_FEATURE_V7VE); 1810 } 1811 } 1812 1813 /* 1814 * There exist AArch64 cpus without AArch32 support. When KVM 1815 * queries ID_ISAR0_EL1 on such a host, the value is UNKNOWN. 1816 * Similarly, we cannot check ID_AA64PFR0 without AArch64 support. 1817 * As a general principle, we also do not make ID register 1818 * consistency checks anywhere unless using TCG, because only 1819 * for TCG would a consistency-check failure be a QEMU bug. 1820 */ 1821 if (arm_feature(&cpu->env, ARM_FEATURE_AARCH64)) { 1822 no_aa32 = !cpu_isar_feature(aa64_aa32, cpu); 1823 } 1824 1825 if (arm_feature(env, ARM_FEATURE_V7VE)) { 1826 /* v7 Virtualization Extensions. In real hardware this implies 1827 * EL2 and also the presence of the Security Extensions. 1828 * For QEMU, for backwards-compatibility we implement some 1829 * CPUs or CPU configs which have no actual EL2 or EL3 but do 1830 * include the various other features that V7VE implies. 1831 * Presence of EL2 itself is ARM_FEATURE_EL2, and of the 1832 * Security Extensions is ARM_FEATURE_EL3. 1833 */ 1834 assert(!tcg_enabled() || no_aa32 || 1835 cpu_isar_feature(aa32_arm_div, cpu)); 1836 set_feature(env, ARM_FEATURE_LPAE); 1837 set_feature(env, ARM_FEATURE_V7); 1838 } 1839 if (arm_feature(env, ARM_FEATURE_V7)) { 1840 set_feature(env, ARM_FEATURE_VAPA); 1841 set_feature(env, ARM_FEATURE_THUMB2); 1842 set_feature(env, ARM_FEATURE_MPIDR); 1843 if (!arm_feature(env, ARM_FEATURE_M)) { 1844 set_feature(env, ARM_FEATURE_V6K); 1845 } else { 1846 set_feature(env, ARM_FEATURE_V6); 1847 } 1848 1849 /* Always define VBAR for V7 CPUs even if it doesn't exist in 1850 * non-EL3 configs. This is needed by some legacy boards. 1851 */ 1852 set_feature(env, ARM_FEATURE_VBAR); 1853 } 1854 if (arm_feature(env, ARM_FEATURE_V6K)) { 1855 set_feature(env, ARM_FEATURE_V6); 1856 set_feature(env, ARM_FEATURE_MVFR); 1857 } 1858 if (arm_feature(env, ARM_FEATURE_V6)) { 1859 set_feature(env, ARM_FEATURE_V5); 1860 if (!arm_feature(env, ARM_FEATURE_M)) { 1861 assert(!tcg_enabled() || no_aa32 || 1862 cpu_isar_feature(aa32_jazelle, cpu)); 1863 set_feature(env, ARM_FEATURE_AUXCR); 1864 } 1865 } 1866 if (arm_feature(env, ARM_FEATURE_V5)) { 1867 set_feature(env, ARM_FEATURE_V4T); 1868 } 1869 if (arm_feature(env, ARM_FEATURE_LPAE)) { 1870 set_feature(env, ARM_FEATURE_V7MP); 1871 } 1872 if (arm_feature(env, ARM_FEATURE_CBAR_RO)) { 1873 set_feature(env, ARM_FEATURE_CBAR); 1874 } 1875 if (arm_feature(env, ARM_FEATURE_THUMB2) && 1876 !arm_feature(env, ARM_FEATURE_M)) { 1877 set_feature(env, ARM_FEATURE_THUMB_DSP); 1878 } 1879 1880 /* 1881 * We rely on no XScale CPU having VFP so we can use the same bits in the 1882 * TB flags field for VECSTRIDE and XSCALE_CPAR. 1883 */ 1884 assert(arm_feature(&cpu->env, ARM_FEATURE_AARCH64) || 1885 !cpu_isar_feature(aa32_vfp_simd, cpu) || 1886 !arm_feature(env, ARM_FEATURE_XSCALE)); 1887 1888 if (arm_feature(env, ARM_FEATURE_V7) && 1889 !arm_feature(env, ARM_FEATURE_M) && 1890 !arm_feature(env, ARM_FEATURE_PMSA)) { 1891 /* v7VMSA drops support for the old ARMv5 tiny pages, so we 1892 * can use 4K pages. 1893 */ 1894 pagebits = 12; 1895 } else { 1896 /* For CPUs which might have tiny 1K pages, or which have an 1897 * MPU and might have small region sizes, stick with 1K pages. 1898 */ 1899 pagebits = 10; 1900 } 1901 if (!set_preferred_target_page_bits(pagebits)) { 1902 /* This can only ever happen for hotplugging a CPU, or if 1903 * the board code incorrectly creates a CPU which it has 1904 * promised via minimum_page_size that it will not. 1905 */ 1906 error_setg(errp, "This CPU requires a smaller page size than the " 1907 "system is using"); 1908 return; 1909 } 1910 1911 /* This cpu-id-to-MPIDR affinity is used only for TCG; KVM will override it. 1912 * We don't support setting cluster ID ([16..23]) (known as Aff2 1913 * in later ARM ARM versions), or any of the higher affinity level fields, 1914 * so these bits always RAZ. 1915 */ 1916 if (cpu->mp_affinity == ARM64_AFFINITY_INVALID) { 1917 cpu->mp_affinity = arm_cpu_mp_affinity(cs->cpu_index, 1918 ARM_DEFAULT_CPUS_PER_CLUSTER); 1919 } 1920 1921 if (cpu->reset_hivecs) { 1922 cpu->reset_sctlr |= (1 << 13); 1923 } 1924 1925 if (cpu->cfgend) { 1926 if (arm_feature(&cpu->env, ARM_FEATURE_V7)) { 1927 cpu->reset_sctlr |= SCTLR_EE; 1928 } else { 1929 cpu->reset_sctlr |= SCTLR_B; 1930 } 1931 } 1932 1933 if (!arm_feature(env, ARM_FEATURE_M) && !cpu->has_el3) { 1934 /* If the has_el3 CPU property is disabled then we need to disable the 1935 * feature. 1936 */ 1937 unset_feature(env, ARM_FEATURE_EL3); 1938 1939 /* 1940 * Disable the security extension feature bits in the processor 1941 * feature registers as well. 1942 */ 1943 cpu->isar.id_pfr1 = FIELD_DP32(cpu->isar.id_pfr1, ID_PFR1, SECURITY, 0); 1944 cpu->isar.id_dfr0 = FIELD_DP32(cpu->isar.id_dfr0, ID_DFR0, COPSDBG, 0); 1945 cpu->isar.id_aa64pfr0 = FIELD_DP64(cpu->isar.id_aa64pfr0, 1946 ID_AA64PFR0, EL3, 0); 1947 } 1948 1949 if (!cpu->has_el2) { 1950 unset_feature(env, ARM_FEATURE_EL2); 1951 } 1952 1953 if (!cpu->has_pmu) { 1954 unset_feature(env, ARM_FEATURE_PMU); 1955 } 1956 if (arm_feature(env, ARM_FEATURE_PMU)) { 1957 pmu_init(cpu); 1958 1959 if (!kvm_enabled()) { 1960 arm_register_pre_el_change_hook(cpu, &pmu_pre_el_change, 0); 1961 arm_register_el_change_hook(cpu, &pmu_post_el_change, 0); 1962 } 1963 1964 #ifndef CONFIG_USER_ONLY 1965 cpu->pmu_timer = timer_new_ns(QEMU_CLOCK_VIRTUAL, arm_pmu_timer_cb, 1966 cpu); 1967 #endif 1968 } else { 1969 cpu->isar.id_aa64dfr0 = 1970 FIELD_DP64(cpu->isar.id_aa64dfr0, ID_AA64DFR0, PMUVER, 0); 1971 cpu->isar.id_dfr0 = FIELD_DP32(cpu->isar.id_dfr0, ID_DFR0, PERFMON, 0); 1972 cpu->pmceid0 = 0; 1973 cpu->pmceid1 = 0; 1974 } 1975 1976 if (!arm_feature(env, ARM_FEATURE_EL2)) { 1977 /* 1978 * Disable the hypervisor feature bits in the processor feature 1979 * registers if we don't have EL2. 1980 */ 1981 cpu->isar.id_aa64pfr0 = FIELD_DP64(cpu->isar.id_aa64pfr0, 1982 ID_AA64PFR0, EL2, 0); 1983 cpu->isar.id_pfr1 = FIELD_DP32(cpu->isar.id_pfr1, 1984 ID_PFR1, VIRTUALIZATION, 0); 1985 } 1986 1987 #ifndef CONFIG_USER_ONLY 1988 if (cpu->tag_memory == NULL && cpu_isar_feature(aa64_mte, cpu)) { 1989 /* 1990 * Disable the MTE feature bits if we do not have tag-memory 1991 * provided by the machine. 1992 */ 1993 cpu->isar.id_aa64pfr1 = 1994 FIELD_DP64(cpu->isar.id_aa64pfr1, ID_AA64PFR1, MTE, 0); 1995 } 1996 #endif 1997 1998 if (tcg_enabled()) { 1999 /* 2000 * Don't report the Statistical Profiling Extension in the ID 2001 * registers, because TCG doesn't implement it yet (not even a 2002 * minimal stub version) and guests will fall over when they 2003 * try to access the non-existent system registers for it. 2004 */ 2005 cpu->isar.id_aa64dfr0 = 2006 FIELD_DP64(cpu->isar.id_aa64dfr0, ID_AA64DFR0, PMSVER, 0); 2007 } 2008 2009 /* MPU can be configured out of a PMSA CPU either by setting has-mpu 2010 * to false or by setting pmsav7-dregion to 0. 2011 */ 2012 if (!cpu->has_mpu || cpu->pmsav7_dregion == 0) { 2013 cpu->has_mpu = false; 2014 cpu->pmsav7_dregion = 0; 2015 cpu->pmsav8r_hdregion = 0; 2016 } 2017 2018 if (arm_feature(env, ARM_FEATURE_PMSA) && 2019 arm_feature(env, ARM_FEATURE_V7)) { 2020 uint32_t nr = cpu->pmsav7_dregion; 2021 2022 if (nr > 0xff) { 2023 error_setg(errp, "PMSAv7 MPU #regions invalid %" PRIu32, nr); 2024 return; 2025 } 2026 2027 if (nr) { 2028 if (arm_feature(env, ARM_FEATURE_V8)) { 2029 /* PMSAv8 */ 2030 env->pmsav8.rbar[M_REG_NS] = g_new0(uint32_t, nr); 2031 env->pmsav8.rlar[M_REG_NS] = g_new0(uint32_t, nr); 2032 if (arm_feature(env, ARM_FEATURE_M_SECURITY)) { 2033 env->pmsav8.rbar[M_REG_S] = g_new0(uint32_t, nr); 2034 env->pmsav8.rlar[M_REG_S] = g_new0(uint32_t, nr); 2035 } 2036 } else { 2037 env->pmsav7.drbar = g_new0(uint32_t, nr); 2038 env->pmsav7.drsr = g_new0(uint32_t, nr); 2039 env->pmsav7.dracr = g_new0(uint32_t, nr); 2040 } 2041 } 2042 2043 if (cpu->pmsav8r_hdregion > 0xff) { 2044 error_setg(errp, "PMSAv8 MPU EL2 #regions invalid %" PRIu32, 2045 cpu->pmsav8r_hdregion); 2046 return; 2047 } 2048 2049 if (cpu->pmsav8r_hdregion) { 2050 env->pmsav8.hprbar = g_new0(uint32_t, 2051 cpu->pmsav8r_hdregion); 2052 env->pmsav8.hprlar = g_new0(uint32_t, 2053 cpu->pmsav8r_hdregion); 2054 } 2055 } 2056 2057 if (arm_feature(env, ARM_FEATURE_M_SECURITY)) { 2058 uint32_t nr = cpu->sau_sregion; 2059 2060 if (nr > 0xff) { 2061 error_setg(errp, "v8M SAU #regions invalid %" PRIu32, nr); 2062 return; 2063 } 2064 2065 if (nr) { 2066 env->sau.rbar = g_new0(uint32_t, nr); 2067 env->sau.rlar = g_new0(uint32_t, nr); 2068 } 2069 } 2070 2071 if (arm_feature(env, ARM_FEATURE_EL3)) { 2072 set_feature(env, ARM_FEATURE_VBAR); 2073 } 2074 2075 register_cp_regs_for_features(cpu); 2076 arm_cpu_register_gdb_regs_for_features(cpu); 2077 2078 init_cpreg_list(cpu); 2079 2080 #ifndef CONFIG_USER_ONLY 2081 MachineState *ms = MACHINE(qdev_get_machine()); 2082 unsigned int smp_cpus = ms->smp.cpus; 2083 bool has_secure = cpu->has_el3 || arm_feature(env, ARM_FEATURE_M_SECURITY); 2084 2085 /* 2086 * We must set cs->num_ases to the final value before 2087 * the first call to cpu_address_space_init. 2088 */ 2089 if (cpu->tag_memory != NULL) { 2090 cs->num_ases = 3 + has_secure; 2091 } else { 2092 cs->num_ases = 1 + has_secure; 2093 } 2094 2095 if (has_secure) { 2096 if (!cpu->secure_memory) { 2097 cpu->secure_memory = cs->memory; 2098 } 2099 cpu_address_space_init(cs, ARMASIdx_S, "cpu-secure-memory", 2100 cpu->secure_memory); 2101 } 2102 2103 if (cpu->tag_memory != NULL) { 2104 cpu_address_space_init(cs, ARMASIdx_TagNS, "cpu-tag-memory", 2105 cpu->tag_memory); 2106 if (has_secure) { 2107 cpu_address_space_init(cs, ARMASIdx_TagS, "cpu-tag-memory", 2108 cpu->secure_tag_memory); 2109 } 2110 } 2111 2112 cpu_address_space_init(cs, ARMASIdx_NS, "cpu-memory", cs->memory); 2113 2114 /* No core_count specified, default to smp_cpus. */ 2115 if (cpu->core_count == -1) { 2116 cpu->core_count = smp_cpus; 2117 } 2118 #endif 2119 2120 if (tcg_enabled()) { 2121 int dcz_blocklen = 4 << cpu->dcz_blocksize; 2122 2123 /* 2124 * We only support DCZ blocklen that fits on one page. 2125 * 2126 * Architectually this is always true. However TARGET_PAGE_SIZE 2127 * is variable and, for compatibility with -machine virt-2.7, 2128 * is only 1KiB, as an artifact of legacy ARMv5 subpage support. 2129 * But even then, while the largest architectural DCZ blocklen 2130 * is 2KiB, no cpu actually uses such a large blocklen. 2131 */ 2132 assert(dcz_blocklen <= TARGET_PAGE_SIZE); 2133 2134 /* 2135 * We only support DCZ blocksize >= 2*TAG_GRANULE, which is to say 2136 * both nibbles of each byte storing tag data may be written at once. 2137 * Since TAG_GRANULE is 16, this means that blocklen must be >= 32. 2138 */ 2139 if (cpu_isar_feature(aa64_mte, cpu)) { 2140 assert(dcz_blocklen >= 2 * TAG_GRANULE); 2141 } 2142 } 2143 2144 qemu_init_vcpu(cs); 2145 cpu_reset(cs); 2146 2147 acc->parent_realize(dev, errp); 2148 } 2149 2150 static ObjectClass *arm_cpu_class_by_name(const char *cpu_model) 2151 { 2152 ObjectClass *oc; 2153 char *typename; 2154 char **cpuname; 2155 const char *cpunamestr; 2156 2157 cpuname = g_strsplit(cpu_model, ",", 1); 2158 cpunamestr = cpuname[0]; 2159 #ifdef CONFIG_USER_ONLY 2160 /* For backwards compatibility usermode emulation allows "-cpu any", 2161 * which has the same semantics as "-cpu max". 2162 */ 2163 if (!strcmp(cpunamestr, "any")) { 2164 cpunamestr = "max"; 2165 } 2166 #endif 2167 typename = g_strdup_printf(ARM_CPU_TYPE_NAME("%s"), cpunamestr); 2168 oc = object_class_by_name(typename); 2169 g_strfreev(cpuname); 2170 g_free(typename); 2171 if (!oc || !object_class_dynamic_cast(oc, TYPE_ARM_CPU) || 2172 object_class_is_abstract(oc)) { 2173 return NULL; 2174 } 2175 return oc; 2176 } 2177 2178 static Property arm_cpu_properties[] = { 2179 DEFINE_PROP_UINT64("midr", ARMCPU, midr, 0), 2180 DEFINE_PROP_UINT64("mp-affinity", ARMCPU, 2181 mp_affinity, ARM64_AFFINITY_INVALID), 2182 DEFINE_PROP_INT32("node-id", ARMCPU, node_id, CPU_UNSET_NUMA_NODE_ID), 2183 DEFINE_PROP_INT32("core-count", ARMCPU, core_count, -1), 2184 DEFINE_PROP_END_OF_LIST() 2185 }; 2186 2187 static gchar *arm_gdb_arch_name(CPUState *cs) 2188 { 2189 ARMCPU *cpu = ARM_CPU(cs); 2190 CPUARMState *env = &cpu->env; 2191 2192 if (arm_feature(env, ARM_FEATURE_IWMMXT)) { 2193 return g_strdup("iwmmxt"); 2194 } 2195 return g_strdup("arm"); 2196 } 2197 2198 #ifndef CONFIG_USER_ONLY 2199 #include "hw/core/sysemu-cpu-ops.h" 2200 2201 static const struct SysemuCPUOps arm_sysemu_ops = { 2202 .get_phys_page_attrs_debug = arm_cpu_get_phys_page_attrs_debug, 2203 .asidx_from_attrs = arm_asidx_from_attrs, 2204 .write_elf32_note = arm_cpu_write_elf32_note, 2205 .write_elf64_note = arm_cpu_write_elf64_note, 2206 .virtio_is_big_endian = arm_cpu_virtio_is_big_endian, 2207 .legacy_vmsd = &vmstate_arm_cpu, 2208 }; 2209 #endif 2210 2211 #ifdef CONFIG_TCG 2212 static const struct TCGCPUOps arm_tcg_ops = { 2213 .initialize = arm_translate_init, 2214 .synchronize_from_tb = arm_cpu_synchronize_from_tb, 2215 .debug_excp_handler = arm_debug_excp_handler, 2216 .restore_state_to_opc = arm_restore_state_to_opc, 2217 2218 #ifdef CONFIG_USER_ONLY 2219 .record_sigsegv = arm_cpu_record_sigsegv, 2220 .record_sigbus = arm_cpu_record_sigbus, 2221 #else 2222 .tlb_fill = arm_cpu_tlb_fill, 2223 .cpu_exec_interrupt = arm_cpu_exec_interrupt, 2224 .do_interrupt = arm_cpu_do_interrupt, 2225 .do_transaction_failed = arm_cpu_do_transaction_failed, 2226 .do_unaligned_access = arm_cpu_do_unaligned_access, 2227 .adjust_watchpoint_address = arm_adjust_watchpoint_address, 2228 .debug_check_watchpoint = arm_debug_check_watchpoint, 2229 .debug_check_breakpoint = arm_debug_check_breakpoint, 2230 #endif /* !CONFIG_USER_ONLY */ 2231 }; 2232 #endif /* CONFIG_TCG */ 2233 2234 static void arm_cpu_class_init(ObjectClass *oc, void *data) 2235 { 2236 ARMCPUClass *acc = ARM_CPU_CLASS(oc); 2237 CPUClass *cc = CPU_CLASS(acc); 2238 DeviceClass *dc = DEVICE_CLASS(oc); 2239 ResettableClass *rc = RESETTABLE_CLASS(oc); 2240 2241 device_class_set_parent_realize(dc, arm_cpu_realizefn, 2242 &acc->parent_realize); 2243 2244 device_class_set_props(dc, arm_cpu_properties); 2245 2246 resettable_class_set_parent_phases(rc, NULL, arm_cpu_reset_hold, NULL, 2247 &acc->parent_phases); 2248 2249 cc->class_by_name = arm_cpu_class_by_name; 2250 cc->has_work = arm_cpu_has_work; 2251 cc->dump_state = arm_cpu_dump_state; 2252 cc->set_pc = arm_cpu_set_pc; 2253 cc->get_pc = arm_cpu_get_pc; 2254 cc->gdb_read_register = arm_cpu_gdb_read_register; 2255 cc->gdb_write_register = arm_cpu_gdb_write_register; 2256 #ifndef CONFIG_USER_ONLY 2257 cc->sysemu_ops = &arm_sysemu_ops; 2258 #endif 2259 cc->gdb_num_core_regs = 26; 2260 cc->gdb_core_xml_file = "arm-core.xml"; 2261 cc->gdb_arch_name = arm_gdb_arch_name; 2262 cc->gdb_get_dynamic_xml = arm_gdb_get_dynamic_xml; 2263 cc->gdb_stop_before_watchpoint = true; 2264 cc->disas_set_info = arm_disas_set_info; 2265 2266 #ifdef CONFIG_TCG 2267 cc->tcg_ops = &arm_tcg_ops; 2268 #endif /* CONFIG_TCG */ 2269 } 2270 2271 static void arm_cpu_instance_init(Object *obj) 2272 { 2273 ARMCPUClass *acc = ARM_CPU_GET_CLASS(obj); 2274 2275 acc->info->initfn(obj); 2276 arm_cpu_post_init(obj); 2277 } 2278 2279 static void cpu_register_class_init(ObjectClass *oc, void *data) 2280 { 2281 ARMCPUClass *acc = ARM_CPU_CLASS(oc); 2282 2283 acc->info = data; 2284 } 2285 2286 void arm_cpu_register(const ARMCPUInfo *info) 2287 { 2288 TypeInfo type_info = { 2289 .parent = TYPE_ARM_CPU, 2290 .instance_size = sizeof(ARMCPU), 2291 .instance_align = __alignof__(ARMCPU), 2292 .instance_init = arm_cpu_instance_init, 2293 .class_size = sizeof(ARMCPUClass), 2294 .class_init = info->class_init ?: cpu_register_class_init, 2295 .class_data = (void *)info, 2296 }; 2297 2298 type_info.name = g_strdup_printf("%s-" TYPE_ARM_CPU, info->name); 2299 type_register(&type_info); 2300 g_free((void *)type_info.name); 2301 } 2302 2303 static const TypeInfo arm_cpu_type_info = { 2304 .name = TYPE_ARM_CPU, 2305 .parent = TYPE_CPU, 2306 .instance_size = sizeof(ARMCPU), 2307 .instance_align = __alignof__(ARMCPU), 2308 .instance_init = arm_cpu_initfn, 2309 .instance_finalize = arm_cpu_finalizefn, 2310 .abstract = true, 2311 .class_size = sizeof(ARMCPUClass), 2312 .class_init = arm_cpu_class_init, 2313 }; 2314 2315 static void arm_cpu_register_types(void) 2316 { 2317 type_register_static(&arm_cpu_type_info); 2318 } 2319 2320 type_init(arm_cpu_register_types) 2321