1 /* 2 * QEMU ARM CPU 3 * 4 * Copyright (c) 2012 SUSE LINUX Products GmbH 5 * 6 * This program is free software; you can redistribute it and/or 7 * modify it under the terms of the GNU General Public License 8 * as published by the Free Software Foundation; either version 2 9 * of the License, or (at your option) any later version. 10 * 11 * This program is distributed in the hope that it will be useful, 12 * but WITHOUT ANY WARRANTY; without even the implied warranty of 13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 14 * GNU General Public License for more details. 15 * 16 * You should have received a copy of the GNU General Public License 17 * along with this program; if not, see 18 * <http://www.gnu.org/licenses/gpl-2.0.html> 19 */ 20 21 #include "qemu/osdep.h" 22 #include "target/arm/idau.h" 23 #include "qemu/error-report.h" 24 #include "qapi/error.h" 25 #include "cpu.h" 26 #include "internals.h" 27 #include "qemu-common.h" 28 #include "exec/exec-all.h" 29 #include "hw/qdev-properties.h" 30 #if !defined(CONFIG_USER_ONLY) 31 #include "hw/loader.h" 32 #endif 33 #include "hw/arm/arm.h" 34 #include "sysemu/sysemu.h" 35 #include "sysemu/hw_accel.h" 36 #include "kvm_arm.h" 37 #include "disas/capstone.h" 38 #include "fpu/softfloat.h" 39 40 static void arm_cpu_set_pc(CPUState *cs, vaddr value) 41 { 42 ARMCPU *cpu = ARM_CPU(cs); 43 44 cpu->env.regs[15] = value; 45 } 46 47 static bool arm_cpu_has_work(CPUState *cs) 48 { 49 ARMCPU *cpu = ARM_CPU(cs); 50 51 return (cpu->power_state != PSCI_OFF) 52 && cs->interrupt_request & 53 (CPU_INTERRUPT_FIQ | CPU_INTERRUPT_HARD 54 | CPU_INTERRUPT_VFIQ | CPU_INTERRUPT_VIRQ 55 | CPU_INTERRUPT_EXITTB); 56 } 57 58 void arm_register_el_change_hook(ARMCPU *cpu, ARMELChangeHook *hook, 59 void *opaque) 60 { 61 /* We currently only support registering a single hook function */ 62 assert(!cpu->el_change_hook); 63 cpu->el_change_hook = hook; 64 cpu->el_change_hook_opaque = opaque; 65 } 66 67 static void cp_reg_reset(gpointer key, gpointer value, gpointer opaque) 68 { 69 /* Reset a single ARMCPRegInfo register */ 70 ARMCPRegInfo *ri = value; 71 ARMCPU *cpu = opaque; 72 73 if (ri->type & (ARM_CP_SPECIAL | ARM_CP_ALIAS)) { 74 return; 75 } 76 77 if (ri->resetfn) { 78 ri->resetfn(&cpu->env, ri); 79 return; 80 } 81 82 /* A zero offset is never possible as it would be regs[0] 83 * so we use it to indicate that reset is being handled elsewhere. 84 * This is basically only used for fields in non-core coprocessors 85 * (like the pxa2xx ones). 86 */ 87 if (!ri->fieldoffset) { 88 return; 89 } 90 91 if (cpreg_field_is_64bit(ri)) { 92 CPREG_FIELD64(&cpu->env, ri) = ri->resetvalue; 93 } else { 94 CPREG_FIELD32(&cpu->env, ri) = ri->resetvalue; 95 } 96 } 97 98 static void cp_reg_check_reset(gpointer key, gpointer value, gpointer opaque) 99 { 100 /* Purely an assertion check: we've already done reset once, 101 * so now check that running the reset for the cpreg doesn't 102 * change its value. This traps bugs where two different cpregs 103 * both try to reset the same state field but to different values. 104 */ 105 ARMCPRegInfo *ri = value; 106 ARMCPU *cpu = opaque; 107 uint64_t oldvalue, newvalue; 108 109 if (ri->type & (ARM_CP_SPECIAL | ARM_CP_ALIAS | ARM_CP_NO_RAW)) { 110 return; 111 } 112 113 oldvalue = read_raw_cp_reg(&cpu->env, ri); 114 cp_reg_reset(key, value, opaque); 115 newvalue = read_raw_cp_reg(&cpu->env, ri); 116 assert(oldvalue == newvalue); 117 } 118 119 /* CPUClass::reset() */ 120 static void arm_cpu_reset(CPUState *s) 121 { 122 ARMCPU *cpu = ARM_CPU(s); 123 ARMCPUClass *acc = ARM_CPU_GET_CLASS(cpu); 124 CPUARMState *env = &cpu->env; 125 126 acc->parent_reset(s); 127 128 memset(env, 0, offsetof(CPUARMState, end_reset_fields)); 129 130 g_hash_table_foreach(cpu->cp_regs, cp_reg_reset, cpu); 131 g_hash_table_foreach(cpu->cp_regs, cp_reg_check_reset, cpu); 132 133 env->vfp.xregs[ARM_VFP_FPSID] = cpu->reset_fpsid; 134 env->vfp.xregs[ARM_VFP_MVFR0] = cpu->mvfr0; 135 env->vfp.xregs[ARM_VFP_MVFR1] = cpu->mvfr1; 136 env->vfp.xregs[ARM_VFP_MVFR2] = cpu->mvfr2; 137 138 cpu->power_state = cpu->start_powered_off ? PSCI_OFF : PSCI_ON; 139 s->halted = cpu->start_powered_off; 140 141 if (arm_feature(env, ARM_FEATURE_IWMMXT)) { 142 env->iwmmxt.cregs[ARM_IWMMXT_wCID] = 0x69051000 | 'Q'; 143 } 144 145 if (arm_feature(env, ARM_FEATURE_AARCH64)) { 146 /* 64 bit CPUs always start in 64 bit mode */ 147 env->aarch64 = 1; 148 #if defined(CONFIG_USER_ONLY) 149 env->pstate = PSTATE_MODE_EL0t; 150 /* Userspace expects access to DC ZVA, CTL_EL0 and the cache ops */ 151 env->cp15.sctlr_el[1] |= SCTLR_UCT | SCTLR_UCI | SCTLR_DZE; 152 /* and to the FP/Neon instructions */ 153 env->cp15.cpacr_el1 = deposit64(env->cp15.cpacr_el1, 20, 2, 3); 154 #else 155 /* Reset into the highest available EL */ 156 if (arm_feature(env, ARM_FEATURE_EL3)) { 157 env->pstate = PSTATE_MODE_EL3h; 158 } else if (arm_feature(env, ARM_FEATURE_EL2)) { 159 env->pstate = PSTATE_MODE_EL2h; 160 } else { 161 env->pstate = PSTATE_MODE_EL1h; 162 } 163 env->pc = cpu->rvbar; 164 #endif 165 } else { 166 #if defined(CONFIG_USER_ONLY) 167 /* Userspace expects access to cp10 and cp11 for FP/Neon */ 168 env->cp15.cpacr_el1 = deposit64(env->cp15.cpacr_el1, 20, 4, 0xf); 169 #endif 170 } 171 172 #if defined(CONFIG_USER_ONLY) 173 env->uncached_cpsr = ARM_CPU_MODE_USR; 174 /* For user mode we must enable access to coprocessors */ 175 env->vfp.xregs[ARM_VFP_FPEXC] = 1 << 30; 176 if (arm_feature(env, ARM_FEATURE_IWMMXT)) { 177 env->cp15.c15_cpar = 3; 178 } else if (arm_feature(env, ARM_FEATURE_XSCALE)) { 179 env->cp15.c15_cpar = 1; 180 } 181 #else 182 /* SVC mode with interrupts disabled. */ 183 env->uncached_cpsr = ARM_CPU_MODE_SVC; 184 env->daif = PSTATE_D | PSTATE_A | PSTATE_I | PSTATE_F; 185 186 if (arm_feature(env, ARM_FEATURE_M)) { 187 uint32_t initial_msp; /* Loaded from 0x0 */ 188 uint32_t initial_pc; /* Loaded from 0x4 */ 189 uint8_t *rom; 190 uint32_t vecbase; 191 192 if (arm_feature(env, ARM_FEATURE_M_SECURITY)) { 193 env->v7m.secure = true; 194 } else { 195 /* This bit resets to 0 if security is supported, but 1 if 196 * it is not. The bit is not present in v7M, but we set it 197 * here so we can avoid having to make checks on it conditional 198 * on ARM_FEATURE_V8 (we don't let the guest see the bit). 199 */ 200 env->v7m.aircr = R_V7M_AIRCR_BFHFNMINS_MASK; 201 } 202 203 /* In v7M the reset value of this bit is IMPDEF, but ARM recommends 204 * that it resets to 1, so QEMU always does that rather than making 205 * it dependent on CPU model. In v8M it is RES1. 206 */ 207 env->v7m.ccr[M_REG_NS] = R_V7M_CCR_STKALIGN_MASK; 208 env->v7m.ccr[M_REG_S] = R_V7M_CCR_STKALIGN_MASK; 209 if (arm_feature(env, ARM_FEATURE_V8)) { 210 /* in v8M the NONBASETHRDENA bit [0] is RES1 */ 211 env->v7m.ccr[M_REG_NS] |= R_V7M_CCR_NONBASETHRDENA_MASK; 212 env->v7m.ccr[M_REG_S] |= R_V7M_CCR_NONBASETHRDENA_MASK; 213 } 214 215 /* Unlike A/R profile, M profile defines the reset LR value */ 216 env->regs[14] = 0xffffffff; 217 218 env->v7m.vecbase[M_REG_S] = cpu->init_svtor & 0xffffff80; 219 220 /* Load the initial SP and PC from offset 0 and 4 in the vector table */ 221 vecbase = env->v7m.vecbase[env->v7m.secure]; 222 rom = rom_ptr(vecbase); 223 if (rom) { 224 /* Address zero is covered by ROM which hasn't yet been 225 * copied into physical memory. 226 */ 227 initial_msp = ldl_p(rom); 228 initial_pc = ldl_p(rom + 4); 229 } else { 230 /* Address zero not covered by a ROM blob, or the ROM blob 231 * is in non-modifiable memory and this is a second reset after 232 * it got copied into memory. In the latter case, rom_ptr 233 * will return a NULL pointer and we should use ldl_phys instead. 234 */ 235 initial_msp = ldl_phys(s->as, vecbase); 236 initial_pc = ldl_phys(s->as, vecbase + 4); 237 } 238 239 env->regs[13] = initial_msp & 0xFFFFFFFC; 240 env->regs[15] = initial_pc & ~1; 241 env->thumb = initial_pc & 1; 242 } 243 244 /* AArch32 has a hard highvec setting of 0xFFFF0000. If we are currently 245 * executing as AArch32 then check if highvecs are enabled and 246 * adjust the PC accordingly. 247 */ 248 if (A32_BANKED_CURRENT_REG_GET(env, sctlr) & SCTLR_V) { 249 env->regs[15] = 0xFFFF0000; 250 } 251 252 /* M profile requires that reset clears the exclusive monitor; 253 * A profile does not, but clearing it makes more sense than having it 254 * set with an exclusive access on address zero. 255 */ 256 arm_clear_exclusive(env); 257 258 env->vfp.xregs[ARM_VFP_FPEXC] = 0; 259 #endif 260 261 if (arm_feature(env, ARM_FEATURE_PMSA)) { 262 if (cpu->pmsav7_dregion > 0) { 263 if (arm_feature(env, ARM_FEATURE_V8)) { 264 memset(env->pmsav8.rbar[M_REG_NS], 0, 265 sizeof(*env->pmsav8.rbar[M_REG_NS]) 266 * cpu->pmsav7_dregion); 267 memset(env->pmsav8.rlar[M_REG_NS], 0, 268 sizeof(*env->pmsav8.rlar[M_REG_NS]) 269 * cpu->pmsav7_dregion); 270 if (arm_feature(env, ARM_FEATURE_M_SECURITY)) { 271 memset(env->pmsav8.rbar[M_REG_S], 0, 272 sizeof(*env->pmsav8.rbar[M_REG_S]) 273 * cpu->pmsav7_dregion); 274 memset(env->pmsav8.rlar[M_REG_S], 0, 275 sizeof(*env->pmsav8.rlar[M_REG_S]) 276 * cpu->pmsav7_dregion); 277 } 278 } else if (arm_feature(env, ARM_FEATURE_V7)) { 279 memset(env->pmsav7.drbar, 0, 280 sizeof(*env->pmsav7.drbar) * cpu->pmsav7_dregion); 281 memset(env->pmsav7.drsr, 0, 282 sizeof(*env->pmsav7.drsr) * cpu->pmsav7_dregion); 283 memset(env->pmsav7.dracr, 0, 284 sizeof(*env->pmsav7.dracr) * cpu->pmsav7_dregion); 285 } 286 } 287 env->pmsav7.rnr[M_REG_NS] = 0; 288 env->pmsav7.rnr[M_REG_S] = 0; 289 env->pmsav8.mair0[M_REG_NS] = 0; 290 env->pmsav8.mair0[M_REG_S] = 0; 291 env->pmsav8.mair1[M_REG_NS] = 0; 292 env->pmsav8.mair1[M_REG_S] = 0; 293 } 294 295 if (arm_feature(env, ARM_FEATURE_M_SECURITY)) { 296 if (cpu->sau_sregion > 0) { 297 memset(env->sau.rbar, 0, sizeof(*env->sau.rbar) * cpu->sau_sregion); 298 memset(env->sau.rlar, 0, sizeof(*env->sau.rlar) * cpu->sau_sregion); 299 } 300 env->sau.rnr = 0; 301 /* SAU_CTRL reset value is IMPDEF; we choose 0, which is what 302 * the Cortex-M33 does. 303 */ 304 env->sau.ctrl = 0; 305 } 306 307 set_flush_to_zero(1, &env->vfp.standard_fp_status); 308 set_flush_inputs_to_zero(1, &env->vfp.standard_fp_status); 309 set_default_nan_mode(1, &env->vfp.standard_fp_status); 310 set_float_detect_tininess(float_tininess_before_rounding, 311 &env->vfp.fp_status); 312 set_float_detect_tininess(float_tininess_before_rounding, 313 &env->vfp.standard_fp_status); 314 #ifndef CONFIG_USER_ONLY 315 if (kvm_enabled()) { 316 kvm_arm_reset_vcpu(cpu); 317 } 318 #endif 319 320 hw_breakpoint_update_all(cpu); 321 hw_watchpoint_update_all(cpu); 322 } 323 324 bool arm_cpu_exec_interrupt(CPUState *cs, int interrupt_request) 325 { 326 CPUClass *cc = CPU_GET_CLASS(cs); 327 CPUARMState *env = cs->env_ptr; 328 uint32_t cur_el = arm_current_el(env); 329 bool secure = arm_is_secure(env); 330 uint32_t target_el; 331 uint32_t excp_idx; 332 bool ret = false; 333 334 if (interrupt_request & CPU_INTERRUPT_FIQ) { 335 excp_idx = EXCP_FIQ; 336 target_el = arm_phys_excp_target_el(cs, excp_idx, cur_el, secure); 337 if (arm_excp_unmasked(cs, excp_idx, target_el)) { 338 cs->exception_index = excp_idx; 339 env->exception.target_el = target_el; 340 cc->do_interrupt(cs); 341 ret = true; 342 } 343 } 344 if (interrupt_request & CPU_INTERRUPT_HARD) { 345 excp_idx = EXCP_IRQ; 346 target_el = arm_phys_excp_target_el(cs, excp_idx, cur_el, secure); 347 if (arm_excp_unmasked(cs, excp_idx, target_el)) { 348 cs->exception_index = excp_idx; 349 env->exception.target_el = target_el; 350 cc->do_interrupt(cs); 351 ret = true; 352 } 353 } 354 if (interrupt_request & CPU_INTERRUPT_VIRQ) { 355 excp_idx = EXCP_VIRQ; 356 target_el = 1; 357 if (arm_excp_unmasked(cs, excp_idx, target_el)) { 358 cs->exception_index = excp_idx; 359 env->exception.target_el = target_el; 360 cc->do_interrupt(cs); 361 ret = true; 362 } 363 } 364 if (interrupt_request & CPU_INTERRUPT_VFIQ) { 365 excp_idx = EXCP_VFIQ; 366 target_el = 1; 367 if (arm_excp_unmasked(cs, excp_idx, target_el)) { 368 cs->exception_index = excp_idx; 369 env->exception.target_el = target_el; 370 cc->do_interrupt(cs); 371 ret = true; 372 } 373 } 374 375 return ret; 376 } 377 378 #if !defined(CONFIG_USER_ONLY) || !defined(TARGET_AARCH64) 379 static bool arm_v7m_cpu_exec_interrupt(CPUState *cs, int interrupt_request) 380 { 381 CPUClass *cc = CPU_GET_CLASS(cs); 382 ARMCPU *cpu = ARM_CPU(cs); 383 CPUARMState *env = &cpu->env; 384 bool ret = false; 385 386 /* ARMv7-M interrupt masking works differently than -A or -R. 387 * There is no FIQ/IRQ distinction. Instead of I and F bits 388 * masking FIQ and IRQ interrupts, an exception is taken only 389 * if it is higher priority than the current execution priority 390 * (which depends on state like BASEPRI, FAULTMASK and the 391 * currently active exception). 392 */ 393 if (interrupt_request & CPU_INTERRUPT_HARD 394 && (armv7m_nvic_can_take_pending_exception(env->nvic))) { 395 cs->exception_index = EXCP_IRQ; 396 cc->do_interrupt(cs); 397 ret = true; 398 } 399 return ret; 400 } 401 #endif 402 403 #ifndef CONFIG_USER_ONLY 404 static void arm_cpu_set_irq(void *opaque, int irq, int level) 405 { 406 ARMCPU *cpu = opaque; 407 CPUARMState *env = &cpu->env; 408 CPUState *cs = CPU(cpu); 409 static const int mask[] = { 410 [ARM_CPU_IRQ] = CPU_INTERRUPT_HARD, 411 [ARM_CPU_FIQ] = CPU_INTERRUPT_FIQ, 412 [ARM_CPU_VIRQ] = CPU_INTERRUPT_VIRQ, 413 [ARM_CPU_VFIQ] = CPU_INTERRUPT_VFIQ 414 }; 415 416 switch (irq) { 417 case ARM_CPU_VIRQ: 418 case ARM_CPU_VFIQ: 419 assert(arm_feature(env, ARM_FEATURE_EL2)); 420 /* fall through */ 421 case ARM_CPU_IRQ: 422 case ARM_CPU_FIQ: 423 if (level) { 424 cpu_interrupt(cs, mask[irq]); 425 } else { 426 cpu_reset_interrupt(cs, mask[irq]); 427 } 428 break; 429 default: 430 g_assert_not_reached(); 431 } 432 } 433 434 static void arm_cpu_kvm_set_irq(void *opaque, int irq, int level) 435 { 436 #ifdef CONFIG_KVM 437 ARMCPU *cpu = opaque; 438 CPUState *cs = CPU(cpu); 439 int kvm_irq = KVM_ARM_IRQ_TYPE_CPU << KVM_ARM_IRQ_TYPE_SHIFT; 440 441 switch (irq) { 442 case ARM_CPU_IRQ: 443 kvm_irq |= KVM_ARM_IRQ_CPU_IRQ; 444 break; 445 case ARM_CPU_FIQ: 446 kvm_irq |= KVM_ARM_IRQ_CPU_FIQ; 447 break; 448 default: 449 g_assert_not_reached(); 450 } 451 kvm_irq |= cs->cpu_index << KVM_ARM_IRQ_VCPU_SHIFT; 452 kvm_set_irq(kvm_state, kvm_irq, level ? 1 : 0); 453 #endif 454 } 455 456 static bool arm_cpu_virtio_is_big_endian(CPUState *cs) 457 { 458 ARMCPU *cpu = ARM_CPU(cs); 459 CPUARMState *env = &cpu->env; 460 461 cpu_synchronize_state(cs); 462 return arm_cpu_data_is_big_endian(env); 463 } 464 465 #endif 466 467 static inline void set_feature(CPUARMState *env, int feature) 468 { 469 env->features |= 1ULL << feature; 470 } 471 472 static inline void unset_feature(CPUARMState *env, int feature) 473 { 474 env->features &= ~(1ULL << feature); 475 } 476 477 static int 478 print_insn_thumb1(bfd_vma pc, disassemble_info *info) 479 { 480 return print_insn_arm(pc | 1, info); 481 } 482 483 static void arm_disas_set_info(CPUState *cpu, disassemble_info *info) 484 { 485 ARMCPU *ac = ARM_CPU(cpu); 486 CPUARMState *env = &ac->env; 487 bool sctlr_b; 488 489 if (is_a64(env)) { 490 /* We might not be compiled with the A64 disassembler 491 * because it needs a C++ compiler. Leave print_insn 492 * unset in this case to use the caller default behaviour. 493 */ 494 #if defined(CONFIG_ARM_A64_DIS) 495 info->print_insn = print_insn_arm_a64; 496 #endif 497 info->cap_arch = CS_ARCH_ARM64; 498 info->cap_insn_unit = 4; 499 info->cap_insn_split = 4; 500 } else { 501 int cap_mode; 502 if (env->thumb) { 503 info->print_insn = print_insn_thumb1; 504 info->cap_insn_unit = 2; 505 info->cap_insn_split = 4; 506 cap_mode = CS_MODE_THUMB; 507 } else { 508 info->print_insn = print_insn_arm; 509 info->cap_insn_unit = 4; 510 info->cap_insn_split = 4; 511 cap_mode = CS_MODE_ARM; 512 } 513 if (arm_feature(env, ARM_FEATURE_V8)) { 514 cap_mode |= CS_MODE_V8; 515 } 516 if (arm_feature(env, ARM_FEATURE_M)) { 517 cap_mode |= CS_MODE_MCLASS; 518 } 519 info->cap_arch = CS_ARCH_ARM; 520 info->cap_mode = cap_mode; 521 } 522 523 sctlr_b = arm_sctlr_b(env); 524 if (bswap_code(sctlr_b)) { 525 #ifdef TARGET_WORDS_BIGENDIAN 526 info->endian = BFD_ENDIAN_LITTLE; 527 #else 528 info->endian = BFD_ENDIAN_BIG; 529 #endif 530 } 531 info->flags &= ~INSN_ARM_BE32; 532 #ifndef CONFIG_USER_ONLY 533 if (sctlr_b) { 534 info->flags |= INSN_ARM_BE32; 535 } 536 #endif 537 } 538 539 uint64_t arm_cpu_mp_affinity(int idx, uint8_t clustersz) 540 { 541 uint32_t Aff1 = idx / clustersz; 542 uint32_t Aff0 = idx % clustersz; 543 return (Aff1 << ARM_AFF1_SHIFT) | Aff0; 544 } 545 546 static void arm_cpu_initfn(Object *obj) 547 { 548 CPUState *cs = CPU(obj); 549 ARMCPU *cpu = ARM_CPU(obj); 550 551 cs->env_ptr = &cpu->env; 552 cpu->cp_regs = g_hash_table_new_full(g_int_hash, g_int_equal, 553 g_free, g_free); 554 555 #ifndef CONFIG_USER_ONLY 556 /* Our inbound IRQ and FIQ lines */ 557 if (kvm_enabled()) { 558 /* VIRQ and VFIQ are unused with KVM but we add them to maintain 559 * the same interface as non-KVM CPUs. 560 */ 561 qdev_init_gpio_in(DEVICE(cpu), arm_cpu_kvm_set_irq, 4); 562 } else { 563 qdev_init_gpio_in(DEVICE(cpu), arm_cpu_set_irq, 4); 564 } 565 566 cpu->gt_timer[GTIMER_PHYS] = timer_new(QEMU_CLOCK_VIRTUAL, GTIMER_SCALE, 567 arm_gt_ptimer_cb, cpu); 568 cpu->gt_timer[GTIMER_VIRT] = timer_new(QEMU_CLOCK_VIRTUAL, GTIMER_SCALE, 569 arm_gt_vtimer_cb, cpu); 570 cpu->gt_timer[GTIMER_HYP] = timer_new(QEMU_CLOCK_VIRTUAL, GTIMER_SCALE, 571 arm_gt_htimer_cb, cpu); 572 cpu->gt_timer[GTIMER_SEC] = timer_new(QEMU_CLOCK_VIRTUAL, GTIMER_SCALE, 573 arm_gt_stimer_cb, cpu); 574 qdev_init_gpio_out(DEVICE(cpu), cpu->gt_timer_outputs, 575 ARRAY_SIZE(cpu->gt_timer_outputs)); 576 577 qdev_init_gpio_out_named(DEVICE(cpu), &cpu->gicv3_maintenance_interrupt, 578 "gicv3-maintenance-interrupt", 1); 579 qdev_init_gpio_out_named(DEVICE(cpu), &cpu->pmu_interrupt, 580 "pmu-interrupt", 1); 581 #endif 582 583 /* DTB consumers generally don't in fact care what the 'compatible' 584 * string is, so always provide some string and trust that a hypothetical 585 * picky DTB consumer will also provide a helpful error message. 586 */ 587 cpu->dtb_compatible = "qemu,unknown"; 588 cpu->psci_version = 1; /* By default assume PSCI v0.1 */ 589 cpu->kvm_target = QEMU_KVM_ARM_TARGET_NONE; 590 591 if (tcg_enabled()) { 592 cpu->psci_version = 2; /* TCG implements PSCI 0.2 */ 593 } 594 } 595 596 static Property arm_cpu_reset_cbar_property = 597 DEFINE_PROP_UINT64("reset-cbar", ARMCPU, reset_cbar, 0); 598 599 static Property arm_cpu_reset_hivecs_property = 600 DEFINE_PROP_BOOL("reset-hivecs", ARMCPU, reset_hivecs, false); 601 602 static Property arm_cpu_rvbar_property = 603 DEFINE_PROP_UINT64("rvbar", ARMCPU, rvbar, 0); 604 605 static Property arm_cpu_has_el2_property = 606 DEFINE_PROP_BOOL("has_el2", ARMCPU, has_el2, true); 607 608 static Property arm_cpu_has_el3_property = 609 DEFINE_PROP_BOOL("has_el3", ARMCPU, has_el3, true); 610 611 static Property arm_cpu_cfgend_property = 612 DEFINE_PROP_BOOL("cfgend", ARMCPU, cfgend, false); 613 614 /* use property name "pmu" to match other archs and virt tools */ 615 static Property arm_cpu_has_pmu_property = 616 DEFINE_PROP_BOOL("pmu", ARMCPU, has_pmu, true); 617 618 static Property arm_cpu_has_mpu_property = 619 DEFINE_PROP_BOOL("has-mpu", ARMCPU, has_mpu, true); 620 621 /* This is like DEFINE_PROP_UINT32 but it doesn't set the default value, 622 * because the CPU initfn will have already set cpu->pmsav7_dregion to 623 * the right value for that particular CPU type, and we don't want 624 * to override that with an incorrect constant value. 625 */ 626 static Property arm_cpu_pmsav7_dregion_property = 627 DEFINE_PROP_UNSIGNED_NODEFAULT("pmsav7-dregion", ARMCPU, 628 pmsav7_dregion, 629 qdev_prop_uint32, uint32_t); 630 631 /* M profile: initial value of the Secure VTOR */ 632 static Property arm_cpu_initsvtor_property = 633 DEFINE_PROP_UINT32("init-svtor", ARMCPU, init_svtor, 0); 634 635 static void arm_cpu_post_init(Object *obj) 636 { 637 ARMCPU *cpu = ARM_CPU(obj); 638 639 /* M profile implies PMSA. We have to do this here rather than 640 * in realize with the other feature-implication checks because 641 * we look at the PMSA bit to see if we should add some properties. 642 */ 643 if (arm_feature(&cpu->env, ARM_FEATURE_M)) { 644 set_feature(&cpu->env, ARM_FEATURE_PMSA); 645 } 646 647 if (arm_feature(&cpu->env, ARM_FEATURE_CBAR) || 648 arm_feature(&cpu->env, ARM_FEATURE_CBAR_RO)) { 649 qdev_property_add_static(DEVICE(obj), &arm_cpu_reset_cbar_property, 650 &error_abort); 651 } 652 653 if (!arm_feature(&cpu->env, ARM_FEATURE_M)) { 654 qdev_property_add_static(DEVICE(obj), &arm_cpu_reset_hivecs_property, 655 &error_abort); 656 } 657 658 if (arm_feature(&cpu->env, ARM_FEATURE_AARCH64)) { 659 qdev_property_add_static(DEVICE(obj), &arm_cpu_rvbar_property, 660 &error_abort); 661 } 662 663 if (arm_feature(&cpu->env, ARM_FEATURE_EL3)) { 664 /* Add the has_el3 state CPU property only if EL3 is allowed. This will 665 * prevent "has_el3" from existing on CPUs which cannot support EL3. 666 */ 667 qdev_property_add_static(DEVICE(obj), &arm_cpu_has_el3_property, 668 &error_abort); 669 670 #ifndef CONFIG_USER_ONLY 671 object_property_add_link(obj, "secure-memory", 672 TYPE_MEMORY_REGION, 673 (Object **)&cpu->secure_memory, 674 qdev_prop_allow_set_link_before_realize, 675 OBJ_PROP_LINK_UNREF_ON_RELEASE, 676 &error_abort); 677 #endif 678 } 679 680 if (arm_feature(&cpu->env, ARM_FEATURE_EL2)) { 681 qdev_property_add_static(DEVICE(obj), &arm_cpu_has_el2_property, 682 &error_abort); 683 } 684 685 if (arm_feature(&cpu->env, ARM_FEATURE_PMU)) { 686 qdev_property_add_static(DEVICE(obj), &arm_cpu_has_pmu_property, 687 &error_abort); 688 } 689 690 if (arm_feature(&cpu->env, ARM_FEATURE_PMSA)) { 691 qdev_property_add_static(DEVICE(obj), &arm_cpu_has_mpu_property, 692 &error_abort); 693 if (arm_feature(&cpu->env, ARM_FEATURE_V7)) { 694 qdev_property_add_static(DEVICE(obj), 695 &arm_cpu_pmsav7_dregion_property, 696 &error_abort); 697 } 698 } 699 700 if (arm_feature(&cpu->env, ARM_FEATURE_M_SECURITY)) { 701 object_property_add_link(obj, "idau", TYPE_IDAU_INTERFACE, &cpu->idau, 702 qdev_prop_allow_set_link_before_realize, 703 OBJ_PROP_LINK_UNREF_ON_RELEASE, 704 &error_abort); 705 qdev_property_add_static(DEVICE(obj), &arm_cpu_initsvtor_property, 706 &error_abort); 707 } 708 709 qdev_property_add_static(DEVICE(obj), &arm_cpu_cfgend_property, 710 &error_abort); 711 } 712 713 static void arm_cpu_finalizefn(Object *obj) 714 { 715 ARMCPU *cpu = ARM_CPU(obj); 716 g_hash_table_destroy(cpu->cp_regs); 717 } 718 719 static void arm_cpu_realizefn(DeviceState *dev, Error **errp) 720 { 721 CPUState *cs = CPU(dev); 722 ARMCPU *cpu = ARM_CPU(dev); 723 ARMCPUClass *acc = ARM_CPU_GET_CLASS(dev); 724 CPUARMState *env = &cpu->env; 725 int pagebits; 726 Error *local_err = NULL; 727 728 cpu_exec_realizefn(cs, &local_err); 729 if (local_err != NULL) { 730 error_propagate(errp, local_err); 731 return; 732 } 733 734 /* Some features automatically imply others: */ 735 if (arm_feature(env, ARM_FEATURE_V8)) { 736 set_feature(env, ARM_FEATURE_V7); 737 set_feature(env, ARM_FEATURE_ARM_DIV); 738 set_feature(env, ARM_FEATURE_LPAE); 739 } 740 if (arm_feature(env, ARM_FEATURE_V7)) { 741 set_feature(env, ARM_FEATURE_VAPA); 742 set_feature(env, ARM_FEATURE_THUMB2); 743 set_feature(env, ARM_FEATURE_MPIDR); 744 if (!arm_feature(env, ARM_FEATURE_M)) { 745 set_feature(env, ARM_FEATURE_V6K); 746 } else { 747 set_feature(env, ARM_FEATURE_V6); 748 } 749 750 /* Always define VBAR for V7 CPUs even if it doesn't exist in 751 * non-EL3 configs. This is needed by some legacy boards. 752 */ 753 set_feature(env, ARM_FEATURE_VBAR); 754 } 755 if (arm_feature(env, ARM_FEATURE_V6K)) { 756 set_feature(env, ARM_FEATURE_V6); 757 set_feature(env, ARM_FEATURE_MVFR); 758 } 759 if (arm_feature(env, ARM_FEATURE_V6)) { 760 set_feature(env, ARM_FEATURE_V5); 761 set_feature(env, ARM_FEATURE_JAZELLE); 762 if (!arm_feature(env, ARM_FEATURE_M)) { 763 set_feature(env, ARM_FEATURE_AUXCR); 764 } 765 } 766 if (arm_feature(env, ARM_FEATURE_V5)) { 767 set_feature(env, ARM_FEATURE_V4T); 768 } 769 if (arm_feature(env, ARM_FEATURE_M)) { 770 set_feature(env, ARM_FEATURE_THUMB_DIV); 771 } 772 if (arm_feature(env, ARM_FEATURE_ARM_DIV)) { 773 set_feature(env, ARM_FEATURE_THUMB_DIV); 774 } 775 if (arm_feature(env, ARM_FEATURE_VFP4)) { 776 set_feature(env, ARM_FEATURE_VFP3); 777 set_feature(env, ARM_FEATURE_VFP_FP16); 778 } 779 if (arm_feature(env, ARM_FEATURE_VFP3)) { 780 set_feature(env, ARM_FEATURE_VFP); 781 } 782 if (arm_feature(env, ARM_FEATURE_LPAE)) { 783 set_feature(env, ARM_FEATURE_V7MP); 784 set_feature(env, ARM_FEATURE_PXN); 785 } 786 if (arm_feature(env, ARM_FEATURE_CBAR_RO)) { 787 set_feature(env, ARM_FEATURE_CBAR); 788 } 789 if (arm_feature(env, ARM_FEATURE_THUMB2) && 790 !arm_feature(env, ARM_FEATURE_M)) { 791 set_feature(env, ARM_FEATURE_THUMB_DSP); 792 } 793 794 if (arm_feature(env, ARM_FEATURE_V7) && 795 !arm_feature(env, ARM_FEATURE_M) && 796 !arm_feature(env, ARM_FEATURE_PMSA)) { 797 /* v7VMSA drops support for the old ARMv5 tiny pages, so we 798 * can use 4K pages. 799 */ 800 pagebits = 12; 801 } else { 802 /* For CPUs which might have tiny 1K pages, or which have an 803 * MPU and might have small region sizes, stick with 1K pages. 804 */ 805 pagebits = 10; 806 } 807 if (!set_preferred_target_page_bits(pagebits)) { 808 /* This can only ever happen for hotplugging a CPU, or if 809 * the board code incorrectly creates a CPU which it has 810 * promised via minimum_page_size that it will not. 811 */ 812 error_setg(errp, "This CPU requires a smaller page size than the " 813 "system is using"); 814 return; 815 } 816 817 /* This cpu-id-to-MPIDR affinity is used only for TCG; KVM will override it. 818 * We don't support setting cluster ID ([16..23]) (known as Aff2 819 * in later ARM ARM versions), or any of the higher affinity level fields, 820 * so these bits always RAZ. 821 */ 822 if (cpu->mp_affinity == ARM64_AFFINITY_INVALID) { 823 cpu->mp_affinity = arm_cpu_mp_affinity(cs->cpu_index, 824 ARM_DEFAULT_CPUS_PER_CLUSTER); 825 } 826 827 if (cpu->reset_hivecs) { 828 cpu->reset_sctlr |= (1 << 13); 829 } 830 831 if (cpu->cfgend) { 832 if (arm_feature(&cpu->env, ARM_FEATURE_V7)) { 833 cpu->reset_sctlr |= SCTLR_EE; 834 } else { 835 cpu->reset_sctlr |= SCTLR_B; 836 } 837 } 838 839 if (!cpu->has_el3) { 840 /* If the has_el3 CPU property is disabled then we need to disable the 841 * feature. 842 */ 843 unset_feature(env, ARM_FEATURE_EL3); 844 845 /* Disable the security extension feature bits in the processor feature 846 * registers as well. These are id_pfr1[7:4] and id_aa64pfr0[15:12]. 847 */ 848 cpu->id_pfr1 &= ~0xf0; 849 cpu->id_aa64pfr0 &= ~0xf000; 850 } 851 852 if (!cpu->has_el2) { 853 unset_feature(env, ARM_FEATURE_EL2); 854 } 855 856 if (!cpu->has_pmu) { 857 unset_feature(env, ARM_FEATURE_PMU); 858 cpu->id_aa64dfr0 &= ~0xf00; 859 } 860 861 if (!arm_feature(env, ARM_FEATURE_EL2)) { 862 /* Disable the hypervisor feature bits in the processor feature 863 * registers if we don't have EL2. These are id_pfr1[15:12] and 864 * id_aa64pfr0_el1[11:8]. 865 */ 866 cpu->id_aa64pfr0 &= ~0xf00; 867 cpu->id_pfr1 &= ~0xf000; 868 } 869 870 /* MPU can be configured out of a PMSA CPU either by setting has-mpu 871 * to false or by setting pmsav7-dregion to 0. 872 */ 873 if (!cpu->has_mpu) { 874 cpu->pmsav7_dregion = 0; 875 } 876 if (cpu->pmsav7_dregion == 0) { 877 cpu->has_mpu = false; 878 } 879 880 if (arm_feature(env, ARM_FEATURE_PMSA) && 881 arm_feature(env, ARM_FEATURE_V7)) { 882 uint32_t nr = cpu->pmsav7_dregion; 883 884 if (nr > 0xff) { 885 error_setg(errp, "PMSAv7 MPU #regions invalid %" PRIu32, nr); 886 return; 887 } 888 889 if (nr) { 890 if (arm_feature(env, ARM_FEATURE_V8)) { 891 /* PMSAv8 */ 892 env->pmsav8.rbar[M_REG_NS] = g_new0(uint32_t, nr); 893 env->pmsav8.rlar[M_REG_NS] = g_new0(uint32_t, nr); 894 if (arm_feature(env, ARM_FEATURE_M_SECURITY)) { 895 env->pmsav8.rbar[M_REG_S] = g_new0(uint32_t, nr); 896 env->pmsav8.rlar[M_REG_S] = g_new0(uint32_t, nr); 897 } 898 } else { 899 env->pmsav7.drbar = g_new0(uint32_t, nr); 900 env->pmsav7.drsr = g_new0(uint32_t, nr); 901 env->pmsav7.dracr = g_new0(uint32_t, nr); 902 } 903 } 904 } 905 906 if (arm_feature(env, ARM_FEATURE_M_SECURITY)) { 907 uint32_t nr = cpu->sau_sregion; 908 909 if (nr > 0xff) { 910 error_setg(errp, "v8M SAU #regions invalid %" PRIu32, nr); 911 return; 912 } 913 914 if (nr) { 915 env->sau.rbar = g_new0(uint32_t, nr); 916 env->sau.rlar = g_new0(uint32_t, nr); 917 } 918 } 919 920 if (arm_feature(env, ARM_FEATURE_EL3)) { 921 set_feature(env, ARM_FEATURE_VBAR); 922 } 923 924 register_cp_regs_for_features(cpu); 925 arm_cpu_register_gdb_regs_for_features(cpu); 926 927 init_cpreg_list(cpu); 928 929 #ifndef CONFIG_USER_ONLY 930 if (cpu->has_el3 || arm_feature(env, ARM_FEATURE_M_SECURITY)) { 931 cs->num_ases = 2; 932 933 if (!cpu->secure_memory) { 934 cpu->secure_memory = cs->memory; 935 } 936 cpu_address_space_init(cs, ARMASIdx_S, "cpu-secure-memory", 937 cpu->secure_memory); 938 } else { 939 cs->num_ases = 1; 940 } 941 cpu_address_space_init(cs, ARMASIdx_NS, "cpu-memory", cs->memory); 942 #endif 943 944 qemu_init_vcpu(cs); 945 cpu_reset(cs); 946 947 acc->parent_realize(dev, errp); 948 } 949 950 static ObjectClass *arm_cpu_class_by_name(const char *cpu_model) 951 { 952 ObjectClass *oc; 953 char *typename; 954 char **cpuname; 955 956 cpuname = g_strsplit(cpu_model, ",", 1); 957 typename = g_strdup_printf(ARM_CPU_TYPE_NAME("%s"), cpuname[0]); 958 oc = object_class_by_name(typename); 959 g_strfreev(cpuname); 960 g_free(typename); 961 if (!oc || !object_class_dynamic_cast(oc, TYPE_ARM_CPU) || 962 object_class_is_abstract(oc)) { 963 return NULL; 964 } 965 return oc; 966 } 967 968 /* CPU models. These are not needed for the AArch64 linux-user build. */ 969 #if !defined(CONFIG_USER_ONLY) || !defined(TARGET_AARCH64) 970 971 static void arm926_initfn(Object *obj) 972 { 973 ARMCPU *cpu = ARM_CPU(obj); 974 975 cpu->dtb_compatible = "arm,arm926"; 976 set_feature(&cpu->env, ARM_FEATURE_V5); 977 set_feature(&cpu->env, ARM_FEATURE_VFP); 978 set_feature(&cpu->env, ARM_FEATURE_DUMMY_C15_REGS); 979 set_feature(&cpu->env, ARM_FEATURE_CACHE_TEST_CLEAN); 980 set_feature(&cpu->env, ARM_FEATURE_JAZELLE); 981 cpu->midr = 0x41069265; 982 cpu->reset_fpsid = 0x41011090; 983 cpu->ctr = 0x1dd20d2; 984 cpu->reset_sctlr = 0x00090078; 985 } 986 987 static void arm946_initfn(Object *obj) 988 { 989 ARMCPU *cpu = ARM_CPU(obj); 990 991 cpu->dtb_compatible = "arm,arm946"; 992 set_feature(&cpu->env, ARM_FEATURE_V5); 993 set_feature(&cpu->env, ARM_FEATURE_PMSA); 994 set_feature(&cpu->env, ARM_FEATURE_DUMMY_C15_REGS); 995 cpu->midr = 0x41059461; 996 cpu->ctr = 0x0f004006; 997 cpu->reset_sctlr = 0x00000078; 998 } 999 1000 static void arm1026_initfn(Object *obj) 1001 { 1002 ARMCPU *cpu = ARM_CPU(obj); 1003 1004 cpu->dtb_compatible = "arm,arm1026"; 1005 set_feature(&cpu->env, ARM_FEATURE_V5); 1006 set_feature(&cpu->env, ARM_FEATURE_VFP); 1007 set_feature(&cpu->env, ARM_FEATURE_AUXCR); 1008 set_feature(&cpu->env, ARM_FEATURE_DUMMY_C15_REGS); 1009 set_feature(&cpu->env, ARM_FEATURE_CACHE_TEST_CLEAN); 1010 set_feature(&cpu->env, ARM_FEATURE_JAZELLE); 1011 cpu->midr = 0x4106a262; 1012 cpu->reset_fpsid = 0x410110a0; 1013 cpu->ctr = 0x1dd20d2; 1014 cpu->reset_sctlr = 0x00090078; 1015 cpu->reset_auxcr = 1; 1016 { 1017 /* The 1026 had an IFAR at c6,c0,0,1 rather than the ARMv6 c6,c0,0,2 */ 1018 ARMCPRegInfo ifar = { 1019 .name = "IFAR", .cp = 15, .crn = 6, .crm = 0, .opc1 = 0, .opc2 = 1, 1020 .access = PL1_RW, 1021 .fieldoffset = offsetof(CPUARMState, cp15.ifar_ns), 1022 .resetvalue = 0 1023 }; 1024 define_one_arm_cp_reg(cpu, &ifar); 1025 } 1026 } 1027 1028 static void arm1136_r2_initfn(Object *obj) 1029 { 1030 ARMCPU *cpu = ARM_CPU(obj); 1031 /* What qemu calls "arm1136_r2" is actually the 1136 r0p2, ie an 1032 * older core than plain "arm1136". In particular this does not 1033 * have the v6K features. 1034 * These ID register values are correct for 1136 but may be wrong 1035 * for 1136_r2 (in particular r0p2 does not actually implement most 1036 * of the ID registers). 1037 */ 1038 1039 cpu->dtb_compatible = "arm,arm1136"; 1040 set_feature(&cpu->env, ARM_FEATURE_V6); 1041 set_feature(&cpu->env, ARM_FEATURE_VFP); 1042 set_feature(&cpu->env, ARM_FEATURE_DUMMY_C15_REGS); 1043 set_feature(&cpu->env, ARM_FEATURE_CACHE_DIRTY_REG); 1044 set_feature(&cpu->env, ARM_FEATURE_CACHE_BLOCK_OPS); 1045 cpu->midr = 0x4107b362; 1046 cpu->reset_fpsid = 0x410120b4; 1047 cpu->mvfr0 = 0x11111111; 1048 cpu->mvfr1 = 0x00000000; 1049 cpu->ctr = 0x1dd20d2; 1050 cpu->reset_sctlr = 0x00050078; 1051 cpu->id_pfr0 = 0x111; 1052 cpu->id_pfr1 = 0x1; 1053 cpu->id_dfr0 = 0x2; 1054 cpu->id_afr0 = 0x3; 1055 cpu->id_mmfr0 = 0x01130003; 1056 cpu->id_mmfr1 = 0x10030302; 1057 cpu->id_mmfr2 = 0x01222110; 1058 cpu->id_isar0 = 0x00140011; 1059 cpu->id_isar1 = 0x12002111; 1060 cpu->id_isar2 = 0x11231111; 1061 cpu->id_isar3 = 0x01102131; 1062 cpu->id_isar4 = 0x141; 1063 cpu->reset_auxcr = 7; 1064 } 1065 1066 static void arm1136_initfn(Object *obj) 1067 { 1068 ARMCPU *cpu = ARM_CPU(obj); 1069 1070 cpu->dtb_compatible = "arm,arm1136"; 1071 set_feature(&cpu->env, ARM_FEATURE_V6K); 1072 set_feature(&cpu->env, ARM_FEATURE_V6); 1073 set_feature(&cpu->env, ARM_FEATURE_VFP); 1074 set_feature(&cpu->env, ARM_FEATURE_DUMMY_C15_REGS); 1075 set_feature(&cpu->env, ARM_FEATURE_CACHE_DIRTY_REG); 1076 set_feature(&cpu->env, ARM_FEATURE_CACHE_BLOCK_OPS); 1077 cpu->midr = 0x4117b363; 1078 cpu->reset_fpsid = 0x410120b4; 1079 cpu->mvfr0 = 0x11111111; 1080 cpu->mvfr1 = 0x00000000; 1081 cpu->ctr = 0x1dd20d2; 1082 cpu->reset_sctlr = 0x00050078; 1083 cpu->id_pfr0 = 0x111; 1084 cpu->id_pfr1 = 0x1; 1085 cpu->id_dfr0 = 0x2; 1086 cpu->id_afr0 = 0x3; 1087 cpu->id_mmfr0 = 0x01130003; 1088 cpu->id_mmfr1 = 0x10030302; 1089 cpu->id_mmfr2 = 0x01222110; 1090 cpu->id_isar0 = 0x00140011; 1091 cpu->id_isar1 = 0x12002111; 1092 cpu->id_isar2 = 0x11231111; 1093 cpu->id_isar3 = 0x01102131; 1094 cpu->id_isar4 = 0x141; 1095 cpu->reset_auxcr = 7; 1096 } 1097 1098 static void arm1176_initfn(Object *obj) 1099 { 1100 ARMCPU *cpu = ARM_CPU(obj); 1101 1102 cpu->dtb_compatible = "arm,arm1176"; 1103 set_feature(&cpu->env, ARM_FEATURE_V6K); 1104 set_feature(&cpu->env, ARM_FEATURE_VFP); 1105 set_feature(&cpu->env, ARM_FEATURE_VAPA); 1106 set_feature(&cpu->env, ARM_FEATURE_DUMMY_C15_REGS); 1107 set_feature(&cpu->env, ARM_FEATURE_CACHE_DIRTY_REG); 1108 set_feature(&cpu->env, ARM_FEATURE_CACHE_BLOCK_OPS); 1109 set_feature(&cpu->env, ARM_FEATURE_EL3); 1110 cpu->midr = 0x410fb767; 1111 cpu->reset_fpsid = 0x410120b5; 1112 cpu->mvfr0 = 0x11111111; 1113 cpu->mvfr1 = 0x00000000; 1114 cpu->ctr = 0x1dd20d2; 1115 cpu->reset_sctlr = 0x00050078; 1116 cpu->id_pfr0 = 0x111; 1117 cpu->id_pfr1 = 0x11; 1118 cpu->id_dfr0 = 0x33; 1119 cpu->id_afr0 = 0; 1120 cpu->id_mmfr0 = 0x01130003; 1121 cpu->id_mmfr1 = 0x10030302; 1122 cpu->id_mmfr2 = 0x01222100; 1123 cpu->id_isar0 = 0x0140011; 1124 cpu->id_isar1 = 0x12002111; 1125 cpu->id_isar2 = 0x11231121; 1126 cpu->id_isar3 = 0x01102131; 1127 cpu->id_isar4 = 0x01141; 1128 cpu->reset_auxcr = 7; 1129 } 1130 1131 static void arm11mpcore_initfn(Object *obj) 1132 { 1133 ARMCPU *cpu = ARM_CPU(obj); 1134 1135 cpu->dtb_compatible = "arm,arm11mpcore"; 1136 set_feature(&cpu->env, ARM_FEATURE_V6K); 1137 set_feature(&cpu->env, ARM_FEATURE_VFP); 1138 set_feature(&cpu->env, ARM_FEATURE_VAPA); 1139 set_feature(&cpu->env, ARM_FEATURE_MPIDR); 1140 set_feature(&cpu->env, ARM_FEATURE_DUMMY_C15_REGS); 1141 cpu->midr = 0x410fb022; 1142 cpu->reset_fpsid = 0x410120b4; 1143 cpu->mvfr0 = 0x11111111; 1144 cpu->mvfr1 = 0x00000000; 1145 cpu->ctr = 0x1d192992; /* 32K icache 32K dcache */ 1146 cpu->id_pfr0 = 0x111; 1147 cpu->id_pfr1 = 0x1; 1148 cpu->id_dfr0 = 0; 1149 cpu->id_afr0 = 0x2; 1150 cpu->id_mmfr0 = 0x01100103; 1151 cpu->id_mmfr1 = 0x10020302; 1152 cpu->id_mmfr2 = 0x01222000; 1153 cpu->id_isar0 = 0x00100011; 1154 cpu->id_isar1 = 0x12002111; 1155 cpu->id_isar2 = 0x11221011; 1156 cpu->id_isar3 = 0x01102131; 1157 cpu->id_isar4 = 0x141; 1158 cpu->reset_auxcr = 1; 1159 } 1160 1161 static void cortex_m3_initfn(Object *obj) 1162 { 1163 ARMCPU *cpu = ARM_CPU(obj); 1164 set_feature(&cpu->env, ARM_FEATURE_V7); 1165 set_feature(&cpu->env, ARM_FEATURE_M); 1166 cpu->midr = 0x410fc231; 1167 cpu->pmsav7_dregion = 8; 1168 cpu->id_pfr0 = 0x00000030; 1169 cpu->id_pfr1 = 0x00000200; 1170 cpu->id_dfr0 = 0x00100000; 1171 cpu->id_afr0 = 0x00000000; 1172 cpu->id_mmfr0 = 0x00000030; 1173 cpu->id_mmfr1 = 0x00000000; 1174 cpu->id_mmfr2 = 0x00000000; 1175 cpu->id_mmfr3 = 0x00000000; 1176 cpu->id_isar0 = 0x01141110; 1177 cpu->id_isar1 = 0x02111000; 1178 cpu->id_isar2 = 0x21112231; 1179 cpu->id_isar3 = 0x01111110; 1180 cpu->id_isar4 = 0x01310102; 1181 cpu->id_isar5 = 0x00000000; 1182 } 1183 1184 static void cortex_m4_initfn(Object *obj) 1185 { 1186 ARMCPU *cpu = ARM_CPU(obj); 1187 1188 set_feature(&cpu->env, ARM_FEATURE_V7); 1189 set_feature(&cpu->env, ARM_FEATURE_M); 1190 set_feature(&cpu->env, ARM_FEATURE_THUMB_DSP); 1191 cpu->midr = 0x410fc240; /* r0p0 */ 1192 cpu->pmsav7_dregion = 8; 1193 cpu->id_pfr0 = 0x00000030; 1194 cpu->id_pfr1 = 0x00000200; 1195 cpu->id_dfr0 = 0x00100000; 1196 cpu->id_afr0 = 0x00000000; 1197 cpu->id_mmfr0 = 0x00000030; 1198 cpu->id_mmfr1 = 0x00000000; 1199 cpu->id_mmfr2 = 0x00000000; 1200 cpu->id_mmfr3 = 0x00000000; 1201 cpu->id_isar0 = 0x01141110; 1202 cpu->id_isar1 = 0x02111000; 1203 cpu->id_isar2 = 0x21112231; 1204 cpu->id_isar3 = 0x01111110; 1205 cpu->id_isar4 = 0x01310102; 1206 cpu->id_isar5 = 0x00000000; 1207 } 1208 1209 static void cortex_m33_initfn(Object *obj) 1210 { 1211 ARMCPU *cpu = ARM_CPU(obj); 1212 1213 set_feature(&cpu->env, ARM_FEATURE_V8); 1214 set_feature(&cpu->env, ARM_FEATURE_M); 1215 set_feature(&cpu->env, ARM_FEATURE_M_SECURITY); 1216 set_feature(&cpu->env, ARM_FEATURE_THUMB_DSP); 1217 cpu->midr = 0x410fd213; /* r0p3 */ 1218 cpu->pmsav7_dregion = 16; 1219 cpu->sau_sregion = 8; 1220 cpu->id_pfr0 = 0x00000030; 1221 cpu->id_pfr1 = 0x00000210; 1222 cpu->id_dfr0 = 0x00200000; 1223 cpu->id_afr0 = 0x00000000; 1224 cpu->id_mmfr0 = 0x00101F40; 1225 cpu->id_mmfr1 = 0x00000000; 1226 cpu->id_mmfr2 = 0x01000000; 1227 cpu->id_mmfr3 = 0x00000000; 1228 cpu->id_isar0 = 0x01101110; 1229 cpu->id_isar1 = 0x02212000; 1230 cpu->id_isar2 = 0x20232232; 1231 cpu->id_isar3 = 0x01111131; 1232 cpu->id_isar4 = 0x01310132; 1233 cpu->id_isar5 = 0x00000000; 1234 cpu->clidr = 0x00000000; 1235 cpu->ctr = 0x8000c000; 1236 } 1237 1238 static void arm_v7m_class_init(ObjectClass *oc, void *data) 1239 { 1240 CPUClass *cc = CPU_CLASS(oc); 1241 1242 #ifndef CONFIG_USER_ONLY 1243 cc->do_interrupt = arm_v7m_cpu_do_interrupt; 1244 #endif 1245 1246 cc->cpu_exec_interrupt = arm_v7m_cpu_exec_interrupt; 1247 } 1248 1249 static const ARMCPRegInfo cortexr5_cp_reginfo[] = { 1250 /* Dummy the TCM region regs for the moment */ 1251 { .name = "ATCM", .cp = 15, .opc1 = 0, .crn = 9, .crm = 1, .opc2 = 0, 1252 .access = PL1_RW, .type = ARM_CP_CONST }, 1253 { .name = "BTCM", .cp = 15, .opc1 = 0, .crn = 9, .crm = 1, .opc2 = 1, 1254 .access = PL1_RW, .type = ARM_CP_CONST }, 1255 { .name = "DCACHE_INVAL", .cp = 15, .opc1 = 0, .crn = 15, .crm = 5, 1256 .opc2 = 0, .access = PL1_W, .type = ARM_CP_NOP }, 1257 REGINFO_SENTINEL 1258 }; 1259 1260 static void cortex_r5_initfn(Object *obj) 1261 { 1262 ARMCPU *cpu = ARM_CPU(obj); 1263 1264 set_feature(&cpu->env, ARM_FEATURE_V7); 1265 set_feature(&cpu->env, ARM_FEATURE_THUMB_DIV); 1266 set_feature(&cpu->env, ARM_FEATURE_ARM_DIV); 1267 set_feature(&cpu->env, ARM_FEATURE_V7MP); 1268 set_feature(&cpu->env, ARM_FEATURE_PMSA); 1269 cpu->midr = 0x411fc153; /* r1p3 */ 1270 cpu->id_pfr0 = 0x0131; 1271 cpu->id_pfr1 = 0x001; 1272 cpu->id_dfr0 = 0x010400; 1273 cpu->id_afr0 = 0x0; 1274 cpu->id_mmfr0 = 0x0210030; 1275 cpu->id_mmfr1 = 0x00000000; 1276 cpu->id_mmfr2 = 0x01200000; 1277 cpu->id_mmfr3 = 0x0211; 1278 cpu->id_isar0 = 0x2101111; 1279 cpu->id_isar1 = 0x13112111; 1280 cpu->id_isar2 = 0x21232141; 1281 cpu->id_isar3 = 0x01112131; 1282 cpu->id_isar4 = 0x0010142; 1283 cpu->id_isar5 = 0x0; 1284 cpu->mp_is_up = true; 1285 cpu->pmsav7_dregion = 16; 1286 define_arm_cp_regs(cpu, cortexr5_cp_reginfo); 1287 } 1288 1289 static const ARMCPRegInfo cortexa8_cp_reginfo[] = { 1290 { .name = "L2LOCKDOWN", .cp = 15, .crn = 9, .crm = 0, .opc1 = 1, .opc2 = 0, 1291 .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0 }, 1292 { .name = "L2AUXCR", .cp = 15, .crn = 9, .crm = 0, .opc1 = 1, .opc2 = 2, 1293 .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0 }, 1294 REGINFO_SENTINEL 1295 }; 1296 1297 static void cortex_a8_initfn(Object *obj) 1298 { 1299 ARMCPU *cpu = ARM_CPU(obj); 1300 1301 cpu->dtb_compatible = "arm,cortex-a8"; 1302 set_feature(&cpu->env, ARM_FEATURE_V7); 1303 set_feature(&cpu->env, ARM_FEATURE_VFP3); 1304 set_feature(&cpu->env, ARM_FEATURE_NEON); 1305 set_feature(&cpu->env, ARM_FEATURE_THUMB2EE); 1306 set_feature(&cpu->env, ARM_FEATURE_DUMMY_C15_REGS); 1307 set_feature(&cpu->env, ARM_FEATURE_EL3); 1308 cpu->midr = 0x410fc080; 1309 cpu->reset_fpsid = 0x410330c0; 1310 cpu->mvfr0 = 0x11110222; 1311 cpu->mvfr1 = 0x00011111; 1312 cpu->ctr = 0x82048004; 1313 cpu->reset_sctlr = 0x00c50078; 1314 cpu->id_pfr0 = 0x1031; 1315 cpu->id_pfr1 = 0x11; 1316 cpu->id_dfr0 = 0x400; 1317 cpu->id_afr0 = 0; 1318 cpu->id_mmfr0 = 0x31100003; 1319 cpu->id_mmfr1 = 0x20000000; 1320 cpu->id_mmfr2 = 0x01202000; 1321 cpu->id_mmfr3 = 0x11; 1322 cpu->id_isar0 = 0x00101111; 1323 cpu->id_isar1 = 0x12112111; 1324 cpu->id_isar2 = 0x21232031; 1325 cpu->id_isar3 = 0x11112131; 1326 cpu->id_isar4 = 0x00111142; 1327 cpu->dbgdidr = 0x15141000; 1328 cpu->clidr = (1 << 27) | (2 << 24) | 3; 1329 cpu->ccsidr[0] = 0xe007e01a; /* 16k L1 dcache. */ 1330 cpu->ccsidr[1] = 0x2007e01a; /* 16k L1 icache. */ 1331 cpu->ccsidr[2] = 0xf0000000; /* No L2 icache. */ 1332 cpu->reset_auxcr = 2; 1333 define_arm_cp_regs(cpu, cortexa8_cp_reginfo); 1334 } 1335 1336 static const ARMCPRegInfo cortexa9_cp_reginfo[] = { 1337 /* power_control should be set to maximum latency. Again, 1338 * default to 0 and set by private hook 1339 */ 1340 { .name = "A9_PWRCTL", .cp = 15, .crn = 15, .crm = 0, .opc1 = 0, .opc2 = 0, 1341 .access = PL1_RW, .resetvalue = 0, 1342 .fieldoffset = offsetof(CPUARMState, cp15.c15_power_control) }, 1343 { .name = "A9_DIAG", .cp = 15, .crn = 15, .crm = 0, .opc1 = 0, .opc2 = 1, 1344 .access = PL1_RW, .resetvalue = 0, 1345 .fieldoffset = offsetof(CPUARMState, cp15.c15_diagnostic) }, 1346 { .name = "A9_PWRDIAG", .cp = 15, .crn = 15, .crm = 0, .opc1 = 0, .opc2 = 2, 1347 .access = PL1_RW, .resetvalue = 0, 1348 .fieldoffset = offsetof(CPUARMState, cp15.c15_power_diagnostic) }, 1349 { .name = "NEONBUSY", .cp = 15, .crn = 15, .crm = 1, .opc1 = 0, .opc2 = 0, 1350 .access = PL1_RW, .resetvalue = 0, .type = ARM_CP_CONST }, 1351 /* TLB lockdown control */ 1352 { .name = "TLB_LOCKR", .cp = 15, .crn = 15, .crm = 4, .opc1 = 5, .opc2 = 2, 1353 .access = PL1_W, .resetvalue = 0, .type = ARM_CP_NOP }, 1354 { .name = "TLB_LOCKW", .cp = 15, .crn = 15, .crm = 4, .opc1 = 5, .opc2 = 4, 1355 .access = PL1_W, .resetvalue = 0, .type = ARM_CP_NOP }, 1356 { .name = "TLB_VA", .cp = 15, .crn = 15, .crm = 5, .opc1 = 5, .opc2 = 2, 1357 .access = PL1_RW, .resetvalue = 0, .type = ARM_CP_CONST }, 1358 { .name = "TLB_PA", .cp = 15, .crn = 15, .crm = 6, .opc1 = 5, .opc2 = 2, 1359 .access = PL1_RW, .resetvalue = 0, .type = ARM_CP_CONST }, 1360 { .name = "TLB_ATTR", .cp = 15, .crn = 15, .crm = 7, .opc1 = 5, .opc2 = 2, 1361 .access = PL1_RW, .resetvalue = 0, .type = ARM_CP_CONST }, 1362 REGINFO_SENTINEL 1363 }; 1364 1365 static void cortex_a9_initfn(Object *obj) 1366 { 1367 ARMCPU *cpu = ARM_CPU(obj); 1368 1369 cpu->dtb_compatible = "arm,cortex-a9"; 1370 set_feature(&cpu->env, ARM_FEATURE_V7); 1371 set_feature(&cpu->env, ARM_FEATURE_VFP3); 1372 set_feature(&cpu->env, ARM_FEATURE_VFP_FP16); 1373 set_feature(&cpu->env, ARM_FEATURE_NEON); 1374 set_feature(&cpu->env, ARM_FEATURE_THUMB2EE); 1375 set_feature(&cpu->env, ARM_FEATURE_EL3); 1376 /* Note that A9 supports the MP extensions even for 1377 * A9UP and single-core A9MP (which are both different 1378 * and valid configurations; we don't model A9UP). 1379 */ 1380 set_feature(&cpu->env, ARM_FEATURE_V7MP); 1381 set_feature(&cpu->env, ARM_FEATURE_CBAR); 1382 cpu->midr = 0x410fc090; 1383 cpu->reset_fpsid = 0x41033090; 1384 cpu->mvfr0 = 0x11110222; 1385 cpu->mvfr1 = 0x01111111; 1386 cpu->ctr = 0x80038003; 1387 cpu->reset_sctlr = 0x00c50078; 1388 cpu->id_pfr0 = 0x1031; 1389 cpu->id_pfr1 = 0x11; 1390 cpu->id_dfr0 = 0x000; 1391 cpu->id_afr0 = 0; 1392 cpu->id_mmfr0 = 0x00100103; 1393 cpu->id_mmfr1 = 0x20000000; 1394 cpu->id_mmfr2 = 0x01230000; 1395 cpu->id_mmfr3 = 0x00002111; 1396 cpu->id_isar0 = 0x00101111; 1397 cpu->id_isar1 = 0x13112111; 1398 cpu->id_isar2 = 0x21232041; 1399 cpu->id_isar3 = 0x11112131; 1400 cpu->id_isar4 = 0x00111142; 1401 cpu->dbgdidr = 0x35141000; 1402 cpu->clidr = (1 << 27) | (1 << 24) | 3; 1403 cpu->ccsidr[0] = 0xe00fe019; /* 16k L1 dcache. */ 1404 cpu->ccsidr[1] = 0x200fe019; /* 16k L1 icache. */ 1405 define_arm_cp_regs(cpu, cortexa9_cp_reginfo); 1406 } 1407 1408 #ifndef CONFIG_USER_ONLY 1409 static uint64_t a15_l2ctlr_read(CPUARMState *env, const ARMCPRegInfo *ri) 1410 { 1411 /* Linux wants the number of processors from here. 1412 * Might as well set the interrupt-controller bit too. 1413 */ 1414 return ((smp_cpus - 1) << 24) | (1 << 23); 1415 } 1416 #endif 1417 1418 static const ARMCPRegInfo cortexa15_cp_reginfo[] = { 1419 #ifndef CONFIG_USER_ONLY 1420 { .name = "L2CTLR", .cp = 15, .crn = 9, .crm = 0, .opc1 = 1, .opc2 = 2, 1421 .access = PL1_RW, .resetvalue = 0, .readfn = a15_l2ctlr_read, 1422 .writefn = arm_cp_write_ignore, }, 1423 #endif 1424 { .name = "L2ECTLR", .cp = 15, .crn = 9, .crm = 0, .opc1 = 1, .opc2 = 3, 1425 .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0 }, 1426 REGINFO_SENTINEL 1427 }; 1428 1429 static void cortex_a7_initfn(Object *obj) 1430 { 1431 ARMCPU *cpu = ARM_CPU(obj); 1432 1433 cpu->dtb_compatible = "arm,cortex-a7"; 1434 set_feature(&cpu->env, ARM_FEATURE_V7); 1435 set_feature(&cpu->env, ARM_FEATURE_VFP4); 1436 set_feature(&cpu->env, ARM_FEATURE_NEON); 1437 set_feature(&cpu->env, ARM_FEATURE_THUMB2EE); 1438 set_feature(&cpu->env, ARM_FEATURE_ARM_DIV); 1439 set_feature(&cpu->env, ARM_FEATURE_GENERIC_TIMER); 1440 set_feature(&cpu->env, ARM_FEATURE_DUMMY_C15_REGS); 1441 set_feature(&cpu->env, ARM_FEATURE_CBAR_RO); 1442 set_feature(&cpu->env, ARM_FEATURE_LPAE); 1443 set_feature(&cpu->env, ARM_FEATURE_EL3); 1444 cpu->kvm_target = QEMU_KVM_ARM_TARGET_CORTEX_A7; 1445 cpu->midr = 0x410fc075; 1446 cpu->reset_fpsid = 0x41023075; 1447 cpu->mvfr0 = 0x10110222; 1448 cpu->mvfr1 = 0x11111111; 1449 cpu->ctr = 0x84448003; 1450 cpu->reset_sctlr = 0x00c50078; 1451 cpu->id_pfr0 = 0x00001131; 1452 cpu->id_pfr1 = 0x00011011; 1453 cpu->id_dfr0 = 0x02010555; 1454 cpu->pmceid0 = 0x00000000; 1455 cpu->pmceid1 = 0x00000000; 1456 cpu->id_afr0 = 0x00000000; 1457 cpu->id_mmfr0 = 0x10101105; 1458 cpu->id_mmfr1 = 0x40000000; 1459 cpu->id_mmfr2 = 0x01240000; 1460 cpu->id_mmfr3 = 0x02102211; 1461 cpu->id_isar0 = 0x01101110; 1462 cpu->id_isar1 = 0x13112111; 1463 cpu->id_isar2 = 0x21232041; 1464 cpu->id_isar3 = 0x11112131; 1465 cpu->id_isar4 = 0x10011142; 1466 cpu->dbgdidr = 0x3515f005; 1467 cpu->clidr = 0x0a200023; 1468 cpu->ccsidr[0] = 0x701fe00a; /* 32K L1 dcache */ 1469 cpu->ccsidr[1] = 0x201fe00a; /* 32K L1 icache */ 1470 cpu->ccsidr[2] = 0x711fe07a; /* 4096K L2 unified cache */ 1471 define_arm_cp_regs(cpu, cortexa15_cp_reginfo); /* Same as A15 */ 1472 } 1473 1474 static void cortex_a15_initfn(Object *obj) 1475 { 1476 ARMCPU *cpu = ARM_CPU(obj); 1477 1478 cpu->dtb_compatible = "arm,cortex-a15"; 1479 set_feature(&cpu->env, ARM_FEATURE_V7); 1480 set_feature(&cpu->env, ARM_FEATURE_VFP4); 1481 set_feature(&cpu->env, ARM_FEATURE_NEON); 1482 set_feature(&cpu->env, ARM_FEATURE_THUMB2EE); 1483 set_feature(&cpu->env, ARM_FEATURE_ARM_DIV); 1484 set_feature(&cpu->env, ARM_FEATURE_GENERIC_TIMER); 1485 set_feature(&cpu->env, ARM_FEATURE_DUMMY_C15_REGS); 1486 set_feature(&cpu->env, ARM_FEATURE_CBAR_RO); 1487 set_feature(&cpu->env, ARM_FEATURE_LPAE); 1488 set_feature(&cpu->env, ARM_FEATURE_EL3); 1489 cpu->kvm_target = QEMU_KVM_ARM_TARGET_CORTEX_A15; 1490 cpu->midr = 0x412fc0f1; 1491 cpu->reset_fpsid = 0x410430f0; 1492 cpu->mvfr0 = 0x10110222; 1493 cpu->mvfr1 = 0x11111111; 1494 cpu->ctr = 0x8444c004; 1495 cpu->reset_sctlr = 0x00c50078; 1496 cpu->id_pfr0 = 0x00001131; 1497 cpu->id_pfr1 = 0x00011011; 1498 cpu->id_dfr0 = 0x02010555; 1499 cpu->pmceid0 = 0x0000000; 1500 cpu->pmceid1 = 0x00000000; 1501 cpu->id_afr0 = 0x00000000; 1502 cpu->id_mmfr0 = 0x10201105; 1503 cpu->id_mmfr1 = 0x20000000; 1504 cpu->id_mmfr2 = 0x01240000; 1505 cpu->id_mmfr3 = 0x02102211; 1506 cpu->id_isar0 = 0x02101110; 1507 cpu->id_isar1 = 0x13112111; 1508 cpu->id_isar2 = 0x21232041; 1509 cpu->id_isar3 = 0x11112131; 1510 cpu->id_isar4 = 0x10011142; 1511 cpu->dbgdidr = 0x3515f021; 1512 cpu->clidr = 0x0a200023; 1513 cpu->ccsidr[0] = 0x701fe00a; /* 32K L1 dcache */ 1514 cpu->ccsidr[1] = 0x201fe00a; /* 32K L1 icache */ 1515 cpu->ccsidr[2] = 0x711fe07a; /* 4096K L2 unified cache */ 1516 define_arm_cp_regs(cpu, cortexa15_cp_reginfo); 1517 } 1518 1519 static void ti925t_initfn(Object *obj) 1520 { 1521 ARMCPU *cpu = ARM_CPU(obj); 1522 set_feature(&cpu->env, ARM_FEATURE_V4T); 1523 set_feature(&cpu->env, ARM_FEATURE_OMAPCP); 1524 cpu->midr = ARM_CPUID_TI925T; 1525 cpu->ctr = 0x5109149; 1526 cpu->reset_sctlr = 0x00000070; 1527 } 1528 1529 static void sa1100_initfn(Object *obj) 1530 { 1531 ARMCPU *cpu = ARM_CPU(obj); 1532 1533 cpu->dtb_compatible = "intel,sa1100"; 1534 set_feature(&cpu->env, ARM_FEATURE_STRONGARM); 1535 set_feature(&cpu->env, ARM_FEATURE_DUMMY_C15_REGS); 1536 cpu->midr = 0x4401A11B; 1537 cpu->reset_sctlr = 0x00000070; 1538 } 1539 1540 static void sa1110_initfn(Object *obj) 1541 { 1542 ARMCPU *cpu = ARM_CPU(obj); 1543 set_feature(&cpu->env, ARM_FEATURE_STRONGARM); 1544 set_feature(&cpu->env, ARM_FEATURE_DUMMY_C15_REGS); 1545 cpu->midr = 0x6901B119; 1546 cpu->reset_sctlr = 0x00000070; 1547 } 1548 1549 static void pxa250_initfn(Object *obj) 1550 { 1551 ARMCPU *cpu = ARM_CPU(obj); 1552 1553 cpu->dtb_compatible = "marvell,xscale"; 1554 set_feature(&cpu->env, ARM_FEATURE_V5); 1555 set_feature(&cpu->env, ARM_FEATURE_XSCALE); 1556 cpu->midr = 0x69052100; 1557 cpu->ctr = 0xd172172; 1558 cpu->reset_sctlr = 0x00000078; 1559 } 1560 1561 static void pxa255_initfn(Object *obj) 1562 { 1563 ARMCPU *cpu = ARM_CPU(obj); 1564 1565 cpu->dtb_compatible = "marvell,xscale"; 1566 set_feature(&cpu->env, ARM_FEATURE_V5); 1567 set_feature(&cpu->env, ARM_FEATURE_XSCALE); 1568 cpu->midr = 0x69052d00; 1569 cpu->ctr = 0xd172172; 1570 cpu->reset_sctlr = 0x00000078; 1571 } 1572 1573 static void pxa260_initfn(Object *obj) 1574 { 1575 ARMCPU *cpu = ARM_CPU(obj); 1576 1577 cpu->dtb_compatible = "marvell,xscale"; 1578 set_feature(&cpu->env, ARM_FEATURE_V5); 1579 set_feature(&cpu->env, ARM_FEATURE_XSCALE); 1580 cpu->midr = 0x69052903; 1581 cpu->ctr = 0xd172172; 1582 cpu->reset_sctlr = 0x00000078; 1583 } 1584 1585 static void pxa261_initfn(Object *obj) 1586 { 1587 ARMCPU *cpu = ARM_CPU(obj); 1588 1589 cpu->dtb_compatible = "marvell,xscale"; 1590 set_feature(&cpu->env, ARM_FEATURE_V5); 1591 set_feature(&cpu->env, ARM_FEATURE_XSCALE); 1592 cpu->midr = 0x69052d05; 1593 cpu->ctr = 0xd172172; 1594 cpu->reset_sctlr = 0x00000078; 1595 } 1596 1597 static void pxa262_initfn(Object *obj) 1598 { 1599 ARMCPU *cpu = ARM_CPU(obj); 1600 1601 cpu->dtb_compatible = "marvell,xscale"; 1602 set_feature(&cpu->env, ARM_FEATURE_V5); 1603 set_feature(&cpu->env, ARM_FEATURE_XSCALE); 1604 cpu->midr = 0x69052d06; 1605 cpu->ctr = 0xd172172; 1606 cpu->reset_sctlr = 0x00000078; 1607 } 1608 1609 static void pxa270a0_initfn(Object *obj) 1610 { 1611 ARMCPU *cpu = ARM_CPU(obj); 1612 1613 cpu->dtb_compatible = "marvell,xscale"; 1614 set_feature(&cpu->env, ARM_FEATURE_V5); 1615 set_feature(&cpu->env, ARM_FEATURE_XSCALE); 1616 set_feature(&cpu->env, ARM_FEATURE_IWMMXT); 1617 cpu->midr = 0x69054110; 1618 cpu->ctr = 0xd172172; 1619 cpu->reset_sctlr = 0x00000078; 1620 } 1621 1622 static void pxa270a1_initfn(Object *obj) 1623 { 1624 ARMCPU *cpu = ARM_CPU(obj); 1625 1626 cpu->dtb_compatible = "marvell,xscale"; 1627 set_feature(&cpu->env, ARM_FEATURE_V5); 1628 set_feature(&cpu->env, ARM_FEATURE_XSCALE); 1629 set_feature(&cpu->env, ARM_FEATURE_IWMMXT); 1630 cpu->midr = 0x69054111; 1631 cpu->ctr = 0xd172172; 1632 cpu->reset_sctlr = 0x00000078; 1633 } 1634 1635 static void pxa270b0_initfn(Object *obj) 1636 { 1637 ARMCPU *cpu = ARM_CPU(obj); 1638 1639 cpu->dtb_compatible = "marvell,xscale"; 1640 set_feature(&cpu->env, ARM_FEATURE_V5); 1641 set_feature(&cpu->env, ARM_FEATURE_XSCALE); 1642 set_feature(&cpu->env, ARM_FEATURE_IWMMXT); 1643 cpu->midr = 0x69054112; 1644 cpu->ctr = 0xd172172; 1645 cpu->reset_sctlr = 0x00000078; 1646 } 1647 1648 static void pxa270b1_initfn(Object *obj) 1649 { 1650 ARMCPU *cpu = ARM_CPU(obj); 1651 1652 cpu->dtb_compatible = "marvell,xscale"; 1653 set_feature(&cpu->env, ARM_FEATURE_V5); 1654 set_feature(&cpu->env, ARM_FEATURE_XSCALE); 1655 set_feature(&cpu->env, ARM_FEATURE_IWMMXT); 1656 cpu->midr = 0x69054113; 1657 cpu->ctr = 0xd172172; 1658 cpu->reset_sctlr = 0x00000078; 1659 } 1660 1661 static void pxa270c0_initfn(Object *obj) 1662 { 1663 ARMCPU *cpu = ARM_CPU(obj); 1664 1665 cpu->dtb_compatible = "marvell,xscale"; 1666 set_feature(&cpu->env, ARM_FEATURE_V5); 1667 set_feature(&cpu->env, ARM_FEATURE_XSCALE); 1668 set_feature(&cpu->env, ARM_FEATURE_IWMMXT); 1669 cpu->midr = 0x69054114; 1670 cpu->ctr = 0xd172172; 1671 cpu->reset_sctlr = 0x00000078; 1672 } 1673 1674 static void pxa270c5_initfn(Object *obj) 1675 { 1676 ARMCPU *cpu = ARM_CPU(obj); 1677 1678 cpu->dtb_compatible = "marvell,xscale"; 1679 set_feature(&cpu->env, ARM_FEATURE_V5); 1680 set_feature(&cpu->env, ARM_FEATURE_XSCALE); 1681 set_feature(&cpu->env, ARM_FEATURE_IWMMXT); 1682 cpu->midr = 0x69054117; 1683 cpu->ctr = 0xd172172; 1684 cpu->reset_sctlr = 0x00000078; 1685 } 1686 1687 #ifdef CONFIG_USER_ONLY 1688 static void arm_any_initfn(Object *obj) 1689 { 1690 ARMCPU *cpu = ARM_CPU(obj); 1691 set_feature(&cpu->env, ARM_FEATURE_V8); 1692 set_feature(&cpu->env, ARM_FEATURE_VFP4); 1693 set_feature(&cpu->env, ARM_FEATURE_NEON); 1694 set_feature(&cpu->env, ARM_FEATURE_THUMB2EE); 1695 set_feature(&cpu->env, ARM_FEATURE_V8_AES); 1696 set_feature(&cpu->env, ARM_FEATURE_V8_SHA1); 1697 set_feature(&cpu->env, ARM_FEATURE_V8_SHA256); 1698 set_feature(&cpu->env, ARM_FEATURE_V8_PMULL); 1699 set_feature(&cpu->env, ARM_FEATURE_CRC); 1700 set_feature(&cpu->env, ARM_FEATURE_V8_RDM); 1701 set_feature(&cpu->env, ARM_FEATURE_V8_FCMA); 1702 cpu->midr = 0xffffffff; 1703 } 1704 #endif 1705 1706 #endif /* !defined(CONFIG_USER_ONLY) || !defined(TARGET_AARCH64) */ 1707 1708 typedef struct ARMCPUInfo { 1709 const char *name; 1710 void (*initfn)(Object *obj); 1711 void (*class_init)(ObjectClass *oc, void *data); 1712 } ARMCPUInfo; 1713 1714 static const ARMCPUInfo arm_cpus[] = { 1715 #if !defined(CONFIG_USER_ONLY) || !defined(TARGET_AARCH64) 1716 { .name = "arm926", .initfn = arm926_initfn }, 1717 { .name = "arm946", .initfn = arm946_initfn }, 1718 { .name = "arm1026", .initfn = arm1026_initfn }, 1719 /* What QEMU calls "arm1136-r2" is actually the 1136 r0p2, i.e. an 1720 * older core than plain "arm1136". In particular this does not 1721 * have the v6K features. 1722 */ 1723 { .name = "arm1136-r2", .initfn = arm1136_r2_initfn }, 1724 { .name = "arm1136", .initfn = arm1136_initfn }, 1725 { .name = "arm1176", .initfn = arm1176_initfn }, 1726 { .name = "arm11mpcore", .initfn = arm11mpcore_initfn }, 1727 { .name = "cortex-m3", .initfn = cortex_m3_initfn, 1728 .class_init = arm_v7m_class_init }, 1729 { .name = "cortex-m4", .initfn = cortex_m4_initfn, 1730 .class_init = arm_v7m_class_init }, 1731 { .name = "cortex-m33", .initfn = cortex_m33_initfn, 1732 .class_init = arm_v7m_class_init }, 1733 { .name = "cortex-r5", .initfn = cortex_r5_initfn }, 1734 { .name = "cortex-a7", .initfn = cortex_a7_initfn }, 1735 { .name = "cortex-a8", .initfn = cortex_a8_initfn }, 1736 { .name = "cortex-a9", .initfn = cortex_a9_initfn }, 1737 { .name = "cortex-a15", .initfn = cortex_a15_initfn }, 1738 { .name = "ti925t", .initfn = ti925t_initfn }, 1739 { .name = "sa1100", .initfn = sa1100_initfn }, 1740 { .name = "sa1110", .initfn = sa1110_initfn }, 1741 { .name = "pxa250", .initfn = pxa250_initfn }, 1742 { .name = "pxa255", .initfn = pxa255_initfn }, 1743 { .name = "pxa260", .initfn = pxa260_initfn }, 1744 { .name = "pxa261", .initfn = pxa261_initfn }, 1745 { .name = "pxa262", .initfn = pxa262_initfn }, 1746 /* "pxa270" is an alias for "pxa270-a0" */ 1747 { .name = "pxa270", .initfn = pxa270a0_initfn }, 1748 { .name = "pxa270-a0", .initfn = pxa270a0_initfn }, 1749 { .name = "pxa270-a1", .initfn = pxa270a1_initfn }, 1750 { .name = "pxa270-b0", .initfn = pxa270b0_initfn }, 1751 { .name = "pxa270-b1", .initfn = pxa270b1_initfn }, 1752 { .name = "pxa270-c0", .initfn = pxa270c0_initfn }, 1753 { .name = "pxa270-c5", .initfn = pxa270c5_initfn }, 1754 #ifdef CONFIG_USER_ONLY 1755 { .name = "any", .initfn = arm_any_initfn }, 1756 #endif 1757 #endif 1758 { .name = NULL } 1759 }; 1760 1761 static Property arm_cpu_properties[] = { 1762 DEFINE_PROP_BOOL("start-powered-off", ARMCPU, start_powered_off, false), 1763 DEFINE_PROP_UINT32("psci-conduit", ARMCPU, psci_conduit, 0), 1764 DEFINE_PROP_UINT32("midr", ARMCPU, midr, 0), 1765 DEFINE_PROP_UINT64("mp-affinity", ARMCPU, 1766 mp_affinity, ARM64_AFFINITY_INVALID), 1767 DEFINE_PROP_INT32("node-id", ARMCPU, node_id, CPU_UNSET_NUMA_NODE_ID), 1768 DEFINE_PROP_END_OF_LIST() 1769 }; 1770 1771 #ifdef CONFIG_USER_ONLY 1772 static int arm_cpu_handle_mmu_fault(CPUState *cs, vaddr address, int size, 1773 int rw, int mmu_idx) 1774 { 1775 ARMCPU *cpu = ARM_CPU(cs); 1776 CPUARMState *env = &cpu->env; 1777 1778 env->exception.vaddress = address; 1779 if (rw == 2) { 1780 cs->exception_index = EXCP_PREFETCH_ABORT; 1781 } else { 1782 cs->exception_index = EXCP_DATA_ABORT; 1783 } 1784 return 1; 1785 } 1786 #endif 1787 1788 static gchar *arm_gdb_arch_name(CPUState *cs) 1789 { 1790 ARMCPU *cpu = ARM_CPU(cs); 1791 CPUARMState *env = &cpu->env; 1792 1793 if (arm_feature(env, ARM_FEATURE_IWMMXT)) { 1794 return g_strdup("iwmmxt"); 1795 } 1796 return g_strdup("arm"); 1797 } 1798 1799 static void arm_cpu_class_init(ObjectClass *oc, void *data) 1800 { 1801 ARMCPUClass *acc = ARM_CPU_CLASS(oc); 1802 CPUClass *cc = CPU_CLASS(acc); 1803 DeviceClass *dc = DEVICE_CLASS(oc); 1804 1805 device_class_set_parent_realize(dc, arm_cpu_realizefn, 1806 &acc->parent_realize); 1807 dc->props = arm_cpu_properties; 1808 1809 acc->parent_reset = cc->reset; 1810 cc->reset = arm_cpu_reset; 1811 1812 cc->class_by_name = arm_cpu_class_by_name; 1813 cc->has_work = arm_cpu_has_work; 1814 cc->cpu_exec_interrupt = arm_cpu_exec_interrupt; 1815 cc->dump_state = arm_cpu_dump_state; 1816 cc->set_pc = arm_cpu_set_pc; 1817 cc->gdb_read_register = arm_cpu_gdb_read_register; 1818 cc->gdb_write_register = arm_cpu_gdb_write_register; 1819 #ifdef CONFIG_USER_ONLY 1820 cc->handle_mmu_fault = arm_cpu_handle_mmu_fault; 1821 #else 1822 cc->do_interrupt = arm_cpu_do_interrupt; 1823 cc->do_unaligned_access = arm_cpu_do_unaligned_access; 1824 cc->do_transaction_failed = arm_cpu_do_transaction_failed; 1825 cc->get_phys_page_attrs_debug = arm_cpu_get_phys_page_attrs_debug; 1826 cc->asidx_from_attrs = arm_asidx_from_attrs; 1827 cc->vmsd = &vmstate_arm_cpu; 1828 cc->virtio_is_big_endian = arm_cpu_virtio_is_big_endian; 1829 cc->write_elf64_note = arm_cpu_write_elf64_note; 1830 cc->write_elf32_note = arm_cpu_write_elf32_note; 1831 #endif 1832 cc->gdb_num_core_regs = 26; 1833 cc->gdb_core_xml_file = "arm-core.xml"; 1834 cc->gdb_arch_name = arm_gdb_arch_name; 1835 cc->gdb_stop_before_watchpoint = true; 1836 cc->debug_excp_handler = arm_debug_excp_handler; 1837 cc->debug_check_watchpoint = arm_debug_check_watchpoint; 1838 #if !defined(CONFIG_USER_ONLY) 1839 cc->adjust_watchpoint_address = arm_adjust_watchpoint_address; 1840 #endif 1841 1842 cc->disas_set_info = arm_disas_set_info; 1843 #ifdef CONFIG_TCG 1844 cc->tcg_initialize = arm_translate_init; 1845 #endif 1846 } 1847 1848 static void cpu_register(const ARMCPUInfo *info) 1849 { 1850 TypeInfo type_info = { 1851 .parent = TYPE_ARM_CPU, 1852 .instance_size = sizeof(ARMCPU), 1853 .instance_init = info->initfn, 1854 .class_size = sizeof(ARMCPUClass), 1855 .class_init = info->class_init, 1856 }; 1857 1858 type_info.name = g_strdup_printf("%s-" TYPE_ARM_CPU, info->name); 1859 type_register(&type_info); 1860 g_free((void *)type_info.name); 1861 } 1862 1863 static const TypeInfo arm_cpu_type_info = { 1864 .name = TYPE_ARM_CPU, 1865 .parent = TYPE_CPU, 1866 .instance_size = sizeof(ARMCPU), 1867 .instance_init = arm_cpu_initfn, 1868 .instance_post_init = arm_cpu_post_init, 1869 .instance_finalize = arm_cpu_finalizefn, 1870 .abstract = true, 1871 .class_size = sizeof(ARMCPUClass), 1872 .class_init = arm_cpu_class_init, 1873 }; 1874 1875 static const TypeInfo idau_interface_type_info = { 1876 .name = TYPE_IDAU_INTERFACE, 1877 .parent = TYPE_INTERFACE, 1878 .class_size = sizeof(IDAUInterfaceClass), 1879 }; 1880 1881 static void arm_cpu_register_types(void) 1882 { 1883 const ARMCPUInfo *info = arm_cpus; 1884 1885 type_register_static(&arm_cpu_type_info); 1886 type_register_static(&idau_interface_type_info); 1887 1888 while (info->name) { 1889 cpu_register(info); 1890 info++; 1891 } 1892 } 1893 1894 type_init(arm_cpu_register_types) 1895