1 /* 2 * QEMU ARM CPU 3 * 4 * Copyright (c) 2012 SUSE LINUX Products GmbH 5 * 6 * This program is free software; you can redistribute it and/or 7 * modify it under the terms of the GNU General Public License 8 * as published by the Free Software Foundation; either version 2 9 * of the License, or (at your option) any later version. 10 * 11 * This program is distributed in the hope that it will be useful, 12 * but WITHOUT ANY WARRANTY; without even the implied warranty of 13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 14 * GNU General Public License for more details. 15 * 16 * You should have received a copy of the GNU General Public License 17 * along with this program; if not, see 18 * <http://www.gnu.org/licenses/gpl-2.0.html> 19 */ 20 21 #include "qemu/osdep.h" 22 #include "qemu/qemu-print.h" 23 #include "qemu/timer.h" 24 #include "qemu/log.h" 25 #include "exec/page-vary.h" 26 #include "target/arm/idau.h" 27 #include "qemu/module.h" 28 #include "qapi/error.h" 29 #include "qapi/visitor.h" 30 #include "cpu.h" 31 #ifdef CONFIG_TCG 32 #include "hw/core/tcg-cpu-ops.h" 33 #endif /* CONFIG_TCG */ 34 #include "internals.h" 35 #include "exec/exec-all.h" 36 #include "hw/qdev-properties.h" 37 #if !defined(CONFIG_USER_ONLY) 38 #include "hw/loader.h" 39 #include "hw/boards.h" 40 #endif 41 #include "sysemu/tcg.h" 42 #include "sysemu/hw_accel.h" 43 #include "kvm_arm.h" 44 #include "disas/capstone.h" 45 #include "fpu/softfloat.h" 46 #include "cpregs.h" 47 48 static void arm_cpu_set_pc(CPUState *cs, vaddr value) 49 { 50 ARMCPU *cpu = ARM_CPU(cs); 51 CPUARMState *env = &cpu->env; 52 53 if (is_a64(env)) { 54 env->pc = value; 55 env->thumb = false; 56 } else { 57 env->regs[15] = value & ~1; 58 env->thumb = value & 1; 59 } 60 } 61 62 #ifdef CONFIG_TCG 63 void arm_cpu_synchronize_from_tb(CPUState *cs, 64 const TranslationBlock *tb) 65 { 66 ARMCPU *cpu = ARM_CPU(cs); 67 CPUARMState *env = &cpu->env; 68 69 /* 70 * It's OK to look at env for the current mode here, because it's 71 * never possible for an AArch64 TB to chain to an AArch32 TB. 72 */ 73 if (is_a64(env)) { 74 env->pc = tb->pc; 75 } else { 76 env->regs[15] = tb->pc; 77 } 78 } 79 #endif /* CONFIG_TCG */ 80 81 static bool arm_cpu_has_work(CPUState *cs) 82 { 83 ARMCPU *cpu = ARM_CPU(cs); 84 85 return (cpu->power_state != PSCI_OFF) 86 && cs->interrupt_request & 87 (CPU_INTERRUPT_FIQ | CPU_INTERRUPT_HARD 88 | CPU_INTERRUPT_VFIQ | CPU_INTERRUPT_VIRQ | CPU_INTERRUPT_VSERR 89 | CPU_INTERRUPT_EXITTB); 90 } 91 92 void arm_register_pre_el_change_hook(ARMCPU *cpu, ARMELChangeHookFn *hook, 93 void *opaque) 94 { 95 ARMELChangeHook *entry = g_new0(ARMELChangeHook, 1); 96 97 entry->hook = hook; 98 entry->opaque = opaque; 99 100 QLIST_INSERT_HEAD(&cpu->pre_el_change_hooks, entry, node); 101 } 102 103 void arm_register_el_change_hook(ARMCPU *cpu, ARMELChangeHookFn *hook, 104 void *opaque) 105 { 106 ARMELChangeHook *entry = g_new0(ARMELChangeHook, 1); 107 108 entry->hook = hook; 109 entry->opaque = opaque; 110 111 QLIST_INSERT_HEAD(&cpu->el_change_hooks, entry, node); 112 } 113 114 static void cp_reg_reset(gpointer key, gpointer value, gpointer opaque) 115 { 116 /* Reset a single ARMCPRegInfo register */ 117 ARMCPRegInfo *ri = value; 118 ARMCPU *cpu = opaque; 119 120 if (ri->type & (ARM_CP_SPECIAL_MASK | ARM_CP_ALIAS)) { 121 return; 122 } 123 124 if (ri->resetfn) { 125 ri->resetfn(&cpu->env, ri); 126 return; 127 } 128 129 /* A zero offset is never possible as it would be regs[0] 130 * so we use it to indicate that reset is being handled elsewhere. 131 * This is basically only used for fields in non-core coprocessors 132 * (like the pxa2xx ones). 133 */ 134 if (!ri->fieldoffset) { 135 return; 136 } 137 138 if (cpreg_field_is_64bit(ri)) { 139 CPREG_FIELD64(&cpu->env, ri) = ri->resetvalue; 140 } else { 141 CPREG_FIELD32(&cpu->env, ri) = ri->resetvalue; 142 } 143 } 144 145 static void cp_reg_check_reset(gpointer key, gpointer value, gpointer opaque) 146 { 147 /* Purely an assertion check: we've already done reset once, 148 * so now check that running the reset for the cpreg doesn't 149 * change its value. This traps bugs where two different cpregs 150 * both try to reset the same state field but to different values. 151 */ 152 ARMCPRegInfo *ri = value; 153 ARMCPU *cpu = opaque; 154 uint64_t oldvalue, newvalue; 155 156 if (ri->type & (ARM_CP_SPECIAL_MASK | ARM_CP_ALIAS | ARM_CP_NO_RAW)) { 157 return; 158 } 159 160 oldvalue = read_raw_cp_reg(&cpu->env, ri); 161 cp_reg_reset(key, value, opaque); 162 newvalue = read_raw_cp_reg(&cpu->env, ri); 163 assert(oldvalue == newvalue); 164 } 165 166 static void arm_cpu_reset(DeviceState *dev) 167 { 168 CPUState *s = CPU(dev); 169 ARMCPU *cpu = ARM_CPU(s); 170 ARMCPUClass *acc = ARM_CPU_GET_CLASS(cpu); 171 CPUARMState *env = &cpu->env; 172 173 acc->parent_reset(dev); 174 175 memset(env, 0, offsetof(CPUARMState, end_reset_fields)); 176 177 g_hash_table_foreach(cpu->cp_regs, cp_reg_reset, cpu); 178 g_hash_table_foreach(cpu->cp_regs, cp_reg_check_reset, cpu); 179 180 env->vfp.xregs[ARM_VFP_FPSID] = cpu->reset_fpsid; 181 env->vfp.xregs[ARM_VFP_MVFR0] = cpu->isar.mvfr0; 182 env->vfp.xregs[ARM_VFP_MVFR1] = cpu->isar.mvfr1; 183 env->vfp.xregs[ARM_VFP_MVFR2] = cpu->isar.mvfr2; 184 185 cpu->power_state = s->start_powered_off ? PSCI_OFF : PSCI_ON; 186 187 if (arm_feature(env, ARM_FEATURE_IWMMXT)) { 188 env->iwmmxt.cregs[ARM_IWMMXT_wCID] = 0x69051000 | 'Q'; 189 } 190 191 if (arm_feature(env, ARM_FEATURE_AARCH64)) { 192 /* 64 bit CPUs always start in 64 bit mode */ 193 env->aarch64 = true; 194 #if defined(CONFIG_USER_ONLY) 195 env->pstate = PSTATE_MODE_EL0t; 196 /* Userspace expects access to DC ZVA, CTL_EL0 and the cache ops */ 197 env->cp15.sctlr_el[1] |= SCTLR_UCT | SCTLR_UCI | SCTLR_DZE; 198 /* Enable all PAC keys. */ 199 env->cp15.sctlr_el[1] |= (SCTLR_EnIA | SCTLR_EnIB | 200 SCTLR_EnDA | SCTLR_EnDB); 201 /* Trap on btype=3 for PACIxSP. */ 202 env->cp15.sctlr_el[1] |= SCTLR_BT0; 203 /* and to the FP/Neon instructions */ 204 env->cp15.cpacr_el1 = FIELD_DP64(env->cp15.cpacr_el1, 205 CPACR_EL1, FPEN, 3); 206 /* and to the SVE instructions */ 207 env->cp15.cpacr_el1 = FIELD_DP64(env->cp15.cpacr_el1, 208 CPACR_EL1, ZEN, 3); 209 /* with reasonable vector length */ 210 if (cpu_isar_feature(aa64_sve, cpu)) { 211 env->vfp.zcr_el[1] = 212 aarch64_sve_zcr_get_valid_len(cpu, cpu->sve_default_vq - 1); 213 } 214 /* 215 * Enable 48-bit address space (TODO: take reserved_va into account). 216 * Enable TBI0 but not TBI1. 217 * Note that this must match useronly_clean_ptr. 218 */ 219 env->cp15.tcr_el[1].raw_tcr = 5 | (1ULL << 37); 220 221 /* Enable MTE */ 222 if (cpu_isar_feature(aa64_mte, cpu)) { 223 /* Enable tag access, but leave TCF0 as No Effect (0). */ 224 env->cp15.sctlr_el[1] |= SCTLR_ATA0; 225 /* 226 * Exclude all tags, so that tag 0 is always used. 227 * This corresponds to Linux current->thread.gcr_incl = 0. 228 * 229 * Set RRND, so that helper_irg() will generate a seed later. 230 * Here in cpu_reset(), the crypto subsystem has not yet been 231 * initialized. 232 */ 233 env->cp15.gcr_el1 = 0x1ffff; 234 } 235 /* 236 * Disable access to SCXTNUM_EL0 from CSV2_1p2. 237 * This is not yet exposed from the Linux kernel in any way. 238 */ 239 env->cp15.sctlr_el[1] |= SCTLR_TSCXT; 240 #else 241 /* Reset into the highest available EL */ 242 if (arm_feature(env, ARM_FEATURE_EL3)) { 243 env->pstate = PSTATE_MODE_EL3h; 244 } else if (arm_feature(env, ARM_FEATURE_EL2)) { 245 env->pstate = PSTATE_MODE_EL2h; 246 } else { 247 env->pstate = PSTATE_MODE_EL1h; 248 } 249 250 /* Sample rvbar at reset. */ 251 env->cp15.rvbar = cpu->rvbar_prop; 252 env->pc = env->cp15.rvbar; 253 #endif 254 } else { 255 #if defined(CONFIG_USER_ONLY) 256 /* Userspace expects access to cp10 and cp11 for FP/Neon */ 257 env->cp15.cpacr_el1 = FIELD_DP64(env->cp15.cpacr_el1, 258 CPACR, CP10, 3); 259 env->cp15.cpacr_el1 = FIELD_DP64(env->cp15.cpacr_el1, 260 CPACR, CP11, 3); 261 #endif 262 } 263 264 #if defined(CONFIG_USER_ONLY) 265 env->uncached_cpsr = ARM_CPU_MODE_USR; 266 /* For user mode we must enable access to coprocessors */ 267 env->vfp.xregs[ARM_VFP_FPEXC] = 1 << 30; 268 if (arm_feature(env, ARM_FEATURE_IWMMXT)) { 269 env->cp15.c15_cpar = 3; 270 } else if (arm_feature(env, ARM_FEATURE_XSCALE)) { 271 env->cp15.c15_cpar = 1; 272 } 273 #else 274 275 /* 276 * If the highest available EL is EL2, AArch32 will start in Hyp 277 * mode; otherwise it starts in SVC. Note that if we start in 278 * AArch64 then these values in the uncached_cpsr will be ignored. 279 */ 280 if (arm_feature(env, ARM_FEATURE_EL2) && 281 !arm_feature(env, ARM_FEATURE_EL3)) { 282 env->uncached_cpsr = ARM_CPU_MODE_HYP; 283 } else { 284 env->uncached_cpsr = ARM_CPU_MODE_SVC; 285 } 286 env->daif = PSTATE_D | PSTATE_A | PSTATE_I | PSTATE_F; 287 288 /* AArch32 has a hard highvec setting of 0xFFFF0000. If we are currently 289 * executing as AArch32 then check if highvecs are enabled and 290 * adjust the PC accordingly. 291 */ 292 if (A32_BANKED_CURRENT_REG_GET(env, sctlr) & SCTLR_V) { 293 env->regs[15] = 0xFFFF0000; 294 } 295 296 env->vfp.xregs[ARM_VFP_FPEXC] = 0; 297 #endif 298 299 if (arm_feature(env, ARM_FEATURE_M)) { 300 #ifndef CONFIG_USER_ONLY 301 uint32_t initial_msp; /* Loaded from 0x0 */ 302 uint32_t initial_pc; /* Loaded from 0x4 */ 303 uint8_t *rom; 304 uint32_t vecbase; 305 #endif 306 307 if (cpu_isar_feature(aa32_lob, cpu)) { 308 /* 309 * LTPSIZE is constant 4 if MVE not implemented, and resets 310 * to an UNKNOWN value if MVE is implemented. We choose to 311 * always reset to 4. 312 */ 313 env->v7m.ltpsize = 4; 314 /* The LTPSIZE field in FPDSCR is constant and reads as 4. */ 315 env->v7m.fpdscr[M_REG_NS] = 4 << FPCR_LTPSIZE_SHIFT; 316 env->v7m.fpdscr[M_REG_S] = 4 << FPCR_LTPSIZE_SHIFT; 317 } 318 319 if (arm_feature(env, ARM_FEATURE_M_SECURITY)) { 320 env->v7m.secure = true; 321 } else { 322 /* This bit resets to 0 if security is supported, but 1 if 323 * it is not. The bit is not present in v7M, but we set it 324 * here so we can avoid having to make checks on it conditional 325 * on ARM_FEATURE_V8 (we don't let the guest see the bit). 326 */ 327 env->v7m.aircr = R_V7M_AIRCR_BFHFNMINS_MASK; 328 /* 329 * Set NSACR to indicate "NS access permitted to everything"; 330 * this avoids having to have all the tests of it being 331 * conditional on ARM_FEATURE_M_SECURITY. Note also that from 332 * v8.1M the guest-visible value of NSACR in a CPU without the 333 * Security Extension is 0xcff. 334 */ 335 env->v7m.nsacr = 0xcff; 336 } 337 338 /* In v7M the reset value of this bit is IMPDEF, but ARM recommends 339 * that it resets to 1, so QEMU always does that rather than making 340 * it dependent on CPU model. In v8M it is RES1. 341 */ 342 env->v7m.ccr[M_REG_NS] = R_V7M_CCR_STKALIGN_MASK; 343 env->v7m.ccr[M_REG_S] = R_V7M_CCR_STKALIGN_MASK; 344 if (arm_feature(env, ARM_FEATURE_V8)) { 345 /* in v8M the NONBASETHRDENA bit [0] is RES1 */ 346 env->v7m.ccr[M_REG_NS] |= R_V7M_CCR_NONBASETHRDENA_MASK; 347 env->v7m.ccr[M_REG_S] |= R_V7M_CCR_NONBASETHRDENA_MASK; 348 } 349 if (!arm_feature(env, ARM_FEATURE_M_MAIN)) { 350 env->v7m.ccr[M_REG_NS] |= R_V7M_CCR_UNALIGN_TRP_MASK; 351 env->v7m.ccr[M_REG_S] |= R_V7M_CCR_UNALIGN_TRP_MASK; 352 } 353 354 if (cpu_isar_feature(aa32_vfp_simd, cpu)) { 355 env->v7m.fpccr[M_REG_NS] = R_V7M_FPCCR_ASPEN_MASK; 356 env->v7m.fpccr[M_REG_S] = R_V7M_FPCCR_ASPEN_MASK | 357 R_V7M_FPCCR_LSPEN_MASK | R_V7M_FPCCR_S_MASK; 358 } 359 360 #ifndef CONFIG_USER_ONLY 361 /* Unlike A/R profile, M profile defines the reset LR value */ 362 env->regs[14] = 0xffffffff; 363 364 env->v7m.vecbase[M_REG_S] = cpu->init_svtor & 0xffffff80; 365 env->v7m.vecbase[M_REG_NS] = cpu->init_nsvtor & 0xffffff80; 366 367 /* Load the initial SP and PC from offset 0 and 4 in the vector table */ 368 vecbase = env->v7m.vecbase[env->v7m.secure]; 369 rom = rom_ptr_for_as(s->as, vecbase, 8); 370 if (rom) { 371 /* Address zero is covered by ROM which hasn't yet been 372 * copied into physical memory. 373 */ 374 initial_msp = ldl_p(rom); 375 initial_pc = ldl_p(rom + 4); 376 } else { 377 /* Address zero not covered by a ROM blob, or the ROM blob 378 * is in non-modifiable memory and this is a second reset after 379 * it got copied into memory. In the latter case, rom_ptr 380 * will return a NULL pointer and we should use ldl_phys instead. 381 */ 382 initial_msp = ldl_phys(s->as, vecbase); 383 initial_pc = ldl_phys(s->as, vecbase + 4); 384 } 385 386 qemu_log_mask(CPU_LOG_INT, 387 "Loaded reset SP 0x%x PC 0x%x from vector table\n", 388 initial_msp, initial_pc); 389 390 env->regs[13] = initial_msp & 0xFFFFFFFC; 391 env->regs[15] = initial_pc & ~1; 392 env->thumb = initial_pc & 1; 393 #else 394 /* 395 * For user mode we run non-secure and with access to the FPU. 396 * The FPU context is active (ie does not need further setup) 397 * and is owned by non-secure. 398 */ 399 env->v7m.secure = false; 400 env->v7m.nsacr = 0xcff; 401 env->v7m.cpacr[M_REG_NS] = 0xf0ffff; 402 env->v7m.fpccr[M_REG_S] &= 403 ~(R_V7M_FPCCR_LSPEN_MASK | R_V7M_FPCCR_S_MASK); 404 env->v7m.control[M_REG_S] |= R_V7M_CONTROL_FPCA_MASK; 405 #endif 406 } 407 408 /* M profile requires that reset clears the exclusive monitor; 409 * A profile does not, but clearing it makes more sense than having it 410 * set with an exclusive access on address zero. 411 */ 412 arm_clear_exclusive(env); 413 414 if (arm_feature(env, ARM_FEATURE_PMSA)) { 415 if (cpu->pmsav7_dregion > 0) { 416 if (arm_feature(env, ARM_FEATURE_V8)) { 417 memset(env->pmsav8.rbar[M_REG_NS], 0, 418 sizeof(*env->pmsav8.rbar[M_REG_NS]) 419 * cpu->pmsav7_dregion); 420 memset(env->pmsav8.rlar[M_REG_NS], 0, 421 sizeof(*env->pmsav8.rlar[M_REG_NS]) 422 * cpu->pmsav7_dregion); 423 if (arm_feature(env, ARM_FEATURE_M_SECURITY)) { 424 memset(env->pmsav8.rbar[M_REG_S], 0, 425 sizeof(*env->pmsav8.rbar[M_REG_S]) 426 * cpu->pmsav7_dregion); 427 memset(env->pmsav8.rlar[M_REG_S], 0, 428 sizeof(*env->pmsav8.rlar[M_REG_S]) 429 * cpu->pmsav7_dregion); 430 } 431 } else if (arm_feature(env, ARM_FEATURE_V7)) { 432 memset(env->pmsav7.drbar, 0, 433 sizeof(*env->pmsav7.drbar) * cpu->pmsav7_dregion); 434 memset(env->pmsav7.drsr, 0, 435 sizeof(*env->pmsav7.drsr) * cpu->pmsav7_dregion); 436 memset(env->pmsav7.dracr, 0, 437 sizeof(*env->pmsav7.dracr) * cpu->pmsav7_dregion); 438 } 439 } 440 env->pmsav7.rnr[M_REG_NS] = 0; 441 env->pmsav7.rnr[M_REG_S] = 0; 442 env->pmsav8.mair0[M_REG_NS] = 0; 443 env->pmsav8.mair0[M_REG_S] = 0; 444 env->pmsav8.mair1[M_REG_NS] = 0; 445 env->pmsav8.mair1[M_REG_S] = 0; 446 } 447 448 if (arm_feature(env, ARM_FEATURE_M_SECURITY)) { 449 if (cpu->sau_sregion > 0) { 450 memset(env->sau.rbar, 0, sizeof(*env->sau.rbar) * cpu->sau_sregion); 451 memset(env->sau.rlar, 0, sizeof(*env->sau.rlar) * cpu->sau_sregion); 452 } 453 env->sau.rnr = 0; 454 /* SAU_CTRL reset value is IMPDEF; we choose 0, which is what 455 * the Cortex-M33 does. 456 */ 457 env->sau.ctrl = 0; 458 } 459 460 set_flush_to_zero(1, &env->vfp.standard_fp_status); 461 set_flush_inputs_to_zero(1, &env->vfp.standard_fp_status); 462 set_default_nan_mode(1, &env->vfp.standard_fp_status); 463 set_default_nan_mode(1, &env->vfp.standard_fp_status_f16); 464 set_float_detect_tininess(float_tininess_before_rounding, 465 &env->vfp.fp_status); 466 set_float_detect_tininess(float_tininess_before_rounding, 467 &env->vfp.standard_fp_status); 468 set_float_detect_tininess(float_tininess_before_rounding, 469 &env->vfp.fp_status_f16); 470 set_float_detect_tininess(float_tininess_before_rounding, 471 &env->vfp.standard_fp_status_f16); 472 #ifndef CONFIG_USER_ONLY 473 if (kvm_enabled()) { 474 kvm_arm_reset_vcpu(cpu); 475 } 476 #endif 477 478 hw_breakpoint_update_all(cpu); 479 hw_watchpoint_update_all(cpu); 480 arm_rebuild_hflags(env); 481 } 482 483 #ifndef CONFIG_USER_ONLY 484 485 static inline bool arm_excp_unmasked(CPUState *cs, unsigned int excp_idx, 486 unsigned int target_el, 487 unsigned int cur_el, bool secure, 488 uint64_t hcr_el2) 489 { 490 CPUARMState *env = cs->env_ptr; 491 bool pstate_unmasked; 492 bool unmasked = false; 493 494 /* 495 * Don't take exceptions if they target a lower EL. 496 * This check should catch any exceptions that would not be taken 497 * but left pending. 498 */ 499 if (cur_el > target_el) { 500 return false; 501 } 502 503 switch (excp_idx) { 504 case EXCP_FIQ: 505 pstate_unmasked = !(env->daif & PSTATE_F); 506 break; 507 508 case EXCP_IRQ: 509 pstate_unmasked = !(env->daif & PSTATE_I); 510 break; 511 512 case EXCP_VFIQ: 513 if (!(hcr_el2 & HCR_FMO) || (hcr_el2 & HCR_TGE)) { 514 /* VFIQs are only taken when hypervized. */ 515 return false; 516 } 517 return !(env->daif & PSTATE_F); 518 case EXCP_VIRQ: 519 if (!(hcr_el2 & HCR_IMO) || (hcr_el2 & HCR_TGE)) { 520 /* VIRQs are only taken when hypervized. */ 521 return false; 522 } 523 return !(env->daif & PSTATE_I); 524 case EXCP_VSERR: 525 if (!(hcr_el2 & HCR_AMO) || (hcr_el2 & HCR_TGE)) { 526 /* VIRQs are only taken when hypervized. */ 527 return false; 528 } 529 return !(env->daif & PSTATE_A); 530 default: 531 g_assert_not_reached(); 532 } 533 534 /* 535 * Use the target EL, current execution state and SCR/HCR settings to 536 * determine whether the corresponding CPSR bit is used to mask the 537 * interrupt. 538 */ 539 if ((target_el > cur_el) && (target_el != 1)) { 540 /* Exceptions targeting a higher EL may not be maskable */ 541 if (arm_feature(env, ARM_FEATURE_AARCH64)) { 542 /* 543 * 64-bit masking rules are simple: exceptions to EL3 544 * can't be masked, and exceptions to EL2 can only be 545 * masked from Secure state. The HCR and SCR settings 546 * don't affect the masking logic, only the interrupt routing. 547 */ 548 if (target_el == 3 || !secure || (env->cp15.scr_el3 & SCR_EEL2)) { 549 unmasked = true; 550 } 551 } else { 552 /* 553 * The old 32-bit-only environment has a more complicated 554 * masking setup. HCR and SCR bits not only affect interrupt 555 * routing but also change the behaviour of masking. 556 */ 557 bool hcr, scr; 558 559 switch (excp_idx) { 560 case EXCP_FIQ: 561 /* 562 * If FIQs are routed to EL3 or EL2 then there are cases where 563 * we override the CPSR.F in determining if the exception is 564 * masked or not. If neither of these are set then we fall back 565 * to the CPSR.F setting otherwise we further assess the state 566 * below. 567 */ 568 hcr = hcr_el2 & HCR_FMO; 569 scr = (env->cp15.scr_el3 & SCR_FIQ); 570 571 /* 572 * When EL3 is 32-bit, the SCR.FW bit controls whether the 573 * CPSR.F bit masks FIQ interrupts when taken in non-secure 574 * state. If SCR.FW is set then FIQs can be masked by CPSR.F 575 * when non-secure but only when FIQs are only routed to EL3. 576 */ 577 scr = scr && !((env->cp15.scr_el3 & SCR_FW) && !hcr); 578 break; 579 case EXCP_IRQ: 580 /* 581 * When EL3 execution state is 32-bit, if HCR.IMO is set then 582 * we may override the CPSR.I masking when in non-secure state. 583 * The SCR.IRQ setting has already been taken into consideration 584 * when setting the target EL, so it does not have a further 585 * affect here. 586 */ 587 hcr = hcr_el2 & HCR_IMO; 588 scr = false; 589 break; 590 default: 591 g_assert_not_reached(); 592 } 593 594 if ((scr || hcr) && !secure) { 595 unmasked = true; 596 } 597 } 598 } 599 600 /* 601 * The PSTATE bits only mask the interrupt if we have not overriden the 602 * ability above. 603 */ 604 return unmasked || pstate_unmasked; 605 } 606 607 static bool arm_cpu_exec_interrupt(CPUState *cs, int interrupt_request) 608 { 609 CPUClass *cc = CPU_GET_CLASS(cs); 610 CPUARMState *env = cs->env_ptr; 611 uint32_t cur_el = arm_current_el(env); 612 bool secure = arm_is_secure(env); 613 uint64_t hcr_el2 = arm_hcr_el2_eff(env); 614 uint32_t target_el; 615 uint32_t excp_idx; 616 617 /* The prioritization of interrupts is IMPLEMENTATION DEFINED. */ 618 619 if (interrupt_request & CPU_INTERRUPT_FIQ) { 620 excp_idx = EXCP_FIQ; 621 target_el = arm_phys_excp_target_el(cs, excp_idx, cur_el, secure); 622 if (arm_excp_unmasked(cs, excp_idx, target_el, 623 cur_el, secure, hcr_el2)) { 624 goto found; 625 } 626 } 627 if (interrupt_request & CPU_INTERRUPT_HARD) { 628 excp_idx = EXCP_IRQ; 629 target_el = arm_phys_excp_target_el(cs, excp_idx, cur_el, secure); 630 if (arm_excp_unmasked(cs, excp_idx, target_el, 631 cur_el, secure, hcr_el2)) { 632 goto found; 633 } 634 } 635 if (interrupt_request & CPU_INTERRUPT_VIRQ) { 636 excp_idx = EXCP_VIRQ; 637 target_el = 1; 638 if (arm_excp_unmasked(cs, excp_idx, target_el, 639 cur_el, secure, hcr_el2)) { 640 goto found; 641 } 642 } 643 if (interrupt_request & CPU_INTERRUPT_VFIQ) { 644 excp_idx = EXCP_VFIQ; 645 target_el = 1; 646 if (arm_excp_unmasked(cs, excp_idx, target_el, 647 cur_el, secure, hcr_el2)) { 648 goto found; 649 } 650 } 651 if (interrupt_request & CPU_INTERRUPT_VSERR) { 652 excp_idx = EXCP_VSERR; 653 target_el = 1; 654 if (arm_excp_unmasked(cs, excp_idx, target_el, 655 cur_el, secure, hcr_el2)) { 656 /* Taking a virtual abort clears HCR_EL2.VSE */ 657 env->cp15.hcr_el2 &= ~HCR_VSE; 658 cpu_reset_interrupt(cs, CPU_INTERRUPT_VSERR); 659 goto found; 660 } 661 } 662 return false; 663 664 found: 665 cs->exception_index = excp_idx; 666 env->exception.target_el = target_el; 667 cc->tcg_ops->do_interrupt(cs); 668 return true; 669 } 670 #endif /* !CONFIG_USER_ONLY */ 671 672 void arm_cpu_update_virq(ARMCPU *cpu) 673 { 674 /* 675 * Update the interrupt level for VIRQ, which is the logical OR of 676 * the HCR_EL2.VI bit and the input line level from the GIC. 677 */ 678 CPUARMState *env = &cpu->env; 679 CPUState *cs = CPU(cpu); 680 681 bool new_state = (env->cp15.hcr_el2 & HCR_VI) || 682 (env->irq_line_state & CPU_INTERRUPT_VIRQ); 683 684 if (new_state != ((cs->interrupt_request & CPU_INTERRUPT_VIRQ) != 0)) { 685 if (new_state) { 686 cpu_interrupt(cs, CPU_INTERRUPT_VIRQ); 687 } else { 688 cpu_reset_interrupt(cs, CPU_INTERRUPT_VIRQ); 689 } 690 } 691 } 692 693 void arm_cpu_update_vfiq(ARMCPU *cpu) 694 { 695 /* 696 * Update the interrupt level for VFIQ, which is the logical OR of 697 * the HCR_EL2.VF bit and the input line level from the GIC. 698 */ 699 CPUARMState *env = &cpu->env; 700 CPUState *cs = CPU(cpu); 701 702 bool new_state = (env->cp15.hcr_el2 & HCR_VF) || 703 (env->irq_line_state & CPU_INTERRUPT_VFIQ); 704 705 if (new_state != ((cs->interrupt_request & CPU_INTERRUPT_VFIQ) != 0)) { 706 if (new_state) { 707 cpu_interrupt(cs, CPU_INTERRUPT_VFIQ); 708 } else { 709 cpu_reset_interrupt(cs, CPU_INTERRUPT_VFIQ); 710 } 711 } 712 } 713 714 void arm_cpu_update_vserr(ARMCPU *cpu) 715 { 716 /* 717 * Update the interrupt level for VSERR, which is the HCR_EL2.VSE bit. 718 */ 719 CPUARMState *env = &cpu->env; 720 CPUState *cs = CPU(cpu); 721 722 bool new_state = env->cp15.hcr_el2 & HCR_VSE; 723 724 if (new_state != ((cs->interrupt_request & CPU_INTERRUPT_VSERR) != 0)) { 725 if (new_state) { 726 cpu_interrupt(cs, CPU_INTERRUPT_VSERR); 727 } else { 728 cpu_reset_interrupt(cs, CPU_INTERRUPT_VSERR); 729 } 730 } 731 } 732 733 #ifndef CONFIG_USER_ONLY 734 static void arm_cpu_set_irq(void *opaque, int irq, int level) 735 { 736 ARMCPU *cpu = opaque; 737 CPUARMState *env = &cpu->env; 738 CPUState *cs = CPU(cpu); 739 static const int mask[] = { 740 [ARM_CPU_IRQ] = CPU_INTERRUPT_HARD, 741 [ARM_CPU_FIQ] = CPU_INTERRUPT_FIQ, 742 [ARM_CPU_VIRQ] = CPU_INTERRUPT_VIRQ, 743 [ARM_CPU_VFIQ] = CPU_INTERRUPT_VFIQ 744 }; 745 746 if (!arm_feature(env, ARM_FEATURE_EL2) && 747 (irq == ARM_CPU_VIRQ || irq == ARM_CPU_VFIQ)) { 748 /* 749 * The GIC might tell us about VIRQ and VFIQ state, but if we don't 750 * have EL2 support we don't care. (Unless the guest is doing something 751 * silly this will only be calls saying "level is still 0".) 752 */ 753 return; 754 } 755 756 if (level) { 757 env->irq_line_state |= mask[irq]; 758 } else { 759 env->irq_line_state &= ~mask[irq]; 760 } 761 762 switch (irq) { 763 case ARM_CPU_VIRQ: 764 arm_cpu_update_virq(cpu); 765 break; 766 case ARM_CPU_VFIQ: 767 arm_cpu_update_vfiq(cpu); 768 break; 769 case ARM_CPU_IRQ: 770 case ARM_CPU_FIQ: 771 if (level) { 772 cpu_interrupt(cs, mask[irq]); 773 } else { 774 cpu_reset_interrupt(cs, mask[irq]); 775 } 776 break; 777 default: 778 g_assert_not_reached(); 779 } 780 } 781 782 static void arm_cpu_kvm_set_irq(void *opaque, int irq, int level) 783 { 784 #ifdef CONFIG_KVM 785 ARMCPU *cpu = opaque; 786 CPUARMState *env = &cpu->env; 787 CPUState *cs = CPU(cpu); 788 uint32_t linestate_bit; 789 int irq_id; 790 791 switch (irq) { 792 case ARM_CPU_IRQ: 793 irq_id = KVM_ARM_IRQ_CPU_IRQ; 794 linestate_bit = CPU_INTERRUPT_HARD; 795 break; 796 case ARM_CPU_FIQ: 797 irq_id = KVM_ARM_IRQ_CPU_FIQ; 798 linestate_bit = CPU_INTERRUPT_FIQ; 799 break; 800 default: 801 g_assert_not_reached(); 802 } 803 804 if (level) { 805 env->irq_line_state |= linestate_bit; 806 } else { 807 env->irq_line_state &= ~linestate_bit; 808 } 809 kvm_arm_set_irq(cs->cpu_index, KVM_ARM_IRQ_TYPE_CPU, irq_id, !!level); 810 #endif 811 } 812 813 static bool arm_cpu_virtio_is_big_endian(CPUState *cs) 814 { 815 ARMCPU *cpu = ARM_CPU(cs); 816 CPUARMState *env = &cpu->env; 817 818 cpu_synchronize_state(cs); 819 return arm_cpu_data_is_big_endian(env); 820 } 821 822 #endif 823 824 static void arm_disas_set_info(CPUState *cpu, disassemble_info *info) 825 { 826 ARMCPU *ac = ARM_CPU(cpu); 827 CPUARMState *env = &ac->env; 828 bool sctlr_b; 829 830 if (is_a64(env)) { 831 /* We might not be compiled with the A64 disassembler 832 * because it needs a C++ compiler. Leave print_insn 833 * unset in this case to use the caller default behaviour. 834 */ 835 #if defined(CONFIG_ARM_A64_DIS) 836 info->print_insn = print_insn_arm_a64; 837 #endif 838 info->cap_arch = CS_ARCH_ARM64; 839 info->cap_insn_unit = 4; 840 info->cap_insn_split = 4; 841 } else { 842 int cap_mode; 843 if (env->thumb) { 844 info->cap_insn_unit = 2; 845 info->cap_insn_split = 4; 846 cap_mode = CS_MODE_THUMB; 847 } else { 848 info->cap_insn_unit = 4; 849 info->cap_insn_split = 4; 850 cap_mode = CS_MODE_ARM; 851 } 852 if (arm_feature(env, ARM_FEATURE_V8)) { 853 cap_mode |= CS_MODE_V8; 854 } 855 if (arm_feature(env, ARM_FEATURE_M)) { 856 cap_mode |= CS_MODE_MCLASS; 857 } 858 info->cap_arch = CS_ARCH_ARM; 859 info->cap_mode = cap_mode; 860 } 861 862 sctlr_b = arm_sctlr_b(env); 863 if (bswap_code(sctlr_b)) { 864 #if TARGET_BIG_ENDIAN 865 info->endian = BFD_ENDIAN_LITTLE; 866 #else 867 info->endian = BFD_ENDIAN_BIG; 868 #endif 869 } 870 info->flags &= ~INSN_ARM_BE32; 871 #ifndef CONFIG_USER_ONLY 872 if (sctlr_b) { 873 info->flags |= INSN_ARM_BE32; 874 } 875 #endif 876 } 877 878 #ifdef TARGET_AARCH64 879 880 static void aarch64_cpu_dump_state(CPUState *cs, FILE *f, int flags) 881 { 882 ARMCPU *cpu = ARM_CPU(cs); 883 CPUARMState *env = &cpu->env; 884 uint32_t psr = pstate_read(env); 885 int i; 886 int el = arm_current_el(env); 887 const char *ns_status; 888 889 qemu_fprintf(f, " PC=%016" PRIx64 " ", env->pc); 890 for (i = 0; i < 32; i++) { 891 if (i == 31) { 892 qemu_fprintf(f, " SP=%016" PRIx64 "\n", env->xregs[i]); 893 } else { 894 qemu_fprintf(f, "X%02d=%016" PRIx64 "%s", i, env->xregs[i], 895 (i + 2) % 3 ? " " : "\n"); 896 } 897 } 898 899 if (arm_feature(env, ARM_FEATURE_EL3) && el != 3) { 900 ns_status = env->cp15.scr_el3 & SCR_NS ? "NS " : "S "; 901 } else { 902 ns_status = ""; 903 } 904 qemu_fprintf(f, "PSTATE=%08x %c%c%c%c %sEL%d%c", 905 psr, 906 psr & PSTATE_N ? 'N' : '-', 907 psr & PSTATE_Z ? 'Z' : '-', 908 psr & PSTATE_C ? 'C' : '-', 909 psr & PSTATE_V ? 'V' : '-', 910 ns_status, 911 el, 912 psr & PSTATE_SP ? 'h' : 't'); 913 914 if (cpu_isar_feature(aa64_bti, cpu)) { 915 qemu_fprintf(f, " BTYPE=%d", (psr & PSTATE_BTYPE) >> 10); 916 } 917 if (!(flags & CPU_DUMP_FPU)) { 918 qemu_fprintf(f, "\n"); 919 return; 920 } 921 if (fp_exception_el(env, el) != 0) { 922 qemu_fprintf(f, " FPU disabled\n"); 923 return; 924 } 925 qemu_fprintf(f, " FPCR=%08x FPSR=%08x\n", 926 vfp_get_fpcr(env), vfp_get_fpsr(env)); 927 928 if (cpu_isar_feature(aa64_sve, cpu) && sve_exception_el(env, el) == 0) { 929 int j, zcr_len = sve_zcr_len_for_el(env, el); 930 931 for (i = 0; i <= FFR_PRED_NUM; i++) { 932 bool eol; 933 if (i == FFR_PRED_NUM) { 934 qemu_fprintf(f, "FFR="); 935 /* It's last, so end the line. */ 936 eol = true; 937 } else { 938 qemu_fprintf(f, "P%02d=", i); 939 switch (zcr_len) { 940 case 0: 941 eol = i % 8 == 7; 942 break; 943 case 1: 944 eol = i % 6 == 5; 945 break; 946 case 2: 947 case 3: 948 eol = i % 3 == 2; 949 break; 950 default: 951 /* More than one quadword per predicate. */ 952 eol = true; 953 break; 954 } 955 } 956 for (j = zcr_len / 4; j >= 0; j--) { 957 int digits; 958 if (j * 4 + 4 <= zcr_len + 1) { 959 digits = 16; 960 } else { 961 digits = (zcr_len % 4 + 1) * 4; 962 } 963 qemu_fprintf(f, "%0*" PRIx64 "%s", digits, 964 env->vfp.pregs[i].p[j], 965 j ? ":" : eol ? "\n" : " "); 966 } 967 } 968 969 for (i = 0; i < 32; i++) { 970 if (zcr_len == 0) { 971 qemu_fprintf(f, "Z%02d=%016" PRIx64 ":%016" PRIx64 "%s", 972 i, env->vfp.zregs[i].d[1], 973 env->vfp.zregs[i].d[0], i & 1 ? "\n" : " "); 974 } else if (zcr_len == 1) { 975 qemu_fprintf(f, "Z%02d=%016" PRIx64 ":%016" PRIx64 976 ":%016" PRIx64 ":%016" PRIx64 "\n", 977 i, env->vfp.zregs[i].d[3], env->vfp.zregs[i].d[2], 978 env->vfp.zregs[i].d[1], env->vfp.zregs[i].d[0]); 979 } else { 980 for (j = zcr_len; j >= 0; j--) { 981 bool odd = (zcr_len - j) % 2 != 0; 982 if (j == zcr_len) { 983 qemu_fprintf(f, "Z%02d[%x-%x]=", i, j, j - 1); 984 } else if (!odd) { 985 if (j > 0) { 986 qemu_fprintf(f, " [%x-%x]=", j, j - 1); 987 } else { 988 qemu_fprintf(f, " [%x]=", j); 989 } 990 } 991 qemu_fprintf(f, "%016" PRIx64 ":%016" PRIx64 "%s", 992 env->vfp.zregs[i].d[j * 2 + 1], 993 env->vfp.zregs[i].d[j * 2], 994 odd || j == 0 ? "\n" : ":"); 995 } 996 } 997 } 998 } else { 999 for (i = 0; i < 32; i++) { 1000 uint64_t *q = aa64_vfp_qreg(env, i); 1001 qemu_fprintf(f, "Q%02d=%016" PRIx64 ":%016" PRIx64 "%s", 1002 i, q[1], q[0], (i & 1 ? "\n" : " ")); 1003 } 1004 } 1005 } 1006 1007 #else 1008 1009 static inline void aarch64_cpu_dump_state(CPUState *cs, FILE *f, int flags) 1010 { 1011 g_assert_not_reached(); 1012 } 1013 1014 #endif 1015 1016 static void arm_cpu_dump_state(CPUState *cs, FILE *f, int flags) 1017 { 1018 ARMCPU *cpu = ARM_CPU(cs); 1019 CPUARMState *env = &cpu->env; 1020 int i; 1021 1022 if (is_a64(env)) { 1023 aarch64_cpu_dump_state(cs, f, flags); 1024 return; 1025 } 1026 1027 for (i = 0; i < 16; i++) { 1028 qemu_fprintf(f, "R%02d=%08x", i, env->regs[i]); 1029 if ((i % 4) == 3) { 1030 qemu_fprintf(f, "\n"); 1031 } else { 1032 qemu_fprintf(f, " "); 1033 } 1034 } 1035 1036 if (arm_feature(env, ARM_FEATURE_M)) { 1037 uint32_t xpsr = xpsr_read(env); 1038 const char *mode; 1039 const char *ns_status = ""; 1040 1041 if (arm_feature(env, ARM_FEATURE_M_SECURITY)) { 1042 ns_status = env->v7m.secure ? "S " : "NS "; 1043 } 1044 1045 if (xpsr & XPSR_EXCP) { 1046 mode = "handler"; 1047 } else { 1048 if (env->v7m.control[env->v7m.secure] & R_V7M_CONTROL_NPRIV_MASK) { 1049 mode = "unpriv-thread"; 1050 } else { 1051 mode = "priv-thread"; 1052 } 1053 } 1054 1055 qemu_fprintf(f, "XPSR=%08x %c%c%c%c %c %s%s\n", 1056 xpsr, 1057 xpsr & XPSR_N ? 'N' : '-', 1058 xpsr & XPSR_Z ? 'Z' : '-', 1059 xpsr & XPSR_C ? 'C' : '-', 1060 xpsr & XPSR_V ? 'V' : '-', 1061 xpsr & XPSR_T ? 'T' : 'A', 1062 ns_status, 1063 mode); 1064 } else { 1065 uint32_t psr = cpsr_read(env); 1066 const char *ns_status = ""; 1067 1068 if (arm_feature(env, ARM_FEATURE_EL3) && 1069 (psr & CPSR_M) != ARM_CPU_MODE_MON) { 1070 ns_status = env->cp15.scr_el3 & SCR_NS ? "NS " : "S "; 1071 } 1072 1073 qemu_fprintf(f, "PSR=%08x %c%c%c%c %c %s%s%d\n", 1074 psr, 1075 psr & CPSR_N ? 'N' : '-', 1076 psr & CPSR_Z ? 'Z' : '-', 1077 psr & CPSR_C ? 'C' : '-', 1078 psr & CPSR_V ? 'V' : '-', 1079 psr & CPSR_T ? 'T' : 'A', 1080 ns_status, 1081 aarch32_mode_name(psr), (psr & 0x10) ? 32 : 26); 1082 } 1083 1084 if (flags & CPU_DUMP_FPU) { 1085 int numvfpregs = 0; 1086 if (cpu_isar_feature(aa32_simd_r32, cpu)) { 1087 numvfpregs = 32; 1088 } else if (cpu_isar_feature(aa32_vfp_simd, cpu)) { 1089 numvfpregs = 16; 1090 } 1091 for (i = 0; i < numvfpregs; i++) { 1092 uint64_t v = *aa32_vfp_dreg(env, i); 1093 qemu_fprintf(f, "s%02d=%08x s%02d=%08x d%02d=%016" PRIx64 "\n", 1094 i * 2, (uint32_t)v, 1095 i * 2 + 1, (uint32_t)(v >> 32), 1096 i, v); 1097 } 1098 qemu_fprintf(f, "FPSCR: %08x\n", vfp_get_fpscr(env)); 1099 if (cpu_isar_feature(aa32_mve, cpu)) { 1100 qemu_fprintf(f, "VPR: %08x\n", env->v7m.vpr); 1101 } 1102 } 1103 } 1104 1105 uint64_t arm_cpu_mp_affinity(int idx, uint8_t clustersz) 1106 { 1107 uint32_t Aff1 = idx / clustersz; 1108 uint32_t Aff0 = idx % clustersz; 1109 return (Aff1 << ARM_AFF1_SHIFT) | Aff0; 1110 } 1111 1112 static void arm_cpu_initfn(Object *obj) 1113 { 1114 ARMCPU *cpu = ARM_CPU(obj); 1115 1116 cpu_set_cpustate_pointers(cpu); 1117 cpu->cp_regs = g_hash_table_new_full(g_direct_hash, g_direct_equal, 1118 NULL, g_free); 1119 1120 QLIST_INIT(&cpu->pre_el_change_hooks); 1121 QLIST_INIT(&cpu->el_change_hooks); 1122 1123 #ifdef CONFIG_USER_ONLY 1124 # ifdef TARGET_AARCH64 1125 /* 1126 * The linux kernel defaults to 512-bit vectors, when sve is supported. 1127 * See documentation for /proc/sys/abi/sve_default_vector_length, and 1128 * our corresponding sve-default-vector-length cpu property. 1129 */ 1130 cpu->sve_default_vq = 4; 1131 # endif 1132 #else 1133 /* Our inbound IRQ and FIQ lines */ 1134 if (kvm_enabled()) { 1135 /* VIRQ and VFIQ are unused with KVM but we add them to maintain 1136 * the same interface as non-KVM CPUs. 1137 */ 1138 qdev_init_gpio_in(DEVICE(cpu), arm_cpu_kvm_set_irq, 4); 1139 } else { 1140 qdev_init_gpio_in(DEVICE(cpu), arm_cpu_set_irq, 4); 1141 } 1142 1143 qdev_init_gpio_out(DEVICE(cpu), cpu->gt_timer_outputs, 1144 ARRAY_SIZE(cpu->gt_timer_outputs)); 1145 1146 qdev_init_gpio_out_named(DEVICE(cpu), &cpu->gicv3_maintenance_interrupt, 1147 "gicv3-maintenance-interrupt", 1); 1148 qdev_init_gpio_out_named(DEVICE(cpu), &cpu->pmu_interrupt, 1149 "pmu-interrupt", 1); 1150 #endif 1151 1152 /* DTB consumers generally don't in fact care what the 'compatible' 1153 * string is, so always provide some string and trust that a hypothetical 1154 * picky DTB consumer will also provide a helpful error message. 1155 */ 1156 cpu->dtb_compatible = "qemu,unknown"; 1157 cpu->psci_version = QEMU_PSCI_VERSION_0_1; /* By default assume PSCI v0.1 */ 1158 cpu->kvm_target = QEMU_KVM_ARM_TARGET_NONE; 1159 1160 if (tcg_enabled() || hvf_enabled()) { 1161 /* TCG and HVF implement PSCI 1.1 */ 1162 cpu->psci_version = QEMU_PSCI_VERSION_1_1; 1163 } 1164 } 1165 1166 static Property arm_cpu_gt_cntfrq_property = 1167 DEFINE_PROP_UINT64("cntfrq", ARMCPU, gt_cntfrq_hz, 1168 NANOSECONDS_PER_SECOND / GTIMER_SCALE); 1169 1170 static Property arm_cpu_reset_cbar_property = 1171 DEFINE_PROP_UINT64("reset-cbar", ARMCPU, reset_cbar, 0); 1172 1173 static Property arm_cpu_reset_hivecs_property = 1174 DEFINE_PROP_BOOL("reset-hivecs", ARMCPU, reset_hivecs, false); 1175 1176 #ifndef CONFIG_USER_ONLY 1177 static Property arm_cpu_has_el2_property = 1178 DEFINE_PROP_BOOL("has_el2", ARMCPU, has_el2, true); 1179 1180 static Property arm_cpu_has_el3_property = 1181 DEFINE_PROP_BOOL("has_el3", ARMCPU, has_el3, true); 1182 #endif 1183 1184 static Property arm_cpu_cfgend_property = 1185 DEFINE_PROP_BOOL("cfgend", ARMCPU, cfgend, false); 1186 1187 static Property arm_cpu_has_vfp_property = 1188 DEFINE_PROP_BOOL("vfp", ARMCPU, has_vfp, true); 1189 1190 static Property arm_cpu_has_neon_property = 1191 DEFINE_PROP_BOOL("neon", ARMCPU, has_neon, true); 1192 1193 static Property arm_cpu_has_dsp_property = 1194 DEFINE_PROP_BOOL("dsp", ARMCPU, has_dsp, true); 1195 1196 static Property arm_cpu_has_mpu_property = 1197 DEFINE_PROP_BOOL("has-mpu", ARMCPU, has_mpu, true); 1198 1199 /* This is like DEFINE_PROP_UINT32 but it doesn't set the default value, 1200 * because the CPU initfn will have already set cpu->pmsav7_dregion to 1201 * the right value for that particular CPU type, and we don't want 1202 * to override that with an incorrect constant value. 1203 */ 1204 static Property arm_cpu_pmsav7_dregion_property = 1205 DEFINE_PROP_UNSIGNED_NODEFAULT("pmsav7-dregion", ARMCPU, 1206 pmsav7_dregion, 1207 qdev_prop_uint32, uint32_t); 1208 1209 static bool arm_get_pmu(Object *obj, Error **errp) 1210 { 1211 ARMCPU *cpu = ARM_CPU(obj); 1212 1213 return cpu->has_pmu; 1214 } 1215 1216 static void arm_set_pmu(Object *obj, bool value, Error **errp) 1217 { 1218 ARMCPU *cpu = ARM_CPU(obj); 1219 1220 if (value) { 1221 if (kvm_enabled() && !kvm_arm_pmu_supported()) { 1222 error_setg(errp, "'pmu' feature not supported by KVM on this host"); 1223 return; 1224 } 1225 set_feature(&cpu->env, ARM_FEATURE_PMU); 1226 } else { 1227 unset_feature(&cpu->env, ARM_FEATURE_PMU); 1228 } 1229 cpu->has_pmu = value; 1230 } 1231 1232 unsigned int gt_cntfrq_period_ns(ARMCPU *cpu) 1233 { 1234 /* 1235 * The exact approach to calculating guest ticks is: 1236 * 1237 * muldiv64(qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL), cpu->gt_cntfrq_hz, 1238 * NANOSECONDS_PER_SECOND); 1239 * 1240 * We don't do that. Rather we intentionally use integer division 1241 * truncation below and in the caller for the conversion of host monotonic 1242 * time to guest ticks to provide the exact inverse for the semantics of 1243 * the QEMUTimer scale factor. QEMUTimer's scale facter is an integer, so 1244 * it loses precision when representing frequencies where 1245 * `(NANOSECONDS_PER_SECOND % cpu->gt_cntfrq) > 0` holds. Failing to 1246 * provide an exact inverse leads to scheduling timers with negative 1247 * periods, which in turn leads to sticky behaviour in the guest. 1248 * 1249 * Finally, CNTFRQ is effectively capped at 1GHz to ensure our scale factor 1250 * cannot become zero. 1251 */ 1252 return NANOSECONDS_PER_SECOND > cpu->gt_cntfrq_hz ? 1253 NANOSECONDS_PER_SECOND / cpu->gt_cntfrq_hz : 1; 1254 } 1255 1256 void arm_cpu_post_init(Object *obj) 1257 { 1258 ARMCPU *cpu = ARM_CPU(obj); 1259 1260 /* M profile implies PMSA. We have to do this here rather than 1261 * in realize with the other feature-implication checks because 1262 * we look at the PMSA bit to see if we should add some properties. 1263 */ 1264 if (arm_feature(&cpu->env, ARM_FEATURE_M)) { 1265 set_feature(&cpu->env, ARM_FEATURE_PMSA); 1266 } 1267 1268 if (arm_feature(&cpu->env, ARM_FEATURE_CBAR) || 1269 arm_feature(&cpu->env, ARM_FEATURE_CBAR_RO)) { 1270 qdev_property_add_static(DEVICE(obj), &arm_cpu_reset_cbar_property); 1271 } 1272 1273 if (!arm_feature(&cpu->env, ARM_FEATURE_M)) { 1274 qdev_property_add_static(DEVICE(obj), &arm_cpu_reset_hivecs_property); 1275 } 1276 1277 if (arm_feature(&cpu->env, ARM_FEATURE_AARCH64)) { 1278 object_property_add_uint64_ptr(obj, "rvbar", 1279 &cpu->rvbar_prop, 1280 OBJ_PROP_FLAG_READWRITE); 1281 } 1282 1283 #ifndef CONFIG_USER_ONLY 1284 if (arm_feature(&cpu->env, ARM_FEATURE_EL3)) { 1285 /* Add the has_el3 state CPU property only if EL3 is allowed. This will 1286 * prevent "has_el3" from existing on CPUs which cannot support EL3. 1287 */ 1288 qdev_property_add_static(DEVICE(obj), &arm_cpu_has_el3_property); 1289 1290 object_property_add_link(obj, "secure-memory", 1291 TYPE_MEMORY_REGION, 1292 (Object **)&cpu->secure_memory, 1293 qdev_prop_allow_set_link_before_realize, 1294 OBJ_PROP_LINK_STRONG); 1295 } 1296 1297 if (arm_feature(&cpu->env, ARM_FEATURE_EL2)) { 1298 qdev_property_add_static(DEVICE(obj), &arm_cpu_has_el2_property); 1299 } 1300 #endif 1301 1302 if (arm_feature(&cpu->env, ARM_FEATURE_PMU)) { 1303 cpu->has_pmu = true; 1304 object_property_add_bool(obj, "pmu", arm_get_pmu, arm_set_pmu); 1305 } 1306 1307 /* 1308 * Allow user to turn off VFP and Neon support, but only for TCG -- 1309 * KVM does not currently allow us to lie to the guest about its 1310 * ID/feature registers, so the guest always sees what the host has. 1311 */ 1312 if (arm_feature(&cpu->env, ARM_FEATURE_AARCH64) 1313 ? cpu_isar_feature(aa64_fp_simd, cpu) 1314 : cpu_isar_feature(aa32_vfp, cpu)) { 1315 cpu->has_vfp = true; 1316 if (!kvm_enabled()) { 1317 qdev_property_add_static(DEVICE(obj), &arm_cpu_has_vfp_property); 1318 } 1319 } 1320 1321 if (arm_feature(&cpu->env, ARM_FEATURE_NEON)) { 1322 cpu->has_neon = true; 1323 if (!kvm_enabled()) { 1324 qdev_property_add_static(DEVICE(obj), &arm_cpu_has_neon_property); 1325 } 1326 } 1327 1328 if (arm_feature(&cpu->env, ARM_FEATURE_M) && 1329 arm_feature(&cpu->env, ARM_FEATURE_THUMB_DSP)) { 1330 qdev_property_add_static(DEVICE(obj), &arm_cpu_has_dsp_property); 1331 } 1332 1333 if (arm_feature(&cpu->env, ARM_FEATURE_PMSA)) { 1334 qdev_property_add_static(DEVICE(obj), &arm_cpu_has_mpu_property); 1335 if (arm_feature(&cpu->env, ARM_FEATURE_V7)) { 1336 qdev_property_add_static(DEVICE(obj), 1337 &arm_cpu_pmsav7_dregion_property); 1338 } 1339 } 1340 1341 if (arm_feature(&cpu->env, ARM_FEATURE_M_SECURITY)) { 1342 object_property_add_link(obj, "idau", TYPE_IDAU_INTERFACE, &cpu->idau, 1343 qdev_prop_allow_set_link_before_realize, 1344 OBJ_PROP_LINK_STRONG); 1345 /* 1346 * M profile: initial value of the Secure VTOR. We can't just use 1347 * a simple DEFINE_PROP_UINT32 for this because we want to permit 1348 * the property to be set after realize. 1349 */ 1350 object_property_add_uint32_ptr(obj, "init-svtor", 1351 &cpu->init_svtor, 1352 OBJ_PROP_FLAG_READWRITE); 1353 } 1354 if (arm_feature(&cpu->env, ARM_FEATURE_M)) { 1355 /* 1356 * Initial value of the NS VTOR (for cores without the Security 1357 * extension, this is the only VTOR) 1358 */ 1359 object_property_add_uint32_ptr(obj, "init-nsvtor", 1360 &cpu->init_nsvtor, 1361 OBJ_PROP_FLAG_READWRITE); 1362 } 1363 1364 /* Not DEFINE_PROP_UINT32: we want this to be settable after realize */ 1365 object_property_add_uint32_ptr(obj, "psci-conduit", 1366 &cpu->psci_conduit, 1367 OBJ_PROP_FLAG_READWRITE); 1368 1369 qdev_property_add_static(DEVICE(obj), &arm_cpu_cfgend_property); 1370 1371 if (arm_feature(&cpu->env, ARM_FEATURE_GENERIC_TIMER)) { 1372 qdev_property_add_static(DEVICE(cpu), &arm_cpu_gt_cntfrq_property); 1373 } 1374 1375 if (kvm_enabled()) { 1376 kvm_arm_add_vcpu_properties(obj); 1377 } 1378 1379 #ifndef CONFIG_USER_ONLY 1380 if (arm_feature(&cpu->env, ARM_FEATURE_AARCH64) && 1381 cpu_isar_feature(aa64_mte, cpu)) { 1382 object_property_add_link(obj, "tag-memory", 1383 TYPE_MEMORY_REGION, 1384 (Object **)&cpu->tag_memory, 1385 qdev_prop_allow_set_link_before_realize, 1386 OBJ_PROP_LINK_STRONG); 1387 1388 if (arm_feature(&cpu->env, ARM_FEATURE_EL3)) { 1389 object_property_add_link(obj, "secure-tag-memory", 1390 TYPE_MEMORY_REGION, 1391 (Object **)&cpu->secure_tag_memory, 1392 qdev_prop_allow_set_link_before_realize, 1393 OBJ_PROP_LINK_STRONG); 1394 } 1395 } 1396 #endif 1397 } 1398 1399 static void arm_cpu_finalizefn(Object *obj) 1400 { 1401 ARMCPU *cpu = ARM_CPU(obj); 1402 ARMELChangeHook *hook, *next; 1403 1404 g_hash_table_destroy(cpu->cp_regs); 1405 1406 QLIST_FOREACH_SAFE(hook, &cpu->pre_el_change_hooks, node, next) { 1407 QLIST_REMOVE(hook, node); 1408 g_free(hook); 1409 } 1410 QLIST_FOREACH_SAFE(hook, &cpu->el_change_hooks, node, next) { 1411 QLIST_REMOVE(hook, node); 1412 g_free(hook); 1413 } 1414 #ifndef CONFIG_USER_ONLY 1415 if (cpu->pmu_timer) { 1416 timer_free(cpu->pmu_timer); 1417 } 1418 #endif 1419 } 1420 1421 void arm_cpu_finalize_features(ARMCPU *cpu, Error **errp) 1422 { 1423 Error *local_err = NULL; 1424 1425 if (arm_feature(&cpu->env, ARM_FEATURE_AARCH64)) { 1426 arm_cpu_sve_finalize(cpu, &local_err); 1427 if (local_err != NULL) { 1428 error_propagate(errp, local_err); 1429 return; 1430 } 1431 1432 arm_cpu_pauth_finalize(cpu, &local_err); 1433 if (local_err != NULL) { 1434 error_propagate(errp, local_err); 1435 return; 1436 } 1437 1438 arm_cpu_lpa2_finalize(cpu, &local_err); 1439 if (local_err != NULL) { 1440 error_propagate(errp, local_err); 1441 return; 1442 } 1443 } 1444 1445 if (kvm_enabled()) { 1446 kvm_arm_steal_time_finalize(cpu, &local_err); 1447 if (local_err != NULL) { 1448 error_propagate(errp, local_err); 1449 return; 1450 } 1451 } 1452 } 1453 1454 static void arm_cpu_realizefn(DeviceState *dev, Error **errp) 1455 { 1456 CPUState *cs = CPU(dev); 1457 ARMCPU *cpu = ARM_CPU(dev); 1458 ARMCPUClass *acc = ARM_CPU_GET_CLASS(dev); 1459 CPUARMState *env = &cpu->env; 1460 int pagebits; 1461 Error *local_err = NULL; 1462 bool no_aa32 = false; 1463 1464 /* If we needed to query the host kernel for the CPU features 1465 * then it's possible that might have failed in the initfn, but 1466 * this is the first point where we can report it. 1467 */ 1468 if (cpu->host_cpu_probe_failed) { 1469 if (!kvm_enabled() && !hvf_enabled()) { 1470 error_setg(errp, "The 'host' CPU type can only be used with KVM or HVF"); 1471 } else { 1472 error_setg(errp, "Failed to retrieve host CPU features"); 1473 } 1474 return; 1475 } 1476 1477 #ifndef CONFIG_USER_ONLY 1478 /* The NVIC and M-profile CPU are two halves of a single piece of 1479 * hardware; trying to use one without the other is a command line 1480 * error and will result in segfaults if not caught here. 1481 */ 1482 if (arm_feature(env, ARM_FEATURE_M)) { 1483 if (!env->nvic) { 1484 error_setg(errp, "This board cannot be used with Cortex-M CPUs"); 1485 return; 1486 } 1487 } else { 1488 if (env->nvic) { 1489 error_setg(errp, "This board can only be used with Cortex-M CPUs"); 1490 return; 1491 } 1492 } 1493 1494 if (kvm_enabled()) { 1495 /* 1496 * Catch all the cases which might cause us to create more than one 1497 * address space for the CPU (otherwise we will assert() later in 1498 * cpu_address_space_init()). 1499 */ 1500 if (arm_feature(env, ARM_FEATURE_M)) { 1501 error_setg(errp, 1502 "Cannot enable KVM when using an M-profile guest CPU"); 1503 return; 1504 } 1505 if (cpu->has_el3) { 1506 error_setg(errp, 1507 "Cannot enable KVM when guest CPU has EL3 enabled"); 1508 return; 1509 } 1510 if (cpu->tag_memory) { 1511 error_setg(errp, 1512 "Cannot enable KVM when guest CPUs has MTE enabled"); 1513 return; 1514 } 1515 } 1516 1517 { 1518 uint64_t scale; 1519 1520 if (arm_feature(env, ARM_FEATURE_GENERIC_TIMER)) { 1521 if (!cpu->gt_cntfrq_hz) { 1522 error_setg(errp, "Invalid CNTFRQ: %"PRId64"Hz", 1523 cpu->gt_cntfrq_hz); 1524 return; 1525 } 1526 scale = gt_cntfrq_period_ns(cpu); 1527 } else { 1528 scale = GTIMER_SCALE; 1529 } 1530 1531 cpu->gt_timer[GTIMER_PHYS] = timer_new(QEMU_CLOCK_VIRTUAL, scale, 1532 arm_gt_ptimer_cb, cpu); 1533 cpu->gt_timer[GTIMER_VIRT] = timer_new(QEMU_CLOCK_VIRTUAL, scale, 1534 arm_gt_vtimer_cb, cpu); 1535 cpu->gt_timer[GTIMER_HYP] = timer_new(QEMU_CLOCK_VIRTUAL, scale, 1536 arm_gt_htimer_cb, cpu); 1537 cpu->gt_timer[GTIMER_SEC] = timer_new(QEMU_CLOCK_VIRTUAL, scale, 1538 arm_gt_stimer_cb, cpu); 1539 cpu->gt_timer[GTIMER_HYPVIRT] = timer_new(QEMU_CLOCK_VIRTUAL, scale, 1540 arm_gt_hvtimer_cb, cpu); 1541 } 1542 #endif 1543 1544 cpu_exec_realizefn(cs, &local_err); 1545 if (local_err != NULL) { 1546 error_propagate(errp, local_err); 1547 return; 1548 } 1549 1550 arm_cpu_finalize_features(cpu, &local_err); 1551 if (local_err != NULL) { 1552 error_propagate(errp, local_err); 1553 return; 1554 } 1555 1556 if (arm_feature(env, ARM_FEATURE_AARCH64) && 1557 cpu->has_vfp != cpu->has_neon) { 1558 /* 1559 * This is an architectural requirement for AArch64; AArch32 is 1560 * more flexible and permits VFP-no-Neon and Neon-no-VFP. 1561 */ 1562 error_setg(errp, 1563 "AArch64 CPUs must have both VFP and Neon or neither"); 1564 return; 1565 } 1566 1567 if (!cpu->has_vfp) { 1568 uint64_t t; 1569 uint32_t u; 1570 1571 t = cpu->isar.id_aa64isar1; 1572 t = FIELD_DP64(t, ID_AA64ISAR1, JSCVT, 0); 1573 cpu->isar.id_aa64isar1 = t; 1574 1575 t = cpu->isar.id_aa64pfr0; 1576 t = FIELD_DP64(t, ID_AA64PFR0, FP, 0xf); 1577 cpu->isar.id_aa64pfr0 = t; 1578 1579 u = cpu->isar.id_isar6; 1580 u = FIELD_DP32(u, ID_ISAR6, JSCVT, 0); 1581 u = FIELD_DP32(u, ID_ISAR6, BF16, 0); 1582 cpu->isar.id_isar6 = u; 1583 1584 u = cpu->isar.mvfr0; 1585 u = FIELD_DP32(u, MVFR0, FPSP, 0); 1586 u = FIELD_DP32(u, MVFR0, FPDP, 0); 1587 u = FIELD_DP32(u, MVFR0, FPDIVIDE, 0); 1588 u = FIELD_DP32(u, MVFR0, FPSQRT, 0); 1589 u = FIELD_DP32(u, MVFR0, FPROUND, 0); 1590 if (!arm_feature(env, ARM_FEATURE_M)) { 1591 u = FIELD_DP32(u, MVFR0, FPTRAP, 0); 1592 u = FIELD_DP32(u, MVFR0, FPSHVEC, 0); 1593 } 1594 cpu->isar.mvfr0 = u; 1595 1596 u = cpu->isar.mvfr1; 1597 u = FIELD_DP32(u, MVFR1, FPFTZ, 0); 1598 u = FIELD_DP32(u, MVFR1, FPDNAN, 0); 1599 u = FIELD_DP32(u, MVFR1, FPHP, 0); 1600 if (arm_feature(env, ARM_FEATURE_M)) { 1601 u = FIELD_DP32(u, MVFR1, FP16, 0); 1602 } 1603 cpu->isar.mvfr1 = u; 1604 1605 u = cpu->isar.mvfr2; 1606 u = FIELD_DP32(u, MVFR2, FPMISC, 0); 1607 cpu->isar.mvfr2 = u; 1608 } 1609 1610 if (!cpu->has_neon) { 1611 uint64_t t; 1612 uint32_t u; 1613 1614 unset_feature(env, ARM_FEATURE_NEON); 1615 1616 t = cpu->isar.id_aa64isar0; 1617 t = FIELD_DP64(t, ID_AA64ISAR0, AES, 0); 1618 t = FIELD_DP64(t, ID_AA64ISAR0, SHA1, 0); 1619 t = FIELD_DP64(t, ID_AA64ISAR0, SHA2, 0); 1620 t = FIELD_DP64(t, ID_AA64ISAR0, SHA3, 0); 1621 t = FIELD_DP64(t, ID_AA64ISAR0, SM3, 0); 1622 t = FIELD_DP64(t, ID_AA64ISAR0, SM4, 0); 1623 t = FIELD_DP64(t, ID_AA64ISAR0, DP, 0); 1624 cpu->isar.id_aa64isar0 = t; 1625 1626 t = cpu->isar.id_aa64isar1; 1627 t = FIELD_DP64(t, ID_AA64ISAR1, FCMA, 0); 1628 t = FIELD_DP64(t, ID_AA64ISAR1, BF16, 0); 1629 t = FIELD_DP64(t, ID_AA64ISAR1, I8MM, 0); 1630 cpu->isar.id_aa64isar1 = t; 1631 1632 t = cpu->isar.id_aa64pfr0; 1633 t = FIELD_DP64(t, ID_AA64PFR0, ADVSIMD, 0xf); 1634 cpu->isar.id_aa64pfr0 = t; 1635 1636 u = cpu->isar.id_isar5; 1637 u = FIELD_DP32(u, ID_ISAR5, AES, 0); 1638 u = FIELD_DP32(u, ID_ISAR5, SHA1, 0); 1639 u = FIELD_DP32(u, ID_ISAR5, SHA2, 0); 1640 u = FIELD_DP32(u, ID_ISAR5, RDM, 0); 1641 u = FIELD_DP32(u, ID_ISAR5, VCMA, 0); 1642 cpu->isar.id_isar5 = u; 1643 1644 u = cpu->isar.id_isar6; 1645 u = FIELD_DP32(u, ID_ISAR6, DP, 0); 1646 u = FIELD_DP32(u, ID_ISAR6, FHM, 0); 1647 u = FIELD_DP32(u, ID_ISAR6, BF16, 0); 1648 u = FIELD_DP32(u, ID_ISAR6, I8MM, 0); 1649 cpu->isar.id_isar6 = u; 1650 1651 if (!arm_feature(env, ARM_FEATURE_M)) { 1652 u = cpu->isar.mvfr1; 1653 u = FIELD_DP32(u, MVFR1, SIMDLS, 0); 1654 u = FIELD_DP32(u, MVFR1, SIMDINT, 0); 1655 u = FIELD_DP32(u, MVFR1, SIMDSP, 0); 1656 u = FIELD_DP32(u, MVFR1, SIMDHP, 0); 1657 cpu->isar.mvfr1 = u; 1658 1659 u = cpu->isar.mvfr2; 1660 u = FIELD_DP32(u, MVFR2, SIMDMISC, 0); 1661 cpu->isar.mvfr2 = u; 1662 } 1663 } 1664 1665 if (!cpu->has_neon && !cpu->has_vfp) { 1666 uint64_t t; 1667 uint32_t u; 1668 1669 t = cpu->isar.id_aa64isar0; 1670 t = FIELD_DP64(t, ID_AA64ISAR0, FHM, 0); 1671 cpu->isar.id_aa64isar0 = t; 1672 1673 t = cpu->isar.id_aa64isar1; 1674 t = FIELD_DP64(t, ID_AA64ISAR1, FRINTTS, 0); 1675 cpu->isar.id_aa64isar1 = t; 1676 1677 u = cpu->isar.mvfr0; 1678 u = FIELD_DP32(u, MVFR0, SIMDREG, 0); 1679 cpu->isar.mvfr0 = u; 1680 1681 /* Despite the name, this field covers both VFP and Neon */ 1682 u = cpu->isar.mvfr1; 1683 u = FIELD_DP32(u, MVFR1, SIMDFMAC, 0); 1684 cpu->isar.mvfr1 = u; 1685 } 1686 1687 if (arm_feature(env, ARM_FEATURE_M) && !cpu->has_dsp) { 1688 uint32_t u; 1689 1690 unset_feature(env, ARM_FEATURE_THUMB_DSP); 1691 1692 u = cpu->isar.id_isar1; 1693 u = FIELD_DP32(u, ID_ISAR1, EXTEND, 1); 1694 cpu->isar.id_isar1 = u; 1695 1696 u = cpu->isar.id_isar2; 1697 u = FIELD_DP32(u, ID_ISAR2, MULTU, 1); 1698 u = FIELD_DP32(u, ID_ISAR2, MULTS, 1); 1699 cpu->isar.id_isar2 = u; 1700 1701 u = cpu->isar.id_isar3; 1702 u = FIELD_DP32(u, ID_ISAR3, SIMD, 1); 1703 u = FIELD_DP32(u, ID_ISAR3, SATURATE, 0); 1704 cpu->isar.id_isar3 = u; 1705 } 1706 1707 /* Some features automatically imply others: */ 1708 if (arm_feature(env, ARM_FEATURE_V8)) { 1709 if (arm_feature(env, ARM_FEATURE_M)) { 1710 set_feature(env, ARM_FEATURE_V7); 1711 } else { 1712 set_feature(env, ARM_FEATURE_V7VE); 1713 } 1714 } 1715 1716 /* 1717 * There exist AArch64 cpus without AArch32 support. When KVM 1718 * queries ID_ISAR0_EL1 on such a host, the value is UNKNOWN. 1719 * Similarly, we cannot check ID_AA64PFR0 without AArch64 support. 1720 * As a general principle, we also do not make ID register 1721 * consistency checks anywhere unless using TCG, because only 1722 * for TCG would a consistency-check failure be a QEMU bug. 1723 */ 1724 if (arm_feature(&cpu->env, ARM_FEATURE_AARCH64)) { 1725 no_aa32 = !cpu_isar_feature(aa64_aa32, cpu); 1726 } 1727 1728 if (arm_feature(env, ARM_FEATURE_V7VE)) { 1729 /* v7 Virtualization Extensions. In real hardware this implies 1730 * EL2 and also the presence of the Security Extensions. 1731 * For QEMU, for backwards-compatibility we implement some 1732 * CPUs or CPU configs which have no actual EL2 or EL3 but do 1733 * include the various other features that V7VE implies. 1734 * Presence of EL2 itself is ARM_FEATURE_EL2, and of the 1735 * Security Extensions is ARM_FEATURE_EL3. 1736 */ 1737 assert(!tcg_enabled() || no_aa32 || 1738 cpu_isar_feature(aa32_arm_div, cpu)); 1739 set_feature(env, ARM_FEATURE_LPAE); 1740 set_feature(env, ARM_FEATURE_V7); 1741 } 1742 if (arm_feature(env, ARM_FEATURE_V7)) { 1743 set_feature(env, ARM_FEATURE_VAPA); 1744 set_feature(env, ARM_FEATURE_THUMB2); 1745 set_feature(env, ARM_FEATURE_MPIDR); 1746 if (!arm_feature(env, ARM_FEATURE_M)) { 1747 set_feature(env, ARM_FEATURE_V6K); 1748 } else { 1749 set_feature(env, ARM_FEATURE_V6); 1750 } 1751 1752 /* Always define VBAR for V7 CPUs even if it doesn't exist in 1753 * non-EL3 configs. This is needed by some legacy boards. 1754 */ 1755 set_feature(env, ARM_FEATURE_VBAR); 1756 } 1757 if (arm_feature(env, ARM_FEATURE_V6K)) { 1758 set_feature(env, ARM_FEATURE_V6); 1759 set_feature(env, ARM_FEATURE_MVFR); 1760 } 1761 if (arm_feature(env, ARM_FEATURE_V6)) { 1762 set_feature(env, ARM_FEATURE_V5); 1763 if (!arm_feature(env, ARM_FEATURE_M)) { 1764 assert(!tcg_enabled() || no_aa32 || 1765 cpu_isar_feature(aa32_jazelle, cpu)); 1766 set_feature(env, ARM_FEATURE_AUXCR); 1767 } 1768 } 1769 if (arm_feature(env, ARM_FEATURE_V5)) { 1770 set_feature(env, ARM_FEATURE_V4T); 1771 } 1772 if (arm_feature(env, ARM_FEATURE_LPAE)) { 1773 set_feature(env, ARM_FEATURE_V7MP); 1774 } 1775 if (arm_feature(env, ARM_FEATURE_CBAR_RO)) { 1776 set_feature(env, ARM_FEATURE_CBAR); 1777 } 1778 if (arm_feature(env, ARM_FEATURE_THUMB2) && 1779 !arm_feature(env, ARM_FEATURE_M)) { 1780 set_feature(env, ARM_FEATURE_THUMB_DSP); 1781 } 1782 1783 /* 1784 * We rely on no XScale CPU having VFP so we can use the same bits in the 1785 * TB flags field for VECSTRIDE and XSCALE_CPAR. 1786 */ 1787 assert(arm_feature(&cpu->env, ARM_FEATURE_AARCH64) || 1788 !cpu_isar_feature(aa32_vfp_simd, cpu) || 1789 !arm_feature(env, ARM_FEATURE_XSCALE)); 1790 1791 if (arm_feature(env, ARM_FEATURE_V7) && 1792 !arm_feature(env, ARM_FEATURE_M) && 1793 !arm_feature(env, ARM_FEATURE_PMSA)) { 1794 /* v7VMSA drops support for the old ARMv5 tiny pages, so we 1795 * can use 4K pages. 1796 */ 1797 pagebits = 12; 1798 } else { 1799 /* For CPUs which might have tiny 1K pages, or which have an 1800 * MPU and might have small region sizes, stick with 1K pages. 1801 */ 1802 pagebits = 10; 1803 } 1804 if (!set_preferred_target_page_bits(pagebits)) { 1805 /* This can only ever happen for hotplugging a CPU, or if 1806 * the board code incorrectly creates a CPU which it has 1807 * promised via minimum_page_size that it will not. 1808 */ 1809 error_setg(errp, "This CPU requires a smaller page size than the " 1810 "system is using"); 1811 return; 1812 } 1813 1814 /* This cpu-id-to-MPIDR affinity is used only for TCG; KVM will override it. 1815 * We don't support setting cluster ID ([16..23]) (known as Aff2 1816 * in later ARM ARM versions), or any of the higher affinity level fields, 1817 * so these bits always RAZ. 1818 */ 1819 if (cpu->mp_affinity == ARM64_AFFINITY_INVALID) { 1820 cpu->mp_affinity = arm_cpu_mp_affinity(cs->cpu_index, 1821 ARM_DEFAULT_CPUS_PER_CLUSTER); 1822 } 1823 1824 if (cpu->reset_hivecs) { 1825 cpu->reset_sctlr |= (1 << 13); 1826 } 1827 1828 if (cpu->cfgend) { 1829 if (arm_feature(&cpu->env, ARM_FEATURE_V7)) { 1830 cpu->reset_sctlr |= SCTLR_EE; 1831 } else { 1832 cpu->reset_sctlr |= SCTLR_B; 1833 } 1834 } 1835 1836 if (!arm_feature(env, ARM_FEATURE_M) && !cpu->has_el3) { 1837 /* If the has_el3 CPU property is disabled then we need to disable the 1838 * feature. 1839 */ 1840 unset_feature(env, ARM_FEATURE_EL3); 1841 1842 /* 1843 * Disable the security extension feature bits in the processor 1844 * feature registers as well. 1845 */ 1846 cpu->isar.id_pfr1 = FIELD_DP32(cpu->isar.id_pfr1, ID_PFR1, SECURITY, 0); 1847 cpu->isar.id_dfr0 = FIELD_DP32(cpu->isar.id_dfr0, ID_DFR0, COPSDBG, 0); 1848 cpu->isar.id_aa64pfr0 = FIELD_DP64(cpu->isar.id_aa64pfr0, 1849 ID_AA64PFR0, EL3, 0); 1850 } 1851 1852 if (!cpu->has_el2) { 1853 unset_feature(env, ARM_FEATURE_EL2); 1854 } 1855 1856 if (!cpu->has_pmu) { 1857 unset_feature(env, ARM_FEATURE_PMU); 1858 } 1859 if (arm_feature(env, ARM_FEATURE_PMU)) { 1860 pmu_init(cpu); 1861 1862 if (!kvm_enabled()) { 1863 arm_register_pre_el_change_hook(cpu, &pmu_pre_el_change, 0); 1864 arm_register_el_change_hook(cpu, &pmu_post_el_change, 0); 1865 } 1866 1867 #ifndef CONFIG_USER_ONLY 1868 cpu->pmu_timer = timer_new_ns(QEMU_CLOCK_VIRTUAL, arm_pmu_timer_cb, 1869 cpu); 1870 #endif 1871 } else { 1872 cpu->isar.id_aa64dfr0 = 1873 FIELD_DP64(cpu->isar.id_aa64dfr0, ID_AA64DFR0, PMUVER, 0); 1874 cpu->isar.id_dfr0 = FIELD_DP32(cpu->isar.id_dfr0, ID_DFR0, PERFMON, 0); 1875 cpu->pmceid0 = 0; 1876 cpu->pmceid1 = 0; 1877 } 1878 1879 if (!arm_feature(env, ARM_FEATURE_EL2)) { 1880 /* 1881 * Disable the hypervisor feature bits in the processor feature 1882 * registers if we don't have EL2. 1883 */ 1884 cpu->isar.id_aa64pfr0 = FIELD_DP64(cpu->isar.id_aa64pfr0, 1885 ID_AA64PFR0, EL2, 0); 1886 cpu->isar.id_pfr1 = FIELD_DP32(cpu->isar.id_pfr1, 1887 ID_PFR1, VIRTUALIZATION, 0); 1888 } 1889 1890 #ifndef CONFIG_USER_ONLY 1891 if (cpu->tag_memory == NULL && cpu_isar_feature(aa64_mte, cpu)) { 1892 /* 1893 * Disable the MTE feature bits if we do not have tag-memory 1894 * provided by the machine. 1895 */ 1896 cpu->isar.id_aa64pfr1 = 1897 FIELD_DP64(cpu->isar.id_aa64pfr1, ID_AA64PFR1, MTE, 0); 1898 } 1899 #endif 1900 1901 /* MPU can be configured out of a PMSA CPU either by setting has-mpu 1902 * to false or by setting pmsav7-dregion to 0. 1903 */ 1904 if (!cpu->has_mpu) { 1905 cpu->pmsav7_dregion = 0; 1906 } 1907 if (cpu->pmsav7_dregion == 0) { 1908 cpu->has_mpu = false; 1909 } 1910 1911 if (arm_feature(env, ARM_FEATURE_PMSA) && 1912 arm_feature(env, ARM_FEATURE_V7)) { 1913 uint32_t nr = cpu->pmsav7_dregion; 1914 1915 if (nr > 0xff) { 1916 error_setg(errp, "PMSAv7 MPU #regions invalid %" PRIu32, nr); 1917 return; 1918 } 1919 1920 if (nr) { 1921 if (arm_feature(env, ARM_FEATURE_V8)) { 1922 /* PMSAv8 */ 1923 env->pmsav8.rbar[M_REG_NS] = g_new0(uint32_t, nr); 1924 env->pmsav8.rlar[M_REG_NS] = g_new0(uint32_t, nr); 1925 if (arm_feature(env, ARM_FEATURE_M_SECURITY)) { 1926 env->pmsav8.rbar[M_REG_S] = g_new0(uint32_t, nr); 1927 env->pmsav8.rlar[M_REG_S] = g_new0(uint32_t, nr); 1928 } 1929 } else { 1930 env->pmsav7.drbar = g_new0(uint32_t, nr); 1931 env->pmsav7.drsr = g_new0(uint32_t, nr); 1932 env->pmsav7.dracr = g_new0(uint32_t, nr); 1933 } 1934 } 1935 } 1936 1937 if (arm_feature(env, ARM_FEATURE_M_SECURITY)) { 1938 uint32_t nr = cpu->sau_sregion; 1939 1940 if (nr > 0xff) { 1941 error_setg(errp, "v8M SAU #regions invalid %" PRIu32, nr); 1942 return; 1943 } 1944 1945 if (nr) { 1946 env->sau.rbar = g_new0(uint32_t, nr); 1947 env->sau.rlar = g_new0(uint32_t, nr); 1948 } 1949 } 1950 1951 if (arm_feature(env, ARM_FEATURE_EL3)) { 1952 set_feature(env, ARM_FEATURE_VBAR); 1953 } 1954 1955 register_cp_regs_for_features(cpu); 1956 arm_cpu_register_gdb_regs_for_features(cpu); 1957 1958 init_cpreg_list(cpu); 1959 1960 #ifndef CONFIG_USER_ONLY 1961 MachineState *ms = MACHINE(qdev_get_machine()); 1962 unsigned int smp_cpus = ms->smp.cpus; 1963 bool has_secure = cpu->has_el3 || arm_feature(env, ARM_FEATURE_M_SECURITY); 1964 1965 /* 1966 * We must set cs->num_ases to the final value before 1967 * the first call to cpu_address_space_init. 1968 */ 1969 if (cpu->tag_memory != NULL) { 1970 cs->num_ases = 3 + has_secure; 1971 } else { 1972 cs->num_ases = 1 + has_secure; 1973 } 1974 1975 if (has_secure) { 1976 if (!cpu->secure_memory) { 1977 cpu->secure_memory = cs->memory; 1978 } 1979 cpu_address_space_init(cs, ARMASIdx_S, "cpu-secure-memory", 1980 cpu->secure_memory); 1981 } 1982 1983 if (cpu->tag_memory != NULL) { 1984 cpu_address_space_init(cs, ARMASIdx_TagNS, "cpu-tag-memory", 1985 cpu->tag_memory); 1986 if (has_secure) { 1987 cpu_address_space_init(cs, ARMASIdx_TagS, "cpu-tag-memory", 1988 cpu->secure_tag_memory); 1989 } 1990 } 1991 1992 cpu_address_space_init(cs, ARMASIdx_NS, "cpu-memory", cs->memory); 1993 1994 /* No core_count specified, default to smp_cpus. */ 1995 if (cpu->core_count == -1) { 1996 cpu->core_count = smp_cpus; 1997 } 1998 #endif 1999 2000 if (tcg_enabled()) { 2001 int dcz_blocklen = 4 << cpu->dcz_blocksize; 2002 2003 /* 2004 * We only support DCZ blocklen that fits on one page. 2005 * 2006 * Architectually this is always true. However TARGET_PAGE_SIZE 2007 * is variable and, for compatibility with -machine virt-2.7, 2008 * is only 1KiB, as an artifact of legacy ARMv5 subpage support. 2009 * But even then, while the largest architectural DCZ blocklen 2010 * is 2KiB, no cpu actually uses such a large blocklen. 2011 */ 2012 assert(dcz_blocklen <= TARGET_PAGE_SIZE); 2013 2014 /* 2015 * We only support DCZ blocksize >= 2*TAG_GRANULE, which is to say 2016 * both nibbles of each byte storing tag data may be written at once. 2017 * Since TAG_GRANULE is 16, this means that blocklen must be >= 32. 2018 */ 2019 if (cpu_isar_feature(aa64_mte, cpu)) { 2020 assert(dcz_blocklen >= 2 * TAG_GRANULE); 2021 } 2022 } 2023 2024 qemu_init_vcpu(cs); 2025 cpu_reset(cs); 2026 2027 acc->parent_realize(dev, errp); 2028 } 2029 2030 static ObjectClass *arm_cpu_class_by_name(const char *cpu_model) 2031 { 2032 ObjectClass *oc; 2033 char *typename; 2034 char **cpuname; 2035 const char *cpunamestr; 2036 2037 cpuname = g_strsplit(cpu_model, ",", 1); 2038 cpunamestr = cpuname[0]; 2039 #ifdef CONFIG_USER_ONLY 2040 /* For backwards compatibility usermode emulation allows "-cpu any", 2041 * which has the same semantics as "-cpu max". 2042 */ 2043 if (!strcmp(cpunamestr, "any")) { 2044 cpunamestr = "max"; 2045 } 2046 #endif 2047 typename = g_strdup_printf(ARM_CPU_TYPE_NAME("%s"), cpunamestr); 2048 oc = object_class_by_name(typename); 2049 g_strfreev(cpuname); 2050 g_free(typename); 2051 if (!oc || !object_class_dynamic_cast(oc, TYPE_ARM_CPU) || 2052 object_class_is_abstract(oc)) { 2053 return NULL; 2054 } 2055 return oc; 2056 } 2057 2058 static Property arm_cpu_properties[] = { 2059 DEFINE_PROP_UINT64("midr", ARMCPU, midr, 0), 2060 DEFINE_PROP_UINT64("mp-affinity", ARMCPU, 2061 mp_affinity, ARM64_AFFINITY_INVALID), 2062 DEFINE_PROP_INT32("node-id", ARMCPU, node_id, CPU_UNSET_NUMA_NODE_ID), 2063 DEFINE_PROP_INT32("core-count", ARMCPU, core_count, -1), 2064 DEFINE_PROP_END_OF_LIST() 2065 }; 2066 2067 static gchar *arm_gdb_arch_name(CPUState *cs) 2068 { 2069 ARMCPU *cpu = ARM_CPU(cs); 2070 CPUARMState *env = &cpu->env; 2071 2072 if (arm_feature(env, ARM_FEATURE_IWMMXT)) { 2073 return g_strdup("iwmmxt"); 2074 } 2075 return g_strdup("arm"); 2076 } 2077 2078 #ifndef CONFIG_USER_ONLY 2079 #include "hw/core/sysemu-cpu-ops.h" 2080 2081 static const struct SysemuCPUOps arm_sysemu_ops = { 2082 .get_phys_page_attrs_debug = arm_cpu_get_phys_page_attrs_debug, 2083 .asidx_from_attrs = arm_asidx_from_attrs, 2084 .write_elf32_note = arm_cpu_write_elf32_note, 2085 .write_elf64_note = arm_cpu_write_elf64_note, 2086 .virtio_is_big_endian = arm_cpu_virtio_is_big_endian, 2087 .legacy_vmsd = &vmstate_arm_cpu, 2088 }; 2089 #endif 2090 2091 #ifdef CONFIG_TCG 2092 static const struct TCGCPUOps arm_tcg_ops = { 2093 .initialize = arm_translate_init, 2094 .synchronize_from_tb = arm_cpu_synchronize_from_tb, 2095 .debug_excp_handler = arm_debug_excp_handler, 2096 2097 #ifdef CONFIG_USER_ONLY 2098 .record_sigsegv = arm_cpu_record_sigsegv, 2099 .record_sigbus = arm_cpu_record_sigbus, 2100 #else 2101 .tlb_fill = arm_cpu_tlb_fill, 2102 .cpu_exec_interrupt = arm_cpu_exec_interrupt, 2103 .do_interrupt = arm_cpu_do_interrupt, 2104 .do_transaction_failed = arm_cpu_do_transaction_failed, 2105 .do_unaligned_access = arm_cpu_do_unaligned_access, 2106 .adjust_watchpoint_address = arm_adjust_watchpoint_address, 2107 .debug_check_watchpoint = arm_debug_check_watchpoint, 2108 .debug_check_breakpoint = arm_debug_check_breakpoint, 2109 #endif /* !CONFIG_USER_ONLY */ 2110 }; 2111 #endif /* CONFIG_TCG */ 2112 2113 static void arm_cpu_class_init(ObjectClass *oc, void *data) 2114 { 2115 ARMCPUClass *acc = ARM_CPU_CLASS(oc); 2116 CPUClass *cc = CPU_CLASS(acc); 2117 DeviceClass *dc = DEVICE_CLASS(oc); 2118 2119 device_class_set_parent_realize(dc, arm_cpu_realizefn, 2120 &acc->parent_realize); 2121 2122 device_class_set_props(dc, arm_cpu_properties); 2123 device_class_set_parent_reset(dc, arm_cpu_reset, &acc->parent_reset); 2124 2125 cc->class_by_name = arm_cpu_class_by_name; 2126 cc->has_work = arm_cpu_has_work; 2127 cc->dump_state = arm_cpu_dump_state; 2128 cc->set_pc = arm_cpu_set_pc; 2129 cc->gdb_read_register = arm_cpu_gdb_read_register; 2130 cc->gdb_write_register = arm_cpu_gdb_write_register; 2131 #ifndef CONFIG_USER_ONLY 2132 cc->sysemu_ops = &arm_sysemu_ops; 2133 #endif 2134 cc->gdb_num_core_regs = 26; 2135 cc->gdb_core_xml_file = "arm-core.xml"; 2136 cc->gdb_arch_name = arm_gdb_arch_name; 2137 cc->gdb_get_dynamic_xml = arm_gdb_get_dynamic_xml; 2138 cc->gdb_stop_before_watchpoint = true; 2139 cc->disas_set_info = arm_disas_set_info; 2140 2141 #ifdef CONFIG_TCG 2142 cc->tcg_ops = &arm_tcg_ops; 2143 #endif /* CONFIG_TCG */ 2144 } 2145 2146 static void arm_cpu_instance_init(Object *obj) 2147 { 2148 ARMCPUClass *acc = ARM_CPU_GET_CLASS(obj); 2149 2150 acc->info->initfn(obj); 2151 arm_cpu_post_init(obj); 2152 } 2153 2154 static void cpu_register_class_init(ObjectClass *oc, void *data) 2155 { 2156 ARMCPUClass *acc = ARM_CPU_CLASS(oc); 2157 2158 acc->info = data; 2159 } 2160 2161 void arm_cpu_register(const ARMCPUInfo *info) 2162 { 2163 TypeInfo type_info = { 2164 .parent = TYPE_ARM_CPU, 2165 .instance_size = sizeof(ARMCPU), 2166 .instance_align = __alignof__(ARMCPU), 2167 .instance_init = arm_cpu_instance_init, 2168 .class_size = sizeof(ARMCPUClass), 2169 .class_init = info->class_init ?: cpu_register_class_init, 2170 .class_data = (void *)info, 2171 }; 2172 2173 type_info.name = g_strdup_printf("%s-" TYPE_ARM_CPU, info->name); 2174 type_register(&type_info); 2175 g_free((void *)type_info.name); 2176 } 2177 2178 static const TypeInfo arm_cpu_type_info = { 2179 .name = TYPE_ARM_CPU, 2180 .parent = TYPE_CPU, 2181 .instance_size = sizeof(ARMCPU), 2182 .instance_align = __alignof__(ARMCPU), 2183 .instance_init = arm_cpu_initfn, 2184 .instance_finalize = arm_cpu_finalizefn, 2185 .abstract = true, 2186 .class_size = sizeof(ARMCPUClass), 2187 .class_init = arm_cpu_class_init, 2188 }; 2189 2190 static void arm_cpu_register_types(void) 2191 { 2192 type_register_static(&arm_cpu_type_info); 2193 } 2194 2195 type_init(arm_cpu_register_types) 2196