1 /* 2 * QEMU ARM CPU 3 * 4 * Copyright (c) 2012 SUSE LINUX Products GmbH 5 * 6 * This program is free software; you can redistribute it and/or 7 * modify it under the terms of the GNU General Public License 8 * as published by the Free Software Foundation; either version 2 9 * of the License, or (at your option) any later version. 10 * 11 * This program is distributed in the hope that it will be useful, 12 * but WITHOUT ANY WARRANTY; without even the implied warranty of 13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 14 * GNU General Public License for more details. 15 * 16 * You should have received a copy of the GNU General Public License 17 * along with this program; if not, see 18 * <http://www.gnu.org/licenses/gpl-2.0.html> 19 */ 20 21 #include "qemu/osdep.h" 22 #include "qemu/qemu-print.h" 23 #include "qemu/timer.h" 24 #include "qemu/log.h" 25 #include "exec/page-vary.h" 26 #include "target/arm/idau.h" 27 #include "qemu/module.h" 28 #include "qapi/error.h" 29 #include "cpu.h" 30 #ifdef CONFIG_TCG 31 #include "hw/core/tcg-cpu-ops.h" 32 #endif /* CONFIG_TCG */ 33 #include "internals.h" 34 #include "exec/exec-all.h" 35 #include "hw/qdev-properties.h" 36 #if !defined(CONFIG_USER_ONLY) 37 #include "hw/loader.h" 38 #include "hw/boards.h" 39 #ifdef CONFIG_TCG 40 #include "hw/intc/armv7m_nvic.h" 41 #endif /* CONFIG_TCG */ 42 #endif /* !CONFIG_USER_ONLY */ 43 #include "sysemu/tcg.h" 44 #include "sysemu/qtest.h" 45 #include "sysemu/hw_accel.h" 46 #include "kvm_arm.h" 47 #include "disas/capstone.h" 48 #include "fpu/softfloat.h" 49 #include "cpregs.h" 50 51 static void arm_cpu_set_pc(CPUState *cs, vaddr value) 52 { 53 ARMCPU *cpu = ARM_CPU(cs); 54 CPUARMState *env = &cpu->env; 55 56 if (is_a64(env)) { 57 env->pc = value; 58 env->thumb = false; 59 } else { 60 env->regs[15] = value & ~1; 61 env->thumb = value & 1; 62 } 63 } 64 65 static vaddr arm_cpu_get_pc(CPUState *cs) 66 { 67 ARMCPU *cpu = ARM_CPU(cs); 68 CPUARMState *env = &cpu->env; 69 70 if (is_a64(env)) { 71 return env->pc; 72 } else { 73 return env->regs[15]; 74 } 75 } 76 77 #ifdef CONFIG_TCG 78 void arm_cpu_synchronize_from_tb(CPUState *cs, 79 const TranslationBlock *tb) 80 { 81 /* The program counter is always up to date with CF_PCREL. */ 82 if (!(tb_cflags(tb) & CF_PCREL)) { 83 CPUARMState *env = cs->env_ptr; 84 /* 85 * It's OK to look at env for the current mode here, because it's 86 * never possible for an AArch64 TB to chain to an AArch32 TB. 87 */ 88 if (is_a64(env)) { 89 env->pc = tb->pc; 90 } else { 91 env->regs[15] = tb->pc; 92 } 93 } 94 } 95 96 void arm_restore_state_to_opc(CPUState *cs, 97 const TranslationBlock *tb, 98 const uint64_t *data) 99 { 100 CPUARMState *env = cs->env_ptr; 101 102 if (is_a64(env)) { 103 if (tb_cflags(tb) & CF_PCREL) { 104 env->pc = (env->pc & TARGET_PAGE_MASK) | data[0]; 105 } else { 106 env->pc = data[0]; 107 } 108 env->condexec_bits = 0; 109 env->exception.syndrome = data[2] << ARM_INSN_START_WORD2_SHIFT; 110 } else { 111 if (tb_cflags(tb) & CF_PCREL) { 112 env->regs[15] = (env->regs[15] & TARGET_PAGE_MASK) | data[0]; 113 } else { 114 env->regs[15] = data[0]; 115 } 116 env->condexec_bits = data[1]; 117 env->exception.syndrome = data[2] << ARM_INSN_START_WORD2_SHIFT; 118 } 119 } 120 #endif /* CONFIG_TCG */ 121 122 static bool arm_cpu_has_work(CPUState *cs) 123 { 124 ARMCPU *cpu = ARM_CPU(cs); 125 126 return (cpu->power_state != PSCI_OFF) 127 && cs->interrupt_request & 128 (CPU_INTERRUPT_FIQ | CPU_INTERRUPT_HARD 129 | CPU_INTERRUPT_VFIQ | CPU_INTERRUPT_VIRQ | CPU_INTERRUPT_VSERR 130 | CPU_INTERRUPT_EXITTB); 131 } 132 133 void arm_register_pre_el_change_hook(ARMCPU *cpu, ARMELChangeHookFn *hook, 134 void *opaque) 135 { 136 ARMELChangeHook *entry = g_new0(ARMELChangeHook, 1); 137 138 entry->hook = hook; 139 entry->opaque = opaque; 140 141 QLIST_INSERT_HEAD(&cpu->pre_el_change_hooks, entry, node); 142 } 143 144 void arm_register_el_change_hook(ARMCPU *cpu, ARMELChangeHookFn *hook, 145 void *opaque) 146 { 147 ARMELChangeHook *entry = g_new0(ARMELChangeHook, 1); 148 149 entry->hook = hook; 150 entry->opaque = opaque; 151 152 QLIST_INSERT_HEAD(&cpu->el_change_hooks, entry, node); 153 } 154 155 static void cp_reg_reset(gpointer key, gpointer value, gpointer opaque) 156 { 157 /* Reset a single ARMCPRegInfo register */ 158 ARMCPRegInfo *ri = value; 159 ARMCPU *cpu = opaque; 160 161 if (ri->type & (ARM_CP_SPECIAL_MASK | ARM_CP_ALIAS)) { 162 return; 163 } 164 165 if (ri->resetfn) { 166 ri->resetfn(&cpu->env, ri); 167 return; 168 } 169 170 /* A zero offset is never possible as it would be regs[0] 171 * so we use it to indicate that reset is being handled elsewhere. 172 * This is basically only used for fields in non-core coprocessors 173 * (like the pxa2xx ones). 174 */ 175 if (!ri->fieldoffset) { 176 return; 177 } 178 179 if (cpreg_field_is_64bit(ri)) { 180 CPREG_FIELD64(&cpu->env, ri) = ri->resetvalue; 181 } else { 182 CPREG_FIELD32(&cpu->env, ri) = ri->resetvalue; 183 } 184 } 185 186 static void cp_reg_check_reset(gpointer key, gpointer value, gpointer opaque) 187 { 188 /* Purely an assertion check: we've already done reset once, 189 * so now check that running the reset for the cpreg doesn't 190 * change its value. This traps bugs where two different cpregs 191 * both try to reset the same state field but to different values. 192 */ 193 ARMCPRegInfo *ri = value; 194 ARMCPU *cpu = opaque; 195 uint64_t oldvalue, newvalue; 196 197 if (ri->type & (ARM_CP_SPECIAL_MASK | ARM_CP_ALIAS | ARM_CP_NO_RAW)) { 198 return; 199 } 200 201 oldvalue = read_raw_cp_reg(&cpu->env, ri); 202 cp_reg_reset(key, value, opaque); 203 newvalue = read_raw_cp_reg(&cpu->env, ri); 204 assert(oldvalue == newvalue); 205 } 206 207 static void arm_cpu_reset_hold(Object *obj) 208 { 209 CPUState *s = CPU(obj); 210 ARMCPU *cpu = ARM_CPU(s); 211 ARMCPUClass *acc = ARM_CPU_GET_CLASS(cpu); 212 CPUARMState *env = &cpu->env; 213 214 if (acc->parent_phases.hold) { 215 acc->parent_phases.hold(obj); 216 } 217 218 memset(env, 0, offsetof(CPUARMState, end_reset_fields)); 219 220 g_hash_table_foreach(cpu->cp_regs, cp_reg_reset, cpu); 221 g_hash_table_foreach(cpu->cp_regs, cp_reg_check_reset, cpu); 222 223 env->vfp.xregs[ARM_VFP_FPSID] = cpu->reset_fpsid; 224 env->vfp.xregs[ARM_VFP_MVFR0] = cpu->isar.mvfr0; 225 env->vfp.xregs[ARM_VFP_MVFR1] = cpu->isar.mvfr1; 226 env->vfp.xregs[ARM_VFP_MVFR2] = cpu->isar.mvfr2; 227 228 cpu->power_state = s->start_powered_off ? PSCI_OFF : PSCI_ON; 229 230 if (arm_feature(env, ARM_FEATURE_IWMMXT)) { 231 env->iwmmxt.cregs[ARM_IWMMXT_wCID] = 0x69051000 | 'Q'; 232 } 233 234 if (arm_feature(env, ARM_FEATURE_AARCH64)) { 235 /* 64 bit CPUs always start in 64 bit mode */ 236 env->aarch64 = true; 237 #if defined(CONFIG_USER_ONLY) 238 env->pstate = PSTATE_MODE_EL0t; 239 /* Userspace expects access to DC ZVA, CTL_EL0 and the cache ops */ 240 env->cp15.sctlr_el[1] |= SCTLR_UCT | SCTLR_UCI | SCTLR_DZE; 241 /* Enable all PAC keys. */ 242 env->cp15.sctlr_el[1] |= (SCTLR_EnIA | SCTLR_EnIB | 243 SCTLR_EnDA | SCTLR_EnDB); 244 /* Trap on btype=3 for PACIxSP. */ 245 env->cp15.sctlr_el[1] |= SCTLR_BT0; 246 /* Trap on implementation defined registers. */ 247 if (cpu_isar_feature(aa64_tidcp1, cpu)) { 248 env->cp15.sctlr_el[1] |= SCTLR_TIDCP; 249 } 250 /* and to the FP/Neon instructions */ 251 env->cp15.cpacr_el1 = FIELD_DP64(env->cp15.cpacr_el1, 252 CPACR_EL1, FPEN, 3); 253 /* and to the SVE instructions, with default vector length */ 254 if (cpu_isar_feature(aa64_sve, cpu)) { 255 env->cp15.cpacr_el1 = FIELD_DP64(env->cp15.cpacr_el1, 256 CPACR_EL1, ZEN, 3); 257 env->vfp.zcr_el[1] = cpu->sve_default_vq - 1; 258 } 259 /* and for SME instructions, with default vector length, and TPIDR2 */ 260 if (cpu_isar_feature(aa64_sme, cpu)) { 261 env->cp15.sctlr_el[1] |= SCTLR_EnTP2; 262 env->cp15.cpacr_el1 = FIELD_DP64(env->cp15.cpacr_el1, 263 CPACR_EL1, SMEN, 3); 264 env->vfp.smcr_el[1] = cpu->sme_default_vq - 1; 265 if (cpu_isar_feature(aa64_sme_fa64, cpu)) { 266 env->vfp.smcr_el[1] = FIELD_DP64(env->vfp.smcr_el[1], 267 SMCR, FA64, 1); 268 } 269 } 270 /* 271 * Enable 48-bit address space (TODO: take reserved_va into account). 272 * Enable TBI0 but not TBI1. 273 * Note that this must match useronly_clean_ptr. 274 */ 275 env->cp15.tcr_el[1] = 5 | (1ULL << 37); 276 277 /* Enable MTE */ 278 if (cpu_isar_feature(aa64_mte, cpu)) { 279 /* Enable tag access, but leave TCF0 as No Effect (0). */ 280 env->cp15.sctlr_el[1] |= SCTLR_ATA0; 281 /* 282 * Exclude all tags, so that tag 0 is always used. 283 * This corresponds to Linux current->thread.gcr_incl = 0. 284 * 285 * Set RRND, so that helper_irg() will generate a seed later. 286 * Here in cpu_reset(), the crypto subsystem has not yet been 287 * initialized. 288 */ 289 env->cp15.gcr_el1 = 0x1ffff; 290 } 291 /* 292 * Disable access to SCXTNUM_EL0 from CSV2_1p2. 293 * This is not yet exposed from the Linux kernel in any way. 294 */ 295 env->cp15.sctlr_el[1] |= SCTLR_TSCXT; 296 /* Disable access to Debug Communication Channel (DCC). */ 297 env->cp15.mdscr_el1 |= 1 << 12; 298 #else 299 /* Reset into the highest available EL */ 300 if (arm_feature(env, ARM_FEATURE_EL3)) { 301 env->pstate = PSTATE_MODE_EL3h; 302 } else if (arm_feature(env, ARM_FEATURE_EL2)) { 303 env->pstate = PSTATE_MODE_EL2h; 304 } else { 305 env->pstate = PSTATE_MODE_EL1h; 306 } 307 308 /* Sample rvbar at reset. */ 309 env->cp15.rvbar = cpu->rvbar_prop; 310 env->pc = env->cp15.rvbar; 311 #endif 312 } else { 313 #if defined(CONFIG_USER_ONLY) 314 /* Userspace expects access to cp10 and cp11 for FP/Neon */ 315 env->cp15.cpacr_el1 = FIELD_DP64(env->cp15.cpacr_el1, 316 CPACR, CP10, 3); 317 env->cp15.cpacr_el1 = FIELD_DP64(env->cp15.cpacr_el1, 318 CPACR, CP11, 3); 319 #endif 320 if (arm_feature(env, ARM_FEATURE_V8)) { 321 env->cp15.rvbar = cpu->rvbar_prop; 322 env->regs[15] = cpu->rvbar_prop; 323 } 324 } 325 326 #if defined(CONFIG_USER_ONLY) 327 env->uncached_cpsr = ARM_CPU_MODE_USR; 328 /* For user mode we must enable access to coprocessors */ 329 env->vfp.xregs[ARM_VFP_FPEXC] = 1 << 30; 330 if (arm_feature(env, ARM_FEATURE_IWMMXT)) { 331 env->cp15.c15_cpar = 3; 332 } else if (arm_feature(env, ARM_FEATURE_XSCALE)) { 333 env->cp15.c15_cpar = 1; 334 } 335 #else 336 337 /* 338 * If the highest available EL is EL2, AArch32 will start in Hyp 339 * mode; otherwise it starts in SVC. Note that if we start in 340 * AArch64 then these values in the uncached_cpsr will be ignored. 341 */ 342 if (arm_feature(env, ARM_FEATURE_EL2) && 343 !arm_feature(env, ARM_FEATURE_EL3)) { 344 env->uncached_cpsr = ARM_CPU_MODE_HYP; 345 } else { 346 env->uncached_cpsr = ARM_CPU_MODE_SVC; 347 } 348 env->daif = PSTATE_D | PSTATE_A | PSTATE_I | PSTATE_F; 349 350 /* AArch32 has a hard highvec setting of 0xFFFF0000. If we are currently 351 * executing as AArch32 then check if highvecs are enabled and 352 * adjust the PC accordingly. 353 */ 354 if (A32_BANKED_CURRENT_REG_GET(env, sctlr) & SCTLR_V) { 355 env->regs[15] = 0xFFFF0000; 356 } 357 358 env->vfp.xregs[ARM_VFP_FPEXC] = 0; 359 #endif 360 361 if (arm_feature(env, ARM_FEATURE_M)) { 362 #ifndef CONFIG_USER_ONLY 363 uint32_t initial_msp; /* Loaded from 0x0 */ 364 uint32_t initial_pc; /* Loaded from 0x4 */ 365 uint8_t *rom; 366 uint32_t vecbase; 367 #endif 368 369 if (cpu_isar_feature(aa32_lob, cpu)) { 370 /* 371 * LTPSIZE is constant 4 if MVE not implemented, and resets 372 * to an UNKNOWN value if MVE is implemented. We choose to 373 * always reset to 4. 374 */ 375 env->v7m.ltpsize = 4; 376 /* The LTPSIZE field in FPDSCR is constant and reads as 4. */ 377 env->v7m.fpdscr[M_REG_NS] = 4 << FPCR_LTPSIZE_SHIFT; 378 env->v7m.fpdscr[M_REG_S] = 4 << FPCR_LTPSIZE_SHIFT; 379 } 380 381 if (arm_feature(env, ARM_FEATURE_M_SECURITY)) { 382 env->v7m.secure = true; 383 } else { 384 /* This bit resets to 0 if security is supported, but 1 if 385 * it is not. The bit is not present in v7M, but we set it 386 * here so we can avoid having to make checks on it conditional 387 * on ARM_FEATURE_V8 (we don't let the guest see the bit). 388 */ 389 env->v7m.aircr = R_V7M_AIRCR_BFHFNMINS_MASK; 390 /* 391 * Set NSACR to indicate "NS access permitted to everything"; 392 * this avoids having to have all the tests of it being 393 * conditional on ARM_FEATURE_M_SECURITY. Note also that from 394 * v8.1M the guest-visible value of NSACR in a CPU without the 395 * Security Extension is 0xcff. 396 */ 397 env->v7m.nsacr = 0xcff; 398 } 399 400 /* In v7M the reset value of this bit is IMPDEF, but ARM recommends 401 * that it resets to 1, so QEMU always does that rather than making 402 * it dependent on CPU model. In v8M it is RES1. 403 */ 404 env->v7m.ccr[M_REG_NS] = R_V7M_CCR_STKALIGN_MASK; 405 env->v7m.ccr[M_REG_S] = R_V7M_CCR_STKALIGN_MASK; 406 if (arm_feature(env, ARM_FEATURE_V8)) { 407 /* in v8M the NONBASETHRDENA bit [0] is RES1 */ 408 env->v7m.ccr[M_REG_NS] |= R_V7M_CCR_NONBASETHRDENA_MASK; 409 env->v7m.ccr[M_REG_S] |= R_V7M_CCR_NONBASETHRDENA_MASK; 410 } 411 if (!arm_feature(env, ARM_FEATURE_M_MAIN)) { 412 env->v7m.ccr[M_REG_NS] |= R_V7M_CCR_UNALIGN_TRP_MASK; 413 env->v7m.ccr[M_REG_S] |= R_V7M_CCR_UNALIGN_TRP_MASK; 414 } 415 416 if (cpu_isar_feature(aa32_vfp_simd, cpu)) { 417 env->v7m.fpccr[M_REG_NS] = R_V7M_FPCCR_ASPEN_MASK; 418 env->v7m.fpccr[M_REG_S] = R_V7M_FPCCR_ASPEN_MASK | 419 R_V7M_FPCCR_LSPEN_MASK | R_V7M_FPCCR_S_MASK; 420 } 421 422 #ifndef CONFIG_USER_ONLY 423 /* Unlike A/R profile, M profile defines the reset LR value */ 424 env->regs[14] = 0xffffffff; 425 426 env->v7m.vecbase[M_REG_S] = cpu->init_svtor & 0xffffff80; 427 env->v7m.vecbase[M_REG_NS] = cpu->init_nsvtor & 0xffffff80; 428 429 /* Load the initial SP and PC from offset 0 and 4 in the vector table */ 430 vecbase = env->v7m.vecbase[env->v7m.secure]; 431 rom = rom_ptr_for_as(s->as, vecbase, 8); 432 if (rom) { 433 /* Address zero is covered by ROM which hasn't yet been 434 * copied into physical memory. 435 */ 436 initial_msp = ldl_p(rom); 437 initial_pc = ldl_p(rom + 4); 438 } else { 439 /* Address zero not covered by a ROM blob, or the ROM blob 440 * is in non-modifiable memory and this is a second reset after 441 * it got copied into memory. In the latter case, rom_ptr 442 * will return a NULL pointer and we should use ldl_phys instead. 443 */ 444 initial_msp = ldl_phys(s->as, vecbase); 445 initial_pc = ldl_phys(s->as, vecbase + 4); 446 } 447 448 qemu_log_mask(CPU_LOG_INT, 449 "Loaded reset SP 0x%x PC 0x%x from vector table\n", 450 initial_msp, initial_pc); 451 452 env->regs[13] = initial_msp & 0xFFFFFFFC; 453 env->regs[15] = initial_pc & ~1; 454 env->thumb = initial_pc & 1; 455 #else 456 /* 457 * For user mode we run non-secure and with access to the FPU. 458 * The FPU context is active (ie does not need further setup) 459 * and is owned by non-secure. 460 */ 461 env->v7m.secure = false; 462 env->v7m.nsacr = 0xcff; 463 env->v7m.cpacr[M_REG_NS] = 0xf0ffff; 464 env->v7m.fpccr[M_REG_S] &= 465 ~(R_V7M_FPCCR_LSPEN_MASK | R_V7M_FPCCR_S_MASK); 466 env->v7m.control[M_REG_S] |= R_V7M_CONTROL_FPCA_MASK; 467 #endif 468 } 469 470 /* M profile requires that reset clears the exclusive monitor; 471 * A profile does not, but clearing it makes more sense than having it 472 * set with an exclusive access on address zero. 473 */ 474 arm_clear_exclusive(env); 475 476 if (arm_feature(env, ARM_FEATURE_PMSA)) { 477 if (cpu->pmsav7_dregion > 0) { 478 if (arm_feature(env, ARM_FEATURE_V8)) { 479 memset(env->pmsav8.rbar[M_REG_NS], 0, 480 sizeof(*env->pmsav8.rbar[M_REG_NS]) 481 * cpu->pmsav7_dregion); 482 memset(env->pmsav8.rlar[M_REG_NS], 0, 483 sizeof(*env->pmsav8.rlar[M_REG_NS]) 484 * cpu->pmsav7_dregion); 485 if (arm_feature(env, ARM_FEATURE_M_SECURITY)) { 486 memset(env->pmsav8.rbar[M_REG_S], 0, 487 sizeof(*env->pmsav8.rbar[M_REG_S]) 488 * cpu->pmsav7_dregion); 489 memset(env->pmsav8.rlar[M_REG_S], 0, 490 sizeof(*env->pmsav8.rlar[M_REG_S]) 491 * cpu->pmsav7_dregion); 492 } 493 } else if (arm_feature(env, ARM_FEATURE_V7)) { 494 memset(env->pmsav7.drbar, 0, 495 sizeof(*env->pmsav7.drbar) * cpu->pmsav7_dregion); 496 memset(env->pmsav7.drsr, 0, 497 sizeof(*env->pmsav7.drsr) * cpu->pmsav7_dregion); 498 memset(env->pmsav7.dracr, 0, 499 sizeof(*env->pmsav7.dracr) * cpu->pmsav7_dregion); 500 } 501 } 502 503 if (cpu->pmsav8r_hdregion > 0) { 504 memset(env->pmsav8.hprbar, 0, 505 sizeof(*env->pmsav8.hprbar) * cpu->pmsav8r_hdregion); 506 memset(env->pmsav8.hprlar, 0, 507 sizeof(*env->pmsav8.hprlar) * cpu->pmsav8r_hdregion); 508 } 509 510 env->pmsav7.rnr[M_REG_NS] = 0; 511 env->pmsav7.rnr[M_REG_S] = 0; 512 env->pmsav8.mair0[M_REG_NS] = 0; 513 env->pmsav8.mair0[M_REG_S] = 0; 514 env->pmsav8.mair1[M_REG_NS] = 0; 515 env->pmsav8.mair1[M_REG_S] = 0; 516 } 517 518 if (arm_feature(env, ARM_FEATURE_M_SECURITY)) { 519 if (cpu->sau_sregion > 0) { 520 memset(env->sau.rbar, 0, sizeof(*env->sau.rbar) * cpu->sau_sregion); 521 memset(env->sau.rlar, 0, sizeof(*env->sau.rlar) * cpu->sau_sregion); 522 } 523 env->sau.rnr = 0; 524 /* SAU_CTRL reset value is IMPDEF; we choose 0, which is what 525 * the Cortex-M33 does. 526 */ 527 env->sau.ctrl = 0; 528 } 529 530 set_flush_to_zero(1, &env->vfp.standard_fp_status); 531 set_flush_inputs_to_zero(1, &env->vfp.standard_fp_status); 532 set_default_nan_mode(1, &env->vfp.standard_fp_status); 533 set_default_nan_mode(1, &env->vfp.standard_fp_status_f16); 534 set_float_detect_tininess(float_tininess_before_rounding, 535 &env->vfp.fp_status); 536 set_float_detect_tininess(float_tininess_before_rounding, 537 &env->vfp.standard_fp_status); 538 set_float_detect_tininess(float_tininess_before_rounding, 539 &env->vfp.fp_status_f16); 540 set_float_detect_tininess(float_tininess_before_rounding, 541 &env->vfp.standard_fp_status_f16); 542 #ifndef CONFIG_USER_ONLY 543 if (kvm_enabled()) { 544 kvm_arm_reset_vcpu(cpu); 545 } 546 #endif 547 548 if (tcg_enabled()) { 549 hw_breakpoint_update_all(cpu); 550 hw_watchpoint_update_all(cpu); 551 552 arm_rebuild_hflags(env); 553 } 554 } 555 556 #if defined(CONFIG_TCG) && !defined(CONFIG_USER_ONLY) 557 558 static inline bool arm_excp_unmasked(CPUState *cs, unsigned int excp_idx, 559 unsigned int target_el, 560 unsigned int cur_el, bool secure, 561 uint64_t hcr_el2) 562 { 563 CPUARMState *env = cs->env_ptr; 564 bool pstate_unmasked; 565 bool unmasked = false; 566 567 /* 568 * Don't take exceptions if they target a lower EL. 569 * This check should catch any exceptions that would not be taken 570 * but left pending. 571 */ 572 if (cur_el > target_el) { 573 return false; 574 } 575 576 switch (excp_idx) { 577 case EXCP_FIQ: 578 pstate_unmasked = !(env->daif & PSTATE_F); 579 break; 580 581 case EXCP_IRQ: 582 pstate_unmasked = !(env->daif & PSTATE_I); 583 break; 584 585 case EXCP_VFIQ: 586 if (!(hcr_el2 & HCR_FMO) || (hcr_el2 & HCR_TGE)) { 587 /* VFIQs are only taken when hypervized. */ 588 return false; 589 } 590 return !(env->daif & PSTATE_F); 591 case EXCP_VIRQ: 592 if (!(hcr_el2 & HCR_IMO) || (hcr_el2 & HCR_TGE)) { 593 /* VIRQs are only taken when hypervized. */ 594 return false; 595 } 596 return !(env->daif & PSTATE_I); 597 case EXCP_VSERR: 598 if (!(hcr_el2 & HCR_AMO) || (hcr_el2 & HCR_TGE)) { 599 /* VIRQs are only taken when hypervized. */ 600 return false; 601 } 602 return !(env->daif & PSTATE_A); 603 default: 604 g_assert_not_reached(); 605 } 606 607 /* 608 * Use the target EL, current execution state and SCR/HCR settings to 609 * determine whether the corresponding CPSR bit is used to mask the 610 * interrupt. 611 */ 612 if ((target_el > cur_el) && (target_el != 1)) { 613 /* Exceptions targeting a higher EL may not be maskable */ 614 if (arm_feature(env, ARM_FEATURE_AARCH64)) { 615 switch (target_el) { 616 case 2: 617 /* 618 * According to ARM DDI 0487H.a, an interrupt can be masked 619 * when HCR_E2H and HCR_TGE are both set regardless of the 620 * current Security state. Note that we need to revisit this 621 * part again once we need to support NMI. 622 */ 623 if ((hcr_el2 & (HCR_E2H | HCR_TGE)) != (HCR_E2H | HCR_TGE)) { 624 unmasked = true; 625 } 626 break; 627 case 3: 628 /* Interrupt cannot be masked when the target EL is 3 */ 629 unmasked = true; 630 break; 631 default: 632 g_assert_not_reached(); 633 } 634 } else { 635 /* 636 * The old 32-bit-only environment has a more complicated 637 * masking setup. HCR and SCR bits not only affect interrupt 638 * routing but also change the behaviour of masking. 639 */ 640 bool hcr, scr; 641 642 switch (excp_idx) { 643 case EXCP_FIQ: 644 /* 645 * If FIQs are routed to EL3 or EL2 then there are cases where 646 * we override the CPSR.F in determining if the exception is 647 * masked or not. If neither of these are set then we fall back 648 * to the CPSR.F setting otherwise we further assess the state 649 * below. 650 */ 651 hcr = hcr_el2 & HCR_FMO; 652 scr = (env->cp15.scr_el3 & SCR_FIQ); 653 654 /* 655 * When EL3 is 32-bit, the SCR.FW bit controls whether the 656 * CPSR.F bit masks FIQ interrupts when taken in non-secure 657 * state. If SCR.FW is set then FIQs can be masked by CPSR.F 658 * when non-secure but only when FIQs are only routed to EL3. 659 */ 660 scr = scr && !((env->cp15.scr_el3 & SCR_FW) && !hcr); 661 break; 662 case EXCP_IRQ: 663 /* 664 * When EL3 execution state is 32-bit, if HCR.IMO is set then 665 * we may override the CPSR.I masking when in non-secure state. 666 * The SCR.IRQ setting has already been taken into consideration 667 * when setting the target EL, so it does not have a further 668 * affect here. 669 */ 670 hcr = hcr_el2 & HCR_IMO; 671 scr = false; 672 break; 673 default: 674 g_assert_not_reached(); 675 } 676 677 if ((scr || hcr) && !secure) { 678 unmasked = true; 679 } 680 } 681 } 682 683 /* 684 * The PSTATE bits only mask the interrupt if we have not overridden the 685 * ability above. 686 */ 687 return unmasked || pstate_unmasked; 688 } 689 690 static bool arm_cpu_exec_interrupt(CPUState *cs, int interrupt_request) 691 { 692 CPUClass *cc = CPU_GET_CLASS(cs); 693 CPUARMState *env = cs->env_ptr; 694 uint32_t cur_el = arm_current_el(env); 695 bool secure = arm_is_secure(env); 696 uint64_t hcr_el2 = arm_hcr_el2_eff(env); 697 uint32_t target_el; 698 uint32_t excp_idx; 699 700 /* The prioritization of interrupts is IMPLEMENTATION DEFINED. */ 701 702 if (interrupt_request & CPU_INTERRUPT_FIQ) { 703 excp_idx = EXCP_FIQ; 704 target_el = arm_phys_excp_target_el(cs, excp_idx, cur_el, secure); 705 if (arm_excp_unmasked(cs, excp_idx, target_el, 706 cur_el, secure, hcr_el2)) { 707 goto found; 708 } 709 } 710 if (interrupt_request & CPU_INTERRUPT_HARD) { 711 excp_idx = EXCP_IRQ; 712 target_el = arm_phys_excp_target_el(cs, excp_idx, cur_el, secure); 713 if (arm_excp_unmasked(cs, excp_idx, target_el, 714 cur_el, secure, hcr_el2)) { 715 goto found; 716 } 717 } 718 if (interrupt_request & CPU_INTERRUPT_VIRQ) { 719 excp_idx = EXCP_VIRQ; 720 target_el = 1; 721 if (arm_excp_unmasked(cs, excp_idx, target_el, 722 cur_el, secure, hcr_el2)) { 723 goto found; 724 } 725 } 726 if (interrupt_request & CPU_INTERRUPT_VFIQ) { 727 excp_idx = EXCP_VFIQ; 728 target_el = 1; 729 if (arm_excp_unmasked(cs, excp_idx, target_el, 730 cur_el, secure, hcr_el2)) { 731 goto found; 732 } 733 } 734 if (interrupt_request & CPU_INTERRUPT_VSERR) { 735 excp_idx = EXCP_VSERR; 736 target_el = 1; 737 if (arm_excp_unmasked(cs, excp_idx, target_el, 738 cur_el, secure, hcr_el2)) { 739 /* Taking a virtual abort clears HCR_EL2.VSE */ 740 env->cp15.hcr_el2 &= ~HCR_VSE; 741 cpu_reset_interrupt(cs, CPU_INTERRUPT_VSERR); 742 goto found; 743 } 744 } 745 return false; 746 747 found: 748 cs->exception_index = excp_idx; 749 env->exception.target_el = target_el; 750 cc->tcg_ops->do_interrupt(cs); 751 return true; 752 } 753 754 #endif /* CONFIG_TCG && !CONFIG_USER_ONLY */ 755 756 void arm_cpu_update_virq(ARMCPU *cpu) 757 { 758 /* 759 * Update the interrupt level for VIRQ, which is the logical OR of 760 * the HCR_EL2.VI bit and the input line level from the GIC. 761 */ 762 CPUARMState *env = &cpu->env; 763 CPUState *cs = CPU(cpu); 764 765 bool new_state = (env->cp15.hcr_el2 & HCR_VI) || 766 (env->irq_line_state & CPU_INTERRUPT_VIRQ); 767 768 if (new_state != ((cs->interrupt_request & CPU_INTERRUPT_VIRQ) != 0)) { 769 if (new_state) { 770 cpu_interrupt(cs, CPU_INTERRUPT_VIRQ); 771 } else { 772 cpu_reset_interrupt(cs, CPU_INTERRUPT_VIRQ); 773 } 774 } 775 } 776 777 void arm_cpu_update_vfiq(ARMCPU *cpu) 778 { 779 /* 780 * Update the interrupt level for VFIQ, which is the logical OR of 781 * the HCR_EL2.VF bit and the input line level from the GIC. 782 */ 783 CPUARMState *env = &cpu->env; 784 CPUState *cs = CPU(cpu); 785 786 bool new_state = (env->cp15.hcr_el2 & HCR_VF) || 787 (env->irq_line_state & CPU_INTERRUPT_VFIQ); 788 789 if (new_state != ((cs->interrupt_request & CPU_INTERRUPT_VFIQ) != 0)) { 790 if (new_state) { 791 cpu_interrupt(cs, CPU_INTERRUPT_VFIQ); 792 } else { 793 cpu_reset_interrupt(cs, CPU_INTERRUPT_VFIQ); 794 } 795 } 796 } 797 798 void arm_cpu_update_vserr(ARMCPU *cpu) 799 { 800 /* 801 * Update the interrupt level for VSERR, which is the HCR_EL2.VSE bit. 802 */ 803 CPUARMState *env = &cpu->env; 804 CPUState *cs = CPU(cpu); 805 806 bool new_state = env->cp15.hcr_el2 & HCR_VSE; 807 808 if (new_state != ((cs->interrupt_request & CPU_INTERRUPT_VSERR) != 0)) { 809 if (new_state) { 810 cpu_interrupt(cs, CPU_INTERRUPT_VSERR); 811 } else { 812 cpu_reset_interrupt(cs, CPU_INTERRUPT_VSERR); 813 } 814 } 815 } 816 817 #ifndef CONFIG_USER_ONLY 818 static void arm_cpu_set_irq(void *opaque, int irq, int level) 819 { 820 ARMCPU *cpu = opaque; 821 CPUARMState *env = &cpu->env; 822 CPUState *cs = CPU(cpu); 823 static const int mask[] = { 824 [ARM_CPU_IRQ] = CPU_INTERRUPT_HARD, 825 [ARM_CPU_FIQ] = CPU_INTERRUPT_FIQ, 826 [ARM_CPU_VIRQ] = CPU_INTERRUPT_VIRQ, 827 [ARM_CPU_VFIQ] = CPU_INTERRUPT_VFIQ 828 }; 829 830 if (!arm_feature(env, ARM_FEATURE_EL2) && 831 (irq == ARM_CPU_VIRQ || irq == ARM_CPU_VFIQ)) { 832 /* 833 * The GIC might tell us about VIRQ and VFIQ state, but if we don't 834 * have EL2 support we don't care. (Unless the guest is doing something 835 * silly this will only be calls saying "level is still 0".) 836 */ 837 return; 838 } 839 840 if (level) { 841 env->irq_line_state |= mask[irq]; 842 } else { 843 env->irq_line_state &= ~mask[irq]; 844 } 845 846 switch (irq) { 847 case ARM_CPU_VIRQ: 848 arm_cpu_update_virq(cpu); 849 break; 850 case ARM_CPU_VFIQ: 851 arm_cpu_update_vfiq(cpu); 852 break; 853 case ARM_CPU_IRQ: 854 case ARM_CPU_FIQ: 855 if (level) { 856 cpu_interrupt(cs, mask[irq]); 857 } else { 858 cpu_reset_interrupt(cs, mask[irq]); 859 } 860 break; 861 default: 862 g_assert_not_reached(); 863 } 864 } 865 866 static void arm_cpu_kvm_set_irq(void *opaque, int irq, int level) 867 { 868 #ifdef CONFIG_KVM 869 ARMCPU *cpu = opaque; 870 CPUARMState *env = &cpu->env; 871 CPUState *cs = CPU(cpu); 872 uint32_t linestate_bit; 873 int irq_id; 874 875 switch (irq) { 876 case ARM_CPU_IRQ: 877 irq_id = KVM_ARM_IRQ_CPU_IRQ; 878 linestate_bit = CPU_INTERRUPT_HARD; 879 break; 880 case ARM_CPU_FIQ: 881 irq_id = KVM_ARM_IRQ_CPU_FIQ; 882 linestate_bit = CPU_INTERRUPT_FIQ; 883 break; 884 default: 885 g_assert_not_reached(); 886 } 887 888 if (level) { 889 env->irq_line_state |= linestate_bit; 890 } else { 891 env->irq_line_state &= ~linestate_bit; 892 } 893 kvm_arm_set_irq(cs->cpu_index, KVM_ARM_IRQ_TYPE_CPU, irq_id, !!level); 894 #endif 895 } 896 897 static bool arm_cpu_virtio_is_big_endian(CPUState *cs) 898 { 899 ARMCPU *cpu = ARM_CPU(cs); 900 CPUARMState *env = &cpu->env; 901 902 cpu_synchronize_state(cs); 903 return arm_cpu_data_is_big_endian(env); 904 } 905 906 #endif 907 908 static void arm_disas_set_info(CPUState *cpu, disassemble_info *info) 909 { 910 ARMCPU *ac = ARM_CPU(cpu); 911 CPUARMState *env = &ac->env; 912 bool sctlr_b; 913 914 if (is_a64(env)) { 915 info->cap_arch = CS_ARCH_ARM64; 916 info->cap_insn_unit = 4; 917 info->cap_insn_split = 4; 918 } else { 919 int cap_mode; 920 if (env->thumb) { 921 info->cap_insn_unit = 2; 922 info->cap_insn_split = 4; 923 cap_mode = CS_MODE_THUMB; 924 } else { 925 info->cap_insn_unit = 4; 926 info->cap_insn_split = 4; 927 cap_mode = CS_MODE_ARM; 928 } 929 if (arm_feature(env, ARM_FEATURE_V8)) { 930 cap_mode |= CS_MODE_V8; 931 } 932 if (arm_feature(env, ARM_FEATURE_M)) { 933 cap_mode |= CS_MODE_MCLASS; 934 } 935 info->cap_arch = CS_ARCH_ARM; 936 info->cap_mode = cap_mode; 937 } 938 939 sctlr_b = arm_sctlr_b(env); 940 if (bswap_code(sctlr_b)) { 941 #if TARGET_BIG_ENDIAN 942 info->endian = BFD_ENDIAN_LITTLE; 943 #else 944 info->endian = BFD_ENDIAN_BIG; 945 #endif 946 } 947 info->flags &= ~INSN_ARM_BE32; 948 #ifndef CONFIG_USER_ONLY 949 if (sctlr_b) { 950 info->flags |= INSN_ARM_BE32; 951 } 952 #endif 953 } 954 955 #ifdef TARGET_AARCH64 956 957 static void aarch64_cpu_dump_state(CPUState *cs, FILE *f, int flags) 958 { 959 ARMCPU *cpu = ARM_CPU(cs); 960 CPUARMState *env = &cpu->env; 961 uint32_t psr = pstate_read(env); 962 int i, j; 963 int el = arm_current_el(env); 964 const char *ns_status; 965 bool sve; 966 967 qemu_fprintf(f, " PC=%016" PRIx64 " ", env->pc); 968 for (i = 0; i < 32; i++) { 969 if (i == 31) { 970 qemu_fprintf(f, " SP=%016" PRIx64 "\n", env->xregs[i]); 971 } else { 972 qemu_fprintf(f, "X%02d=%016" PRIx64 "%s", i, env->xregs[i], 973 (i + 2) % 3 ? " " : "\n"); 974 } 975 } 976 977 if (arm_feature(env, ARM_FEATURE_EL3) && el != 3) { 978 ns_status = env->cp15.scr_el3 & SCR_NS ? "NS " : "S "; 979 } else { 980 ns_status = ""; 981 } 982 qemu_fprintf(f, "PSTATE=%08x %c%c%c%c %sEL%d%c", 983 psr, 984 psr & PSTATE_N ? 'N' : '-', 985 psr & PSTATE_Z ? 'Z' : '-', 986 psr & PSTATE_C ? 'C' : '-', 987 psr & PSTATE_V ? 'V' : '-', 988 ns_status, 989 el, 990 psr & PSTATE_SP ? 'h' : 't'); 991 992 if (cpu_isar_feature(aa64_sme, cpu)) { 993 qemu_fprintf(f, " SVCR=%08" PRIx64 " %c%c", 994 env->svcr, 995 (FIELD_EX64(env->svcr, SVCR, ZA) ? 'Z' : '-'), 996 (FIELD_EX64(env->svcr, SVCR, SM) ? 'S' : '-')); 997 } 998 if (cpu_isar_feature(aa64_bti, cpu)) { 999 qemu_fprintf(f, " BTYPE=%d", (psr & PSTATE_BTYPE) >> 10); 1000 } 1001 if (!(flags & CPU_DUMP_FPU)) { 1002 qemu_fprintf(f, "\n"); 1003 return; 1004 } 1005 if (fp_exception_el(env, el) != 0) { 1006 qemu_fprintf(f, " FPU disabled\n"); 1007 return; 1008 } 1009 qemu_fprintf(f, " FPCR=%08x FPSR=%08x\n", 1010 vfp_get_fpcr(env), vfp_get_fpsr(env)); 1011 1012 if (cpu_isar_feature(aa64_sme, cpu) && FIELD_EX64(env->svcr, SVCR, SM)) { 1013 sve = sme_exception_el(env, el) == 0; 1014 } else if (cpu_isar_feature(aa64_sve, cpu)) { 1015 sve = sve_exception_el(env, el) == 0; 1016 } else { 1017 sve = false; 1018 } 1019 1020 if (sve) { 1021 int zcr_len = sve_vqm1_for_el(env, el); 1022 1023 for (i = 0; i <= FFR_PRED_NUM; i++) { 1024 bool eol; 1025 if (i == FFR_PRED_NUM) { 1026 qemu_fprintf(f, "FFR="); 1027 /* It's last, so end the line. */ 1028 eol = true; 1029 } else { 1030 qemu_fprintf(f, "P%02d=", i); 1031 switch (zcr_len) { 1032 case 0: 1033 eol = i % 8 == 7; 1034 break; 1035 case 1: 1036 eol = i % 6 == 5; 1037 break; 1038 case 2: 1039 case 3: 1040 eol = i % 3 == 2; 1041 break; 1042 default: 1043 /* More than one quadword per predicate. */ 1044 eol = true; 1045 break; 1046 } 1047 } 1048 for (j = zcr_len / 4; j >= 0; j--) { 1049 int digits; 1050 if (j * 4 + 4 <= zcr_len + 1) { 1051 digits = 16; 1052 } else { 1053 digits = (zcr_len % 4 + 1) * 4; 1054 } 1055 qemu_fprintf(f, "%0*" PRIx64 "%s", digits, 1056 env->vfp.pregs[i].p[j], 1057 j ? ":" : eol ? "\n" : " "); 1058 } 1059 } 1060 1061 if (zcr_len == 0) { 1062 /* 1063 * With vl=16, there are only 37 columns per register, 1064 * so output two registers per line. 1065 */ 1066 for (i = 0; i < 32; i++) { 1067 qemu_fprintf(f, "Z%02d=%016" PRIx64 ":%016" PRIx64 "%s", 1068 i, env->vfp.zregs[i].d[1], 1069 env->vfp.zregs[i].d[0], i & 1 ? "\n" : " "); 1070 } 1071 } else { 1072 for (i = 0; i < 32; i++) { 1073 qemu_fprintf(f, "Z%02d=", i); 1074 for (j = zcr_len; j >= 0; j--) { 1075 qemu_fprintf(f, "%016" PRIx64 ":%016" PRIx64 "%s", 1076 env->vfp.zregs[i].d[j * 2 + 1], 1077 env->vfp.zregs[i].d[j * 2 + 0], 1078 j ? ":" : "\n"); 1079 } 1080 } 1081 } 1082 } else { 1083 for (i = 0; i < 32; i++) { 1084 uint64_t *q = aa64_vfp_qreg(env, i); 1085 qemu_fprintf(f, "Q%02d=%016" PRIx64 ":%016" PRIx64 "%s", 1086 i, q[1], q[0], (i & 1 ? "\n" : " ")); 1087 } 1088 } 1089 1090 if (cpu_isar_feature(aa64_sme, cpu) && 1091 FIELD_EX64(env->svcr, SVCR, ZA) && 1092 sme_exception_el(env, el) == 0) { 1093 int zcr_len = sve_vqm1_for_el_sm(env, el, true); 1094 int svl = (zcr_len + 1) * 16; 1095 int svl_lg10 = svl < 100 ? 2 : 3; 1096 1097 for (i = 0; i < svl; i++) { 1098 qemu_fprintf(f, "ZA[%0*d]=", svl_lg10, i); 1099 for (j = zcr_len; j >= 0; --j) { 1100 qemu_fprintf(f, "%016" PRIx64 ":%016" PRIx64 "%c", 1101 env->zarray[i].d[2 * j + 1], 1102 env->zarray[i].d[2 * j], 1103 j ? ':' : '\n'); 1104 } 1105 } 1106 } 1107 } 1108 1109 #else 1110 1111 static inline void aarch64_cpu_dump_state(CPUState *cs, FILE *f, int flags) 1112 { 1113 g_assert_not_reached(); 1114 } 1115 1116 #endif 1117 1118 static void arm_cpu_dump_state(CPUState *cs, FILE *f, int flags) 1119 { 1120 ARMCPU *cpu = ARM_CPU(cs); 1121 CPUARMState *env = &cpu->env; 1122 int i; 1123 1124 if (is_a64(env)) { 1125 aarch64_cpu_dump_state(cs, f, flags); 1126 return; 1127 } 1128 1129 for (i = 0; i < 16; i++) { 1130 qemu_fprintf(f, "R%02d=%08x", i, env->regs[i]); 1131 if ((i % 4) == 3) { 1132 qemu_fprintf(f, "\n"); 1133 } else { 1134 qemu_fprintf(f, " "); 1135 } 1136 } 1137 1138 if (arm_feature(env, ARM_FEATURE_M)) { 1139 uint32_t xpsr = xpsr_read(env); 1140 const char *mode; 1141 const char *ns_status = ""; 1142 1143 if (arm_feature(env, ARM_FEATURE_M_SECURITY)) { 1144 ns_status = env->v7m.secure ? "S " : "NS "; 1145 } 1146 1147 if (xpsr & XPSR_EXCP) { 1148 mode = "handler"; 1149 } else { 1150 if (env->v7m.control[env->v7m.secure] & R_V7M_CONTROL_NPRIV_MASK) { 1151 mode = "unpriv-thread"; 1152 } else { 1153 mode = "priv-thread"; 1154 } 1155 } 1156 1157 qemu_fprintf(f, "XPSR=%08x %c%c%c%c %c %s%s\n", 1158 xpsr, 1159 xpsr & XPSR_N ? 'N' : '-', 1160 xpsr & XPSR_Z ? 'Z' : '-', 1161 xpsr & XPSR_C ? 'C' : '-', 1162 xpsr & XPSR_V ? 'V' : '-', 1163 xpsr & XPSR_T ? 'T' : 'A', 1164 ns_status, 1165 mode); 1166 } else { 1167 uint32_t psr = cpsr_read(env); 1168 const char *ns_status = ""; 1169 1170 if (arm_feature(env, ARM_FEATURE_EL3) && 1171 (psr & CPSR_M) != ARM_CPU_MODE_MON) { 1172 ns_status = env->cp15.scr_el3 & SCR_NS ? "NS " : "S "; 1173 } 1174 1175 qemu_fprintf(f, "PSR=%08x %c%c%c%c %c %s%s%d\n", 1176 psr, 1177 psr & CPSR_N ? 'N' : '-', 1178 psr & CPSR_Z ? 'Z' : '-', 1179 psr & CPSR_C ? 'C' : '-', 1180 psr & CPSR_V ? 'V' : '-', 1181 psr & CPSR_T ? 'T' : 'A', 1182 ns_status, 1183 aarch32_mode_name(psr), (psr & 0x10) ? 32 : 26); 1184 } 1185 1186 if (flags & CPU_DUMP_FPU) { 1187 int numvfpregs = 0; 1188 if (cpu_isar_feature(aa32_simd_r32, cpu)) { 1189 numvfpregs = 32; 1190 } else if (cpu_isar_feature(aa32_vfp_simd, cpu)) { 1191 numvfpregs = 16; 1192 } 1193 for (i = 0; i < numvfpregs; i++) { 1194 uint64_t v = *aa32_vfp_dreg(env, i); 1195 qemu_fprintf(f, "s%02d=%08x s%02d=%08x d%02d=%016" PRIx64 "\n", 1196 i * 2, (uint32_t)v, 1197 i * 2 + 1, (uint32_t)(v >> 32), 1198 i, v); 1199 } 1200 qemu_fprintf(f, "FPSCR: %08x\n", vfp_get_fpscr(env)); 1201 if (cpu_isar_feature(aa32_mve, cpu)) { 1202 qemu_fprintf(f, "VPR: %08x\n", env->v7m.vpr); 1203 } 1204 } 1205 } 1206 1207 uint64_t arm_cpu_mp_affinity(int idx, uint8_t clustersz) 1208 { 1209 uint32_t Aff1 = idx / clustersz; 1210 uint32_t Aff0 = idx % clustersz; 1211 return (Aff1 << ARM_AFF1_SHIFT) | Aff0; 1212 } 1213 1214 static void arm_cpu_initfn(Object *obj) 1215 { 1216 ARMCPU *cpu = ARM_CPU(obj); 1217 1218 cpu_set_cpustate_pointers(cpu); 1219 cpu->cp_regs = g_hash_table_new_full(g_direct_hash, g_direct_equal, 1220 NULL, g_free); 1221 1222 QLIST_INIT(&cpu->pre_el_change_hooks); 1223 QLIST_INIT(&cpu->el_change_hooks); 1224 1225 #ifdef CONFIG_USER_ONLY 1226 # ifdef TARGET_AARCH64 1227 /* 1228 * The linux kernel defaults to 512-bit for SVE, and 256-bit for SME. 1229 * These values were chosen to fit within the default signal frame. 1230 * See documentation for /proc/sys/abi/{sve,sme}_default_vector_length, 1231 * and our corresponding cpu property. 1232 */ 1233 cpu->sve_default_vq = 4; 1234 cpu->sme_default_vq = 2; 1235 # endif 1236 #else 1237 /* Our inbound IRQ and FIQ lines */ 1238 if (kvm_enabled()) { 1239 /* VIRQ and VFIQ are unused with KVM but we add them to maintain 1240 * the same interface as non-KVM CPUs. 1241 */ 1242 qdev_init_gpio_in(DEVICE(cpu), arm_cpu_kvm_set_irq, 4); 1243 } else { 1244 qdev_init_gpio_in(DEVICE(cpu), arm_cpu_set_irq, 4); 1245 } 1246 1247 qdev_init_gpio_out(DEVICE(cpu), cpu->gt_timer_outputs, 1248 ARRAY_SIZE(cpu->gt_timer_outputs)); 1249 1250 qdev_init_gpio_out_named(DEVICE(cpu), &cpu->gicv3_maintenance_interrupt, 1251 "gicv3-maintenance-interrupt", 1); 1252 qdev_init_gpio_out_named(DEVICE(cpu), &cpu->pmu_interrupt, 1253 "pmu-interrupt", 1); 1254 #endif 1255 1256 /* DTB consumers generally don't in fact care what the 'compatible' 1257 * string is, so always provide some string and trust that a hypothetical 1258 * picky DTB consumer will also provide a helpful error message. 1259 */ 1260 cpu->dtb_compatible = "qemu,unknown"; 1261 cpu->psci_version = QEMU_PSCI_VERSION_0_1; /* By default assume PSCI v0.1 */ 1262 cpu->kvm_target = QEMU_KVM_ARM_TARGET_NONE; 1263 1264 if (tcg_enabled() || hvf_enabled()) { 1265 /* TCG and HVF implement PSCI 1.1 */ 1266 cpu->psci_version = QEMU_PSCI_VERSION_1_1; 1267 } 1268 } 1269 1270 static Property arm_cpu_gt_cntfrq_property = 1271 DEFINE_PROP_UINT64("cntfrq", ARMCPU, gt_cntfrq_hz, 1272 NANOSECONDS_PER_SECOND / GTIMER_SCALE); 1273 1274 static Property arm_cpu_reset_cbar_property = 1275 DEFINE_PROP_UINT64("reset-cbar", ARMCPU, reset_cbar, 0); 1276 1277 static Property arm_cpu_reset_hivecs_property = 1278 DEFINE_PROP_BOOL("reset-hivecs", ARMCPU, reset_hivecs, false); 1279 1280 #ifndef CONFIG_USER_ONLY 1281 static Property arm_cpu_has_el2_property = 1282 DEFINE_PROP_BOOL("has_el2", ARMCPU, has_el2, true); 1283 1284 static Property arm_cpu_has_el3_property = 1285 DEFINE_PROP_BOOL("has_el3", ARMCPU, has_el3, true); 1286 #endif 1287 1288 static Property arm_cpu_cfgend_property = 1289 DEFINE_PROP_BOOL("cfgend", ARMCPU, cfgend, false); 1290 1291 static Property arm_cpu_has_vfp_property = 1292 DEFINE_PROP_BOOL("vfp", ARMCPU, has_vfp, true); 1293 1294 static Property arm_cpu_has_vfp_d32_property = 1295 DEFINE_PROP_BOOL("vfp-d32", ARMCPU, has_vfp_d32, true); 1296 1297 static Property arm_cpu_has_neon_property = 1298 DEFINE_PROP_BOOL("neon", ARMCPU, has_neon, true); 1299 1300 static Property arm_cpu_has_dsp_property = 1301 DEFINE_PROP_BOOL("dsp", ARMCPU, has_dsp, true); 1302 1303 static Property arm_cpu_has_mpu_property = 1304 DEFINE_PROP_BOOL("has-mpu", ARMCPU, has_mpu, true); 1305 1306 /* This is like DEFINE_PROP_UINT32 but it doesn't set the default value, 1307 * because the CPU initfn will have already set cpu->pmsav7_dregion to 1308 * the right value for that particular CPU type, and we don't want 1309 * to override that with an incorrect constant value. 1310 */ 1311 static Property arm_cpu_pmsav7_dregion_property = 1312 DEFINE_PROP_UNSIGNED_NODEFAULT("pmsav7-dregion", ARMCPU, 1313 pmsav7_dregion, 1314 qdev_prop_uint32, uint32_t); 1315 1316 static bool arm_get_pmu(Object *obj, Error **errp) 1317 { 1318 ARMCPU *cpu = ARM_CPU(obj); 1319 1320 return cpu->has_pmu; 1321 } 1322 1323 static void arm_set_pmu(Object *obj, bool value, Error **errp) 1324 { 1325 ARMCPU *cpu = ARM_CPU(obj); 1326 1327 if (value) { 1328 if (kvm_enabled() && !kvm_arm_pmu_supported()) { 1329 error_setg(errp, "'pmu' feature not supported by KVM on this host"); 1330 return; 1331 } 1332 set_feature(&cpu->env, ARM_FEATURE_PMU); 1333 } else { 1334 unset_feature(&cpu->env, ARM_FEATURE_PMU); 1335 } 1336 cpu->has_pmu = value; 1337 } 1338 1339 unsigned int gt_cntfrq_period_ns(ARMCPU *cpu) 1340 { 1341 /* 1342 * The exact approach to calculating guest ticks is: 1343 * 1344 * muldiv64(qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL), cpu->gt_cntfrq_hz, 1345 * NANOSECONDS_PER_SECOND); 1346 * 1347 * We don't do that. Rather we intentionally use integer division 1348 * truncation below and in the caller for the conversion of host monotonic 1349 * time to guest ticks to provide the exact inverse for the semantics of 1350 * the QEMUTimer scale factor. QEMUTimer's scale facter is an integer, so 1351 * it loses precision when representing frequencies where 1352 * `(NANOSECONDS_PER_SECOND % cpu->gt_cntfrq) > 0` holds. Failing to 1353 * provide an exact inverse leads to scheduling timers with negative 1354 * periods, which in turn leads to sticky behaviour in the guest. 1355 * 1356 * Finally, CNTFRQ is effectively capped at 1GHz to ensure our scale factor 1357 * cannot become zero. 1358 */ 1359 return NANOSECONDS_PER_SECOND > cpu->gt_cntfrq_hz ? 1360 NANOSECONDS_PER_SECOND / cpu->gt_cntfrq_hz : 1; 1361 } 1362 1363 static void arm_cpu_propagate_feature_implications(ARMCPU *cpu) 1364 { 1365 CPUARMState *env = &cpu->env; 1366 bool no_aa32 = false; 1367 1368 /* 1369 * Some features automatically imply others: set the feature 1370 * bits explicitly for these cases. 1371 */ 1372 1373 if (arm_feature(env, ARM_FEATURE_M)) { 1374 set_feature(env, ARM_FEATURE_PMSA); 1375 } 1376 1377 if (arm_feature(env, ARM_FEATURE_V8)) { 1378 if (arm_feature(env, ARM_FEATURE_M)) { 1379 set_feature(env, ARM_FEATURE_V7); 1380 } else { 1381 set_feature(env, ARM_FEATURE_V7VE); 1382 } 1383 } 1384 1385 /* 1386 * There exist AArch64 cpus without AArch32 support. When KVM 1387 * queries ID_ISAR0_EL1 on such a host, the value is UNKNOWN. 1388 * Similarly, we cannot check ID_AA64PFR0 without AArch64 support. 1389 * As a general principle, we also do not make ID register 1390 * consistency checks anywhere unless using TCG, because only 1391 * for TCG would a consistency-check failure be a QEMU bug. 1392 */ 1393 if (arm_feature(&cpu->env, ARM_FEATURE_AARCH64)) { 1394 no_aa32 = !cpu_isar_feature(aa64_aa32, cpu); 1395 } 1396 1397 if (arm_feature(env, ARM_FEATURE_V7VE)) { 1398 /* 1399 * v7 Virtualization Extensions. In real hardware this implies 1400 * EL2 and also the presence of the Security Extensions. 1401 * For QEMU, for backwards-compatibility we implement some 1402 * CPUs or CPU configs which have no actual EL2 or EL3 but do 1403 * include the various other features that V7VE implies. 1404 * Presence of EL2 itself is ARM_FEATURE_EL2, and of the 1405 * Security Extensions is ARM_FEATURE_EL3. 1406 */ 1407 assert(!tcg_enabled() || no_aa32 || 1408 cpu_isar_feature(aa32_arm_div, cpu)); 1409 set_feature(env, ARM_FEATURE_LPAE); 1410 set_feature(env, ARM_FEATURE_V7); 1411 } 1412 if (arm_feature(env, ARM_FEATURE_V7)) { 1413 set_feature(env, ARM_FEATURE_VAPA); 1414 set_feature(env, ARM_FEATURE_THUMB2); 1415 set_feature(env, ARM_FEATURE_MPIDR); 1416 if (!arm_feature(env, ARM_FEATURE_M)) { 1417 set_feature(env, ARM_FEATURE_V6K); 1418 } else { 1419 set_feature(env, ARM_FEATURE_V6); 1420 } 1421 1422 /* 1423 * Always define VBAR for V7 CPUs even if it doesn't exist in 1424 * non-EL3 configs. This is needed by some legacy boards. 1425 */ 1426 set_feature(env, ARM_FEATURE_VBAR); 1427 } 1428 if (arm_feature(env, ARM_FEATURE_V6K)) { 1429 set_feature(env, ARM_FEATURE_V6); 1430 set_feature(env, ARM_FEATURE_MVFR); 1431 } 1432 if (arm_feature(env, ARM_FEATURE_V6)) { 1433 set_feature(env, ARM_FEATURE_V5); 1434 if (!arm_feature(env, ARM_FEATURE_M)) { 1435 assert(!tcg_enabled() || no_aa32 || 1436 cpu_isar_feature(aa32_jazelle, cpu)); 1437 set_feature(env, ARM_FEATURE_AUXCR); 1438 } 1439 } 1440 if (arm_feature(env, ARM_FEATURE_V5)) { 1441 set_feature(env, ARM_FEATURE_V4T); 1442 } 1443 if (arm_feature(env, ARM_FEATURE_LPAE)) { 1444 set_feature(env, ARM_FEATURE_V7MP); 1445 } 1446 if (arm_feature(env, ARM_FEATURE_CBAR_RO)) { 1447 set_feature(env, ARM_FEATURE_CBAR); 1448 } 1449 if (arm_feature(env, ARM_FEATURE_THUMB2) && 1450 !arm_feature(env, ARM_FEATURE_M)) { 1451 set_feature(env, ARM_FEATURE_THUMB_DSP); 1452 } 1453 } 1454 1455 void arm_cpu_post_init(Object *obj) 1456 { 1457 ARMCPU *cpu = ARM_CPU(obj); 1458 1459 /* 1460 * Some features imply others. Figure this out now, because we 1461 * are going to look at the feature bits in deciding which 1462 * properties to add. 1463 */ 1464 arm_cpu_propagate_feature_implications(cpu); 1465 1466 if (arm_feature(&cpu->env, ARM_FEATURE_CBAR) || 1467 arm_feature(&cpu->env, ARM_FEATURE_CBAR_RO)) { 1468 qdev_property_add_static(DEVICE(obj), &arm_cpu_reset_cbar_property); 1469 } 1470 1471 if (!arm_feature(&cpu->env, ARM_FEATURE_M)) { 1472 qdev_property_add_static(DEVICE(obj), &arm_cpu_reset_hivecs_property); 1473 } 1474 1475 if (arm_feature(&cpu->env, ARM_FEATURE_V8)) { 1476 object_property_add_uint64_ptr(obj, "rvbar", 1477 &cpu->rvbar_prop, 1478 OBJ_PROP_FLAG_READWRITE); 1479 } 1480 1481 #ifndef CONFIG_USER_ONLY 1482 if (arm_feature(&cpu->env, ARM_FEATURE_EL3)) { 1483 /* Add the has_el3 state CPU property only if EL3 is allowed. This will 1484 * prevent "has_el3" from existing on CPUs which cannot support EL3. 1485 */ 1486 qdev_property_add_static(DEVICE(obj), &arm_cpu_has_el3_property); 1487 1488 object_property_add_link(obj, "secure-memory", 1489 TYPE_MEMORY_REGION, 1490 (Object **)&cpu->secure_memory, 1491 qdev_prop_allow_set_link_before_realize, 1492 OBJ_PROP_LINK_STRONG); 1493 } 1494 1495 if (arm_feature(&cpu->env, ARM_FEATURE_EL2)) { 1496 qdev_property_add_static(DEVICE(obj), &arm_cpu_has_el2_property); 1497 } 1498 #endif 1499 1500 if (arm_feature(&cpu->env, ARM_FEATURE_PMU)) { 1501 cpu->has_pmu = true; 1502 object_property_add_bool(obj, "pmu", arm_get_pmu, arm_set_pmu); 1503 } 1504 1505 /* 1506 * Allow user to turn off VFP and Neon support, but only for TCG -- 1507 * KVM does not currently allow us to lie to the guest about its 1508 * ID/feature registers, so the guest always sees what the host has. 1509 */ 1510 if (arm_feature(&cpu->env, ARM_FEATURE_AARCH64)) { 1511 if (cpu_isar_feature(aa64_fp_simd, cpu)) { 1512 cpu->has_vfp = true; 1513 cpu->has_vfp_d32 = true; 1514 if (tcg_enabled() || qtest_enabled()) { 1515 qdev_property_add_static(DEVICE(obj), 1516 &arm_cpu_has_vfp_property); 1517 } 1518 } 1519 } else if (cpu_isar_feature(aa32_vfp, cpu)) { 1520 cpu->has_vfp = true; 1521 if (cpu_isar_feature(aa32_simd_r32, cpu)) { 1522 cpu->has_vfp_d32 = true; 1523 /* 1524 * The permitted values of the SIMDReg bits [3:0] on 1525 * Armv8-A are either 0b0000 and 0b0010. On such CPUs, 1526 * make sure that has_vfp_d32 can not be set to false. 1527 */ 1528 if ((tcg_enabled() || qtest_enabled()) 1529 && !(arm_feature(&cpu->env, ARM_FEATURE_V8) 1530 && !arm_feature(&cpu->env, ARM_FEATURE_M))) { 1531 qdev_property_add_static(DEVICE(obj), 1532 &arm_cpu_has_vfp_d32_property); 1533 } 1534 } 1535 } 1536 1537 if (arm_feature(&cpu->env, ARM_FEATURE_NEON)) { 1538 cpu->has_neon = true; 1539 if (!kvm_enabled()) { 1540 qdev_property_add_static(DEVICE(obj), &arm_cpu_has_neon_property); 1541 } 1542 } 1543 1544 if (arm_feature(&cpu->env, ARM_FEATURE_M) && 1545 arm_feature(&cpu->env, ARM_FEATURE_THUMB_DSP)) { 1546 qdev_property_add_static(DEVICE(obj), &arm_cpu_has_dsp_property); 1547 } 1548 1549 if (arm_feature(&cpu->env, ARM_FEATURE_PMSA)) { 1550 qdev_property_add_static(DEVICE(obj), &arm_cpu_has_mpu_property); 1551 if (arm_feature(&cpu->env, ARM_FEATURE_V7)) { 1552 qdev_property_add_static(DEVICE(obj), 1553 &arm_cpu_pmsav7_dregion_property); 1554 } 1555 } 1556 1557 if (arm_feature(&cpu->env, ARM_FEATURE_M_SECURITY)) { 1558 object_property_add_link(obj, "idau", TYPE_IDAU_INTERFACE, &cpu->idau, 1559 qdev_prop_allow_set_link_before_realize, 1560 OBJ_PROP_LINK_STRONG); 1561 /* 1562 * M profile: initial value of the Secure VTOR. We can't just use 1563 * a simple DEFINE_PROP_UINT32 for this because we want to permit 1564 * the property to be set after realize. 1565 */ 1566 object_property_add_uint32_ptr(obj, "init-svtor", 1567 &cpu->init_svtor, 1568 OBJ_PROP_FLAG_READWRITE); 1569 } 1570 if (arm_feature(&cpu->env, ARM_FEATURE_M)) { 1571 /* 1572 * Initial value of the NS VTOR (for cores without the Security 1573 * extension, this is the only VTOR) 1574 */ 1575 object_property_add_uint32_ptr(obj, "init-nsvtor", 1576 &cpu->init_nsvtor, 1577 OBJ_PROP_FLAG_READWRITE); 1578 } 1579 1580 /* Not DEFINE_PROP_UINT32: we want this to be settable after realize */ 1581 object_property_add_uint32_ptr(obj, "psci-conduit", 1582 &cpu->psci_conduit, 1583 OBJ_PROP_FLAG_READWRITE); 1584 1585 qdev_property_add_static(DEVICE(obj), &arm_cpu_cfgend_property); 1586 1587 if (arm_feature(&cpu->env, ARM_FEATURE_GENERIC_TIMER)) { 1588 qdev_property_add_static(DEVICE(cpu), &arm_cpu_gt_cntfrq_property); 1589 } 1590 1591 if (kvm_enabled()) { 1592 kvm_arm_add_vcpu_properties(obj); 1593 } 1594 1595 #ifndef CONFIG_USER_ONLY 1596 if (arm_feature(&cpu->env, ARM_FEATURE_AARCH64) && 1597 cpu_isar_feature(aa64_mte, cpu)) { 1598 object_property_add_link(obj, "tag-memory", 1599 TYPE_MEMORY_REGION, 1600 (Object **)&cpu->tag_memory, 1601 qdev_prop_allow_set_link_before_realize, 1602 OBJ_PROP_LINK_STRONG); 1603 1604 if (arm_feature(&cpu->env, ARM_FEATURE_EL3)) { 1605 object_property_add_link(obj, "secure-tag-memory", 1606 TYPE_MEMORY_REGION, 1607 (Object **)&cpu->secure_tag_memory, 1608 qdev_prop_allow_set_link_before_realize, 1609 OBJ_PROP_LINK_STRONG); 1610 } 1611 } 1612 #endif 1613 } 1614 1615 static void arm_cpu_finalizefn(Object *obj) 1616 { 1617 ARMCPU *cpu = ARM_CPU(obj); 1618 ARMELChangeHook *hook, *next; 1619 1620 g_hash_table_destroy(cpu->cp_regs); 1621 1622 QLIST_FOREACH_SAFE(hook, &cpu->pre_el_change_hooks, node, next) { 1623 QLIST_REMOVE(hook, node); 1624 g_free(hook); 1625 } 1626 QLIST_FOREACH_SAFE(hook, &cpu->el_change_hooks, node, next) { 1627 QLIST_REMOVE(hook, node); 1628 g_free(hook); 1629 } 1630 #ifndef CONFIG_USER_ONLY 1631 if (cpu->pmu_timer) { 1632 timer_free(cpu->pmu_timer); 1633 } 1634 #endif 1635 } 1636 1637 void arm_cpu_finalize_features(ARMCPU *cpu, Error **errp) 1638 { 1639 Error *local_err = NULL; 1640 1641 #ifdef TARGET_AARCH64 1642 if (arm_feature(&cpu->env, ARM_FEATURE_AARCH64)) { 1643 arm_cpu_sve_finalize(cpu, &local_err); 1644 if (local_err != NULL) { 1645 error_propagate(errp, local_err); 1646 return; 1647 } 1648 1649 arm_cpu_sme_finalize(cpu, &local_err); 1650 if (local_err != NULL) { 1651 error_propagate(errp, local_err); 1652 return; 1653 } 1654 1655 arm_cpu_pauth_finalize(cpu, &local_err); 1656 if (local_err != NULL) { 1657 error_propagate(errp, local_err); 1658 return; 1659 } 1660 1661 arm_cpu_lpa2_finalize(cpu, &local_err); 1662 if (local_err != NULL) { 1663 error_propagate(errp, local_err); 1664 return; 1665 } 1666 } 1667 #endif 1668 1669 if (kvm_enabled()) { 1670 kvm_arm_steal_time_finalize(cpu, &local_err); 1671 if (local_err != NULL) { 1672 error_propagate(errp, local_err); 1673 return; 1674 } 1675 } 1676 } 1677 1678 static void arm_cpu_realizefn(DeviceState *dev, Error **errp) 1679 { 1680 CPUState *cs = CPU(dev); 1681 ARMCPU *cpu = ARM_CPU(dev); 1682 ARMCPUClass *acc = ARM_CPU_GET_CLASS(dev); 1683 CPUARMState *env = &cpu->env; 1684 int pagebits; 1685 Error *local_err = NULL; 1686 1687 /* Use pc-relative instructions in system-mode */ 1688 #ifndef CONFIG_USER_ONLY 1689 cs->tcg_cflags |= CF_PCREL; 1690 #endif 1691 1692 /* If we needed to query the host kernel for the CPU features 1693 * then it's possible that might have failed in the initfn, but 1694 * this is the first point where we can report it. 1695 */ 1696 if (cpu->host_cpu_probe_failed) { 1697 if (!kvm_enabled() && !hvf_enabled()) { 1698 error_setg(errp, "The 'host' CPU type can only be used with KVM or HVF"); 1699 } else { 1700 error_setg(errp, "Failed to retrieve host CPU features"); 1701 } 1702 return; 1703 } 1704 1705 #ifndef CONFIG_USER_ONLY 1706 /* The NVIC and M-profile CPU are two halves of a single piece of 1707 * hardware; trying to use one without the other is a command line 1708 * error and will result in segfaults if not caught here. 1709 */ 1710 if (arm_feature(env, ARM_FEATURE_M)) { 1711 if (!env->nvic) { 1712 error_setg(errp, "This board cannot be used with Cortex-M CPUs"); 1713 return; 1714 } 1715 } else { 1716 if (env->nvic) { 1717 error_setg(errp, "This board can only be used with Cortex-M CPUs"); 1718 return; 1719 } 1720 } 1721 1722 if (!tcg_enabled() && !qtest_enabled()) { 1723 /* 1724 * We assume that no accelerator except TCG (and the "not really an 1725 * accelerator" qtest) can handle these features, because Arm hardware 1726 * virtualization can't virtualize them. 1727 * 1728 * Catch all the cases which might cause us to create more than one 1729 * address space for the CPU (otherwise we will assert() later in 1730 * cpu_address_space_init()). 1731 */ 1732 if (arm_feature(env, ARM_FEATURE_M)) { 1733 error_setg(errp, 1734 "Cannot enable %s when using an M-profile guest CPU", 1735 current_accel_name()); 1736 return; 1737 } 1738 if (cpu->has_el3) { 1739 error_setg(errp, 1740 "Cannot enable %s when guest CPU has EL3 enabled", 1741 current_accel_name()); 1742 return; 1743 } 1744 if (cpu->tag_memory) { 1745 error_setg(errp, 1746 "Cannot enable %s when guest CPUs has MTE enabled", 1747 current_accel_name()); 1748 return; 1749 } 1750 } 1751 1752 { 1753 uint64_t scale; 1754 1755 if (arm_feature(env, ARM_FEATURE_GENERIC_TIMER)) { 1756 if (!cpu->gt_cntfrq_hz) { 1757 error_setg(errp, "Invalid CNTFRQ: %"PRId64"Hz", 1758 cpu->gt_cntfrq_hz); 1759 return; 1760 } 1761 scale = gt_cntfrq_period_ns(cpu); 1762 } else { 1763 scale = GTIMER_SCALE; 1764 } 1765 1766 cpu->gt_timer[GTIMER_PHYS] = timer_new(QEMU_CLOCK_VIRTUAL, scale, 1767 arm_gt_ptimer_cb, cpu); 1768 cpu->gt_timer[GTIMER_VIRT] = timer_new(QEMU_CLOCK_VIRTUAL, scale, 1769 arm_gt_vtimer_cb, cpu); 1770 cpu->gt_timer[GTIMER_HYP] = timer_new(QEMU_CLOCK_VIRTUAL, scale, 1771 arm_gt_htimer_cb, cpu); 1772 cpu->gt_timer[GTIMER_SEC] = timer_new(QEMU_CLOCK_VIRTUAL, scale, 1773 arm_gt_stimer_cb, cpu); 1774 cpu->gt_timer[GTIMER_HYPVIRT] = timer_new(QEMU_CLOCK_VIRTUAL, scale, 1775 arm_gt_hvtimer_cb, cpu); 1776 } 1777 #endif 1778 1779 cpu_exec_realizefn(cs, &local_err); 1780 if (local_err != NULL) { 1781 error_propagate(errp, local_err); 1782 return; 1783 } 1784 1785 arm_cpu_finalize_features(cpu, &local_err); 1786 if (local_err != NULL) { 1787 error_propagate(errp, local_err); 1788 return; 1789 } 1790 1791 #ifdef CONFIG_USER_ONLY 1792 /* 1793 * User mode relies on IC IVAU instructions to catch modification of 1794 * dual-mapped code. 1795 * 1796 * Clear CTR_EL0.DIC to ensure that software that honors these flags uses 1797 * IC IVAU even if the emulated processor does not normally require it. 1798 */ 1799 cpu->ctr = FIELD_DP64(cpu->ctr, CTR_EL0, DIC, 0); 1800 #endif 1801 1802 if (arm_feature(env, ARM_FEATURE_AARCH64) && 1803 cpu->has_vfp != cpu->has_neon) { 1804 /* 1805 * This is an architectural requirement for AArch64; AArch32 is 1806 * more flexible and permits VFP-no-Neon and Neon-no-VFP. 1807 */ 1808 error_setg(errp, 1809 "AArch64 CPUs must have both VFP and Neon or neither"); 1810 return; 1811 } 1812 1813 if (cpu->has_vfp_d32 != cpu->has_neon) { 1814 error_setg(errp, "ARM CPUs must have both VFP-D32 and Neon or neither"); 1815 return; 1816 } 1817 1818 if (!cpu->has_vfp_d32) { 1819 uint32_t u; 1820 1821 u = cpu->isar.mvfr0; 1822 u = FIELD_DP32(u, MVFR0, SIMDREG, 1); /* 16 registers */ 1823 cpu->isar.mvfr0 = u; 1824 } 1825 1826 if (!cpu->has_vfp) { 1827 uint64_t t; 1828 uint32_t u; 1829 1830 t = cpu->isar.id_aa64isar1; 1831 t = FIELD_DP64(t, ID_AA64ISAR1, JSCVT, 0); 1832 cpu->isar.id_aa64isar1 = t; 1833 1834 t = cpu->isar.id_aa64pfr0; 1835 t = FIELD_DP64(t, ID_AA64PFR0, FP, 0xf); 1836 cpu->isar.id_aa64pfr0 = t; 1837 1838 u = cpu->isar.id_isar6; 1839 u = FIELD_DP32(u, ID_ISAR6, JSCVT, 0); 1840 u = FIELD_DP32(u, ID_ISAR6, BF16, 0); 1841 cpu->isar.id_isar6 = u; 1842 1843 u = cpu->isar.mvfr0; 1844 u = FIELD_DP32(u, MVFR0, FPSP, 0); 1845 u = FIELD_DP32(u, MVFR0, FPDP, 0); 1846 u = FIELD_DP32(u, MVFR0, FPDIVIDE, 0); 1847 u = FIELD_DP32(u, MVFR0, FPSQRT, 0); 1848 u = FIELD_DP32(u, MVFR0, FPROUND, 0); 1849 if (!arm_feature(env, ARM_FEATURE_M)) { 1850 u = FIELD_DP32(u, MVFR0, FPTRAP, 0); 1851 u = FIELD_DP32(u, MVFR0, FPSHVEC, 0); 1852 } 1853 cpu->isar.mvfr0 = u; 1854 1855 u = cpu->isar.mvfr1; 1856 u = FIELD_DP32(u, MVFR1, FPFTZ, 0); 1857 u = FIELD_DP32(u, MVFR1, FPDNAN, 0); 1858 u = FIELD_DP32(u, MVFR1, FPHP, 0); 1859 if (arm_feature(env, ARM_FEATURE_M)) { 1860 u = FIELD_DP32(u, MVFR1, FP16, 0); 1861 } 1862 cpu->isar.mvfr1 = u; 1863 1864 u = cpu->isar.mvfr2; 1865 u = FIELD_DP32(u, MVFR2, FPMISC, 0); 1866 cpu->isar.mvfr2 = u; 1867 } 1868 1869 if (!cpu->has_neon) { 1870 uint64_t t; 1871 uint32_t u; 1872 1873 unset_feature(env, ARM_FEATURE_NEON); 1874 1875 t = cpu->isar.id_aa64isar0; 1876 t = FIELD_DP64(t, ID_AA64ISAR0, AES, 0); 1877 t = FIELD_DP64(t, ID_AA64ISAR0, SHA1, 0); 1878 t = FIELD_DP64(t, ID_AA64ISAR0, SHA2, 0); 1879 t = FIELD_DP64(t, ID_AA64ISAR0, SHA3, 0); 1880 t = FIELD_DP64(t, ID_AA64ISAR0, SM3, 0); 1881 t = FIELD_DP64(t, ID_AA64ISAR0, SM4, 0); 1882 t = FIELD_DP64(t, ID_AA64ISAR0, DP, 0); 1883 cpu->isar.id_aa64isar0 = t; 1884 1885 t = cpu->isar.id_aa64isar1; 1886 t = FIELD_DP64(t, ID_AA64ISAR1, FCMA, 0); 1887 t = FIELD_DP64(t, ID_AA64ISAR1, BF16, 0); 1888 t = FIELD_DP64(t, ID_AA64ISAR1, I8MM, 0); 1889 cpu->isar.id_aa64isar1 = t; 1890 1891 t = cpu->isar.id_aa64pfr0; 1892 t = FIELD_DP64(t, ID_AA64PFR0, ADVSIMD, 0xf); 1893 cpu->isar.id_aa64pfr0 = t; 1894 1895 u = cpu->isar.id_isar5; 1896 u = FIELD_DP32(u, ID_ISAR5, AES, 0); 1897 u = FIELD_DP32(u, ID_ISAR5, SHA1, 0); 1898 u = FIELD_DP32(u, ID_ISAR5, SHA2, 0); 1899 u = FIELD_DP32(u, ID_ISAR5, RDM, 0); 1900 u = FIELD_DP32(u, ID_ISAR5, VCMA, 0); 1901 cpu->isar.id_isar5 = u; 1902 1903 u = cpu->isar.id_isar6; 1904 u = FIELD_DP32(u, ID_ISAR6, DP, 0); 1905 u = FIELD_DP32(u, ID_ISAR6, FHM, 0); 1906 u = FIELD_DP32(u, ID_ISAR6, BF16, 0); 1907 u = FIELD_DP32(u, ID_ISAR6, I8MM, 0); 1908 cpu->isar.id_isar6 = u; 1909 1910 if (!arm_feature(env, ARM_FEATURE_M)) { 1911 u = cpu->isar.mvfr1; 1912 u = FIELD_DP32(u, MVFR1, SIMDLS, 0); 1913 u = FIELD_DP32(u, MVFR1, SIMDINT, 0); 1914 u = FIELD_DP32(u, MVFR1, SIMDSP, 0); 1915 u = FIELD_DP32(u, MVFR1, SIMDHP, 0); 1916 cpu->isar.mvfr1 = u; 1917 1918 u = cpu->isar.mvfr2; 1919 u = FIELD_DP32(u, MVFR2, SIMDMISC, 0); 1920 cpu->isar.mvfr2 = u; 1921 } 1922 } 1923 1924 if (!cpu->has_neon && !cpu->has_vfp) { 1925 uint64_t t; 1926 uint32_t u; 1927 1928 t = cpu->isar.id_aa64isar0; 1929 t = FIELD_DP64(t, ID_AA64ISAR0, FHM, 0); 1930 cpu->isar.id_aa64isar0 = t; 1931 1932 t = cpu->isar.id_aa64isar1; 1933 t = FIELD_DP64(t, ID_AA64ISAR1, FRINTTS, 0); 1934 cpu->isar.id_aa64isar1 = t; 1935 1936 u = cpu->isar.mvfr0; 1937 u = FIELD_DP32(u, MVFR0, SIMDREG, 0); 1938 cpu->isar.mvfr0 = u; 1939 1940 /* Despite the name, this field covers both VFP and Neon */ 1941 u = cpu->isar.mvfr1; 1942 u = FIELD_DP32(u, MVFR1, SIMDFMAC, 0); 1943 cpu->isar.mvfr1 = u; 1944 } 1945 1946 if (arm_feature(env, ARM_FEATURE_M) && !cpu->has_dsp) { 1947 uint32_t u; 1948 1949 unset_feature(env, ARM_FEATURE_THUMB_DSP); 1950 1951 u = cpu->isar.id_isar1; 1952 u = FIELD_DP32(u, ID_ISAR1, EXTEND, 1); 1953 cpu->isar.id_isar1 = u; 1954 1955 u = cpu->isar.id_isar2; 1956 u = FIELD_DP32(u, ID_ISAR2, MULTU, 1); 1957 u = FIELD_DP32(u, ID_ISAR2, MULTS, 1); 1958 cpu->isar.id_isar2 = u; 1959 1960 u = cpu->isar.id_isar3; 1961 u = FIELD_DP32(u, ID_ISAR3, SIMD, 1); 1962 u = FIELD_DP32(u, ID_ISAR3, SATURATE, 0); 1963 cpu->isar.id_isar3 = u; 1964 } 1965 1966 1967 /* 1968 * We rely on no XScale CPU having VFP so we can use the same bits in the 1969 * TB flags field for VECSTRIDE and XSCALE_CPAR. 1970 */ 1971 assert(arm_feature(&cpu->env, ARM_FEATURE_AARCH64) || 1972 !cpu_isar_feature(aa32_vfp_simd, cpu) || 1973 !arm_feature(env, ARM_FEATURE_XSCALE)); 1974 1975 if (arm_feature(env, ARM_FEATURE_V7) && 1976 !arm_feature(env, ARM_FEATURE_M) && 1977 !arm_feature(env, ARM_FEATURE_PMSA)) { 1978 /* v7VMSA drops support for the old ARMv5 tiny pages, so we 1979 * can use 4K pages. 1980 */ 1981 pagebits = 12; 1982 } else { 1983 /* For CPUs which might have tiny 1K pages, or which have an 1984 * MPU and might have small region sizes, stick with 1K pages. 1985 */ 1986 pagebits = 10; 1987 } 1988 if (!set_preferred_target_page_bits(pagebits)) { 1989 /* This can only ever happen for hotplugging a CPU, or if 1990 * the board code incorrectly creates a CPU which it has 1991 * promised via minimum_page_size that it will not. 1992 */ 1993 error_setg(errp, "This CPU requires a smaller page size than the " 1994 "system is using"); 1995 return; 1996 } 1997 1998 /* This cpu-id-to-MPIDR affinity is used only for TCG; KVM will override it. 1999 * We don't support setting cluster ID ([16..23]) (known as Aff2 2000 * in later ARM ARM versions), or any of the higher affinity level fields, 2001 * so these bits always RAZ. 2002 */ 2003 if (cpu->mp_affinity == ARM64_AFFINITY_INVALID) { 2004 cpu->mp_affinity = arm_cpu_mp_affinity(cs->cpu_index, 2005 ARM_DEFAULT_CPUS_PER_CLUSTER); 2006 } 2007 2008 if (cpu->reset_hivecs) { 2009 cpu->reset_sctlr |= (1 << 13); 2010 } 2011 2012 if (cpu->cfgend) { 2013 if (arm_feature(&cpu->env, ARM_FEATURE_V7)) { 2014 cpu->reset_sctlr |= SCTLR_EE; 2015 } else { 2016 cpu->reset_sctlr |= SCTLR_B; 2017 } 2018 } 2019 2020 if (!arm_feature(env, ARM_FEATURE_M) && !cpu->has_el3) { 2021 /* If the has_el3 CPU property is disabled then we need to disable the 2022 * feature. 2023 */ 2024 unset_feature(env, ARM_FEATURE_EL3); 2025 2026 /* 2027 * Disable the security extension feature bits in the processor 2028 * feature registers as well. 2029 */ 2030 cpu->isar.id_pfr1 = FIELD_DP32(cpu->isar.id_pfr1, ID_PFR1, SECURITY, 0); 2031 cpu->isar.id_dfr0 = FIELD_DP32(cpu->isar.id_dfr0, ID_DFR0, COPSDBG, 0); 2032 cpu->isar.id_aa64pfr0 = FIELD_DP64(cpu->isar.id_aa64pfr0, 2033 ID_AA64PFR0, EL3, 0); 2034 2035 /* Disable the realm management extension, which requires EL3. */ 2036 cpu->isar.id_aa64pfr0 = FIELD_DP64(cpu->isar.id_aa64pfr0, 2037 ID_AA64PFR0, RME, 0); 2038 } 2039 2040 if (!cpu->has_el2) { 2041 unset_feature(env, ARM_FEATURE_EL2); 2042 } 2043 2044 if (!cpu->has_pmu) { 2045 unset_feature(env, ARM_FEATURE_PMU); 2046 } 2047 if (arm_feature(env, ARM_FEATURE_PMU)) { 2048 pmu_init(cpu); 2049 2050 if (!kvm_enabled()) { 2051 arm_register_pre_el_change_hook(cpu, &pmu_pre_el_change, 0); 2052 arm_register_el_change_hook(cpu, &pmu_post_el_change, 0); 2053 } 2054 2055 #ifndef CONFIG_USER_ONLY 2056 cpu->pmu_timer = timer_new_ns(QEMU_CLOCK_VIRTUAL, arm_pmu_timer_cb, 2057 cpu); 2058 #endif 2059 } else { 2060 cpu->isar.id_aa64dfr0 = 2061 FIELD_DP64(cpu->isar.id_aa64dfr0, ID_AA64DFR0, PMUVER, 0); 2062 cpu->isar.id_dfr0 = FIELD_DP32(cpu->isar.id_dfr0, ID_DFR0, PERFMON, 0); 2063 cpu->pmceid0 = 0; 2064 cpu->pmceid1 = 0; 2065 } 2066 2067 if (!arm_feature(env, ARM_FEATURE_EL2)) { 2068 /* 2069 * Disable the hypervisor feature bits in the processor feature 2070 * registers if we don't have EL2. 2071 */ 2072 cpu->isar.id_aa64pfr0 = FIELD_DP64(cpu->isar.id_aa64pfr0, 2073 ID_AA64PFR0, EL2, 0); 2074 cpu->isar.id_pfr1 = FIELD_DP32(cpu->isar.id_pfr1, 2075 ID_PFR1, VIRTUALIZATION, 0); 2076 } 2077 2078 if (cpu_isar_feature(aa64_mte, cpu)) { 2079 /* 2080 * The architectural range of GM blocksize is 2-6, however qemu 2081 * doesn't support blocksize of 2 (see HELPER(ldgm)). 2082 */ 2083 if (tcg_enabled()) { 2084 assert(cpu->gm_blocksize >= 3 && cpu->gm_blocksize <= 6); 2085 } 2086 2087 #ifndef CONFIG_USER_ONLY 2088 /* 2089 * If we do not have tag-memory provided by the machine, 2090 * reduce MTE support to instructions enabled at EL0. 2091 * This matches Cortex-A710 BROADCASTMTE input being LOW. 2092 */ 2093 if (cpu->tag_memory == NULL) { 2094 cpu->isar.id_aa64pfr1 = 2095 FIELD_DP64(cpu->isar.id_aa64pfr1, ID_AA64PFR1, MTE, 1); 2096 } 2097 #endif 2098 } 2099 2100 if (tcg_enabled()) { 2101 /* 2102 * Don't report some architectural features in the ID registers 2103 * where TCG does not yet implement it (not even a minimal 2104 * stub version). This avoids guests falling over when they 2105 * try to access the non-existent system registers for them. 2106 */ 2107 /* FEAT_SPE (Statistical Profiling Extension) */ 2108 cpu->isar.id_aa64dfr0 = 2109 FIELD_DP64(cpu->isar.id_aa64dfr0, ID_AA64DFR0, PMSVER, 0); 2110 /* FEAT_TRBE (Trace Buffer Extension) */ 2111 cpu->isar.id_aa64dfr0 = 2112 FIELD_DP64(cpu->isar.id_aa64dfr0, ID_AA64DFR0, TRACEBUFFER, 0); 2113 /* FEAT_TRF (Self-hosted Trace Extension) */ 2114 cpu->isar.id_aa64dfr0 = 2115 FIELD_DP64(cpu->isar.id_aa64dfr0, ID_AA64DFR0, TRACEFILT, 0); 2116 cpu->isar.id_dfr0 = 2117 FIELD_DP32(cpu->isar.id_dfr0, ID_DFR0, TRACEFILT, 0); 2118 /* Trace Macrocell system register access */ 2119 cpu->isar.id_aa64dfr0 = 2120 FIELD_DP64(cpu->isar.id_aa64dfr0, ID_AA64DFR0, TRACEVER, 0); 2121 cpu->isar.id_dfr0 = 2122 FIELD_DP32(cpu->isar.id_dfr0, ID_DFR0, COPTRC, 0); 2123 /* Memory mapped trace */ 2124 cpu->isar.id_dfr0 = 2125 FIELD_DP32(cpu->isar.id_dfr0, ID_DFR0, MMAPTRC, 0); 2126 /* FEAT_AMU (Activity Monitors Extension) */ 2127 cpu->isar.id_aa64pfr0 = 2128 FIELD_DP64(cpu->isar.id_aa64pfr0, ID_AA64PFR0, AMU, 0); 2129 cpu->isar.id_pfr0 = 2130 FIELD_DP32(cpu->isar.id_pfr0, ID_PFR0, AMU, 0); 2131 /* FEAT_MPAM (Memory Partitioning and Monitoring Extension) */ 2132 cpu->isar.id_aa64pfr0 = 2133 FIELD_DP64(cpu->isar.id_aa64pfr0, ID_AA64PFR0, MPAM, 0); 2134 /* FEAT_NV (Nested Virtualization) */ 2135 cpu->isar.id_aa64mmfr2 = 2136 FIELD_DP64(cpu->isar.id_aa64mmfr2, ID_AA64MMFR2, NV, 0); 2137 } 2138 2139 /* MPU can be configured out of a PMSA CPU either by setting has-mpu 2140 * to false or by setting pmsav7-dregion to 0. 2141 */ 2142 if (!cpu->has_mpu || cpu->pmsav7_dregion == 0) { 2143 cpu->has_mpu = false; 2144 cpu->pmsav7_dregion = 0; 2145 cpu->pmsav8r_hdregion = 0; 2146 } 2147 2148 if (arm_feature(env, ARM_FEATURE_PMSA) && 2149 arm_feature(env, ARM_FEATURE_V7)) { 2150 uint32_t nr = cpu->pmsav7_dregion; 2151 2152 if (nr > 0xff) { 2153 error_setg(errp, "PMSAv7 MPU #regions invalid %" PRIu32, nr); 2154 return; 2155 } 2156 2157 if (nr) { 2158 if (arm_feature(env, ARM_FEATURE_V8)) { 2159 /* PMSAv8 */ 2160 env->pmsav8.rbar[M_REG_NS] = g_new0(uint32_t, nr); 2161 env->pmsav8.rlar[M_REG_NS] = g_new0(uint32_t, nr); 2162 if (arm_feature(env, ARM_FEATURE_M_SECURITY)) { 2163 env->pmsav8.rbar[M_REG_S] = g_new0(uint32_t, nr); 2164 env->pmsav8.rlar[M_REG_S] = g_new0(uint32_t, nr); 2165 } 2166 } else { 2167 env->pmsav7.drbar = g_new0(uint32_t, nr); 2168 env->pmsav7.drsr = g_new0(uint32_t, nr); 2169 env->pmsav7.dracr = g_new0(uint32_t, nr); 2170 } 2171 } 2172 2173 if (cpu->pmsav8r_hdregion > 0xff) { 2174 error_setg(errp, "PMSAv8 MPU EL2 #regions invalid %" PRIu32, 2175 cpu->pmsav8r_hdregion); 2176 return; 2177 } 2178 2179 if (cpu->pmsav8r_hdregion) { 2180 env->pmsav8.hprbar = g_new0(uint32_t, 2181 cpu->pmsav8r_hdregion); 2182 env->pmsav8.hprlar = g_new0(uint32_t, 2183 cpu->pmsav8r_hdregion); 2184 } 2185 } 2186 2187 if (arm_feature(env, ARM_FEATURE_M_SECURITY)) { 2188 uint32_t nr = cpu->sau_sregion; 2189 2190 if (nr > 0xff) { 2191 error_setg(errp, "v8M SAU #regions invalid %" PRIu32, nr); 2192 return; 2193 } 2194 2195 if (nr) { 2196 env->sau.rbar = g_new0(uint32_t, nr); 2197 env->sau.rlar = g_new0(uint32_t, nr); 2198 } 2199 } 2200 2201 if (arm_feature(env, ARM_FEATURE_EL3)) { 2202 set_feature(env, ARM_FEATURE_VBAR); 2203 } 2204 2205 #ifndef CONFIG_USER_ONLY 2206 if (tcg_enabled() && cpu_isar_feature(aa64_rme, cpu)) { 2207 arm_register_el_change_hook(cpu, >_rme_post_el_change, 0); 2208 } 2209 #endif 2210 2211 register_cp_regs_for_features(cpu); 2212 arm_cpu_register_gdb_regs_for_features(cpu); 2213 2214 init_cpreg_list(cpu); 2215 2216 #ifndef CONFIG_USER_ONLY 2217 MachineState *ms = MACHINE(qdev_get_machine()); 2218 unsigned int smp_cpus = ms->smp.cpus; 2219 bool has_secure = cpu->has_el3 || arm_feature(env, ARM_FEATURE_M_SECURITY); 2220 2221 /* 2222 * We must set cs->num_ases to the final value before 2223 * the first call to cpu_address_space_init. 2224 */ 2225 if (cpu->tag_memory != NULL) { 2226 cs->num_ases = 3 + has_secure; 2227 } else { 2228 cs->num_ases = 1 + has_secure; 2229 } 2230 2231 if (has_secure) { 2232 if (!cpu->secure_memory) { 2233 cpu->secure_memory = cs->memory; 2234 } 2235 cpu_address_space_init(cs, ARMASIdx_S, "cpu-secure-memory", 2236 cpu->secure_memory); 2237 } 2238 2239 if (cpu->tag_memory != NULL) { 2240 cpu_address_space_init(cs, ARMASIdx_TagNS, "cpu-tag-memory", 2241 cpu->tag_memory); 2242 if (has_secure) { 2243 cpu_address_space_init(cs, ARMASIdx_TagS, "cpu-tag-memory", 2244 cpu->secure_tag_memory); 2245 } 2246 } 2247 2248 cpu_address_space_init(cs, ARMASIdx_NS, "cpu-memory", cs->memory); 2249 2250 /* No core_count specified, default to smp_cpus. */ 2251 if (cpu->core_count == -1) { 2252 cpu->core_count = smp_cpus; 2253 } 2254 #endif 2255 2256 if (tcg_enabled()) { 2257 int dcz_blocklen = 4 << cpu->dcz_blocksize; 2258 2259 /* 2260 * We only support DCZ blocklen that fits on one page. 2261 * 2262 * Architectually this is always true. However TARGET_PAGE_SIZE 2263 * is variable and, for compatibility with -machine virt-2.7, 2264 * is only 1KiB, as an artifact of legacy ARMv5 subpage support. 2265 * But even then, while the largest architectural DCZ blocklen 2266 * is 2KiB, no cpu actually uses such a large blocklen. 2267 */ 2268 assert(dcz_blocklen <= TARGET_PAGE_SIZE); 2269 2270 /* 2271 * We only support DCZ blocksize >= 2*TAG_GRANULE, which is to say 2272 * both nibbles of each byte storing tag data may be written at once. 2273 * Since TAG_GRANULE is 16, this means that blocklen must be >= 32. 2274 */ 2275 if (cpu_isar_feature(aa64_mte, cpu)) { 2276 assert(dcz_blocklen >= 2 * TAG_GRANULE); 2277 } 2278 } 2279 2280 qemu_init_vcpu(cs); 2281 cpu_reset(cs); 2282 2283 acc->parent_realize(dev, errp); 2284 } 2285 2286 static ObjectClass *arm_cpu_class_by_name(const char *cpu_model) 2287 { 2288 ObjectClass *oc; 2289 char *typename; 2290 char **cpuname; 2291 const char *cpunamestr; 2292 2293 cpuname = g_strsplit(cpu_model, ",", 1); 2294 cpunamestr = cpuname[0]; 2295 #ifdef CONFIG_USER_ONLY 2296 /* For backwards compatibility usermode emulation allows "-cpu any", 2297 * which has the same semantics as "-cpu max". 2298 */ 2299 if (!strcmp(cpunamestr, "any")) { 2300 cpunamestr = "max"; 2301 } 2302 #endif 2303 typename = g_strdup_printf(ARM_CPU_TYPE_NAME("%s"), cpunamestr); 2304 oc = object_class_by_name(typename); 2305 g_strfreev(cpuname); 2306 g_free(typename); 2307 if (!oc || !object_class_dynamic_cast(oc, TYPE_ARM_CPU) || 2308 object_class_is_abstract(oc)) { 2309 return NULL; 2310 } 2311 return oc; 2312 } 2313 2314 static Property arm_cpu_properties[] = { 2315 DEFINE_PROP_UINT64("midr", ARMCPU, midr, 0), 2316 DEFINE_PROP_UINT64("mp-affinity", ARMCPU, 2317 mp_affinity, ARM64_AFFINITY_INVALID), 2318 DEFINE_PROP_INT32("node-id", ARMCPU, node_id, CPU_UNSET_NUMA_NODE_ID), 2319 DEFINE_PROP_INT32("core-count", ARMCPU, core_count, -1), 2320 DEFINE_PROP_END_OF_LIST() 2321 }; 2322 2323 static gchar *arm_gdb_arch_name(CPUState *cs) 2324 { 2325 ARMCPU *cpu = ARM_CPU(cs); 2326 CPUARMState *env = &cpu->env; 2327 2328 if (arm_feature(env, ARM_FEATURE_IWMMXT)) { 2329 return g_strdup("iwmmxt"); 2330 } 2331 return g_strdup("arm"); 2332 } 2333 2334 #ifndef CONFIG_USER_ONLY 2335 #include "hw/core/sysemu-cpu-ops.h" 2336 2337 static const struct SysemuCPUOps arm_sysemu_ops = { 2338 .get_phys_page_attrs_debug = arm_cpu_get_phys_page_attrs_debug, 2339 .asidx_from_attrs = arm_asidx_from_attrs, 2340 .write_elf32_note = arm_cpu_write_elf32_note, 2341 .write_elf64_note = arm_cpu_write_elf64_note, 2342 .virtio_is_big_endian = arm_cpu_virtio_is_big_endian, 2343 .legacy_vmsd = &vmstate_arm_cpu, 2344 }; 2345 #endif 2346 2347 #ifdef CONFIG_TCG 2348 static const struct TCGCPUOps arm_tcg_ops = { 2349 .initialize = arm_translate_init, 2350 .synchronize_from_tb = arm_cpu_synchronize_from_tb, 2351 .debug_excp_handler = arm_debug_excp_handler, 2352 .restore_state_to_opc = arm_restore_state_to_opc, 2353 2354 #ifdef CONFIG_USER_ONLY 2355 .record_sigsegv = arm_cpu_record_sigsegv, 2356 .record_sigbus = arm_cpu_record_sigbus, 2357 #else 2358 .tlb_fill = arm_cpu_tlb_fill, 2359 .cpu_exec_interrupt = arm_cpu_exec_interrupt, 2360 .do_interrupt = arm_cpu_do_interrupt, 2361 .do_transaction_failed = arm_cpu_do_transaction_failed, 2362 .do_unaligned_access = arm_cpu_do_unaligned_access, 2363 .adjust_watchpoint_address = arm_adjust_watchpoint_address, 2364 .debug_check_watchpoint = arm_debug_check_watchpoint, 2365 .debug_check_breakpoint = arm_debug_check_breakpoint, 2366 #endif /* !CONFIG_USER_ONLY */ 2367 }; 2368 #endif /* CONFIG_TCG */ 2369 2370 static void arm_cpu_class_init(ObjectClass *oc, void *data) 2371 { 2372 ARMCPUClass *acc = ARM_CPU_CLASS(oc); 2373 CPUClass *cc = CPU_CLASS(acc); 2374 DeviceClass *dc = DEVICE_CLASS(oc); 2375 ResettableClass *rc = RESETTABLE_CLASS(oc); 2376 2377 device_class_set_parent_realize(dc, arm_cpu_realizefn, 2378 &acc->parent_realize); 2379 2380 device_class_set_props(dc, arm_cpu_properties); 2381 2382 resettable_class_set_parent_phases(rc, NULL, arm_cpu_reset_hold, NULL, 2383 &acc->parent_phases); 2384 2385 cc->class_by_name = arm_cpu_class_by_name; 2386 cc->has_work = arm_cpu_has_work; 2387 cc->dump_state = arm_cpu_dump_state; 2388 cc->set_pc = arm_cpu_set_pc; 2389 cc->get_pc = arm_cpu_get_pc; 2390 cc->gdb_read_register = arm_cpu_gdb_read_register; 2391 cc->gdb_write_register = arm_cpu_gdb_write_register; 2392 #ifndef CONFIG_USER_ONLY 2393 cc->sysemu_ops = &arm_sysemu_ops; 2394 #endif 2395 cc->gdb_num_core_regs = 26; 2396 cc->gdb_core_xml_file = "arm-core.xml"; 2397 cc->gdb_arch_name = arm_gdb_arch_name; 2398 cc->gdb_get_dynamic_xml = arm_gdb_get_dynamic_xml; 2399 cc->gdb_stop_before_watchpoint = true; 2400 cc->disas_set_info = arm_disas_set_info; 2401 2402 #ifdef CONFIG_TCG 2403 cc->tcg_ops = &arm_tcg_ops; 2404 #endif /* CONFIG_TCG */ 2405 } 2406 2407 static void arm_cpu_instance_init(Object *obj) 2408 { 2409 ARMCPUClass *acc = ARM_CPU_GET_CLASS(obj); 2410 2411 acc->info->initfn(obj); 2412 arm_cpu_post_init(obj); 2413 } 2414 2415 static void cpu_register_class_init(ObjectClass *oc, void *data) 2416 { 2417 ARMCPUClass *acc = ARM_CPU_CLASS(oc); 2418 2419 acc->info = data; 2420 } 2421 2422 void arm_cpu_register(const ARMCPUInfo *info) 2423 { 2424 TypeInfo type_info = { 2425 .parent = TYPE_ARM_CPU, 2426 .instance_size = sizeof(ARMCPU), 2427 .instance_align = __alignof__(ARMCPU), 2428 .instance_init = arm_cpu_instance_init, 2429 .class_size = sizeof(ARMCPUClass), 2430 .class_init = info->class_init ?: cpu_register_class_init, 2431 .class_data = (void *)info, 2432 }; 2433 2434 type_info.name = g_strdup_printf("%s-" TYPE_ARM_CPU, info->name); 2435 type_register(&type_info); 2436 g_free((void *)type_info.name); 2437 } 2438 2439 static const TypeInfo arm_cpu_type_info = { 2440 .name = TYPE_ARM_CPU, 2441 .parent = TYPE_CPU, 2442 .instance_size = sizeof(ARMCPU), 2443 .instance_align = __alignof__(ARMCPU), 2444 .instance_init = arm_cpu_initfn, 2445 .instance_finalize = arm_cpu_finalizefn, 2446 .abstract = true, 2447 .class_size = sizeof(ARMCPUClass), 2448 .class_init = arm_cpu_class_init, 2449 }; 2450 2451 static void arm_cpu_register_types(void) 2452 { 2453 type_register_static(&arm_cpu_type_info); 2454 } 2455 2456 type_init(arm_cpu_register_types) 2457