1 /* 2 * QEMU ARM CPU 3 * 4 * Copyright (c) 2012 SUSE LINUX Products GmbH 5 * 6 * This program is free software; you can redistribute it and/or 7 * modify it under the terms of the GNU General Public License 8 * as published by the Free Software Foundation; either version 2 9 * of the License, or (at your option) any later version. 10 * 11 * This program is distributed in the hope that it will be useful, 12 * but WITHOUT ANY WARRANTY; without even the implied warranty of 13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 14 * GNU General Public License for more details. 15 * 16 * You should have received a copy of the GNU General Public License 17 * along with this program; if not, see 18 * <http://www.gnu.org/licenses/gpl-2.0.html> 19 */ 20 21 #include "qemu/osdep.h" 22 #include "qemu/error-report.h" 23 #include "qapi/error.h" 24 #include "cpu.h" 25 #include "internals.h" 26 #include "qemu-common.h" 27 #include "exec/exec-all.h" 28 #include "hw/qdev-properties.h" 29 #if !defined(CONFIG_USER_ONLY) 30 #include "hw/loader.h" 31 #endif 32 #include "hw/arm/arm.h" 33 #include "sysemu/sysemu.h" 34 #include "sysemu/hw_accel.h" 35 #include "kvm_arm.h" 36 37 static void arm_cpu_set_pc(CPUState *cs, vaddr value) 38 { 39 ARMCPU *cpu = ARM_CPU(cs); 40 41 cpu->env.regs[15] = value; 42 } 43 44 static bool arm_cpu_has_work(CPUState *cs) 45 { 46 ARMCPU *cpu = ARM_CPU(cs); 47 48 return (cpu->power_state != PSCI_OFF) 49 && cs->interrupt_request & 50 (CPU_INTERRUPT_FIQ | CPU_INTERRUPT_HARD 51 | CPU_INTERRUPT_VFIQ | CPU_INTERRUPT_VIRQ 52 | CPU_INTERRUPT_EXITTB); 53 } 54 55 void arm_register_el_change_hook(ARMCPU *cpu, ARMELChangeHook *hook, 56 void *opaque) 57 { 58 /* We currently only support registering a single hook function */ 59 assert(!cpu->el_change_hook); 60 cpu->el_change_hook = hook; 61 cpu->el_change_hook_opaque = opaque; 62 } 63 64 static void cp_reg_reset(gpointer key, gpointer value, gpointer opaque) 65 { 66 /* Reset a single ARMCPRegInfo register */ 67 ARMCPRegInfo *ri = value; 68 ARMCPU *cpu = opaque; 69 70 if (ri->type & (ARM_CP_SPECIAL | ARM_CP_ALIAS)) { 71 return; 72 } 73 74 if (ri->resetfn) { 75 ri->resetfn(&cpu->env, ri); 76 return; 77 } 78 79 /* A zero offset is never possible as it would be regs[0] 80 * so we use it to indicate that reset is being handled elsewhere. 81 * This is basically only used for fields in non-core coprocessors 82 * (like the pxa2xx ones). 83 */ 84 if (!ri->fieldoffset) { 85 return; 86 } 87 88 if (cpreg_field_is_64bit(ri)) { 89 CPREG_FIELD64(&cpu->env, ri) = ri->resetvalue; 90 } else { 91 CPREG_FIELD32(&cpu->env, ri) = ri->resetvalue; 92 } 93 } 94 95 static void cp_reg_check_reset(gpointer key, gpointer value, gpointer opaque) 96 { 97 /* Purely an assertion check: we've already done reset once, 98 * so now check that running the reset for the cpreg doesn't 99 * change its value. This traps bugs where two different cpregs 100 * both try to reset the same state field but to different values. 101 */ 102 ARMCPRegInfo *ri = value; 103 ARMCPU *cpu = opaque; 104 uint64_t oldvalue, newvalue; 105 106 if (ri->type & (ARM_CP_SPECIAL | ARM_CP_ALIAS | ARM_CP_NO_RAW)) { 107 return; 108 } 109 110 oldvalue = read_raw_cp_reg(&cpu->env, ri); 111 cp_reg_reset(key, value, opaque); 112 newvalue = read_raw_cp_reg(&cpu->env, ri); 113 assert(oldvalue == newvalue); 114 } 115 116 /* CPUClass::reset() */ 117 static void arm_cpu_reset(CPUState *s) 118 { 119 ARMCPU *cpu = ARM_CPU(s); 120 ARMCPUClass *acc = ARM_CPU_GET_CLASS(cpu); 121 CPUARMState *env = &cpu->env; 122 123 acc->parent_reset(s); 124 125 memset(env, 0, offsetof(CPUARMState, end_reset_fields)); 126 127 g_hash_table_foreach(cpu->cp_regs, cp_reg_reset, cpu); 128 g_hash_table_foreach(cpu->cp_regs, cp_reg_check_reset, cpu); 129 130 env->vfp.xregs[ARM_VFP_FPSID] = cpu->reset_fpsid; 131 env->vfp.xregs[ARM_VFP_MVFR0] = cpu->mvfr0; 132 env->vfp.xregs[ARM_VFP_MVFR1] = cpu->mvfr1; 133 env->vfp.xregs[ARM_VFP_MVFR2] = cpu->mvfr2; 134 135 cpu->power_state = cpu->start_powered_off ? PSCI_OFF : PSCI_ON; 136 s->halted = cpu->start_powered_off; 137 138 if (arm_feature(env, ARM_FEATURE_IWMMXT)) { 139 env->iwmmxt.cregs[ARM_IWMMXT_wCID] = 0x69051000 | 'Q'; 140 } 141 142 if (arm_feature(env, ARM_FEATURE_AARCH64)) { 143 /* 64 bit CPUs always start in 64 bit mode */ 144 env->aarch64 = 1; 145 #if defined(CONFIG_USER_ONLY) 146 env->pstate = PSTATE_MODE_EL0t; 147 /* Userspace expects access to DC ZVA, CTL_EL0 and the cache ops */ 148 env->cp15.sctlr_el[1] |= SCTLR_UCT | SCTLR_UCI | SCTLR_DZE; 149 /* and to the FP/Neon instructions */ 150 env->cp15.cpacr_el1 = deposit64(env->cp15.cpacr_el1, 20, 2, 3); 151 #else 152 /* Reset into the highest available EL */ 153 if (arm_feature(env, ARM_FEATURE_EL3)) { 154 env->pstate = PSTATE_MODE_EL3h; 155 } else if (arm_feature(env, ARM_FEATURE_EL2)) { 156 env->pstate = PSTATE_MODE_EL2h; 157 } else { 158 env->pstate = PSTATE_MODE_EL1h; 159 } 160 env->pc = cpu->rvbar; 161 #endif 162 } else { 163 #if defined(CONFIG_USER_ONLY) 164 /* Userspace expects access to cp10 and cp11 for FP/Neon */ 165 env->cp15.cpacr_el1 = deposit64(env->cp15.cpacr_el1, 20, 4, 0xf); 166 #endif 167 } 168 169 #if defined(CONFIG_USER_ONLY) 170 env->uncached_cpsr = ARM_CPU_MODE_USR; 171 /* For user mode we must enable access to coprocessors */ 172 env->vfp.xregs[ARM_VFP_FPEXC] = 1 << 30; 173 if (arm_feature(env, ARM_FEATURE_IWMMXT)) { 174 env->cp15.c15_cpar = 3; 175 } else if (arm_feature(env, ARM_FEATURE_XSCALE)) { 176 env->cp15.c15_cpar = 1; 177 } 178 #else 179 /* SVC mode with interrupts disabled. */ 180 env->uncached_cpsr = ARM_CPU_MODE_SVC; 181 env->daif = PSTATE_D | PSTATE_A | PSTATE_I | PSTATE_F; 182 183 if (arm_feature(env, ARM_FEATURE_M)) { 184 uint32_t initial_msp; /* Loaded from 0x0 */ 185 uint32_t initial_pc; /* Loaded from 0x4 */ 186 uint8_t *rom; 187 188 if (arm_feature(env, ARM_FEATURE_M_SECURITY)) { 189 env->v7m.secure = true; 190 } 191 192 /* In v7M the reset value of this bit is IMPDEF, but ARM recommends 193 * that it resets to 1, so QEMU always does that rather than making 194 * it dependent on CPU model. In v8M it is RES1. 195 */ 196 env->v7m.ccr[M_REG_NS] = R_V7M_CCR_STKALIGN_MASK; 197 env->v7m.ccr[M_REG_S] = R_V7M_CCR_STKALIGN_MASK; 198 if (arm_feature(env, ARM_FEATURE_V8)) { 199 /* in v8M the NONBASETHRDENA bit [0] is RES1 */ 200 env->v7m.ccr[M_REG_NS] |= R_V7M_CCR_NONBASETHRDENA_MASK; 201 env->v7m.ccr[M_REG_S] |= R_V7M_CCR_NONBASETHRDENA_MASK; 202 } 203 204 /* Unlike A/R profile, M profile defines the reset LR value */ 205 env->regs[14] = 0xffffffff; 206 207 /* Load the initial SP and PC from the vector table at address 0 */ 208 rom = rom_ptr(0); 209 if (rom) { 210 /* Address zero is covered by ROM which hasn't yet been 211 * copied into physical memory. 212 */ 213 initial_msp = ldl_p(rom); 214 initial_pc = ldl_p(rom + 4); 215 } else { 216 /* Address zero not covered by a ROM blob, or the ROM blob 217 * is in non-modifiable memory and this is a second reset after 218 * it got copied into memory. In the latter case, rom_ptr 219 * will return a NULL pointer and we should use ldl_phys instead. 220 */ 221 initial_msp = ldl_phys(s->as, 0); 222 initial_pc = ldl_phys(s->as, 4); 223 } 224 225 env->regs[13] = initial_msp & 0xFFFFFFFC; 226 env->regs[15] = initial_pc & ~1; 227 env->thumb = initial_pc & 1; 228 } 229 230 /* AArch32 has a hard highvec setting of 0xFFFF0000. If we are currently 231 * executing as AArch32 then check if highvecs are enabled and 232 * adjust the PC accordingly. 233 */ 234 if (A32_BANKED_CURRENT_REG_GET(env, sctlr) & SCTLR_V) { 235 env->regs[15] = 0xFFFF0000; 236 } 237 238 /* M profile requires that reset clears the exclusive monitor; 239 * A profile does not, but clearing it makes more sense than having it 240 * set with an exclusive access on address zero. 241 */ 242 arm_clear_exclusive(env); 243 244 env->vfp.xregs[ARM_VFP_FPEXC] = 0; 245 #endif 246 247 if (arm_feature(env, ARM_FEATURE_PMSA)) { 248 if (cpu->pmsav7_dregion > 0) { 249 if (arm_feature(env, ARM_FEATURE_V8)) { 250 memset(env->pmsav8.rbar[M_REG_NS], 0, 251 sizeof(*env->pmsav8.rbar[M_REG_NS]) 252 * cpu->pmsav7_dregion); 253 memset(env->pmsav8.rlar[M_REG_NS], 0, 254 sizeof(*env->pmsav8.rlar[M_REG_NS]) 255 * cpu->pmsav7_dregion); 256 if (arm_feature(env, ARM_FEATURE_M_SECURITY)) { 257 memset(env->pmsav8.rbar[M_REG_S], 0, 258 sizeof(*env->pmsav8.rbar[M_REG_S]) 259 * cpu->pmsav7_dregion); 260 memset(env->pmsav8.rlar[M_REG_S], 0, 261 sizeof(*env->pmsav8.rlar[M_REG_S]) 262 * cpu->pmsav7_dregion); 263 } 264 } else if (arm_feature(env, ARM_FEATURE_V7)) { 265 memset(env->pmsav7.drbar, 0, 266 sizeof(*env->pmsav7.drbar) * cpu->pmsav7_dregion); 267 memset(env->pmsav7.drsr, 0, 268 sizeof(*env->pmsav7.drsr) * cpu->pmsav7_dregion); 269 memset(env->pmsav7.dracr, 0, 270 sizeof(*env->pmsav7.dracr) * cpu->pmsav7_dregion); 271 } 272 } 273 env->pmsav7.rnr[M_REG_NS] = 0; 274 env->pmsav7.rnr[M_REG_S] = 0; 275 env->pmsav8.mair0[M_REG_NS] = 0; 276 env->pmsav8.mair0[M_REG_S] = 0; 277 env->pmsav8.mair1[M_REG_NS] = 0; 278 env->pmsav8.mair1[M_REG_S] = 0; 279 } 280 281 set_flush_to_zero(1, &env->vfp.standard_fp_status); 282 set_flush_inputs_to_zero(1, &env->vfp.standard_fp_status); 283 set_default_nan_mode(1, &env->vfp.standard_fp_status); 284 set_float_detect_tininess(float_tininess_before_rounding, 285 &env->vfp.fp_status); 286 set_float_detect_tininess(float_tininess_before_rounding, 287 &env->vfp.standard_fp_status); 288 #ifndef CONFIG_USER_ONLY 289 if (kvm_enabled()) { 290 kvm_arm_reset_vcpu(cpu); 291 } 292 #endif 293 294 hw_breakpoint_update_all(cpu); 295 hw_watchpoint_update_all(cpu); 296 } 297 298 bool arm_cpu_exec_interrupt(CPUState *cs, int interrupt_request) 299 { 300 CPUClass *cc = CPU_GET_CLASS(cs); 301 CPUARMState *env = cs->env_ptr; 302 uint32_t cur_el = arm_current_el(env); 303 bool secure = arm_is_secure(env); 304 uint32_t target_el; 305 uint32_t excp_idx; 306 bool ret = false; 307 308 if (interrupt_request & CPU_INTERRUPT_FIQ) { 309 excp_idx = EXCP_FIQ; 310 target_el = arm_phys_excp_target_el(cs, excp_idx, cur_el, secure); 311 if (arm_excp_unmasked(cs, excp_idx, target_el)) { 312 cs->exception_index = excp_idx; 313 env->exception.target_el = target_el; 314 cc->do_interrupt(cs); 315 ret = true; 316 } 317 } 318 if (interrupt_request & CPU_INTERRUPT_HARD) { 319 excp_idx = EXCP_IRQ; 320 target_el = arm_phys_excp_target_el(cs, excp_idx, cur_el, secure); 321 if (arm_excp_unmasked(cs, excp_idx, target_el)) { 322 cs->exception_index = excp_idx; 323 env->exception.target_el = target_el; 324 cc->do_interrupt(cs); 325 ret = true; 326 } 327 } 328 if (interrupt_request & CPU_INTERRUPT_VIRQ) { 329 excp_idx = EXCP_VIRQ; 330 target_el = 1; 331 if (arm_excp_unmasked(cs, excp_idx, target_el)) { 332 cs->exception_index = excp_idx; 333 env->exception.target_el = target_el; 334 cc->do_interrupt(cs); 335 ret = true; 336 } 337 } 338 if (interrupt_request & CPU_INTERRUPT_VFIQ) { 339 excp_idx = EXCP_VFIQ; 340 target_el = 1; 341 if (arm_excp_unmasked(cs, excp_idx, target_el)) { 342 cs->exception_index = excp_idx; 343 env->exception.target_el = target_el; 344 cc->do_interrupt(cs); 345 ret = true; 346 } 347 } 348 349 return ret; 350 } 351 352 #if !defined(CONFIG_USER_ONLY) || !defined(TARGET_AARCH64) 353 static bool arm_v7m_cpu_exec_interrupt(CPUState *cs, int interrupt_request) 354 { 355 CPUClass *cc = CPU_GET_CLASS(cs); 356 ARMCPU *cpu = ARM_CPU(cs); 357 CPUARMState *env = &cpu->env; 358 bool ret = false; 359 360 /* ARMv7-M interrupt masking works differently than -A or -R. 361 * There is no FIQ/IRQ distinction. Instead of I and F bits 362 * masking FIQ and IRQ interrupts, an exception is taken only 363 * if it is higher priority than the current execution priority 364 * (which depends on state like BASEPRI, FAULTMASK and the 365 * currently active exception). 366 */ 367 if (interrupt_request & CPU_INTERRUPT_HARD 368 && (armv7m_nvic_can_take_pending_exception(env->nvic))) { 369 cs->exception_index = EXCP_IRQ; 370 cc->do_interrupt(cs); 371 ret = true; 372 } 373 return ret; 374 } 375 #endif 376 377 #ifndef CONFIG_USER_ONLY 378 static void arm_cpu_set_irq(void *opaque, int irq, int level) 379 { 380 ARMCPU *cpu = opaque; 381 CPUARMState *env = &cpu->env; 382 CPUState *cs = CPU(cpu); 383 static const int mask[] = { 384 [ARM_CPU_IRQ] = CPU_INTERRUPT_HARD, 385 [ARM_CPU_FIQ] = CPU_INTERRUPT_FIQ, 386 [ARM_CPU_VIRQ] = CPU_INTERRUPT_VIRQ, 387 [ARM_CPU_VFIQ] = CPU_INTERRUPT_VFIQ 388 }; 389 390 switch (irq) { 391 case ARM_CPU_VIRQ: 392 case ARM_CPU_VFIQ: 393 assert(arm_feature(env, ARM_FEATURE_EL2)); 394 /* fall through */ 395 case ARM_CPU_IRQ: 396 case ARM_CPU_FIQ: 397 if (level) { 398 cpu_interrupt(cs, mask[irq]); 399 } else { 400 cpu_reset_interrupt(cs, mask[irq]); 401 } 402 break; 403 default: 404 g_assert_not_reached(); 405 } 406 } 407 408 static void arm_cpu_kvm_set_irq(void *opaque, int irq, int level) 409 { 410 #ifdef CONFIG_KVM 411 ARMCPU *cpu = opaque; 412 CPUState *cs = CPU(cpu); 413 int kvm_irq = KVM_ARM_IRQ_TYPE_CPU << KVM_ARM_IRQ_TYPE_SHIFT; 414 415 switch (irq) { 416 case ARM_CPU_IRQ: 417 kvm_irq |= KVM_ARM_IRQ_CPU_IRQ; 418 break; 419 case ARM_CPU_FIQ: 420 kvm_irq |= KVM_ARM_IRQ_CPU_FIQ; 421 break; 422 default: 423 g_assert_not_reached(); 424 } 425 kvm_irq |= cs->cpu_index << KVM_ARM_IRQ_VCPU_SHIFT; 426 kvm_set_irq(kvm_state, kvm_irq, level ? 1 : 0); 427 #endif 428 } 429 430 static bool arm_cpu_virtio_is_big_endian(CPUState *cs) 431 { 432 ARMCPU *cpu = ARM_CPU(cs); 433 CPUARMState *env = &cpu->env; 434 435 cpu_synchronize_state(cs); 436 return arm_cpu_data_is_big_endian(env); 437 } 438 439 #endif 440 441 static inline void set_feature(CPUARMState *env, int feature) 442 { 443 env->features |= 1ULL << feature; 444 } 445 446 static inline void unset_feature(CPUARMState *env, int feature) 447 { 448 env->features &= ~(1ULL << feature); 449 } 450 451 static int 452 print_insn_thumb1(bfd_vma pc, disassemble_info *info) 453 { 454 return print_insn_arm(pc | 1, info); 455 } 456 457 static int arm_read_memory_func(bfd_vma memaddr, bfd_byte *b, 458 int length, struct disassemble_info *info) 459 { 460 assert(info->read_memory_inner_func); 461 assert((info->flags & INSN_ARM_BE32) == 0 || length == 2 || length == 4); 462 463 if ((info->flags & INSN_ARM_BE32) != 0 && length == 2) { 464 assert(info->endian == BFD_ENDIAN_LITTLE); 465 return info->read_memory_inner_func(memaddr ^ 2, (bfd_byte *)b, 2, 466 info); 467 } else { 468 return info->read_memory_inner_func(memaddr, b, length, info); 469 } 470 } 471 472 static void arm_disas_set_info(CPUState *cpu, disassemble_info *info) 473 { 474 ARMCPU *ac = ARM_CPU(cpu); 475 CPUARMState *env = &ac->env; 476 477 if (is_a64(env)) { 478 /* We might not be compiled with the A64 disassembler 479 * because it needs a C++ compiler. Leave print_insn 480 * unset in this case to use the caller default behaviour. 481 */ 482 #if defined(CONFIG_ARM_A64_DIS) 483 info->print_insn = print_insn_arm_a64; 484 #endif 485 } else if (env->thumb) { 486 info->print_insn = print_insn_thumb1; 487 } else { 488 info->print_insn = print_insn_arm; 489 } 490 if (bswap_code(arm_sctlr_b(env))) { 491 #ifdef TARGET_WORDS_BIGENDIAN 492 info->endian = BFD_ENDIAN_LITTLE; 493 #else 494 info->endian = BFD_ENDIAN_BIG; 495 #endif 496 } 497 if (info->read_memory_inner_func == NULL) { 498 info->read_memory_inner_func = info->read_memory_func; 499 info->read_memory_func = arm_read_memory_func; 500 } 501 info->flags &= ~INSN_ARM_BE32; 502 if (arm_sctlr_b(env)) { 503 info->flags |= INSN_ARM_BE32; 504 } 505 } 506 507 uint64_t arm_cpu_mp_affinity(int idx, uint8_t clustersz) 508 { 509 uint32_t Aff1 = idx / clustersz; 510 uint32_t Aff0 = idx % clustersz; 511 return (Aff1 << ARM_AFF1_SHIFT) | Aff0; 512 } 513 514 static void arm_cpu_initfn(Object *obj) 515 { 516 CPUState *cs = CPU(obj); 517 ARMCPU *cpu = ARM_CPU(obj); 518 static bool inited; 519 520 cs->env_ptr = &cpu->env; 521 cpu->cp_regs = g_hash_table_new_full(g_int_hash, g_int_equal, 522 g_free, g_free); 523 524 #ifndef CONFIG_USER_ONLY 525 /* Our inbound IRQ and FIQ lines */ 526 if (kvm_enabled()) { 527 /* VIRQ and VFIQ are unused with KVM but we add them to maintain 528 * the same interface as non-KVM CPUs. 529 */ 530 qdev_init_gpio_in(DEVICE(cpu), arm_cpu_kvm_set_irq, 4); 531 } else { 532 qdev_init_gpio_in(DEVICE(cpu), arm_cpu_set_irq, 4); 533 } 534 535 cpu->gt_timer[GTIMER_PHYS] = timer_new(QEMU_CLOCK_VIRTUAL, GTIMER_SCALE, 536 arm_gt_ptimer_cb, cpu); 537 cpu->gt_timer[GTIMER_VIRT] = timer_new(QEMU_CLOCK_VIRTUAL, GTIMER_SCALE, 538 arm_gt_vtimer_cb, cpu); 539 cpu->gt_timer[GTIMER_HYP] = timer_new(QEMU_CLOCK_VIRTUAL, GTIMER_SCALE, 540 arm_gt_htimer_cb, cpu); 541 cpu->gt_timer[GTIMER_SEC] = timer_new(QEMU_CLOCK_VIRTUAL, GTIMER_SCALE, 542 arm_gt_stimer_cb, cpu); 543 qdev_init_gpio_out(DEVICE(cpu), cpu->gt_timer_outputs, 544 ARRAY_SIZE(cpu->gt_timer_outputs)); 545 546 qdev_init_gpio_out_named(DEVICE(cpu), &cpu->gicv3_maintenance_interrupt, 547 "gicv3-maintenance-interrupt", 1); 548 qdev_init_gpio_out_named(DEVICE(cpu), &cpu->pmu_interrupt, 549 "pmu-interrupt", 1); 550 #endif 551 552 /* DTB consumers generally don't in fact care what the 'compatible' 553 * string is, so always provide some string and trust that a hypothetical 554 * picky DTB consumer will also provide a helpful error message. 555 */ 556 cpu->dtb_compatible = "qemu,unknown"; 557 cpu->psci_version = 1; /* By default assume PSCI v0.1 */ 558 cpu->kvm_target = QEMU_KVM_ARM_TARGET_NONE; 559 560 if (tcg_enabled()) { 561 cpu->psci_version = 2; /* TCG implements PSCI 0.2 */ 562 if (!inited) { 563 inited = true; 564 arm_translate_init(); 565 } 566 } 567 } 568 569 static Property arm_cpu_reset_cbar_property = 570 DEFINE_PROP_UINT64("reset-cbar", ARMCPU, reset_cbar, 0); 571 572 static Property arm_cpu_reset_hivecs_property = 573 DEFINE_PROP_BOOL("reset-hivecs", ARMCPU, reset_hivecs, false); 574 575 static Property arm_cpu_rvbar_property = 576 DEFINE_PROP_UINT64("rvbar", ARMCPU, rvbar, 0); 577 578 static Property arm_cpu_has_el2_property = 579 DEFINE_PROP_BOOL("has_el2", ARMCPU, has_el2, true); 580 581 static Property arm_cpu_has_el3_property = 582 DEFINE_PROP_BOOL("has_el3", ARMCPU, has_el3, true); 583 584 static Property arm_cpu_cfgend_property = 585 DEFINE_PROP_BOOL("cfgend", ARMCPU, cfgend, false); 586 587 /* use property name "pmu" to match other archs and virt tools */ 588 static Property arm_cpu_has_pmu_property = 589 DEFINE_PROP_BOOL("pmu", ARMCPU, has_pmu, true); 590 591 static Property arm_cpu_has_mpu_property = 592 DEFINE_PROP_BOOL("has-mpu", ARMCPU, has_mpu, true); 593 594 /* This is like DEFINE_PROP_UINT32 but it doesn't set the default value, 595 * because the CPU initfn will have already set cpu->pmsav7_dregion to 596 * the right value for that particular CPU type, and we don't want 597 * to override that with an incorrect constant value. 598 */ 599 static Property arm_cpu_pmsav7_dregion_property = 600 DEFINE_PROP_UNSIGNED_NODEFAULT("pmsav7-dregion", ARMCPU, 601 pmsav7_dregion, 602 qdev_prop_uint32, uint32_t); 603 604 static void arm_cpu_post_init(Object *obj) 605 { 606 ARMCPU *cpu = ARM_CPU(obj); 607 608 /* M profile implies PMSA. We have to do this here rather than 609 * in realize with the other feature-implication checks because 610 * we look at the PMSA bit to see if we should add some properties. 611 */ 612 if (arm_feature(&cpu->env, ARM_FEATURE_M)) { 613 set_feature(&cpu->env, ARM_FEATURE_PMSA); 614 } 615 616 if (arm_feature(&cpu->env, ARM_FEATURE_CBAR) || 617 arm_feature(&cpu->env, ARM_FEATURE_CBAR_RO)) { 618 qdev_property_add_static(DEVICE(obj), &arm_cpu_reset_cbar_property, 619 &error_abort); 620 } 621 622 if (!arm_feature(&cpu->env, ARM_FEATURE_M)) { 623 qdev_property_add_static(DEVICE(obj), &arm_cpu_reset_hivecs_property, 624 &error_abort); 625 } 626 627 if (arm_feature(&cpu->env, ARM_FEATURE_AARCH64)) { 628 qdev_property_add_static(DEVICE(obj), &arm_cpu_rvbar_property, 629 &error_abort); 630 } 631 632 if (arm_feature(&cpu->env, ARM_FEATURE_EL3)) { 633 /* Add the has_el3 state CPU property only if EL3 is allowed. This will 634 * prevent "has_el3" from existing on CPUs which cannot support EL3. 635 */ 636 qdev_property_add_static(DEVICE(obj), &arm_cpu_has_el3_property, 637 &error_abort); 638 639 #ifndef CONFIG_USER_ONLY 640 object_property_add_link(obj, "secure-memory", 641 TYPE_MEMORY_REGION, 642 (Object **)&cpu->secure_memory, 643 qdev_prop_allow_set_link_before_realize, 644 OBJ_PROP_LINK_UNREF_ON_RELEASE, 645 &error_abort); 646 #endif 647 } 648 649 if (arm_feature(&cpu->env, ARM_FEATURE_EL2)) { 650 qdev_property_add_static(DEVICE(obj), &arm_cpu_has_el2_property, 651 &error_abort); 652 } 653 654 if (arm_feature(&cpu->env, ARM_FEATURE_PMU)) { 655 qdev_property_add_static(DEVICE(obj), &arm_cpu_has_pmu_property, 656 &error_abort); 657 } 658 659 if (arm_feature(&cpu->env, ARM_FEATURE_PMSA)) { 660 qdev_property_add_static(DEVICE(obj), &arm_cpu_has_mpu_property, 661 &error_abort); 662 if (arm_feature(&cpu->env, ARM_FEATURE_V7)) { 663 qdev_property_add_static(DEVICE(obj), 664 &arm_cpu_pmsav7_dregion_property, 665 &error_abort); 666 } 667 } 668 669 qdev_property_add_static(DEVICE(obj), &arm_cpu_cfgend_property, 670 &error_abort); 671 } 672 673 static void arm_cpu_finalizefn(Object *obj) 674 { 675 ARMCPU *cpu = ARM_CPU(obj); 676 g_hash_table_destroy(cpu->cp_regs); 677 } 678 679 static void arm_cpu_realizefn(DeviceState *dev, Error **errp) 680 { 681 CPUState *cs = CPU(dev); 682 ARMCPU *cpu = ARM_CPU(dev); 683 ARMCPUClass *acc = ARM_CPU_GET_CLASS(dev); 684 CPUARMState *env = &cpu->env; 685 int pagebits; 686 Error *local_err = NULL; 687 688 cpu_exec_realizefn(cs, &local_err); 689 if (local_err != NULL) { 690 error_propagate(errp, local_err); 691 return; 692 } 693 694 /* Some features automatically imply others: */ 695 if (arm_feature(env, ARM_FEATURE_V8)) { 696 set_feature(env, ARM_FEATURE_V7); 697 set_feature(env, ARM_FEATURE_ARM_DIV); 698 set_feature(env, ARM_FEATURE_LPAE); 699 } 700 if (arm_feature(env, ARM_FEATURE_V7)) { 701 set_feature(env, ARM_FEATURE_VAPA); 702 set_feature(env, ARM_FEATURE_THUMB2); 703 set_feature(env, ARM_FEATURE_MPIDR); 704 if (!arm_feature(env, ARM_FEATURE_M)) { 705 set_feature(env, ARM_FEATURE_V6K); 706 } else { 707 set_feature(env, ARM_FEATURE_V6); 708 } 709 710 /* Always define VBAR for V7 CPUs even if it doesn't exist in 711 * non-EL3 configs. This is needed by some legacy boards. 712 */ 713 set_feature(env, ARM_FEATURE_VBAR); 714 } 715 if (arm_feature(env, ARM_FEATURE_V6K)) { 716 set_feature(env, ARM_FEATURE_V6); 717 set_feature(env, ARM_FEATURE_MVFR); 718 } 719 if (arm_feature(env, ARM_FEATURE_V6)) { 720 set_feature(env, ARM_FEATURE_V5); 721 set_feature(env, ARM_FEATURE_JAZELLE); 722 if (!arm_feature(env, ARM_FEATURE_M)) { 723 set_feature(env, ARM_FEATURE_AUXCR); 724 } 725 } 726 if (arm_feature(env, ARM_FEATURE_V5)) { 727 set_feature(env, ARM_FEATURE_V4T); 728 } 729 if (arm_feature(env, ARM_FEATURE_M)) { 730 set_feature(env, ARM_FEATURE_THUMB_DIV); 731 } 732 if (arm_feature(env, ARM_FEATURE_ARM_DIV)) { 733 set_feature(env, ARM_FEATURE_THUMB_DIV); 734 } 735 if (arm_feature(env, ARM_FEATURE_VFP4)) { 736 set_feature(env, ARM_FEATURE_VFP3); 737 set_feature(env, ARM_FEATURE_VFP_FP16); 738 } 739 if (arm_feature(env, ARM_FEATURE_VFP3)) { 740 set_feature(env, ARM_FEATURE_VFP); 741 } 742 if (arm_feature(env, ARM_FEATURE_LPAE)) { 743 set_feature(env, ARM_FEATURE_V7MP); 744 set_feature(env, ARM_FEATURE_PXN); 745 } 746 if (arm_feature(env, ARM_FEATURE_CBAR_RO)) { 747 set_feature(env, ARM_FEATURE_CBAR); 748 } 749 if (arm_feature(env, ARM_FEATURE_THUMB2) && 750 !arm_feature(env, ARM_FEATURE_M)) { 751 set_feature(env, ARM_FEATURE_THUMB_DSP); 752 } 753 754 if (arm_feature(env, ARM_FEATURE_V7) && 755 !arm_feature(env, ARM_FEATURE_M) && 756 !arm_feature(env, ARM_FEATURE_PMSA)) { 757 /* v7VMSA drops support for the old ARMv5 tiny pages, so we 758 * can use 4K pages. 759 */ 760 pagebits = 12; 761 } else { 762 /* For CPUs which might have tiny 1K pages, or which have an 763 * MPU and might have small region sizes, stick with 1K pages. 764 */ 765 pagebits = 10; 766 } 767 if (!set_preferred_target_page_bits(pagebits)) { 768 /* This can only ever happen for hotplugging a CPU, or if 769 * the board code incorrectly creates a CPU which it has 770 * promised via minimum_page_size that it will not. 771 */ 772 error_setg(errp, "This CPU requires a smaller page size than the " 773 "system is using"); 774 return; 775 } 776 777 /* This cpu-id-to-MPIDR affinity is used only for TCG; KVM will override it. 778 * We don't support setting cluster ID ([16..23]) (known as Aff2 779 * in later ARM ARM versions), or any of the higher affinity level fields, 780 * so these bits always RAZ. 781 */ 782 if (cpu->mp_affinity == ARM64_AFFINITY_INVALID) { 783 cpu->mp_affinity = arm_cpu_mp_affinity(cs->cpu_index, 784 ARM_DEFAULT_CPUS_PER_CLUSTER); 785 } 786 787 if (cpu->reset_hivecs) { 788 cpu->reset_sctlr |= (1 << 13); 789 } 790 791 if (cpu->cfgend) { 792 if (arm_feature(&cpu->env, ARM_FEATURE_V7)) { 793 cpu->reset_sctlr |= SCTLR_EE; 794 } else { 795 cpu->reset_sctlr |= SCTLR_B; 796 } 797 } 798 799 if (!cpu->has_el3) { 800 /* If the has_el3 CPU property is disabled then we need to disable the 801 * feature. 802 */ 803 unset_feature(env, ARM_FEATURE_EL3); 804 805 /* Disable the security extension feature bits in the processor feature 806 * registers as well. These are id_pfr1[7:4] and id_aa64pfr0[15:12]. 807 */ 808 cpu->id_pfr1 &= ~0xf0; 809 cpu->id_aa64pfr0 &= ~0xf000; 810 } 811 812 if (!cpu->has_el2) { 813 unset_feature(env, ARM_FEATURE_EL2); 814 } 815 816 if (!cpu->has_pmu) { 817 unset_feature(env, ARM_FEATURE_PMU); 818 cpu->id_aa64dfr0 &= ~0xf00; 819 } 820 821 if (!arm_feature(env, ARM_FEATURE_EL2)) { 822 /* Disable the hypervisor feature bits in the processor feature 823 * registers if we don't have EL2. These are id_pfr1[15:12] and 824 * id_aa64pfr0_el1[11:8]. 825 */ 826 cpu->id_aa64pfr0 &= ~0xf00; 827 cpu->id_pfr1 &= ~0xf000; 828 } 829 830 /* MPU can be configured out of a PMSA CPU either by setting has-mpu 831 * to false or by setting pmsav7-dregion to 0. 832 */ 833 if (!cpu->has_mpu) { 834 cpu->pmsav7_dregion = 0; 835 } 836 if (cpu->pmsav7_dregion == 0) { 837 cpu->has_mpu = false; 838 } 839 840 if (arm_feature(env, ARM_FEATURE_PMSA) && 841 arm_feature(env, ARM_FEATURE_V7)) { 842 uint32_t nr = cpu->pmsav7_dregion; 843 844 if (nr > 0xff) { 845 error_setg(errp, "PMSAv7 MPU #regions invalid %" PRIu32, nr); 846 return; 847 } 848 849 if (nr) { 850 if (arm_feature(env, ARM_FEATURE_V8)) { 851 /* PMSAv8 */ 852 env->pmsav8.rbar[M_REG_NS] = g_new0(uint32_t, nr); 853 env->pmsav8.rlar[M_REG_NS] = g_new0(uint32_t, nr); 854 if (arm_feature(env, ARM_FEATURE_M_SECURITY)) { 855 env->pmsav8.rbar[M_REG_S] = g_new0(uint32_t, nr); 856 env->pmsav8.rlar[M_REG_S] = g_new0(uint32_t, nr); 857 } 858 } else { 859 env->pmsav7.drbar = g_new0(uint32_t, nr); 860 env->pmsav7.drsr = g_new0(uint32_t, nr); 861 env->pmsav7.dracr = g_new0(uint32_t, nr); 862 } 863 } 864 } 865 866 if (arm_feature(env, ARM_FEATURE_EL3)) { 867 set_feature(env, ARM_FEATURE_VBAR); 868 } 869 870 register_cp_regs_for_features(cpu); 871 arm_cpu_register_gdb_regs_for_features(cpu); 872 873 init_cpreg_list(cpu); 874 875 #ifndef CONFIG_USER_ONLY 876 if (cpu->has_el3 || arm_feature(env, ARM_FEATURE_M_SECURITY)) { 877 AddressSpace *as; 878 879 cs->num_ases = 2; 880 881 if (!cpu->secure_memory) { 882 cpu->secure_memory = cs->memory; 883 } 884 as = address_space_init_shareable(cpu->secure_memory, 885 "cpu-secure-memory"); 886 cpu_address_space_init(cs, as, ARMASIdx_S); 887 } else { 888 cs->num_ases = 1; 889 } 890 891 cpu_address_space_init(cs, 892 address_space_init_shareable(cs->memory, 893 "cpu-memory"), 894 ARMASIdx_NS); 895 #endif 896 897 qemu_init_vcpu(cs); 898 cpu_reset(cs); 899 900 acc->parent_realize(dev, errp); 901 } 902 903 static ObjectClass *arm_cpu_class_by_name(const char *cpu_model) 904 { 905 ObjectClass *oc; 906 char *typename; 907 char **cpuname; 908 909 if (!cpu_model) { 910 return NULL; 911 } 912 913 cpuname = g_strsplit(cpu_model, ",", 1); 914 typename = g_strdup_printf("%s-" TYPE_ARM_CPU, cpuname[0]); 915 oc = object_class_by_name(typename); 916 g_strfreev(cpuname); 917 g_free(typename); 918 if (!oc || !object_class_dynamic_cast(oc, TYPE_ARM_CPU) || 919 object_class_is_abstract(oc)) { 920 return NULL; 921 } 922 return oc; 923 } 924 925 /* CPU models. These are not needed for the AArch64 linux-user build. */ 926 #if !defined(CONFIG_USER_ONLY) || !defined(TARGET_AARCH64) 927 928 static void arm926_initfn(Object *obj) 929 { 930 ARMCPU *cpu = ARM_CPU(obj); 931 932 cpu->dtb_compatible = "arm,arm926"; 933 set_feature(&cpu->env, ARM_FEATURE_V5); 934 set_feature(&cpu->env, ARM_FEATURE_VFP); 935 set_feature(&cpu->env, ARM_FEATURE_DUMMY_C15_REGS); 936 set_feature(&cpu->env, ARM_FEATURE_CACHE_TEST_CLEAN); 937 set_feature(&cpu->env, ARM_FEATURE_JAZELLE); 938 cpu->midr = 0x41069265; 939 cpu->reset_fpsid = 0x41011090; 940 cpu->ctr = 0x1dd20d2; 941 cpu->reset_sctlr = 0x00090078; 942 } 943 944 static void arm946_initfn(Object *obj) 945 { 946 ARMCPU *cpu = ARM_CPU(obj); 947 948 cpu->dtb_compatible = "arm,arm946"; 949 set_feature(&cpu->env, ARM_FEATURE_V5); 950 set_feature(&cpu->env, ARM_FEATURE_PMSA); 951 set_feature(&cpu->env, ARM_FEATURE_DUMMY_C15_REGS); 952 cpu->midr = 0x41059461; 953 cpu->ctr = 0x0f004006; 954 cpu->reset_sctlr = 0x00000078; 955 } 956 957 static void arm1026_initfn(Object *obj) 958 { 959 ARMCPU *cpu = ARM_CPU(obj); 960 961 cpu->dtb_compatible = "arm,arm1026"; 962 set_feature(&cpu->env, ARM_FEATURE_V5); 963 set_feature(&cpu->env, ARM_FEATURE_VFP); 964 set_feature(&cpu->env, ARM_FEATURE_AUXCR); 965 set_feature(&cpu->env, ARM_FEATURE_DUMMY_C15_REGS); 966 set_feature(&cpu->env, ARM_FEATURE_CACHE_TEST_CLEAN); 967 set_feature(&cpu->env, ARM_FEATURE_JAZELLE); 968 cpu->midr = 0x4106a262; 969 cpu->reset_fpsid = 0x410110a0; 970 cpu->ctr = 0x1dd20d2; 971 cpu->reset_sctlr = 0x00090078; 972 cpu->reset_auxcr = 1; 973 { 974 /* The 1026 had an IFAR at c6,c0,0,1 rather than the ARMv6 c6,c0,0,2 */ 975 ARMCPRegInfo ifar = { 976 .name = "IFAR", .cp = 15, .crn = 6, .crm = 0, .opc1 = 0, .opc2 = 1, 977 .access = PL1_RW, 978 .fieldoffset = offsetof(CPUARMState, cp15.ifar_ns), 979 .resetvalue = 0 980 }; 981 define_one_arm_cp_reg(cpu, &ifar); 982 } 983 } 984 985 static void arm1136_r2_initfn(Object *obj) 986 { 987 ARMCPU *cpu = ARM_CPU(obj); 988 /* What qemu calls "arm1136_r2" is actually the 1136 r0p2, ie an 989 * older core than plain "arm1136". In particular this does not 990 * have the v6K features. 991 * These ID register values are correct for 1136 but may be wrong 992 * for 1136_r2 (in particular r0p2 does not actually implement most 993 * of the ID registers). 994 */ 995 996 cpu->dtb_compatible = "arm,arm1136"; 997 set_feature(&cpu->env, ARM_FEATURE_V6); 998 set_feature(&cpu->env, ARM_FEATURE_VFP); 999 set_feature(&cpu->env, ARM_FEATURE_DUMMY_C15_REGS); 1000 set_feature(&cpu->env, ARM_FEATURE_CACHE_DIRTY_REG); 1001 set_feature(&cpu->env, ARM_FEATURE_CACHE_BLOCK_OPS); 1002 cpu->midr = 0x4107b362; 1003 cpu->reset_fpsid = 0x410120b4; 1004 cpu->mvfr0 = 0x11111111; 1005 cpu->mvfr1 = 0x00000000; 1006 cpu->ctr = 0x1dd20d2; 1007 cpu->reset_sctlr = 0x00050078; 1008 cpu->id_pfr0 = 0x111; 1009 cpu->id_pfr1 = 0x1; 1010 cpu->id_dfr0 = 0x2; 1011 cpu->id_afr0 = 0x3; 1012 cpu->id_mmfr0 = 0x01130003; 1013 cpu->id_mmfr1 = 0x10030302; 1014 cpu->id_mmfr2 = 0x01222110; 1015 cpu->id_isar0 = 0x00140011; 1016 cpu->id_isar1 = 0x12002111; 1017 cpu->id_isar2 = 0x11231111; 1018 cpu->id_isar3 = 0x01102131; 1019 cpu->id_isar4 = 0x141; 1020 cpu->reset_auxcr = 7; 1021 } 1022 1023 static void arm1136_initfn(Object *obj) 1024 { 1025 ARMCPU *cpu = ARM_CPU(obj); 1026 1027 cpu->dtb_compatible = "arm,arm1136"; 1028 set_feature(&cpu->env, ARM_FEATURE_V6K); 1029 set_feature(&cpu->env, ARM_FEATURE_V6); 1030 set_feature(&cpu->env, ARM_FEATURE_VFP); 1031 set_feature(&cpu->env, ARM_FEATURE_DUMMY_C15_REGS); 1032 set_feature(&cpu->env, ARM_FEATURE_CACHE_DIRTY_REG); 1033 set_feature(&cpu->env, ARM_FEATURE_CACHE_BLOCK_OPS); 1034 cpu->midr = 0x4117b363; 1035 cpu->reset_fpsid = 0x410120b4; 1036 cpu->mvfr0 = 0x11111111; 1037 cpu->mvfr1 = 0x00000000; 1038 cpu->ctr = 0x1dd20d2; 1039 cpu->reset_sctlr = 0x00050078; 1040 cpu->id_pfr0 = 0x111; 1041 cpu->id_pfr1 = 0x1; 1042 cpu->id_dfr0 = 0x2; 1043 cpu->id_afr0 = 0x3; 1044 cpu->id_mmfr0 = 0x01130003; 1045 cpu->id_mmfr1 = 0x10030302; 1046 cpu->id_mmfr2 = 0x01222110; 1047 cpu->id_isar0 = 0x00140011; 1048 cpu->id_isar1 = 0x12002111; 1049 cpu->id_isar2 = 0x11231111; 1050 cpu->id_isar3 = 0x01102131; 1051 cpu->id_isar4 = 0x141; 1052 cpu->reset_auxcr = 7; 1053 } 1054 1055 static void arm1176_initfn(Object *obj) 1056 { 1057 ARMCPU *cpu = ARM_CPU(obj); 1058 1059 cpu->dtb_compatible = "arm,arm1176"; 1060 set_feature(&cpu->env, ARM_FEATURE_V6K); 1061 set_feature(&cpu->env, ARM_FEATURE_VFP); 1062 set_feature(&cpu->env, ARM_FEATURE_VAPA); 1063 set_feature(&cpu->env, ARM_FEATURE_DUMMY_C15_REGS); 1064 set_feature(&cpu->env, ARM_FEATURE_CACHE_DIRTY_REG); 1065 set_feature(&cpu->env, ARM_FEATURE_CACHE_BLOCK_OPS); 1066 set_feature(&cpu->env, ARM_FEATURE_EL3); 1067 cpu->midr = 0x410fb767; 1068 cpu->reset_fpsid = 0x410120b5; 1069 cpu->mvfr0 = 0x11111111; 1070 cpu->mvfr1 = 0x00000000; 1071 cpu->ctr = 0x1dd20d2; 1072 cpu->reset_sctlr = 0x00050078; 1073 cpu->id_pfr0 = 0x111; 1074 cpu->id_pfr1 = 0x11; 1075 cpu->id_dfr0 = 0x33; 1076 cpu->id_afr0 = 0; 1077 cpu->id_mmfr0 = 0x01130003; 1078 cpu->id_mmfr1 = 0x10030302; 1079 cpu->id_mmfr2 = 0x01222100; 1080 cpu->id_isar0 = 0x0140011; 1081 cpu->id_isar1 = 0x12002111; 1082 cpu->id_isar2 = 0x11231121; 1083 cpu->id_isar3 = 0x01102131; 1084 cpu->id_isar4 = 0x01141; 1085 cpu->reset_auxcr = 7; 1086 } 1087 1088 static void arm11mpcore_initfn(Object *obj) 1089 { 1090 ARMCPU *cpu = ARM_CPU(obj); 1091 1092 cpu->dtb_compatible = "arm,arm11mpcore"; 1093 set_feature(&cpu->env, ARM_FEATURE_V6K); 1094 set_feature(&cpu->env, ARM_FEATURE_VFP); 1095 set_feature(&cpu->env, ARM_FEATURE_VAPA); 1096 set_feature(&cpu->env, ARM_FEATURE_MPIDR); 1097 set_feature(&cpu->env, ARM_FEATURE_DUMMY_C15_REGS); 1098 cpu->midr = 0x410fb022; 1099 cpu->reset_fpsid = 0x410120b4; 1100 cpu->mvfr0 = 0x11111111; 1101 cpu->mvfr1 = 0x00000000; 1102 cpu->ctr = 0x1d192992; /* 32K icache 32K dcache */ 1103 cpu->id_pfr0 = 0x111; 1104 cpu->id_pfr1 = 0x1; 1105 cpu->id_dfr0 = 0; 1106 cpu->id_afr0 = 0x2; 1107 cpu->id_mmfr0 = 0x01100103; 1108 cpu->id_mmfr1 = 0x10020302; 1109 cpu->id_mmfr2 = 0x01222000; 1110 cpu->id_isar0 = 0x00100011; 1111 cpu->id_isar1 = 0x12002111; 1112 cpu->id_isar2 = 0x11221011; 1113 cpu->id_isar3 = 0x01102131; 1114 cpu->id_isar4 = 0x141; 1115 cpu->reset_auxcr = 1; 1116 } 1117 1118 static void cortex_m3_initfn(Object *obj) 1119 { 1120 ARMCPU *cpu = ARM_CPU(obj); 1121 set_feature(&cpu->env, ARM_FEATURE_V7); 1122 set_feature(&cpu->env, ARM_FEATURE_M); 1123 cpu->midr = 0x410fc231; 1124 cpu->pmsav7_dregion = 8; 1125 } 1126 1127 static void cortex_m4_initfn(Object *obj) 1128 { 1129 ARMCPU *cpu = ARM_CPU(obj); 1130 1131 set_feature(&cpu->env, ARM_FEATURE_V7); 1132 set_feature(&cpu->env, ARM_FEATURE_M); 1133 set_feature(&cpu->env, ARM_FEATURE_THUMB_DSP); 1134 cpu->midr = 0x410fc240; /* r0p0 */ 1135 cpu->pmsav7_dregion = 8; 1136 } 1137 static void arm_v7m_class_init(ObjectClass *oc, void *data) 1138 { 1139 CPUClass *cc = CPU_CLASS(oc); 1140 1141 #ifndef CONFIG_USER_ONLY 1142 cc->do_interrupt = arm_v7m_cpu_do_interrupt; 1143 #endif 1144 1145 cc->cpu_exec_interrupt = arm_v7m_cpu_exec_interrupt; 1146 } 1147 1148 static const ARMCPRegInfo cortexr5_cp_reginfo[] = { 1149 /* Dummy the TCM region regs for the moment */ 1150 { .name = "ATCM", .cp = 15, .opc1 = 0, .crn = 9, .crm = 1, .opc2 = 0, 1151 .access = PL1_RW, .type = ARM_CP_CONST }, 1152 { .name = "BTCM", .cp = 15, .opc1 = 0, .crn = 9, .crm = 1, .opc2 = 1, 1153 .access = PL1_RW, .type = ARM_CP_CONST }, 1154 { .name = "DCACHE_INVAL", .cp = 15, .opc1 = 0, .crn = 15, .crm = 5, 1155 .opc2 = 0, .access = PL1_W, .type = ARM_CP_NOP }, 1156 REGINFO_SENTINEL 1157 }; 1158 1159 static void cortex_r5_initfn(Object *obj) 1160 { 1161 ARMCPU *cpu = ARM_CPU(obj); 1162 1163 set_feature(&cpu->env, ARM_FEATURE_V7); 1164 set_feature(&cpu->env, ARM_FEATURE_THUMB_DIV); 1165 set_feature(&cpu->env, ARM_FEATURE_ARM_DIV); 1166 set_feature(&cpu->env, ARM_FEATURE_V7MP); 1167 set_feature(&cpu->env, ARM_FEATURE_PMSA); 1168 cpu->midr = 0x411fc153; /* r1p3 */ 1169 cpu->id_pfr0 = 0x0131; 1170 cpu->id_pfr1 = 0x001; 1171 cpu->id_dfr0 = 0x010400; 1172 cpu->id_afr0 = 0x0; 1173 cpu->id_mmfr0 = 0x0210030; 1174 cpu->id_mmfr1 = 0x00000000; 1175 cpu->id_mmfr2 = 0x01200000; 1176 cpu->id_mmfr3 = 0x0211; 1177 cpu->id_isar0 = 0x2101111; 1178 cpu->id_isar1 = 0x13112111; 1179 cpu->id_isar2 = 0x21232141; 1180 cpu->id_isar3 = 0x01112131; 1181 cpu->id_isar4 = 0x0010142; 1182 cpu->id_isar5 = 0x0; 1183 cpu->mp_is_up = true; 1184 cpu->pmsav7_dregion = 16; 1185 define_arm_cp_regs(cpu, cortexr5_cp_reginfo); 1186 } 1187 1188 static const ARMCPRegInfo cortexa8_cp_reginfo[] = { 1189 { .name = "L2LOCKDOWN", .cp = 15, .crn = 9, .crm = 0, .opc1 = 1, .opc2 = 0, 1190 .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0 }, 1191 { .name = "L2AUXCR", .cp = 15, .crn = 9, .crm = 0, .opc1 = 1, .opc2 = 2, 1192 .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0 }, 1193 REGINFO_SENTINEL 1194 }; 1195 1196 static void cortex_a8_initfn(Object *obj) 1197 { 1198 ARMCPU *cpu = ARM_CPU(obj); 1199 1200 cpu->dtb_compatible = "arm,cortex-a8"; 1201 set_feature(&cpu->env, ARM_FEATURE_V7); 1202 set_feature(&cpu->env, ARM_FEATURE_VFP3); 1203 set_feature(&cpu->env, ARM_FEATURE_NEON); 1204 set_feature(&cpu->env, ARM_FEATURE_THUMB2EE); 1205 set_feature(&cpu->env, ARM_FEATURE_DUMMY_C15_REGS); 1206 set_feature(&cpu->env, ARM_FEATURE_EL3); 1207 cpu->midr = 0x410fc080; 1208 cpu->reset_fpsid = 0x410330c0; 1209 cpu->mvfr0 = 0x11110222; 1210 cpu->mvfr1 = 0x00011111; 1211 cpu->ctr = 0x82048004; 1212 cpu->reset_sctlr = 0x00c50078; 1213 cpu->id_pfr0 = 0x1031; 1214 cpu->id_pfr1 = 0x11; 1215 cpu->id_dfr0 = 0x400; 1216 cpu->id_afr0 = 0; 1217 cpu->id_mmfr0 = 0x31100003; 1218 cpu->id_mmfr1 = 0x20000000; 1219 cpu->id_mmfr2 = 0x01202000; 1220 cpu->id_mmfr3 = 0x11; 1221 cpu->id_isar0 = 0x00101111; 1222 cpu->id_isar1 = 0x12112111; 1223 cpu->id_isar2 = 0x21232031; 1224 cpu->id_isar3 = 0x11112131; 1225 cpu->id_isar4 = 0x00111142; 1226 cpu->dbgdidr = 0x15141000; 1227 cpu->clidr = (1 << 27) | (2 << 24) | 3; 1228 cpu->ccsidr[0] = 0xe007e01a; /* 16k L1 dcache. */ 1229 cpu->ccsidr[1] = 0x2007e01a; /* 16k L1 icache. */ 1230 cpu->ccsidr[2] = 0xf0000000; /* No L2 icache. */ 1231 cpu->reset_auxcr = 2; 1232 define_arm_cp_regs(cpu, cortexa8_cp_reginfo); 1233 } 1234 1235 static const ARMCPRegInfo cortexa9_cp_reginfo[] = { 1236 /* power_control should be set to maximum latency. Again, 1237 * default to 0 and set by private hook 1238 */ 1239 { .name = "A9_PWRCTL", .cp = 15, .crn = 15, .crm = 0, .opc1 = 0, .opc2 = 0, 1240 .access = PL1_RW, .resetvalue = 0, 1241 .fieldoffset = offsetof(CPUARMState, cp15.c15_power_control) }, 1242 { .name = "A9_DIAG", .cp = 15, .crn = 15, .crm = 0, .opc1 = 0, .opc2 = 1, 1243 .access = PL1_RW, .resetvalue = 0, 1244 .fieldoffset = offsetof(CPUARMState, cp15.c15_diagnostic) }, 1245 { .name = "A9_PWRDIAG", .cp = 15, .crn = 15, .crm = 0, .opc1 = 0, .opc2 = 2, 1246 .access = PL1_RW, .resetvalue = 0, 1247 .fieldoffset = offsetof(CPUARMState, cp15.c15_power_diagnostic) }, 1248 { .name = "NEONBUSY", .cp = 15, .crn = 15, .crm = 1, .opc1 = 0, .opc2 = 0, 1249 .access = PL1_RW, .resetvalue = 0, .type = ARM_CP_CONST }, 1250 /* TLB lockdown control */ 1251 { .name = "TLB_LOCKR", .cp = 15, .crn = 15, .crm = 4, .opc1 = 5, .opc2 = 2, 1252 .access = PL1_W, .resetvalue = 0, .type = ARM_CP_NOP }, 1253 { .name = "TLB_LOCKW", .cp = 15, .crn = 15, .crm = 4, .opc1 = 5, .opc2 = 4, 1254 .access = PL1_W, .resetvalue = 0, .type = ARM_CP_NOP }, 1255 { .name = "TLB_VA", .cp = 15, .crn = 15, .crm = 5, .opc1 = 5, .opc2 = 2, 1256 .access = PL1_RW, .resetvalue = 0, .type = ARM_CP_CONST }, 1257 { .name = "TLB_PA", .cp = 15, .crn = 15, .crm = 6, .opc1 = 5, .opc2 = 2, 1258 .access = PL1_RW, .resetvalue = 0, .type = ARM_CP_CONST }, 1259 { .name = "TLB_ATTR", .cp = 15, .crn = 15, .crm = 7, .opc1 = 5, .opc2 = 2, 1260 .access = PL1_RW, .resetvalue = 0, .type = ARM_CP_CONST }, 1261 REGINFO_SENTINEL 1262 }; 1263 1264 static void cortex_a9_initfn(Object *obj) 1265 { 1266 ARMCPU *cpu = ARM_CPU(obj); 1267 1268 cpu->dtb_compatible = "arm,cortex-a9"; 1269 set_feature(&cpu->env, ARM_FEATURE_V7); 1270 set_feature(&cpu->env, ARM_FEATURE_VFP3); 1271 set_feature(&cpu->env, ARM_FEATURE_VFP_FP16); 1272 set_feature(&cpu->env, ARM_FEATURE_NEON); 1273 set_feature(&cpu->env, ARM_FEATURE_THUMB2EE); 1274 set_feature(&cpu->env, ARM_FEATURE_EL3); 1275 /* Note that A9 supports the MP extensions even for 1276 * A9UP and single-core A9MP (which are both different 1277 * and valid configurations; we don't model A9UP). 1278 */ 1279 set_feature(&cpu->env, ARM_FEATURE_V7MP); 1280 set_feature(&cpu->env, ARM_FEATURE_CBAR); 1281 cpu->midr = 0x410fc090; 1282 cpu->reset_fpsid = 0x41033090; 1283 cpu->mvfr0 = 0x11110222; 1284 cpu->mvfr1 = 0x01111111; 1285 cpu->ctr = 0x80038003; 1286 cpu->reset_sctlr = 0x00c50078; 1287 cpu->id_pfr0 = 0x1031; 1288 cpu->id_pfr1 = 0x11; 1289 cpu->id_dfr0 = 0x000; 1290 cpu->id_afr0 = 0; 1291 cpu->id_mmfr0 = 0x00100103; 1292 cpu->id_mmfr1 = 0x20000000; 1293 cpu->id_mmfr2 = 0x01230000; 1294 cpu->id_mmfr3 = 0x00002111; 1295 cpu->id_isar0 = 0x00101111; 1296 cpu->id_isar1 = 0x13112111; 1297 cpu->id_isar2 = 0x21232041; 1298 cpu->id_isar3 = 0x11112131; 1299 cpu->id_isar4 = 0x00111142; 1300 cpu->dbgdidr = 0x35141000; 1301 cpu->clidr = (1 << 27) | (1 << 24) | 3; 1302 cpu->ccsidr[0] = 0xe00fe019; /* 16k L1 dcache. */ 1303 cpu->ccsidr[1] = 0x200fe019; /* 16k L1 icache. */ 1304 define_arm_cp_regs(cpu, cortexa9_cp_reginfo); 1305 } 1306 1307 #ifndef CONFIG_USER_ONLY 1308 static uint64_t a15_l2ctlr_read(CPUARMState *env, const ARMCPRegInfo *ri) 1309 { 1310 /* Linux wants the number of processors from here. 1311 * Might as well set the interrupt-controller bit too. 1312 */ 1313 return ((smp_cpus - 1) << 24) | (1 << 23); 1314 } 1315 #endif 1316 1317 static const ARMCPRegInfo cortexa15_cp_reginfo[] = { 1318 #ifndef CONFIG_USER_ONLY 1319 { .name = "L2CTLR", .cp = 15, .crn = 9, .crm = 0, .opc1 = 1, .opc2 = 2, 1320 .access = PL1_RW, .resetvalue = 0, .readfn = a15_l2ctlr_read, 1321 .writefn = arm_cp_write_ignore, }, 1322 #endif 1323 { .name = "L2ECTLR", .cp = 15, .crn = 9, .crm = 0, .opc1 = 1, .opc2 = 3, 1324 .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0 }, 1325 REGINFO_SENTINEL 1326 }; 1327 1328 static void cortex_a7_initfn(Object *obj) 1329 { 1330 ARMCPU *cpu = ARM_CPU(obj); 1331 1332 cpu->dtb_compatible = "arm,cortex-a7"; 1333 set_feature(&cpu->env, ARM_FEATURE_V7); 1334 set_feature(&cpu->env, ARM_FEATURE_VFP4); 1335 set_feature(&cpu->env, ARM_FEATURE_NEON); 1336 set_feature(&cpu->env, ARM_FEATURE_THUMB2EE); 1337 set_feature(&cpu->env, ARM_FEATURE_ARM_DIV); 1338 set_feature(&cpu->env, ARM_FEATURE_GENERIC_TIMER); 1339 set_feature(&cpu->env, ARM_FEATURE_DUMMY_C15_REGS); 1340 set_feature(&cpu->env, ARM_FEATURE_CBAR_RO); 1341 set_feature(&cpu->env, ARM_FEATURE_LPAE); 1342 set_feature(&cpu->env, ARM_FEATURE_EL3); 1343 cpu->kvm_target = QEMU_KVM_ARM_TARGET_CORTEX_A7; 1344 cpu->midr = 0x410fc075; 1345 cpu->reset_fpsid = 0x41023075; 1346 cpu->mvfr0 = 0x10110222; 1347 cpu->mvfr1 = 0x11111111; 1348 cpu->ctr = 0x84448003; 1349 cpu->reset_sctlr = 0x00c50078; 1350 cpu->id_pfr0 = 0x00001131; 1351 cpu->id_pfr1 = 0x00011011; 1352 cpu->id_dfr0 = 0x02010555; 1353 cpu->pmceid0 = 0x00000000; 1354 cpu->pmceid1 = 0x00000000; 1355 cpu->id_afr0 = 0x00000000; 1356 cpu->id_mmfr0 = 0x10101105; 1357 cpu->id_mmfr1 = 0x40000000; 1358 cpu->id_mmfr2 = 0x01240000; 1359 cpu->id_mmfr3 = 0x02102211; 1360 cpu->id_isar0 = 0x01101110; 1361 cpu->id_isar1 = 0x13112111; 1362 cpu->id_isar2 = 0x21232041; 1363 cpu->id_isar3 = 0x11112131; 1364 cpu->id_isar4 = 0x10011142; 1365 cpu->dbgdidr = 0x3515f005; 1366 cpu->clidr = 0x0a200023; 1367 cpu->ccsidr[0] = 0x701fe00a; /* 32K L1 dcache */ 1368 cpu->ccsidr[1] = 0x201fe00a; /* 32K L1 icache */ 1369 cpu->ccsidr[2] = 0x711fe07a; /* 4096K L2 unified cache */ 1370 define_arm_cp_regs(cpu, cortexa15_cp_reginfo); /* Same as A15 */ 1371 } 1372 1373 static void cortex_a15_initfn(Object *obj) 1374 { 1375 ARMCPU *cpu = ARM_CPU(obj); 1376 1377 cpu->dtb_compatible = "arm,cortex-a15"; 1378 set_feature(&cpu->env, ARM_FEATURE_V7); 1379 set_feature(&cpu->env, ARM_FEATURE_VFP4); 1380 set_feature(&cpu->env, ARM_FEATURE_NEON); 1381 set_feature(&cpu->env, ARM_FEATURE_THUMB2EE); 1382 set_feature(&cpu->env, ARM_FEATURE_ARM_DIV); 1383 set_feature(&cpu->env, ARM_FEATURE_GENERIC_TIMER); 1384 set_feature(&cpu->env, ARM_FEATURE_DUMMY_C15_REGS); 1385 set_feature(&cpu->env, ARM_FEATURE_CBAR_RO); 1386 set_feature(&cpu->env, ARM_FEATURE_LPAE); 1387 set_feature(&cpu->env, ARM_FEATURE_EL3); 1388 cpu->kvm_target = QEMU_KVM_ARM_TARGET_CORTEX_A15; 1389 cpu->midr = 0x412fc0f1; 1390 cpu->reset_fpsid = 0x410430f0; 1391 cpu->mvfr0 = 0x10110222; 1392 cpu->mvfr1 = 0x11111111; 1393 cpu->ctr = 0x8444c004; 1394 cpu->reset_sctlr = 0x00c50078; 1395 cpu->id_pfr0 = 0x00001131; 1396 cpu->id_pfr1 = 0x00011011; 1397 cpu->id_dfr0 = 0x02010555; 1398 cpu->pmceid0 = 0x0000000; 1399 cpu->pmceid1 = 0x00000000; 1400 cpu->id_afr0 = 0x00000000; 1401 cpu->id_mmfr0 = 0x10201105; 1402 cpu->id_mmfr1 = 0x20000000; 1403 cpu->id_mmfr2 = 0x01240000; 1404 cpu->id_mmfr3 = 0x02102211; 1405 cpu->id_isar0 = 0x02101110; 1406 cpu->id_isar1 = 0x13112111; 1407 cpu->id_isar2 = 0x21232041; 1408 cpu->id_isar3 = 0x11112131; 1409 cpu->id_isar4 = 0x10011142; 1410 cpu->dbgdidr = 0x3515f021; 1411 cpu->clidr = 0x0a200023; 1412 cpu->ccsidr[0] = 0x701fe00a; /* 32K L1 dcache */ 1413 cpu->ccsidr[1] = 0x201fe00a; /* 32K L1 icache */ 1414 cpu->ccsidr[2] = 0x711fe07a; /* 4096K L2 unified cache */ 1415 define_arm_cp_regs(cpu, cortexa15_cp_reginfo); 1416 } 1417 1418 static void ti925t_initfn(Object *obj) 1419 { 1420 ARMCPU *cpu = ARM_CPU(obj); 1421 set_feature(&cpu->env, ARM_FEATURE_V4T); 1422 set_feature(&cpu->env, ARM_FEATURE_OMAPCP); 1423 cpu->midr = ARM_CPUID_TI925T; 1424 cpu->ctr = 0x5109149; 1425 cpu->reset_sctlr = 0x00000070; 1426 } 1427 1428 static void sa1100_initfn(Object *obj) 1429 { 1430 ARMCPU *cpu = ARM_CPU(obj); 1431 1432 cpu->dtb_compatible = "intel,sa1100"; 1433 set_feature(&cpu->env, ARM_FEATURE_STRONGARM); 1434 set_feature(&cpu->env, ARM_FEATURE_DUMMY_C15_REGS); 1435 cpu->midr = 0x4401A11B; 1436 cpu->reset_sctlr = 0x00000070; 1437 } 1438 1439 static void sa1110_initfn(Object *obj) 1440 { 1441 ARMCPU *cpu = ARM_CPU(obj); 1442 set_feature(&cpu->env, ARM_FEATURE_STRONGARM); 1443 set_feature(&cpu->env, ARM_FEATURE_DUMMY_C15_REGS); 1444 cpu->midr = 0x6901B119; 1445 cpu->reset_sctlr = 0x00000070; 1446 } 1447 1448 static void pxa250_initfn(Object *obj) 1449 { 1450 ARMCPU *cpu = ARM_CPU(obj); 1451 1452 cpu->dtb_compatible = "marvell,xscale"; 1453 set_feature(&cpu->env, ARM_FEATURE_V5); 1454 set_feature(&cpu->env, ARM_FEATURE_XSCALE); 1455 cpu->midr = 0x69052100; 1456 cpu->ctr = 0xd172172; 1457 cpu->reset_sctlr = 0x00000078; 1458 } 1459 1460 static void pxa255_initfn(Object *obj) 1461 { 1462 ARMCPU *cpu = ARM_CPU(obj); 1463 1464 cpu->dtb_compatible = "marvell,xscale"; 1465 set_feature(&cpu->env, ARM_FEATURE_V5); 1466 set_feature(&cpu->env, ARM_FEATURE_XSCALE); 1467 cpu->midr = 0x69052d00; 1468 cpu->ctr = 0xd172172; 1469 cpu->reset_sctlr = 0x00000078; 1470 } 1471 1472 static void pxa260_initfn(Object *obj) 1473 { 1474 ARMCPU *cpu = ARM_CPU(obj); 1475 1476 cpu->dtb_compatible = "marvell,xscale"; 1477 set_feature(&cpu->env, ARM_FEATURE_V5); 1478 set_feature(&cpu->env, ARM_FEATURE_XSCALE); 1479 cpu->midr = 0x69052903; 1480 cpu->ctr = 0xd172172; 1481 cpu->reset_sctlr = 0x00000078; 1482 } 1483 1484 static void pxa261_initfn(Object *obj) 1485 { 1486 ARMCPU *cpu = ARM_CPU(obj); 1487 1488 cpu->dtb_compatible = "marvell,xscale"; 1489 set_feature(&cpu->env, ARM_FEATURE_V5); 1490 set_feature(&cpu->env, ARM_FEATURE_XSCALE); 1491 cpu->midr = 0x69052d05; 1492 cpu->ctr = 0xd172172; 1493 cpu->reset_sctlr = 0x00000078; 1494 } 1495 1496 static void pxa262_initfn(Object *obj) 1497 { 1498 ARMCPU *cpu = ARM_CPU(obj); 1499 1500 cpu->dtb_compatible = "marvell,xscale"; 1501 set_feature(&cpu->env, ARM_FEATURE_V5); 1502 set_feature(&cpu->env, ARM_FEATURE_XSCALE); 1503 cpu->midr = 0x69052d06; 1504 cpu->ctr = 0xd172172; 1505 cpu->reset_sctlr = 0x00000078; 1506 } 1507 1508 static void pxa270a0_initfn(Object *obj) 1509 { 1510 ARMCPU *cpu = ARM_CPU(obj); 1511 1512 cpu->dtb_compatible = "marvell,xscale"; 1513 set_feature(&cpu->env, ARM_FEATURE_V5); 1514 set_feature(&cpu->env, ARM_FEATURE_XSCALE); 1515 set_feature(&cpu->env, ARM_FEATURE_IWMMXT); 1516 cpu->midr = 0x69054110; 1517 cpu->ctr = 0xd172172; 1518 cpu->reset_sctlr = 0x00000078; 1519 } 1520 1521 static void pxa270a1_initfn(Object *obj) 1522 { 1523 ARMCPU *cpu = ARM_CPU(obj); 1524 1525 cpu->dtb_compatible = "marvell,xscale"; 1526 set_feature(&cpu->env, ARM_FEATURE_V5); 1527 set_feature(&cpu->env, ARM_FEATURE_XSCALE); 1528 set_feature(&cpu->env, ARM_FEATURE_IWMMXT); 1529 cpu->midr = 0x69054111; 1530 cpu->ctr = 0xd172172; 1531 cpu->reset_sctlr = 0x00000078; 1532 } 1533 1534 static void pxa270b0_initfn(Object *obj) 1535 { 1536 ARMCPU *cpu = ARM_CPU(obj); 1537 1538 cpu->dtb_compatible = "marvell,xscale"; 1539 set_feature(&cpu->env, ARM_FEATURE_V5); 1540 set_feature(&cpu->env, ARM_FEATURE_XSCALE); 1541 set_feature(&cpu->env, ARM_FEATURE_IWMMXT); 1542 cpu->midr = 0x69054112; 1543 cpu->ctr = 0xd172172; 1544 cpu->reset_sctlr = 0x00000078; 1545 } 1546 1547 static void pxa270b1_initfn(Object *obj) 1548 { 1549 ARMCPU *cpu = ARM_CPU(obj); 1550 1551 cpu->dtb_compatible = "marvell,xscale"; 1552 set_feature(&cpu->env, ARM_FEATURE_V5); 1553 set_feature(&cpu->env, ARM_FEATURE_XSCALE); 1554 set_feature(&cpu->env, ARM_FEATURE_IWMMXT); 1555 cpu->midr = 0x69054113; 1556 cpu->ctr = 0xd172172; 1557 cpu->reset_sctlr = 0x00000078; 1558 } 1559 1560 static void pxa270c0_initfn(Object *obj) 1561 { 1562 ARMCPU *cpu = ARM_CPU(obj); 1563 1564 cpu->dtb_compatible = "marvell,xscale"; 1565 set_feature(&cpu->env, ARM_FEATURE_V5); 1566 set_feature(&cpu->env, ARM_FEATURE_XSCALE); 1567 set_feature(&cpu->env, ARM_FEATURE_IWMMXT); 1568 cpu->midr = 0x69054114; 1569 cpu->ctr = 0xd172172; 1570 cpu->reset_sctlr = 0x00000078; 1571 } 1572 1573 static void pxa270c5_initfn(Object *obj) 1574 { 1575 ARMCPU *cpu = ARM_CPU(obj); 1576 1577 cpu->dtb_compatible = "marvell,xscale"; 1578 set_feature(&cpu->env, ARM_FEATURE_V5); 1579 set_feature(&cpu->env, ARM_FEATURE_XSCALE); 1580 set_feature(&cpu->env, ARM_FEATURE_IWMMXT); 1581 cpu->midr = 0x69054117; 1582 cpu->ctr = 0xd172172; 1583 cpu->reset_sctlr = 0x00000078; 1584 } 1585 1586 #ifdef CONFIG_USER_ONLY 1587 static void arm_any_initfn(Object *obj) 1588 { 1589 ARMCPU *cpu = ARM_CPU(obj); 1590 set_feature(&cpu->env, ARM_FEATURE_V8); 1591 set_feature(&cpu->env, ARM_FEATURE_VFP4); 1592 set_feature(&cpu->env, ARM_FEATURE_NEON); 1593 set_feature(&cpu->env, ARM_FEATURE_THUMB2EE); 1594 set_feature(&cpu->env, ARM_FEATURE_V8_AES); 1595 set_feature(&cpu->env, ARM_FEATURE_V8_SHA1); 1596 set_feature(&cpu->env, ARM_FEATURE_V8_SHA256); 1597 set_feature(&cpu->env, ARM_FEATURE_V8_PMULL); 1598 set_feature(&cpu->env, ARM_FEATURE_CRC); 1599 cpu->midr = 0xffffffff; 1600 } 1601 #endif 1602 1603 #endif /* !defined(CONFIG_USER_ONLY) || !defined(TARGET_AARCH64) */ 1604 1605 typedef struct ARMCPUInfo { 1606 const char *name; 1607 void (*initfn)(Object *obj); 1608 void (*class_init)(ObjectClass *oc, void *data); 1609 } ARMCPUInfo; 1610 1611 static const ARMCPUInfo arm_cpus[] = { 1612 #if !defined(CONFIG_USER_ONLY) || !defined(TARGET_AARCH64) 1613 { .name = "arm926", .initfn = arm926_initfn }, 1614 { .name = "arm946", .initfn = arm946_initfn }, 1615 { .name = "arm1026", .initfn = arm1026_initfn }, 1616 /* What QEMU calls "arm1136-r2" is actually the 1136 r0p2, i.e. an 1617 * older core than plain "arm1136". In particular this does not 1618 * have the v6K features. 1619 */ 1620 { .name = "arm1136-r2", .initfn = arm1136_r2_initfn }, 1621 { .name = "arm1136", .initfn = arm1136_initfn }, 1622 { .name = "arm1176", .initfn = arm1176_initfn }, 1623 { .name = "arm11mpcore", .initfn = arm11mpcore_initfn }, 1624 { .name = "cortex-m3", .initfn = cortex_m3_initfn, 1625 .class_init = arm_v7m_class_init }, 1626 { .name = "cortex-m4", .initfn = cortex_m4_initfn, 1627 .class_init = arm_v7m_class_init }, 1628 { .name = "cortex-r5", .initfn = cortex_r5_initfn }, 1629 { .name = "cortex-a7", .initfn = cortex_a7_initfn }, 1630 { .name = "cortex-a8", .initfn = cortex_a8_initfn }, 1631 { .name = "cortex-a9", .initfn = cortex_a9_initfn }, 1632 { .name = "cortex-a15", .initfn = cortex_a15_initfn }, 1633 { .name = "ti925t", .initfn = ti925t_initfn }, 1634 { .name = "sa1100", .initfn = sa1100_initfn }, 1635 { .name = "sa1110", .initfn = sa1110_initfn }, 1636 { .name = "pxa250", .initfn = pxa250_initfn }, 1637 { .name = "pxa255", .initfn = pxa255_initfn }, 1638 { .name = "pxa260", .initfn = pxa260_initfn }, 1639 { .name = "pxa261", .initfn = pxa261_initfn }, 1640 { .name = "pxa262", .initfn = pxa262_initfn }, 1641 /* "pxa270" is an alias for "pxa270-a0" */ 1642 { .name = "pxa270", .initfn = pxa270a0_initfn }, 1643 { .name = "pxa270-a0", .initfn = pxa270a0_initfn }, 1644 { .name = "pxa270-a1", .initfn = pxa270a1_initfn }, 1645 { .name = "pxa270-b0", .initfn = pxa270b0_initfn }, 1646 { .name = "pxa270-b1", .initfn = pxa270b1_initfn }, 1647 { .name = "pxa270-c0", .initfn = pxa270c0_initfn }, 1648 { .name = "pxa270-c5", .initfn = pxa270c5_initfn }, 1649 #ifdef CONFIG_USER_ONLY 1650 { .name = "any", .initfn = arm_any_initfn }, 1651 #endif 1652 #endif 1653 { .name = NULL } 1654 }; 1655 1656 static Property arm_cpu_properties[] = { 1657 DEFINE_PROP_BOOL("start-powered-off", ARMCPU, start_powered_off, false), 1658 DEFINE_PROP_UINT32("psci-conduit", ARMCPU, psci_conduit, 0), 1659 DEFINE_PROP_UINT32("midr", ARMCPU, midr, 0), 1660 DEFINE_PROP_UINT64("mp-affinity", ARMCPU, 1661 mp_affinity, ARM64_AFFINITY_INVALID), 1662 DEFINE_PROP_INT32("node-id", ARMCPU, node_id, CPU_UNSET_NUMA_NODE_ID), 1663 DEFINE_PROP_END_OF_LIST() 1664 }; 1665 1666 #ifdef CONFIG_USER_ONLY 1667 static int arm_cpu_handle_mmu_fault(CPUState *cs, vaddr address, int rw, 1668 int mmu_idx) 1669 { 1670 ARMCPU *cpu = ARM_CPU(cs); 1671 CPUARMState *env = &cpu->env; 1672 1673 env->exception.vaddress = address; 1674 if (rw == 2) { 1675 cs->exception_index = EXCP_PREFETCH_ABORT; 1676 } else { 1677 cs->exception_index = EXCP_DATA_ABORT; 1678 } 1679 return 1; 1680 } 1681 #endif 1682 1683 static gchar *arm_gdb_arch_name(CPUState *cs) 1684 { 1685 ARMCPU *cpu = ARM_CPU(cs); 1686 CPUARMState *env = &cpu->env; 1687 1688 if (arm_feature(env, ARM_FEATURE_IWMMXT)) { 1689 return g_strdup("iwmmxt"); 1690 } 1691 return g_strdup("arm"); 1692 } 1693 1694 static void arm_cpu_class_init(ObjectClass *oc, void *data) 1695 { 1696 ARMCPUClass *acc = ARM_CPU_CLASS(oc); 1697 CPUClass *cc = CPU_CLASS(acc); 1698 DeviceClass *dc = DEVICE_CLASS(oc); 1699 1700 acc->parent_realize = dc->realize; 1701 dc->realize = arm_cpu_realizefn; 1702 dc->props = arm_cpu_properties; 1703 1704 acc->parent_reset = cc->reset; 1705 cc->reset = arm_cpu_reset; 1706 1707 cc->class_by_name = arm_cpu_class_by_name; 1708 cc->has_work = arm_cpu_has_work; 1709 cc->cpu_exec_interrupt = arm_cpu_exec_interrupt; 1710 cc->dump_state = arm_cpu_dump_state; 1711 cc->set_pc = arm_cpu_set_pc; 1712 cc->gdb_read_register = arm_cpu_gdb_read_register; 1713 cc->gdb_write_register = arm_cpu_gdb_write_register; 1714 #ifdef CONFIG_USER_ONLY 1715 cc->handle_mmu_fault = arm_cpu_handle_mmu_fault; 1716 #else 1717 cc->do_interrupt = arm_cpu_do_interrupt; 1718 cc->do_unaligned_access = arm_cpu_do_unaligned_access; 1719 cc->do_transaction_failed = arm_cpu_do_transaction_failed; 1720 cc->get_phys_page_attrs_debug = arm_cpu_get_phys_page_attrs_debug; 1721 cc->asidx_from_attrs = arm_asidx_from_attrs; 1722 cc->vmsd = &vmstate_arm_cpu; 1723 cc->virtio_is_big_endian = arm_cpu_virtio_is_big_endian; 1724 cc->write_elf64_note = arm_cpu_write_elf64_note; 1725 cc->write_elf32_note = arm_cpu_write_elf32_note; 1726 #endif 1727 cc->gdb_num_core_regs = 26; 1728 cc->gdb_core_xml_file = "arm-core.xml"; 1729 cc->gdb_arch_name = arm_gdb_arch_name; 1730 cc->gdb_stop_before_watchpoint = true; 1731 cc->debug_excp_handler = arm_debug_excp_handler; 1732 cc->debug_check_watchpoint = arm_debug_check_watchpoint; 1733 #if !defined(CONFIG_USER_ONLY) 1734 cc->adjust_watchpoint_address = arm_adjust_watchpoint_address; 1735 #endif 1736 1737 cc->disas_set_info = arm_disas_set_info; 1738 } 1739 1740 static void cpu_register(const ARMCPUInfo *info) 1741 { 1742 TypeInfo type_info = { 1743 .parent = TYPE_ARM_CPU, 1744 .instance_size = sizeof(ARMCPU), 1745 .instance_init = info->initfn, 1746 .class_size = sizeof(ARMCPUClass), 1747 .class_init = info->class_init, 1748 }; 1749 1750 type_info.name = g_strdup_printf("%s-" TYPE_ARM_CPU, info->name); 1751 type_register(&type_info); 1752 g_free((void *)type_info.name); 1753 } 1754 1755 static const TypeInfo arm_cpu_type_info = { 1756 .name = TYPE_ARM_CPU, 1757 .parent = TYPE_CPU, 1758 .instance_size = sizeof(ARMCPU), 1759 .instance_init = arm_cpu_initfn, 1760 .instance_post_init = arm_cpu_post_init, 1761 .instance_finalize = arm_cpu_finalizefn, 1762 .abstract = true, 1763 .class_size = sizeof(ARMCPUClass), 1764 .class_init = arm_cpu_class_init, 1765 }; 1766 1767 static void arm_cpu_register_types(void) 1768 { 1769 const ARMCPUInfo *info = arm_cpus; 1770 1771 type_register_static(&arm_cpu_type_info); 1772 1773 while (info->name) { 1774 cpu_register(info); 1775 info++; 1776 } 1777 } 1778 1779 type_init(arm_cpu_register_types) 1780