1 /* 2 * QEMU ARM CPU 3 * 4 * Copyright (c) 2012 SUSE LINUX Products GmbH 5 * 6 * This program is free software; you can redistribute it and/or 7 * modify it under the terms of the GNU General Public License 8 * as published by the Free Software Foundation; either version 2 9 * of the License, or (at your option) any later version. 10 * 11 * This program is distributed in the hope that it will be useful, 12 * but WITHOUT ANY WARRANTY; without even the implied warranty of 13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 14 * GNU General Public License for more details. 15 * 16 * You should have received a copy of the GNU General Public License 17 * along with this program; if not, see 18 * <http://www.gnu.org/licenses/gpl-2.0.html> 19 */ 20 21 #include "qemu/osdep.h" 22 #include "qemu/qemu-print.h" 23 #include "qemu-common.h" 24 #include "target/arm/idau.h" 25 #include "qemu/module.h" 26 #include "qapi/error.h" 27 #include "qapi/visitor.h" 28 #include "cpu.h" 29 #ifdef CONFIG_TCG 30 #include "hw/core/tcg-cpu-ops.h" 31 #endif /* CONFIG_TCG */ 32 #include "internals.h" 33 #include "exec/exec-all.h" 34 #include "hw/qdev-properties.h" 35 #if !defined(CONFIG_USER_ONLY) 36 #include "hw/loader.h" 37 #include "hw/boards.h" 38 #endif 39 #include "sysemu/tcg.h" 40 #include "sysemu/hw_accel.h" 41 #include "kvm_arm.h" 42 #include "disas/capstone.h" 43 #include "fpu/softfloat.h" 44 45 static void arm_cpu_set_pc(CPUState *cs, vaddr value) 46 { 47 ARMCPU *cpu = ARM_CPU(cs); 48 CPUARMState *env = &cpu->env; 49 50 if (is_a64(env)) { 51 env->pc = value; 52 env->thumb = 0; 53 } else { 54 env->regs[15] = value & ~1; 55 env->thumb = value & 1; 56 } 57 } 58 59 #ifdef CONFIG_TCG 60 void arm_cpu_synchronize_from_tb(CPUState *cs, 61 const TranslationBlock *tb) 62 { 63 ARMCPU *cpu = ARM_CPU(cs); 64 CPUARMState *env = &cpu->env; 65 66 /* 67 * It's OK to look at env for the current mode here, because it's 68 * never possible for an AArch64 TB to chain to an AArch32 TB. 69 */ 70 if (is_a64(env)) { 71 env->pc = tb->pc; 72 } else { 73 env->regs[15] = tb->pc; 74 } 75 } 76 #endif /* CONFIG_TCG */ 77 78 static bool arm_cpu_has_work(CPUState *cs) 79 { 80 ARMCPU *cpu = ARM_CPU(cs); 81 82 return (cpu->power_state != PSCI_OFF) 83 && cs->interrupt_request & 84 (CPU_INTERRUPT_FIQ | CPU_INTERRUPT_HARD 85 | CPU_INTERRUPT_VFIQ | CPU_INTERRUPT_VIRQ 86 | CPU_INTERRUPT_EXITTB); 87 } 88 89 void arm_register_pre_el_change_hook(ARMCPU *cpu, ARMELChangeHookFn *hook, 90 void *opaque) 91 { 92 ARMELChangeHook *entry = g_new0(ARMELChangeHook, 1); 93 94 entry->hook = hook; 95 entry->opaque = opaque; 96 97 QLIST_INSERT_HEAD(&cpu->pre_el_change_hooks, entry, node); 98 } 99 100 void arm_register_el_change_hook(ARMCPU *cpu, ARMELChangeHookFn *hook, 101 void *opaque) 102 { 103 ARMELChangeHook *entry = g_new0(ARMELChangeHook, 1); 104 105 entry->hook = hook; 106 entry->opaque = opaque; 107 108 QLIST_INSERT_HEAD(&cpu->el_change_hooks, entry, node); 109 } 110 111 static void cp_reg_reset(gpointer key, gpointer value, gpointer opaque) 112 { 113 /* Reset a single ARMCPRegInfo register */ 114 ARMCPRegInfo *ri = value; 115 ARMCPU *cpu = opaque; 116 117 if (ri->type & (ARM_CP_SPECIAL | ARM_CP_ALIAS)) { 118 return; 119 } 120 121 if (ri->resetfn) { 122 ri->resetfn(&cpu->env, ri); 123 return; 124 } 125 126 /* A zero offset is never possible as it would be regs[0] 127 * so we use it to indicate that reset is being handled elsewhere. 128 * This is basically only used for fields in non-core coprocessors 129 * (like the pxa2xx ones). 130 */ 131 if (!ri->fieldoffset) { 132 return; 133 } 134 135 if (cpreg_field_is_64bit(ri)) { 136 CPREG_FIELD64(&cpu->env, ri) = ri->resetvalue; 137 } else { 138 CPREG_FIELD32(&cpu->env, ri) = ri->resetvalue; 139 } 140 } 141 142 static void cp_reg_check_reset(gpointer key, gpointer value, gpointer opaque) 143 { 144 /* Purely an assertion check: we've already done reset once, 145 * so now check that running the reset for the cpreg doesn't 146 * change its value. This traps bugs where two different cpregs 147 * both try to reset the same state field but to different values. 148 */ 149 ARMCPRegInfo *ri = value; 150 ARMCPU *cpu = opaque; 151 uint64_t oldvalue, newvalue; 152 153 if (ri->type & (ARM_CP_SPECIAL | ARM_CP_ALIAS | ARM_CP_NO_RAW)) { 154 return; 155 } 156 157 oldvalue = read_raw_cp_reg(&cpu->env, ri); 158 cp_reg_reset(key, value, opaque); 159 newvalue = read_raw_cp_reg(&cpu->env, ri); 160 assert(oldvalue == newvalue); 161 } 162 163 static void arm_cpu_reset(DeviceState *dev) 164 { 165 CPUState *s = CPU(dev); 166 ARMCPU *cpu = ARM_CPU(s); 167 ARMCPUClass *acc = ARM_CPU_GET_CLASS(cpu); 168 CPUARMState *env = &cpu->env; 169 170 acc->parent_reset(dev); 171 172 memset(env, 0, offsetof(CPUARMState, end_reset_fields)); 173 174 g_hash_table_foreach(cpu->cp_regs, cp_reg_reset, cpu); 175 g_hash_table_foreach(cpu->cp_regs, cp_reg_check_reset, cpu); 176 177 env->vfp.xregs[ARM_VFP_FPSID] = cpu->reset_fpsid; 178 env->vfp.xregs[ARM_VFP_MVFR0] = cpu->isar.mvfr0; 179 env->vfp.xregs[ARM_VFP_MVFR1] = cpu->isar.mvfr1; 180 env->vfp.xregs[ARM_VFP_MVFR2] = cpu->isar.mvfr2; 181 182 cpu->power_state = s->start_powered_off ? PSCI_OFF : PSCI_ON; 183 184 if (arm_feature(env, ARM_FEATURE_IWMMXT)) { 185 env->iwmmxt.cregs[ARM_IWMMXT_wCID] = 0x69051000 | 'Q'; 186 } 187 188 if (arm_feature(env, ARM_FEATURE_AARCH64)) { 189 /* 64 bit CPUs always start in 64 bit mode */ 190 env->aarch64 = 1; 191 #if defined(CONFIG_USER_ONLY) 192 env->pstate = PSTATE_MODE_EL0t; 193 /* Userspace expects access to DC ZVA, CTL_EL0 and the cache ops */ 194 env->cp15.sctlr_el[1] |= SCTLR_UCT | SCTLR_UCI | SCTLR_DZE; 195 /* Enable all PAC keys. */ 196 env->cp15.sctlr_el[1] |= (SCTLR_EnIA | SCTLR_EnIB | 197 SCTLR_EnDA | SCTLR_EnDB); 198 /* and to the FP/Neon instructions */ 199 env->cp15.cpacr_el1 = deposit64(env->cp15.cpacr_el1, 20, 2, 3); 200 /* and to the SVE instructions */ 201 env->cp15.cpacr_el1 = deposit64(env->cp15.cpacr_el1, 16, 2, 3); 202 /* with reasonable vector length */ 203 if (cpu_isar_feature(aa64_sve, cpu)) { 204 env->vfp.zcr_el[1] = 205 aarch64_sve_zcr_get_valid_len(cpu, cpu->sve_default_vq - 1); 206 } 207 /* 208 * Enable TBI0 but not TBI1. 209 * Note that this must match useronly_clean_ptr. 210 */ 211 env->cp15.tcr_el[1].raw_tcr = (1ULL << 37); 212 213 /* Enable MTE */ 214 if (cpu_isar_feature(aa64_mte, cpu)) { 215 /* Enable tag access, but leave TCF0 as No Effect (0). */ 216 env->cp15.sctlr_el[1] |= SCTLR_ATA0; 217 /* 218 * Exclude all tags, so that tag 0 is always used. 219 * This corresponds to Linux current->thread.gcr_incl = 0. 220 * 221 * Set RRND, so that helper_irg() will generate a seed later. 222 * Here in cpu_reset(), the crypto subsystem has not yet been 223 * initialized. 224 */ 225 env->cp15.gcr_el1 = 0x1ffff; 226 } 227 #else 228 /* Reset into the highest available EL */ 229 if (arm_feature(env, ARM_FEATURE_EL3)) { 230 env->pstate = PSTATE_MODE_EL3h; 231 } else if (arm_feature(env, ARM_FEATURE_EL2)) { 232 env->pstate = PSTATE_MODE_EL2h; 233 } else { 234 env->pstate = PSTATE_MODE_EL1h; 235 } 236 env->pc = cpu->rvbar; 237 #endif 238 } else { 239 #if defined(CONFIG_USER_ONLY) 240 /* Userspace expects access to cp10 and cp11 for FP/Neon */ 241 env->cp15.cpacr_el1 = deposit64(env->cp15.cpacr_el1, 20, 4, 0xf); 242 #endif 243 } 244 245 #if defined(CONFIG_USER_ONLY) 246 env->uncached_cpsr = ARM_CPU_MODE_USR; 247 /* For user mode we must enable access to coprocessors */ 248 env->vfp.xregs[ARM_VFP_FPEXC] = 1 << 30; 249 if (arm_feature(env, ARM_FEATURE_IWMMXT)) { 250 env->cp15.c15_cpar = 3; 251 } else if (arm_feature(env, ARM_FEATURE_XSCALE)) { 252 env->cp15.c15_cpar = 1; 253 } 254 #else 255 256 /* 257 * If the highest available EL is EL2, AArch32 will start in Hyp 258 * mode; otherwise it starts in SVC. Note that if we start in 259 * AArch64 then these values in the uncached_cpsr will be ignored. 260 */ 261 if (arm_feature(env, ARM_FEATURE_EL2) && 262 !arm_feature(env, ARM_FEATURE_EL3)) { 263 env->uncached_cpsr = ARM_CPU_MODE_HYP; 264 } else { 265 env->uncached_cpsr = ARM_CPU_MODE_SVC; 266 } 267 env->daif = PSTATE_D | PSTATE_A | PSTATE_I | PSTATE_F; 268 269 /* AArch32 has a hard highvec setting of 0xFFFF0000. If we are currently 270 * executing as AArch32 then check if highvecs are enabled and 271 * adjust the PC accordingly. 272 */ 273 if (A32_BANKED_CURRENT_REG_GET(env, sctlr) & SCTLR_V) { 274 env->regs[15] = 0xFFFF0000; 275 } 276 277 env->vfp.xregs[ARM_VFP_FPEXC] = 0; 278 #endif 279 280 if (arm_feature(env, ARM_FEATURE_M)) { 281 #ifndef CONFIG_USER_ONLY 282 uint32_t initial_msp; /* Loaded from 0x0 */ 283 uint32_t initial_pc; /* Loaded from 0x4 */ 284 uint8_t *rom; 285 uint32_t vecbase; 286 #endif 287 288 if (cpu_isar_feature(aa32_lob, cpu)) { 289 /* 290 * LTPSIZE is constant 4 if MVE not implemented, and resets 291 * to an UNKNOWN value if MVE is implemented. We choose to 292 * always reset to 4. 293 */ 294 env->v7m.ltpsize = 4; 295 /* The LTPSIZE field in FPDSCR is constant and reads as 4. */ 296 env->v7m.fpdscr[M_REG_NS] = 4 << FPCR_LTPSIZE_SHIFT; 297 env->v7m.fpdscr[M_REG_S] = 4 << FPCR_LTPSIZE_SHIFT; 298 } 299 300 if (arm_feature(env, ARM_FEATURE_M_SECURITY)) { 301 env->v7m.secure = true; 302 } else { 303 /* This bit resets to 0 if security is supported, but 1 if 304 * it is not. The bit is not present in v7M, but we set it 305 * here so we can avoid having to make checks on it conditional 306 * on ARM_FEATURE_V8 (we don't let the guest see the bit). 307 */ 308 env->v7m.aircr = R_V7M_AIRCR_BFHFNMINS_MASK; 309 /* 310 * Set NSACR to indicate "NS access permitted to everything"; 311 * this avoids having to have all the tests of it being 312 * conditional on ARM_FEATURE_M_SECURITY. Note also that from 313 * v8.1M the guest-visible value of NSACR in a CPU without the 314 * Security Extension is 0xcff. 315 */ 316 env->v7m.nsacr = 0xcff; 317 } 318 319 /* In v7M the reset value of this bit is IMPDEF, but ARM recommends 320 * that it resets to 1, so QEMU always does that rather than making 321 * it dependent on CPU model. In v8M it is RES1. 322 */ 323 env->v7m.ccr[M_REG_NS] = R_V7M_CCR_STKALIGN_MASK; 324 env->v7m.ccr[M_REG_S] = R_V7M_CCR_STKALIGN_MASK; 325 if (arm_feature(env, ARM_FEATURE_V8)) { 326 /* in v8M the NONBASETHRDENA bit [0] is RES1 */ 327 env->v7m.ccr[M_REG_NS] |= R_V7M_CCR_NONBASETHRDENA_MASK; 328 env->v7m.ccr[M_REG_S] |= R_V7M_CCR_NONBASETHRDENA_MASK; 329 } 330 if (!arm_feature(env, ARM_FEATURE_M_MAIN)) { 331 env->v7m.ccr[M_REG_NS] |= R_V7M_CCR_UNALIGN_TRP_MASK; 332 env->v7m.ccr[M_REG_S] |= R_V7M_CCR_UNALIGN_TRP_MASK; 333 } 334 335 if (cpu_isar_feature(aa32_vfp_simd, cpu)) { 336 env->v7m.fpccr[M_REG_NS] = R_V7M_FPCCR_ASPEN_MASK; 337 env->v7m.fpccr[M_REG_S] = R_V7M_FPCCR_ASPEN_MASK | 338 R_V7M_FPCCR_LSPEN_MASK | R_V7M_FPCCR_S_MASK; 339 } 340 341 #ifndef CONFIG_USER_ONLY 342 /* Unlike A/R profile, M profile defines the reset LR value */ 343 env->regs[14] = 0xffffffff; 344 345 env->v7m.vecbase[M_REG_S] = cpu->init_svtor & 0xffffff80; 346 env->v7m.vecbase[M_REG_NS] = cpu->init_nsvtor & 0xffffff80; 347 348 /* Load the initial SP and PC from offset 0 and 4 in the vector table */ 349 vecbase = env->v7m.vecbase[env->v7m.secure]; 350 rom = rom_ptr_for_as(s->as, vecbase, 8); 351 if (rom) { 352 /* Address zero is covered by ROM which hasn't yet been 353 * copied into physical memory. 354 */ 355 initial_msp = ldl_p(rom); 356 initial_pc = ldl_p(rom + 4); 357 } else { 358 /* Address zero not covered by a ROM blob, or the ROM blob 359 * is in non-modifiable memory and this is a second reset after 360 * it got copied into memory. In the latter case, rom_ptr 361 * will return a NULL pointer and we should use ldl_phys instead. 362 */ 363 initial_msp = ldl_phys(s->as, vecbase); 364 initial_pc = ldl_phys(s->as, vecbase + 4); 365 } 366 367 env->regs[13] = initial_msp & 0xFFFFFFFC; 368 env->regs[15] = initial_pc & ~1; 369 env->thumb = initial_pc & 1; 370 #else 371 /* 372 * For user mode we run non-secure and with access to the FPU. 373 * The FPU context is active (ie does not need further setup) 374 * and is owned by non-secure. 375 */ 376 env->v7m.secure = false; 377 env->v7m.nsacr = 0xcff; 378 env->v7m.cpacr[M_REG_NS] = 0xf0ffff; 379 env->v7m.fpccr[M_REG_S] &= 380 ~(R_V7M_FPCCR_LSPEN_MASK | R_V7M_FPCCR_S_MASK); 381 env->v7m.control[M_REG_S] |= R_V7M_CONTROL_FPCA_MASK; 382 #endif 383 } 384 385 /* M profile requires that reset clears the exclusive monitor; 386 * A profile does not, but clearing it makes more sense than having it 387 * set with an exclusive access on address zero. 388 */ 389 arm_clear_exclusive(env); 390 391 if (arm_feature(env, ARM_FEATURE_PMSA)) { 392 if (cpu->pmsav7_dregion > 0) { 393 if (arm_feature(env, ARM_FEATURE_V8)) { 394 memset(env->pmsav8.rbar[M_REG_NS], 0, 395 sizeof(*env->pmsav8.rbar[M_REG_NS]) 396 * cpu->pmsav7_dregion); 397 memset(env->pmsav8.rlar[M_REG_NS], 0, 398 sizeof(*env->pmsav8.rlar[M_REG_NS]) 399 * cpu->pmsav7_dregion); 400 if (arm_feature(env, ARM_FEATURE_M_SECURITY)) { 401 memset(env->pmsav8.rbar[M_REG_S], 0, 402 sizeof(*env->pmsav8.rbar[M_REG_S]) 403 * cpu->pmsav7_dregion); 404 memset(env->pmsav8.rlar[M_REG_S], 0, 405 sizeof(*env->pmsav8.rlar[M_REG_S]) 406 * cpu->pmsav7_dregion); 407 } 408 } else if (arm_feature(env, ARM_FEATURE_V7)) { 409 memset(env->pmsav7.drbar, 0, 410 sizeof(*env->pmsav7.drbar) * cpu->pmsav7_dregion); 411 memset(env->pmsav7.drsr, 0, 412 sizeof(*env->pmsav7.drsr) * cpu->pmsav7_dregion); 413 memset(env->pmsav7.dracr, 0, 414 sizeof(*env->pmsav7.dracr) * cpu->pmsav7_dregion); 415 } 416 } 417 env->pmsav7.rnr[M_REG_NS] = 0; 418 env->pmsav7.rnr[M_REG_S] = 0; 419 env->pmsav8.mair0[M_REG_NS] = 0; 420 env->pmsav8.mair0[M_REG_S] = 0; 421 env->pmsav8.mair1[M_REG_NS] = 0; 422 env->pmsav8.mair1[M_REG_S] = 0; 423 } 424 425 if (arm_feature(env, ARM_FEATURE_M_SECURITY)) { 426 if (cpu->sau_sregion > 0) { 427 memset(env->sau.rbar, 0, sizeof(*env->sau.rbar) * cpu->sau_sregion); 428 memset(env->sau.rlar, 0, sizeof(*env->sau.rlar) * cpu->sau_sregion); 429 } 430 env->sau.rnr = 0; 431 /* SAU_CTRL reset value is IMPDEF; we choose 0, which is what 432 * the Cortex-M33 does. 433 */ 434 env->sau.ctrl = 0; 435 } 436 437 set_flush_to_zero(1, &env->vfp.standard_fp_status); 438 set_flush_inputs_to_zero(1, &env->vfp.standard_fp_status); 439 set_default_nan_mode(1, &env->vfp.standard_fp_status); 440 set_default_nan_mode(1, &env->vfp.standard_fp_status_f16); 441 set_float_detect_tininess(float_tininess_before_rounding, 442 &env->vfp.fp_status); 443 set_float_detect_tininess(float_tininess_before_rounding, 444 &env->vfp.standard_fp_status); 445 set_float_detect_tininess(float_tininess_before_rounding, 446 &env->vfp.fp_status_f16); 447 set_float_detect_tininess(float_tininess_before_rounding, 448 &env->vfp.standard_fp_status_f16); 449 #ifndef CONFIG_USER_ONLY 450 if (kvm_enabled()) { 451 kvm_arm_reset_vcpu(cpu); 452 } 453 #endif 454 455 hw_breakpoint_update_all(cpu); 456 hw_watchpoint_update_all(cpu); 457 arm_rebuild_hflags(env); 458 } 459 460 #ifndef CONFIG_USER_ONLY 461 462 static inline bool arm_excp_unmasked(CPUState *cs, unsigned int excp_idx, 463 unsigned int target_el, 464 unsigned int cur_el, bool secure, 465 uint64_t hcr_el2) 466 { 467 CPUARMState *env = cs->env_ptr; 468 bool pstate_unmasked; 469 bool unmasked = false; 470 471 /* 472 * Don't take exceptions if they target a lower EL. 473 * This check should catch any exceptions that would not be taken 474 * but left pending. 475 */ 476 if (cur_el > target_el) { 477 return false; 478 } 479 480 switch (excp_idx) { 481 case EXCP_FIQ: 482 pstate_unmasked = !(env->daif & PSTATE_F); 483 break; 484 485 case EXCP_IRQ: 486 pstate_unmasked = !(env->daif & PSTATE_I); 487 break; 488 489 case EXCP_VFIQ: 490 if (!(hcr_el2 & HCR_FMO) || (hcr_el2 & HCR_TGE)) { 491 /* VFIQs are only taken when hypervized. */ 492 return false; 493 } 494 return !(env->daif & PSTATE_F); 495 case EXCP_VIRQ: 496 if (!(hcr_el2 & HCR_IMO) || (hcr_el2 & HCR_TGE)) { 497 /* VIRQs are only taken when hypervized. */ 498 return false; 499 } 500 return !(env->daif & PSTATE_I); 501 default: 502 g_assert_not_reached(); 503 } 504 505 /* 506 * Use the target EL, current execution state and SCR/HCR settings to 507 * determine whether the corresponding CPSR bit is used to mask the 508 * interrupt. 509 */ 510 if ((target_el > cur_el) && (target_el != 1)) { 511 /* Exceptions targeting a higher EL may not be maskable */ 512 if (arm_feature(env, ARM_FEATURE_AARCH64)) { 513 /* 514 * 64-bit masking rules are simple: exceptions to EL3 515 * can't be masked, and exceptions to EL2 can only be 516 * masked from Secure state. The HCR and SCR settings 517 * don't affect the masking logic, only the interrupt routing. 518 */ 519 if (target_el == 3 || !secure || (env->cp15.scr_el3 & SCR_EEL2)) { 520 unmasked = true; 521 } 522 } else { 523 /* 524 * The old 32-bit-only environment has a more complicated 525 * masking setup. HCR and SCR bits not only affect interrupt 526 * routing but also change the behaviour of masking. 527 */ 528 bool hcr, scr; 529 530 switch (excp_idx) { 531 case EXCP_FIQ: 532 /* 533 * If FIQs are routed to EL3 or EL2 then there are cases where 534 * we override the CPSR.F in determining if the exception is 535 * masked or not. If neither of these are set then we fall back 536 * to the CPSR.F setting otherwise we further assess the state 537 * below. 538 */ 539 hcr = hcr_el2 & HCR_FMO; 540 scr = (env->cp15.scr_el3 & SCR_FIQ); 541 542 /* 543 * When EL3 is 32-bit, the SCR.FW bit controls whether the 544 * CPSR.F bit masks FIQ interrupts when taken in non-secure 545 * state. If SCR.FW is set then FIQs can be masked by CPSR.F 546 * when non-secure but only when FIQs are only routed to EL3. 547 */ 548 scr = scr && !((env->cp15.scr_el3 & SCR_FW) && !hcr); 549 break; 550 case EXCP_IRQ: 551 /* 552 * When EL3 execution state is 32-bit, if HCR.IMO is set then 553 * we may override the CPSR.I masking when in non-secure state. 554 * The SCR.IRQ setting has already been taken into consideration 555 * when setting the target EL, so it does not have a further 556 * affect here. 557 */ 558 hcr = hcr_el2 & HCR_IMO; 559 scr = false; 560 break; 561 default: 562 g_assert_not_reached(); 563 } 564 565 if ((scr || hcr) && !secure) { 566 unmasked = true; 567 } 568 } 569 } 570 571 /* 572 * The PSTATE bits only mask the interrupt if we have not overriden the 573 * ability above. 574 */ 575 return unmasked || pstate_unmasked; 576 } 577 578 static bool arm_cpu_exec_interrupt(CPUState *cs, int interrupt_request) 579 { 580 CPUClass *cc = CPU_GET_CLASS(cs); 581 CPUARMState *env = cs->env_ptr; 582 uint32_t cur_el = arm_current_el(env); 583 bool secure = arm_is_secure(env); 584 uint64_t hcr_el2 = arm_hcr_el2_eff(env); 585 uint32_t target_el; 586 uint32_t excp_idx; 587 588 /* The prioritization of interrupts is IMPLEMENTATION DEFINED. */ 589 590 if (interrupt_request & CPU_INTERRUPT_FIQ) { 591 excp_idx = EXCP_FIQ; 592 target_el = arm_phys_excp_target_el(cs, excp_idx, cur_el, secure); 593 if (arm_excp_unmasked(cs, excp_idx, target_el, 594 cur_el, secure, hcr_el2)) { 595 goto found; 596 } 597 } 598 if (interrupt_request & CPU_INTERRUPT_HARD) { 599 excp_idx = EXCP_IRQ; 600 target_el = arm_phys_excp_target_el(cs, excp_idx, cur_el, secure); 601 if (arm_excp_unmasked(cs, excp_idx, target_el, 602 cur_el, secure, hcr_el2)) { 603 goto found; 604 } 605 } 606 if (interrupt_request & CPU_INTERRUPT_VIRQ) { 607 excp_idx = EXCP_VIRQ; 608 target_el = 1; 609 if (arm_excp_unmasked(cs, excp_idx, target_el, 610 cur_el, secure, hcr_el2)) { 611 goto found; 612 } 613 } 614 if (interrupt_request & CPU_INTERRUPT_VFIQ) { 615 excp_idx = EXCP_VFIQ; 616 target_el = 1; 617 if (arm_excp_unmasked(cs, excp_idx, target_el, 618 cur_el, secure, hcr_el2)) { 619 goto found; 620 } 621 } 622 return false; 623 624 found: 625 cs->exception_index = excp_idx; 626 env->exception.target_el = target_el; 627 cc->tcg_ops->do_interrupt(cs); 628 return true; 629 } 630 #endif /* !CONFIG_USER_ONLY */ 631 632 void arm_cpu_update_virq(ARMCPU *cpu) 633 { 634 /* 635 * Update the interrupt level for VIRQ, which is the logical OR of 636 * the HCR_EL2.VI bit and the input line level from the GIC. 637 */ 638 CPUARMState *env = &cpu->env; 639 CPUState *cs = CPU(cpu); 640 641 bool new_state = (env->cp15.hcr_el2 & HCR_VI) || 642 (env->irq_line_state & CPU_INTERRUPT_VIRQ); 643 644 if (new_state != ((cs->interrupt_request & CPU_INTERRUPT_VIRQ) != 0)) { 645 if (new_state) { 646 cpu_interrupt(cs, CPU_INTERRUPT_VIRQ); 647 } else { 648 cpu_reset_interrupt(cs, CPU_INTERRUPT_VIRQ); 649 } 650 } 651 } 652 653 void arm_cpu_update_vfiq(ARMCPU *cpu) 654 { 655 /* 656 * Update the interrupt level for VFIQ, which is the logical OR of 657 * the HCR_EL2.VF bit and the input line level from the GIC. 658 */ 659 CPUARMState *env = &cpu->env; 660 CPUState *cs = CPU(cpu); 661 662 bool new_state = (env->cp15.hcr_el2 & HCR_VF) || 663 (env->irq_line_state & CPU_INTERRUPT_VFIQ); 664 665 if (new_state != ((cs->interrupt_request & CPU_INTERRUPT_VFIQ) != 0)) { 666 if (new_state) { 667 cpu_interrupt(cs, CPU_INTERRUPT_VFIQ); 668 } else { 669 cpu_reset_interrupt(cs, CPU_INTERRUPT_VFIQ); 670 } 671 } 672 } 673 674 #ifndef CONFIG_USER_ONLY 675 static void arm_cpu_set_irq(void *opaque, int irq, int level) 676 { 677 ARMCPU *cpu = opaque; 678 CPUARMState *env = &cpu->env; 679 CPUState *cs = CPU(cpu); 680 static const int mask[] = { 681 [ARM_CPU_IRQ] = CPU_INTERRUPT_HARD, 682 [ARM_CPU_FIQ] = CPU_INTERRUPT_FIQ, 683 [ARM_CPU_VIRQ] = CPU_INTERRUPT_VIRQ, 684 [ARM_CPU_VFIQ] = CPU_INTERRUPT_VFIQ 685 }; 686 687 if (level) { 688 env->irq_line_state |= mask[irq]; 689 } else { 690 env->irq_line_state &= ~mask[irq]; 691 } 692 693 switch (irq) { 694 case ARM_CPU_VIRQ: 695 assert(arm_feature(env, ARM_FEATURE_EL2)); 696 arm_cpu_update_virq(cpu); 697 break; 698 case ARM_CPU_VFIQ: 699 assert(arm_feature(env, ARM_FEATURE_EL2)); 700 arm_cpu_update_vfiq(cpu); 701 break; 702 case ARM_CPU_IRQ: 703 case ARM_CPU_FIQ: 704 if (level) { 705 cpu_interrupt(cs, mask[irq]); 706 } else { 707 cpu_reset_interrupt(cs, mask[irq]); 708 } 709 break; 710 default: 711 g_assert_not_reached(); 712 } 713 } 714 715 static void arm_cpu_kvm_set_irq(void *opaque, int irq, int level) 716 { 717 #ifdef CONFIG_KVM 718 ARMCPU *cpu = opaque; 719 CPUARMState *env = &cpu->env; 720 CPUState *cs = CPU(cpu); 721 uint32_t linestate_bit; 722 int irq_id; 723 724 switch (irq) { 725 case ARM_CPU_IRQ: 726 irq_id = KVM_ARM_IRQ_CPU_IRQ; 727 linestate_bit = CPU_INTERRUPT_HARD; 728 break; 729 case ARM_CPU_FIQ: 730 irq_id = KVM_ARM_IRQ_CPU_FIQ; 731 linestate_bit = CPU_INTERRUPT_FIQ; 732 break; 733 default: 734 g_assert_not_reached(); 735 } 736 737 if (level) { 738 env->irq_line_state |= linestate_bit; 739 } else { 740 env->irq_line_state &= ~linestate_bit; 741 } 742 kvm_arm_set_irq(cs->cpu_index, KVM_ARM_IRQ_TYPE_CPU, irq_id, !!level); 743 #endif 744 } 745 746 static bool arm_cpu_virtio_is_big_endian(CPUState *cs) 747 { 748 ARMCPU *cpu = ARM_CPU(cs); 749 CPUARMState *env = &cpu->env; 750 751 cpu_synchronize_state(cs); 752 return arm_cpu_data_is_big_endian(env); 753 } 754 755 #endif 756 757 static int 758 print_insn_thumb1(bfd_vma pc, disassemble_info *info) 759 { 760 return print_insn_arm(pc | 1, info); 761 } 762 763 static void arm_disas_set_info(CPUState *cpu, disassemble_info *info) 764 { 765 ARMCPU *ac = ARM_CPU(cpu); 766 CPUARMState *env = &ac->env; 767 bool sctlr_b; 768 769 if (is_a64(env)) { 770 /* We might not be compiled with the A64 disassembler 771 * because it needs a C++ compiler. Leave print_insn 772 * unset in this case to use the caller default behaviour. 773 */ 774 #if defined(CONFIG_ARM_A64_DIS) 775 info->print_insn = print_insn_arm_a64; 776 #endif 777 info->cap_arch = CS_ARCH_ARM64; 778 info->cap_insn_unit = 4; 779 info->cap_insn_split = 4; 780 } else { 781 int cap_mode; 782 if (env->thumb) { 783 info->print_insn = print_insn_thumb1; 784 info->cap_insn_unit = 2; 785 info->cap_insn_split = 4; 786 cap_mode = CS_MODE_THUMB; 787 } else { 788 info->print_insn = print_insn_arm; 789 info->cap_insn_unit = 4; 790 info->cap_insn_split = 4; 791 cap_mode = CS_MODE_ARM; 792 } 793 if (arm_feature(env, ARM_FEATURE_V8)) { 794 cap_mode |= CS_MODE_V8; 795 } 796 if (arm_feature(env, ARM_FEATURE_M)) { 797 cap_mode |= CS_MODE_MCLASS; 798 } 799 info->cap_arch = CS_ARCH_ARM; 800 info->cap_mode = cap_mode; 801 } 802 803 sctlr_b = arm_sctlr_b(env); 804 if (bswap_code(sctlr_b)) { 805 #ifdef TARGET_WORDS_BIGENDIAN 806 info->endian = BFD_ENDIAN_LITTLE; 807 #else 808 info->endian = BFD_ENDIAN_BIG; 809 #endif 810 } 811 info->flags &= ~INSN_ARM_BE32; 812 #ifndef CONFIG_USER_ONLY 813 if (sctlr_b) { 814 info->flags |= INSN_ARM_BE32; 815 } 816 #endif 817 } 818 819 #ifdef TARGET_AARCH64 820 821 static void aarch64_cpu_dump_state(CPUState *cs, FILE *f, int flags) 822 { 823 ARMCPU *cpu = ARM_CPU(cs); 824 CPUARMState *env = &cpu->env; 825 uint32_t psr = pstate_read(env); 826 int i; 827 int el = arm_current_el(env); 828 const char *ns_status; 829 830 qemu_fprintf(f, " PC=%016" PRIx64 " ", env->pc); 831 for (i = 0; i < 32; i++) { 832 if (i == 31) { 833 qemu_fprintf(f, " SP=%016" PRIx64 "\n", env->xregs[i]); 834 } else { 835 qemu_fprintf(f, "X%02d=%016" PRIx64 "%s", i, env->xregs[i], 836 (i + 2) % 3 ? " " : "\n"); 837 } 838 } 839 840 if (arm_feature(env, ARM_FEATURE_EL3) && el != 3) { 841 ns_status = env->cp15.scr_el3 & SCR_NS ? "NS " : "S "; 842 } else { 843 ns_status = ""; 844 } 845 qemu_fprintf(f, "PSTATE=%08x %c%c%c%c %sEL%d%c", 846 psr, 847 psr & PSTATE_N ? 'N' : '-', 848 psr & PSTATE_Z ? 'Z' : '-', 849 psr & PSTATE_C ? 'C' : '-', 850 psr & PSTATE_V ? 'V' : '-', 851 ns_status, 852 el, 853 psr & PSTATE_SP ? 'h' : 't'); 854 855 if (cpu_isar_feature(aa64_bti, cpu)) { 856 qemu_fprintf(f, " BTYPE=%d", (psr & PSTATE_BTYPE) >> 10); 857 } 858 if (!(flags & CPU_DUMP_FPU)) { 859 qemu_fprintf(f, "\n"); 860 return; 861 } 862 if (fp_exception_el(env, el) != 0) { 863 qemu_fprintf(f, " FPU disabled\n"); 864 return; 865 } 866 qemu_fprintf(f, " FPCR=%08x FPSR=%08x\n", 867 vfp_get_fpcr(env), vfp_get_fpsr(env)); 868 869 if (cpu_isar_feature(aa64_sve, cpu) && sve_exception_el(env, el) == 0) { 870 int j, zcr_len = sve_zcr_len_for_el(env, el); 871 872 for (i = 0; i <= FFR_PRED_NUM; i++) { 873 bool eol; 874 if (i == FFR_PRED_NUM) { 875 qemu_fprintf(f, "FFR="); 876 /* It's last, so end the line. */ 877 eol = true; 878 } else { 879 qemu_fprintf(f, "P%02d=", i); 880 switch (zcr_len) { 881 case 0: 882 eol = i % 8 == 7; 883 break; 884 case 1: 885 eol = i % 6 == 5; 886 break; 887 case 2: 888 case 3: 889 eol = i % 3 == 2; 890 break; 891 default: 892 /* More than one quadword per predicate. */ 893 eol = true; 894 break; 895 } 896 } 897 for (j = zcr_len / 4; j >= 0; j--) { 898 int digits; 899 if (j * 4 + 4 <= zcr_len + 1) { 900 digits = 16; 901 } else { 902 digits = (zcr_len % 4 + 1) * 4; 903 } 904 qemu_fprintf(f, "%0*" PRIx64 "%s", digits, 905 env->vfp.pregs[i].p[j], 906 j ? ":" : eol ? "\n" : " "); 907 } 908 } 909 910 for (i = 0; i < 32; i++) { 911 if (zcr_len == 0) { 912 qemu_fprintf(f, "Z%02d=%016" PRIx64 ":%016" PRIx64 "%s", 913 i, env->vfp.zregs[i].d[1], 914 env->vfp.zregs[i].d[0], i & 1 ? "\n" : " "); 915 } else if (zcr_len == 1) { 916 qemu_fprintf(f, "Z%02d=%016" PRIx64 ":%016" PRIx64 917 ":%016" PRIx64 ":%016" PRIx64 "\n", 918 i, env->vfp.zregs[i].d[3], env->vfp.zregs[i].d[2], 919 env->vfp.zregs[i].d[1], env->vfp.zregs[i].d[0]); 920 } else { 921 for (j = zcr_len; j >= 0; j--) { 922 bool odd = (zcr_len - j) % 2 != 0; 923 if (j == zcr_len) { 924 qemu_fprintf(f, "Z%02d[%x-%x]=", i, j, j - 1); 925 } else if (!odd) { 926 if (j > 0) { 927 qemu_fprintf(f, " [%x-%x]=", j, j - 1); 928 } else { 929 qemu_fprintf(f, " [%x]=", j); 930 } 931 } 932 qemu_fprintf(f, "%016" PRIx64 ":%016" PRIx64 "%s", 933 env->vfp.zregs[i].d[j * 2 + 1], 934 env->vfp.zregs[i].d[j * 2], 935 odd || j == 0 ? "\n" : ":"); 936 } 937 } 938 } 939 } else { 940 for (i = 0; i < 32; i++) { 941 uint64_t *q = aa64_vfp_qreg(env, i); 942 qemu_fprintf(f, "Q%02d=%016" PRIx64 ":%016" PRIx64 "%s", 943 i, q[1], q[0], (i & 1 ? "\n" : " ")); 944 } 945 } 946 } 947 948 #else 949 950 static inline void aarch64_cpu_dump_state(CPUState *cs, FILE *f, int flags) 951 { 952 g_assert_not_reached(); 953 } 954 955 #endif 956 957 static void arm_cpu_dump_state(CPUState *cs, FILE *f, int flags) 958 { 959 ARMCPU *cpu = ARM_CPU(cs); 960 CPUARMState *env = &cpu->env; 961 int i; 962 963 if (is_a64(env)) { 964 aarch64_cpu_dump_state(cs, f, flags); 965 return; 966 } 967 968 for (i = 0; i < 16; i++) { 969 qemu_fprintf(f, "R%02d=%08x", i, env->regs[i]); 970 if ((i % 4) == 3) { 971 qemu_fprintf(f, "\n"); 972 } else { 973 qemu_fprintf(f, " "); 974 } 975 } 976 977 if (arm_feature(env, ARM_FEATURE_M)) { 978 uint32_t xpsr = xpsr_read(env); 979 const char *mode; 980 const char *ns_status = ""; 981 982 if (arm_feature(env, ARM_FEATURE_M_SECURITY)) { 983 ns_status = env->v7m.secure ? "S " : "NS "; 984 } 985 986 if (xpsr & XPSR_EXCP) { 987 mode = "handler"; 988 } else { 989 if (env->v7m.control[env->v7m.secure] & R_V7M_CONTROL_NPRIV_MASK) { 990 mode = "unpriv-thread"; 991 } else { 992 mode = "priv-thread"; 993 } 994 } 995 996 qemu_fprintf(f, "XPSR=%08x %c%c%c%c %c %s%s\n", 997 xpsr, 998 xpsr & XPSR_N ? 'N' : '-', 999 xpsr & XPSR_Z ? 'Z' : '-', 1000 xpsr & XPSR_C ? 'C' : '-', 1001 xpsr & XPSR_V ? 'V' : '-', 1002 xpsr & XPSR_T ? 'T' : 'A', 1003 ns_status, 1004 mode); 1005 } else { 1006 uint32_t psr = cpsr_read(env); 1007 const char *ns_status = ""; 1008 1009 if (arm_feature(env, ARM_FEATURE_EL3) && 1010 (psr & CPSR_M) != ARM_CPU_MODE_MON) { 1011 ns_status = env->cp15.scr_el3 & SCR_NS ? "NS " : "S "; 1012 } 1013 1014 qemu_fprintf(f, "PSR=%08x %c%c%c%c %c %s%s%d\n", 1015 psr, 1016 psr & CPSR_N ? 'N' : '-', 1017 psr & CPSR_Z ? 'Z' : '-', 1018 psr & CPSR_C ? 'C' : '-', 1019 psr & CPSR_V ? 'V' : '-', 1020 psr & CPSR_T ? 'T' : 'A', 1021 ns_status, 1022 aarch32_mode_name(psr), (psr & 0x10) ? 32 : 26); 1023 } 1024 1025 if (flags & CPU_DUMP_FPU) { 1026 int numvfpregs = 0; 1027 if (cpu_isar_feature(aa32_simd_r32, cpu)) { 1028 numvfpregs = 32; 1029 } else if (cpu_isar_feature(aa32_vfp_simd, cpu)) { 1030 numvfpregs = 16; 1031 } 1032 for (i = 0; i < numvfpregs; i++) { 1033 uint64_t v = *aa32_vfp_dreg(env, i); 1034 qemu_fprintf(f, "s%02d=%08x s%02d=%08x d%02d=%016" PRIx64 "\n", 1035 i * 2, (uint32_t)v, 1036 i * 2 + 1, (uint32_t)(v >> 32), 1037 i, v); 1038 } 1039 qemu_fprintf(f, "FPSCR: %08x\n", vfp_get_fpscr(env)); 1040 if (cpu_isar_feature(aa32_mve, cpu)) { 1041 qemu_fprintf(f, "VPR: %08x\n", env->v7m.vpr); 1042 } 1043 } 1044 } 1045 1046 uint64_t arm_cpu_mp_affinity(int idx, uint8_t clustersz) 1047 { 1048 uint32_t Aff1 = idx / clustersz; 1049 uint32_t Aff0 = idx % clustersz; 1050 return (Aff1 << ARM_AFF1_SHIFT) | Aff0; 1051 } 1052 1053 static void cpreg_hashtable_data_destroy(gpointer data) 1054 { 1055 /* 1056 * Destroy function for cpu->cp_regs hashtable data entries. 1057 * We must free the name string because it was g_strdup()ed in 1058 * add_cpreg_to_hashtable(). It's OK to cast away the 'const' 1059 * from r->name because we know we definitely allocated it. 1060 */ 1061 ARMCPRegInfo *r = data; 1062 1063 g_free((void *)r->name); 1064 g_free(r); 1065 } 1066 1067 static void arm_cpu_initfn(Object *obj) 1068 { 1069 ARMCPU *cpu = ARM_CPU(obj); 1070 1071 cpu_set_cpustate_pointers(cpu); 1072 cpu->cp_regs = g_hash_table_new_full(g_int_hash, g_int_equal, 1073 g_free, cpreg_hashtable_data_destroy); 1074 1075 QLIST_INIT(&cpu->pre_el_change_hooks); 1076 QLIST_INIT(&cpu->el_change_hooks); 1077 1078 #ifdef CONFIG_USER_ONLY 1079 # ifdef TARGET_AARCH64 1080 /* 1081 * The linux kernel defaults to 512-bit vectors, when sve is supported. 1082 * See documentation for /proc/sys/abi/sve_default_vector_length, and 1083 * our corresponding sve-default-vector-length cpu property. 1084 */ 1085 cpu->sve_default_vq = 4; 1086 # endif 1087 #else 1088 /* Our inbound IRQ and FIQ lines */ 1089 if (kvm_enabled()) { 1090 /* VIRQ and VFIQ are unused with KVM but we add them to maintain 1091 * the same interface as non-KVM CPUs. 1092 */ 1093 qdev_init_gpio_in(DEVICE(cpu), arm_cpu_kvm_set_irq, 4); 1094 } else { 1095 qdev_init_gpio_in(DEVICE(cpu), arm_cpu_set_irq, 4); 1096 } 1097 1098 qdev_init_gpio_out(DEVICE(cpu), cpu->gt_timer_outputs, 1099 ARRAY_SIZE(cpu->gt_timer_outputs)); 1100 1101 qdev_init_gpio_out_named(DEVICE(cpu), &cpu->gicv3_maintenance_interrupt, 1102 "gicv3-maintenance-interrupt", 1); 1103 qdev_init_gpio_out_named(DEVICE(cpu), &cpu->pmu_interrupt, 1104 "pmu-interrupt", 1); 1105 #endif 1106 1107 /* DTB consumers generally don't in fact care what the 'compatible' 1108 * string is, so always provide some string and trust that a hypothetical 1109 * picky DTB consumer will also provide a helpful error message. 1110 */ 1111 cpu->dtb_compatible = "qemu,unknown"; 1112 cpu->psci_version = 1; /* By default assume PSCI v0.1 */ 1113 cpu->kvm_target = QEMU_KVM_ARM_TARGET_NONE; 1114 1115 if (tcg_enabled() || hvf_enabled()) { 1116 cpu->psci_version = 2; /* TCG and HVF implement PSCI 0.2 */ 1117 } 1118 } 1119 1120 static Property arm_cpu_gt_cntfrq_property = 1121 DEFINE_PROP_UINT64("cntfrq", ARMCPU, gt_cntfrq_hz, 1122 NANOSECONDS_PER_SECOND / GTIMER_SCALE); 1123 1124 static Property arm_cpu_reset_cbar_property = 1125 DEFINE_PROP_UINT64("reset-cbar", ARMCPU, reset_cbar, 0); 1126 1127 static Property arm_cpu_reset_hivecs_property = 1128 DEFINE_PROP_BOOL("reset-hivecs", ARMCPU, reset_hivecs, false); 1129 1130 static Property arm_cpu_rvbar_property = 1131 DEFINE_PROP_UINT64("rvbar", ARMCPU, rvbar, 0); 1132 1133 #ifndef CONFIG_USER_ONLY 1134 static Property arm_cpu_has_el2_property = 1135 DEFINE_PROP_BOOL("has_el2", ARMCPU, has_el2, true); 1136 1137 static Property arm_cpu_has_el3_property = 1138 DEFINE_PROP_BOOL("has_el3", ARMCPU, has_el3, true); 1139 #endif 1140 1141 static Property arm_cpu_cfgend_property = 1142 DEFINE_PROP_BOOL("cfgend", ARMCPU, cfgend, false); 1143 1144 static Property arm_cpu_has_vfp_property = 1145 DEFINE_PROP_BOOL("vfp", ARMCPU, has_vfp, true); 1146 1147 static Property arm_cpu_has_neon_property = 1148 DEFINE_PROP_BOOL("neon", ARMCPU, has_neon, true); 1149 1150 static Property arm_cpu_has_dsp_property = 1151 DEFINE_PROP_BOOL("dsp", ARMCPU, has_dsp, true); 1152 1153 static Property arm_cpu_has_mpu_property = 1154 DEFINE_PROP_BOOL("has-mpu", ARMCPU, has_mpu, true); 1155 1156 /* This is like DEFINE_PROP_UINT32 but it doesn't set the default value, 1157 * because the CPU initfn will have already set cpu->pmsav7_dregion to 1158 * the right value for that particular CPU type, and we don't want 1159 * to override that with an incorrect constant value. 1160 */ 1161 static Property arm_cpu_pmsav7_dregion_property = 1162 DEFINE_PROP_UNSIGNED_NODEFAULT("pmsav7-dregion", ARMCPU, 1163 pmsav7_dregion, 1164 qdev_prop_uint32, uint32_t); 1165 1166 static bool arm_get_pmu(Object *obj, Error **errp) 1167 { 1168 ARMCPU *cpu = ARM_CPU(obj); 1169 1170 return cpu->has_pmu; 1171 } 1172 1173 static void arm_set_pmu(Object *obj, bool value, Error **errp) 1174 { 1175 ARMCPU *cpu = ARM_CPU(obj); 1176 1177 if (value) { 1178 if (kvm_enabled() && !kvm_arm_pmu_supported()) { 1179 error_setg(errp, "'pmu' feature not supported by KVM on this host"); 1180 return; 1181 } 1182 set_feature(&cpu->env, ARM_FEATURE_PMU); 1183 } else { 1184 unset_feature(&cpu->env, ARM_FEATURE_PMU); 1185 } 1186 cpu->has_pmu = value; 1187 } 1188 1189 unsigned int gt_cntfrq_period_ns(ARMCPU *cpu) 1190 { 1191 /* 1192 * The exact approach to calculating guest ticks is: 1193 * 1194 * muldiv64(qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL), cpu->gt_cntfrq_hz, 1195 * NANOSECONDS_PER_SECOND); 1196 * 1197 * We don't do that. Rather we intentionally use integer division 1198 * truncation below and in the caller for the conversion of host monotonic 1199 * time to guest ticks to provide the exact inverse for the semantics of 1200 * the QEMUTimer scale factor. QEMUTimer's scale facter is an integer, so 1201 * it loses precision when representing frequencies where 1202 * `(NANOSECONDS_PER_SECOND % cpu->gt_cntfrq) > 0` holds. Failing to 1203 * provide an exact inverse leads to scheduling timers with negative 1204 * periods, which in turn leads to sticky behaviour in the guest. 1205 * 1206 * Finally, CNTFRQ is effectively capped at 1GHz to ensure our scale factor 1207 * cannot become zero. 1208 */ 1209 return NANOSECONDS_PER_SECOND > cpu->gt_cntfrq_hz ? 1210 NANOSECONDS_PER_SECOND / cpu->gt_cntfrq_hz : 1; 1211 } 1212 1213 void arm_cpu_post_init(Object *obj) 1214 { 1215 ARMCPU *cpu = ARM_CPU(obj); 1216 1217 /* M profile implies PMSA. We have to do this here rather than 1218 * in realize with the other feature-implication checks because 1219 * we look at the PMSA bit to see if we should add some properties. 1220 */ 1221 if (arm_feature(&cpu->env, ARM_FEATURE_M)) { 1222 set_feature(&cpu->env, ARM_FEATURE_PMSA); 1223 } 1224 1225 if (arm_feature(&cpu->env, ARM_FEATURE_CBAR) || 1226 arm_feature(&cpu->env, ARM_FEATURE_CBAR_RO)) { 1227 qdev_property_add_static(DEVICE(obj), &arm_cpu_reset_cbar_property); 1228 } 1229 1230 if (!arm_feature(&cpu->env, ARM_FEATURE_M)) { 1231 qdev_property_add_static(DEVICE(obj), &arm_cpu_reset_hivecs_property); 1232 } 1233 1234 if (arm_feature(&cpu->env, ARM_FEATURE_AARCH64)) { 1235 qdev_property_add_static(DEVICE(obj), &arm_cpu_rvbar_property); 1236 } 1237 1238 #ifndef CONFIG_USER_ONLY 1239 if (arm_feature(&cpu->env, ARM_FEATURE_EL3)) { 1240 /* Add the has_el3 state CPU property only if EL3 is allowed. This will 1241 * prevent "has_el3" from existing on CPUs which cannot support EL3. 1242 */ 1243 qdev_property_add_static(DEVICE(obj), &arm_cpu_has_el3_property); 1244 1245 object_property_add_link(obj, "secure-memory", 1246 TYPE_MEMORY_REGION, 1247 (Object **)&cpu->secure_memory, 1248 qdev_prop_allow_set_link_before_realize, 1249 OBJ_PROP_LINK_STRONG); 1250 } 1251 1252 if (arm_feature(&cpu->env, ARM_FEATURE_EL2)) { 1253 qdev_property_add_static(DEVICE(obj), &arm_cpu_has_el2_property); 1254 } 1255 #endif 1256 1257 if (arm_feature(&cpu->env, ARM_FEATURE_PMU)) { 1258 cpu->has_pmu = true; 1259 object_property_add_bool(obj, "pmu", arm_get_pmu, arm_set_pmu); 1260 } 1261 1262 /* 1263 * Allow user to turn off VFP and Neon support, but only for TCG -- 1264 * KVM does not currently allow us to lie to the guest about its 1265 * ID/feature registers, so the guest always sees what the host has. 1266 */ 1267 if (arm_feature(&cpu->env, ARM_FEATURE_AARCH64) 1268 ? cpu_isar_feature(aa64_fp_simd, cpu) 1269 : cpu_isar_feature(aa32_vfp, cpu)) { 1270 cpu->has_vfp = true; 1271 if (!kvm_enabled()) { 1272 qdev_property_add_static(DEVICE(obj), &arm_cpu_has_vfp_property); 1273 } 1274 } 1275 1276 if (arm_feature(&cpu->env, ARM_FEATURE_NEON)) { 1277 cpu->has_neon = true; 1278 if (!kvm_enabled()) { 1279 qdev_property_add_static(DEVICE(obj), &arm_cpu_has_neon_property); 1280 } 1281 } 1282 1283 if (arm_feature(&cpu->env, ARM_FEATURE_M) && 1284 arm_feature(&cpu->env, ARM_FEATURE_THUMB_DSP)) { 1285 qdev_property_add_static(DEVICE(obj), &arm_cpu_has_dsp_property); 1286 } 1287 1288 if (arm_feature(&cpu->env, ARM_FEATURE_PMSA)) { 1289 qdev_property_add_static(DEVICE(obj), &arm_cpu_has_mpu_property); 1290 if (arm_feature(&cpu->env, ARM_FEATURE_V7)) { 1291 qdev_property_add_static(DEVICE(obj), 1292 &arm_cpu_pmsav7_dregion_property); 1293 } 1294 } 1295 1296 if (arm_feature(&cpu->env, ARM_FEATURE_M_SECURITY)) { 1297 object_property_add_link(obj, "idau", TYPE_IDAU_INTERFACE, &cpu->idau, 1298 qdev_prop_allow_set_link_before_realize, 1299 OBJ_PROP_LINK_STRONG); 1300 /* 1301 * M profile: initial value of the Secure VTOR. We can't just use 1302 * a simple DEFINE_PROP_UINT32 for this because we want to permit 1303 * the property to be set after realize. 1304 */ 1305 object_property_add_uint32_ptr(obj, "init-svtor", 1306 &cpu->init_svtor, 1307 OBJ_PROP_FLAG_READWRITE); 1308 } 1309 if (arm_feature(&cpu->env, ARM_FEATURE_M)) { 1310 /* 1311 * Initial value of the NS VTOR (for cores without the Security 1312 * extension, this is the only VTOR) 1313 */ 1314 object_property_add_uint32_ptr(obj, "init-nsvtor", 1315 &cpu->init_nsvtor, 1316 OBJ_PROP_FLAG_READWRITE); 1317 } 1318 1319 /* Not DEFINE_PROP_UINT32: we want this to be settable after realize */ 1320 object_property_add_uint32_ptr(obj, "psci-conduit", 1321 &cpu->psci_conduit, 1322 OBJ_PROP_FLAG_READWRITE); 1323 1324 qdev_property_add_static(DEVICE(obj), &arm_cpu_cfgend_property); 1325 1326 if (arm_feature(&cpu->env, ARM_FEATURE_GENERIC_TIMER)) { 1327 qdev_property_add_static(DEVICE(cpu), &arm_cpu_gt_cntfrq_property); 1328 } 1329 1330 if (kvm_enabled()) { 1331 kvm_arm_add_vcpu_properties(obj); 1332 } 1333 1334 #ifndef CONFIG_USER_ONLY 1335 if (arm_feature(&cpu->env, ARM_FEATURE_AARCH64) && 1336 cpu_isar_feature(aa64_mte, cpu)) { 1337 object_property_add_link(obj, "tag-memory", 1338 TYPE_MEMORY_REGION, 1339 (Object **)&cpu->tag_memory, 1340 qdev_prop_allow_set_link_before_realize, 1341 OBJ_PROP_LINK_STRONG); 1342 1343 if (arm_feature(&cpu->env, ARM_FEATURE_EL3)) { 1344 object_property_add_link(obj, "secure-tag-memory", 1345 TYPE_MEMORY_REGION, 1346 (Object **)&cpu->secure_tag_memory, 1347 qdev_prop_allow_set_link_before_realize, 1348 OBJ_PROP_LINK_STRONG); 1349 } 1350 } 1351 #endif 1352 } 1353 1354 static void arm_cpu_finalizefn(Object *obj) 1355 { 1356 ARMCPU *cpu = ARM_CPU(obj); 1357 ARMELChangeHook *hook, *next; 1358 1359 g_hash_table_destroy(cpu->cp_regs); 1360 1361 QLIST_FOREACH_SAFE(hook, &cpu->pre_el_change_hooks, node, next) { 1362 QLIST_REMOVE(hook, node); 1363 g_free(hook); 1364 } 1365 QLIST_FOREACH_SAFE(hook, &cpu->el_change_hooks, node, next) { 1366 QLIST_REMOVE(hook, node); 1367 g_free(hook); 1368 } 1369 #ifndef CONFIG_USER_ONLY 1370 if (cpu->pmu_timer) { 1371 timer_free(cpu->pmu_timer); 1372 } 1373 #endif 1374 } 1375 1376 void arm_cpu_finalize_features(ARMCPU *cpu, Error **errp) 1377 { 1378 Error *local_err = NULL; 1379 1380 if (arm_feature(&cpu->env, ARM_FEATURE_AARCH64)) { 1381 arm_cpu_sve_finalize(cpu, &local_err); 1382 if (local_err != NULL) { 1383 error_propagate(errp, local_err); 1384 return; 1385 } 1386 1387 arm_cpu_pauth_finalize(cpu, &local_err); 1388 if (local_err != NULL) { 1389 error_propagate(errp, local_err); 1390 return; 1391 } 1392 } 1393 1394 if (kvm_enabled()) { 1395 kvm_arm_steal_time_finalize(cpu, &local_err); 1396 if (local_err != NULL) { 1397 error_propagate(errp, local_err); 1398 return; 1399 } 1400 } 1401 } 1402 1403 static void arm_cpu_realizefn(DeviceState *dev, Error **errp) 1404 { 1405 CPUState *cs = CPU(dev); 1406 ARMCPU *cpu = ARM_CPU(dev); 1407 ARMCPUClass *acc = ARM_CPU_GET_CLASS(dev); 1408 CPUARMState *env = &cpu->env; 1409 int pagebits; 1410 Error *local_err = NULL; 1411 bool no_aa32 = false; 1412 1413 /* If we needed to query the host kernel for the CPU features 1414 * then it's possible that might have failed in the initfn, but 1415 * this is the first point where we can report it. 1416 */ 1417 if (cpu->host_cpu_probe_failed) { 1418 if (!kvm_enabled() && !hvf_enabled()) { 1419 error_setg(errp, "The 'host' CPU type can only be used with KVM or HVF"); 1420 } else { 1421 error_setg(errp, "Failed to retrieve host CPU features"); 1422 } 1423 return; 1424 } 1425 1426 #ifndef CONFIG_USER_ONLY 1427 /* The NVIC and M-profile CPU are two halves of a single piece of 1428 * hardware; trying to use one without the other is a command line 1429 * error and will result in segfaults if not caught here. 1430 */ 1431 if (arm_feature(env, ARM_FEATURE_M)) { 1432 if (!env->nvic) { 1433 error_setg(errp, "This board cannot be used with Cortex-M CPUs"); 1434 return; 1435 } 1436 } else { 1437 if (env->nvic) { 1438 error_setg(errp, "This board can only be used with Cortex-M CPUs"); 1439 return; 1440 } 1441 } 1442 1443 if (kvm_enabled()) { 1444 /* 1445 * Catch all the cases which might cause us to create more than one 1446 * address space for the CPU (otherwise we will assert() later in 1447 * cpu_address_space_init()). 1448 */ 1449 if (arm_feature(env, ARM_FEATURE_M)) { 1450 error_setg(errp, 1451 "Cannot enable KVM when using an M-profile guest CPU"); 1452 return; 1453 } 1454 if (cpu->has_el3) { 1455 error_setg(errp, 1456 "Cannot enable KVM when guest CPU has EL3 enabled"); 1457 return; 1458 } 1459 if (cpu->tag_memory) { 1460 error_setg(errp, 1461 "Cannot enable KVM when guest CPUs has MTE enabled"); 1462 return; 1463 } 1464 } 1465 1466 { 1467 uint64_t scale; 1468 1469 if (arm_feature(env, ARM_FEATURE_GENERIC_TIMER)) { 1470 if (!cpu->gt_cntfrq_hz) { 1471 error_setg(errp, "Invalid CNTFRQ: %"PRId64"Hz", 1472 cpu->gt_cntfrq_hz); 1473 return; 1474 } 1475 scale = gt_cntfrq_period_ns(cpu); 1476 } else { 1477 scale = GTIMER_SCALE; 1478 } 1479 1480 cpu->gt_timer[GTIMER_PHYS] = timer_new(QEMU_CLOCK_VIRTUAL, scale, 1481 arm_gt_ptimer_cb, cpu); 1482 cpu->gt_timer[GTIMER_VIRT] = timer_new(QEMU_CLOCK_VIRTUAL, scale, 1483 arm_gt_vtimer_cb, cpu); 1484 cpu->gt_timer[GTIMER_HYP] = timer_new(QEMU_CLOCK_VIRTUAL, scale, 1485 arm_gt_htimer_cb, cpu); 1486 cpu->gt_timer[GTIMER_SEC] = timer_new(QEMU_CLOCK_VIRTUAL, scale, 1487 arm_gt_stimer_cb, cpu); 1488 cpu->gt_timer[GTIMER_HYPVIRT] = timer_new(QEMU_CLOCK_VIRTUAL, scale, 1489 arm_gt_hvtimer_cb, cpu); 1490 } 1491 #endif 1492 1493 cpu_exec_realizefn(cs, &local_err); 1494 if (local_err != NULL) { 1495 error_propagate(errp, local_err); 1496 return; 1497 } 1498 1499 arm_cpu_finalize_features(cpu, &local_err); 1500 if (local_err != NULL) { 1501 error_propagate(errp, local_err); 1502 return; 1503 } 1504 1505 if (arm_feature(env, ARM_FEATURE_AARCH64) && 1506 cpu->has_vfp != cpu->has_neon) { 1507 /* 1508 * This is an architectural requirement for AArch64; AArch32 is 1509 * more flexible and permits VFP-no-Neon and Neon-no-VFP. 1510 */ 1511 error_setg(errp, 1512 "AArch64 CPUs must have both VFP and Neon or neither"); 1513 return; 1514 } 1515 1516 if (!cpu->has_vfp) { 1517 uint64_t t; 1518 uint32_t u; 1519 1520 t = cpu->isar.id_aa64isar1; 1521 t = FIELD_DP64(t, ID_AA64ISAR1, JSCVT, 0); 1522 cpu->isar.id_aa64isar1 = t; 1523 1524 t = cpu->isar.id_aa64pfr0; 1525 t = FIELD_DP64(t, ID_AA64PFR0, FP, 0xf); 1526 cpu->isar.id_aa64pfr0 = t; 1527 1528 u = cpu->isar.id_isar6; 1529 u = FIELD_DP32(u, ID_ISAR6, JSCVT, 0); 1530 u = FIELD_DP32(u, ID_ISAR6, BF16, 0); 1531 cpu->isar.id_isar6 = u; 1532 1533 u = cpu->isar.mvfr0; 1534 u = FIELD_DP32(u, MVFR0, FPSP, 0); 1535 u = FIELD_DP32(u, MVFR0, FPDP, 0); 1536 u = FIELD_DP32(u, MVFR0, FPDIVIDE, 0); 1537 u = FIELD_DP32(u, MVFR0, FPSQRT, 0); 1538 u = FIELD_DP32(u, MVFR0, FPROUND, 0); 1539 if (!arm_feature(env, ARM_FEATURE_M)) { 1540 u = FIELD_DP32(u, MVFR0, FPTRAP, 0); 1541 u = FIELD_DP32(u, MVFR0, FPSHVEC, 0); 1542 } 1543 cpu->isar.mvfr0 = u; 1544 1545 u = cpu->isar.mvfr1; 1546 u = FIELD_DP32(u, MVFR1, FPFTZ, 0); 1547 u = FIELD_DP32(u, MVFR1, FPDNAN, 0); 1548 u = FIELD_DP32(u, MVFR1, FPHP, 0); 1549 if (arm_feature(env, ARM_FEATURE_M)) { 1550 u = FIELD_DP32(u, MVFR1, FP16, 0); 1551 } 1552 cpu->isar.mvfr1 = u; 1553 1554 u = cpu->isar.mvfr2; 1555 u = FIELD_DP32(u, MVFR2, FPMISC, 0); 1556 cpu->isar.mvfr2 = u; 1557 } 1558 1559 if (!cpu->has_neon) { 1560 uint64_t t; 1561 uint32_t u; 1562 1563 unset_feature(env, ARM_FEATURE_NEON); 1564 1565 t = cpu->isar.id_aa64isar0; 1566 t = FIELD_DP64(t, ID_AA64ISAR0, DP, 0); 1567 cpu->isar.id_aa64isar0 = t; 1568 1569 t = cpu->isar.id_aa64isar1; 1570 t = FIELD_DP64(t, ID_AA64ISAR1, FCMA, 0); 1571 t = FIELD_DP64(t, ID_AA64ISAR1, BF16, 0); 1572 t = FIELD_DP64(t, ID_AA64ISAR1, I8MM, 0); 1573 cpu->isar.id_aa64isar1 = t; 1574 1575 t = cpu->isar.id_aa64pfr0; 1576 t = FIELD_DP64(t, ID_AA64PFR0, ADVSIMD, 0xf); 1577 cpu->isar.id_aa64pfr0 = t; 1578 1579 u = cpu->isar.id_isar5; 1580 u = FIELD_DP32(u, ID_ISAR5, RDM, 0); 1581 u = FIELD_DP32(u, ID_ISAR5, VCMA, 0); 1582 cpu->isar.id_isar5 = u; 1583 1584 u = cpu->isar.id_isar6; 1585 u = FIELD_DP32(u, ID_ISAR6, DP, 0); 1586 u = FIELD_DP32(u, ID_ISAR6, FHM, 0); 1587 u = FIELD_DP32(u, ID_ISAR6, BF16, 0); 1588 u = FIELD_DP32(u, ID_ISAR6, I8MM, 0); 1589 cpu->isar.id_isar6 = u; 1590 1591 if (!arm_feature(env, ARM_FEATURE_M)) { 1592 u = cpu->isar.mvfr1; 1593 u = FIELD_DP32(u, MVFR1, SIMDLS, 0); 1594 u = FIELD_DP32(u, MVFR1, SIMDINT, 0); 1595 u = FIELD_DP32(u, MVFR1, SIMDSP, 0); 1596 u = FIELD_DP32(u, MVFR1, SIMDHP, 0); 1597 cpu->isar.mvfr1 = u; 1598 1599 u = cpu->isar.mvfr2; 1600 u = FIELD_DP32(u, MVFR2, SIMDMISC, 0); 1601 cpu->isar.mvfr2 = u; 1602 } 1603 } 1604 1605 if (!cpu->has_neon && !cpu->has_vfp) { 1606 uint64_t t; 1607 uint32_t u; 1608 1609 t = cpu->isar.id_aa64isar0; 1610 t = FIELD_DP64(t, ID_AA64ISAR0, FHM, 0); 1611 cpu->isar.id_aa64isar0 = t; 1612 1613 t = cpu->isar.id_aa64isar1; 1614 t = FIELD_DP64(t, ID_AA64ISAR1, FRINTTS, 0); 1615 cpu->isar.id_aa64isar1 = t; 1616 1617 u = cpu->isar.mvfr0; 1618 u = FIELD_DP32(u, MVFR0, SIMDREG, 0); 1619 cpu->isar.mvfr0 = u; 1620 1621 /* Despite the name, this field covers both VFP and Neon */ 1622 u = cpu->isar.mvfr1; 1623 u = FIELD_DP32(u, MVFR1, SIMDFMAC, 0); 1624 cpu->isar.mvfr1 = u; 1625 } 1626 1627 if (arm_feature(env, ARM_FEATURE_M) && !cpu->has_dsp) { 1628 uint32_t u; 1629 1630 unset_feature(env, ARM_FEATURE_THUMB_DSP); 1631 1632 u = cpu->isar.id_isar1; 1633 u = FIELD_DP32(u, ID_ISAR1, EXTEND, 1); 1634 cpu->isar.id_isar1 = u; 1635 1636 u = cpu->isar.id_isar2; 1637 u = FIELD_DP32(u, ID_ISAR2, MULTU, 1); 1638 u = FIELD_DP32(u, ID_ISAR2, MULTS, 1); 1639 cpu->isar.id_isar2 = u; 1640 1641 u = cpu->isar.id_isar3; 1642 u = FIELD_DP32(u, ID_ISAR3, SIMD, 1); 1643 u = FIELD_DP32(u, ID_ISAR3, SATURATE, 0); 1644 cpu->isar.id_isar3 = u; 1645 } 1646 1647 /* Some features automatically imply others: */ 1648 if (arm_feature(env, ARM_FEATURE_V8)) { 1649 if (arm_feature(env, ARM_FEATURE_M)) { 1650 set_feature(env, ARM_FEATURE_V7); 1651 } else { 1652 set_feature(env, ARM_FEATURE_V7VE); 1653 } 1654 } 1655 1656 /* 1657 * There exist AArch64 cpus without AArch32 support. When KVM 1658 * queries ID_ISAR0_EL1 on such a host, the value is UNKNOWN. 1659 * Similarly, we cannot check ID_AA64PFR0 without AArch64 support. 1660 * As a general principle, we also do not make ID register 1661 * consistency checks anywhere unless using TCG, because only 1662 * for TCG would a consistency-check failure be a QEMU bug. 1663 */ 1664 if (arm_feature(&cpu->env, ARM_FEATURE_AARCH64)) { 1665 no_aa32 = !cpu_isar_feature(aa64_aa32, cpu); 1666 } 1667 1668 if (arm_feature(env, ARM_FEATURE_V7VE)) { 1669 /* v7 Virtualization Extensions. In real hardware this implies 1670 * EL2 and also the presence of the Security Extensions. 1671 * For QEMU, for backwards-compatibility we implement some 1672 * CPUs or CPU configs which have no actual EL2 or EL3 but do 1673 * include the various other features that V7VE implies. 1674 * Presence of EL2 itself is ARM_FEATURE_EL2, and of the 1675 * Security Extensions is ARM_FEATURE_EL3. 1676 */ 1677 assert(!tcg_enabled() || no_aa32 || 1678 cpu_isar_feature(aa32_arm_div, cpu)); 1679 set_feature(env, ARM_FEATURE_LPAE); 1680 set_feature(env, ARM_FEATURE_V7); 1681 } 1682 if (arm_feature(env, ARM_FEATURE_V7)) { 1683 set_feature(env, ARM_FEATURE_VAPA); 1684 set_feature(env, ARM_FEATURE_THUMB2); 1685 set_feature(env, ARM_FEATURE_MPIDR); 1686 if (!arm_feature(env, ARM_FEATURE_M)) { 1687 set_feature(env, ARM_FEATURE_V6K); 1688 } else { 1689 set_feature(env, ARM_FEATURE_V6); 1690 } 1691 1692 /* Always define VBAR for V7 CPUs even if it doesn't exist in 1693 * non-EL3 configs. This is needed by some legacy boards. 1694 */ 1695 set_feature(env, ARM_FEATURE_VBAR); 1696 } 1697 if (arm_feature(env, ARM_FEATURE_V6K)) { 1698 set_feature(env, ARM_FEATURE_V6); 1699 set_feature(env, ARM_FEATURE_MVFR); 1700 } 1701 if (arm_feature(env, ARM_FEATURE_V6)) { 1702 set_feature(env, ARM_FEATURE_V5); 1703 if (!arm_feature(env, ARM_FEATURE_M)) { 1704 assert(!tcg_enabled() || no_aa32 || 1705 cpu_isar_feature(aa32_jazelle, cpu)); 1706 set_feature(env, ARM_FEATURE_AUXCR); 1707 } 1708 } 1709 if (arm_feature(env, ARM_FEATURE_V5)) { 1710 set_feature(env, ARM_FEATURE_V4T); 1711 } 1712 if (arm_feature(env, ARM_FEATURE_LPAE)) { 1713 set_feature(env, ARM_FEATURE_V7MP); 1714 } 1715 if (arm_feature(env, ARM_FEATURE_CBAR_RO)) { 1716 set_feature(env, ARM_FEATURE_CBAR); 1717 } 1718 if (arm_feature(env, ARM_FEATURE_THUMB2) && 1719 !arm_feature(env, ARM_FEATURE_M)) { 1720 set_feature(env, ARM_FEATURE_THUMB_DSP); 1721 } 1722 1723 /* 1724 * We rely on no XScale CPU having VFP so we can use the same bits in the 1725 * TB flags field for VECSTRIDE and XSCALE_CPAR. 1726 */ 1727 assert(arm_feature(&cpu->env, ARM_FEATURE_AARCH64) || 1728 !cpu_isar_feature(aa32_vfp_simd, cpu) || 1729 !arm_feature(env, ARM_FEATURE_XSCALE)); 1730 1731 if (arm_feature(env, ARM_FEATURE_V7) && 1732 !arm_feature(env, ARM_FEATURE_M) && 1733 !arm_feature(env, ARM_FEATURE_PMSA)) { 1734 /* v7VMSA drops support for the old ARMv5 tiny pages, so we 1735 * can use 4K pages. 1736 */ 1737 pagebits = 12; 1738 } else { 1739 /* For CPUs which might have tiny 1K pages, or which have an 1740 * MPU and might have small region sizes, stick with 1K pages. 1741 */ 1742 pagebits = 10; 1743 } 1744 if (!set_preferred_target_page_bits(pagebits)) { 1745 /* This can only ever happen for hotplugging a CPU, or if 1746 * the board code incorrectly creates a CPU which it has 1747 * promised via minimum_page_size that it will not. 1748 */ 1749 error_setg(errp, "This CPU requires a smaller page size than the " 1750 "system is using"); 1751 return; 1752 } 1753 1754 /* This cpu-id-to-MPIDR affinity is used only for TCG; KVM will override it. 1755 * We don't support setting cluster ID ([16..23]) (known as Aff2 1756 * in later ARM ARM versions), or any of the higher affinity level fields, 1757 * so these bits always RAZ. 1758 */ 1759 if (cpu->mp_affinity == ARM64_AFFINITY_INVALID) { 1760 cpu->mp_affinity = arm_cpu_mp_affinity(cs->cpu_index, 1761 ARM_DEFAULT_CPUS_PER_CLUSTER); 1762 } 1763 1764 if (cpu->reset_hivecs) { 1765 cpu->reset_sctlr |= (1 << 13); 1766 } 1767 1768 if (cpu->cfgend) { 1769 if (arm_feature(&cpu->env, ARM_FEATURE_V7)) { 1770 cpu->reset_sctlr |= SCTLR_EE; 1771 } else { 1772 cpu->reset_sctlr |= SCTLR_B; 1773 } 1774 } 1775 1776 if (!arm_feature(env, ARM_FEATURE_M) && !cpu->has_el3) { 1777 /* If the has_el3 CPU property is disabled then we need to disable the 1778 * feature. 1779 */ 1780 unset_feature(env, ARM_FEATURE_EL3); 1781 1782 /* Disable the security extension feature bits in the processor feature 1783 * registers as well. These are id_pfr1[7:4] and id_aa64pfr0[15:12]. 1784 */ 1785 cpu->isar.id_pfr1 &= ~0xf0; 1786 cpu->isar.id_aa64pfr0 &= ~0xf000; 1787 } 1788 1789 if (!cpu->has_el2) { 1790 unset_feature(env, ARM_FEATURE_EL2); 1791 } 1792 1793 if (!cpu->has_pmu) { 1794 unset_feature(env, ARM_FEATURE_PMU); 1795 } 1796 if (arm_feature(env, ARM_FEATURE_PMU)) { 1797 pmu_init(cpu); 1798 1799 if (!kvm_enabled()) { 1800 arm_register_pre_el_change_hook(cpu, &pmu_pre_el_change, 0); 1801 arm_register_el_change_hook(cpu, &pmu_post_el_change, 0); 1802 } 1803 1804 #ifndef CONFIG_USER_ONLY 1805 cpu->pmu_timer = timer_new_ns(QEMU_CLOCK_VIRTUAL, arm_pmu_timer_cb, 1806 cpu); 1807 #endif 1808 } else { 1809 cpu->isar.id_aa64dfr0 = 1810 FIELD_DP64(cpu->isar.id_aa64dfr0, ID_AA64DFR0, PMUVER, 0); 1811 cpu->isar.id_dfr0 = FIELD_DP32(cpu->isar.id_dfr0, ID_DFR0, PERFMON, 0); 1812 cpu->pmceid0 = 0; 1813 cpu->pmceid1 = 0; 1814 } 1815 1816 if (!arm_feature(env, ARM_FEATURE_EL2)) { 1817 /* Disable the hypervisor feature bits in the processor feature 1818 * registers if we don't have EL2. These are id_pfr1[15:12] and 1819 * id_aa64pfr0_el1[11:8]. 1820 */ 1821 cpu->isar.id_aa64pfr0 &= ~0xf00; 1822 cpu->isar.id_pfr1 &= ~0xf000; 1823 } 1824 1825 #ifndef CONFIG_USER_ONLY 1826 if (cpu->tag_memory == NULL && cpu_isar_feature(aa64_mte, cpu)) { 1827 /* 1828 * Disable the MTE feature bits if we do not have tag-memory 1829 * provided by the machine. 1830 */ 1831 cpu->isar.id_aa64pfr1 = 1832 FIELD_DP64(cpu->isar.id_aa64pfr1, ID_AA64PFR1, MTE, 0); 1833 } 1834 #endif 1835 1836 /* MPU can be configured out of a PMSA CPU either by setting has-mpu 1837 * to false or by setting pmsav7-dregion to 0. 1838 */ 1839 if (!cpu->has_mpu) { 1840 cpu->pmsav7_dregion = 0; 1841 } 1842 if (cpu->pmsav7_dregion == 0) { 1843 cpu->has_mpu = false; 1844 } 1845 1846 if (arm_feature(env, ARM_FEATURE_PMSA) && 1847 arm_feature(env, ARM_FEATURE_V7)) { 1848 uint32_t nr = cpu->pmsav7_dregion; 1849 1850 if (nr > 0xff) { 1851 error_setg(errp, "PMSAv7 MPU #regions invalid %" PRIu32, nr); 1852 return; 1853 } 1854 1855 if (nr) { 1856 if (arm_feature(env, ARM_FEATURE_V8)) { 1857 /* PMSAv8 */ 1858 env->pmsav8.rbar[M_REG_NS] = g_new0(uint32_t, nr); 1859 env->pmsav8.rlar[M_REG_NS] = g_new0(uint32_t, nr); 1860 if (arm_feature(env, ARM_FEATURE_M_SECURITY)) { 1861 env->pmsav8.rbar[M_REG_S] = g_new0(uint32_t, nr); 1862 env->pmsav8.rlar[M_REG_S] = g_new0(uint32_t, nr); 1863 } 1864 } else { 1865 env->pmsav7.drbar = g_new0(uint32_t, nr); 1866 env->pmsav7.drsr = g_new0(uint32_t, nr); 1867 env->pmsav7.dracr = g_new0(uint32_t, nr); 1868 } 1869 } 1870 } 1871 1872 if (arm_feature(env, ARM_FEATURE_M_SECURITY)) { 1873 uint32_t nr = cpu->sau_sregion; 1874 1875 if (nr > 0xff) { 1876 error_setg(errp, "v8M SAU #regions invalid %" PRIu32, nr); 1877 return; 1878 } 1879 1880 if (nr) { 1881 env->sau.rbar = g_new0(uint32_t, nr); 1882 env->sau.rlar = g_new0(uint32_t, nr); 1883 } 1884 } 1885 1886 if (arm_feature(env, ARM_FEATURE_EL3)) { 1887 set_feature(env, ARM_FEATURE_VBAR); 1888 } 1889 1890 register_cp_regs_for_features(cpu); 1891 arm_cpu_register_gdb_regs_for_features(cpu); 1892 1893 init_cpreg_list(cpu); 1894 1895 #ifndef CONFIG_USER_ONLY 1896 MachineState *ms = MACHINE(qdev_get_machine()); 1897 unsigned int smp_cpus = ms->smp.cpus; 1898 bool has_secure = cpu->has_el3 || arm_feature(env, ARM_FEATURE_M_SECURITY); 1899 1900 /* 1901 * We must set cs->num_ases to the final value before 1902 * the first call to cpu_address_space_init. 1903 */ 1904 if (cpu->tag_memory != NULL) { 1905 cs->num_ases = 3 + has_secure; 1906 } else { 1907 cs->num_ases = 1 + has_secure; 1908 } 1909 1910 if (has_secure) { 1911 if (!cpu->secure_memory) { 1912 cpu->secure_memory = cs->memory; 1913 } 1914 cpu_address_space_init(cs, ARMASIdx_S, "cpu-secure-memory", 1915 cpu->secure_memory); 1916 } 1917 1918 if (cpu->tag_memory != NULL) { 1919 cpu_address_space_init(cs, ARMASIdx_TagNS, "cpu-tag-memory", 1920 cpu->tag_memory); 1921 if (has_secure) { 1922 cpu_address_space_init(cs, ARMASIdx_TagS, "cpu-tag-memory", 1923 cpu->secure_tag_memory); 1924 } 1925 } 1926 1927 cpu_address_space_init(cs, ARMASIdx_NS, "cpu-memory", cs->memory); 1928 1929 /* No core_count specified, default to smp_cpus. */ 1930 if (cpu->core_count == -1) { 1931 cpu->core_count = smp_cpus; 1932 } 1933 #endif 1934 1935 if (tcg_enabled()) { 1936 int dcz_blocklen = 4 << cpu->dcz_blocksize; 1937 1938 /* 1939 * We only support DCZ blocklen that fits on one page. 1940 * 1941 * Architectually this is always true. However TARGET_PAGE_SIZE 1942 * is variable and, for compatibility with -machine virt-2.7, 1943 * is only 1KiB, as an artifact of legacy ARMv5 subpage support. 1944 * But even then, while the largest architectural DCZ blocklen 1945 * is 2KiB, no cpu actually uses such a large blocklen. 1946 */ 1947 assert(dcz_blocklen <= TARGET_PAGE_SIZE); 1948 1949 /* 1950 * We only support DCZ blocksize >= 2*TAG_GRANULE, which is to say 1951 * both nibbles of each byte storing tag data may be written at once. 1952 * Since TAG_GRANULE is 16, this means that blocklen must be >= 32. 1953 */ 1954 if (cpu_isar_feature(aa64_mte, cpu)) { 1955 assert(dcz_blocklen >= 2 * TAG_GRANULE); 1956 } 1957 } 1958 1959 qemu_init_vcpu(cs); 1960 cpu_reset(cs); 1961 1962 acc->parent_realize(dev, errp); 1963 } 1964 1965 static ObjectClass *arm_cpu_class_by_name(const char *cpu_model) 1966 { 1967 ObjectClass *oc; 1968 char *typename; 1969 char **cpuname; 1970 const char *cpunamestr; 1971 1972 cpuname = g_strsplit(cpu_model, ",", 1); 1973 cpunamestr = cpuname[0]; 1974 #ifdef CONFIG_USER_ONLY 1975 /* For backwards compatibility usermode emulation allows "-cpu any", 1976 * which has the same semantics as "-cpu max". 1977 */ 1978 if (!strcmp(cpunamestr, "any")) { 1979 cpunamestr = "max"; 1980 } 1981 #endif 1982 typename = g_strdup_printf(ARM_CPU_TYPE_NAME("%s"), cpunamestr); 1983 oc = object_class_by_name(typename); 1984 g_strfreev(cpuname); 1985 g_free(typename); 1986 if (!oc || !object_class_dynamic_cast(oc, TYPE_ARM_CPU) || 1987 object_class_is_abstract(oc)) { 1988 return NULL; 1989 } 1990 return oc; 1991 } 1992 1993 static Property arm_cpu_properties[] = { 1994 DEFINE_PROP_UINT64("midr", ARMCPU, midr, 0), 1995 DEFINE_PROP_UINT64("mp-affinity", ARMCPU, 1996 mp_affinity, ARM64_AFFINITY_INVALID), 1997 DEFINE_PROP_INT32("node-id", ARMCPU, node_id, CPU_UNSET_NUMA_NODE_ID), 1998 DEFINE_PROP_INT32("core-count", ARMCPU, core_count, -1), 1999 DEFINE_PROP_END_OF_LIST() 2000 }; 2001 2002 static gchar *arm_gdb_arch_name(CPUState *cs) 2003 { 2004 ARMCPU *cpu = ARM_CPU(cs); 2005 CPUARMState *env = &cpu->env; 2006 2007 if (arm_feature(env, ARM_FEATURE_IWMMXT)) { 2008 return g_strdup("iwmmxt"); 2009 } 2010 return g_strdup("arm"); 2011 } 2012 2013 #ifndef CONFIG_USER_ONLY 2014 #include "hw/core/sysemu-cpu-ops.h" 2015 2016 static const struct SysemuCPUOps arm_sysemu_ops = { 2017 .get_phys_page_attrs_debug = arm_cpu_get_phys_page_attrs_debug, 2018 .asidx_from_attrs = arm_asidx_from_attrs, 2019 .write_elf32_note = arm_cpu_write_elf32_note, 2020 .write_elf64_note = arm_cpu_write_elf64_note, 2021 .virtio_is_big_endian = arm_cpu_virtio_is_big_endian, 2022 .legacy_vmsd = &vmstate_arm_cpu, 2023 }; 2024 #endif 2025 2026 #ifdef CONFIG_TCG 2027 static const struct TCGCPUOps arm_tcg_ops = { 2028 .initialize = arm_translate_init, 2029 .synchronize_from_tb = arm_cpu_synchronize_from_tb, 2030 .debug_excp_handler = arm_debug_excp_handler, 2031 2032 #ifdef CONFIG_USER_ONLY 2033 .record_sigsegv = arm_cpu_record_sigsegv, 2034 .record_sigbus = arm_cpu_record_sigbus, 2035 #else 2036 .tlb_fill = arm_cpu_tlb_fill, 2037 .cpu_exec_interrupt = arm_cpu_exec_interrupt, 2038 .do_interrupt = arm_cpu_do_interrupt, 2039 .do_transaction_failed = arm_cpu_do_transaction_failed, 2040 .do_unaligned_access = arm_cpu_do_unaligned_access, 2041 .adjust_watchpoint_address = arm_adjust_watchpoint_address, 2042 .debug_check_watchpoint = arm_debug_check_watchpoint, 2043 .debug_check_breakpoint = arm_debug_check_breakpoint, 2044 #endif /* !CONFIG_USER_ONLY */ 2045 }; 2046 #endif /* CONFIG_TCG */ 2047 2048 static void arm_cpu_class_init(ObjectClass *oc, void *data) 2049 { 2050 ARMCPUClass *acc = ARM_CPU_CLASS(oc); 2051 CPUClass *cc = CPU_CLASS(acc); 2052 DeviceClass *dc = DEVICE_CLASS(oc); 2053 2054 device_class_set_parent_realize(dc, arm_cpu_realizefn, 2055 &acc->parent_realize); 2056 2057 device_class_set_props(dc, arm_cpu_properties); 2058 device_class_set_parent_reset(dc, arm_cpu_reset, &acc->parent_reset); 2059 2060 cc->class_by_name = arm_cpu_class_by_name; 2061 cc->has_work = arm_cpu_has_work; 2062 cc->dump_state = arm_cpu_dump_state; 2063 cc->set_pc = arm_cpu_set_pc; 2064 cc->gdb_read_register = arm_cpu_gdb_read_register; 2065 cc->gdb_write_register = arm_cpu_gdb_write_register; 2066 #ifndef CONFIG_USER_ONLY 2067 cc->sysemu_ops = &arm_sysemu_ops; 2068 #endif 2069 cc->gdb_num_core_regs = 26; 2070 cc->gdb_core_xml_file = "arm-core.xml"; 2071 cc->gdb_arch_name = arm_gdb_arch_name; 2072 cc->gdb_get_dynamic_xml = arm_gdb_get_dynamic_xml; 2073 cc->gdb_stop_before_watchpoint = true; 2074 cc->disas_set_info = arm_disas_set_info; 2075 2076 #ifdef CONFIG_TCG 2077 cc->tcg_ops = &arm_tcg_ops; 2078 #endif /* CONFIG_TCG */ 2079 } 2080 2081 static void arm_cpu_instance_init(Object *obj) 2082 { 2083 ARMCPUClass *acc = ARM_CPU_GET_CLASS(obj); 2084 2085 acc->info->initfn(obj); 2086 arm_cpu_post_init(obj); 2087 } 2088 2089 static void cpu_register_class_init(ObjectClass *oc, void *data) 2090 { 2091 ARMCPUClass *acc = ARM_CPU_CLASS(oc); 2092 2093 acc->info = data; 2094 } 2095 2096 void arm_cpu_register(const ARMCPUInfo *info) 2097 { 2098 TypeInfo type_info = { 2099 .parent = TYPE_ARM_CPU, 2100 .instance_size = sizeof(ARMCPU), 2101 .instance_align = __alignof__(ARMCPU), 2102 .instance_init = arm_cpu_instance_init, 2103 .class_size = sizeof(ARMCPUClass), 2104 .class_init = info->class_init ?: cpu_register_class_init, 2105 .class_data = (void *)info, 2106 }; 2107 2108 type_info.name = g_strdup_printf("%s-" TYPE_ARM_CPU, info->name); 2109 type_register(&type_info); 2110 g_free((void *)type_info.name); 2111 } 2112 2113 static const TypeInfo arm_cpu_type_info = { 2114 .name = TYPE_ARM_CPU, 2115 .parent = TYPE_CPU, 2116 .instance_size = sizeof(ARMCPU), 2117 .instance_align = __alignof__(ARMCPU), 2118 .instance_init = arm_cpu_initfn, 2119 .instance_finalize = arm_cpu_finalizefn, 2120 .abstract = true, 2121 .class_size = sizeof(ARMCPUClass), 2122 .class_init = arm_cpu_class_init, 2123 }; 2124 2125 static void arm_cpu_register_types(void) 2126 { 2127 type_register_static(&arm_cpu_type_info); 2128 } 2129 2130 type_init(arm_cpu_register_types) 2131