1 /* 2 * QEMU ARM CPU 3 * 4 * Copyright (c) 2012 SUSE LINUX Products GmbH 5 * 6 * This program is free software; you can redistribute it and/or 7 * modify it under the terms of the GNU General Public License 8 * as published by the Free Software Foundation; either version 2 9 * of the License, or (at your option) any later version. 10 * 11 * This program is distributed in the hope that it will be useful, 12 * but WITHOUT ANY WARRANTY; without even the implied warranty of 13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 14 * GNU General Public License for more details. 15 * 16 * You should have received a copy of the GNU General Public License 17 * along with this program; if not, see 18 * <http://www.gnu.org/licenses/gpl-2.0.html> 19 */ 20 21 #include "qemu/osdep.h" 22 #include "qemu/qemu-print.h" 23 #include "qemu-common.h" 24 #include "target/arm/idau.h" 25 #include "qemu/module.h" 26 #include "qapi/error.h" 27 #include "qapi/visitor.h" 28 #include "cpu.h" 29 #include "internals.h" 30 #include "exec/exec-all.h" 31 #include "hw/qdev-properties.h" 32 #if !defined(CONFIG_USER_ONLY) 33 #include "hw/loader.h" 34 #include "hw/boards.h" 35 #endif 36 #include "sysemu/sysemu.h" 37 #include "sysemu/tcg.h" 38 #include "sysemu/hw_accel.h" 39 #include "kvm_arm.h" 40 #include "disas/capstone.h" 41 #include "fpu/softfloat.h" 42 43 static void arm_cpu_set_pc(CPUState *cs, vaddr value) 44 { 45 ARMCPU *cpu = ARM_CPU(cs); 46 CPUARMState *env = &cpu->env; 47 48 if (is_a64(env)) { 49 env->pc = value; 50 env->thumb = 0; 51 } else { 52 env->regs[15] = value & ~1; 53 env->thumb = value & 1; 54 } 55 } 56 57 static void arm_cpu_synchronize_from_tb(CPUState *cs, TranslationBlock *tb) 58 { 59 ARMCPU *cpu = ARM_CPU(cs); 60 CPUARMState *env = &cpu->env; 61 62 /* 63 * It's OK to look at env for the current mode here, because it's 64 * never possible for an AArch64 TB to chain to an AArch32 TB. 65 */ 66 if (is_a64(env)) { 67 env->pc = tb->pc; 68 } else { 69 env->regs[15] = tb->pc; 70 } 71 } 72 73 static bool arm_cpu_has_work(CPUState *cs) 74 { 75 ARMCPU *cpu = ARM_CPU(cs); 76 77 return (cpu->power_state != PSCI_OFF) 78 && cs->interrupt_request & 79 (CPU_INTERRUPT_FIQ | CPU_INTERRUPT_HARD 80 | CPU_INTERRUPT_VFIQ | CPU_INTERRUPT_VIRQ 81 | CPU_INTERRUPT_EXITTB); 82 } 83 84 void arm_register_pre_el_change_hook(ARMCPU *cpu, ARMELChangeHookFn *hook, 85 void *opaque) 86 { 87 ARMELChangeHook *entry = g_new0(ARMELChangeHook, 1); 88 89 entry->hook = hook; 90 entry->opaque = opaque; 91 92 QLIST_INSERT_HEAD(&cpu->pre_el_change_hooks, entry, node); 93 } 94 95 void arm_register_el_change_hook(ARMCPU *cpu, ARMELChangeHookFn *hook, 96 void *opaque) 97 { 98 ARMELChangeHook *entry = g_new0(ARMELChangeHook, 1); 99 100 entry->hook = hook; 101 entry->opaque = opaque; 102 103 QLIST_INSERT_HEAD(&cpu->el_change_hooks, entry, node); 104 } 105 106 static void cp_reg_reset(gpointer key, gpointer value, gpointer opaque) 107 { 108 /* Reset a single ARMCPRegInfo register */ 109 ARMCPRegInfo *ri = value; 110 ARMCPU *cpu = opaque; 111 112 if (ri->type & (ARM_CP_SPECIAL | ARM_CP_ALIAS)) { 113 return; 114 } 115 116 if (ri->resetfn) { 117 ri->resetfn(&cpu->env, ri); 118 return; 119 } 120 121 /* A zero offset is never possible as it would be regs[0] 122 * so we use it to indicate that reset is being handled elsewhere. 123 * This is basically only used for fields in non-core coprocessors 124 * (like the pxa2xx ones). 125 */ 126 if (!ri->fieldoffset) { 127 return; 128 } 129 130 if (cpreg_field_is_64bit(ri)) { 131 CPREG_FIELD64(&cpu->env, ri) = ri->resetvalue; 132 } else { 133 CPREG_FIELD32(&cpu->env, ri) = ri->resetvalue; 134 } 135 } 136 137 static void cp_reg_check_reset(gpointer key, gpointer value, gpointer opaque) 138 { 139 /* Purely an assertion check: we've already done reset once, 140 * so now check that running the reset for the cpreg doesn't 141 * change its value. This traps bugs where two different cpregs 142 * both try to reset the same state field but to different values. 143 */ 144 ARMCPRegInfo *ri = value; 145 ARMCPU *cpu = opaque; 146 uint64_t oldvalue, newvalue; 147 148 if (ri->type & (ARM_CP_SPECIAL | ARM_CP_ALIAS | ARM_CP_NO_RAW)) { 149 return; 150 } 151 152 oldvalue = read_raw_cp_reg(&cpu->env, ri); 153 cp_reg_reset(key, value, opaque); 154 newvalue = read_raw_cp_reg(&cpu->env, ri); 155 assert(oldvalue == newvalue); 156 } 157 158 static void arm_cpu_reset(DeviceState *dev) 159 { 160 CPUState *s = CPU(dev); 161 ARMCPU *cpu = ARM_CPU(s); 162 ARMCPUClass *acc = ARM_CPU_GET_CLASS(cpu); 163 CPUARMState *env = &cpu->env; 164 165 acc->parent_reset(dev); 166 167 memset(env, 0, offsetof(CPUARMState, end_reset_fields)); 168 169 g_hash_table_foreach(cpu->cp_regs, cp_reg_reset, cpu); 170 g_hash_table_foreach(cpu->cp_regs, cp_reg_check_reset, cpu); 171 172 env->vfp.xregs[ARM_VFP_FPSID] = cpu->reset_fpsid; 173 env->vfp.xregs[ARM_VFP_MVFR0] = cpu->isar.mvfr0; 174 env->vfp.xregs[ARM_VFP_MVFR1] = cpu->isar.mvfr1; 175 env->vfp.xregs[ARM_VFP_MVFR2] = cpu->isar.mvfr2; 176 177 cpu->power_state = s->start_powered_off ? PSCI_OFF : PSCI_ON; 178 179 if (arm_feature(env, ARM_FEATURE_IWMMXT)) { 180 env->iwmmxt.cregs[ARM_IWMMXT_wCID] = 0x69051000 | 'Q'; 181 } 182 183 if (arm_feature(env, ARM_FEATURE_AARCH64)) { 184 /* 64 bit CPUs always start in 64 bit mode */ 185 env->aarch64 = 1; 186 #if defined(CONFIG_USER_ONLY) 187 env->pstate = PSTATE_MODE_EL0t; 188 /* Userspace expects access to DC ZVA, CTL_EL0 and the cache ops */ 189 env->cp15.sctlr_el[1] |= SCTLR_UCT | SCTLR_UCI | SCTLR_DZE; 190 /* Enable all PAC keys. */ 191 env->cp15.sctlr_el[1] |= (SCTLR_EnIA | SCTLR_EnIB | 192 SCTLR_EnDA | SCTLR_EnDB); 193 /* and to the FP/Neon instructions */ 194 env->cp15.cpacr_el1 = deposit64(env->cp15.cpacr_el1, 20, 2, 3); 195 /* and to the SVE instructions */ 196 env->cp15.cpacr_el1 = deposit64(env->cp15.cpacr_el1, 16, 2, 3); 197 /* with reasonable vector length */ 198 if (cpu_isar_feature(aa64_sve, cpu)) { 199 env->vfp.zcr_el[1] = MIN(cpu->sve_max_vq - 1, 3); 200 } 201 /* 202 * Enable TBI0 and TBI1. While the real kernel only enables TBI0, 203 * turning on both here will produce smaller code and otherwise 204 * make no difference to the user-level emulation. 205 * 206 * In sve_probe_page, we assume that this is set. 207 * Do not modify this without other changes. 208 */ 209 env->cp15.tcr_el[1].raw_tcr = (3ULL << 37); 210 #else 211 /* Reset into the highest available EL */ 212 if (arm_feature(env, ARM_FEATURE_EL3)) { 213 env->pstate = PSTATE_MODE_EL3h; 214 } else if (arm_feature(env, ARM_FEATURE_EL2)) { 215 env->pstate = PSTATE_MODE_EL2h; 216 } else { 217 env->pstate = PSTATE_MODE_EL1h; 218 } 219 env->pc = cpu->rvbar; 220 #endif 221 } else { 222 #if defined(CONFIG_USER_ONLY) 223 /* Userspace expects access to cp10 and cp11 for FP/Neon */ 224 env->cp15.cpacr_el1 = deposit64(env->cp15.cpacr_el1, 20, 4, 0xf); 225 #endif 226 } 227 228 #if defined(CONFIG_USER_ONLY) 229 env->uncached_cpsr = ARM_CPU_MODE_USR; 230 /* For user mode we must enable access to coprocessors */ 231 env->vfp.xregs[ARM_VFP_FPEXC] = 1 << 30; 232 if (arm_feature(env, ARM_FEATURE_IWMMXT)) { 233 env->cp15.c15_cpar = 3; 234 } else if (arm_feature(env, ARM_FEATURE_XSCALE)) { 235 env->cp15.c15_cpar = 1; 236 } 237 #else 238 239 /* 240 * If the highest available EL is EL2, AArch32 will start in Hyp 241 * mode; otherwise it starts in SVC. Note that if we start in 242 * AArch64 then these values in the uncached_cpsr will be ignored. 243 */ 244 if (arm_feature(env, ARM_FEATURE_EL2) && 245 !arm_feature(env, ARM_FEATURE_EL3)) { 246 env->uncached_cpsr = ARM_CPU_MODE_HYP; 247 } else { 248 env->uncached_cpsr = ARM_CPU_MODE_SVC; 249 } 250 env->daif = PSTATE_D | PSTATE_A | PSTATE_I | PSTATE_F; 251 252 if (arm_feature(env, ARM_FEATURE_M)) { 253 uint32_t initial_msp; /* Loaded from 0x0 */ 254 uint32_t initial_pc; /* Loaded from 0x4 */ 255 uint8_t *rom; 256 uint32_t vecbase; 257 258 if (cpu_isar_feature(aa32_lob, cpu)) { 259 /* 260 * LTPSIZE is constant 4 if MVE not implemented, and resets 261 * to an UNKNOWN value if MVE is implemented. We choose to 262 * always reset to 4. 263 */ 264 env->v7m.ltpsize = 4; 265 /* The LTPSIZE field in FPDSCR is constant and reads as 4. */ 266 env->v7m.fpdscr[M_REG_NS] = 4 << FPCR_LTPSIZE_SHIFT; 267 env->v7m.fpdscr[M_REG_S] = 4 << FPCR_LTPSIZE_SHIFT; 268 } 269 270 if (arm_feature(env, ARM_FEATURE_M_SECURITY)) { 271 env->v7m.secure = true; 272 } else { 273 /* This bit resets to 0 if security is supported, but 1 if 274 * it is not. The bit is not present in v7M, but we set it 275 * here so we can avoid having to make checks on it conditional 276 * on ARM_FEATURE_V8 (we don't let the guest see the bit). 277 */ 278 env->v7m.aircr = R_V7M_AIRCR_BFHFNMINS_MASK; 279 /* 280 * Set NSACR to indicate "NS access permitted to everything"; 281 * this avoids having to have all the tests of it being 282 * conditional on ARM_FEATURE_M_SECURITY. Note also that from 283 * v8.1M the guest-visible value of NSACR in a CPU without the 284 * Security Extension is 0xcff. 285 */ 286 env->v7m.nsacr = 0xcff; 287 } 288 289 /* In v7M the reset value of this bit is IMPDEF, but ARM recommends 290 * that it resets to 1, so QEMU always does that rather than making 291 * it dependent on CPU model. In v8M it is RES1. 292 */ 293 env->v7m.ccr[M_REG_NS] = R_V7M_CCR_STKALIGN_MASK; 294 env->v7m.ccr[M_REG_S] = R_V7M_CCR_STKALIGN_MASK; 295 if (arm_feature(env, ARM_FEATURE_V8)) { 296 /* in v8M the NONBASETHRDENA bit [0] is RES1 */ 297 env->v7m.ccr[M_REG_NS] |= R_V7M_CCR_NONBASETHRDENA_MASK; 298 env->v7m.ccr[M_REG_S] |= R_V7M_CCR_NONBASETHRDENA_MASK; 299 } 300 if (!arm_feature(env, ARM_FEATURE_M_MAIN)) { 301 env->v7m.ccr[M_REG_NS] |= R_V7M_CCR_UNALIGN_TRP_MASK; 302 env->v7m.ccr[M_REG_S] |= R_V7M_CCR_UNALIGN_TRP_MASK; 303 } 304 305 if (cpu_isar_feature(aa32_vfp_simd, cpu)) { 306 env->v7m.fpccr[M_REG_NS] = R_V7M_FPCCR_ASPEN_MASK; 307 env->v7m.fpccr[M_REG_S] = R_V7M_FPCCR_ASPEN_MASK | 308 R_V7M_FPCCR_LSPEN_MASK | R_V7M_FPCCR_S_MASK; 309 } 310 /* Unlike A/R profile, M profile defines the reset LR value */ 311 env->regs[14] = 0xffffffff; 312 313 env->v7m.vecbase[M_REG_S] = cpu->init_svtor & 0xffffff80; 314 315 /* Load the initial SP and PC from offset 0 and 4 in the vector table */ 316 vecbase = env->v7m.vecbase[env->v7m.secure]; 317 rom = rom_ptr(vecbase, 8); 318 if (rom) { 319 /* Address zero is covered by ROM which hasn't yet been 320 * copied into physical memory. 321 */ 322 initial_msp = ldl_p(rom); 323 initial_pc = ldl_p(rom + 4); 324 } else { 325 /* Address zero not covered by a ROM blob, or the ROM blob 326 * is in non-modifiable memory and this is a second reset after 327 * it got copied into memory. In the latter case, rom_ptr 328 * will return a NULL pointer and we should use ldl_phys instead. 329 */ 330 initial_msp = ldl_phys(s->as, vecbase); 331 initial_pc = ldl_phys(s->as, vecbase + 4); 332 } 333 334 env->regs[13] = initial_msp & 0xFFFFFFFC; 335 env->regs[15] = initial_pc & ~1; 336 env->thumb = initial_pc & 1; 337 } 338 339 /* AArch32 has a hard highvec setting of 0xFFFF0000. If we are currently 340 * executing as AArch32 then check if highvecs are enabled and 341 * adjust the PC accordingly. 342 */ 343 if (A32_BANKED_CURRENT_REG_GET(env, sctlr) & SCTLR_V) { 344 env->regs[15] = 0xFFFF0000; 345 } 346 347 /* M profile requires that reset clears the exclusive monitor; 348 * A profile does not, but clearing it makes more sense than having it 349 * set with an exclusive access on address zero. 350 */ 351 arm_clear_exclusive(env); 352 353 env->vfp.xregs[ARM_VFP_FPEXC] = 0; 354 #endif 355 356 if (arm_feature(env, ARM_FEATURE_PMSA)) { 357 if (cpu->pmsav7_dregion > 0) { 358 if (arm_feature(env, ARM_FEATURE_V8)) { 359 memset(env->pmsav8.rbar[M_REG_NS], 0, 360 sizeof(*env->pmsav8.rbar[M_REG_NS]) 361 * cpu->pmsav7_dregion); 362 memset(env->pmsav8.rlar[M_REG_NS], 0, 363 sizeof(*env->pmsav8.rlar[M_REG_NS]) 364 * cpu->pmsav7_dregion); 365 if (arm_feature(env, ARM_FEATURE_M_SECURITY)) { 366 memset(env->pmsav8.rbar[M_REG_S], 0, 367 sizeof(*env->pmsav8.rbar[M_REG_S]) 368 * cpu->pmsav7_dregion); 369 memset(env->pmsav8.rlar[M_REG_S], 0, 370 sizeof(*env->pmsav8.rlar[M_REG_S]) 371 * cpu->pmsav7_dregion); 372 } 373 } else if (arm_feature(env, ARM_FEATURE_V7)) { 374 memset(env->pmsav7.drbar, 0, 375 sizeof(*env->pmsav7.drbar) * cpu->pmsav7_dregion); 376 memset(env->pmsav7.drsr, 0, 377 sizeof(*env->pmsav7.drsr) * cpu->pmsav7_dregion); 378 memset(env->pmsav7.dracr, 0, 379 sizeof(*env->pmsav7.dracr) * cpu->pmsav7_dregion); 380 } 381 } 382 env->pmsav7.rnr[M_REG_NS] = 0; 383 env->pmsav7.rnr[M_REG_S] = 0; 384 env->pmsav8.mair0[M_REG_NS] = 0; 385 env->pmsav8.mair0[M_REG_S] = 0; 386 env->pmsav8.mair1[M_REG_NS] = 0; 387 env->pmsav8.mair1[M_REG_S] = 0; 388 } 389 390 if (arm_feature(env, ARM_FEATURE_M_SECURITY)) { 391 if (cpu->sau_sregion > 0) { 392 memset(env->sau.rbar, 0, sizeof(*env->sau.rbar) * cpu->sau_sregion); 393 memset(env->sau.rlar, 0, sizeof(*env->sau.rlar) * cpu->sau_sregion); 394 } 395 env->sau.rnr = 0; 396 /* SAU_CTRL reset value is IMPDEF; we choose 0, which is what 397 * the Cortex-M33 does. 398 */ 399 env->sau.ctrl = 0; 400 } 401 402 set_flush_to_zero(1, &env->vfp.standard_fp_status); 403 set_flush_inputs_to_zero(1, &env->vfp.standard_fp_status); 404 set_default_nan_mode(1, &env->vfp.standard_fp_status); 405 set_default_nan_mode(1, &env->vfp.standard_fp_status_f16); 406 set_float_detect_tininess(float_tininess_before_rounding, 407 &env->vfp.fp_status); 408 set_float_detect_tininess(float_tininess_before_rounding, 409 &env->vfp.standard_fp_status); 410 set_float_detect_tininess(float_tininess_before_rounding, 411 &env->vfp.fp_status_f16); 412 set_float_detect_tininess(float_tininess_before_rounding, 413 &env->vfp.standard_fp_status_f16); 414 #ifndef CONFIG_USER_ONLY 415 if (kvm_enabled()) { 416 kvm_arm_reset_vcpu(cpu); 417 } 418 #endif 419 420 hw_breakpoint_update_all(cpu); 421 hw_watchpoint_update_all(cpu); 422 arm_rebuild_hflags(env); 423 } 424 425 static inline bool arm_excp_unmasked(CPUState *cs, unsigned int excp_idx, 426 unsigned int target_el, 427 unsigned int cur_el, bool secure, 428 uint64_t hcr_el2) 429 { 430 CPUARMState *env = cs->env_ptr; 431 bool pstate_unmasked; 432 bool unmasked = false; 433 434 /* 435 * Don't take exceptions if they target a lower EL. 436 * This check should catch any exceptions that would not be taken 437 * but left pending. 438 */ 439 if (cur_el > target_el) { 440 return false; 441 } 442 443 switch (excp_idx) { 444 case EXCP_FIQ: 445 pstate_unmasked = !(env->daif & PSTATE_F); 446 break; 447 448 case EXCP_IRQ: 449 pstate_unmasked = !(env->daif & PSTATE_I); 450 break; 451 452 case EXCP_VFIQ: 453 if (secure || !(hcr_el2 & HCR_FMO) || (hcr_el2 & HCR_TGE)) { 454 /* VFIQs are only taken when hypervized and non-secure. */ 455 return false; 456 } 457 return !(env->daif & PSTATE_F); 458 case EXCP_VIRQ: 459 if (secure || !(hcr_el2 & HCR_IMO) || (hcr_el2 & HCR_TGE)) { 460 /* VIRQs are only taken when hypervized and non-secure. */ 461 return false; 462 } 463 return !(env->daif & PSTATE_I); 464 default: 465 g_assert_not_reached(); 466 } 467 468 /* 469 * Use the target EL, current execution state and SCR/HCR settings to 470 * determine whether the corresponding CPSR bit is used to mask the 471 * interrupt. 472 */ 473 if ((target_el > cur_el) && (target_el != 1)) { 474 /* Exceptions targeting a higher EL may not be maskable */ 475 if (arm_feature(env, ARM_FEATURE_AARCH64)) { 476 /* 477 * 64-bit masking rules are simple: exceptions to EL3 478 * can't be masked, and exceptions to EL2 can only be 479 * masked from Secure state. The HCR and SCR settings 480 * don't affect the masking logic, only the interrupt routing. 481 */ 482 if (target_el == 3 || !secure) { 483 unmasked = true; 484 } 485 } else { 486 /* 487 * The old 32-bit-only environment has a more complicated 488 * masking setup. HCR and SCR bits not only affect interrupt 489 * routing but also change the behaviour of masking. 490 */ 491 bool hcr, scr; 492 493 switch (excp_idx) { 494 case EXCP_FIQ: 495 /* 496 * If FIQs are routed to EL3 or EL2 then there are cases where 497 * we override the CPSR.F in determining if the exception is 498 * masked or not. If neither of these are set then we fall back 499 * to the CPSR.F setting otherwise we further assess the state 500 * below. 501 */ 502 hcr = hcr_el2 & HCR_FMO; 503 scr = (env->cp15.scr_el3 & SCR_FIQ); 504 505 /* 506 * When EL3 is 32-bit, the SCR.FW bit controls whether the 507 * CPSR.F bit masks FIQ interrupts when taken in non-secure 508 * state. If SCR.FW is set then FIQs can be masked by CPSR.F 509 * when non-secure but only when FIQs are only routed to EL3. 510 */ 511 scr = scr && !((env->cp15.scr_el3 & SCR_FW) && !hcr); 512 break; 513 case EXCP_IRQ: 514 /* 515 * When EL3 execution state is 32-bit, if HCR.IMO is set then 516 * we may override the CPSR.I masking when in non-secure state. 517 * The SCR.IRQ setting has already been taken into consideration 518 * when setting the target EL, so it does not have a further 519 * affect here. 520 */ 521 hcr = hcr_el2 & HCR_IMO; 522 scr = false; 523 break; 524 default: 525 g_assert_not_reached(); 526 } 527 528 if ((scr || hcr) && !secure) { 529 unmasked = true; 530 } 531 } 532 } 533 534 /* 535 * The PSTATE bits only mask the interrupt if we have not overriden the 536 * ability above. 537 */ 538 return unmasked || pstate_unmasked; 539 } 540 541 bool arm_cpu_exec_interrupt(CPUState *cs, int interrupt_request) 542 { 543 CPUClass *cc = CPU_GET_CLASS(cs); 544 CPUARMState *env = cs->env_ptr; 545 uint32_t cur_el = arm_current_el(env); 546 bool secure = arm_is_secure(env); 547 uint64_t hcr_el2 = arm_hcr_el2_eff(env); 548 uint32_t target_el; 549 uint32_t excp_idx; 550 551 /* The prioritization of interrupts is IMPLEMENTATION DEFINED. */ 552 553 if (interrupt_request & CPU_INTERRUPT_FIQ) { 554 excp_idx = EXCP_FIQ; 555 target_el = arm_phys_excp_target_el(cs, excp_idx, cur_el, secure); 556 if (arm_excp_unmasked(cs, excp_idx, target_el, 557 cur_el, secure, hcr_el2)) { 558 goto found; 559 } 560 } 561 if (interrupt_request & CPU_INTERRUPT_HARD) { 562 excp_idx = EXCP_IRQ; 563 target_el = arm_phys_excp_target_el(cs, excp_idx, cur_el, secure); 564 if (arm_excp_unmasked(cs, excp_idx, target_el, 565 cur_el, secure, hcr_el2)) { 566 goto found; 567 } 568 } 569 if (interrupt_request & CPU_INTERRUPT_VIRQ) { 570 excp_idx = EXCP_VIRQ; 571 target_el = 1; 572 if (arm_excp_unmasked(cs, excp_idx, target_el, 573 cur_el, secure, hcr_el2)) { 574 goto found; 575 } 576 } 577 if (interrupt_request & CPU_INTERRUPT_VFIQ) { 578 excp_idx = EXCP_VFIQ; 579 target_el = 1; 580 if (arm_excp_unmasked(cs, excp_idx, target_el, 581 cur_el, secure, hcr_el2)) { 582 goto found; 583 } 584 } 585 return false; 586 587 found: 588 cs->exception_index = excp_idx; 589 env->exception.target_el = target_el; 590 cc->do_interrupt(cs); 591 return true; 592 } 593 594 void arm_cpu_update_virq(ARMCPU *cpu) 595 { 596 /* 597 * Update the interrupt level for VIRQ, which is the logical OR of 598 * the HCR_EL2.VI bit and the input line level from the GIC. 599 */ 600 CPUARMState *env = &cpu->env; 601 CPUState *cs = CPU(cpu); 602 603 bool new_state = (env->cp15.hcr_el2 & HCR_VI) || 604 (env->irq_line_state & CPU_INTERRUPT_VIRQ); 605 606 if (new_state != ((cs->interrupt_request & CPU_INTERRUPT_VIRQ) != 0)) { 607 if (new_state) { 608 cpu_interrupt(cs, CPU_INTERRUPT_VIRQ); 609 } else { 610 cpu_reset_interrupt(cs, CPU_INTERRUPT_VIRQ); 611 } 612 } 613 } 614 615 void arm_cpu_update_vfiq(ARMCPU *cpu) 616 { 617 /* 618 * Update the interrupt level for VFIQ, which is the logical OR of 619 * the HCR_EL2.VF bit and the input line level from the GIC. 620 */ 621 CPUARMState *env = &cpu->env; 622 CPUState *cs = CPU(cpu); 623 624 bool new_state = (env->cp15.hcr_el2 & HCR_VF) || 625 (env->irq_line_state & CPU_INTERRUPT_VFIQ); 626 627 if (new_state != ((cs->interrupt_request & CPU_INTERRUPT_VFIQ) != 0)) { 628 if (new_state) { 629 cpu_interrupt(cs, CPU_INTERRUPT_VFIQ); 630 } else { 631 cpu_reset_interrupt(cs, CPU_INTERRUPT_VFIQ); 632 } 633 } 634 } 635 636 #ifndef CONFIG_USER_ONLY 637 static void arm_cpu_set_irq(void *opaque, int irq, int level) 638 { 639 ARMCPU *cpu = opaque; 640 CPUARMState *env = &cpu->env; 641 CPUState *cs = CPU(cpu); 642 static const int mask[] = { 643 [ARM_CPU_IRQ] = CPU_INTERRUPT_HARD, 644 [ARM_CPU_FIQ] = CPU_INTERRUPT_FIQ, 645 [ARM_CPU_VIRQ] = CPU_INTERRUPT_VIRQ, 646 [ARM_CPU_VFIQ] = CPU_INTERRUPT_VFIQ 647 }; 648 649 if (level) { 650 env->irq_line_state |= mask[irq]; 651 } else { 652 env->irq_line_state &= ~mask[irq]; 653 } 654 655 switch (irq) { 656 case ARM_CPU_VIRQ: 657 assert(arm_feature(env, ARM_FEATURE_EL2)); 658 arm_cpu_update_virq(cpu); 659 break; 660 case ARM_CPU_VFIQ: 661 assert(arm_feature(env, ARM_FEATURE_EL2)); 662 arm_cpu_update_vfiq(cpu); 663 break; 664 case ARM_CPU_IRQ: 665 case ARM_CPU_FIQ: 666 if (level) { 667 cpu_interrupt(cs, mask[irq]); 668 } else { 669 cpu_reset_interrupt(cs, mask[irq]); 670 } 671 break; 672 default: 673 g_assert_not_reached(); 674 } 675 } 676 677 static void arm_cpu_kvm_set_irq(void *opaque, int irq, int level) 678 { 679 #ifdef CONFIG_KVM 680 ARMCPU *cpu = opaque; 681 CPUARMState *env = &cpu->env; 682 CPUState *cs = CPU(cpu); 683 uint32_t linestate_bit; 684 int irq_id; 685 686 switch (irq) { 687 case ARM_CPU_IRQ: 688 irq_id = KVM_ARM_IRQ_CPU_IRQ; 689 linestate_bit = CPU_INTERRUPT_HARD; 690 break; 691 case ARM_CPU_FIQ: 692 irq_id = KVM_ARM_IRQ_CPU_FIQ; 693 linestate_bit = CPU_INTERRUPT_FIQ; 694 break; 695 default: 696 g_assert_not_reached(); 697 } 698 699 if (level) { 700 env->irq_line_state |= linestate_bit; 701 } else { 702 env->irq_line_state &= ~linestate_bit; 703 } 704 kvm_arm_set_irq(cs->cpu_index, KVM_ARM_IRQ_TYPE_CPU, irq_id, !!level); 705 #endif 706 } 707 708 static bool arm_cpu_virtio_is_big_endian(CPUState *cs) 709 { 710 ARMCPU *cpu = ARM_CPU(cs); 711 CPUARMState *env = &cpu->env; 712 713 cpu_synchronize_state(cs); 714 return arm_cpu_data_is_big_endian(env); 715 } 716 717 #endif 718 719 static int 720 print_insn_thumb1(bfd_vma pc, disassemble_info *info) 721 { 722 return print_insn_arm(pc | 1, info); 723 } 724 725 static void arm_disas_set_info(CPUState *cpu, disassemble_info *info) 726 { 727 ARMCPU *ac = ARM_CPU(cpu); 728 CPUARMState *env = &ac->env; 729 bool sctlr_b; 730 731 if (is_a64(env)) { 732 /* We might not be compiled with the A64 disassembler 733 * because it needs a C++ compiler. Leave print_insn 734 * unset in this case to use the caller default behaviour. 735 */ 736 #if defined(CONFIG_ARM_A64_DIS) 737 info->print_insn = print_insn_arm_a64; 738 #endif 739 info->cap_arch = CS_ARCH_ARM64; 740 info->cap_insn_unit = 4; 741 info->cap_insn_split = 4; 742 } else { 743 int cap_mode; 744 if (env->thumb) { 745 info->print_insn = print_insn_thumb1; 746 info->cap_insn_unit = 2; 747 info->cap_insn_split = 4; 748 cap_mode = CS_MODE_THUMB; 749 } else { 750 info->print_insn = print_insn_arm; 751 info->cap_insn_unit = 4; 752 info->cap_insn_split = 4; 753 cap_mode = CS_MODE_ARM; 754 } 755 if (arm_feature(env, ARM_FEATURE_V8)) { 756 cap_mode |= CS_MODE_V8; 757 } 758 if (arm_feature(env, ARM_FEATURE_M)) { 759 cap_mode |= CS_MODE_MCLASS; 760 } 761 info->cap_arch = CS_ARCH_ARM; 762 info->cap_mode = cap_mode; 763 } 764 765 sctlr_b = arm_sctlr_b(env); 766 if (bswap_code(sctlr_b)) { 767 #ifdef TARGET_WORDS_BIGENDIAN 768 info->endian = BFD_ENDIAN_LITTLE; 769 #else 770 info->endian = BFD_ENDIAN_BIG; 771 #endif 772 } 773 info->flags &= ~INSN_ARM_BE32; 774 #ifndef CONFIG_USER_ONLY 775 if (sctlr_b) { 776 info->flags |= INSN_ARM_BE32; 777 } 778 #endif 779 } 780 781 #ifdef TARGET_AARCH64 782 783 static void aarch64_cpu_dump_state(CPUState *cs, FILE *f, int flags) 784 { 785 ARMCPU *cpu = ARM_CPU(cs); 786 CPUARMState *env = &cpu->env; 787 uint32_t psr = pstate_read(env); 788 int i; 789 int el = arm_current_el(env); 790 const char *ns_status; 791 792 qemu_fprintf(f, " PC=%016" PRIx64 " ", env->pc); 793 for (i = 0; i < 32; i++) { 794 if (i == 31) { 795 qemu_fprintf(f, " SP=%016" PRIx64 "\n", env->xregs[i]); 796 } else { 797 qemu_fprintf(f, "X%02d=%016" PRIx64 "%s", i, env->xregs[i], 798 (i + 2) % 3 ? " " : "\n"); 799 } 800 } 801 802 if (arm_feature(env, ARM_FEATURE_EL3) && el != 3) { 803 ns_status = env->cp15.scr_el3 & SCR_NS ? "NS " : "S "; 804 } else { 805 ns_status = ""; 806 } 807 qemu_fprintf(f, "PSTATE=%08x %c%c%c%c %sEL%d%c", 808 psr, 809 psr & PSTATE_N ? 'N' : '-', 810 psr & PSTATE_Z ? 'Z' : '-', 811 psr & PSTATE_C ? 'C' : '-', 812 psr & PSTATE_V ? 'V' : '-', 813 ns_status, 814 el, 815 psr & PSTATE_SP ? 'h' : 't'); 816 817 if (cpu_isar_feature(aa64_bti, cpu)) { 818 qemu_fprintf(f, " BTYPE=%d", (psr & PSTATE_BTYPE) >> 10); 819 } 820 if (!(flags & CPU_DUMP_FPU)) { 821 qemu_fprintf(f, "\n"); 822 return; 823 } 824 if (fp_exception_el(env, el) != 0) { 825 qemu_fprintf(f, " FPU disabled\n"); 826 return; 827 } 828 qemu_fprintf(f, " FPCR=%08x FPSR=%08x\n", 829 vfp_get_fpcr(env), vfp_get_fpsr(env)); 830 831 if (cpu_isar_feature(aa64_sve, cpu) && sve_exception_el(env, el) == 0) { 832 int j, zcr_len = sve_zcr_len_for_el(env, el); 833 834 for (i = 0; i <= FFR_PRED_NUM; i++) { 835 bool eol; 836 if (i == FFR_PRED_NUM) { 837 qemu_fprintf(f, "FFR="); 838 /* It's last, so end the line. */ 839 eol = true; 840 } else { 841 qemu_fprintf(f, "P%02d=", i); 842 switch (zcr_len) { 843 case 0: 844 eol = i % 8 == 7; 845 break; 846 case 1: 847 eol = i % 6 == 5; 848 break; 849 case 2: 850 case 3: 851 eol = i % 3 == 2; 852 break; 853 default: 854 /* More than one quadword per predicate. */ 855 eol = true; 856 break; 857 } 858 } 859 for (j = zcr_len / 4; j >= 0; j--) { 860 int digits; 861 if (j * 4 + 4 <= zcr_len + 1) { 862 digits = 16; 863 } else { 864 digits = (zcr_len % 4 + 1) * 4; 865 } 866 qemu_fprintf(f, "%0*" PRIx64 "%s", digits, 867 env->vfp.pregs[i].p[j], 868 j ? ":" : eol ? "\n" : " "); 869 } 870 } 871 872 for (i = 0; i < 32; i++) { 873 if (zcr_len == 0) { 874 qemu_fprintf(f, "Z%02d=%016" PRIx64 ":%016" PRIx64 "%s", 875 i, env->vfp.zregs[i].d[1], 876 env->vfp.zregs[i].d[0], i & 1 ? "\n" : " "); 877 } else if (zcr_len == 1) { 878 qemu_fprintf(f, "Z%02d=%016" PRIx64 ":%016" PRIx64 879 ":%016" PRIx64 ":%016" PRIx64 "\n", 880 i, env->vfp.zregs[i].d[3], env->vfp.zregs[i].d[2], 881 env->vfp.zregs[i].d[1], env->vfp.zregs[i].d[0]); 882 } else { 883 for (j = zcr_len; j >= 0; j--) { 884 bool odd = (zcr_len - j) % 2 != 0; 885 if (j == zcr_len) { 886 qemu_fprintf(f, "Z%02d[%x-%x]=", i, j, j - 1); 887 } else if (!odd) { 888 if (j > 0) { 889 qemu_fprintf(f, " [%x-%x]=", j, j - 1); 890 } else { 891 qemu_fprintf(f, " [%x]=", j); 892 } 893 } 894 qemu_fprintf(f, "%016" PRIx64 ":%016" PRIx64 "%s", 895 env->vfp.zregs[i].d[j * 2 + 1], 896 env->vfp.zregs[i].d[j * 2], 897 odd || j == 0 ? "\n" : ":"); 898 } 899 } 900 } 901 } else { 902 for (i = 0; i < 32; i++) { 903 uint64_t *q = aa64_vfp_qreg(env, i); 904 qemu_fprintf(f, "Q%02d=%016" PRIx64 ":%016" PRIx64 "%s", 905 i, q[1], q[0], (i & 1 ? "\n" : " ")); 906 } 907 } 908 } 909 910 #else 911 912 static inline void aarch64_cpu_dump_state(CPUState *cs, FILE *f, int flags) 913 { 914 g_assert_not_reached(); 915 } 916 917 #endif 918 919 static void arm_cpu_dump_state(CPUState *cs, FILE *f, int flags) 920 { 921 ARMCPU *cpu = ARM_CPU(cs); 922 CPUARMState *env = &cpu->env; 923 int i; 924 925 if (is_a64(env)) { 926 aarch64_cpu_dump_state(cs, f, flags); 927 return; 928 } 929 930 for (i = 0; i < 16; i++) { 931 qemu_fprintf(f, "R%02d=%08x", i, env->regs[i]); 932 if ((i % 4) == 3) { 933 qemu_fprintf(f, "\n"); 934 } else { 935 qemu_fprintf(f, " "); 936 } 937 } 938 939 if (arm_feature(env, ARM_FEATURE_M)) { 940 uint32_t xpsr = xpsr_read(env); 941 const char *mode; 942 const char *ns_status = ""; 943 944 if (arm_feature(env, ARM_FEATURE_M_SECURITY)) { 945 ns_status = env->v7m.secure ? "S " : "NS "; 946 } 947 948 if (xpsr & XPSR_EXCP) { 949 mode = "handler"; 950 } else { 951 if (env->v7m.control[env->v7m.secure] & R_V7M_CONTROL_NPRIV_MASK) { 952 mode = "unpriv-thread"; 953 } else { 954 mode = "priv-thread"; 955 } 956 } 957 958 qemu_fprintf(f, "XPSR=%08x %c%c%c%c %c %s%s\n", 959 xpsr, 960 xpsr & XPSR_N ? 'N' : '-', 961 xpsr & XPSR_Z ? 'Z' : '-', 962 xpsr & XPSR_C ? 'C' : '-', 963 xpsr & XPSR_V ? 'V' : '-', 964 xpsr & XPSR_T ? 'T' : 'A', 965 ns_status, 966 mode); 967 } else { 968 uint32_t psr = cpsr_read(env); 969 const char *ns_status = ""; 970 971 if (arm_feature(env, ARM_FEATURE_EL3) && 972 (psr & CPSR_M) != ARM_CPU_MODE_MON) { 973 ns_status = env->cp15.scr_el3 & SCR_NS ? "NS " : "S "; 974 } 975 976 qemu_fprintf(f, "PSR=%08x %c%c%c%c %c %s%s%d\n", 977 psr, 978 psr & CPSR_N ? 'N' : '-', 979 psr & CPSR_Z ? 'Z' : '-', 980 psr & CPSR_C ? 'C' : '-', 981 psr & CPSR_V ? 'V' : '-', 982 psr & CPSR_T ? 'T' : 'A', 983 ns_status, 984 aarch32_mode_name(psr), (psr & 0x10) ? 32 : 26); 985 } 986 987 if (flags & CPU_DUMP_FPU) { 988 int numvfpregs = 0; 989 if (cpu_isar_feature(aa32_simd_r32, cpu)) { 990 numvfpregs = 32; 991 } else if (cpu_isar_feature(aa32_vfp_simd, cpu)) { 992 numvfpregs = 16; 993 } 994 for (i = 0; i < numvfpregs; i++) { 995 uint64_t v = *aa32_vfp_dreg(env, i); 996 qemu_fprintf(f, "s%02d=%08x s%02d=%08x d%02d=%016" PRIx64 "\n", 997 i * 2, (uint32_t)v, 998 i * 2 + 1, (uint32_t)(v >> 32), 999 i, v); 1000 } 1001 qemu_fprintf(f, "FPSCR: %08x\n", vfp_get_fpscr(env)); 1002 } 1003 } 1004 1005 uint64_t arm_cpu_mp_affinity(int idx, uint8_t clustersz) 1006 { 1007 uint32_t Aff1 = idx / clustersz; 1008 uint32_t Aff0 = idx % clustersz; 1009 return (Aff1 << ARM_AFF1_SHIFT) | Aff0; 1010 } 1011 1012 static void cpreg_hashtable_data_destroy(gpointer data) 1013 { 1014 /* 1015 * Destroy function for cpu->cp_regs hashtable data entries. 1016 * We must free the name string because it was g_strdup()ed in 1017 * add_cpreg_to_hashtable(). It's OK to cast away the 'const' 1018 * from r->name because we know we definitely allocated it. 1019 */ 1020 ARMCPRegInfo *r = data; 1021 1022 g_free((void *)r->name); 1023 g_free(r); 1024 } 1025 1026 static void arm_cpu_initfn(Object *obj) 1027 { 1028 ARMCPU *cpu = ARM_CPU(obj); 1029 1030 cpu_set_cpustate_pointers(cpu); 1031 cpu->cp_regs = g_hash_table_new_full(g_int_hash, g_int_equal, 1032 g_free, cpreg_hashtable_data_destroy); 1033 1034 QLIST_INIT(&cpu->pre_el_change_hooks); 1035 QLIST_INIT(&cpu->el_change_hooks); 1036 1037 #ifndef CONFIG_USER_ONLY 1038 /* Our inbound IRQ and FIQ lines */ 1039 if (kvm_enabled()) { 1040 /* VIRQ and VFIQ are unused with KVM but we add them to maintain 1041 * the same interface as non-KVM CPUs. 1042 */ 1043 qdev_init_gpio_in(DEVICE(cpu), arm_cpu_kvm_set_irq, 4); 1044 } else { 1045 qdev_init_gpio_in(DEVICE(cpu), arm_cpu_set_irq, 4); 1046 } 1047 1048 qdev_init_gpio_out(DEVICE(cpu), cpu->gt_timer_outputs, 1049 ARRAY_SIZE(cpu->gt_timer_outputs)); 1050 1051 qdev_init_gpio_out_named(DEVICE(cpu), &cpu->gicv3_maintenance_interrupt, 1052 "gicv3-maintenance-interrupt", 1); 1053 qdev_init_gpio_out_named(DEVICE(cpu), &cpu->pmu_interrupt, 1054 "pmu-interrupt", 1); 1055 #endif 1056 1057 /* DTB consumers generally don't in fact care what the 'compatible' 1058 * string is, so always provide some string and trust that a hypothetical 1059 * picky DTB consumer will also provide a helpful error message. 1060 */ 1061 cpu->dtb_compatible = "qemu,unknown"; 1062 cpu->psci_version = 1; /* By default assume PSCI v0.1 */ 1063 cpu->kvm_target = QEMU_KVM_ARM_TARGET_NONE; 1064 1065 if (tcg_enabled()) { 1066 cpu->psci_version = 2; /* TCG implements PSCI 0.2 */ 1067 } 1068 } 1069 1070 static Property arm_cpu_gt_cntfrq_property = 1071 DEFINE_PROP_UINT64("cntfrq", ARMCPU, gt_cntfrq_hz, 1072 NANOSECONDS_PER_SECOND / GTIMER_SCALE); 1073 1074 static Property arm_cpu_reset_cbar_property = 1075 DEFINE_PROP_UINT64("reset-cbar", ARMCPU, reset_cbar, 0); 1076 1077 static Property arm_cpu_reset_hivecs_property = 1078 DEFINE_PROP_BOOL("reset-hivecs", ARMCPU, reset_hivecs, false); 1079 1080 static Property arm_cpu_rvbar_property = 1081 DEFINE_PROP_UINT64("rvbar", ARMCPU, rvbar, 0); 1082 1083 #ifndef CONFIG_USER_ONLY 1084 static Property arm_cpu_has_el2_property = 1085 DEFINE_PROP_BOOL("has_el2", ARMCPU, has_el2, true); 1086 1087 static Property arm_cpu_has_el3_property = 1088 DEFINE_PROP_BOOL("has_el3", ARMCPU, has_el3, true); 1089 #endif 1090 1091 static Property arm_cpu_cfgend_property = 1092 DEFINE_PROP_BOOL("cfgend", ARMCPU, cfgend, false); 1093 1094 static Property arm_cpu_has_vfp_property = 1095 DEFINE_PROP_BOOL("vfp", ARMCPU, has_vfp, true); 1096 1097 static Property arm_cpu_has_neon_property = 1098 DEFINE_PROP_BOOL("neon", ARMCPU, has_neon, true); 1099 1100 static Property arm_cpu_has_dsp_property = 1101 DEFINE_PROP_BOOL("dsp", ARMCPU, has_dsp, true); 1102 1103 static Property arm_cpu_has_mpu_property = 1104 DEFINE_PROP_BOOL("has-mpu", ARMCPU, has_mpu, true); 1105 1106 /* This is like DEFINE_PROP_UINT32 but it doesn't set the default value, 1107 * because the CPU initfn will have already set cpu->pmsav7_dregion to 1108 * the right value for that particular CPU type, and we don't want 1109 * to override that with an incorrect constant value. 1110 */ 1111 static Property arm_cpu_pmsav7_dregion_property = 1112 DEFINE_PROP_UNSIGNED_NODEFAULT("pmsav7-dregion", ARMCPU, 1113 pmsav7_dregion, 1114 qdev_prop_uint32, uint32_t); 1115 1116 static bool arm_get_pmu(Object *obj, Error **errp) 1117 { 1118 ARMCPU *cpu = ARM_CPU(obj); 1119 1120 return cpu->has_pmu; 1121 } 1122 1123 static void arm_set_pmu(Object *obj, bool value, Error **errp) 1124 { 1125 ARMCPU *cpu = ARM_CPU(obj); 1126 1127 if (value) { 1128 if (kvm_enabled() && !kvm_arm_pmu_supported()) { 1129 error_setg(errp, "'pmu' feature not supported by KVM on this host"); 1130 return; 1131 } 1132 set_feature(&cpu->env, ARM_FEATURE_PMU); 1133 } else { 1134 unset_feature(&cpu->env, ARM_FEATURE_PMU); 1135 } 1136 cpu->has_pmu = value; 1137 } 1138 1139 unsigned int gt_cntfrq_period_ns(ARMCPU *cpu) 1140 { 1141 /* 1142 * The exact approach to calculating guest ticks is: 1143 * 1144 * muldiv64(qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL), cpu->gt_cntfrq_hz, 1145 * NANOSECONDS_PER_SECOND); 1146 * 1147 * We don't do that. Rather we intentionally use integer division 1148 * truncation below and in the caller for the conversion of host monotonic 1149 * time to guest ticks to provide the exact inverse for the semantics of 1150 * the QEMUTimer scale factor. QEMUTimer's scale facter is an integer, so 1151 * it loses precision when representing frequencies where 1152 * `(NANOSECONDS_PER_SECOND % cpu->gt_cntfrq) > 0` holds. Failing to 1153 * provide an exact inverse leads to scheduling timers with negative 1154 * periods, which in turn leads to sticky behaviour in the guest. 1155 * 1156 * Finally, CNTFRQ is effectively capped at 1GHz to ensure our scale factor 1157 * cannot become zero. 1158 */ 1159 return NANOSECONDS_PER_SECOND > cpu->gt_cntfrq_hz ? 1160 NANOSECONDS_PER_SECOND / cpu->gt_cntfrq_hz : 1; 1161 } 1162 1163 void arm_cpu_post_init(Object *obj) 1164 { 1165 ARMCPU *cpu = ARM_CPU(obj); 1166 1167 /* M profile implies PMSA. We have to do this here rather than 1168 * in realize with the other feature-implication checks because 1169 * we look at the PMSA bit to see if we should add some properties. 1170 */ 1171 if (arm_feature(&cpu->env, ARM_FEATURE_M)) { 1172 set_feature(&cpu->env, ARM_FEATURE_PMSA); 1173 } 1174 1175 if (arm_feature(&cpu->env, ARM_FEATURE_CBAR) || 1176 arm_feature(&cpu->env, ARM_FEATURE_CBAR_RO)) { 1177 qdev_property_add_static(DEVICE(obj), &arm_cpu_reset_cbar_property); 1178 } 1179 1180 if (!arm_feature(&cpu->env, ARM_FEATURE_M)) { 1181 qdev_property_add_static(DEVICE(obj), &arm_cpu_reset_hivecs_property); 1182 } 1183 1184 if (arm_feature(&cpu->env, ARM_FEATURE_AARCH64)) { 1185 qdev_property_add_static(DEVICE(obj), &arm_cpu_rvbar_property); 1186 } 1187 1188 #ifndef CONFIG_USER_ONLY 1189 if (arm_feature(&cpu->env, ARM_FEATURE_EL3)) { 1190 /* Add the has_el3 state CPU property only if EL3 is allowed. This will 1191 * prevent "has_el3" from existing on CPUs which cannot support EL3. 1192 */ 1193 qdev_property_add_static(DEVICE(obj), &arm_cpu_has_el3_property); 1194 1195 object_property_add_link(obj, "secure-memory", 1196 TYPE_MEMORY_REGION, 1197 (Object **)&cpu->secure_memory, 1198 qdev_prop_allow_set_link_before_realize, 1199 OBJ_PROP_LINK_STRONG); 1200 } 1201 1202 if (arm_feature(&cpu->env, ARM_FEATURE_EL2)) { 1203 qdev_property_add_static(DEVICE(obj), &arm_cpu_has_el2_property); 1204 } 1205 #endif 1206 1207 if (arm_feature(&cpu->env, ARM_FEATURE_PMU)) { 1208 cpu->has_pmu = true; 1209 object_property_add_bool(obj, "pmu", arm_get_pmu, arm_set_pmu); 1210 } 1211 1212 /* 1213 * Allow user to turn off VFP and Neon support, but only for TCG -- 1214 * KVM does not currently allow us to lie to the guest about its 1215 * ID/feature registers, so the guest always sees what the host has. 1216 */ 1217 if (arm_feature(&cpu->env, ARM_FEATURE_AARCH64) 1218 ? cpu_isar_feature(aa64_fp_simd, cpu) 1219 : cpu_isar_feature(aa32_vfp, cpu)) { 1220 cpu->has_vfp = true; 1221 if (!kvm_enabled()) { 1222 qdev_property_add_static(DEVICE(obj), &arm_cpu_has_vfp_property); 1223 } 1224 } 1225 1226 if (arm_feature(&cpu->env, ARM_FEATURE_NEON)) { 1227 cpu->has_neon = true; 1228 if (!kvm_enabled()) { 1229 qdev_property_add_static(DEVICE(obj), &arm_cpu_has_neon_property); 1230 } 1231 } 1232 1233 if (arm_feature(&cpu->env, ARM_FEATURE_M) && 1234 arm_feature(&cpu->env, ARM_FEATURE_THUMB_DSP)) { 1235 qdev_property_add_static(DEVICE(obj), &arm_cpu_has_dsp_property); 1236 } 1237 1238 if (arm_feature(&cpu->env, ARM_FEATURE_PMSA)) { 1239 qdev_property_add_static(DEVICE(obj), &arm_cpu_has_mpu_property); 1240 if (arm_feature(&cpu->env, ARM_FEATURE_V7)) { 1241 qdev_property_add_static(DEVICE(obj), 1242 &arm_cpu_pmsav7_dregion_property); 1243 } 1244 } 1245 1246 if (arm_feature(&cpu->env, ARM_FEATURE_M_SECURITY)) { 1247 object_property_add_link(obj, "idau", TYPE_IDAU_INTERFACE, &cpu->idau, 1248 qdev_prop_allow_set_link_before_realize, 1249 OBJ_PROP_LINK_STRONG); 1250 /* 1251 * M profile: initial value of the Secure VTOR. We can't just use 1252 * a simple DEFINE_PROP_UINT32 for this because we want to permit 1253 * the property to be set after realize. 1254 */ 1255 object_property_add_uint32_ptr(obj, "init-svtor", 1256 &cpu->init_svtor, 1257 OBJ_PROP_FLAG_READWRITE); 1258 } 1259 1260 qdev_property_add_static(DEVICE(obj), &arm_cpu_cfgend_property); 1261 1262 if (arm_feature(&cpu->env, ARM_FEATURE_GENERIC_TIMER)) { 1263 qdev_property_add_static(DEVICE(cpu), &arm_cpu_gt_cntfrq_property); 1264 } 1265 1266 if (kvm_enabled()) { 1267 kvm_arm_add_vcpu_properties(obj); 1268 } 1269 1270 #ifndef CONFIG_USER_ONLY 1271 if (arm_feature(&cpu->env, ARM_FEATURE_AARCH64) && 1272 cpu_isar_feature(aa64_mte, cpu)) { 1273 object_property_add_link(obj, "tag-memory", 1274 TYPE_MEMORY_REGION, 1275 (Object **)&cpu->tag_memory, 1276 qdev_prop_allow_set_link_before_realize, 1277 OBJ_PROP_LINK_STRONG); 1278 1279 if (arm_feature(&cpu->env, ARM_FEATURE_EL3)) { 1280 object_property_add_link(obj, "secure-tag-memory", 1281 TYPE_MEMORY_REGION, 1282 (Object **)&cpu->secure_tag_memory, 1283 qdev_prop_allow_set_link_before_realize, 1284 OBJ_PROP_LINK_STRONG); 1285 } 1286 } 1287 #endif 1288 } 1289 1290 static void arm_cpu_finalizefn(Object *obj) 1291 { 1292 ARMCPU *cpu = ARM_CPU(obj); 1293 ARMELChangeHook *hook, *next; 1294 1295 g_hash_table_destroy(cpu->cp_regs); 1296 1297 QLIST_FOREACH_SAFE(hook, &cpu->pre_el_change_hooks, node, next) { 1298 QLIST_REMOVE(hook, node); 1299 g_free(hook); 1300 } 1301 QLIST_FOREACH_SAFE(hook, &cpu->el_change_hooks, node, next) { 1302 QLIST_REMOVE(hook, node); 1303 g_free(hook); 1304 } 1305 #ifndef CONFIG_USER_ONLY 1306 if (cpu->pmu_timer) { 1307 timer_del(cpu->pmu_timer); 1308 timer_deinit(cpu->pmu_timer); 1309 timer_free(cpu->pmu_timer); 1310 } 1311 #endif 1312 } 1313 1314 void arm_cpu_finalize_features(ARMCPU *cpu, Error **errp) 1315 { 1316 Error *local_err = NULL; 1317 1318 if (arm_feature(&cpu->env, ARM_FEATURE_AARCH64)) { 1319 arm_cpu_sve_finalize(cpu, &local_err); 1320 if (local_err != NULL) { 1321 error_propagate(errp, local_err); 1322 return; 1323 } 1324 } 1325 1326 if (kvm_enabled()) { 1327 kvm_arm_steal_time_finalize(cpu, &local_err); 1328 if (local_err != NULL) { 1329 error_propagate(errp, local_err); 1330 return; 1331 } 1332 } 1333 } 1334 1335 static void arm_cpu_realizefn(DeviceState *dev, Error **errp) 1336 { 1337 CPUState *cs = CPU(dev); 1338 ARMCPU *cpu = ARM_CPU(dev); 1339 ARMCPUClass *acc = ARM_CPU_GET_CLASS(dev); 1340 CPUARMState *env = &cpu->env; 1341 int pagebits; 1342 Error *local_err = NULL; 1343 bool no_aa32 = false; 1344 1345 /* If we needed to query the host kernel for the CPU features 1346 * then it's possible that might have failed in the initfn, but 1347 * this is the first point where we can report it. 1348 */ 1349 if (cpu->host_cpu_probe_failed) { 1350 if (!kvm_enabled()) { 1351 error_setg(errp, "The 'host' CPU type can only be used with KVM"); 1352 } else { 1353 error_setg(errp, "Failed to retrieve host CPU features"); 1354 } 1355 return; 1356 } 1357 1358 #ifndef CONFIG_USER_ONLY 1359 /* The NVIC and M-profile CPU are two halves of a single piece of 1360 * hardware; trying to use one without the other is a command line 1361 * error and will result in segfaults if not caught here. 1362 */ 1363 if (arm_feature(env, ARM_FEATURE_M)) { 1364 if (!env->nvic) { 1365 error_setg(errp, "This board cannot be used with Cortex-M CPUs"); 1366 return; 1367 } 1368 } else { 1369 if (env->nvic) { 1370 error_setg(errp, "This board can only be used with Cortex-M CPUs"); 1371 return; 1372 } 1373 } 1374 1375 { 1376 uint64_t scale; 1377 1378 if (arm_feature(env, ARM_FEATURE_GENERIC_TIMER)) { 1379 if (!cpu->gt_cntfrq_hz) { 1380 error_setg(errp, "Invalid CNTFRQ: %"PRId64"Hz", 1381 cpu->gt_cntfrq_hz); 1382 return; 1383 } 1384 scale = gt_cntfrq_period_ns(cpu); 1385 } else { 1386 scale = GTIMER_SCALE; 1387 } 1388 1389 cpu->gt_timer[GTIMER_PHYS] = timer_new(QEMU_CLOCK_VIRTUAL, scale, 1390 arm_gt_ptimer_cb, cpu); 1391 cpu->gt_timer[GTIMER_VIRT] = timer_new(QEMU_CLOCK_VIRTUAL, scale, 1392 arm_gt_vtimer_cb, cpu); 1393 cpu->gt_timer[GTIMER_HYP] = timer_new(QEMU_CLOCK_VIRTUAL, scale, 1394 arm_gt_htimer_cb, cpu); 1395 cpu->gt_timer[GTIMER_SEC] = timer_new(QEMU_CLOCK_VIRTUAL, scale, 1396 arm_gt_stimer_cb, cpu); 1397 cpu->gt_timer[GTIMER_HYPVIRT] = timer_new(QEMU_CLOCK_VIRTUAL, scale, 1398 arm_gt_hvtimer_cb, cpu); 1399 } 1400 #endif 1401 1402 cpu_exec_realizefn(cs, &local_err); 1403 if (local_err != NULL) { 1404 error_propagate(errp, local_err); 1405 return; 1406 } 1407 1408 arm_cpu_finalize_features(cpu, &local_err); 1409 if (local_err != NULL) { 1410 error_propagate(errp, local_err); 1411 return; 1412 } 1413 1414 if (arm_feature(env, ARM_FEATURE_AARCH64) && 1415 cpu->has_vfp != cpu->has_neon) { 1416 /* 1417 * This is an architectural requirement for AArch64; AArch32 is 1418 * more flexible and permits VFP-no-Neon and Neon-no-VFP. 1419 */ 1420 error_setg(errp, 1421 "AArch64 CPUs must have both VFP and Neon or neither"); 1422 return; 1423 } 1424 1425 if (!cpu->has_vfp) { 1426 uint64_t t; 1427 uint32_t u; 1428 1429 t = cpu->isar.id_aa64isar1; 1430 t = FIELD_DP64(t, ID_AA64ISAR1, JSCVT, 0); 1431 cpu->isar.id_aa64isar1 = t; 1432 1433 t = cpu->isar.id_aa64pfr0; 1434 t = FIELD_DP64(t, ID_AA64PFR0, FP, 0xf); 1435 cpu->isar.id_aa64pfr0 = t; 1436 1437 u = cpu->isar.id_isar6; 1438 u = FIELD_DP32(u, ID_ISAR6, JSCVT, 0); 1439 cpu->isar.id_isar6 = u; 1440 1441 u = cpu->isar.mvfr0; 1442 u = FIELD_DP32(u, MVFR0, FPSP, 0); 1443 u = FIELD_DP32(u, MVFR0, FPDP, 0); 1444 u = FIELD_DP32(u, MVFR0, FPDIVIDE, 0); 1445 u = FIELD_DP32(u, MVFR0, FPSQRT, 0); 1446 u = FIELD_DP32(u, MVFR0, FPROUND, 0); 1447 if (!arm_feature(env, ARM_FEATURE_M)) { 1448 u = FIELD_DP32(u, MVFR0, FPTRAP, 0); 1449 u = FIELD_DP32(u, MVFR0, FPSHVEC, 0); 1450 } 1451 cpu->isar.mvfr0 = u; 1452 1453 u = cpu->isar.mvfr1; 1454 u = FIELD_DP32(u, MVFR1, FPFTZ, 0); 1455 u = FIELD_DP32(u, MVFR1, FPDNAN, 0); 1456 u = FIELD_DP32(u, MVFR1, FPHP, 0); 1457 if (arm_feature(env, ARM_FEATURE_M)) { 1458 u = FIELD_DP32(u, MVFR1, FP16, 0); 1459 } 1460 cpu->isar.mvfr1 = u; 1461 1462 u = cpu->isar.mvfr2; 1463 u = FIELD_DP32(u, MVFR2, FPMISC, 0); 1464 cpu->isar.mvfr2 = u; 1465 } 1466 1467 if (!cpu->has_neon) { 1468 uint64_t t; 1469 uint32_t u; 1470 1471 unset_feature(env, ARM_FEATURE_NEON); 1472 1473 t = cpu->isar.id_aa64isar0; 1474 t = FIELD_DP64(t, ID_AA64ISAR0, DP, 0); 1475 cpu->isar.id_aa64isar0 = t; 1476 1477 t = cpu->isar.id_aa64isar1; 1478 t = FIELD_DP64(t, ID_AA64ISAR1, FCMA, 0); 1479 cpu->isar.id_aa64isar1 = t; 1480 1481 t = cpu->isar.id_aa64pfr0; 1482 t = FIELD_DP64(t, ID_AA64PFR0, ADVSIMD, 0xf); 1483 cpu->isar.id_aa64pfr0 = t; 1484 1485 u = cpu->isar.id_isar5; 1486 u = FIELD_DP32(u, ID_ISAR5, RDM, 0); 1487 u = FIELD_DP32(u, ID_ISAR5, VCMA, 0); 1488 cpu->isar.id_isar5 = u; 1489 1490 u = cpu->isar.id_isar6; 1491 u = FIELD_DP32(u, ID_ISAR6, DP, 0); 1492 u = FIELD_DP32(u, ID_ISAR6, FHM, 0); 1493 cpu->isar.id_isar6 = u; 1494 1495 if (!arm_feature(env, ARM_FEATURE_M)) { 1496 u = cpu->isar.mvfr1; 1497 u = FIELD_DP32(u, MVFR1, SIMDLS, 0); 1498 u = FIELD_DP32(u, MVFR1, SIMDINT, 0); 1499 u = FIELD_DP32(u, MVFR1, SIMDSP, 0); 1500 u = FIELD_DP32(u, MVFR1, SIMDHP, 0); 1501 cpu->isar.mvfr1 = u; 1502 1503 u = cpu->isar.mvfr2; 1504 u = FIELD_DP32(u, MVFR2, SIMDMISC, 0); 1505 cpu->isar.mvfr2 = u; 1506 } 1507 } 1508 1509 if (!cpu->has_neon && !cpu->has_vfp) { 1510 uint64_t t; 1511 uint32_t u; 1512 1513 t = cpu->isar.id_aa64isar0; 1514 t = FIELD_DP64(t, ID_AA64ISAR0, FHM, 0); 1515 cpu->isar.id_aa64isar0 = t; 1516 1517 t = cpu->isar.id_aa64isar1; 1518 t = FIELD_DP64(t, ID_AA64ISAR1, FRINTTS, 0); 1519 cpu->isar.id_aa64isar1 = t; 1520 1521 u = cpu->isar.mvfr0; 1522 u = FIELD_DP32(u, MVFR0, SIMDREG, 0); 1523 cpu->isar.mvfr0 = u; 1524 1525 /* Despite the name, this field covers both VFP and Neon */ 1526 u = cpu->isar.mvfr1; 1527 u = FIELD_DP32(u, MVFR1, SIMDFMAC, 0); 1528 cpu->isar.mvfr1 = u; 1529 } 1530 1531 if (arm_feature(env, ARM_FEATURE_M) && !cpu->has_dsp) { 1532 uint32_t u; 1533 1534 unset_feature(env, ARM_FEATURE_THUMB_DSP); 1535 1536 u = cpu->isar.id_isar1; 1537 u = FIELD_DP32(u, ID_ISAR1, EXTEND, 1); 1538 cpu->isar.id_isar1 = u; 1539 1540 u = cpu->isar.id_isar2; 1541 u = FIELD_DP32(u, ID_ISAR2, MULTU, 1); 1542 u = FIELD_DP32(u, ID_ISAR2, MULTS, 1); 1543 cpu->isar.id_isar2 = u; 1544 1545 u = cpu->isar.id_isar3; 1546 u = FIELD_DP32(u, ID_ISAR3, SIMD, 1); 1547 u = FIELD_DP32(u, ID_ISAR3, SATURATE, 0); 1548 cpu->isar.id_isar3 = u; 1549 } 1550 1551 /* Some features automatically imply others: */ 1552 if (arm_feature(env, ARM_FEATURE_V8)) { 1553 if (arm_feature(env, ARM_FEATURE_M)) { 1554 set_feature(env, ARM_FEATURE_V7); 1555 } else { 1556 set_feature(env, ARM_FEATURE_V7VE); 1557 } 1558 } 1559 1560 /* 1561 * There exist AArch64 cpus without AArch32 support. When KVM 1562 * queries ID_ISAR0_EL1 on such a host, the value is UNKNOWN. 1563 * Similarly, we cannot check ID_AA64PFR0 without AArch64 support. 1564 * As a general principle, we also do not make ID register 1565 * consistency checks anywhere unless using TCG, because only 1566 * for TCG would a consistency-check failure be a QEMU bug. 1567 */ 1568 if (arm_feature(&cpu->env, ARM_FEATURE_AARCH64)) { 1569 no_aa32 = !cpu_isar_feature(aa64_aa32, cpu); 1570 } 1571 1572 if (arm_feature(env, ARM_FEATURE_V7VE)) { 1573 /* v7 Virtualization Extensions. In real hardware this implies 1574 * EL2 and also the presence of the Security Extensions. 1575 * For QEMU, for backwards-compatibility we implement some 1576 * CPUs or CPU configs which have no actual EL2 or EL3 but do 1577 * include the various other features that V7VE implies. 1578 * Presence of EL2 itself is ARM_FEATURE_EL2, and of the 1579 * Security Extensions is ARM_FEATURE_EL3. 1580 */ 1581 assert(!tcg_enabled() || no_aa32 || 1582 cpu_isar_feature(aa32_arm_div, cpu)); 1583 set_feature(env, ARM_FEATURE_LPAE); 1584 set_feature(env, ARM_FEATURE_V7); 1585 } 1586 if (arm_feature(env, ARM_FEATURE_V7)) { 1587 set_feature(env, ARM_FEATURE_VAPA); 1588 set_feature(env, ARM_FEATURE_THUMB2); 1589 set_feature(env, ARM_FEATURE_MPIDR); 1590 if (!arm_feature(env, ARM_FEATURE_M)) { 1591 set_feature(env, ARM_FEATURE_V6K); 1592 } else { 1593 set_feature(env, ARM_FEATURE_V6); 1594 } 1595 1596 /* Always define VBAR for V7 CPUs even if it doesn't exist in 1597 * non-EL3 configs. This is needed by some legacy boards. 1598 */ 1599 set_feature(env, ARM_FEATURE_VBAR); 1600 } 1601 if (arm_feature(env, ARM_FEATURE_V6K)) { 1602 set_feature(env, ARM_FEATURE_V6); 1603 set_feature(env, ARM_FEATURE_MVFR); 1604 } 1605 if (arm_feature(env, ARM_FEATURE_V6)) { 1606 set_feature(env, ARM_FEATURE_V5); 1607 if (!arm_feature(env, ARM_FEATURE_M)) { 1608 assert(!tcg_enabled() || no_aa32 || 1609 cpu_isar_feature(aa32_jazelle, cpu)); 1610 set_feature(env, ARM_FEATURE_AUXCR); 1611 } 1612 } 1613 if (arm_feature(env, ARM_FEATURE_V5)) { 1614 set_feature(env, ARM_FEATURE_V4T); 1615 } 1616 if (arm_feature(env, ARM_FEATURE_LPAE)) { 1617 set_feature(env, ARM_FEATURE_V7MP); 1618 } 1619 if (arm_feature(env, ARM_FEATURE_CBAR_RO)) { 1620 set_feature(env, ARM_FEATURE_CBAR); 1621 } 1622 if (arm_feature(env, ARM_FEATURE_THUMB2) && 1623 !arm_feature(env, ARM_FEATURE_M)) { 1624 set_feature(env, ARM_FEATURE_THUMB_DSP); 1625 } 1626 1627 /* 1628 * We rely on no XScale CPU having VFP so we can use the same bits in the 1629 * TB flags field for VECSTRIDE and XSCALE_CPAR. 1630 */ 1631 assert(arm_feature(&cpu->env, ARM_FEATURE_AARCH64) || 1632 !cpu_isar_feature(aa32_vfp_simd, cpu) || 1633 !arm_feature(env, ARM_FEATURE_XSCALE)); 1634 1635 if (arm_feature(env, ARM_FEATURE_V7) && 1636 !arm_feature(env, ARM_FEATURE_M) && 1637 !arm_feature(env, ARM_FEATURE_PMSA)) { 1638 /* v7VMSA drops support for the old ARMv5 tiny pages, so we 1639 * can use 4K pages. 1640 */ 1641 pagebits = 12; 1642 } else { 1643 /* For CPUs which might have tiny 1K pages, or which have an 1644 * MPU and might have small region sizes, stick with 1K pages. 1645 */ 1646 pagebits = 10; 1647 } 1648 if (!set_preferred_target_page_bits(pagebits)) { 1649 /* This can only ever happen for hotplugging a CPU, or if 1650 * the board code incorrectly creates a CPU which it has 1651 * promised via minimum_page_size that it will not. 1652 */ 1653 error_setg(errp, "This CPU requires a smaller page size than the " 1654 "system is using"); 1655 return; 1656 } 1657 1658 /* This cpu-id-to-MPIDR affinity is used only for TCG; KVM will override it. 1659 * We don't support setting cluster ID ([16..23]) (known as Aff2 1660 * in later ARM ARM versions), or any of the higher affinity level fields, 1661 * so these bits always RAZ. 1662 */ 1663 if (cpu->mp_affinity == ARM64_AFFINITY_INVALID) { 1664 cpu->mp_affinity = arm_cpu_mp_affinity(cs->cpu_index, 1665 ARM_DEFAULT_CPUS_PER_CLUSTER); 1666 } 1667 1668 if (cpu->reset_hivecs) { 1669 cpu->reset_sctlr |= (1 << 13); 1670 } 1671 1672 if (cpu->cfgend) { 1673 if (arm_feature(&cpu->env, ARM_FEATURE_V7)) { 1674 cpu->reset_sctlr |= SCTLR_EE; 1675 } else { 1676 cpu->reset_sctlr |= SCTLR_B; 1677 } 1678 } 1679 1680 if (!arm_feature(env, ARM_FEATURE_M) && !cpu->has_el3) { 1681 /* If the has_el3 CPU property is disabled then we need to disable the 1682 * feature. 1683 */ 1684 unset_feature(env, ARM_FEATURE_EL3); 1685 1686 /* Disable the security extension feature bits in the processor feature 1687 * registers as well. These are id_pfr1[7:4] and id_aa64pfr0[15:12]. 1688 */ 1689 cpu->isar.id_pfr1 &= ~0xf0; 1690 cpu->isar.id_aa64pfr0 &= ~0xf000; 1691 } 1692 1693 if (!cpu->has_el2) { 1694 unset_feature(env, ARM_FEATURE_EL2); 1695 } 1696 1697 if (!cpu->has_pmu) { 1698 unset_feature(env, ARM_FEATURE_PMU); 1699 } 1700 if (arm_feature(env, ARM_FEATURE_PMU)) { 1701 pmu_init(cpu); 1702 1703 if (!kvm_enabled()) { 1704 arm_register_pre_el_change_hook(cpu, &pmu_pre_el_change, 0); 1705 arm_register_el_change_hook(cpu, &pmu_post_el_change, 0); 1706 } 1707 1708 #ifndef CONFIG_USER_ONLY 1709 cpu->pmu_timer = timer_new_ns(QEMU_CLOCK_VIRTUAL, arm_pmu_timer_cb, 1710 cpu); 1711 #endif 1712 } else { 1713 cpu->isar.id_aa64dfr0 = 1714 FIELD_DP64(cpu->isar.id_aa64dfr0, ID_AA64DFR0, PMUVER, 0); 1715 cpu->isar.id_dfr0 = FIELD_DP32(cpu->isar.id_dfr0, ID_DFR0, PERFMON, 0); 1716 cpu->pmceid0 = 0; 1717 cpu->pmceid1 = 0; 1718 } 1719 1720 if (!arm_feature(env, ARM_FEATURE_EL2)) { 1721 /* Disable the hypervisor feature bits in the processor feature 1722 * registers if we don't have EL2. These are id_pfr1[15:12] and 1723 * id_aa64pfr0_el1[11:8]. 1724 */ 1725 cpu->isar.id_aa64pfr0 &= ~0xf00; 1726 cpu->isar.id_pfr1 &= ~0xf000; 1727 } 1728 1729 #ifndef CONFIG_USER_ONLY 1730 if (cpu->tag_memory == NULL && cpu_isar_feature(aa64_mte, cpu)) { 1731 /* 1732 * Disable the MTE feature bits if we do not have tag-memory 1733 * provided by the machine. 1734 */ 1735 cpu->isar.id_aa64pfr1 = 1736 FIELD_DP64(cpu->isar.id_aa64pfr1, ID_AA64PFR1, MTE, 0); 1737 } 1738 #endif 1739 1740 /* MPU can be configured out of a PMSA CPU either by setting has-mpu 1741 * to false or by setting pmsav7-dregion to 0. 1742 */ 1743 if (!cpu->has_mpu) { 1744 cpu->pmsav7_dregion = 0; 1745 } 1746 if (cpu->pmsav7_dregion == 0) { 1747 cpu->has_mpu = false; 1748 } 1749 1750 if (arm_feature(env, ARM_FEATURE_PMSA) && 1751 arm_feature(env, ARM_FEATURE_V7)) { 1752 uint32_t nr = cpu->pmsav7_dregion; 1753 1754 if (nr > 0xff) { 1755 error_setg(errp, "PMSAv7 MPU #regions invalid %" PRIu32, nr); 1756 return; 1757 } 1758 1759 if (nr) { 1760 if (arm_feature(env, ARM_FEATURE_V8)) { 1761 /* PMSAv8 */ 1762 env->pmsav8.rbar[M_REG_NS] = g_new0(uint32_t, nr); 1763 env->pmsav8.rlar[M_REG_NS] = g_new0(uint32_t, nr); 1764 if (arm_feature(env, ARM_FEATURE_M_SECURITY)) { 1765 env->pmsav8.rbar[M_REG_S] = g_new0(uint32_t, nr); 1766 env->pmsav8.rlar[M_REG_S] = g_new0(uint32_t, nr); 1767 } 1768 } else { 1769 env->pmsav7.drbar = g_new0(uint32_t, nr); 1770 env->pmsav7.drsr = g_new0(uint32_t, nr); 1771 env->pmsav7.dracr = g_new0(uint32_t, nr); 1772 } 1773 } 1774 } 1775 1776 if (arm_feature(env, ARM_FEATURE_M_SECURITY)) { 1777 uint32_t nr = cpu->sau_sregion; 1778 1779 if (nr > 0xff) { 1780 error_setg(errp, "v8M SAU #regions invalid %" PRIu32, nr); 1781 return; 1782 } 1783 1784 if (nr) { 1785 env->sau.rbar = g_new0(uint32_t, nr); 1786 env->sau.rlar = g_new0(uint32_t, nr); 1787 } 1788 } 1789 1790 if (arm_feature(env, ARM_FEATURE_EL3)) { 1791 set_feature(env, ARM_FEATURE_VBAR); 1792 } 1793 1794 register_cp_regs_for_features(cpu); 1795 arm_cpu_register_gdb_regs_for_features(cpu); 1796 1797 init_cpreg_list(cpu); 1798 1799 #ifndef CONFIG_USER_ONLY 1800 MachineState *ms = MACHINE(qdev_get_machine()); 1801 unsigned int smp_cpus = ms->smp.cpus; 1802 bool has_secure = cpu->has_el3 || arm_feature(env, ARM_FEATURE_M_SECURITY); 1803 1804 /* 1805 * We must set cs->num_ases to the final value before 1806 * the first call to cpu_address_space_init. 1807 */ 1808 if (cpu->tag_memory != NULL) { 1809 cs->num_ases = 3 + has_secure; 1810 } else { 1811 cs->num_ases = 1 + has_secure; 1812 } 1813 1814 if (has_secure) { 1815 if (!cpu->secure_memory) { 1816 cpu->secure_memory = cs->memory; 1817 } 1818 cpu_address_space_init(cs, ARMASIdx_S, "cpu-secure-memory", 1819 cpu->secure_memory); 1820 } 1821 1822 if (cpu->tag_memory != NULL) { 1823 cpu_address_space_init(cs, ARMASIdx_TagNS, "cpu-tag-memory", 1824 cpu->tag_memory); 1825 if (has_secure) { 1826 cpu_address_space_init(cs, ARMASIdx_TagS, "cpu-tag-memory", 1827 cpu->secure_tag_memory); 1828 } 1829 } 1830 1831 cpu_address_space_init(cs, ARMASIdx_NS, "cpu-memory", cs->memory); 1832 1833 /* No core_count specified, default to smp_cpus. */ 1834 if (cpu->core_count == -1) { 1835 cpu->core_count = smp_cpus; 1836 } 1837 #endif 1838 1839 if (tcg_enabled()) { 1840 int dcz_blocklen = 4 << cpu->dcz_blocksize; 1841 1842 /* 1843 * We only support DCZ blocklen that fits on one page. 1844 * 1845 * Architectually this is always true. However TARGET_PAGE_SIZE 1846 * is variable and, for compatibility with -machine virt-2.7, 1847 * is only 1KiB, as an artifact of legacy ARMv5 subpage support. 1848 * But even then, while the largest architectural DCZ blocklen 1849 * is 2KiB, no cpu actually uses such a large blocklen. 1850 */ 1851 assert(dcz_blocklen <= TARGET_PAGE_SIZE); 1852 1853 /* 1854 * We only support DCZ blocksize >= 2*TAG_GRANULE, which is to say 1855 * both nibbles of each byte storing tag data may be written at once. 1856 * Since TAG_GRANULE is 16, this means that blocklen must be >= 32. 1857 */ 1858 if (cpu_isar_feature(aa64_mte, cpu)) { 1859 assert(dcz_blocklen >= 2 * TAG_GRANULE); 1860 } 1861 } 1862 1863 qemu_init_vcpu(cs); 1864 cpu_reset(cs); 1865 1866 acc->parent_realize(dev, errp); 1867 } 1868 1869 static ObjectClass *arm_cpu_class_by_name(const char *cpu_model) 1870 { 1871 ObjectClass *oc; 1872 char *typename; 1873 char **cpuname; 1874 const char *cpunamestr; 1875 1876 cpuname = g_strsplit(cpu_model, ",", 1); 1877 cpunamestr = cpuname[0]; 1878 #ifdef CONFIG_USER_ONLY 1879 /* For backwards compatibility usermode emulation allows "-cpu any", 1880 * which has the same semantics as "-cpu max". 1881 */ 1882 if (!strcmp(cpunamestr, "any")) { 1883 cpunamestr = "max"; 1884 } 1885 #endif 1886 typename = g_strdup_printf(ARM_CPU_TYPE_NAME("%s"), cpunamestr); 1887 oc = object_class_by_name(typename); 1888 g_strfreev(cpuname); 1889 g_free(typename); 1890 if (!oc || !object_class_dynamic_cast(oc, TYPE_ARM_CPU) || 1891 object_class_is_abstract(oc)) { 1892 return NULL; 1893 } 1894 return oc; 1895 } 1896 1897 /* CPU models. These are not needed for the AArch64 linux-user build. */ 1898 #if !defined(CONFIG_USER_ONLY) || !defined(TARGET_AARCH64) 1899 1900 static const ARMCPRegInfo cortexa8_cp_reginfo[] = { 1901 { .name = "L2LOCKDOWN", .cp = 15, .crn = 9, .crm = 0, .opc1 = 1, .opc2 = 0, 1902 .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0 }, 1903 { .name = "L2AUXCR", .cp = 15, .crn = 9, .crm = 0, .opc1 = 1, .opc2 = 2, 1904 .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0 }, 1905 REGINFO_SENTINEL 1906 }; 1907 1908 static void cortex_a8_initfn(Object *obj) 1909 { 1910 ARMCPU *cpu = ARM_CPU(obj); 1911 1912 cpu->dtb_compatible = "arm,cortex-a8"; 1913 set_feature(&cpu->env, ARM_FEATURE_V7); 1914 set_feature(&cpu->env, ARM_FEATURE_NEON); 1915 set_feature(&cpu->env, ARM_FEATURE_THUMB2EE); 1916 set_feature(&cpu->env, ARM_FEATURE_DUMMY_C15_REGS); 1917 set_feature(&cpu->env, ARM_FEATURE_EL3); 1918 cpu->midr = 0x410fc080; 1919 cpu->reset_fpsid = 0x410330c0; 1920 cpu->isar.mvfr0 = 0x11110222; 1921 cpu->isar.mvfr1 = 0x00011111; 1922 cpu->ctr = 0x82048004; 1923 cpu->reset_sctlr = 0x00c50078; 1924 cpu->isar.id_pfr0 = 0x1031; 1925 cpu->isar.id_pfr1 = 0x11; 1926 cpu->isar.id_dfr0 = 0x400; 1927 cpu->id_afr0 = 0; 1928 cpu->isar.id_mmfr0 = 0x31100003; 1929 cpu->isar.id_mmfr1 = 0x20000000; 1930 cpu->isar.id_mmfr2 = 0x01202000; 1931 cpu->isar.id_mmfr3 = 0x11; 1932 cpu->isar.id_isar0 = 0x00101111; 1933 cpu->isar.id_isar1 = 0x12112111; 1934 cpu->isar.id_isar2 = 0x21232031; 1935 cpu->isar.id_isar3 = 0x11112131; 1936 cpu->isar.id_isar4 = 0x00111142; 1937 cpu->isar.dbgdidr = 0x15141000; 1938 cpu->clidr = (1 << 27) | (2 << 24) | 3; 1939 cpu->ccsidr[0] = 0xe007e01a; /* 16k L1 dcache. */ 1940 cpu->ccsidr[1] = 0x2007e01a; /* 16k L1 icache. */ 1941 cpu->ccsidr[2] = 0xf0000000; /* No L2 icache. */ 1942 cpu->reset_auxcr = 2; 1943 define_arm_cp_regs(cpu, cortexa8_cp_reginfo); 1944 } 1945 1946 static const ARMCPRegInfo cortexa9_cp_reginfo[] = { 1947 /* power_control should be set to maximum latency. Again, 1948 * default to 0 and set by private hook 1949 */ 1950 { .name = "A9_PWRCTL", .cp = 15, .crn = 15, .crm = 0, .opc1 = 0, .opc2 = 0, 1951 .access = PL1_RW, .resetvalue = 0, 1952 .fieldoffset = offsetof(CPUARMState, cp15.c15_power_control) }, 1953 { .name = "A9_DIAG", .cp = 15, .crn = 15, .crm = 0, .opc1 = 0, .opc2 = 1, 1954 .access = PL1_RW, .resetvalue = 0, 1955 .fieldoffset = offsetof(CPUARMState, cp15.c15_diagnostic) }, 1956 { .name = "A9_PWRDIAG", .cp = 15, .crn = 15, .crm = 0, .opc1 = 0, .opc2 = 2, 1957 .access = PL1_RW, .resetvalue = 0, 1958 .fieldoffset = offsetof(CPUARMState, cp15.c15_power_diagnostic) }, 1959 { .name = "NEONBUSY", .cp = 15, .crn = 15, .crm = 1, .opc1 = 0, .opc2 = 0, 1960 .access = PL1_RW, .resetvalue = 0, .type = ARM_CP_CONST }, 1961 /* TLB lockdown control */ 1962 { .name = "TLB_LOCKR", .cp = 15, .crn = 15, .crm = 4, .opc1 = 5, .opc2 = 2, 1963 .access = PL1_W, .resetvalue = 0, .type = ARM_CP_NOP }, 1964 { .name = "TLB_LOCKW", .cp = 15, .crn = 15, .crm = 4, .opc1 = 5, .opc2 = 4, 1965 .access = PL1_W, .resetvalue = 0, .type = ARM_CP_NOP }, 1966 { .name = "TLB_VA", .cp = 15, .crn = 15, .crm = 5, .opc1 = 5, .opc2 = 2, 1967 .access = PL1_RW, .resetvalue = 0, .type = ARM_CP_CONST }, 1968 { .name = "TLB_PA", .cp = 15, .crn = 15, .crm = 6, .opc1 = 5, .opc2 = 2, 1969 .access = PL1_RW, .resetvalue = 0, .type = ARM_CP_CONST }, 1970 { .name = "TLB_ATTR", .cp = 15, .crn = 15, .crm = 7, .opc1 = 5, .opc2 = 2, 1971 .access = PL1_RW, .resetvalue = 0, .type = ARM_CP_CONST }, 1972 REGINFO_SENTINEL 1973 }; 1974 1975 static void cortex_a9_initfn(Object *obj) 1976 { 1977 ARMCPU *cpu = ARM_CPU(obj); 1978 1979 cpu->dtb_compatible = "arm,cortex-a9"; 1980 set_feature(&cpu->env, ARM_FEATURE_V7); 1981 set_feature(&cpu->env, ARM_FEATURE_NEON); 1982 set_feature(&cpu->env, ARM_FEATURE_THUMB2EE); 1983 set_feature(&cpu->env, ARM_FEATURE_EL3); 1984 /* Note that A9 supports the MP extensions even for 1985 * A9UP and single-core A9MP (which are both different 1986 * and valid configurations; we don't model A9UP). 1987 */ 1988 set_feature(&cpu->env, ARM_FEATURE_V7MP); 1989 set_feature(&cpu->env, ARM_FEATURE_CBAR); 1990 cpu->midr = 0x410fc090; 1991 cpu->reset_fpsid = 0x41033090; 1992 cpu->isar.mvfr0 = 0x11110222; 1993 cpu->isar.mvfr1 = 0x01111111; 1994 cpu->ctr = 0x80038003; 1995 cpu->reset_sctlr = 0x00c50078; 1996 cpu->isar.id_pfr0 = 0x1031; 1997 cpu->isar.id_pfr1 = 0x11; 1998 cpu->isar.id_dfr0 = 0x000; 1999 cpu->id_afr0 = 0; 2000 cpu->isar.id_mmfr0 = 0x00100103; 2001 cpu->isar.id_mmfr1 = 0x20000000; 2002 cpu->isar.id_mmfr2 = 0x01230000; 2003 cpu->isar.id_mmfr3 = 0x00002111; 2004 cpu->isar.id_isar0 = 0x00101111; 2005 cpu->isar.id_isar1 = 0x13112111; 2006 cpu->isar.id_isar2 = 0x21232041; 2007 cpu->isar.id_isar3 = 0x11112131; 2008 cpu->isar.id_isar4 = 0x00111142; 2009 cpu->isar.dbgdidr = 0x35141000; 2010 cpu->clidr = (1 << 27) | (1 << 24) | 3; 2011 cpu->ccsidr[0] = 0xe00fe019; /* 16k L1 dcache. */ 2012 cpu->ccsidr[1] = 0x200fe019; /* 16k L1 icache. */ 2013 define_arm_cp_regs(cpu, cortexa9_cp_reginfo); 2014 } 2015 2016 #ifndef CONFIG_USER_ONLY 2017 static uint64_t a15_l2ctlr_read(CPUARMState *env, const ARMCPRegInfo *ri) 2018 { 2019 MachineState *ms = MACHINE(qdev_get_machine()); 2020 2021 /* Linux wants the number of processors from here. 2022 * Might as well set the interrupt-controller bit too. 2023 */ 2024 return ((ms->smp.cpus - 1) << 24) | (1 << 23); 2025 } 2026 #endif 2027 2028 static const ARMCPRegInfo cortexa15_cp_reginfo[] = { 2029 #ifndef CONFIG_USER_ONLY 2030 { .name = "L2CTLR", .cp = 15, .crn = 9, .crm = 0, .opc1 = 1, .opc2 = 2, 2031 .access = PL1_RW, .resetvalue = 0, .readfn = a15_l2ctlr_read, 2032 .writefn = arm_cp_write_ignore, }, 2033 #endif 2034 { .name = "L2ECTLR", .cp = 15, .crn = 9, .crm = 0, .opc1 = 1, .opc2 = 3, 2035 .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0 }, 2036 REGINFO_SENTINEL 2037 }; 2038 2039 static void cortex_a7_initfn(Object *obj) 2040 { 2041 ARMCPU *cpu = ARM_CPU(obj); 2042 2043 cpu->dtb_compatible = "arm,cortex-a7"; 2044 set_feature(&cpu->env, ARM_FEATURE_V7VE); 2045 set_feature(&cpu->env, ARM_FEATURE_NEON); 2046 set_feature(&cpu->env, ARM_FEATURE_THUMB2EE); 2047 set_feature(&cpu->env, ARM_FEATURE_GENERIC_TIMER); 2048 set_feature(&cpu->env, ARM_FEATURE_DUMMY_C15_REGS); 2049 set_feature(&cpu->env, ARM_FEATURE_CBAR_RO); 2050 set_feature(&cpu->env, ARM_FEATURE_EL2); 2051 set_feature(&cpu->env, ARM_FEATURE_EL3); 2052 set_feature(&cpu->env, ARM_FEATURE_PMU); 2053 cpu->kvm_target = QEMU_KVM_ARM_TARGET_CORTEX_A7; 2054 cpu->midr = 0x410fc075; 2055 cpu->reset_fpsid = 0x41023075; 2056 cpu->isar.mvfr0 = 0x10110222; 2057 cpu->isar.mvfr1 = 0x11111111; 2058 cpu->ctr = 0x84448003; 2059 cpu->reset_sctlr = 0x00c50078; 2060 cpu->isar.id_pfr0 = 0x00001131; 2061 cpu->isar.id_pfr1 = 0x00011011; 2062 cpu->isar.id_dfr0 = 0x02010555; 2063 cpu->id_afr0 = 0x00000000; 2064 cpu->isar.id_mmfr0 = 0x10101105; 2065 cpu->isar.id_mmfr1 = 0x40000000; 2066 cpu->isar.id_mmfr2 = 0x01240000; 2067 cpu->isar.id_mmfr3 = 0x02102211; 2068 /* a7_mpcore_r0p5_trm, page 4-4 gives 0x01101110; but 2069 * table 4-41 gives 0x02101110, which includes the arm div insns. 2070 */ 2071 cpu->isar.id_isar0 = 0x02101110; 2072 cpu->isar.id_isar1 = 0x13112111; 2073 cpu->isar.id_isar2 = 0x21232041; 2074 cpu->isar.id_isar3 = 0x11112131; 2075 cpu->isar.id_isar4 = 0x10011142; 2076 cpu->isar.dbgdidr = 0x3515f005; 2077 cpu->clidr = 0x0a200023; 2078 cpu->ccsidr[0] = 0x701fe00a; /* 32K L1 dcache */ 2079 cpu->ccsidr[1] = 0x201fe00a; /* 32K L1 icache */ 2080 cpu->ccsidr[2] = 0x711fe07a; /* 4096K L2 unified cache */ 2081 define_arm_cp_regs(cpu, cortexa15_cp_reginfo); /* Same as A15 */ 2082 } 2083 2084 static void cortex_a15_initfn(Object *obj) 2085 { 2086 ARMCPU *cpu = ARM_CPU(obj); 2087 2088 cpu->dtb_compatible = "arm,cortex-a15"; 2089 set_feature(&cpu->env, ARM_FEATURE_V7VE); 2090 set_feature(&cpu->env, ARM_FEATURE_NEON); 2091 set_feature(&cpu->env, ARM_FEATURE_THUMB2EE); 2092 set_feature(&cpu->env, ARM_FEATURE_GENERIC_TIMER); 2093 set_feature(&cpu->env, ARM_FEATURE_DUMMY_C15_REGS); 2094 set_feature(&cpu->env, ARM_FEATURE_CBAR_RO); 2095 set_feature(&cpu->env, ARM_FEATURE_EL2); 2096 set_feature(&cpu->env, ARM_FEATURE_EL3); 2097 set_feature(&cpu->env, ARM_FEATURE_PMU); 2098 cpu->kvm_target = QEMU_KVM_ARM_TARGET_CORTEX_A15; 2099 cpu->midr = 0x412fc0f1; 2100 cpu->reset_fpsid = 0x410430f0; 2101 cpu->isar.mvfr0 = 0x10110222; 2102 cpu->isar.mvfr1 = 0x11111111; 2103 cpu->ctr = 0x8444c004; 2104 cpu->reset_sctlr = 0x00c50078; 2105 cpu->isar.id_pfr0 = 0x00001131; 2106 cpu->isar.id_pfr1 = 0x00011011; 2107 cpu->isar.id_dfr0 = 0x02010555; 2108 cpu->id_afr0 = 0x00000000; 2109 cpu->isar.id_mmfr0 = 0x10201105; 2110 cpu->isar.id_mmfr1 = 0x20000000; 2111 cpu->isar.id_mmfr2 = 0x01240000; 2112 cpu->isar.id_mmfr3 = 0x02102211; 2113 cpu->isar.id_isar0 = 0x02101110; 2114 cpu->isar.id_isar1 = 0x13112111; 2115 cpu->isar.id_isar2 = 0x21232041; 2116 cpu->isar.id_isar3 = 0x11112131; 2117 cpu->isar.id_isar4 = 0x10011142; 2118 cpu->isar.dbgdidr = 0x3515f021; 2119 cpu->clidr = 0x0a200023; 2120 cpu->ccsidr[0] = 0x701fe00a; /* 32K L1 dcache */ 2121 cpu->ccsidr[1] = 0x201fe00a; /* 32K L1 icache */ 2122 cpu->ccsidr[2] = 0x711fe07a; /* 4096K L2 unified cache */ 2123 define_arm_cp_regs(cpu, cortexa15_cp_reginfo); 2124 } 2125 2126 #ifndef TARGET_AARCH64 2127 /* 2128 * -cpu max: a CPU with as many features enabled as our emulation supports. 2129 * The version of '-cpu max' for qemu-system-aarch64 is defined in cpu64.c; 2130 * this only needs to handle 32 bits, and need not care about KVM. 2131 */ 2132 static void arm_max_initfn(Object *obj) 2133 { 2134 ARMCPU *cpu = ARM_CPU(obj); 2135 2136 cortex_a15_initfn(obj); 2137 2138 /* old-style VFP short-vector support */ 2139 cpu->isar.mvfr0 = FIELD_DP32(cpu->isar.mvfr0, MVFR0, FPSHVEC, 1); 2140 2141 #ifdef CONFIG_USER_ONLY 2142 /* 2143 * We don't set these in system emulation mode for the moment, 2144 * since we don't correctly set (all of) the ID registers to 2145 * advertise them. 2146 */ 2147 set_feature(&cpu->env, ARM_FEATURE_V8); 2148 { 2149 uint32_t t; 2150 2151 t = cpu->isar.id_isar5; 2152 t = FIELD_DP32(t, ID_ISAR5, AES, 2); 2153 t = FIELD_DP32(t, ID_ISAR5, SHA1, 1); 2154 t = FIELD_DP32(t, ID_ISAR5, SHA2, 1); 2155 t = FIELD_DP32(t, ID_ISAR5, CRC32, 1); 2156 t = FIELD_DP32(t, ID_ISAR5, RDM, 1); 2157 t = FIELD_DP32(t, ID_ISAR5, VCMA, 1); 2158 cpu->isar.id_isar5 = t; 2159 2160 t = cpu->isar.id_isar6; 2161 t = FIELD_DP32(t, ID_ISAR6, JSCVT, 1); 2162 t = FIELD_DP32(t, ID_ISAR6, DP, 1); 2163 t = FIELD_DP32(t, ID_ISAR6, FHM, 1); 2164 t = FIELD_DP32(t, ID_ISAR6, SB, 1); 2165 t = FIELD_DP32(t, ID_ISAR6, SPECRES, 1); 2166 cpu->isar.id_isar6 = t; 2167 2168 t = cpu->isar.mvfr1; 2169 t = FIELD_DP32(t, MVFR1, FPHP, 3); /* v8.2-FP16 */ 2170 t = FIELD_DP32(t, MVFR1, SIMDHP, 2); /* v8.2-FP16 */ 2171 cpu->isar.mvfr1 = t; 2172 2173 t = cpu->isar.mvfr2; 2174 t = FIELD_DP32(t, MVFR2, SIMDMISC, 3); /* SIMD MaxNum */ 2175 t = FIELD_DP32(t, MVFR2, FPMISC, 4); /* FP MaxNum */ 2176 cpu->isar.mvfr2 = t; 2177 2178 t = cpu->isar.id_mmfr3; 2179 t = FIELD_DP32(t, ID_MMFR3, PAN, 2); /* ATS1E1 */ 2180 cpu->isar.id_mmfr3 = t; 2181 2182 t = cpu->isar.id_mmfr4; 2183 t = FIELD_DP32(t, ID_MMFR4, HPDS, 1); /* AA32HPD */ 2184 t = FIELD_DP32(t, ID_MMFR4, AC2, 1); /* ACTLR2, HACTLR2 */ 2185 t = FIELD_DP32(t, ID_MMFR4, CNP, 1); /* TTCNP */ 2186 t = FIELD_DP32(t, ID_MMFR4, XNX, 1); /* TTS2UXN */ 2187 cpu->isar.id_mmfr4 = t; 2188 } 2189 #endif 2190 } 2191 #endif 2192 2193 #endif /* !defined(CONFIG_USER_ONLY) || !defined(TARGET_AARCH64) */ 2194 2195 static const ARMCPUInfo arm_cpus[] = { 2196 #if !defined(CONFIG_USER_ONLY) || !defined(TARGET_AARCH64) 2197 { .name = "cortex-a7", .initfn = cortex_a7_initfn }, 2198 { .name = "cortex-a8", .initfn = cortex_a8_initfn }, 2199 { .name = "cortex-a9", .initfn = cortex_a9_initfn }, 2200 { .name = "cortex-a15", .initfn = cortex_a15_initfn }, 2201 #ifndef TARGET_AARCH64 2202 { .name = "max", .initfn = arm_max_initfn }, 2203 #endif 2204 #ifdef CONFIG_USER_ONLY 2205 { .name = "any", .initfn = arm_max_initfn }, 2206 #endif 2207 #endif 2208 }; 2209 2210 static Property arm_cpu_properties[] = { 2211 DEFINE_PROP_UINT32("psci-conduit", ARMCPU, psci_conduit, 0), 2212 DEFINE_PROP_UINT64("midr", ARMCPU, midr, 0), 2213 DEFINE_PROP_UINT64("mp-affinity", ARMCPU, 2214 mp_affinity, ARM64_AFFINITY_INVALID), 2215 DEFINE_PROP_INT32("node-id", ARMCPU, node_id, CPU_UNSET_NUMA_NODE_ID), 2216 DEFINE_PROP_INT32("core-count", ARMCPU, core_count, -1), 2217 DEFINE_PROP_END_OF_LIST() 2218 }; 2219 2220 static gchar *arm_gdb_arch_name(CPUState *cs) 2221 { 2222 ARMCPU *cpu = ARM_CPU(cs); 2223 CPUARMState *env = &cpu->env; 2224 2225 if (arm_feature(env, ARM_FEATURE_IWMMXT)) { 2226 return g_strdup("iwmmxt"); 2227 } 2228 return g_strdup("arm"); 2229 } 2230 2231 static void arm_cpu_class_init(ObjectClass *oc, void *data) 2232 { 2233 ARMCPUClass *acc = ARM_CPU_CLASS(oc); 2234 CPUClass *cc = CPU_CLASS(acc); 2235 DeviceClass *dc = DEVICE_CLASS(oc); 2236 2237 device_class_set_parent_realize(dc, arm_cpu_realizefn, 2238 &acc->parent_realize); 2239 2240 device_class_set_props(dc, arm_cpu_properties); 2241 device_class_set_parent_reset(dc, arm_cpu_reset, &acc->parent_reset); 2242 2243 cc->class_by_name = arm_cpu_class_by_name; 2244 cc->has_work = arm_cpu_has_work; 2245 cc->cpu_exec_interrupt = arm_cpu_exec_interrupt; 2246 cc->dump_state = arm_cpu_dump_state; 2247 cc->set_pc = arm_cpu_set_pc; 2248 cc->synchronize_from_tb = arm_cpu_synchronize_from_tb; 2249 cc->gdb_read_register = arm_cpu_gdb_read_register; 2250 cc->gdb_write_register = arm_cpu_gdb_write_register; 2251 #ifndef CONFIG_USER_ONLY 2252 cc->do_interrupt = arm_cpu_do_interrupt; 2253 cc->get_phys_page_attrs_debug = arm_cpu_get_phys_page_attrs_debug; 2254 cc->asidx_from_attrs = arm_asidx_from_attrs; 2255 cc->vmsd = &vmstate_arm_cpu; 2256 cc->virtio_is_big_endian = arm_cpu_virtio_is_big_endian; 2257 cc->write_elf64_note = arm_cpu_write_elf64_note; 2258 cc->write_elf32_note = arm_cpu_write_elf32_note; 2259 #endif 2260 cc->gdb_num_core_regs = 26; 2261 cc->gdb_core_xml_file = "arm-core.xml"; 2262 cc->gdb_arch_name = arm_gdb_arch_name; 2263 cc->gdb_get_dynamic_xml = arm_gdb_get_dynamic_xml; 2264 cc->gdb_stop_before_watchpoint = true; 2265 cc->disas_set_info = arm_disas_set_info; 2266 #ifdef CONFIG_TCG 2267 cc->tcg_initialize = arm_translate_init; 2268 cc->tlb_fill = arm_cpu_tlb_fill; 2269 cc->debug_excp_handler = arm_debug_excp_handler; 2270 cc->debug_check_watchpoint = arm_debug_check_watchpoint; 2271 cc->do_unaligned_access = arm_cpu_do_unaligned_access; 2272 #if !defined(CONFIG_USER_ONLY) 2273 cc->do_transaction_failed = arm_cpu_do_transaction_failed; 2274 cc->adjust_watchpoint_address = arm_adjust_watchpoint_address; 2275 #endif /* CONFIG_TCG && !CONFIG_USER_ONLY */ 2276 #endif 2277 } 2278 2279 #ifdef CONFIG_KVM 2280 static void arm_host_initfn(Object *obj) 2281 { 2282 ARMCPU *cpu = ARM_CPU(obj); 2283 2284 kvm_arm_set_cpu_features_from_host(cpu); 2285 if (arm_feature(&cpu->env, ARM_FEATURE_AARCH64)) { 2286 aarch64_add_sve_properties(obj); 2287 } 2288 arm_cpu_post_init(obj); 2289 } 2290 2291 static const TypeInfo host_arm_cpu_type_info = { 2292 .name = TYPE_ARM_HOST_CPU, 2293 .parent = TYPE_AARCH64_CPU, 2294 .instance_init = arm_host_initfn, 2295 }; 2296 2297 #endif 2298 2299 static void arm_cpu_instance_init(Object *obj) 2300 { 2301 ARMCPUClass *acc = ARM_CPU_GET_CLASS(obj); 2302 2303 acc->info->initfn(obj); 2304 arm_cpu_post_init(obj); 2305 } 2306 2307 static void cpu_register_class_init(ObjectClass *oc, void *data) 2308 { 2309 ARMCPUClass *acc = ARM_CPU_CLASS(oc); 2310 2311 acc->info = data; 2312 } 2313 2314 void arm_cpu_register(const ARMCPUInfo *info) 2315 { 2316 TypeInfo type_info = { 2317 .parent = TYPE_ARM_CPU, 2318 .instance_size = sizeof(ARMCPU), 2319 .instance_align = __alignof__(ARMCPU), 2320 .instance_init = arm_cpu_instance_init, 2321 .class_size = sizeof(ARMCPUClass), 2322 .class_init = info->class_init ?: cpu_register_class_init, 2323 .class_data = (void *)info, 2324 }; 2325 2326 type_info.name = g_strdup_printf("%s-" TYPE_ARM_CPU, info->name); 2327 type_register(&type_info); 2328 g_free((void *)type_info.name); 2329 } 2330 2331 static const TypeInfo arm_cpu_type_info = { 2332 .name = TYPE_ARM_CPU, 2333 .parent = TYPE_CPU, 2334 .instance_size = sizeof(ARMCPU), 2335 .instance_align = __alignof__(ARMCPU), 2336 .instance_init = arm_cpu_initfn, 2337 .instance_finalize = arm_cpu_finalizefn, 2338 .abstract = true, 2339 .class_size = sizeof(ARMCPUClass), 2340 .class_init = arm_cpu_class_init, 2341 }; 2342 2343 static const TypeInfo idau_interface_type_info = { 2344 .name = TYPE_IDAU_INTERFACE, 2345 .parent = TYPE_INTERFACE, 2346 .class_size = sizeof(IDAUInterfaceClass), 2347 }; 2348 2349 static void arm_cpu_register_types(void) 2350 { 2351 const size_t cpu_count = ARRAY_SIZE(arm_cpus); 2352 2353 type_register_static(&arm_cpu_type_info); 2354 2355 #ifdef CONFIG_KVM 2356 type_register_static(&host_arm_cpu_type_info); 2357 #endif 2358 2359 if (cpu_count) { 2360 size_t i; 2361 2362 type_register_static(&idau_interface_type_info); 2363 for (i = 0; i < cpu_count; ++i) { 2364 arm_cpu_register(&arm_cpus[i]); 2365 } 2366 } 2367 } 2368 2369 type_init(arm_cpu_register_types) 2370