1 /* 2 * QEMU ARM CPU 3 * 4 * Copyright (c) 2012 SUSE LINUX Products GmbH 5 * 6 * This program is free software; you can redistribute it and/or 7 * modify it under the terms of the GNU General Public License 8 * as published by the Free Software Foundation; either version 2 9 * of the License, or (at your option) any later version. 10 * 11 * This program is distributed in the hope that it will be useful, 12 * but WITHOUT ANY WARRANTY; without even the implied warranty of 13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 14 * GNU General Public License for more details. 15 * 16 * You should have received a copy of the GNU General Public License 17 * along with this program; if not, see 18 * <http://www.gnu.org/licenses/gpl-2.0.html> 19 */ 20 21 #include "qemu/osdep.h" 22 #include "qemu/error-report.h" 23 #include "qapi/error.h" 24 #include "cpu.h" 25 #include "internals.h" 26 #include "qemu-common.h" 27 #include "exec/exec-all.h" 28 #include "hw/qdev-properties.h" 29 #if !defined(CONFIG_USER_ONLY) 30 #include "hw/loader.h" 31 #endif 32 #include "hw/arm/arm.h" 33 #include "sysemu/sysemu.h" 34 #include "sysemu/hw_accel.h" 35 #include "kvm_arm.h" 36 37 static void arm_cpu_set_pc(CPUState *cs, vaddr value) 38 { 39 ARMCPU *cpu = ARM_CPU(cs); 40 41 cpu->env.regs[15] = value; 42 } 43 44 static bool arm_cpu_has_work(CPUState *cs) 45 { 46 ARMCPU *cpu = ARM_CPU(cs); 47 48 return (cpu->power_state != PSCI_OFF) 49 && cs->interrupt_request & 50 (CPU_INTERRUPT_FIQ | CPU_INTERRUPT_HARD 51 | CPU_INTERRUPT_VFIQ | CPU_INTERRUPT_VIRQ 52 | CPU_INTERRUPT_EXITTB); 53 } 54 55 void arm_register_el_change_hook(ARMCPU *cpu, ARMELChangeHook *hook, 56 void *opaque) 57 { 58 /* We currently only support registering a single hook function */ 59 assert(!cpu->el_change_hook); 60 cpu->el_change_hook = hook; 61 cpu->el_change_hook_opaque = opaque; 62 } 63 64 static void cp_reg_reset(gpointer key, gpointer value, gpointer opaque) 65 { 66 /* Reset a single ARMCPRegInfo register */ 67 ARMCPRegInfo *ri = value; 68 ARMCPU *cpu = opaque; 69 70 if (ri->type & (ARM_CP_SPECIAL | ARM_CP_ALIAS)) { 71 return; 72 } 73 74 if (ri->resetfn) { 75 ri->resetfn(&cpu->env, ri); 76 return; 77 } 78 79 /* A zero offset is never possible as it would be regs[0] 80 * so we use it to indicate that reset is being handled elsewhere. 81 * This is basically only used for fields in non-core coprocessors 82 * (like the pxa2xx ones). 83 */ 84 if (!ri->fieldoffset) { 85 return; 86 } 87 88 if (cpreg_field_is_64bit(ri)) { 89 CPREG_FIELD64(&cpu->env, ri) = ri->resetvalue; 90 } else { 91 CPREG_FIELD32(&cpu->env, ri) = ri->resetvalue; 92 } 93 } 94 95 static void cp_reg_check_reset(gpointer key, gpointer value, gpointer opaque) 96 { 97 /* Purely an assertion check: we've already done reset once, 98 * so now check that running the reset for the cpreg doesn't 99 * change its value. This traps bugs where two different cpregs 100 * both try to reset the same state field but to different values. 101 */ 102 ARMCPRegInfo *ri = value; 103 ARMCPU *cpu = opaque; 104 uint64_t oldvalue, newvalue; 105 106 if (ri->type & (ARM_CP_SPECIAL | ARM_CP_ALIAS | ARM_CP_NO_RAW)) { 107 return; 108 } 109 110 oldvalue = read_raw_cp_reg(&cpu->env, ri); 111 cp_reg_reset(key, value, opaque); 112 newvalue = read_raw_cp_reg(&cpu->env, ri); 113 assert(oldvalue == newvalue); 114 } 115 116 /* CPUClass::reset() */ 117 static void arm_cpu_reset(CPUState *s) 118 { 119 ARMCPU *cpu = ARM_CPU(s); 120 ARMCPUClass *acc = ARM_CPU_GET_CLASS(cpu); 121 CPUARMState *env = &cpu->env; 122 123 acc->parent_reset(s); 124 125 memset(env, 0, offsetof(CPUARMState, end_reset_fields)); 126 127 g_hash_table_foreach(cpu->cp_regs, cp_reg_reset, cpu); 128 g_hash_table_foreach(cpu->cp_regs, cp_reg_check_reset, cpu); 129 130 env->vfp.xregs[ARM_VFP_FPSID] = cpu->reset_fpsid; 131 env->vfp.xregs[ARM_VFP_MVFR0] = cpu->mvfr0; 132 env->vfp.xregs[ARM_VFP_MVFR1] = cpu->mvfr1; 133 env->vfp.xregs[ARM_VFP_MVFR2] = cpu->mvfr2; 134 135 cpu->power_state = cpu->start_powered_off ? PSCI_OFF : PSCI_ON; 136 s->halted = cpu->start_powered_off; 137 138 if (arm_feature(env, ARM_FEATURE_IWMMXT)) { 139 env->iwmmxt.cregs[ARM_IWMMXT_wCID] = 0x69051000 | 'Q'; 140 } 141 142 if (arm_feature(env, ARM_FEATURE_AARCH64)) { 143 /* 64 bit CPUs always start in 64 bit mode */ 144 env->aarch64 = 1; 145 #if defined(CONFIG_USER_ONLY) 146 env->pstate = PSTATE_MODE_EL0t; 147 /* Userspace expects access to DC ZVA, CTL_EL0 and the cache ops */ 148 env->cp15.sctlr_el[1] |= SCTLR_UCT | SCTLR_UCI | SCTLR_DZE; 149 /* and to the FP/Neon instructions */ 150 env->cp15.cpacr_el1 = deposit64(env->cp15.cpacr_el1, 20, 2, 3); 151 #else 152 /* Reset into the highest available EL */ 153 if (arm_feature(env, ARM_FEATURE_EL3)) { 154 env->pstate = PSTATE_MODE_EL3h; 155 } else if (arm_feature(env, ARM_FEATURE_EL2)) { 156 env->pstate = PSTATE_MODE_EL2h; 157 } else { 158 env->pstate = PSTATE_MODE_EL1h; 159 } 160 env->pc = cpu->rvbar; 161 #endif 162 } else { 163 #if defined(CONFIG_USER_ONLY) 164 /* Userspace expects access to cp10 and cp11 for FP/Neon */ 165 env->cp15.cpacr_el1 = deposit64(env->cp15.cpacr_el1, 20, 4, 0xf); 166 #endif 167 } 168 169 #if defined(CONFIG_USER_ONLY) 170 env->uncached_cpsr = ARM_CPU_MODE_USR; 171 /* For user mode we must enable access to coprocessors */ 172 env->vfp.xregs[ARM_VFP_FPEXC] = 1 << 30; 173 if (arm_feature(env, ARM_FEATURE_IWMMXT)) { 174 env->cp15.c15_cpar = 3; 175 } else if (arm_feature(env, ARM_FEATURE_XSCALE)) { 176 env->cp15.c15_cpar = 1; 177 } 178 #else 179 /* SVC mode with interrupts disabled. */ 180 env->uncached_cpsr = ARM_CPU_MODE_SVC; 181 env->daif = PSTATE_D | PSTATE_A | PSTATE_I | PSTATE_F; 182 183 if (arm_feature(env, ARM_FEATURE_M)) { 184 uint32_t initial_msp; /* Loaded from 0x0 */ 185 uint32_t initial_pc; /* Loaded from 0x4 */ 186 uint8_t *rom; 187 188 if (arm_feature(env, ARM_FEATURE_M_SECURITY)) { 189 env->v7m.secure = true; 190 } else { 191 /* This bit resets to 0 if security is supported, but 1 if 192 * it is not. The bit is not present in v7M, but we set it 193 * here so we can avoid having to make checks on it conditional 194 * on ARM_FEATURE_V8 (we don't let the guest see the bit). 195 */ 196 env->v7m.aircr = R_V7M_AIRCR_BFHFNMINS_MASK; 197 } 198 199 /* In v7M the reset value of this bit is IMPDEF, but ARM recommends 200 * that it resets to 1, so QEMU always does that rather than making 201 * it dependent on CPU model. In v8M it is RES1. 202 */ 203 env->v7m.ccr[M_REG_NS] = R_V7M_CCR_STKALIGN_MASK; 204 env->v7m.ccr[M_REG_S] = R_V7M_CCR_STKALIGN_MASK; 205 if (arm_feature(env, ARM_FEATURE_V8)) { 206 /* in v8M the NONBASETHRDENA bit [0] is RES1 */ 207 env->v7m.ccr[M_REG_NS] |= R_V7M_CCR_NONBASETHRDENA_MASK; 208 env->v7m.ccr[M_REG_S] |= R_V7M_CCR_NONBASETHRDENA_MASK; 209 } 210 211 /* Unlike A/R profile, M profile defines the reset LR value */ 212 env->regs[14] = 0xffffffff; 213 214 /* Load the initial SP and PC from the vector table at address 0 */ 215 rom = rom_ptr(0); 216 if (rom) { 217 /* Address zero is covered by ROM which hasn't yet been 218 * copied into physical memory. 219 */ 220 initial_msp = ldl_p(rom); 221 initial_pc = ldl_p(rom + 4); 222 } else { 223 /* Address zero not covered by a ROM blob, or the ROM blob 224 * is in non-modifiable memory and this is a second reset after 225 * it got copied into memory. In the latter case, rom_ptr 226 * will return a NULL pointer and we should use ldl_phys instead. 227 */ 228 initial_msp = ldl_phys(s->as, 0); 229 initial_pc = ldl_phys(s->as, 4); 230 } 231 232 env->regs[13] = initial_msp & 0xFFFFFFFC; 233 env->regs[15] = initial_pc & ~1; 234 env->thumb = initial_pc & 1; 235 } 236 237 /* AArch32 has a hard highvec setting of 0xFFFF0000. If we are currently 238 * executing as AArch32 then check if highvecs are enabled and 239 * adjust the PC accordingly. 240 */ 241 if (A32_BANKED_CURRENT_REG_GET(env, sctlr) & SCTLR_V) { 242 env->regs[15] = 0xFFFF0000; 243 } 244 245 /* M profile requires that reset clears the exclusive monitor; 246 * A profile does not, but clearing it makes more sense than having it 247 * set with an exclusive access on address zero. 248 */ 249 arm_clear_exclusive(env); 250 251 env->vfp.xregs[ARM_VFP_FPEXC] = 0; 252 #endif 253 254 if (arm_feature(env, ARM_FEATURE_PMSA)) { 255 if (cpu->pmsav7_dregion > 0) { 256 if (arm_feature(env, ARM_FEATURE_V8)) { 257 memset(env->pmsav8.rbar[M_REG_NS], 0, 258 sizeof(*env->pmsav8.rbar[M_REG_NS]) 259 * cpu->pmsav7_dregion); 260 memset(env->pmsav8.rlar[M_REG_NS], 0, 261 sizeof(*env->pmsav8.rlar[M_REG_NS]) 262 * cpu->pmsav7_dregion); 263 if (arm_feature(env, ARM_FEATURE_M_SECURITY)) { 264 memset(env->pmsav8.rbar[M_REG_S], 0, 265 sizeof(*env->pmsav8.rbar[M_REG_S]) 266 * cpu->pmsav7_dregion); 267 memset(env->pmsav8.rlar[M_REG_S], 0, 268 sizeof(*env->pmsav8.rlar[M_REG_S]) 269 * cpu->pmsav7_dregion); 270 } 271 } else if (arm_feature(env, ARM_FEATURE_V7)) { 272 memset(env->pmsav7.drbar, 0, 273 sizeof(*env->pmsav7.drbar) * cpu->pmsav7_dregion); 274 memset(env->pmsav7.drsr, 0, 275 sizeof(*env->pmsav7.drsr) * cpu->pmsav7_dregion); 276 memset(env->pmsav7.dracr, 0, 277 sizeof(*env->pmsav7.dracr) * cpu->pmsav7_dregion); 278 } 279 } 280 env->pmsav7.rnr[M_REG_NS] = 0; 281 env->pmsav7.rnr[M_REG_S] = 0; 282 env->pmsav8.mair0[M_REG_NS] = 0; 283 env->pmsav8.mair0[M_REG_S] = 0; 284 env->pmsav8.mair1[M_REG_NS] = 0; 285 env->pmsav8.mair1[M_REG_S] = 0; 286 } 287 288 if (arm_feature(env, ARM_FEATURE_M_SECURITY)) { 289 if (cpu->sau_sregion > 0) { 290 memset(env->sau.rbar, 0, sizeof(*env->sau.rbar) * cpu->sau_sregion); 291 memset(env->sau.rlar, 0, sizeof(*env->sau.rlar) * cpu->sau_sregion); 292 } 293 env->sau.rnr = 0; 294 /* SAU_CTRL reset value is IMPDEF; we choose 0, which is what 295 * the Cortex-M33 does. 296 */ 297 env->sau.ctrl = 0; 298 } 299 300 set_flush_to_zero(1, &env->vfp.standard_fp_status); 301 set_flush_inputs_to_zero(1, &env->vfp.standard_fp_status); 302 set_default_nan_mode(1, &env->vfp.standard_fp_status); 303 set_float_detect_tininess(float_tininess_before_rounding, 304 &env->vfp.fp_status); 305 set_float_detect_tininess(float_tininess_before_rounding, 306 &env->vfp.standard_fp_status); 307 #ifndef CONFIG_USER_ONLY 308 if (kvm_enabled()) { 309 kvm_arm_reset_vcpu(cpu); 310 } 311 #endif 312 313 hw_breakpoint_update_all(cpu); 314 hw_watchpoint_update_all(cpu); 315 } 316 317 bool arm_cpu_exec_interrupt(CPUState *cs, int interrupt_request) 318 { 319 CPUClass *cc = CPU_GET_CLASS(cs); 320 CPUARMState *env = cs->env_ptr; 321 uint32_t cur_el = arm_current_el(env); 322 bool secure = arm_is_secure(env); 323 uint32_t target_el; 324 uint32_t excp_idx; 325 bool ret = false; 326 327 if (interrupt_request & CPU_INTERRUPT_FIQ) { 328 excp_idx = EXCP_FIQ; 329 target_el = arm_phys_excp_target_el(cs, excp_idx, cur_el, secure); 330 if (arm_excp_unmasked(cs, excp_idx, target_el)) { 331 cs->exception_index = excp_idx; 332 env->exception.target_el = target_el; 333 cc->do_interrupt(cs); 334 ret = true; 335 } 336 } 337 if (interrupt_request & CPU_INTERRUPT_HARD) { 338 excp_idx = EXCP_IRQ; 339 target_el = arm_phys_excp_target_el(cs, excp_idx, cur_el, secure); 340 if (arm_excp_unmasked(cs, excp_idx, target_el)) { 341 cs->exception_index = excp_idx; 342 env->exception.target_el = target_el; 343 cc->do_interrupt(cs); 344 ret = true; 345 } 346 } 347 if (interrupt_request & CPU_INTERRUPT_VIRQ) { 348 excp_idx = EXCP_VIRQ; 349 target_el = 1; 350 if (arm_excp_unmasked(cs, excp_idx, target_el)) { 351 cs->exception_index = excp_idx; 352 env->exception.target_el = target_el; 353 cc->do_interrupt(cs); 354 ret = true; 355 } 356 } 357 if (interrupt_request & CPU_INTERRUPT_VFIQ) { 358 excp_idx = EXCP_VFIQ; 359 target_el = 1; 360 if (arm_excp_unmasked(cs, excp_idx, target_el)) { 361 cs->exception_index = excp_idx; 362 env->exception.target_el = target_el; 363 cc->do_interrupt(cs); 364 ret = true; 365 } 366 } 367 368 return ret; 369 } 370 371 #if !defined(CONFIG_USER_ONLY) || !defined(TARGET_AARCH64) 372 static bool arm_v7m_cpu_exec_interrupt(CPUState *cs, int interrupt_request) 373 { 374 CPUClass *cc = CPU_GET_CLASS(cs); 375 ARMCPU *cpu = ARM_CPU(cs); 376 CPUARMState *env = &cpu->env; 377 bool ret = false; 378 379 /* ARMv7-M interrupt masking works differently than -A or -R. 380 * There is no FIQ/IRQ distinction. Instead of I and F bits 381 * masking FIQ and IRQ interrupts, an exception is taken only 382 * if it is higher priority than the current execution priority 383 * (which depends on state like BASEPRI, FAULTMASK and the 384 * currently active exception). 385 */ 386 if (interrupt_request & CPU_INTERRUPT_HARD 387 && (armv7m_nvic_can_take_pending_exception(env->nvic))) { 388 cs->exception_index = EXCP_IRQ; 389 cc->do_interrupt(cs); 390 ret = true; 391 } 392 return ret; 393 } 394 #endif 395 396 #ifndef CONFIG_USER_ONLY 397 static void arm_cpu_set_irq(void *opaque, int irq, int level) 398 { 399 ARMCPU *cpu = opaque; 400 CPUARMState *env = &cpu->env; 401 CPUState *cs = CPU(cpu); 402 static const int mask[] = { 403 [ARM_CPU_IRQ] = CPU_INTERRUPT_HARD, 404 [ARM_CPU_FIQ] = CPU_INTERRUPT_FIQ, 405 [ARM_CPU_VIRQ] = CPU_INTERRUPT_VIRQ, 406 [ARM_CPU_VFIQ] = CPU_INTERRUPT_VFIQ 407 }; 408 409 switch (irq) { 410 case ARM_CPU_VIRQ: 411 case ARM_CPU_VFIQ: 412 assert(arm_feature(env, ARM_FEATURE_EL2)); 413 /* fall through */ 414 case ARM_CPU_IRQ: 415 case ARM_CPU_FIQ: 416 if (level) { 417 cpu_interrupt(cs, mask[irq]); 418 } else { 419 cpu_reset_interrupt(cs, mask[irq]); 420 } 421 break; 422 default: 423 g_assert_not_reached(); 424 } 425 } 426 427 static void arm_cpu_kvm_set_irq(void *opaque, int irq, int level) 428 { 429 #ifdef CONFIG_KVM 430 ARMCPU *cpu = opaque; 431 CPUState *cs = CPU(cpu); 432 int kvm_irq = KVM_ARM_IRQ_TYPE_CPU << KVM_ARM_IRQ_TYPE_SHIFT; 433 434 switch (irq) { 435 case ARM_CPU_IRQ: 436 kvm_irq |= KVM_ARM_IRQ_CPU_IRQ; 437 break; 438 case ARM_CPU_FIQ: 439 kvm_irq |= KVM_ARM_IRQ_CPU_FIQ; 440 break; 441 default: 442 g_assert_not_reached(); 443 } 444 kvm_irq |= cs->cpu_index << KVM_ARM_IRQ_VCPU_SHIFT; 445 kvm_set_irq(kvm_state, kvm_irq, level ? 1 : 0); 446 #endif 447 } 448 449 static bool arm_cpu_virtio_is_big_endian(CPUState *cs) 450 { 451 ARMCPU *cpu = ARM_CPU(cs); 452 CPUARMState *env = &cpu->env; 453 454 cpu_synchronize_state(cs); 455 return arm_cpu_data_is_big_endian(env); 456 } 457 458 #endif 459 460 static inline void set_feature(CPUARMState *env, int feature) 461 { 462 env->features |= 1ULL << feature; 463 } 464 465 static inline void unset_feature(CPUARMState *env, int feature) 466 { 467 env->features &= ~(1ULL << feature); 468 } 469 470 static int 471 print_insn_thumb1(bfd_vma pc, disassemble_info *info) 472 { 473 return print_insn_arm(pc | 1, info); 474 } 475 476 static int arm_read_memory_func(bfd_vma memaddr, bfd_byte *b, 477 int length, struct disassemble_info *info) 478 { 479 assert(info->read_memory_inner_func); 480 assert((info->flags & INSN_ARM_BE32) == 0 || length == 2 || length == 4); 481 482 if ((info->flags & INSN_ARM_BE32) != 0 && length == 2) { 483 assert(info->endian == BFD_ENDIAN_LITTLE); 484 return info->read_memory_inner_func(memaddr ^ 2, (bfd_byte *)b, 2, 485 info); 486 } else { 487 return info->read_memory_inner_func(memaddr, b, length, info); 488 } 489 } 490 491 static void arm_disas_set_info(CPUState *cpu, disassemble_info *info) 492 { 493 ARMCPU *ac = ARM_CPU(cpu); 494 CPUARMState *env = &ac->env; 495 496 if (is_a64(env)) { 497 /* We might not be compiled with the A64 disassembler 498 * because it needs a C++ compiler. Leave print_insn 499 * unset in this case to use the caller default behaviour. 500 */ 501 #if defined(CONFIG_ARM_A64_DIS) 502 info->print_insn = print_insn_arm_a64; 503 #endif 504 } else if (env->thumb) { 505 info->print_insn = print_insn_thumb1; 506 } else { 507 info->print_insn = print_insn_arm; 508 } 509 if (bswap_code(arm_sctlr_b(env))) { 510 #ifdef TARGET_WORDS_BIGENDIAN 511 info->endian = BFD_ENDIAN_LITTLE; 512 #else 513 info->endian = BFD_ENDIAN_BIG; 514 #endif 515 } 516 if (info->read_memory_inner_func == NULL) { 517 info->read_memory_inner_func = info->read_memory_func; 518 info->read_memory_func = arm_read_memory_func; 519 } 520 info->flags &= ~INSN_ARM_BE32; 521 if (arm_sctlr_b(env)) { 522 info->flags |= INSN_ARM_BE32; 523 } 524 } 525 526 uint64_t arm_cpu_mp_affinity(int idx, uint8_t clustersz) 527 { 528 uint32_t Aff1 = idx / clustersz; 529 uint32_t Aff0 = idx % clustersz; 530 return (Aff1 << ARM_AFF1_SHIFT) | Aff0; 531 } 532 533 static void arm_cpu_initfn(Object *obj) 534 { 535 CPUState *cs = CPU(obj); 536 ARMCPU *cpu = ARM_CPU(obj); 537 static bool inited; 538 539 cs->env_ptr = &cpu->env; 540 cpu->cp_regs = g_hash_table_new_full(g_int_hash, g_int_equal, 541 g_free, g_free); 542 543 #ifndef CONFIG_USER_ONLY 544 /* Our inbound IRQ and FIQ lines */ 545 if (kvm_enabled()) { 546 /* VIRQ and VFIQ are unused with KVM but we add them to maintain 547 * the same interface as non-KVM CPUs. 548 */ 549 qdev_init_gpio_in(DEVICE(cpu), arm_cpu_kvm_set_irq, 4); 550 } else { 551 qdev_init_gpio_in(DEVICE(cpu), arm_cpu_set_irq, 4); 552 } 553 554 cpu->gt_timer[GTIMER_PHYS] = timer_new(QEMU_CLOCK_VIRTUAL, GTIMER_SCALE, 555 arm_gt_ptimer_cb, cpu); 556 cpu->gt_timer[GTIMER_VIRT] = timer_new(QEMU_CLOCK_VIRTUAL, GTIMER_SCALE, 557 arm_gt_vtimer_cb, cpu); 558 cpu->gt_timer[GTIMER_HYP] = timer_new(QEMU_CLOCK_VIRTUAL, GTIMER_SCALE, 559 arm_gt_htimer_cb, cpu); 560 cpu->gt_timer[GTIMER_SEC] = timer_new(QEMU_CLOCK_VIRTUAL, GTIMER_SCALE, 561 arm_gt_stimer_cb, cpu); 562 qdev_init_gpio_out(DEVICE(cpu), cpu->gt_timer_outputs, 563 ARRAY_SIZE(cpu->gt_timer_outputs)); 564 565 qdev_init_gpio_out_named(DEVICE(cpu), &cpu->gicv3_maintenance_interrupt, 566 "gicv3-maintenance-interrupt", 1); 567 qdev_init_gpio_out_named(DEVICE(cpu), &cpu->pmu_interrupt, 568 "pmu-interrupt", 1); 569 #endif 570 571 /* DTB consumers generally don't in fact care what the 'compatible' 572 * string is, so always provide some string and trust that a hypothetical 573 * picky DTB consumer will also provide a helpful error message. 574 */ 575 cpu->dtb_compatible = "qemu,unknown"; 576 cpu->psci_version = 1; /* By default assume PSCI v0.1 */ 577 cpu->kvm_target = QEMU_KVM_ARM_TARGET_NONE; 578 579 if (tcg_enabled()) { 580 cpu->psci_version = 2; /* TCG implements PSCI 0.2 */ 581 if (!inited) { 582 inited = true; 583 arm_translate_init(); 584 } 585 } 586 } 587 588 static Property arm_cpu_reset_cbar_property = 589 DEFINE_PROP_UINT64("reset-cbar", ARMCPU, reset_cbar, 0); 590 591 static Property arm_cpu_reset_hivecs_property = 592 DEFINE_PROP_BOOL("reset-hivecs", ARMCPU, reset_hivecs, false); 593 594 static Property arm_cpu_rvbar_property = 595 DEFINE_PROP_UINT64("rvbar", ARMCPU, rvbar, 0); 596 597 static Property arm_cpu_has_el2_property = 598 DEFINE_PROP_BOOL("has_el2", ARMCPU, has_el2, true); 599 600 static Property arm_cpu_has_el3_property = 601 DEFINE_PROP_BOOL("has_el3", ARMCPU, has_el3, true); 602 603 static Property arm_cpu_cfgend_property = 604 DEFINE_PROP_BOOL("cfgend", ARMCPU, cfgend, false); 605 606 /* use property name "pmu" to match other archs and virt tools */ 607 static Property arm_cpu_has_pmu_property = 608 DEFINE_PROP_BOOL("pmu", ARMCPU, has_pmu, true); 609 610 static Property arm_cpu_has_mpu_property = 611 DEFINE_PROP_BOOL("has-mpu", ARMCPU, has_mpu, true); 612 613 /* This is like DEFINE_PROP_UINT32 but it doesn't set the default value, 614 * because the CPU initfn will have already set cpu->pmsav7_dregion to 615 * the right value for that particular CPU type, and we don't want 616 * to override that with an incorrect constant value. 617 */ 618 static Property arm_cpu_pmsav7_dregion_property = 619 DEFINE_PROP_UNSIGNED_NODEFAULT("pmsav7-dregion", ARMCPU, 620 pmsav7_dregion, 621 qdev_prop_uint32, uint32_t); 622 623 static void arm_cpu_post_init(Object *obj) 624 { 625 ARMCPU *cpu = ARM_CPU(obj); 626 627 /* M profile implies PMSA. We have to do this here rather than 628 * in realize with the other feature-implication checks because 629 * we look at the PMSA bit to see if we should add some properties. 630 */ 631 if (arm_feature(&cpu->env, ARM_FEATURE_M)) { 632 set_feature(&cpu->env, ARM_FEATURE_PMSA); 633 } 634 635 if (arm_feature(&cpu->env, ARM_FEATURE_CBAR) || 636 arm_feature(&cpu->env, ARM_FEATURE_CBAR_RO)) { 637 qdev_property_add_static(DEVICE(obj), &arm_cpu_reset_cbar_property, 638 &error_abort); 639 } 640 641 if (!arm_feature(&cpu->env, ARM_FEATURE_M)) { 642 qdev_property_add_static(DEVICE(obj), &arm_cpu_reset_hivecs_property, 643 &error_abort); 644 } 645 646 if (arm_feature(&cpu->env, ARM_FEATURE_AARCH64)) { 647 qdev_property_add_static(DEVICE(obj), &arm_cpu_rvbar_property, 648 &error_abort); 649 } 650 651 if (arm_feature(&cpu->env, ARM_FEATURE_EL3)) { 652 /* Add the has_el3 state CPU property only if EL3 is allowed. This will 653 * prevent "has_el3" from existing on CPUs which cannot support EL3. 654 */ 655 qdev_property_add_static(DEVICE(obj), &arm_cpu_has_el3_property, 656 &error_abort); 657 658 #ifndef CONFIG_USER_ONLY 659 object_property_add_link(obj, "secure-memory", 660 TYPE_MEMORY_REGION, 661 (Object **)&cpu->secure_memory, 662 qdev_prop_allow_set_link_before_realize, 663 OBJ_PROP_LINK_UNREF_ON_RELEASE, 664 &error_abort); 665 #endif 666 } 667 668 if (arm_feature(&cpu->env, ARM_FEATURE_EL2)) { 669 qdev_property_add_static(DEVICE(obj), &arm_cpu_has_el2_property, 670 &error_abort); 671 } 672 673 if (arm_feature(&cpu->env, ARM_FEATURE_PMU)) { 674 qdev_property_add_static(DEVICE(obj), &arm_cpu_has_pmu_property, 675 &error_abort); 676 } 677 678 if (arm_feature(&cpu->env, ARM_FEATURE_PMSA)) { 679 qdev_property_add_static(DEVICE(obj), &arm_cpu_has_mpu_property, 680 &error_abort); 681 if (arm_feature(&cpu->env, ARM_FEATURE_V7)) { 682 qdev_property_add_static(DEVICE(obj), 683 &arm_cpu_pmsav7_dregion_property, 684 &error_abort); 685 } 686 } 687 688 qdev_property_add_static(DEVICE(obj), &arm_cpu_cfgend_property, 689 &error_abort); 690 } 691 692 static void arm_cpu_finalizefn(Object *obj) 693 { 694 ARMCPU *cpu = ARM_CPU(obj); 695 g_hash_table_destroy(cpu->cp_regs); 696 } 697 698 static void arm_cpu_realizefn(DeviceState *dev, Error **errp) 699 { 700 CPUState *cs = CPU(dev); 701 ARMCPU *cpu = ARM_CPU(dev); 702 ARMCPUClass *acc = ARM_CPU_GET_CLASS(dev); 703 CPUARMState *env = &cpu->env; 704 int pagebits; 705 Error *local_err = NULL; 706 #ifndef CONFIG_USER_ONLY 707 AddressSpace *as; 708 #endif 709 710 cpu_exec_realizefn(cs, &local_err); 711 if (local_err != NULL) { 712 error_propagate(errp, local_err); 713 return; 714 } 715 716 /* Some features automatically imply others: */ 717 if (arm_feature(env, ARM_FEATURE_V8)) { 718 set_feature(env, ARM_FEATURE_V7); 719 set_feature(env, ARM_FEATURE_ARM_DIV); 720 set_feature(env, ARM_FEATURE_LPAE); 721 } 722 if (arm_feature(env, ARM_FEATURE_V7)) { 723 set_feature(env, ARM_FEATURE_VAPA); 724 set_feature(env, ARM_FEATURE_THUMB2); 725 set_feature(env, ARM_FEATURE_MPIDR); 726 if (!arm_feature(env, ARM_FEATURE_M)) { 727 set_feature(env, ARM_FEATURE_V6K); 728 } else { 729 set_feature(env, ARM_FEATURE_V6); 730 } 731 732 /* Always define VBAR for V7 CPUs even if it doesn't exist in 733 * non-EL3 configs. This is needed by some legacy boards. 734 */ 735 set_feature(env, ARM_FEATURE_VBAR); 736 } 737 if (arm_feature(env, ARM_FEATURE_V6K)) { 738 set_feature(env, ARM_FEATURE_V6); 739 set_feature(env, ARM_FEATURE_MVFR); 740 } 741 if (arm_feature(env, ARM_FEATURE_V6)) { 742 set_feature(env, ARM_FEATURE_V5); 743 set_feature(env, ARM_FEATURE_JAZELLE); 744 if (!arm_feature(env, ARM_FEATURE_M)) { 745 set_feature(env, ARM_FEATURE_AUXCR); 746 } 747 } 748 if (arm_feature(env, ARM_FEATURE_V5)) { 749 set_feature(env, ARM_FEATURE_V4T); 750 } 751 if (arm_feature(env, ARM_FEATURE_M)) { 752 set_feature(env, ARM_FEATURE_THUMB_DIV); 753 } 754 if (arm_feature(env, ARM_FEATURE_ARM_DIV)) { 755 set_feature(env, ARM_FEATURE_THUMB_DIV); 756 } 757 if (arm_feature(env, ARM_FEATURE_VFP4)) { 758 set_feature(env, ARM_FEATURE_VFP3); 759 set_feature(env, ARM_FEATURE_VFP_FP16); 760 } 761 if (arm_feature(env, ARM_FEATURE_VFP3)) { 762 set_feature(env, ARM_FEATURE_VFP); 763 } 764 if (arm_feature(env, ARM_FEATURE_LPAE)) { 765 set_feature(env, ARM_FEATURE_V7MP); 766 set_feature(env, ARM_FEATURE_PXN); 767 } 768 if (arm_feature(env, ARM_FEATURE_CBAR_RO)) { 769 set_feature(env, ARM_FEATURE_CBAR); 770 } 771 if (arm_feature(env, ARM_FEATURE_THUMB2) && 772 !arm_feature(env, ARM_FEATURE_M)) { 773 set_feature(env, ARM_FEATURE_THUMB_DSP); 774 } 775 776 if (arm_feature(env, ARM_FEATURE_V7) && 777 !arm_feature(env, ARM_FEATURE_M) && 778 !arm_feature(env, ARM_FEATURE_PMSA)) { 779 /* v7VMSA drops support for the old ARMv5 tiny pages, so we 780 * can use 4K pages. 781 */ 782 pagebits = 12; 783 } else { 784 /* For CPUs which might have tiny 1K pages, or which have an 785 * MPU and might have small region sizes, stick with 1K pages. 786 */ 787 pagebits = 10; 788 } 789 if (!set_preferred_target_page_bits(pagebits)) { 790 /* This can only ever happen for hotplugging a CPU, or if 791 * the board code incorrectly creates a CPU which it has 792 * promised via minimum_page_size that it will not. 793 */ 794 error_setg(errp, "This CPU requires a smaller page size than the " 795 "system is using"); 796 return; 797 } 798 799 /* This cpu-id-to-MPIDR affinity is used only for TCG; KVM will override it. 800 * We don't support setting cluster ID ([16..23]) (known as Aff2 801 * in later ARM ARM versions), or any of the higher affinity level fields, 802 * so these bits always RAZ. 803 */ 804 if (cpu->mp_affinity == ARM64_AFFINITY_INVALID) { 805 cpu->mp_affinity = arm_cpu_mp_affinity(cs->cpu_index, 806 ARM_DEFAULT_CPUS_PER_CLUSTER); 807 } 808 809 if (cpu->reset_hivecs) { 810 cpu->reset_sctlr |= (1 << 13); 811 } 812 813 if (cpu->cfgend) { 814 if (arm_feature(&cpu->env, ARM_FEATURE_V7)) { 815 cpu->reset_sctlr |= SCTLR_EE; 816 } else { 817 cpu->reset_sctlr |= SCTLR_B; 818 } 819 } 820 821 if (!cpu->has_el3) { 822 /* If the has_el3 CPU property is disabled then we need to disable the 823 * feature. 824 */ 825 unset_feature(env, ARM_FEATURE_EL3); 826 827 /* Disable the security extension feature bits in the processor feature 828 * registers as well. These are id_pfr1[7:4] and id_aa64pfr0[15:12]. 829 */ 830 cpu->id_pfr1 &= ~0xf0; 831 cpu->id_aa64pfr0 &= ~0xf000; 832 } 833 834 if (!cpu->has_el2) { 835 unset_feature(env, ARM_FEATURE_EL2); 836 } 837 838 if (!cpu->has_pmu) { 839 unset_feature(env, ARM_FEATURE_PMU); 840 cpu->id_aa64dfr0 &= ~0xf00; 841 } 842 843 if (!arm_feature(env, ARM_FEATURE_EL2)) { 844 /* Disable the hypervisor feature bits in the processor feature 845 * registers if we don't have EL2. These are id_pfr1[15:12] and 846 * id_aa64pfr0_el1[11:8]. 847 */ 848 cpu->id_aa64pfr0 &= ~0xf00; 849 cpu->id_pfr1 &= ~0xf000; 850 } 851 852 /* MPU can be configured out of a PMSA CPU either by setting has-mpu 853 * to false or by setting pmsav7-dregion to 0. 854 */ 855 if (!cpu->has_mpu) { 856 cpu->pmsav7_dregion = 0; 857 } 858 if (cpu->pmsav7_dregion == 0) { 859 cpu->has_mpu = false; 860 } 861 862 if (arm_feature(env, ARM_FEATURE_PMSA) && 863 arm_feature(env, ARM_FEATURE_V7)) { 864 uint32_t nr = cpu->pmsav7_dregion; 865 866 if (nr > 0xff) { 867 error_setg(errp, "PMSAv7 MPU #regions invalid %" PRIu32, nr); 868 return; 869 } 870 871 if (nr) { 872 if (arm_feature(env, ARM_FEATURE_V8)) { 873 /* PMSAv8 */ 874 env->pmsav8.rbar[M_REG_NS] = g_new0(uint32_t, nr); 875 env->pmsav8.rlar[M_REG_NS] = g_new0(uint32_t, nr); 876 if (arm_feature(env, ARM_FEATURE_M_SECURITY)) { 877 env->pmsav8.rbar[M_REG_S] = g_new0(uint32_t, nr); 878 env->pmsav8.rlar[M_REG_S] = g_new0(uint32_t, nr); 879 } 880 } else { 881 env->pmsav7.drbar = g_new0(uint32_t, nr); 882 env->pmsav7.drsr = g_new0(uint32_t, nr); 883 env->pmsav7.dracr = g_new0(uint32_t, nr); 884 } 885 } 886 } 887 888 if (arm_feature(env, ARM_FEATURE_M_SECURITY)) { 889 uint32_t nr = cpu->sau_sregion; 890 891 if (nr > 0xff) { 892 error_setg(errp, "v8M SAU #regions invalid %" PRIu32, nr); 893 return; 894 } 895 896 if (nr) { 897 env->sau.rbar = g_new0(uint32_t, nr); 898 env->sau.rlar = g_new0(uint32_t, nr); 899 } 900 } 901 902 if (arm_feature(env, ARM_FEATURE_EL3)) { 903 set_feature(env, ARM_FEATURE_VBAR); 904 } 905 906 register_cp_regs_for_features(cpu); 907 arm_cpu_register_gdb_regs_for_features(cpu); 908 909 init_cpreg_list(cpu); 910 911 #ifndef CONFIG_USER_ONLY 912 if (cpu->has_el3 || arm_feature(env, ARM_FEATURE_M_SECURITY)) { 913 as = g_new0(AddressSpace, 1); 914 915 cs->num_ases = 2; 916 917 if (!cpu->secure_memory) { 918 cpu->secure_memory = cs->memory; 919 } 920 address_space_init(as, cpu->secure_memory, "cpu-secure-memory"); 921 cpu_address_space_init(cs, as, ARMASIdx_S); 922 } else { 923 cs->num_ases = 1; 924 } 925 as = g_new0(AddressSpace, 1); 926 address_space_init(as, cs->memory, "cpu-memory"); 927 cpu_address_space_init(cs, as, ARMASIdx_NS); 928 #endif 929 930 qemu_init_vcpu(cs); 931 cpu_reset(cs); 932 933 acc->parent_realize(dev, errp); 934 } 935 936 static ObjectClass *arm_cpu_class_by_name(const char *cpu_model) 937 { 938 ObjectClass *oc; 939 char *typename; 940 char **cpuname; 941 942 cpuname = g_strsplit(cpu_model, ",", 1); 943 typename = g_strdup_printf(ARM_CPU_TYPE_NAME("%s"), cpuname[0]); 944 oc = object_class_by_name(typename); 945 g_strfreev(cpuname); 946 g_free(typename); 947 if (!oc || !object_class_dynamic_cast(oc, TYPE_ARM_CPU) || 948 object_class_is_abstract(oc)) { 949 return NULL; 950 } 951 return oc; 952 } 953 954 /* CPU models. These are not needed for the AArch64 linux-user build. */ 955 #if !defined(CONFIG_USER_ONLY) || !defined(TARGET_AARCH64) 956 957 static void arm926_initfn(Object *obj) 958 { 959 ARMCPU *cpu = ARM_CPU(obj); 960 961 cpu->dtb_compatible = "arm,arm926"; 962 set_feature(&cpu->env, ARM_FEATURE_V5); 963 set_feature(&cpu->env, ARM_FEATURE_VFP); 964 set_feature(&cpu->env, ARM_FEATURE_DUMMY_C15_REGS); 965 set_feature(&cpu->env, ARM_FEATURE_CACHE_TEST_CLEAN); 966 set_feature(&cpu->env, ARM_FEATURE_JAZELLE); 967 cpu->midr = 0x41069265; 968 cpu->reset_fpsid = 0x41011090; 969 cpu->ctr = 0x1dd20d2; 970 cpu->reset_sctlr = 0x00090078; 971 } 972 973 static void arm946_initfn(Object *obj) 974 { 975 ARMCPU *cpu = ARM_CPU(obj); 976 977 cpu->dtb_compatible = "arm,arm946"; 978 set_feature(&cpu->env, ARM_FEATURE_V5); 979 set_feature(&cpu->env, ARM_FEATURE_PMSA); 980 set_feature(&cpu->env, ARM_FEATURE_DUMMY_C15_REGS); 981 cpu->midr = 0x41059461; 982 cpu->ctr = 0x0f004006; 983 cpu->reset_sctlr = 0x00000078; 984 } 985 986 static void arm1026_initfn(Object *obj) 987 { 988 ARMCPU *cpu = ARM_CPU(obj); 989 990 cpu->dtb_compatible = "arm,arm1026"; 991 set_feature(&cpu->env, ARM_FEATURE_V5); 992 set_feature(&cpu->env, ARM_FEATURE_VFP); 993 set_feature(&cpu->env, ARM_FEATURE_AUXCR); 994 set_feature(&cpu->env, ARM_FEATURE_DUMMY_C15_REGS); 995 set_feature(&cpu->env, ARM_FEATURE_CACHE_TEST_CLEAN); 996 set_feature(&cpu->env, ARM_FEATURE_JAZELLE); 997 cpu->midr = 0x4106a262; 998 cpu->reset_fpsid = 0x410110a0; 999 cpu->ctr = 0x1dd20d2; 1000 cpu->reset_sctlr = 0x00090078; 1001 cpu->reset_auxcr = 1; 1002 { 1003 /* The 1026 had an IFAR at c6,c0,0,1 rather than the ARMv6 c6,c0,0,2 */ 1004 ARMCPRegInfo ifar = { 1005 .name = "IFAR", .cp = 15, .crn = 6, .crm = 0, .opc1 = 0, .opc2 = 1, 1006 .access = PL1_RW, 1007 .fieldoffset = offsetof(CPUARMState, cp15.ifar_ns), 1008 .resetvalue = 0 1009 }; 1010 define_one_arm_cp_reg(cpu, &ifar); 1011 } 1012 } 1013 1014 static void arm1136_r2_initfn(Object *obj) 1015 { 1016 ARMCPU *cpu = ARM_CPU(obj); 1017 /* What qemu calls "arm1136_r2" is actually the 1136 r0p2, ie an 1018 * older core than plain "arm1136". In particular this does not 1019 * have the v6K features. 1020 * These ID register values are correct for 1136 but may be wrong 1021 * for 1136_r2 (in particular r0p2 does not actually implement most 1022 * of the ID registers). 1023 */ 1024 1025 cpu->dtb_compatible = "arm,arm1136"; 1026 set_feature(&cpu->env, ARM_FEATURE_V6); 1027 set_feature(&cpu->env, ARM_FEATURE_VFP); 1028 set_feature(&cpu->env, ARM_FEATURE_DUMMY_C15_REGS); 1029 set_feature(&cpu->env, ARM_FEATURE_CACHE_DIRTY_REG); 1030 set_feature(&cpu->env, ARM_FEATURE_CACHE_BLOCK_OPS); 1031 cpu->midr = 0x4107b362; 1032 cpu->reset_fpsid = 0x410120b4; 1033 cpu->mvfr0 = 0x11111111; 1034 cpu->mvfr1 = 0x00000000; 1035 cpu->ctr = 0x1dd20d2; 1036 cpu->reset_sctlr = 0x00050078; 1037 cpu->id_pfr0 = 0x111; 1038 cpu->id_pfr1 = 0x1; 1039 cpu->id_dfr0 = 0x2; 1040 cpu->id_afr0 = 0x3; 1041 cpu->id_mmfr0 = 0x01130003; 1042 cpu->id_mmfr1 = 0x10030302; 1043 cpu->id_mmfr2 = 0x01222110; 1044 cpu->id_isar0 = 0x00140011; 1045 cpu->id_isar1 = 0x12002111; 1046 cpu->id_isar2 = 0x11231111; 1047 cpu->id_isar3 = 0x01102131; 1048 cpu->id_isar4 = 0x141; 1049 cpu->reset_auxcr = 7; 1050 } 1051 1052 static void arm1136_initfn(Object *obj) 1053 { 1054 ARMCPU *cpu = ARM_CPU(obj); 1055 1056 cpu->dtb_compatible = "arm,arm1136"; 1057 set_feature(&cpu->env, ARM_FEATURE_V6K); 1058 set_feature(&cpu->env, ARM_FEATURE_V6); 1059 set_feature(&cpu->env, ARM_FEATURE_VFP); 1060 set_feature(&cpu->env, ARM_FEATURE_DUMMY_C15_REGS); 1061 set_feature(&cpu->env, ARM_FEATURE_CACHE_DIRTY_REG); 1062 set_feature(&cpu->env, ARM_FEATURE_CACHE_BLOCK_OPS); 1063 cpu->midr = 0x4117b363; 1064 cpu->reset_fpsid = 0x410120b4; 1065 cpu->mvfr0 = 0x11111111; 1066 cpu->mvfr1 = 0x00000000; 1067 cpu->ctr = 0x1dd20d2; 1068 cpu->reset_sctlr = 0x00050078; 1069 cpu->id_pfr0 = 0x111; 1070 cpu->id_pfr1 = 0x1; 1071 cpu->id_dfr0 = 0x2; 1072 cpu->id_afr0 = 0x3; 1073 cpu->id_mmfr0 = 0x01130003; 1074 cpu->id_mmfr1 = 0x10030302; 1075 cpu->id_mmfr2 = 0x01222110; 1076 cpu->id_isar0 = 0x00140011; 1077 cpu->id_isar1 = 0x12002111; 1078 cpu->id_isar2 = 0x11231111; 1079 cpu->id_isar3 = 0x01102131; 1080 cpu->id_isar4 = 0x141; 1081 cpu->reset_auxcr = 7; 1082 } 1083 1084 static void arm1176_initfn(Object *obj) 1085 { 1086 ARMCPU *cpu = ARM_CPU(obj); 1087 1088 cpu->dtb_compatible = "arm,arm1176"; 1089 set_feature(&cpu->env, ARM_FEATURE_V6K); 1090 set_feature(&cpu->env, ARM_FEATURE_VFP); 1091 set_feature(&cpu->env, ARM_FEATURE_VAPA); 1092 set_feature(&cpu->env, ARM_FEATURE_DUMMY_C15_REGS); 1093 set_feature(&cpu->env, ARM_FEATURE_CACHE_DIRTY_REG); 1094 set_feature(&cpu->env, ARM_FEATURE_CACHE_BLOCK_OPS); 1095 set_feature(&cpu->env, ARM_FEATURE_EL3); 1096 cpu->midr = 0x410fb767; 1097 cpu->reset_fpsid = 0x410120b5; 1098 cpu->mvfr0 = 0x11111111; 1099 cpu->mvfr1 = 0x00000000; 1100 cpu->ctr = 0x1dd20d2; 1101 cpu->reset_sctlr = 0x00050078; 1102 cpu->id_pfr0 = 0x111; 1103 cpu->id_pfr1 = 0x11; 1104 cpu->id_dfr0 = 0x33; 1105 cpu->id_afr0 = 0; 1106 cpu->id_mmfr0 = 0x01130003; 1107 cpu->id_mmfr1 = 0x10030302; 1108 cpu->id_mmfr2 = 0x01222100; 1109 cpu->id_isar0 = 0x0140011; 1110 cpu->id_isar1 = 0x12002111; 1111 cpu->id_isar2 = 0x11231121; 1112 cpu->id_isar3 = 0x01102131; 1113 cpu->id_isar4 = 0x01141; 1114 cpu->reset_auxcr = 7; 1115 } 1116 1117 static void arm11mpcore_initfn(Object *obj) 1118 { 1119 ARMCPU *cpu = ARM_CPU(obj); 1120 1121 cpu->dtb_compatible = "arm,arm11mpcore"; 1122 set_feature(&cpu->env, ARM_FEATURE_V6K); 1123 set_feature(&cpu->env, ARM_FEATURE_VFP); 1124 set_feature(&cpu->env, ARM_FEATURE_VAPA); 1125 set_feature(&cpu->env, ARM_FEATURE_MPIDR); 1126 set_feature(&cpu->env, ARM_FEATURE_DUMMY_C15_REGS); 1127 cpu->midr = 0x410fb022; 1128 cpu->reset_fpsid = 0x410120b4; 1129 cpu->mvfr0 = 0x11111111; 1130 cpu->mvfr1 = 0x00000000; 1131 cpu->ctr = 0x1d192992; /* 32K icache 32K dcache */ 1132 cpu->id_pfr0 = 0x111; 1133 cpu->id_pfr1 = 0x1; 1134 cpu->id_dfr0 = 0; 1135 cpu->id_afr0 = 0x2; 1136 cpu->id_mmfr0 = 0x01100103; 1137 cpu->id_mmfr1 = 0x10020302; 1138 cpu->id_mmfr2 = 0x01222000; 1139 cpu->id_isar0 = 0x00100011; 1140 cpu->id_isar1 = 0x12002111; 1141 cpu->id_isar2 = 0x11221011; 1142 cpu->id_isar3 = 0x01102131; 1143 cpu->id_isar4 = 0x141; 1144 cpu->reset_auxcr = 1; 1145 } 1146 1147 static void cortex_m3_initfn(Object *obj) 1148 { 1149 ARMCPU *cpu = ARM_CPU(obj); 1150 set_feature(&cpu->env, ARM_FEATURE_V7); 1151 set_feature(&cpu->env, ARM_FEATURE_M); 1152 cpu->midr = 0x410fc231; 1153 cpu->pmsav7_dregion = 8; 1154 } 1155 1156 static void cortex_m4_initfn(Object *obj) 1157 { 1158 ARMCPU *cpu = ARM_CPU(obj); 1159 1160 set_feature(&cpu->env, ARM_FEATURE_V7); 1161 set_feature(&cpu->env, ARM_FEATURE_M); 1162 set_feature(&cpu->env, ARM_FEATURE_THUMB_DSP); 1163 cpu->midr = 0x410fc240; /* r0p0 */ 1164 cpu->pmsav7_dregion = 8; 1165 } 1166 1167 static void arm_v7m_class_init(ObjectClass *oc, void *data) 1168 { 1169 CPUClass *cc = CPU_CLASS(oc); 1170 1171 #ifndef CONFIG_USER_ONLY 1172 cc->do_interrupt = arm_v7m_cpu_do_interrupt; 1173 #endif 1174 1175 cc->cpu_exec_interrupt = arm_v7m_cpu_exec_interrupt; 1176 } 1177 1178 static const ARMCPRegInfo cortexr5_cp_reginfo[] = { 1179 /* Dummy the TCM region regs for the moment */ 1180 { .name = "ATCM", .cp = 15, .opc1 = 0, .crn = 9, .crm = 1, .opc2 = 0, 1181 .access = PL1_RW, .type = ARM_CP_CONST }, 1182 { .name = "BTCM", .cp = 15, .opc1 = 0, .crn = 9, .crm = 1, .opc2 = 1, 1183 .access = PL1_RW, .type = ARM_CP_CONST }, 1184 { .name = "DCACHE_INVAL", .cp = 15, .opc1 = 0, .crn = 15, .crm = 5, 1185 .opc2 = 0, .access = PL1_W, .type = ARM_CP_NOP }, 1186 REGINFO_SENTINEL 1187 }; 1188 1189 static void cortex_r5_initfn(Object *obj) 1190 { 1191 ARMCPU *cpu = ARM_CPU(obj); 1192 1193 set_feature(&cpu->env, ARM_FEATURE_V7); 1194 set_feature(&cpu->env, ARM_FEATURE_THUMB_DIV); 1195 set_feature(&cpu->env, ARM_FEATURE_ARM_DIV); 1196 set_feature(&cpu->env, ARM_FEATURE_V7MP); 1197 set_feature(&cpu->env, ARM_FEATURE_PMSA); 1198 cpu->midr = 0x411fc153; /* r1p3 */ 1199 cpu->id_pfr0 = 0x0131; 1200 cpu->id_pfr1 = 0x001; 1201 cpu->id_dfr0 = 0x010400; 1202 cpu->id_afr0 = 0x0; 1203 cpu->id_mmfr0 = 0x0210030; 1204 cpu->id_mmfr1 = 0x00000000; 1205 cpu->id_mmfr2 = 0x01200000; 1206 cpu->id_mmfr3 = 0x0211; 1207 cpu->id_isar0 = 0x2101111; 1208 cpu->id_isar1 = 0x13112111; 1209 cpu->id_isar2 = 0x21232141; 1210 cpu->id_isar3 = 0x01112131; 1211 cpu->id_isar4 = 0x0010142; 1212 cpu->id_isar5 = 0x0; 1213 cpu->mp_is_up = true; 1214 cpu->pmsav7_dregion = 16; 1215 define_arm_cp_regs(cpu, cortexr5_cp_reginfo); 1216 } 1217 1218 static const ARMCPRegInfo cortexa8_cp_reginfo[] = { 1219 { .name = "L2LOCKDOWN", .cp = 15, .crn = 9, .crm = 0, .opc1 = 1, .opc2 = 0, 1220 .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0 }, 1221 { .name = "L2AUXCR", .cp = 15, .crn = 9, .crm = 0, .opc1 = 1, .opc2 = 2, 1222 .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0 }, 1223 REGINFO_SENTINEL 1224 }; 1225 1226 static void cortex_a8_initfn(Object *obj) 1227 { 1228 ARMCPU *cpu = ARM_CPU(obj); 1229 1230 cpu->dtb_compatible = "arm,cortex-a8"; 1231 set_feature(&cpu->env, ARM_FEATURE_V7); 1232 set_feature(&cpu->env, ARM_FEATURE_VFP3); 1233 set_feature(&cpu->env, ARM_FEATURE_NEON); 1234 set_feature(&cpu->env, ARM_FEATURE_THUMB2EE); 1235 set_feature(&cpu->env, ARM_FEATURE_DUMMY_C15_REGS); 1236 set_feature(&cpu->env, ARM_FEATURE_EL3); 1237 cpu->midr = 0x410fc080; 1238 cpu->reset_fpsid = 0x410330c0; 1239 cpu->mvfr0 = 0x11110222; 1240 cpu->mvfr1 = 0x00011111; 1241 cpu->ctr = 0x82048004; 1242 cpu->reset_sctlr = 0x00c50078; 1243 cpu->id_pfr0 = 0x1031; 1244 cpu->id_pfr1 = 0x11; 1245 cpu->id_dfr0 = 0x400; 1246 cpu->id_afr0 = 0; 1247 cpu->id_mmfr0 = 0x31100003; 1248 cpu->id_mmfr1 = 0x20000000; 1249 cpu->id_mmfr2 = 0x01202000; 1250 cpu->id_mmfr3 = 0x11; 1251 cpu->id_isar0 = 0x00101111; 1252 cpu->id_isar1 = 0x12112111; 1253 cpu->id_isar2 = 0x21232031; 1254 cpu->id_isar3 = 0x11112131; 1255 cpu->id_isar4 = 0x00111142; 1256 cpu->dbgdidr = 0x15141000; 1257 cpu->clidr = (1 << 27) | (2 << 24) | 3; 1258 cpu->ccsidr[0] = 0xe007e01a; /* 16k L1 dcache. */ 1259 cpu->ccsidr[1] = 0x2007e01a; /* 16k L1 icache. */ 1260 cpu->ccsidr[2] = 0xf0000000; /* No L2 icache. */ 1261 cpu->reset_auxcr = 2; 1262 define_arm_cp_regs(cpu, cortexa8_cp_reginfo); 1263 } 1264 1265 static const ARMCPRegInfo cortexa9_cp_reginfo[] = { 1266 /* power_control should be set to maximum latency. Again, 1267 * default to 0 and set by private hook 1268 */ 1269 { .name = "A9_PWRCTL", .cp = 15, .crn = 15, .crm = 0, .opc1 = 0, .opc2 = 0, 1270 .access = PL1_RW, .resetvalue = 0, 1271 .fieldoffset = offsetof(CPUARMState, cp15.c15_power_control) }, 1272 { .name = "A9_DIAG", .cp = 15, .crn = 15, .crm = 0, .opc1 = 0, .opc2 = 1, 1273 .access = PL1_RW, .resetvalue = 0, 1274 .fieldoffset = offsetof(CPUARMState, cp15.c15_diagnostic) }, 1275 { .name = "A9_PWRDIAG", .cp = 15, .crn = 15, .crm = 0, .opc1 = 0, .opc2 = 2, 1276 .access = PL1_RW, .resetvalue = 0, 1277 .fieldoffset = offsetof(CPUARMState, cp15.c15_power_diagnostic) }, 1278 { .name = "NEONBUSY", .cp = 15, .crn = 15, .crm = 1, .opc1 = 0, .opc2 = 0, 1279 .access = PL1_RW, .resetvalue = 0, .type = ARM_CP_CONST }, 1280 /* TLB lockdown control */ 1281 { .name = "TLB_LOCKR", .cp = 15, .crn = 15, .crm = 4, .opc1 = 5, .opc2 = 2, 1282 .access = PL1_W, .resetvalue = 0, .type = ARM_CP_NOP }, 1283 { .name = "TLB_LOCKW", .cp = 15, .crn = 15, .crm = 4, .opc1 = 5, .opc2 = 4, 1284 .access = PL1_W, .resetvalue = 0, .type = ARM_CP_NOP }, 1285 { .name = "TLB_VA", .cp = 15, .crn = 15, .crm = 5, .opc1 = 5, .opc2 = 2, 1286 .access = PL1_RW, .resetvalue = 0, .type = ARM_CP_CONST }, 1287 { .name = "TLB_PA", .cp = 15, .crn = 15, .crm = 6, .opc1 = 5, .opc2 = 2, 1288 .access = PL1_RW, .resetvalue = 0, .type = ARM_CP_CONST }, 1289 { .name = "TLB_ATTR", .cp = 15, .crn = 15, .crm = 7, .opc1 = 5, .opc2 = 2, 1290 .access = PL1_RW, .resetvalue = 0, .type = ARM_CP_CONST }, 1291 REGINFO_SENTINEL 1292 }; 1293 1294 static void cortex_a9_initfn(Object *obj) 1295 { 1296 ARMCPU *cpu = ARM_CPU(obj); 1297 1298 cpu->dtb_compatible = "arm,cortex-a9"; 1299 set_feature(&cpu->env, ARM_FEATURE_V7); 1300 set_feature(&cpu->env, ARM_FEATURE_VFP3); 1301 set_feature(&cpu->env, ARM_FEATURE_VFP_FP16); 1302 set_feature(&cpu->env, ARM_FEATURE_NEON); 1303 set_feature(&cpu->env, ARM_FEATURE_THUMB2EE); 1304 set_feature(&cpu->env, ARM_FEATURE_EL3); 1305 /* Note that A9 supports the MP extensions even for 1306 * A9UP and single-core A9MP (which are both different 1307 * and valid configurations; we don't model A9UP). 1308 */ 1309 set_feature(&cpu->env, ARM_FEATURE_V7MP); 1310 set_feature(&cpu->env, ARM_FEATURE_CBAR); 1311 cpu->midr = 0x410fc090; 1312 cpu->reset_fpsid = 0x41033090; 1313 cpu->mvfr0 = 0x11110222; 1314 cpu->mvfr1 = 0x01111111; 1315 cpu->ctr = 0x80038003; 1316 cpu->reset_sctlr = 0x00c50078; 1317 cpu->id_pfr0 = 0x1031; 1318 cpu->id_pfr1 = 0x11; 1319 cpu->id_dfr0 = 0x000; 1320 cpu->id_afr0 = 0; 1321 cpu->id_mmfr0 = 0x00100103; 1322 cpu->id_mmfr1 = 0x20000000; 1323 cpu->id_mmfr2 = 0x01230000; 1324 cpu->id_mmfr3 = 0x00002111; 1325 cpu->id_isar0 = 0x00101111; 1326 cpu->id_isar1 = 0x13112111; 1327 cpu->id_isar2 = 0x21232041; 1328 cpu->id_isar3 = 0x11112131; 1329 cpu->id_isar4 = 0x00111142; 1330 cpu->dbgdidr = 0x35141000; 1331 cpu->clidr = (1 << 27) | (1 << 24) | 3; 1332 cpu->ccsidr[0] = 0xe00fe019; /* 16k L1 dcache. */ 1333 cpu->ccsidr[1] = 0x200fe019; /* 16k L1 icache. */ 1334 define_arm_cp_regs(cpu, cortexa9_cp_reginfo); 1335 } 1336 1337 #ifndef CONFIG_USER_ONLY 1338 static uint64_t a15_l2ctlr_read(CPUARMState *env, const ARMCPRegInfo *ri) 1339 { 1340 /* Linux wants the number of processors from here. 1341 * Might as well set the interrupt-controller bit too. 1342 */ 1343 return ((smp_cpus - 1) << 24) | (1 << 23); 1344 } 1345 #endif 1346 1347 static const ARMCPRegInfo cortexa15_cp_reginfo[] = { 1348 #ifndef CONFIG_USER_ONLY 1349 { .name = "L2CTLR", .cp = 15, .crn = 9, .crm = 0, .opc1 = 1, .opc2 = 2, 1350 .access = PL1_RW, .resetvalue = 0, .readfn = a15_l2ctlr_read, 1351 .writefn = arm_cp_write_ignore, }, 1352 #endif 1353 { .name = "L2ECTLR", .cp = 15, .crn = 9, .crm = 0, .opc1 = 1, .opc2 = 3, 1354 .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0 }, 1355 REGINFO_SENTINEL 1356 }; 1357 1358 static void cortex_a7_initfn(Object *obj) 1359 { 1360 ARMCPU *cpu = ARM_CPU(obj); 1361 1362 cpu->dtb_compatible = "arm,cortex-a7"; 1363 set_feature(&cpu->env, ARM_FEATURE_V7); 1364 set_feature(&cpu->env, ARM_FEATURE_VFP4); 1365 set_feature(&cpu->env, ARM_FEATURE_NEON); 1366 set_feature(&cpu->env, ARM_FEATURE_THUMB2EE); 1367 set_feature(&cpu->env, ARM_FEATURE_ARM_DIV); 1368 set_feature(&cpu->env, ARM_FEATURE_GENERIC_TIMER); 1369 set_feature(&cpu->env, ARM_FEATURE_DUMMY_C15_REGS); 1370 set_feature(&cpu->env, ARM_FEATURE_CBAR_RO); 1371 set_feature(&cpu->env, ARM_FEATURE_LPAE); 1372 set_feature(&cpu->env, ARM_FEATURE_EL3); 1373 cpu->kvm_target = QEMU_KVM_ARM_TARGET_CORTEX_A7; 1374 cpu->midr = 0x410fc075; 1375 cpu->reset_fpsid = 0x41023075; 1376 cpu->mvfr0 = 0x10110222; 1377 cpu->mvfr1 = 0x11111111; 1378 cpu->ctr = 0x84448003; 1379 cpu->reset_sctlr = 0x00c50078; 1380 cpu->id_pfr0 = 0x00001131; 1381 cpu->id_pfr1 = 0x00011011; 1382 cpu->id_dfr0 = 0x02010555; 1383 cpu->pmceid0 = 0x00000000; 1384 cpu->pmceid1 = 0x00000000; 1385 cpu->id_afr0 = 0x00000000; 1386 cpu->id_mmfr0 = 0x10101105; 1387 cpu->id_mmfr1 = 0x40000000; 1388 cpu->id_mmfr2 = 0x01240000; 1389 cpu->id_mmfr3 = 0x02102211; 1390 cpu->id_isar0 = 0x01101110; 1391 cpu->id_isar1 = 0x13112111; 1392 cpu->id_isar2 = 0x21232041; 1393 cpu->id_isar3 = 0x11112131; 1394 cpu->id_isar4 = 0x10011142; 1395 cpu->dbgdidr = 0x3515f005; 1396 cpu->clidr = 0x0a200023; 1397 cpu->ccsidr[0] = 0x701fe00a; /* 32K L1 dcache */ 1398 cpu->ccsidr[1] = 0x201fe00a; /* 32K L1 icache */ 1399 cpu->ccsidr[2] = 0x711fe07a; /* 4096K L2 unified cache */ 1400 define_arm_cp_regs(cpu, cortexa15_cp_reginfo); /* Same as A15 */ 1401 } 1402 1403 static void cortex_a15_initfn(Object *obj) 1404 { 1405 ARMCPU *cpu = ARM_CPU(obj); 1406 1407 cpu->dtb_compatible = "arm,cortex-a15"; 1408 set_feature(&cpu->env, ARM_FEATURE_V7); 1409 set_feature(&cpu->env, ARM_FEATURE_VFP4); 1410 set_feature(&cpu->env, ARM_FEATURE_NEON); 1411 set_feature(&cpu->env, ARM_FEATURE_THUMB2EE); 1412 set_feature(&cpu->env, ARM_FEATURE_ARM_DIV); 1413 set_feature(&cpu->env, ARM_FEATURE_GENERIC_TIMER); 1414 set_feature(&cpu->env, ARM_FEATURE_DUMMY_C15_REGS); 1415 set_feature(&cpu->env, ARM_FEATURE_CBAR_RO); 1416 set_feature(&cpu->env, ARM_FEATURE_LPAE); 1417 set_feature(&cpu->env, ARM_FEATURE_EL3); 1418 cpu->kvm_target = QEMU_KVM_ARM_TARGET_CORTEX_A15; 1419 cpu->midr = 0x412fc0f1; 1420 cpu->reset_fpsid = 0x410430f0; 1421 cpu->mvfr0 = 0x10110222; 1422 cpu->mvfr1 = 0x11111111; 1423 cpu->ctr = 0x8444c004; 1424 cpu->reset_sctlr = 0x00c50078; 1425 cpu->id_pfr0 = 0x00001131; 1426 cpu->id_pfr1 = 0x00011011; 1427 cpu->id_dfr0 = 0x02010555; 1428 cpu->pmceid0 = 0x0000000; 1429 cpu->pmceid1 = 0x00000000; 1430 cpu->id_afr0 = 0x00000000; 1431 cpu->id_mmfr0 = 0x10201105; 1432 cpu->id_mmfr1 = 0x20000000; 1433 cpu->id_mmfr2 = 0x01240000; 1434 cpu->id_mmfr3 = 0x02102211; 1435 cpu->id_isar0 = 0x02101110; 1436 cpu->id_isar1 = 0x13112111; 1437 cpu->id_isar2 = 0x21232041; 1438 cpu->id_isar3 = 0x11112131; 1439 cpu->id_isar4 = 0x10011142; 1440 cpu->dbgdidr = 0x3515f021; 1441 cpu->clidr = 0x0a200023; 1442 cpu->ccsidr[0] = 0x701fe00a; /* 32K L1 dcache */ 1443 cpu->ccsidr[1] = 0x201fe00a; /* 32K L1 icache */ 1444 cpu->ccsidr[2] = 0x711fe07a; /* 4096K L2 unified cache */ 1445 define_arm_cp_regs(cpu, cortexa15_cp_reginfo); 1446 } 1447 1448 static void ti925t_initfn(Object *obj) 1449 { 1450 ARMCPU *cpu = ARM_CPU(obj); 1451 set_feature(&cpu->env, ARM_FEATURE_V4T); 1452 set_feature(&cpu->env, ARM_FEATURE_OMAPCP); 1453 cpu->midr = ARM_CPUID_TI925T; 1454 cpu->ctr = 0x5109149; 1455 cpu->reset_sctlr = 0x00000070; 1456 } 1457 1458 static void sa1100_initfn(Object *obj) 1459 { 1460 ARMCPU *cpu = ARM_CPU(obj); 1461 1462 cpu->dtb_compatible = "intel,sa1100"; 1463 set_feature(&cpu->env, ARM_FEATURE_STRONGARM); 1464 set_feature(&cpu->env, ARM_FEATURE_DUMMY_C15_REGS); 1465 cpu->midr = 0x4401A11B; 1466 cpu->reset_sctlr = 0x00000070; 1467 } 1468 1469 static void sa1110_initfn(Object *obj) 1470 { 1471 ARMCPU *cpu = ARM_CPU(obj); 1472 set_feature(&cpu->env, ARM_FEATURE_STRONGARM); 1473 set_feature(&cpu->env, ARM_FEATURE_DUMMY_C15_REGS); 1474 cpu->midr = 0x6901B119; 1475 cpu->reset_sctlr = 0x00000070; 1476 } 1477 1478 static void pxa250_initfn(Object *obj) 1479 { 1480 ARMCPU *cpu = ARM_CPU(obj); 1481 1482 cpu->dtb_compatible = "marvell,xscale"; 1483 set_feature(&cpu->env, ARM_FEATURE_V5); 1484 set_feature(&cpu->env, ARM_FEATURE_XSCALE); 1485 cpu->midr = 0x69052100; 1486 cpu->ctr = 0xd172172; 1487 cpu->reset_sctlr = 0x00000078; 1488 } 1489 1490 static void pxa255_initfn(Object *obj) 1491 { 1492 ARMCPU *cpu = ARM_CPU(obj); 1493 1494 cpu->dtb_compatible = "marvell,xscale"; 1495 set_feature(&cpu->env, ARM_FEATURE_V5); 1496 set_feature(&cpu->env, ARM_FEATURE_XSCALE); 1497 cpu->midr = 0x69052d00; 1498 cpu->ctr = 0xd172172; 1499 cpu->reset_sctlr = 0x00000078; 1500 } 1501 1502 static void pxa260_initfn(Object *obj) 1503 { 1504 ARMCPU *cpu = ARM_CPU(obj); 1505 1506 cpu->dtb_compatible = "marvell,xscale"; 1507 set_feature(&cpu->env, ARM_FEATURE_V5); 1508 set_feature(&cpu->env, ARM_FEATURE_XSCALE); 1509 cpu->midr = 0x69052903; 1510 cpu->ctr = 0xd172172; 1511 cpu->reset_sctlr = 0x00000078; 1512 } 1513 1514 static void pxa261_initfn(Object *obj) 1515 { 1516 ARMCPU *cpu = ARM_CPU(obj); 1517 1518 cpu->dtb_compatible = "marvell,xscale"; 1519 set_feature(&cpu->env, ARM_FEATURE_V5); 1520 set_feature(&cpu->env, ARM_FEATURE_XSCALE); 1521 cpu->midr = 0x69052d05; 1522 cpu->ctr = 0xd172172; 1523 cpu->reset_sctlr = 0x00000078; 1524 } 1525 1526 static void pxa262_initfn(Object *obj) 1527 { 1528 ARMCPU *cpu = ARM_CPU(obj); 1529 1530 cpu->dtb_compatible = "marvell,xscale"; 1531 set_feature(&cpu->env, ARM_FEATURE_V5); 1532 set_feature(&cpu->env, ARM_FEATURE_XSCALE); 1533 cpu->midr = 0x69052d06; 1534 cpu->ctr = 0xd172172; 1535 cpu->reset_sctlr = 0x00000078; 1536 } 1537 1538 static void pxa270a0_initfn(Object *obj) 1539 { 1540 ARMCPU *cpu = ARM_CPU(obj); 1541 1542 cpu->dtb_compatible = "marvell,xscale"; 1543 set_feature(&cpu->env, ARM_FEATURE_V5); 1544 set_feature(&cpu->env, ARM_FEATURE_XSCALE); 1545 set_feature(&cpu->env, ARM_FEATURE_IWMMXT); 1546 cpu->midr = 0x69054110; 1547 cpu->ctr = 0xd172172; 1548 cpu->reset_sctlr = 0x00000078; 1549 } 1550 1551 static void pxa270a1_initfn(Object *obj) 1552 { 1553 ARMCPU *cpu = ARM_CPU(obj); 1554 1555 cpu->dtb_compatible = "marvell,xscale"; 1556 set_feature(&cpu->env, ARM_FEATURE_V5); 1557 set_feature(&cpu->env, ARM_FEATURE_XSCALE); 1558 set_feature(&cpu->env, ARM_FEATURE_IWMMXT); 1559 cpu->midr = 0x69054111; 1560 cpu->ctr = 0xd172172; 1561 cpu->reset_sctlr = 0x00000078; 1562 } 1563 1564 static void pxa270b0_initfn(Object *obj) 1565 { 1566 ARMCPU *cpu = ARM_CPU(obj); 1567 1568 cpu->dtb_compatible = "marvell,xscale"; 1569 set_feature(&cpu->env, ARM_FEATURE_V5); 1570 set_feature(&cpu->env, ARM_FEATURE_XSCALE); 1571 set_feature(&cpu->env, ARM_FEATURE_IWMMXT); 1572 cpu->midr = 0x69054112; 1573 cpu->ctr = 0xd172172; 1574 cpu->reset_sctlr = 0x00000078; 1575 } 1576 1577 static void pxa270b1_initfn(Object *obj) 1578 { 1579 ARMCPU *cpu = ARM_CPU(obj); 1580 1581 cpu->dtb_compatible = "marvell,xscale"; 1582 set_feature(&cpu->env, ARM_FEATURE_V5); 1583 set_feature(&cpu->env, ARM_FEATURE_XSCALE); 1584 set_feature(&cpu->env, ARM_FEATURE_IWMMXT); 1585 cpu->midr = 0x69054113; 1586 cpu->ctr = 0xd172172; 1587 cpu->reset_sctlr = 0x00000078; 1588 } 1589 1590 static void pxa270c0_initfn(Object *obj) 1591 { 1592 ARMCPU *cpu = ARM_CPU(obj); 1593 1594 cpu->dtb_compatible = "marvell,xscale"; 1595 set_feature(&cpu->env, ARM_FEATURE_V5); 1596 set_feature(&cpu->env, ARM_FEATURE_XSCALE); 1597 set_feature(&cpu->env, ARM_FEATURE_IWMMXT); 1598 cpu->midr = 0x69054114; 1599 cpu->ctr = 0xd172172; 1600 cpu->reset_sctlr = 0x00000078; 1601 } 1602 1603 static void pxa270c5_initfn(Object *obj) 1604 { 1605 ARMCPU *cpu = ARM_CPU(obj); 1606 1607 cpu->dtb_compatible = "marvell,xscale"; 1608 set_feature(&cpu->env, ARM_FEATURE_V5); 1609 set_feature(&cpu->env, ARM_FEATURE_XSCALE); 1610 set_feature(&cpu->env, ARM_FEATURE_IWMMXT); 1611 cpu->midr = 0x69054117; 1612 cpu->ctr = 0xd172172; 1613 cpu->reset_sctlr = 0x00000078; 1614 } 1615 1616 #ifdef CONFIG_USER_ONLY 1617 static void arm_any_initfn(Object *obj) 1618 { 1619 ARMCPU *cpu = ARM_CPU(obj); 1620 set_feature(&cpu->env, ARM_FEATURE_V8); 1621 set_feature(&cpu->env, ARM_FEATURE_VFP4); 1622 set_feature(&cpu->env, ARM_FEATURE_NEON); 1623 set_feature(&cpu->env, ARM_FEATURE_THUMB2EE); 1624 set_feature(&cpu->env, ARM_FEATURE_V8_AES); 1625 set_feature(&cpu->env, ARM_FEATURE_V8_SHA1); 1626 set_feature(&cpu->env, ARM_FEATURE_V8_SHA256); 1627 set_feature(&cpu->env, ARM_FEATURE_V8_PMULL); 1628 set_feature(&cpu->env, ARM_FEATURE_CRC); 1629 cpu->midr = 0xffffffff; 1630 } 1631 #endif 1632 1633 #endif /* !defined(CONFIG_USER_ONLY) || !defined(TARGET_AARCH64) */ 1634 1635 typedef struct ARMCPUInfo { 1636 const char *name; 1637 void (*initfn)(Object *obj); 1638 void (*class_init)(ObjectClass *oc, void *data); 1639 } ARMCPUInfo; 1640 1641 static const ARMCPUInfo arm_cpus[] = { 1642 #if !defined(CONFIG_USER_ONLY) || !defined(TARGET_AARCH64) 1643 { .name = "arm926", .initfn = arm926_initfn }, 1644 { .name = "arm946", .initfn = arm946_initfn }, 1645 { .name = "arm1026", .initfn = arm1026_initfn }, 1646 /* What QEMU calls "arm1136-r2" is actually the 1136 r0p2, i.e. an 1647 * older core than plain "arm1136". In particular this does not 1648 * have the v6K features. 1649 */ 1650 { .name = "arm1136-r2", .initfn = arm1136_r2_initfn }, 1651 { .name = "arm1136", .initfn = arm1136_initfn }, 1652 { .name = "arm1176", .initfn = arm1176_initfn }, 1653 { .name = "arm11mpcore", .initfn = arm11mpcore_initfn }, 1654 { .name = "cortex-m3", .initfn = cortex_m3_initfn, 1655 .class_init = arm_v7m_class_init }, 1656 { .name = "cortex-m4", .initfn = cortex_m4_initfn, 1657 .class_init = arm_v7m_class_init }, 1658 { .name = "cortex-r5", .initfn = cortex_r5_initfn }, 1659 { .name = "cortex-a7", .initfn = cortex_a7_initfn }, 1660 { .name = "cortex-a8", .initfn = cortex_a8_initfn }, 1661 { .name = "cortex-a9", .initfn = cortex_a9_initfn }, 1662 { .name = "cortex-a15", .initfn = cortex_a15_initfn }, 1663 { .name = "ti925t", .initfn = ti925t_initfn }, 1664 { .name = "sa1100", .initfn = sa1100_initfn }, 1665 { .name = "sa1110", .initfn = sa1110_initfn }, 1666 { .name = "pxa250", .initfn = pxa250_initfn }, 1667 { .name = "pxa255", .initfn = pxa255_initfn }, 1668 { .name = "pxa260", .initfn = pxa260_initfn }, 1669 { .name = "pxa261", .initfn = pxa261_initfn }, 1670 { .name = "pxa262", .initfn = pxa262_initfn }, 1671 /* "pxa270" is an alias for "pxa270-a0" */ 1672 { .name = "pxa270", .initfn = pxa270a0_initfn }, 1673 { .name = "pxa270-a0", .initfn = pxa270a0_initfn }, 1674 { .name = "pxa270-a1", .initfn = pxa270a1_initfn }, 1675 { .name = "pxa270-b0", .initfn = pxa270b0_initfn }, 1676 { .name = "pxa270-b1", .initfn = pxa270b1_initfn }, 1677 { .name = "pxa270-c0", .initfn = pxa270c0_initfn }, 1678 { .name = "pxa270-c5", .initfn = pxa270c5_initfn }, 1679 #ifdef CONFIG_USER_ONLY 1680 { .name = "any", .initfn = arm_any_initfn }, 1681 #endif 1682 #endif 1683 { .name = NULL } 1684 }; 1685 1686 static Property arm_cpu_properties[] = { 1687 DEFINE_PROP_BOOL("start-powered-off", ARMCPU, start_powered_off, false), 1688 DEFINE_PROP_UINT32("psci-conduit", ARMCPU, psci_conduit, 0), 1689 DEFINE_PROP_UINT32("midr", ARMCPU, midr, 0), 1690 DEFINE_PROP_UINT64("mp-affinity", ARMCPU, 1691 mp_affinity, ARM64_AFFINITY_INVALID), 1692 DEFINE_PROP_INT32("node-id", ARMCPU, node_id, CPU_UNSET_NUMA_NODE_ID), 1693 DEFINE_PROP_END_OF_LIST() 1694 }; 1695 1696 #ifdef CONFIG_USER_ONLY 1697 static int arm_cpu_handle_mmu_fault(CPUState *cs, vaddr address, int rw, 1698 int mmu_idx) 1699 { 1700 ARMCPU *cpu = ARM_CPU(cs); 1701 CPUARMState *env = &cpu->env; 1702 1703 env->exception.vaddress = address; 1704 if (rw == 2) { 1705 cs->exception_index = EXCP_PREFETCH_ABORT; 1706 } else { 1707 cs->exception_index = EXCP_DATA_ABORT; 1708 } 1709 return 1; 1710 } 1711 #endif 1712 1713 static gchar *arm_gdb_arch_name(CPUState *cs) 1714 { 1715 ARMCPU *cpu = ARM_CPU(cs); 1716 CPUARMState *env = &cpu->env; 1717 1718 if (arm_feature(env, ARM_FEATURE_IWMMXT)) { 1719 return g_strdup("iwmmxt"); 1720 } 1721 return g_strdup("arm"); 1722 } 1723 1724 static void arm_cpu_class_init(ObjectClass *oc, void *data) 1725 { 1726 ARMCPUClass *acc = ARM_CPU_CLASS(oc); 1727 CPUClass *cc = CPU_CLASS(acc); 1728 DeviceClass *dc = DEVICE_CLASS(oc); 1729 1730 acc->parent_realize = dc->realize; 1731 dc->realize = arm_cpu_realizefn; 1732 dc->props = arm_cpu_properties; 1733 1734 acc->parent_reset = cc->reset; 1735 cc->reset = arm_cpu_reset; 1736 1737 cc->class_by_name = arm_cpu_class_by_name; 1738 cc->has_work = arm_cpu_has_work; 1739 cc->cpu_exec_interrupt = arm_cpu_exec_interrupt; 1740 cc->dump_state = arm_cpu_dump_state; 1741 cc->set_pc = arm_cpu_set_pc; 1742 cc->gdb_read_register = arm_cpu_gdb_read_register; 1743 cc->gdb_write_register = arm_cpu_gdb_write_register; 1744 #ifdef CONFIG_USER_ONLY 1745 cc->handle_mmu_fault = arm_cpu_handle_mmu_fault; 1746 #else 1747 cc->do_interrupt = arm_cpu_do_interrupt; 1748 cc->do_unaligned_access = arm_cpu_do_unaligned_access; 1749 cc->do_transaction_failed = arm_cpu_do_transaction_failed; 1750 cc->get_phys_page_attrs_debug = arm_cpu_get_phys_page_attrs_debug; 1751 cc->asidx_from_attrs = arm_asidx_from_attrs; 1752 cc->vmsd = &vmstate_arm_cpu; 1753 cc->virtio_is_big_endian = arm_cpu_virtio_is_big_endian; 1754 cc->write_elf64_note = arm_cpu_write_elf64_note; 1755 cc->write_elf32_note = arm_cpu_write_elf32_note; 1756 #endif 1757 cc->gdb_num_core_regs = 26; 1758 cc->gdb_core_xml_file = "arm-core.xml"; 1759 cc->gdb_arch_name = arm_gdb_arch_name; 1760 cc->gdb_stop_before_watchpoint = true; 1761 cc->debug_excp_handler = arm_debug_excp_handler; 1762 cc->debug_check_watchpoint = arm_debug_check_watchpoint; 1763 #if !defined(CONFIG_USER_ONLY) 1764 cc->adjust_watchpoint_address = arm_adjust_watchpoint_address; 1765 #endif 1766 1767 cc->disas_set_info = arm_disas_set_info; 1768 } 1769 1770 static void cpu_register(const ARMCPUInfo *info) 1771 { 1772 TypeInfo type_info = { 1773 .parent = TYPE_ARM_CPU, 1774 .instance_size = sizeof(ARMCPU), 1775 .instance_init = info->initfn, 1776 .class_size = sizeof(ARMCPUClass), 1777 .class_init = info->class_init, 1778 }; 1779 1780 type_info.name = g_strdup_printf("%s-" TYPE_ARM_CPU, info->name); 1781 type_register(&type_info); 1782 g_free((void *)type_info.name); 1783 } 1784 1785 static const TypeInfo arm_cpu_type_info = { 1786 .name = TYPE_ARM_CPU, 1787 .parent = TYPE_CPU, 1788 .instance_size = sizeof(ARMCPU), 1789 .instance_init = arm_cpu_initfn, 1790 .instance_post_init = arm_cpu_post_init, 1791 .instance_finalize = arm_cpu_finalizefn, 1792 .abstract = true, 1793 .class_size = sizeof(ARMCPUClass), 1794 .class_init = arm_cpu_class_init, 1795 }; 1796 1797 static void arm_cpu_register_types(void) 1798 { 1799 const ARMCPUInfo *info = arm_cpus; 1800 1801 type_register_static(&arm_cpu_type_info); 1802 1803 while (info->name) { 1804 cpu_register(info); 1805 info++; 1806 } 1807 } 1808 1809 type_init(arm_cpu_register_types) 1810