1 /* 2 * QEMU ARM CPU 3 * 4 * Copyright (c) 2012 SUSE LINUX Products GmbH 5 * 6 * This program is free software; you can redistribute it and/or 7 * modify it under the terms of the GNU General Public License 8 * as published by the Free Software Foundation; either version 2 9 * of the License, or (at your option) any later version. 10 * 11 * This program is distributed in the hope that it will be useful, 12 * but WITHOUT ANY WARRANTY; without even the implied warranty of 13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 14 * GNU General Public License for more details. 15 * 16 * You should have received a copy of the GNU General Public License 17 * along with this program; if not, see 18 * <http://www.gnu.org/licenses/gpl-2.0.html> 19 */ 20 21 #include "qemu/osdep.h" 22 #include "qemu/qemu-print.h" 23 #include "qemu/timer.h" 24 #include "qemu/log.h" 25 #include "exec/page-vary.h" 26 #include "target/arm/idau.h" 27 #include "qemu/module.h" 28 #include "qapi/error.h" 29 #include "cpu.h" 30 #ifdef CONFIG_TCG 31 #include "exec/translation-block.h" 32 #include "accel/tcg/cpu-ops.h" 33 #endif /* CONFIG_TCG */ 34 #include "internals.h" 35 #include "cpu-features.h" 36 #include "exec/exec-all.h" 37 #include "hw/qdev-properties.h" 38 #if !defined(CONFIG_USER_ONLY) 39 #include "hw/loader.h" 40 #include "hw/boards.h" 41 #ifdef CONFIG_TCG 42 #include "hw/intc/armv7m_nvic.h" 43 #endif /* CONFIG_TCG */ 44 #endif /* !CONFIG_USER_ONLY */ 45 #include "system/tcg.h" 46 #include "system/qtest.h" 47 #include "system/hw_accel.h" 48 #include "kvm_arm.h" 49 #include "disas/capstone.h" 50 #include "fpu/softfloat.h" 51 #include "cpregs.h" 52 #include "target/arm/cpu-qom.h" 53 #include "target/arm/gtimer.h" 54 55 static void arm_cpu_set_pc(CPUState *cs, vaddr value) 56 { 57 ARMCPU *cpu = ARM_CPU(cs); 58 CPUARMState *env = &cpu->env; 59 60 if (is_a64(env)) { 61 env->pc = value; 62 env->thumb = false; 63 } else { 64 env->regs[15] = value & ~1; 65 env->thumb = value & 1; 66 } 67 } 68 69 static vaddr arm_cpu_get_pc(CPUState *cs) 70 { 71 ARMCPU *cpu = ARM_CPU(cs); 72 CPUARMState *env = &cpu->env; 73 74 if (is_a64(env)) { 75 return env->pc; 76 } else { 77 return env->regs[15]; 78 } 79 } 80 81 #ifdef CONFIG_TCG 82 void arm_cpu_synchronize_from_tb(CPUState *cs, 83 const TranslationBlock *tb) 84 { 85 /* The program counter is always up to date with CF_PCREL. */ 86 if (!(tb_cflags(tb) & CF_PCREL)) { 87 CPUARMState *env = cpu_env(cs); 88 /* 89 * It's OK to look at env for the current mode here, because it's 90 * never possible for an AArch64 TB to chain to an AArch32 TB. 91 */ 92 if (is_a64(env)) { 93 env->pc = tb->pc; 94 } else { 95 env->regs[15] = tb->pc; 96 } 97 } 98 } 99 100 void arm_restore_state_to_opc(CPUState *cs, 101 const TranslationBlock *tb, 102 const uint64_t *data) 103 { 104 CPUARMState *env = cpu_env(cs); 105 106 if (is_a64(env)) { 107 if (tb_cflags(tb) & CF_PCREL) { 108 env->pc = (env->pc & TARGET_PAGE_MASK) | data[0]; 109 } else { 110 env->pc = data[0]; 111 } 112 env->condexec_bits = 0; 113 env->exception.syndrome = data[2] << ARM_INSN_START_WORD2_SHIFT; 114 } else { 115 if (tb_cflags(tb) & CF_PCREL) { 116 env->regs[15] = (env->regs[15] & TARGET_PAGE_MASK) | data[0]; 117 } else { 118 env->regs[15] = data[0]; 119 } 120 env->condexec_bits = data[1]; 121 env->exception.syndrome = data[2] << ARM_INSN_START_WORD2_SHIFT; 122 } 123 } 124 #endif /* CONFIG_TCG */ 125 126 /* 127 * With SCTLR_ELx.NMI == 0, IRQ with Superpriority is masked identically with 128 * IRQ without Superpriority. Moreover, if the GIC is configured so that 129 * FEAT_GICv3_NMI is only set if FEAT_NMI is set, then we won't ever see 130 * CPU_INTERRUPT_*NMI anyway. So we might as well accept NMI here 131 * unconditionally. 132 */ 133 static bool arm_cpu_has_work(CPUState *cs) 134 { 135 ARMCPU *cpu = ARM_CPU(cs); 136 137 return (cpu->power_state != PSCI_OFF) 138 && cs->interrupt_request & 139 (CPU_INTERRUPT_FIQ | CPU_INTERRUPT_HARD 140 | CPU_INTERRUPT_NMI | CPU_INTERRUPT_VINMI | CPU_INTERRUPT_VFNMI 141 | CPU_INTERRUPT_VFIQ | CPU_INTERRUPT_VIRQ | CPU_INTERRUPT_VSERR 142 | CPU_INTERRUPT_EXITTB); 143 } 144 145 static int arm_cpu_mmu_index(CPUState *cs, bool ifetch) 146 { 147 return arm_env_mmu_index(cpu_env(cs)); 148 } 149 150 void arm_register_pre_el_change_hook(ARMCPU *cpu, ARMELChangeHookFn *hook, 151 void *opaque) 152 { 153 ARMELChangeHook *entry = g_new0(ARMELChangeHook, 1); 154 155 entry->hook = hook; 156 entry->opaque = opaque; 157 158 QLIST_INSERT_HEAD(&cpu->pre_el_change_hooks, entry, node); 159 } 160 161 void arm_register_el_change_hook(ARMCPU *cpu, ARMELChangeHookFn *hook, 162 void *opaque) 163 { 164 ARMELChangeHook *entry = g_new0(ARMELChangeHook, 1); 165 166 entry->hook = hook; 167 entry->opaque = opaque; 168 169 QLIST_INSERT_HEAD(&cpu->el_change_hooks, entry, node); 170 } 171 172 static void cp_reg_reset(gpointer key, gpointer value, gpointer opaque) 173 { 174 /* Reset a single ARMCPRegInfo register */ 175 ARMCPRegInfo *ri = value; 176 ARMCPU *cpu = opaque; 177 178 if (ri->type & (ARM_CP_SPECIAL_MASK | ARM_CP_ALIAS)) { 179 return; 180 } 181 182 if (ri->resetfn) { 183 ri->resetfn(&cpu->env, ri); 184 return; 185 } 186 187 /* A zero offset is never possible as it would be regs[0] 188 * so we use it to indicate that reset is being handled elsewhere. 189 * This is basically only used for fields in non-core coprocessors 190 * (like the pxa2xx ones). 191 */ 192 if (!ri->fieldoffset) { 193 return; 194 } 195 196 if (cpreg_field_is_64bit(ri)) { 197 CPREG_FIELD64(&cpu->env, ri) = ri->resetvalue; 198 } else { 199 CPREG_FIELD32(&cpu->env, ri) = ri->resetvalue; 200 } 201 } 202 203 static void cp_reg_check_reset(gpointer key, gpointer value, gpointer opaque) 204 { 205 /* Purely an assertion check: we've already done reset once, 206 * so now check that running the reset for the cpreg doesn't 207 * change its value. This traps bugs where two different cpregs 208 * both try to reset the same state field but to different values. 209 */ 210 ARMCPRegInfo *ri = value; 211 ARMCPU *cpu = opaque; 212 uint64_t oldvalue, newvalue; 213 214 if (ri->type & (ARM_CP_SPECIAL_MASK | ARM_CP_ALIAS | ARM_CP_NO_RAW)) { 215 return; 216 } 217 218 oldvalue = read_raw_cp_reg(&cpu->env, ri); 219 cp_reg_reset(key, value, opaque); 220 newvalue = read_raw_cp_reg(&cpu->env, ri); 221 assert(oldvalue == newvalue); 222 } 223 224 static void arm_cpu_reset_hold(Object *obj, ResetType type) 225 { 226 CPUState *cs = CPU(obj); 227 ARMCPU *cpu = ARM_CPU(cs); 228 ARMCPUClass *acc = ARM_CPU_GET_CLASS(obj); 229 CPUARMState *env = &cpu->env; 230 231 if (acc->parent_phases.hold) { 232 acc->parent_phases.hold(obj, type); 233 } 234 235 memset(env, 0, offsetof(CPUARMState, end_reset_fields)); 236 237 g_hash_table_foreach(cpu->cp_regs, cp_reg_reset, cpu); 238 g_hash_table_foreach(cpu->cp_regs, cp_reg_check_reset, cpu); 239 240 env->vfp.xregs[ARM_VFP_FPSID] = cpu->reset_fpsid; 241 env->vfp.xregs[ARM_VFP_MVFR0] = cpu->isar.mvfr0; 242 env->vfp.xregs[ARM_VFP_MVFR1] = cpu->isar.mvfr1; 243 env->vfp.xregs[ARM_VFP_MVFR2] = cpu->isar.mvfr2; 244 245 cpu->power_state = cs->start_powered_off ? PSCI_OFF : PSCI_ON; 246 247 if (arm_feature(env, ARM_FEATURE_IWMMXT)) { 248 env->iwmmxt.cregs[ARM_IWMMXT_wCID] = 0x69051000 | 'Q'; 249 } 250 251 if (arm_feature(env, ARM_FEATURE_AARCH64)) { 252 /* 64 bit CPUs always start in 64 bit mode */ 253 env->aarch64 = true; 254 #if defined(CONFIG_USER_ONLY) 255 env->pstate = PSTATE_MODE_EL0t; 256 /* Userspace expects access to DC ZVA, CTL_EL0 and the cache ops */ 257 env->cp15.sctlr_el[1] |= SCTLR_UCT | SCTLR_UCI | SCTLR_DZE; 258 /* Enable all PAC keys. */ 259 env->cp15.sctlr_el[1] |= (SCTLR_EnIA | SCTLR_EnIB | 260 SCTLR_EnDA | SCTLR_EnDB); 261 /* Trap on btype=3 for PACIxSP. */ 262 env->cp15.sctlr_el[1] |= SCTLR_BT0; 263 /* Trap on implementation defined registers. */ 264 if (cpu_isar_feature(aa64_tidcp1, cpu)) { 265 env->cp15.sctlr_el[1] |= SCTLR_TIDCP; 266 } 267 /* and to the FP/Neon instructions */ 268 env->cp15.cpacr_el1 = FIELD_DP64(env->cp15.cpacr_el1, 269 CPACR_EL1, FPEN, 3); 270 /* and to the SVE instructions, with default vector length */ 271 if (cpu_isar_feature(aa64_sve, cpu)) { 272 env->cp15.cpacr_el1 = FIELD_DP64(env->cp15.cpacr_el1, 273 CPACR_EL1, ZEN, 3); 274 env->vfp.zcr_el[1] = cpu->sve_default_vq - 1; 275 } 276 /* and for SME instructions, with default vector length, and TPIDR2 */ 277 if (cpu_isar_feature(aa64_sme, cpu)) { 278 env->cp15.sctlr_el[1] |= SCTLR_EnTP2; 279 env->cp15.cpacr_el1 = FIELD_DP64(env->cp15.cpacr_el1, 280 CPACR_EL1, SMEN, 3); 281 env->vfp.smcr_el[1] = cpu->sme_default_vq - 1; 282 if (cpu_isar_feature(aa64_sme_fa64, cpu)) { 283 env->vfp.smcr_el[1] = FIELD_DP64(env->vfp.smcr_el[1], 284 SMCR, FA64, 1); 285 } 286 } 287 /* 288 * Enable 48-bit address space (TODO: take reserved_va into account). 289 * Enable TBI0 but not TBI1. 290 * Note that this must match useronly_clean_ptr. 291 */ 292 env->cp15.tcr_el[1] = 5 | (1ULL << 37); 293 294 /* Enable MTE */ 295 if (cpu_isar_feature(aa64_mte, cpu)) { 296 /* Enable tag access, but leave TCF0 as No Effect (0). */ 297 env->cp15.sctlr_el[1] |= SCTLR_ATA0; 298 /* 299 * Exclude all tags, so that tag 0 is always used. 300 * This corresponds to Linux current->thread.gcr_incl = 0. 301 * 302 * Set RRND, so that helper_irg() will generate a seed later. 303 * Here in cpu_reset(), the crypto subsystem has not yet been 304 * initialized. 305 */ 306 env->cp15.gcr_el1 = 0x1ffff; 307 } 308 /* 309 * Disable access to SCXTNUM_EL0 from CSV2_1p2. 310 * This is not yet exposed from the Linux kernel in any way. 311 */ 312 env->cp15.sctlr_el[1] |= SCTLR_TSCXT; 313 /* Disable access to Debug Communication Channel (DCC). */ 314 env->cp15.mdscr_el1 |= 1 << 12; 315 /* Enable FEAT_MOPS */ 316 env->cp15.sctlr_el[1] |= SCTLR_MSCEN; 317 #else 318 /* Reset into the highest available EL */ 319 if (arm_feature(env, ARM_FEATURE_EL3)) { 320 env->pstate = PSTATE_MODE_EL3h; 321 } else if (arm_feature(env, ARM_FEATURE_EL2)) { 322 env->pstate = PSTATE_MODE_EL2h; 323 } else { 324 env->pstate = PSTATE_MODE_EL1h; 325 } 326 327 /* Sample rvbar at reset. */ 328 env->cp15.rvbar = cpu->rvbar_prop; 329 env->pc = env->cp15.rvbar; 330 #endif 331 } else { 332 #if defined(CONFIG_USER_ONLY) 333 /* Userspace expects access to cp10 and cp11 for FP/Neon */ 334 env->cp15.cpacr_el1 = FIELD_DP64(env->cp15.cpacr_el1, 335 CPACR, CP10, 3); 336 env->cp15.cpacr_el1 = FIELD_DP64(env->cp15.cpacr_el1, 337 CPACR, CP11, 3); 338 #endif 339 if (arm_feature(env, ARM_FEATURE_V8)) { 340 env->cp15.rvbar = cpu->rvbar_prop; 341 env->regs[15] = cpu->rvbar_prop; 342 } 343 } 344 345 #if defined(CONFIG_USER_ONLY) 346 env->uncached_cpsr = ARM_CPU_MODE_USR; 347 /* For user mode we must enable access to coprocessors */ 348 env->vfp.xregs[ARM_VFP_FPEXC] = 1 << 30; 349 if (arm_feature(env, ARM_FEATURE_IWMMXT)) { 350 env->cp15.c15_cpar = 3; 351 } else if (arm_feature(env, ARM_FEATURE_XSCALE)) { 352 env->cp15.c15_cpar = 1; 353 } 354 #else 355 356 /* 357 * If the highest available EL is EL2, AArch32 will start in Hyp 358 * mode; otherwise it starts in SVC. Note that if we start in 359 * AArch64 then these values in the uncached_cpsr will be ignored. 360 */ 361 if (arm_feature(env, ARM_FEATURE_EL2) && 362 !arm_feature(env, ARM_FEATURE_EL3)) { 363 env->uncached_cpsr = ARM_CPU_MODE_HYP; 364 } else { 365 env->uncached_cpsr = ARM_CPU_MODE_SVC; 366 } 367 env->daif = PSTATE_D | PSTATE_A | PSTATE_I | PSTATE_F; 368 369 /* AArch32 has a hard highvec setting of 0xFFFF0000. If we are currently 370 * executing as AArch32 then check if highvecs are enabled and 371 * adjust the PC accordingly. 372 */ 373 if (A32_BANKED_CURRENT_REG_GET(env, sctlr) & SCTLR_V) { 374 env->regs[15] = 0xFFFF0000; 375 } 376 377 env->vfp.xregs[ARM_VFP_FPEXC] = 0; 378 #endif 379 380 if (arm_feature(env, ARM_FEATURE_M)) { 381 #ifndef CONFIG_USER_ONLY 382 uint32_t initial_msp; /* Loaded from 0x0 */ 383 uint32_t initial_pc; /* Loaded from 0x4 */ 384 uint8_t *rom; 385 uint32_t vecbase; 386 #endif 387 388 if (cpu_isar_feature(aa32_lob, cpu)) { 389 /* 390 * LTPSIZE is constant 4 if MVE not implemented, and resets 391 * to an UNKNOWN value if MVE is implemented. We choose to 392 * always reset to 4. 393 */ 394 env->v7m.ltpsize = 4; 395 /* The LTPSIZE field in FPDSCR is constant and reads as 4. */ 396 env->v7m.fpdscr[M_REG_NS] = 4 << FPCR_LTPSIZE_SHIFT; 397 env->v7m.fpdscr[M_REG_S] = 4 << FPCR_LTPSIZE_SHIFT; 398 } 399 400 if (arm_feature(env, ARM_FEATURE_M_SECURITY)) { 401 env->v7m.secure = true; 402 } else { 403 /* This bit resets to 0 if security is supported, but 1 if 404 * it is not. The bit is not present in v7M, but we set it 405 * here so we can avoid having to make checks on it conditional 406 * on ARM_FEATURE_V8 (we don't let the guest see the bit). 407 */ 408 env->v7m.aircr = R_V7M_AIRCR_BFHFNMINS_MASK; 409 /* 410 * Set NSACR to indicate "NS access permitted to everything"; 411 * this avoids having to have all the tests of it being 412 * conditional on ARM_FEATURE_M_SECURITY. Note also that from 413 * v8.1M the guest-visible value of NSACR in a CPU without the 414 * Security Extension is 0xcff. 415 */ 416 env->v7m.nsacr = 0xcff; 417 } 418 419 /* In v7M the reset value of this bit is IMPDEF, but ARM recommends 420 * that it resets to 1, so QEMU always does that rather than making 421 * it dependent on CPU model. In v8M it is RES1. 422 */ 423 env->v7m.ccr[M_REG_NS] = R_V7M_CCR_STKALIGN_MASK; 424 env->v7m.ccr[M_REG_S] = R_V7M_CCR_STKALIGN_MASK; 425 if (arm_feature(env, ARM_FEATURE_V8)) { 426 /* in v8M the NONBASETHRDENA bit [0] is RES1 */ 427 env->v7m.ccr[M_REG_NS] |= R_V7M_CCR_NONBASETHRDENA_MASK; 428 env->v7m.ccr[M_REG_S] |= R_V7M_CCR_NONBASETHRDENA_MASK; 429 } 430 if (!arm_feature(env, ARM_FEATURE_M_MAIN)) { 431 env->v7m.ccr[M_REG_NS] |= R_V7M_CCR_UNALIGN_TRP_MASK; 432 env->v7m.ccr[M_REG_S] |= R_V7M_CCR_UNALIGN_TRP_MASK; 433 } 434 435 if (cpu_isar_feature(aa32_vfp_simd, cpu)) { 436 env->v7m.fpccr[M_REG_NS] = R_V7M_FPCCR_ASPEN_MASK; 437 env->v7m.fpccr[M_REG_S] = R_V7M_FPCCR_ASPEN_MASK | 438 R_V7M_FPCCR_LSPEN_MASK | R_V7M_FPCCR_S_MASK; 439 } 440 441 #ifndef CONFIG_USER_ONLY 442 /* Unlike A/R profile, M profile defines the reset LR value */ 443 env->regs[14] = 0xffffffff; 444 445 env->v7m.vecbase[M_REG_S] = cpu->init_svtor & 0xffffff80; 446 env->v7m.vecbase[M_REG_NS] = cpu->init_nsvtor & 0xffffff80; 447 448 /* Load the initial SP and PC from offset 0 and 4 in the vector table */ 449 vecbase = env->v7m.vecbase[env->v7m.secure]; 450 rom = rom_ptr_for_as(cs->as, vecbase, 8); 451 if (rom) { 452 /* Address zero is covered by ROM which hasn't yet been 453 * copied into physical memory. 454 */ 455 initial_msp = ldl_p(rom); 456 initial_pc = ldl_p(rom + 4); 457 } else { 458 /* Address zero not covered by a ROM blob, or the ROM blob 459 * is in non-modifiable memory and this is a second reset after 460 * it got copied into memory. In the latter case, rom_ptr 461 * will return a NULL pointer and we should use ldl_phys instead. 462 */ 463 initial_msp = ldl_phys(cs->as, vecbase); 464 initial_pc = ldl_phys(cs->as, vecbase + 4); 465 } 466 467 qemu_log_mask(CPU_LOG_INT, 468 "Loaded reset SP 0x%x PC 0x%x from vector table\n", 469 initial_msp, initial_pc); 470 471 env->regs[13] = initial_msp & 0xFFFFFFFC; 472 env->regs[15] = initial_pc & ~1; 473 env->thumb = initial_pc & 1; 474 #else 475 /* 476 * For user mode we run non-secure and with access to the FPU. 477 * The FPU context is active (ie does not need further setup) 478 * and is owned by non-secure. 479 */ 480 env->v7m.secure = false; 481 env->v7m.nsacr = 0xcff; 482 env->v7m.cpacr[M_REG_NS] = 0xf0ffff; 483 env->v7m.fpccr[M_REG_S] &= 484 ~(R_V7M_FPCCR_LSPEN_MASK | R_V7M_FPCCR_S_MASK); 485 env->v7m.control[M_REG_S] |= R_V7M_CONTROL_FPCA_MASK; 486 #endif 487 } 488 489 /* M profile requires that reset clears the exclusive monitor; 490 * A profile does not, but clearing it makes more sense than having it 491 * set with an exclusive access on address zero. 492 */ 493 arm_clear_exclusive(env); 494 495 if (arm_feature(env, ARM_FEATURE_PMSA)) { 496 if (cpu->pmsav7_dregion > 0) { 497 if (arm_feature(env, ARM_FEATURE_V8)) { 498 memset(env->pmsav8.rbar[M_REG_NS], 0, 499 sizeof(*env->pmsav8.rbar[M_REG_NS]) 500 * cpu->pmsav7_dregion); 501 memset(env->pmsav8.rlar[M_REG_NS], 0, 502 sizeof(*env->pmsav8.rlar[M_REG_NS]) 503 * cpu->pmsav7_dregion); 504 if (arm_feature(env, ARM_FEATURE_M_SECURITY)) { 505 memset(env->pmsav8.rbar[M_REG_S], 0, 506 sizeof(*env->pmsav8.rbar[M_REG_S]) 507 * cpu->pmsav7_dregion); 508 memset(env->pmsav8.rlar[M_REG_S], 0, 509 sizeof(*env->pmsav8.rlar[M_REG_S]) 510 * cpu->pmsav7_dregion); 511 } 512 } else if (arm_feature(env, ARM_FEATURE_V7)) { 513 memset(env->pmsav7.drbar, 0, 514 sizeof(*env->pmsav7.drbar) * cpu->pmsav7_dregion); 515 memset(env->pmsav7.drsr, 0, 516 sizeof(*env->pmsav7.drsr) * cpu->pmsav7_dregion); 517 memset(env->pmsav7.dracr, 0, 518 sizeof(*env->pmsav7.dracr) * cpu->pmsav7_dregion); 519 } 520 } 521 522 if (cpu->pmsav8r_hdregion > 0) { 523 memset(env->pmsav8.hprbar, 0, 524 sizeof(*env->pmsav8.hprbar) * cpu->pmsav8r_hdregion); 525 memset(env->pmsav8.hprlar, 0, 526 sizeof(*env->pmsav8.hprlar) * cpu->pmsav8r_hdregion); 527 } 528 529 env->pmsav7.rnr[M_REG_NS] = 0; 530 env->pmsav7.rnr[M_REG_S] = 0; 531 env->pmsav8.mair0[M_REG_NS] = 0; 532 env->pmsav8.mair0[M_REG_S] = 0; 533 env->pmsav8.mair1[M_REG_NS] = 0; 534 env->pmsav8.mair1[M_REG_S] = 0; 535 } 536 537 if (arm_feature(env, ARM_FEATURE_M_SECURITY)) { 538 if (cpu->sau_sregion > 0) { 539 memset(env->sau.rbar, 0, sizeof(*env->sau.rbar) * cpu->sau_sregion); 540 memset(env->sau.rlar, 0, sizeof(*env->sau.rlar) * cpu->sau_sregion); 541 } 542 env->sau.rnr = 0; 543 /* SAU_CTRL reset value is IMPDEF; we choose 0, which is what 544 * the Cortex-M33 does. 545 */ 546 env->sau.ctrl = 0; 547 } 548 549 set_flush_to_zero(1, &env->vfp.fp_status[FPST_STD]); 550 set_flush_inputs_to_zero(1, &env->vfp.fp_status[FPST_STD]); 551 set_default_nan_mode(1, &env->vfp.fp_status[FPST_STD]); 552 set_default_nan_mode(1, &env->vfp.fp_status[FPST_STD_F16]); 553 arm_set_default_fp_behaviours(&env->vfp.fp_status[FPST_A32]); 554 arm_set_default_fp_behaviours(&env->vfp.fp_status[FPST_A64]); 555 arm_set_default_fp_behaviours(&env->vfp.fp_status[FPST_STD]); 556 arm_set_default_fp_behaviours(&env->vfp.fp_status[FPST_A32_F16]); 557 arm_set_default_fp_behaviours(&env->vfp.fp_status[FPST_A64_F16]); 558 arm_set_default_fp_behaviours(&env->vfp.fp_status[FPST_STD_F16]); 559 arm_set_ah_fp_behaviours(&env->vfp.fp_status[FPST_AH]); 560 set_flush_to_zero(1, &env->vfp.fp_status[FPST_AH]); 561 set_flush_inputs_to_zero(1, &env->vfp.fp_status[FPST_AH]); 562 arm_set_ah_fp_behaviours(&env->vfp.fp_status[FPST_AH_F16]); 563 564 #ifndef CONFIG_USER_ONLY 565 if (kvm_enabled()) { 566 kvm_arm_reset_vcpu(cpu); 567 } 568 #endif 569 570 if (tcg_enabled()) { 571 hw_breakpoint_update_all(cpu); 572 hw_watchpoint_update_all(cpu); 573 574 arm_rebuild_hflags(env); 575 } 576 } 577 578 void arm_emulate_firmware_reset(CPUState *cpustate, int target_el) 579 { 580 ARMCPU *cpu = ARM_CPU(cpustate); 581 CPUARMState *env = &cpu->env; 582 bool have_el3 = arm_feature(env, ARM_FEATURE_EL3); 583 bool have_el2 = arm_feature(env, ARM_FEATURE_EL2); 584 585 /* 586 * Check we have the EL we're aiming for. If that is the 587 * highest implemented EL, then cpu_reset has already done 588 * all the work. 589 */ 590 switch (target_el) { 591 case 3: 592 assert(have_el3); 593 return; 594 case 2: 595 assert(have_el2); 596 if (!have_el3) { 597 return; 598 } 599 break; 600 case 1: 601 if (!have_el3 && !have_el2) { 602 return; 603 } 604 break; 605 default: 606 g_assert_not_reached(); 607 } 608 609 if (have_el3) { 610 /* 611 * Set the EL3 state so code can run at EL2. This should match 612 * the requirements set by Linux in its booting spec. 613 */ 614 if (env->aarch64) { 615 env->cp15.scr_el3 |= SCR_RW; 616 if (cpu_isar_feature(aa64_pauth, cpu)) { 617 env->cp15.scr_el3 |= SCR_API | SCR_APK; 618 } 619 if (cpu_isar_feature(aa64_mte, cpu)) { 620 env->cp15.scr_el3 |= SCR_ATA; 621 } 622 if (cpu_isar_feature(aa64_sve, cpu)) { 623 env->cp15.cptr_el[3] |= R_CPTR_EL3_EZ_MASK; 624 env->vfp.zcr_el[3] = 0xf; 625 } 626 if (cpu_isar_feature(aa64_sme, cpu)) { 627 env->cp15.cptr_el[3] |= R_CPTR_EL3_ESM_MASK; 628 env->cp15.scr_el3 |= SCR_ENTP2; 629 env->vfp.smcr_el[3] = 0xf; 630 } 631 if (cpu_isar_feature(aa64_hcx, cpu)) { 632 env->cp15.scr_el3 |= SCR_HXEN; 633 } 634 if (cpu_isar_feature(aa64_fgt, cpu)) { 635 env->cp15.scr_el3 |= SCR_FGTEN; 636 } 637 } 638 639 if (target_el == 2) { 640 /* If the guest is at EL2 then Linux expects the HVC insn to work */ 641 env->cp15.scr_el3 |= SCR_HCE; 642 } 643 644 /* Put CPU into non-secure state */ 645 env->cp15.scr_el3 |= SCR_NS; 646 /* Set NSACR.{CP11,CP10} so NS can access the FPU */ 647 env->cp15.nsacr |= 3 << 10; 648 } 649 650 if (have_el2 && target_el < 2) { 651 /* Set EL2 state so code can run at EL1. */ 652 if (env->aarch64) { 653 env->cp15.hcr_el2 |= HCR_RW; 654 } 655 } 656 657 /* Set the CPU to the desired state */ 658 if (env->aarch64) { 659 env->pstate = aarch64_pstate_mode(target_el, true); 660 } else { 661 static const uint32_t mode_for_el[] = { 662 0, 663 ARM_CPU_MODE_SVC, 664 ARM_CPU_MODE_HYP, 665 ARM_CPU_MODE_SVC, 666 }; 667 668 cpsr_write(env, mode_for_el[target_el], CPSR_M, CPSRWriteRaw); 669 } 670 } 671 672 673 #if defined(CONFIG_TCG) && !defined(CONFIG_USER_ONLY) 674 675 static inline bool arm_excp_unmasked(CPUState *cs, unsigned int excp_idx, 676 unsigned int target_el, 677 unsigned int cur_el, bool secure, 678 uint64_t hcr_el2) 679 { 680 CPUARMState *env = cpu_env(cs); 681 bool pstate_unmasked; 682 bool unmasked = false; 683 bool allIntMask = false; 684 685 /* 686 * Don't take exceptions if they target a lower EL. 687 * This check should catch any exceptions that would not be taken 688 * but left pending. 689 */ 690 if (cur_el > target_el) { 691 return false; 692 } 693 694 if (cpu_isar_feature(aa64_nmi, env_archcpu(env)) && 695 env->cp15.sctlr_el[target_el] & SCTLR_NMI && cur_el == target_el) { 696 allIntMask = env->pstate & PSTATE_ALLINT || 697 ((env->cp15.sctlr_el[target_el] & SCTLR_SPINTMASK) && 698 (env->pstate & PSTATE_SP)); 699 } 700 701 switch (excp_idx) { 702 case EXCP_NMI: 703 pstate_unmasked = !allIntMask; 704 break; 705 706 case EXCP_VINMI: 707 if (!(hcr_el2 & HCR_IMO) || (hcr_el2 & HCR_TGE)) { 708 /* VINMIs are only taken when hypervized. */ 709 return false; 710 } 711 return !allIntMask; 712 case EXCP_VFNMI: 713 if (!(hcr_el2 & HCR_FMO) || (hcr_el2 & HCR_TGE)) { 714 /* VFNMIs are only taken when hypervized. */ 715 return false; 716 } 717 return !allIntMask; 718 case EXCP_FIQ: 719 pstate_unmasked = (!(env->daif & PSTATE_F)) && (!allIntMask); 720 break; 721 722 case EXCP_IRQ: 723 pstate_unmasked = (!(env->daif & PSTATE_I)) && (!allIntMask); 724 break; 725 726 case EXCP_VFIQ: 727 if (!(hcr_el2 & HCR_FMO) || (hcr_el2 & HCR_TGE)) { 728 /* VFIQs are only taken when hypervized. */ 729 return false; 730 } 731 return !(env->daif & PSTATE_F) && (!allIntMask); 732 case EXCP_VIRQ: 733 if (!(hcr_el2 & HCR_IMO) || (hcr_el2 & HCR_TGE)) { 734 /* VIRQs are only taken when hypervized. */ 735 return false; 736 } 737 return !(env->daif & PSTATE_I) && (!allIntMask); 738 case EXCP_VSERR: 739 if (!(hcr_el2 & HCR_AMO) || (hcr_el2 & HCR_TGE)) { 740 /* VIRQs are only taken when hypervized. */ 741 return false; 742 } 743 return !(env->daif & PSTATE_A); 744 default: 745 g_assert_not_reached(); 746 } 747 748 /* 749 * Use the target EL, current execution state and SCR/HCR settings to 750 * determine whether the corresponding CPSR bit is used to mask the 751 * interrupt. 752 */ 753 if ((target_el > cur_el) && (target_el != 1)) { 754 /* Exceptions targeting a higher EL may not be maskable */ 755 if (arm_feature(env, ARM_FEATURE_AARCH64)) { 756 switch (target_el) { 757 case 2: 758 /* 759 * According to ARM DDI 0487H.a, an interrupt can be masked 760 * when HCR_E2H and HCR_TGE are both set regardless of the 761 * current Security state. Note that we need to revisit this 762 * part again once we need to support NMI. 763 */ 764 if ((hcr_el2 & (HCR_E2H | HCR_TGE)) != (HCR_E2H | HCR_TGE)) { 765 unmasked = true; 766 } 767 break; 768 case 3: 769 /* Interrupt cannot be masked when the target EL is 3 */ 770 unmasked = true; 771 break; 772 default: 773 g_assert_not_reached(); 774 } 775 } else { 776 /* 777 * The old 32-bit-only environment has a more complicated 778 * masking setup. HCR and SCR bits not only affect interrupt 779 * routing but also change the behaviour of masking. 780 */ 781 bool hcr, scr; 782 783 switch (excp_idx) { 784 case EXCP_FIQ: 785 /* 786 * If FIQs are routed to EL3 or EL2 then there are cases where 787 * we override the CPSR.F in determining if the exception is 788 * masked or not. If neither of these are set then we fall back 789 * to the CPSR.F setting otherwise we further assess the state 790 * below. 791 */ 792 hcr = hcr_el2 & HCR_FMO; 793 scr = (env->cp15.scr_el3 & SCR_FIQ); 794 795 /* 796 * When EL3 is 32-bit, the SCR.FW bit controls whether the 797 * CPSR.F bit masks FIQ interrupts when taken in non-secure 798 * state. If SCR.FW is set then FIQs can be masked by CPSR.F 799 * when non-secure but only when FIQs are only routed to EL3. 800 */ 801 scr = scr && !((env->cp15.scr_el3 & SCR_FW) && !hcr); 802 break; 803 case EXCP_IRQ: 804 /* 805 * When EL3 execution state is 32-bit, if HCR.IMO is set then 806 * we may override the CPSR.I masking when in non-secure state. 807 * The SCR.IRQ setting has already been taken into consideration 808 * when setting the target EL, so it does not have a further 809 * affect here. 810 */ 811 hcr = hcr_el2 & HCR_IMO; 812 scr = false; 813 break; 814 default: 815 g_assert_not_reached(); 816 } 817 818 if ((scr || hcr) && !secure) { 819 unmasked = true; 820 } 821 } 822 } 823 824 /* 825 * The PSTATE bits only mask the interrupt if we have not overridden the 826 * ability above. 827 */ 828 return unmasked || pstate_unmasked; 829 } 830 831 static bool arm_cpu_exec_interrupt(CPUState *cs, int interrupt_request) 832 { 833 CPUARMState *env = cpu_env(cs); 834 uint32_t cur_el = arm_current_el(env); 835 bool secure = arm_is_secure(env); 836 uint64_t hcr_el2 = arm_hcr_el2_eff(env); 837 uint32_t target_el; 838 uint32_t excp_idx; 839 840 /* The prioritization of interrupts is IMPLEMENTATION DEFINED. */ 841 842 if (cpu_isar_feature(aa64_nmi, env_archcpu(env)) && 843 (arm_sctlr(env, cur_el) & SCTLR_NMI)) { 844 if (interrupt_request & CPU_INTERRUPT_NMI) { 845 excp_idx = EXCP_NMI; 846 target_el = arm_phys_excp_target_el(cs, excp_idx, cur_el, secure); 847 if (arm_excp_unmasked(cs, excp_idx, target_el, 848 cur_el, secure, hcr_el2)) { 849 goto found; 850 } 851 } 852 if (interrupt_request & CPU_INTERRUPT_VINMI) { 853 excp_idx = EXCP_VINMI; 854 target_el = 1; 855 if (arm_excp_unmasked(cs, excp_idx, target_el, 856 cur_el, secure, hcr_el2)) { 857 goto found; 858 } 859 } 860 if (interrupt_request & CPU_INTERRUPT_VFNMI) { 861 excp_idx = EXCP_VFNMI; 862 target_el = 1; 863 if (arm_excp_unmasked(cs, excp_idx, target_el, 864 cur_el, secure, hcr_el2)) { 865 goto found; 866 } 867 } 868 } else { 869 /* 870 * NMI disabled: interrupts with superpriority are handled 871 * as if they didn't have it 872 */ 873 if (interrupt_request & CPU_INTERRUPT_NMI) { 874 interrupt_request |= CPU_INTERRUPT_HARD; 875 } 876 if (interrupt_request & CPU_INTERRUPT_VINMI) { 877 interrupt_request |= CPU_INTERRUPT_VIRQ; 878 } 879 if (interrupt_request & CPU_INTERRUPT_VFNMI) { 880 interrupt_request |= CPU_INTERRUPT_VFIQ; 881 } 882 } 883 884 if (interrupt_request & CPU_INTERRUPT_FIQ) { 885 excp_idx = EXCP_FIQ; 886 target_el = arm_phys_excp_target_el(cs, excp_idx, cur_el, secure); 887 if (arm_excp_unmasked(cs, excp_idx, target_el, 888 cur_el, secure, hcr_el2)) { 889 goto found; 890 } 891 } 892 if (interrupt_request & CPU_INTERRUPT_HARD) { 893 excp_idx = EXCP_IRQ; 894 target_el = arm_phys_excp_target_el(cs, excp_idx, cur_el, secure); 895 if (arm_excp_unmasked(cs, excp_idx, target_el, 896 cur_el, secure, hcr_el2)) { 897 goto found; 898 } 899 } 900 if (interrupt_request & CPU_INTERRUPT_VIRQ) { 901 excp_idx = EXCP_VIRQ; 902 target_el = 1; 903 if (arm_excp_unmasked(cs, excp_idx, target_el, 904 cur_el, secure, hcr_el2)) { 905 goto found; 906 } 907 } 908 if (interrupt_request & CPU_INTERRUPT_VFIQ) { 909 excp_idx = EXCP_VFIQ; 910 target_el = 1; 911 if (arm_excp_unmasked(cs, excp_idx, target_el, 912 cur_el, secure, hcr_el2)) { 913 goto found; 914 } 915 } 916 if (interrupt_request & CPU_INTERRUPT_VSERR) { 917 excp_idx = EXCP_VSERR; 918 target_el = 1; 919 if (arm_excp_unmasked(cs, excp_idx, target_el, 920 cur_el, secure, hcr_el2)) { 921 /* Taking a virtual abort clears HCR_EL2.VSE */ 922 env->cp15.hcr_el2 &= ~HCR_VSE; 923 cpu_reset_interrupt(cs, CPU_INTERRUPT_VSERR); 924 goto found; 925 } 926 } 927 return false; 928 929 found: 930 cs->exception_index = excp_idx; 931 env->exception.target_el = target_el; 932 cs->cc->tcg_ops->do_interrupt(cs); 933 return true; 934 } 935 936 #endif /* CONFIG_TCG && !CONFIG_USER_ONLY */ 937 938 void arm_cpu_update_virq(ARMCPU *cpu) 939 { 940 /* 941 * Update the interrupt level for VIRQ, which is the logical OR of 942 * the HCR_EL2.VI bit and the input line level from the GIC. 943 */ 944 CPUARMState *env = &cpu->env; 945 CPUState *cs = CPU(cpu); 946 947 bool new_state = ((arm_hcr_el2_eff(env) & HCR_VI) && 948 !(arm_hcrx_el2_eff(env) & HCRX_VINMI)) || 949 (env->irq_line_state & CPU_INTERRUPT_VIRQ); 950 951 if (new_state != ((cs->interrupt_request & CPU_INTERRUPT_VIRQ) != 0)) { 952 if (new_state) { 953 cpu_interrupt(cs, CPU_INTERRUPT_VIRQ); 954 } else { 955 cpu_reset_interrupt(cs, CPU_INTERRUPT_VIRQ); 956 } 957 } 958 } 959 960 void arm_cpu_update_vfiq(ARMCPU *cpu) 961 { 962 /* 963 * Update the interrupt level for VFIQ, which is the logical OR of 964 * the HCR_EL2.VF bit and the input line level from the GIC. 965 */ 966 CPUARMState *env = &cpu->env; 967 CPUState *cs = CPU(cpu); 968 969 bool new_state = ((arm_hcr_el2_eff(env) & HCR_VF) && 970 !(arm_hcrx_el2_eff(env) & HCRX_VFNMI)) || 971 (env->irq_line_state & CPU_INTERRUPT_VFIQ); 972 973 if (new_state != ((cs->interrupt_request & CPU_INTERRUPT_VFIQ) != 0)) { 974 if (new_state) { 975 cpu_interrupt(cs, CPU_INTERRUPT_VFIQ); 976 } else { 977 cpu_reset_interrupt(cs, CPU_INTERRUPT_VFIQ); 978 } 979 } 980 } 981 982 void arm_cpu_update_vinmi(ARMCPU *cpu) 983 { 984 /* 985 * Update the interrupt level for VINMI, which is the logical OR of 986 * the HCRX_EL2.VINMI bit and the input line level from the GIC. 987 */ 988 CPUARMState *env = &cpu->env; 989 CPUState *cs = CPU(cpu); 990 991 bool new_state = ((arm_hcr_el2_eff(env) & HCR_VI) && 992 (arm_hcrx_el2_eff(env) & HCRX_VINMI)) || 993 (env->irq_line_state & CPU_INTERRUPT_VINMI); 994 995 if (new_state != ((cs->interrupt_request & CPU_INTERRUPT_VINMI) != 0)) { 996 if (new_state) { 997 cpu_interrupt(cs, CPU_INTERRUPT_VINMI); 998 } else { 999 cpu_reset_interrupt(cs, CPU_INTERRUPT_VINMI); 1000 } 1001 } 1002 } 1003 1004 void arm_cpu_update_vfnmi(ARMCPU *cpu) 1005 { 1006 /* 1007 * Update the interrupt level for VFNMI, which is the HCRX_EL2.VFNMI bit. 1008 */ 1009 CPUARMState *env = &cpu->env; 1010 CPUState *cs = CPU(cpu); 1011 1012 bool new_state = (arm_hcr_el2_eff(env) & HCR_VF) && 1013 (arm_hcrx_el2_eff(env) & HCRX_VFNMI); 1014 1015 if (new_state != ((cs->interrupt_request & CPU_INTERRUPT_VFNMI) != 0)) { 1016 if (new_state) { 1017 cpu_interrupt(cs, CPU_INTERRUPT_VFNMI); 1018 } else { 1019 cpu_reset_interrupt(cs, CPU_INTERRUPT_VFNMI); 1020 } 1021 } 1022 } 1023 1024 void arm_cpu_update_vserr(ARMCPU *cpu) 1025 { 1026 /* 1027 * Update the interrupt level for VSERR, which is the HCR_EL2.VSE bit. 1028 */ 1029 CPUARMState *env = &cpu->env; 1030 CPUState *cs = CPU(cpu); 1031 1032 bool new_state = env->cp15.hcr_el2 & HCR_VSE; 1033 1034 if (new_state != ((cs->interrupt_request & CPU_INTERRUPT_VSERR) != 0)) { 1035 if (new_state) { 1036 cpu_interrupt(cs, CPU_INTERRUPT_VSERR); 1037 } else { 1038 cpu_reset_interrupt(cs, CPU_INTERRUPT_VSERR); 1039 } 1040 } 1041 } 1042 1043 #ifndef CONFIG_USER_ONLY 1044 static void arm_cpu_set_irq(void *opaque, int irq, int level) 1045 { 1046 ARMCPU *cpu = opaque; 1047 CPUARMState *env = &cpu->env; 1048 CPUState *cs = CPU(cpu); 1049 static const int mask[] = { 1050 [ARM_CPU_IRQ] = CPU_INTERRUPT_HARD, 1051 [ARM_CPU_FIQ] = CPU_INTERRUPT_FIQ, 1052 [ARM_CPU_VIRQ] = CPU_INTERRUPT_VIRQ, 1053 [ARM_CPU_VFIQ] = CPU_INTERRUPT_VFIQ, 1054 [ARM_CPU_NMI] = CPU_INTERRUPT_NMI, 1055 [ARM_CPU_VINMI] = CPU_INTERRUPT_VINMI, 1056 }; 1057 1058 if (!arm_feature(env, ARM_FEATURE_EL2) && 1059 (irq == ARM_CPU_VIRQ || irq == ARM_CPU_VFIQ)) { 1060 /* 1061 * The GIC might tell us about VIRQ and VFIQ state, but if we don't 1062 * have EL2 support we don't care. (Unless the guest is doing something 1063 * silly this will only be calls saying "level is still 0".) 1064 */ 1065 return; 1066 } 1067 1068 if (level) { 1069 env->irq_line_state |= mask[irq]; 1070 } else { 1071 env->irq_line_state &= ~mask[irq]; 1072 } 1073 1074 switch (irq) { 1075 case ARM_CPU_VIRQ: 1076 arm_cpu_update_virq(cpu); 1077 break; 1078 case ARM_CPU_VFIQ: 1079 arm_cpu_update_vfiq(cpu); 1080 break; 1081 case ARM_CPU_VINMI: 1082 arm_cpu_update_vinmi(cpu); 1083 break; 1084 case ARM_CPU_IRQ: 1085 case ARM_CPU_FIQ: 1086 case ARM_CPU_NMI: 1087 if (level) { 1088 cpu_interrupt(cs, mask[irq]); 1089 } else { 1090 cpu_reset_interrupt(cs, mask[irq]); 1091 } 1092 break; 1093 default: 1094 g_assert_not_reached(); 1095 } 1096 } 1097 1098 static void arm_cpu_kvm_set_irq(void *opaque, int irq, int level) 1099 { 1100 #ifdef CONFIG_KVM 1101 ARMCPU *cpu = opaque; 1102 CPUARMState *env = &cpu->env; 1103 CPUState *cs = CPU(cpu); 1104 uint32_t linestate_bit; 1105 int irq_id; 1106 1107 switch (irq) { 1108 case ARM_CPU_IRQ: 1109 irq_id = KVM_ARM_IRQ_CPU_IRQ; 1110 linestate_bit = CPU_INTERRUPT_HARD; 1111 break; 1112 case ARM_CPU_FIQ: 1113 irq_id = KVM_ARM_IRQ_CPU_FIQ; 1114 linestate_bit = CPU_INTERRUPT_FIQ; 1115 break; 1116 default: 1117 g_assert_not_reached(); 1118 } 1119 1120 if (level) { 1121 env->irq_line_state |= linestate_bit; 1122 } else { 1123 env->irq_line_state &= ~linestate_bit; 1124 } 1125 kvm_arm_set_irq(cs->cpu_index, KVM_ARM_IRQ_TYPE_CPU, irq_id, !!level); 1126 #endif 1127 } 1128 1129 static bool arm_cpu_virtio_is_big_endian(CPUState *cs) 1130 { 1131 ARMCPU *cpu = ARM_CPU(cs); 1132 CPUARMState *env = &cpu->env; 1133 1134 cpu_synchronize_state(cs); 1135 return arm_cpu_data_is_big_endian(env); 1136 } 1137 1138 #ifdef CONFIG_TCG 1139 bool arm_cpu_exec_halt(CPUState *cs) 1140 { 1141 bool leave_halt = cpu_has_work(cs); 1142 1143 if (leave_halt) { 1144 /* We're about to come out of WFI/WFE: disable the WFxT timer */ 1145 ARMCPU *cpu = ARM_CPU(cs); 1146 if (cpu->wfxt_timer) { 1147 timer_del(cpu->wfxt_timer); 1148 } 1149 } 1150 return leave_halt; 1151 } 1152 #endif 1153 1154 static void arm_wfxt_timer_cb(void *opaque) 1155 { 1156 ARMCPU *cpu = opaque; 1157 CPUState *cs = CPU(cpu); 1158 1159 /* 1160 * We expect the CPU to be halted; this will cause arm_cpu_is_work() 1161 * to return true (so we will come out of halt even with no other 1162 * pending interrupt), and the TCG accelerator's cpu_exec_interrupt() 1163 * function auto-clears the CPU_INTERRUPT_EXITTB flag for us. 1164 */ 1165 cpu_interrupt(cs, CPU_INTERRUPT_EXITTB); 1166 } 1167 #endif 1168 1169 static void arm_disas_set_info(CPUState *cpu, disassemble_info *info) 1170 { 1171 ARMCPU *ac = ARM_CPU(cpu); 1172 CPUARMState *env = &ac->env; 1173 bool sctlr_b = arm_sctlr_b(env); 1174 1175 if (is_a64(env)) { 1176 info->cap_arch = CS_ARCH_ARM64; 1177 info->cap_insn_unit = 4; 1178 info->cap_insn_split = 4; 1179 } else { 1180 int cap_mode; 1181 if (env->thumb) { 1182 info->cap_insn_unit = 2; 1183 info->cap_insn_split = 4; 1184 cap_mode = CS_MODE_THUMB; 1185 } else { 1186 info->cap_insn_unit = 4; 1187 info->cap_insn_split = 4; 1188 cap_mode = CS_MODE_ARM; 1189 } 1190 if (arm_feature(env, ARM_FEATURE_V8)) { 1191 cap_mode |= CS_MODE_V8; 1192 } 1193 if (arm_feature(env, ARM_FEATURE_M)) { 1194 cap_mode |= CS_MODE_MCLASS; 1195 } 1196 info->cap_arch = CS_ARCH_ARM; 1197 info->cap_mode = cap_mode; 1198 } 1199 1200 info->endian = BFD_ENDIAN_LITTLE; 1201 if (bswap_code(sctlr_b)) { 1202 info->endian = TARGET_BIG_ENDIAN ? BFD_ENDIAN_LITTLE : BFD_ENDIAN_BIG; 1203 } 1204 info->flags &= ~INSN_ARM_BE32; 1205 #ifndef CONFIG_USER_ONLY 1206 if (sctlr_b) { 1207 info->flags |= INSN_ARM_BE32; 1208 } 1209 #endif 1210 } 1211 1212 #ifdef TARGET_AARCH64 1213 1214 static void aarch64_cpu_dump_state(CPUState *cs, FILE *f, int flags) 1215 { 1216 ARMCPU *cpu = ARM_CPU(cs); 1217 CPUARMState *env = &cpu->env; 1218 uint32_t psr = pstate_read(env); 1219 int i, j; 1220 int el = arm_current_el(env); 1221 uint64_t hcr = arm_hcr_el2_eff(env); 1222 const char *ns_status; 1223 bool sve; 1224 1225 qemu_fprintf(f, " PC=%016" PRIx64 " ", env->pc); 1226 for (i = 0; i < 32; i++) { 1227 if (i == 31) { 1228 qemu_fprintf(f, " SP=%016" PRIx64 "\n", env->xregs[i]); 1229 } else { 1230 qemu_fprintf(f, "X%02d=%016" PRIx64 "%s", i, env->xregs[i], 1231 (i + 2) % 3 ? " " : "\n"); 1232 } 1233 } 1234 1235 if (arm_feature(env, ARM_FEATURE_EL3) && el != 3) { 1236 ns_status = env->cp15.scr_el3 & SCR_NS ? "NS " : "S "; 1237 } else { 1238 ns_status = ""; 1239 } 1240 qemu_fprintf(f, "PSTATE=%08x %c%c%c%c %sEL%d%c", 1241 psr, 1242 psr & PSTATE_N ? 'N' : '-', 1243 psr & PSTATE_Z ? 'Z' : '-', 1244 psr & PSTATE_C ? 'C' : '-', 1245 psr & PSTATE_V ? 'V' : '-', 1246 ns_status, 1247 el, 1248 psr & PSTATE_SP ? 'h' : 't'); 1249 1250 if (cpu_isar_feature(aa64_sme, cpu)) { 1251 qemu_fprintf(f, " SVCR=%08" PRIx64 " %c%c", 1252 env->svcr, 1253 (FIELD_EX64(env->svcr, SVCR, ZA) ? 'Z' : '-'), 1254 (FIELD_EX64(env->svcr, SVCR, SM) ? 'S' : '-')); 1255 } 1256 if (cpu_isar_feature(aa64_bti, cpu)) { 1257 qemu_fprintf(f, " BTYPE=%d", (psr & PSTATE_BTYPE) >> 10); 1258 } 1259 qemu_fprintf(f, "%s%s%s", 1260 (hcr & HCR_NV) ? " NV" : "", 1261 (hcr & HCR_NV1) ? " NV1" : "", 1262 (hcr & HCR_NV2) ? " NV2" : ""); 1263 if (!(flags & CPU_DUMP_FPU)) { 1264 qemu_fprintf(f, "\n"); 1265 return; 1266 } 1267 if (fp_exception_el(env, el) != 0) { 1268 qemu_fprintf(f, " FPU disabled\n"); 1269 return; 1270 } 1271 qemu_fprintf(f, " FPCR=%08x FPSR=%08x\n", 1272 vfp_get_fpcr(env), vfp_get_fpsr(env)); 1273 1274 if (cpu_isar_feature(aa64_sme, cpu) && FIELD_EX64(env->svcr, SVCR, SM)) { 1275 sve = sme_exception_el(env, el) == 0; 1276 } else if (cpu_isar_feature(aa64_sve, cpu)) { 1277 sve = sve_exception_el(env, el) == 0; 1278 } else { 1279 sve = false; 1280 } 1281 1282 if (sve) { 1283 int zcr_len = sve_vqm1_for_el(env, el); 1284 1285 for (i = 0; i <= FFR_PRED_NUM; i++) { 1286 bool eol; 1287 if (i == FFR_PRED_NUM) { 1288 qemu_fprintf(f, "FFR="); 1289 /* It's last, so end the line. */ 1290 eol = true; 1291 } else { 1292 qemu_fprintf(f, "P%02d=", i); 1293 switch (zcr_len) { 1294 case 0: 1295 eol = i % 8 == 7; 1296 break; 1297 case 1: 1298 eol = i % 6 == 5; 1299 break; 1300 case 2: 1301 case 3: 1302 eol = i % 3 == 2; 1303 break; 1304 default: 1305 /* More than one quadword per predicate. */ 1306 eol = true; 1307 break; 1308 } 1309 } 1310 for (j = zcr_len / 4; j >= 0; j--) { 1311 int digits; 1312 if (j * 4 + 4 <= zcr_len + 1) { 1313 digits = 16; 1314 } else { 1315 digits = (zcr_len % 4 + 1) * 4; 1316 } 1317 qemu_fprintf(f, "%0*" PRIx64 "%s", digits, 1318 env->vfp.pregs[i].p[j], 1319 j ? ":" : eol ? "\n" : " "); 1320 } 1321 } 1322 1323 if (zcr_len == 0) { 1324 /* 1325 * With vl=16, there are only 37 columns per register, 1326 * so output two registers per line. 1327 */ 1328 for (i = 0; i < 32; i++) { 1329 qemu_fprintf(f, "Z%02d=%016" PRIx64 ":%016" PRIx64 "%s", 1330 i, env->vfp.zregs[i].d[1], 1331 env->vfp.zregs[i].d[0], i & 1 ? "\n" : " "); 1332 } 1333 } else { 1334 for (i = 0; i < 32; i++) { 1335 qemu_fprintf(f, "Z%02d=", i); 1336 for (j = zcr_len; j >= 0; j--) { 1337 qemu_fprintf(f, "%016" PRIx64 ":%016" PRIx64 "%s", 1338 env->vfp.zregs[i].d[j * 2 + 1], 1339 env->vfp.zregs[i].d[j * 2 + 0], 1340 j ? ":" : "\n"); 1341 } 1342 } 1343 } 1344 } else { 1345 for (i = 0; i < 32; i++) { 1346 uint64_t *q = aa64_vfp_qreg(env, i); 1347 qemu_fprintf(f, "Q%02d=%016" PRIx64 ":%016" PRIx64 "%s", 1348 i, q[1], q[0], (i & 1 ? "\n" : " ")); 1349 } 1350 } 1351 1352 if (cpu_isar_feature(aa64_sme, cpu) && 1353 FIELD_EX64(env->svcr, SVCR, ZA) && 1354 sme_exception_el(env, el) == 0) { 1355 int zcr_len = sve_vqm1_for_el_sm(env, el, true); 1356 int svl = (zcr_len + 1) * 16; 1357 int svl_lg10 = svl < 100 ? 2 : 3; 1358 1359 for (i = 0; i < svl; i++) { 1360 qemu_fprintf(f, "ZA[%0*d]=", svl_lg10, i); 1361 for (j = zcr_len; j >= 0; --j) { 1362 qemu_fprintf(f, "%016" PRIx64 ":%016" PRIx64 "%c", 1363 env->zarray[i].d[2 * j + 1], 1364 env->zarray[i].d[2 * j], 1365 j ? ':' : '\n'); 1366 } 1367 } 1368 } 1369 } 1370 1371 #else 1372 1373 static inline void aarch64_cpu_dump_state(CPUState *cs, FILE *f, int flags) 1374 { 1375 g_assert_not_reached(); 1376 } 1377 1378 #endif 1379 1380 static void arm_cpu_dump_state(CPUState *cs, FILE *f, int flags) 1381 { 1382 ARMCPU *cpu = ARM_CPU(cs); 1383 CPUARMState *env = &cpu->env; 1384 int i; 1385 1386 if (is_a64(env)) { 1387 aarch64_cpu_dump_state(cs, f, flags); 1388 return; 1389 } 1390 1391 for (i = 0; i < 16; i++) { 1392 qemu_fprintf(f, "R%02d=%08x", i, env->regs[i]); 1393 if ((i % 4) == 3) { 1394 qemu_fprintf(f, "\n"); 1395 } else { 1396 qemu_fprintf(f, " "); 1397 } 1398 } 1399 1400 if (arm_feature(env, ARM_FEATURE_M)) { 1401 uint32_t xpsr = xpsr_read(env); 1402 const char *mode; 1403 const char *ns_status = ""; 1404 1405 if (arm_feature(env, ARM_FEATURE_M_SECURITY)) { 1406 ns_status = env->v7m.secure ? "S " : "NS "; 1407 } 1408 1409 if (xpsr & XPSR_EXCP) { 1410 mode = "handler"; 1411 } else { 1412 if (env->v7m.control[env->v7m.secure] & R_V7M_CONTROL_NPRIV_MASK) { 1413 mode = "unpriv-thread"; 1414 } else { 1415 mode = "priv-thread"; 1416 } 1417 } 1418 1419 qemu_fprintf(f, "XPSR=%08x %c%c%c%c %c %s%s\n", 1420 xpsr, 1421 xpsr & XPSR_N ? 'N' : '-', 1422 xpsr & XPSR_Z ? 'Z' : '-', 1423 xpsr & XPSR_C ? 'C' : '-', 1424 xpsr & XPSR_V ? 'V' : '-', 1425 xpsr & XPSR_T ? 'T' : 'A', 1426 ns_status, 1427 mode); 1428 } else { 1429 uint32_t psr = cpsr_read(env); 1430 const char *ns_status = ""; 1431 1432 if (arm_feature(env, ARM_FEATURE_EL3) && 1433 (psr & CPSR_M) != ARM_CPU_MODE_MON) { 1434 ns_status = env->cp15.scr_el3 & SCR_NS ? "NS " : "S "; 1435 } 1436 1437 qemu_fprintf(f, "PSR=%08x %c%c%c%c %c %s%s%d\n", 1438 psr, 1439 psr & CPSR_N ? 'N' : '-', 1440 psr & CPSR_Z ? 'Z' : '-', 1441 psr & CPSR_C ? 'C' : '-', 1442 psr & CPSR_V ? 'V' : '-', 1443 psr & CPSR_T ? 'T' : 'A', 1444 ns_status, 1445 aarch32_mode_name(psr), (psr & 0x10) ? 32 : 26); 1446 } 1447 1448 if (flags & CPU_DUMP_FPU) { 1449 int numvfpregs = 0; 1450 if (cpu_isar_feature(aa32_simd_r32, cpu)) { 1451 numvfpregs = 32; 1452 } else if (cpu_isar_feature(aa32_vfp_simd, cpu)) { 1453 numvfpregs = 16; 1454 } 1455 for (i = 0; i < numvfpregs; i++) { 1456 uint64_t v = *aa32_vfp_dreg(env, i); 1457 qemu_fprintf(f, "s%02d=%08x s%02d=%08x d%02d=%016" PRIx64 "\n", 1458 i * 2, (uint32_t)v, 1459 i * 2 + 1, (uint32_t)(v >> 32), 1460 i, v); 1461 } 1462 qemu_fprintf(f, "FPSCR: %08x\n", vfp_get_fpscr(env)); 1463 if (cpu_isar_feature(aa32_mve, cpu)) { 1464 qemu_fprintf(f, "VPR: %08x\n", env->v7m.vpr); 1465 } 1466 } 1467 } 1468 1469 uint64_t arm_build_mp_affinity(int idx, uint8_t clustersz) 1470 { 1471 uint32_t Aff1 = idx / clustersz; 1472 uint32_t Aff0 = idx % clustersz; 1473 return (Aff1 << ARM_AFF1_SHIFT) | Aff0; 1474 } 1475 1476 uint64_t arm_cpu_mp_affinity(ARMCPU *cpu) 1477 { 1478 return cpu->mp_affinity; 1479 } 1480 1481 static void arm_cpu_initfn(Object *obj) 1482 { 1483 ARMCPU *cpu = ARM_CPU(obj); 1484 1485 cpu->cp_regs = g_hash_table_new_full(g_direct_hash, g_direct_equal, 1486 NULL, g_free); 1487 1488 QLIST_INIT(&cpu->pre_el_change_hooks); 1489 QLIST_INIT(&cpu->el_change_hooks); 1490 1491 #ifdef CONFIG_USER_ONLY 1492 # ifdef TARGET_AARCH64 1493 /* 1494 * The linux kernel defaults to 512-bit for SVE, and 256-bit for SME. 1495 * These values were chosen to fit within the default signal frame. 1496 * See documentation for /proc/sys/abi/{sve,sme}_default_vector_length, 1497 * and our corresponding cpu property. 1498 */ 1499 cpu->sve_default_vq = 4; 1500 cpu->sme_default_vq = 2; 1501 # endif 1502 #else 1503 /* Our inbound IRQ and FIQ lines */ 1504 if (kvm_enabled()) { 1505 /* 1506 * VIRQ, VFIQ, NMI, VINMI are unused with KVM but we add 1507 * them to maintain the same interface as non-KVM CPUs. 1508 */ 1509 qdev_init_gpio_in(DEVICE(cpu), arm_cpu_kvm_set_irq, 6); 1510 } else { 1511 qdev_init_gpio_in(DEVICE(cpu), arm_cpu_set_irq, 6); 1512 } 1513 1514 qdev_init_gpio_out(DEVICE(cpu), cpu->gt_timer_outputs, 1515 ARRAY_SIZE(cpu->gt_timer_outputs)); 1516 1517 qdev_init_gpio_out_named(DEVICE(cpu), &cpu->gicv3_maintenance_interrupt, 1518 "gicv3-maintenance-interrupt", 1); 1519 qdev_init_gpio_out_named(DEVICE(cpu), &cpu->pmu_interrupt, 1520 "pmu-interrupt", 1); 1521 #endif 1522 1523 /* DTB consumers generally don't in fact care what the 'compatible' 1524 * string is, so always provide some string and trust that a hypothetical 1525 * picky DTB consumer will also provide a helpful error message. 1526 */ 1527 cpu->dtb_compatible = "qemu,unknown"; 1528 cpu->psci_version = QEMU_PSCI_VERSION_0_1; /* By default assume PSCI v0.1 */ 1529 cpu->kvm_target = QEMU_KVM_ARM_TARGET_NONE; 1530 1531 if (tcg_enabled() || hvf_enabled()) { 1532 /* TCG and HVF implement PSCI 1.1 */ 1533 cpu->psci_version = QEMU_PSCI_VERSION_1_1; 1534 } 1535 } 1536 1537 /* 1538 * 0 means "unset, use the default value". That default might vary depending 1539 * on the CPU type, and is set in the realize fn. 1540 */ 1541 static const Property arm_cpu_gt_cntfrq_property = 1542 DEFINE_PROP_UINT64("cntfrq", ARMCPU, gt_cntfrq_hz, 0); 1543 1544 static const Property arm_cpu_reset_cbar_property = 1545 DEFINE_PROP_UINT64("reset-cbar", ARMCPU, reset_cbar, 0); 1546 1547 static const Property arm_cpu_reset_hivecs_property = 1548 DEFINE_PROP_BOOL("reset-hivecs", ARMCPU, reset_hivecs, false); 1549 1550 #ifndef CONFIG_USER_ONLY 1551 static const Property arm_cpu_has_el2_property = 1552 DEFINE_PROP_BOOL("has_el2", ARMCPU, has_el2, true); 1553 1554 static const Property arm_cpu_has_el3_property = 1555 DEFINE_PROP_BOOL("has_el3", ARMCPU, has_el3, true); 1556 #endif 1557 1558 static const Property arm_cpu_cfgend_property = 1559 DEFINE_PROP_BOOL("cfgend", ARMCPU, cfgend, false); 1560 1561 static const Property arm_cpu_has_vfp_property = 1562 DEFINE_PROP_BOOL("vfp", ARMCPU, has_vfp, true); 1563 1564 static const Property arm_cpu_has_vfp_d32_property = 1565 DEFINE_PROP_BOOL("vfp-d32", ARMCPU, has_vfp_d32, true); 1566 1567 static const Property arm_cpu_has_neon_property = 1568 DEFINE_PROP_BOOL("neon", ARMCPU, has_neon, true); 1569 1570 static const Property arm_cpu_has_dsp_property = 1571 DEFINE_PROP_BOOL("dsp", ARMCPU, has_dsp, true); 1572 1573 static const Property arm_cpu_has_mpu_property = 1574 DEFINE_PROP_BOOL("has-mpu", ARMCPU, has_mpu, true); 1575 1576 /* This is like DEFINE_PROP_UINT32 but it doesn't set the default value, 1577 * because the CPU initfn will have already set cpu->pmsav7_dregion to 1578 * the right value for that particular CPU type, and we don't want 1579 * to override that with an incorrect constant value. 1580 */ 1581 static const Property arm_cpu_pmsav7_dregion_property = 1582 DEFINE_PROP_UNSIGNED_NODEFAULT("pmsav7-dregion", ARMCPU, 1583 pmsav7_dregion, 1584 qdev_prop_uint32, uint32_t); 1585 1586 static bool arm_get_pmu(Object *obj, Error **errp) 1587 { 1588 ARMCPU *cpu = ARM_CPU(obj); 1589 1590 return cpu->has_pmu; 1591 } 1592 1593 static void arm_set_pmu(Object *obj, bool value, Error **errp) 1594 { 1595 ARMCPU *cpu = ARM_CPU(obj); 1596 1597 if (value) { 1598 if (kvm_enabled() && !kvm_arm_pmu_supported()) { 1599 error_setg(errp, "'pmu' feature not supported by KVM on this host"); 1600 return; 1601 } 1602 set_feature(&cpu->env, ARM_FEATURE_PMU); 1603 } else { 1604 unset_feature(&cpu->env, ARM_FEATURE_PMU); 1605 } 1606 cpu->has_pmu = value; 1607 } 1608 1609 unsigned int gt_cntfrq_period_ns(ARMCPU *cpu) 1610 { 1611 /* 1612 * The exact approach to calculating guest ticks is: 1613 * 1614 * muldiv64(qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL), cpu->gt_cntfrq_hz, 1615 * NANOSECONDS_PER_SECOND); 1616 * 1617 * We don't do that. Rather we intentionally use integer division 1618 * truncation below and in the caller for the conversion of host monotonic 1619 * time to guest ticks to provide the exact inverse for the semantics of 1620 * the QEMUTimer scale factor. QEMUTimer's scale facter is an integer, so 1621 * it loses precision when representing frequencies where 1622 * `(NANOSECONDS_PER_SECOND % cpu->gt_cntfrq) > 0` holds. Failing to 1623 * provide an exact inverse leads to scheduling timers with negative 1624 * periods, which in turn leads to sticky behaviour in the guest. 1625 * 1626 * Finally, CNTFRQ is effectively capped at 1GHz to ensure our scale factor 1627 * cannot become zero. 1628 */ 1629 return NANOSECONDS_PER_SECOND > cpu->gt_cntfrq_hz ? 1630 NANOSECONDS_PER_SECOND / cpu->gt_cntfrq_hz : 1; 1631 } 1632 1633 static void arm_cpu_propagate_feature_implications(ARMCPU *cpu) 1634 { 1635 CPUARMState *env = &cpu->env; 1636 bool no_aa32 = false; 1637 1638 /* 1639 * Some features automatically imply others: set the feature 1640 * bits explicitly for these cases. 1641 */ 1642 1643 if (arm_feature(env, ARM_FEATURE_M)) { 1644 set_feature(env, ARM_FEATURE_PMSA); 1645 } 1646 1647 if (arm_feature(env, ARM_FEATURE_V8)) { 1648 if (arm_feature(env, ARM_FEATURE_M)) { 1649 set_feature(env, ARM_FEATURE_V7); 1650 } else { 1651 set_feature(env, ARM_FEATURE_V7VE); 1652 } 1653 } 1654 1655 /* 1656 * There exist AArch64 cpus without AArch32 support. When KVM 1657 * queries ID_ISAR0_EL1 on such a host, the value is UNKNOWN. 1658 * Similarly, we cannot check ID_AA64PFR0 without AArch64 support. 1659 * As a general principle, we also do not make ID register 1660 * consistency checks anywhere unless using TCG, because only 1661 * for TCG would a consistency-check failure be a QEMU bug. 1662 */ 1663 if (arm_feature(&cpu->env, ARM_FEATURE_AARCH64)) { 1664 no_aa32 = !cpu_isar_feature(aa64_aa32, cpu); 1665 } 1666 1667 if (arm_feature(env, ARM_FEATURE_V7VE)) { 1668 /* 1669 * v7 Virtualization Extensions. In real hardware this implies 1670 * EL2 and also the presence of the Security Extensions. 1671 * For QEMU, for backwards-compatibility we implement some 1672 * CPUs or CPU configs which have no actual EL2 or EL3 but do 1673 * include the various other features that V7VE implies. 1674 * Presence of EL2 itself is ARM_FEATURE_EL2, and of the 1675 * Security Extensions is ARM_FEATURE_EL3. 1676 */ 1677 assert(!tcg_enabled() || no_aa32 || 1678 cpu_isar_feature(aa32_arm_div, cpu)); 1679 set_feature(env, ARM_FEATURE_LPAE); 1680 set_feature(env, ARM_FEATURE_V7); 1681 } 1682 if (arm_feature(env, ARM_FEATURE_V7)) { 1683 set_feature(env, ARM_FEATURE_VAPA); 1684 set_feature(env, ARM_FEATURE_THUMB2); 1685 set_feature(env, ARM_FEATURE_MPIDR); 1686 if (!arm_feature(env, ARM_FEATURE_M)) { 1687 set_feature(env, ARM_FEATURE_V6K); 1688 } else { 1689 set_feature(env, ARM_FEATURE_V6); 1690 } 1691 1692 /* 1693 * Always define VBAR for V7 CPUs even if it doesn't exist in 1694 * non-EL3 configs. This is needed by some legacy boards. 1695 */ 1696 set_feature(env, ARM_FEATURE_VBAR); 1697 } 1698 if (arm_feature(env, ARM_FEATURE_V6K)) { 1699 set_feature(env, ARM_FEATURE_V6); 1700 set_feature(env, ARM_FEATURE_MVFR); 1701 } 1702 if (arm_feature(env, ARM_FEATURE_V6)) { 1703 set_feature(env, ARM_FEATURE_V5); 1704 if (!arm_feature(env, ARM_FEATURE_M)) { 1705 assert(!tcg_enabled() || no_aa32 || 1706 cpu_isar_feature(aa32_jazelle, cpu)); 1707 set_feature(env, ARM_FEATURE_AUXCR); 1708 } 1709 } 1710 if (arm_feature(env, ARM_FEATURE_V5)) { 1711 set_feature(env, ARM_FEATURE_V4T); 1712 } 1713 if (arm_feature(env, ARM_FEATURE_LPAE)) { 1714 set_feature(env, ARM_FEATURE_V7MP); 1715 } 1716 if (arm_feature(env, ARM_FEATURE_CBAR_RO)) { 1717 set_feature(env, ARM_FEATURE_CBAR); 1718 } 1719 if (arm_feature(env, ARM_FEATURE_THUMB2) && 1720 !arm_feature(env, ARM_FEATURE_M)) { 1721 set_feature(env, ARM_FEATURE_THUMB_DSP); 1722 } 1723 } 1724 1725 void arm_cpu_post_init(Object *obj) 1726 { 1727 ARMCPU *cpu = ARM_CPU(obj); 1728 1729 /* 1730 * Some features imply others. Figure this out now, because we 1731 * are going to look at the feature bits in deciding which 1732 * properties to add. 1733 */ 1734 arm_cpu_propagate_feature_implications(cpu); 1735 1736 if (arm_feature(&cpu->env, ARM_FEATURE_CBAR) || 1737 arm_feature(&cpu->env, ARM_FEATURE_CBAR_RO)) { 1738 qdev_property_add_static(DEVICE(obj), &arm_cpu_reset_cbar_property); 1739 } 1740 1741 if (!arm_feature(&cpu->env, ARM_FEATURE_M)) { 1742 qdev_property_add_static(DEVICE(obj), &arm_cpu_reset_hivecs_property); 1743 } 1744 1745 if (arm_feature(&cpu->env, ARM_FEATURE_V8)) { 1746 object_property_add_uint64_ptr(obj, "rvbar", 1747 &cpu->rvbar_prop, 1748 OBJ_PROP_FLAG_READWRITE); 1749 } 1750 1751 #ifndef CONFIG_USER_ONLY 1752 if (arm_feature(&cpu->env, ARM_FEATURE_EL3)) { 1753 /* Add the has_el3 state CPU property only if EL3 is allowed. This will 1754 * prevent "has_el3" from existing on CPUs which cannot support EL3. 1755 */ 1756 qdev_property_add_static(DEVICE(obj), &arm_cpu_has_el3_property); 1757 1758 object_property_add_link(obj, "secure-memory", 1759 TYPE_MEMORY_REGION, 1760 (Object **)&cpu->secure_memory, 1761 qdev_prop_allow_set_link_before_realize, 1762 OBJ_PROP_LINK_STRONG); 1763 } 1764 1765 if (arm_feature(&cpu->env, ARM_FEATURE_EL2)) { 1766 qdev_property_add_static(DEVICE(obj), &arm_cpu_has_el2_property); 1767 } 1768 #endif 1769 1770 if (arm_feature(&cpu->env, ARM_FEATURE_PMU)) { 1771 cpu->has_pmu = true; 1772 object_property_add_bool(obj, "pmu", arm_get_pmu, arm_set_pmu); 1773 } 1774 1775 /* 1776 * Allow user to turn off VFP and Neon support, but only for TCG -- 1777 * KVM does not currently allow us to lie to the guest about its 1778 * ID/feature registers, so the guest always sees what the host has. 1779 */ 1780 if (arm_feature(&cpu->env, ARM_FEATURE_AARCH64)) { 1781 if (cpu_isar_feature(aa64_fp_simd, cpu)) { 1782 cpu->has_vfp = true; 1783 cpu->has_vfp_d32 = true; 1784 if (tcg_enabled() || qtest_enabled()) { 1785 qdev_property_add_static(DEVICE(obj), 1786 &arm_cpu_has_vfp_property); 1787 } 1788 } 1789 } else if (cpu_isar_feature(aa32_vfp, cpu)) { 1790 cpu->has_vfp = true; 1791 if (tcg_enabled() || qtest_enabled()) { 1792 qdev_property_add_static(DEVICE(obj), 1793 &arm_cpu_has_vfp_property); 1794 } 1795 if (cpu_isar_feature(aa32_simd_r32, cpu)) { 1796 cpu->has_vfp_d32 = true; 1797 /* 1798 * The permitted values of the SIMDReg bits [3:0] on 1799 * Armv8-A are either 0b0000 and 0b0010. On such CPUs, 1800 * make sure that has_vfp_d32 can not be set to false. 1801 */ 1802 if ((tcg_enabled() || qtest_enabled()) 1803 && !(arm_feature(&cpu->env, ARM_FEATURE_V8) 1804 && !arm_feature(&cpu->env, ARM_FEATURE_M))) { 1805 qdev_property_add_static(DEVICE(obj), 1806 &arm_cpu_has_vfp_d32_property); 1807 } 1808 } 1809 } 1810 1811 if (arm_feature(&cpu->env, ARM_FEATURE_NEON)) { 1812 cpu->has_neon = true; 1813 if (!kvm_enabled()) { 1814 qdev_property_add_static(DEVICE(obj), &arm_cpu_has_neon_property); 1815 } 1816 } 1817 1818 if (arm_feature(&cpu->env, ARM_FEATURE_M) && 1819 arm_feature(&cpu->env, ARM_FEATURE_THUMB_DSP)) { 1820 qdev_property_add_static(DEVICE(obj), &arm_cpu_has_dsp_property); 1821 } 1822 1823 if (arm_feature(&cpu->env, ARM_FEATURE_PMSA)) { 1824 qdev_property_add_static(DEVICE(obj), &arm_cpu_has_mpu_property); 1825 if (arm_feature(&cpu->env, ARM_FEATURE_V7)) { 1826 qdev_property_add_static(DEVICE(obj), 1827 &arm_cpu_pmsav7_dregion_property); 1828 } 1829 } 1830 1831 if (arm_feature(&cpu->env, ARM_FEATURE_M_SECURITY)) { 1832 object_property_add_link(obj, "idau", TYPE_IDAU_INTERFACE, &cpu->idau, 1833 qdev_prop_allow_set_link_before_realize, 1834 OBJ_PROP_LINK_STRONG); 1835 /* 1836 * M profile: initial value of the Secure VTOR. We can't just use 1837 * a simple DEFINE_PROP_UINT32 for this because we want to permit 1838 * the property to be set after realize. 1839 */ 1840 object_property_add_uint32_ptr(obj, "init-svtor", 1841 &cpu->init_svtor, 1842 OBJ_PROP_FLAG_READWRITE); 1843 } 1844 if (arm_feature(&cpu->env, ARM_FEATURE_M)) { 1845 /* 1846 * Initial value of the NS VTOR (for cores without the Security 1847 * extension, this is the only VTOR) 1848 */ 1849 object_property_add_uint32_ptr(obj, "init-nsvtor", 1850 &cpu->init_nsvtor, 1851 OBJ_PROP_FLAG_READWRITE); 1852 } 1853 1854 /* Not DEFINE_PROP_UINT32: we want this to be settable after realize */ 1855 object_property_add_uint32_ptr(obj, "psci-conduit", 1856 &cpu->psci_conduit, 1857 OBJ_PROP_FLAG_READWRITE); 1858 1859 qdev_property_add_static(DEVICE(obj), &arm_cpu_cfgend_property); 1860 1861 if (arm_feature(&cpu->env, ARM_FEATURE_GENERIC_TIMER)) { 1862 qdev_property_add_static(DEVICE(cpu), &arm_cpu_gt_cntfrq_property); 1863 } 1864 1865 if (kvm_enabled()) { 1866 kvm_arm_add_vcpu_properties(cpu); 1867 } 1868 1869 #ifndef CONFIG_USER_ONLY 1870 if (arm_feature(&cpu->env, ARM_FEATURE_AARCH64) && 1871 cpu_isar_feature(aa64_mte, cpu)) { 1872 object_property_add_link(obj, "tag-memory", 1873 TYPE_MEMORY_REGION, 1874 (Object **)&cpu->tag_memory, 1875 qdev_prop_allow_set_link_before_realize, 1876 OBJ_PROP_LINK_STRONG); 1877 1878 if (arm_feature(&cpu->env, ARM_FEATURE_EL3)) { 1879 object_property_add_link(obj, "secure-tag-memory", 1880 TYPE_MEMORY_REGION, 1881 (Object **)&cpu->secure_tag_memory, 1882 qdev_prop_allow_set_link_before_realize, 1883 OBJ_PROP_LINK_STRONG); 1884 } 1885 } 1886 #endif 1887 } 1888 1889 static void arm_cpu_finalizefn(Object *obj) 1890 { 1891 ARMCPU *cpu = ARM_CPU(obj); 1892 ARMELChangeHook *hook, *next; 1893 1894 g_hash_table_destroy(cpu->cp_regs); 1895 1896 QLIST_FOREACH_SAFE(hook, &cpu->pre_el_change_hooks, node, next) { 1897 QLIST_REMOVE(hook, node); 1898 g_free(hook); 1899 } 1900 QLIST_FOREACH_SAFE(hook, &cpu->el_change_hooks, node, next) { 1901 QLIST_REMOVE(hook, node); 1902 g_free(hook); 1903 } 1904 #ifndef CONFIG_USER_ONLY 1905 if (cpu->pmu_timer) { 1906 timer_free(cpu->pmu_timer); 1907 } 1908 if (cpu->wfxt_timer) { 1909 timer_free(cpu->wfxt_timer); 1910 } 1911 #endif 1912 } 1913 1914 void arm_cpu_finalize_features(ARMCPU *cpu, Error **errp) 1915 { 1916 Error *local_err = NULL; 1917 1918 #ifdef TARGET_AARCH64 1919 if (arm_feature(&cpu->env, ARM_FEATURE_AARCH64)) { 1920 arm_cpu_sve_finalize(cpu, &local_err); 1921 if (local_err != NULL) { 1922 error_propagate(errp, local_err); 1923 return; 1924 } 1925 1926 /* 1927 * FEAT_SME is not architecturally dependent on FEAT_SVE (unless 1928 * FEAT_SME_FA64 is present). However our implementation currently 1929 * assumes it, so if the user asked for sve=off then turn off SME also. 1930 * (KVM doesn't currently support SME at all.) 1931 */ 1932 if (cpu_isar_feature(aa64_sme, cpu) && !cpu_isar_feature(aa64_sve, cpu)) { 1933 object_property_set_bool(OBJECT(cpu), "sme", false, &error_abort); 1934 } 1935 1936 arm_cpu_sme_finalize(cpu, &local_err); 1937 if (local_err != NULL) { 1938 error_propagate(errp, local_err); 1939 return; 1940 } 1941 1942 arm_cpu_pauth_finalize(cpu, &local_err); 1943 if (local_err != NULL) { 1944 error_propagate(errp, local_err); 1945 return; 1946 } 1947 1948 arm_cpu_lpa2_finalize(cpu, &local_err); 1949 if (local_err != NULL) { 1950 error_propagate(errp, local_err); 1951 return; 1952 } 1953 } 1954 #endif 1955 1956 if (kvm_enabled()) { 1957 kvm_arm_steal_time_finalize(cpu, &local_err); 1958 if (local_err != NULL) { 1959 error_propagate(errp, local_err); 1960 return; 1961 } 1962 } 1963 } 1964 1965 static void arm_cpu_realizefn(DeviceState *dev, Error **errp) 1966 { 1967 CPUState *cs = CPU(dev); 1968 ARMCPU *cpu = ARM_CPU(dev); 1969 ARMCPUClass *acc = ARM_CPU_GET_CLASS(dev); 1970 CPUARMState *env = &cpu->env; 1971 Error *local_err = NULL; 1972 1973 #if defined(CONFIG_TCG) && !defined(CONFIG_USER_ONLY) 1974 /* Use pc-relative instructions in system-mode */ 1975 tcg_cflags_set(cs, CF_PCREL); 1976 #endif 1977 1978 /* If we needed to query the host kernel for the CPU features 1979 * then it's possible that might have failed in the initfn, but 1980 * this is the first point where we can report it. 1981 */ 1982 if (cpu->host_cpu_probe_failed) { 1983 if (!kvm_enabled() && !hvf_enabled()) { 1984 error_setg(errp, "The 'host' CPU type can only be used with KVM or HVF"); 1985 } else { 1986 error_setg(errp, "Failed to retrieve host CPU features"); 1987 } 1988 return; 1989 } 1990 1991 if (!cpu->gt_cntfrq_hz) { 1992 /* 1993 * 0 means "the board didn't set a value, use the default". (We also 1994 * get here for the CONFIG_USER_ONLY case.) 1995 * ARMv8.6 and later CPUs architecturally must use a 1GHz timer; before 1996 * that it was an IMPDEF choice, and QEMU initially picked 62.5MHz, 1997 * which gives a 16ns tick period. 1998 * 1999 * We will use the back-compat value: 2000 * - for QEMU CPU types added before we standardized on 1GHz 2001 * - for versioned machine types with a version of 9.0 or earlier 2002 */ 2003 if (arm_feature(env, ARM_FEATURE_BACKCOMPAT_CNTFRQ) || 2004 cpu->backcompat_cntfrq) { 2005 cpu->gt_cntfrq_hz = GTIMER_BACKCOMPAT_HZ; 2006 } else { 2007 cpu->gt_cntfrq_hz = GTIMER_DEFAULT_HZ; 2008 } 2009 } 2010 2011 #ifndef CONFIG_USER_ONLY 2012 /* The NVIC and M-profile CPU are two halves of a single piece of 2013 * hardware; trying to use one without the other is a command line 2014 * error and will result in segfaults if not caught here. 2015 */ 2016 if (arm_feature(env, ARM_FEATURE_M)) { 2017 if (!env->nvic) { 2018 error_setg(errp, "This board cannot be used with Cortex-M CPUs"); 2019 return; 2020 } 2021 } else { 2022 if (env->nvic) { 2023 error_setg(errp, "This board can only be used with Cortex-M CPUs"); 2024 return; 2025 } 2026 } 2027 2028 if (!tcg_enabled() && !qtest_enabled()) { 2029 /* 2030 * We assume that no accelerator except TCG (and the "not really an 2031 * accelerator" qtest) can handle these features, because Arm hardware 2032 * virtualization can't virtualize them. 2033 * 2034 * Catch all the cases which might cause us to create more than one 2035 * address space for the CPU (otherwise we will assert() later in 2036 * cpu_address_space_init()). 2037 */ 2038 if (arm_feature(env, ARM_FEATURE_M)) { 2039 error_setg(errp, 2040 "Cannot enable %s when using an M-profile guest CPU", 2041 current_accel_name()); 2042 return; 2043 } 2044 if (cpu->has_el3) { 2045 error_setg(errp, 2046 "Cannot enable %s when guest CPU has EL3 enabled", 2047 current_accel_name()); 2048 return; 2049 } 2050 if (cpu->tag_memory) { 2051 error_setg(errp, 2052 "Cannot enable %s when guest CPUs has MTE enabled", 2053 current_accel_name()); 2054 return; 2055 } 2056 } 2057 2058 { 2059 uint64_t scale = gt_cntfrq_period_ns(cpu); 2060 2061 cpu->gt_timer[GTIMER_PHYS] = timer_new(QEMU_CLOCK_VIRTUAL, scale, 2062 arm_gt_ptimer_cb, cpu); 2063 cpu->gt_timer[GTIMER_VIRT] = timer_new(QEMU_CLOCK_VIRTUAL, scale, 2064 arm_gt_vtimer_cb, cpu); 2065 cpu->gt_timer[GTIMER_HYP] = timer_new(QEMU_CLOCK_VIRTUAL, scale, 2066 arm_gt_htimer_cb, cpu); 2067 cpu->gt_timer[GTIMER_SEC] = timer_new(QEMU_CLOCK_VIRTUAL, scale, 2068 arm_gt_stimer_cb, cpu); 2069 cpu->gt_timer[GTIMER_HYPVIRT] = timer_new(QEMU_CLOCK_VIRTUAL, scale, 2070 arm_gt_hvtimer_cb, cpu); 2071 cpu->gt_timer[GTIMER_S_EL2_PHYS] = timer_new(QEMU_CLOCK_VIRTUAL, scale, 2072 arm_gt_sel2timer_cb, cpu); 2073 cpu->gt_timer[GTIMER_S_EL2_VIRT] = timer_new(QEMU_CLOCK_VIRTUAL, scale, 2074 arm_gt_sel2vtimer_cb, cpu); 2075 } 2076 #endif 2077 2078 cpu_exec_realizefn(cs, &local_err); 2079 if (local_err != NULL) { 2080 error_propagate(errp, local_err); 2081 return; 2082 } 2083 2084 arm_cpu_finalize_features(cpu, &local_err); 2085 if (local_err != NULL) { 2086 error_propagate(errp, local_err); 2087 return; 2088 } 2089 2090 #ifdef CONFIG_USER_ONLY 2091 /* 2092 * User mode relies on IC IVAU instructions to catch modification of 2093 * dual-mapped code. 2094 * 2095 * Clear CTR_EL0.DIC to ensure that software that honors these flags uses 2096 * IC IVAU even if the emulated processor does not normally require it. 2097 */ 2098 cpu->ctr = FIELD_DP64(cpu->ctr, CTR_EL0, DIC, 0); 2099 #endif 2100 2101 if (arm_feature(env, ARM_FEATURE_AARCH64) && 2102 cpu->has_vfp != cpu->has_neon) { 2103 /* 2104 * This is an architectural requirement for AArch64; AArch32 is 2105 * more flexible and permits VFP-no-Neon and Neon-no-VFP. 2106 */ 2107 error_setg(errp, 2108 "AArch64 CPUs must have both VFP and Neon or neither"); 2109 return; 2110 } 2111 2112 if (cpu->has_vfp_d32 != cpu->has_neon) { 2113 error_setg(errp, "ARM CPUs must have both VFP-D32 and Neon or neither"); 2114 return; 2115 } 2116 2117 if (!cpu->has_vfp_d32) { 2118 uint32_t u; 2119 2120 u = cpu->isar.mvfr0; 2121 u = FIELD_DP32(u, MVFR0, SIMDREG, 1); /* 16 registers */ 2122 cpu->isar.mvfr0 = u; 2123 } 2124 2125 if (!cpu->has_vfp) { 2126 uint64_t t; 2127 uint32_t u; 2128 2129 t = cpu->isar.id_aa64isar1; 2130 t = FIELD_DP64(t, ID_AA64ISAR1, JSCVT, 0); 2131 cpu->isar.id_aa64isar1 = t; 2132 2133 t = cpu->isar.id_aa64pfr0; 2134 t = FIELD_DP64(t, ID_AA64PFR0, FP, 0xf); 2135 cpu->isar.id_aa64pfr0 = t; 2136 2137 u = cpu->isar.id_isar6; 2138 u = FIELD_DP32(u, ID_ISAR6, JSCVT, 0); 2139 u = FIELD_DP32(u, ID_ISAR6, BF16, 0); 2140 cpu->isar.id_isar6 = u; 2141 2142 u = cpu->isar.mvfr0; 2143 u = FIELD_DP32(u, MVFR0, FPSP, 0); 2144 u = FIELD_DP32(u, MVFR0, FPDP, 0); 2145 u = FIELD_DP32(u, MVFR0, FPDIVIDE, 0); 2146 u = FIELD_DP32(u, MVFR0, FPSQRT, 0); 2147 u = FIELD_DP32(u, MVFR0, FPROUND, 0); 2148 if (!arm_feature(env, ARM_FEATURE_M)) { 2149 u = FIELD_DP32(u, MVFR0, FPTRAP, 0); 2150 u = FIELD_DP32(u, MVFR0, FPSHVEC, 0); 2151 } 2152 cpu->isar.mvfr0 = u; 2153 2154 u = cpu->isar.mvfr1; 2155 u = FIELD_DP32(u, MVFR1, FPFTZ, 0); 2156 u = FIELD_DP32(u, MVFR1, FPDNAN, 0); 2157 u = FIELD_DP32(u, MVFR1, FPHP, 0); 2158 if (arm_feature(env, ARM_FEATURE_M)) { 2159 u = FIELD_DP32(u, MVFR1, FP16, 0); 2160 } 2161 cpu->isar.mvfr1 = u; 2162 2163 u = cpu->isar.mvfr2; 2164 u = FIELD_DP32(u, MVFR2, FPMISC, 0); 2165 cpu->isar.mvfr2 = u; 2166 } 2167 2168 if (!cpu->has_neon) { 2169 uint64_t t; 2170 uint32_t u; 2171 2172 unset_feature(env, ARM_FEATURE_NEON); 2173 2174 t = cpu->isar.id_aa64isar0; 2175 t = FIELD_DP64(t, ID_AA64ISAR0, AES, 0); 2176 t = FIELD_DP64(t, ID_AA64ISAR0, SHA1, 0); 2177 t = FIELD_DP64(t, ID_AA64ISAR0, SHA2, 0); 2178 t = FIELD_DP64(t, ID_AA64ISAR0, SHA3, 0); 2179 t = FIELD_DP64(t, ID_AA64ISAR0, SM3, 0); 2180 t = FIELD_DP64(t, ID_AA64ISAR0, SM4, 0); 2181 t = FIELD_DP64(t, ID_AA64ISAR0, DP, 0); 2182 cpu->isar.id_aa64isar0 = t; 2183 2184 t = cpu->isar.id_aa64isar1; 2185 t = FIELD_DP64(t, ID_AA64ISAR1, FCMA, 0); 2186 t = FIELD_DP64(t, ID_AA64ISAR1, BF16, 0); 2187 t = FIELD_DP64(t, ID_AA64ISAR1, I8MM, 0); 2188 cpu->isar.id_aa64isar1 = t; 2189 2190 t = cpu->isar.id_aa64pfr0; 2191 t = FIELD_DP64(t, ID_AA64PFR0, ADVSIMD, 0xf); 2192 cpu->isar.id_aa64pfr0 = t; 2193 2194 u = cpu->isar.id_isar5; 2195 u = FIELD_DP32(u, ID_ISAR5, AES, 0); 2196 u = FIELD_DP32(u, ID_ISAR5, SHA1, 0); 2197 u = FIELD_DP32(u, ID_ISAR5, SHA2, 0); 2198 u = FIELD_DP32(u, ID_ISAR5, RDM, 0); 2199 u = FIELD_DP32(u, ID_ISAR5, VCMA, 0); 2200 cpu->isar.id_isar5 = u; 2201 2202 u = cpu->isar.id_isar6; 2203 u = FIELD_DP32(u, ID_ISAR6, DP, 0); 2204 u = FIELD_DP32(u, ID_ISAR6, FHM, 0); 2205 u = FIELD_DP32(u, ID_ISAR6, BF16, 0); 2206 u = FIELD_DP32(u, ID_ISAR6, I8MM, 0); 2207 cpu->isar.id_isar6 = u; 2208 2209 if (!arm_feature(env, ARM_FEATURE_M)) { 2210 u = cpu->isar.mvfr1; 2211 u = FIELD_DP32(u, MVFR1, SIMDLS, 0); 2212 u = FIELD_DP32(u, MVFR1, SIMDINT, 0); 2213 u = FIELD_DP32(u, MVFR1, SIMDSP, 0); 2214 u = FIELD_DP32(u, MVFR1, SIMDHP, 0); 2215 cpu->isar.mvfr1 = u; 2216 2217 u = cpu->isar.mvfr2; 2218 u = FIELD_DP32(u, MVFR2, SIMDMISC, 0); 2219 cpu->isar.mvfr2 = u; 2220 } 2221 } 2222 2223 if (!cpu->has_neon && !cpu->has_vfp) { 2224 uint64_t t; 2225 uint32_t u; 2226 2227 t = cpu->isar.id_aa64isar0; 2228 t = FIELD_DP64(t, ID_AA64ISAR0, FHM, 0); 2229 cpu->isar.id_aa64isar0 = t; 2230 2231 t = cpu->isar.id_aa64isar1; 2232 t = FIELD_DP64(t, ID_AA64ISAR1, FRINTTS, 0); 2233 cpu->isar.id_aa64isar1 = t; 2234 2235 u = cpu->isar.mvfr0; 2236 u = FIELD_DP32(u, MVFR0, SIMDREG, 0); 2237 cpu->isar.mvfr0 = u; 2238 2239 /* Despite the name, this field covers both VFP and Neon */ 2240 u = cpu->isar.mvfr1; 2241 u = FIELD_DP32(u, MVFR1, SIMDFMAC, 0); 2242 cpu->isar.mvfr1 = u; 2243 } 2244 2245 if (arm_feature(env, ARM_FEATURE_M) && !cpu->has_dsp) { 2246 uint32_t u; 2247 2248 unset_feature(env, ARM_FEATURE_THUMB_DSP); 2249 2250 u = cpu->isar.id_isar1; 2251 u = FIELD_DP32(u, ID_ISAR1, EXTEND, 1); 2252 cpu->isar.id_isar1 = u; 2253 2254 u = cpu->isar.id_isar2; 2255 u = FIELD_DP32(u, ID_ISAR2, MULTU, 1); 2256 u = FIELD_DP32(u, ID_ISAR2, MULTS, 1); 2257 cpu->isar.id_isar2 = u; 2258 2259 u = cpu->isar.id_isar3; 2260 u = FIELD_DP32(u, ID_ISAR3, SIMD, 1); 2261 u = FIELD_DP32(u, ID_ISAR3, SATURATE, 0); 2262 cpu->isar.id_isar3 = u; 2263 } 2264 2265 2266 /* 2267 * We rely on no XScale CPU having VFP so we can use the same bits in the 2268 * TB flags field for VECSTRIDE and XSCALE_CPAR. 2269 */ 2270 assert(arm_feature(env, ARM_FEATURE_AARCH64) || 2271 !cpu_isar_feature(aa32_vfp_simd, cpu) || 2272 !arm_feature(env, ARM_FEATURE_XSCALE)); 2273 2274 #ifndef CONFIG_USER_ONLY 2275 { 2276 int pagebits; 2277 if (arm_feature(env, ARM_FEATURE_V7) && 2278 !arm_feature(env, ARM_FEATURE_M) && 2279 !arm_feature(env, ARM_FEATURE_PMSA)) { 2280 /* 2281 * v7VMSA drops support for the old ARMv5 tiny pages, 2282 * so we can use 4K pages. 2283 */ 2284 pagebits = 12; 2285 } else { 2286 /* 2287 * For CPUs which might have tiny 1K pages, or which have an 2288 * MPU and might have small region sizes, stick with 1K pages. 2289 */ 2290 pagebits = 10; 2291 } 2292 if (!set_preferred_target_page_bits(pagebits)) { 2293 /* 2294 * This can only ever happen for hotplugging a CPU, or if 2295 * the board code incorrectly creates a CPU which it has 2296 * promised via minimum_page_size that it will not. 2297 */ 2298 error_setg(errp, "This CPU requires a smaller page size " 2299 "than the system is using"); 2300 return; 2301 } 2302 } 2303 #endif 2304 2305 /* This cpu-id-to-MPIDR affinity is used only for TCG; KVM will override it. 2306 * We don't support setting cluster ID ([16..23]) (known as Aff2 2307 * in later ARM ARM versions), or any of the higher affinity level fields, 2308 * so these bits always RAZ. 2309 */ 2310 if (cpu->mp_affinity == ARM64_AFFINITY_INVALID) { 2311 cpu->mp_affinity = arm_build_mp_affinity(cs->cpu_index, 2312 ARM_DEFAULT_CPUS_PER_CLUSTER); 2313 } 2314 2315 if (cpu->reset_hivecs) { 2316 cpu->reset_sctlr |= (1 << 13); 2317 } 2318 2319 if (cpu->cfgend) { 2320 if (arm_feature(env, ARM_FEATURE_V7)) { 2321 cpu->reset_sctlr |= SCTLR_EE; 2322 } else { 2323 cpu->reset_sctlr |= SCTLR_B; 2324 } 2325 } 2326 2327 if (!arm_feature(env, ARM_FEATURE_M) && !cpu->has_el3) { 2328 /* If the has_el3 CPU property is disabled then we need to disable the 2329 * feature. 2330 */ 2331 unset_feature(env, ARM_FEATURE_EL3); 2332 2333 /* 2334 * Disable the security extension feature bits in the processor 2335 * feature registers as well. 2336 */ 2337 cpu->isar.id_pfr1 = FIELD_DP32(cpu->isar.id_pfr1, ID_PFR1, SECURITY, 0); 2338 cpu->isar.id_dfr0 = FIELD_DP32(cpu->isar.id_dfr0, ID_DFR0, COPSDBG, 0); 2339 cpu->isar.id_aa64pfr0 = FIELD_DP64(cpu->isar.id_aa64pfr0, 2340 ID_AA64PFR0, EL3, 0); 2341 2342 /* Disable the realm management extension, which requires EL3. */ 2343 cpu->isar.id_aa64pfr0 = FIELD_DP64(cpu->isar.id_aa64pfr0, 2344 ID_AA64PFR0, RME, 0); 2345 } 2346 2347 if (!cpu->has_el2) { 2348 unset_feature(env, ARM_FEATURE_EL2); 2349 } 2350 2351 if (!cpu->has_pmu) { 2352 unset_feature(env, ARM_FEATURE_PMU); 2353 } 2354 if (arm_feature(env, ARM_FEATURE_PMU)) { 2355 pmu_init(cpu); 2356 2357 if (!kvm_enabled()) { 2358 arm_register_pre_el_change_hook(cpu, &pmu_pre_el_change, 0); 2359 arm_register_el_change_hook(cpu, &pmu_post_el_change, 0); 2360 } 2361 2362 #ifndef CONFIG_USER_ONLY 2363 cpu->pmu_timer = timer_new_ns(QEMU_CLOCK_VIRTUAL, arm_pmu_timer_cb, 2364 cpu); 2365 #endif 2366 } else { 2367 cpu->isar.id_aa64dfr0 = 2368 FIELD_DP64(cpu->isar.id_aa64dfr0, ID_AA64DFR0, PMUVER, 0); 2369 cpu->isar.id_dfr0 = FIELD_DP32(cpu->isar.id_dfr0, ID_DFR0, PERFMON, 0); 2370 cpu->pmceid0 = 0; 2371 cpu->pmceid1 = 0; 2372 } 2373 2374 if (!arm_feature(env, ARM_FEATURE_EL2)) { 2375 /* 2376 * Disable the hypervisor feature bits in the processor feature 2377 * registers if we don't have EL2. 2378 */ 2379 cpu->isar.id_aa64pfr0 = FIELD_DP64(cpu->isar.id_aa64pfr0, 2380 ID_AA64PFR0, EL2, 0); 2381 cpu->isar.id_pfr1 = FIELD_DP32(cpu->isar.id_pfr1, 2382 ID_PFR1, VIRTUALIZATION, 0); 2383 } 2384 2385 if (cpu_isar_feature(aa64_mte, cpu)) { 2386 /* 2387 * The architectural range of GM blocksize is 2-6, however qemu 2388 * doesn't support blocksize of 2 (see HELPER(ldgm)). 2389 */ 2390 if (tcg_enabled()) { 2391 assert(cpu->gm_blocksize >= 3 && cpu->gm_blocksize <= 6); 2392 } 2393 2394 #ifndef CONFIG_USER_ONLY 2395 /* 2396 * If we run with TCG and do not have tag-memory provided by 2397 * the machine, then reduce MTE support to instructions enabled at EL0. 2398 * This matches Cortex-A710 BROADCASTMTE input being LOW. 2399 */ 2400 if (tcg_enabled() && cpu->tag_memory == NULL) { 2401 cpu->isar.id_aa64pfr1 = 2402 FIELD_DP64(cpu->isar.id_aa64pfr1, ID_AA64PFR1, MTE, 1); 2403 } 2404 2405 /* 2406 * If MTE is supported by the host, however it should not be 2407 * enabled on the guest (i.e mte=off), clear guest's MTE bits." 2408 */ 2409 if (kvm_enabled() && !cpu->kvm_mte) { 2410 FIELD_DP64(cpu->isar.id_aa64pfr1, ID_AA64PFR1, MTE, 0); 2411 } 2412 #endif 2413 } 2414 2415 #ifndef CONFIG_USER_ONLY 2416 if (tcg_enabled() && cpu_isar_feature(aa64_wfxt, cpu)) { 2417 cpu->wfxt_timer = timer_new_ns(QEMU_CLOCK_VIRTUAL, 2418 arm_wfxt_timer_cb, cpu); 2419 } 2420 #endif 2421 2422 if (tcg_enabled()) { 2423 /* 2424 * Don't report some architectural features in the ID registers 2425 * where TCG does not yet implement it (not even a minimal 2426 * stub version). This avoids guests falling over when they 2427 * try to access the non-existent system registers for them. 2428 */ 2429 /* FEAT_SPE (Statistical Profiling Extension) */ 2430 cpu->isar.id_aa64dfr0 = 2431 FIELD_DP64(cpu->isar.id_aa64dfr0, ID_AA64DFR0, PMSVER, 0); 2432 /* FEAT_TRBE (Trace Buffer Extension) */ 2433 cpu->isar.id_aa64dfr0 = 2434 FIELD_DP64(cpu->isar.id_aa64dfr0, ID_AA64DFR0, TRACEBUFFER, 0); 2435 /* FEAT_TRF (Self-hosted Trace Extension) */ 2436 cpu->isar.id_aa64dfr0 = 2437 FIELD_DP64(cpu->isar.id_aa64dfr0, ID_AA64DFR0, TRACEFILT, 0); 2438 cpu->isar.id_dfr0 = 2439 FIELD_DP32(cpu->isar.id_dfr0, ID_DFR0, TRACEFILT, 0); 2440 /* Trace Macrocell system register access */ 2441 cpu->isar.id_aa64dfr0 = 2442 FIELD_DP64(cpu->isar.id_aa64dfr0, ID_AA64DFR0, TRACEVER, 0); 2443 cpu->isar.id_dfr0 = 2444 FIELD_DP32(cpu->isar.id_dfr0, ID_DFR0, COPTRC, 0); 2445 /* Memory mapped trace */ 2446 cpu->isar.id_dfr0 = 2447 FIELD_DP32(cpu->isar.id_dfr0, ID_DFR0, MMAPTRC, 0); 2448 /* FEAT_AMU (Activity Monitors Extension) */ 2449 cpu->isar.id_aa64pfr0 = 2450 FIELD_DP64(cpu->isar.id_aa64pfr0, ID_AA64PFR0, AMU, 0); 2451 cpu->isar.id_pfr0 = 2452 FIELD_DP32(cpu->isar.id_pfr0, ID_PFR0, AMU, 0); 2453 /* FEAT_MPAM (Memory Partitioning and Monitoring Extension) */ 2454 cpu->isar.id_aa64pfr0 = 2455 FIELD_DP64(cpu->isar.id_aa64pfr0, ID_AA64PFR0, MPAM, 0); 2456 } 2457 2458 /* MPU can be configured out of a PMSA CPU either by setting has-mpu 2459 * to false or by setting pmsav7-dregion to 0. 2460 */ 2461 if (!cpu->has_mpu || cpu->pmsav7_dregion == 0) { 2462 cpu->has_mpu = false; 2463 cpu->pmsav7_dregion = 0; 2464 cpu->pmsav8r_hdregion = 0; 2465 } 2466 2467 if (arm_feature(env, ARM_FEATURE_PMSA) && 2468 arm_feature(env, ARM_FEATURE_V7)) { 2469 uint32_t nr = cpu->pmsav7_dregion; 2470 2471 if (nr > 0xff) { 2472 error_setg(errp, "PMSAv7 MPU #regions invalid %" PRIu32, nr); 2473 return; 2474 } 2475 2476 if (nr) { 2477 if (arm_feature(env, ARM_FEATURE_V8)) { 2478 /* PMSAv8 */ 2479 env->pmsav8.rbar[M_REG_NS] = g_new0(uint32_t, nr); 2480 env->pmsav8.rlar[M_REG_NS] = g_new0(uint32_t, nr); 2481 if (arm_feature(env, ARM_FEATURE_M_SECURITY)) { 2482 env->pmsav8.rbar[M_REG_S] = g_new0(uint32_t, nr); 2483 env->pmsav8.rlar[M_REG_S] = g_new0(uint32_t, nr); 2484 } 2485 } else { 2486 env->pmsav7.drbar = g_new0(uint32_t, nr); 2487 env->pmsav7.drsr = g_new0(uint32_t, nr); 2488 env->pmsav7.dracr = g_new0(uint32_t, nr); 2489 } 2490 } 2491 2492 if (cpu->pmsav8r_hdregion > 0xff) { 2493 error_setg(errp, "PMSAv8 MPU EL2 #regions invalid %" PRIu32, 2494 cpu->pmsav8r_hdregion); 2495 return; 2496 } 2497 2498 if (cpu->pmsav8r_hdregion) { 2499 env->pmsav8.hprbar = g_new0(uint32_t, 2500 cpu->pmsav8r_hdregion); 2501 env->pmsav8.hprlar = g_new0(uint32_t, 2502 cpu->pmsav8r_hdregion); 2503 } 2504 } 2505 2506 if (arm_feature(env, ARM_FEATURE_M_SECURITY)) { 2507 uint32_t nr = cpu->sau_sregion; 2508 2509 if (nr > 0xff) { 2510 error_setg(errp, "v8M SAU #regions invalid %" PRIu32, nr); 2511 return; 2512 } 2513 2514 if (nr) { 2515 env->sau.rbar = g_new0(uint32_t, nr); 2516 env->sau.rlar = g_new0(uint32_t, nr); 2517 } 2518 } 2519 2520 if (arm_feature(env, ARM_FEATURE_EL3)) { 2521 set_feature(env, ARM_FEATURE_VBAR); 2522 } 2523 2524 #ifndef CONFIG_USER_ONLY 2525 if (tcg_enabled() && cpu_isar_feature(aa64_rme, cpu)) { 2526 arm_register_el_change_hook(cpu, >_rme_post_el_change, 0); 2527 } 2528 #endif 2529 2530 register_cp_regs_for_features(cpu); 2531 arm_cpu_register_gdb_regs_for_features(cpu); 2532 arm_cpu_register_gdb_commands(cpu); 2533 2534 init_cpreg_list(cpu); 2535 2536 #ifndef CONFIG_USER_ONLY 2537 MachineState *ms = MACHINE(qdev_get_machine()); 2538 unsigned int smp_cpus = ms->smp.cpus; 2539 bool has_secure = cpu->has_el3 || arm_feature(env, ARM_FEATURE_M_SECURITY); 2540 2541 /* 2542 * We must set cs->num_ases to the final value before 2543 * the first call to cpu_address_space_init. 2544 */ 2545 if (cpu->tag_memory != NULL) { 2546 cs->num_ases = 3 + has_secure; 2547 } else { 2548 cs->num_ases = 1 + has_secure; 2549 } 2550 2551 if (has_secure) { 2552 if (!cpu->secure_memory) { 2553 cpu->secure_memory = cs->memory; 2554 } 2555 cpu_address_space_init(cs, ARMASIdx_S, "cpu-secure-memory", 2556 cpu->secure_memory); 2557 } 2558 2559 if (cpu->tag_memory != NULL) { 2560 cpu_address_space_init(cs, ARMASIdx_TagNS, "cpu-tag-memory", 2561 cpu->tag_memory); 2562 if (has_secure) { 2563 cpu_address_space_init(cs, ARMASIdx_TagS, "cpu-tag-memory", 2564 cpu->secure_tag_memory); 2565 } 2566 } 2567 2568 cpu_address_space_init(cs, ARMASIdx_NS, "cpu-memory", cs->memory); 2569 2570 /* No core_count specified, default to smp_cpus. */ 2571 if (cpu->core_count == -1) { 2572 cpu->core_count = smp_cpus; 2573 } 2574 #endif 2575 2576 if (tcg_enabled()) { 2577 int dcz_blocklen = 4 << cpu->dcz_blocksize; 2578 2579 /* 2580 * We only support DCZ blocklen that fits on one page. 2581 * 2582 * Architectually this is always true. However TARGET_PAGE_SIZE 2583 * is variable and, for compatibility with -machine virt-2.7, 2584 * is only 1KiB, as an artifact of legacy ARMv5 subpage support. 2585 * But even then, while the largest architectural DCZ blocklen 2586 * is 2KiB, no cpu actually uses such a large blocklen. 2587 */ 2588 assert(dcz_blocklen <= TARGET_PAGE_SIZE); 2589 2590 /* 2591 * We only support DCZ blocksize >= 2*TAG_GRANULE, which is to say 2592 * both nibbles of each byte storing tag data may be written at once. 2593 * Since TAG_GRANULE is 16, this means that blocklen must be >= 32. 2594 */ 2595 if (cpu_isar_feature(aa64_mte, cpu)) { 2596 assert(dcz_blocklen >= 2 * TAG_GRANULE); 2597 } 2598 } 2599 2600 qemu_init_vcpu(cs); 2601 cpu_reset(cs); 2602 2603 acc->parent_realize(dev, errp); 2604 } 2605 2606 static ObjectClass *arm_cpu_class_by_name(const char *cpu_model) 2607 { 2608 ObjectClass *oc; 2609 char *typename; 2610 char **cpuname; 2611 const char *cpunamestr; 2612 2613 cpuname = g_strsplit(cpu_model, ",", 1); 2614 cpunamestr = cpuname[0]; 2615 #ifdef CONFIG_USER_ONLY 2616 /* For backwards compatibility usermode emulation allows "-cpu any", 2617 * which has the same semantics as "-cpu max". 2618 */ 2619 if (!strcmp(cpunamestr, "any")) { 2620 cpunamestr = "max"; 2621 } 2622 #endif 2623 typename = g_strdup_printf(ARM_CPU_TYPE_NAME("%s"), cpunamestr); 2624 oc = object_class_by_name(typename); 2625 g_strfreev(cpuname); 2626 g_free(typename); 2627 2628 return oc; 2629 } 2630 2631 static const Property arm_cpu_properties[] = { 2632 DEFINE_PROP_UINT64("midr", ARMCPU, midr, 0), 2633 DEFINE_PROP_UINT64("mp-affinity", ARMCPU, 2634 mp_affinity, ARM64_AFFINITY_INVALID), 2635 DEFINE_PROP_INT32("node-id", ARMCPU, node_id, CPU_UNSET_NUMA_NODE_ID), 2636 DEFINE_PROP_INT32("core-count", ARMCPU, core_count, -1), 2637 /* True to default to the backward-compat old CNTFRQ rather than 1Ghz */ 2638 DEFINE_PROP_BOOL("backcompat-cntfrq", ARMCPU, backcompat_cntfrq, false), 2639 DEFINE_PROP_BOOL("backcompat-pauth-default-use-qarma5", ARMCPU, 2640 backcompat_pauth_default_use_qarma5, false), 2641 }; 2642 2643 static const gchar *arm_gdb_arch_name(CPUState *cs) 2644 { 2645 ARMCPU *cpu = ARM_CPU(cs); 2646 CPUARMState *env = &cpu->env; 2647 2648 if (arm_feature(env, ARM_FEATURE_IWMMXT)) { 2649 return "iwmmxt"; 2650 } 2651 return "arm"; 2652 } 2653 2654 #ifndef CONFIG_USER_ONLY 2655 #include "hw/core/sysemu-cpu-ops.h" 2656 2657 static const struct SysemuCPUOps arm_sysemu_ops = { 2658 .get_phys_page_attrs_debug = arm_cpu_get_phys_page_attrs_debug, 2659 .asidx_from_attrs = arm_asidx_from_attrs, 2660 .write_elf32_note = arm_cpu_write_elf32_note, 2661 .write_elf64_note = arm_cpu_write_elf64_note, 2662 .virtio_is_big_endian = arm_cpu_virtio_is_big_endian, 2663 .legacy_vmsd = &vmstate_arm_cpu, 2664 }; 2665 #endif 2666 2667 #ifdef CONFIG_TCG 2668 static const TCGCPUOps arm_tcg_ops = { 2669 .initialize = arm_translate_init, 2670 .translate_code = arm_translate_code, 2671 .synchronize_from_tb = arm_cpu_synchronize_from_tb, 2672 .debug_excp_handler = arm_debug_excp_handler, 2673 .restore_state_to_opc = arm_restore_state_to_opc, 2674 2675 #ifdef CONFIG_USER_ONLY 2676 .record_sigsegv = arm_cpu_record_sigsegv, 2677 .record_sigbus = arm_cpu_record_sigbus, 2678 #else 2679 .tlb_fill_align = arm_cpu_tlb_fill_align, 2680 .cpu_exec_interrupt = arm_cpu_exec_interrupt, 2681 .cpu_exec_halt = arm_cpu_exec_halt, 2682 .do_interrupt = arm_cpu_do_interrupt, 2683 .do_transaction_failed = arm_cpu_do_transaction_failed, 2684 .do_unaligned_access = arm_cpu_do_unaligned_access, 2685 .adjust_watchpoint_address = arm_adjust_watchpoint_address, 2686 .debug_check_watchpoint = arm_debug_check_watchpoint, 2687 .debug_check_breakpoint = arm_debug_check_breakpoint, 2688 #endif /* !CONFIG_USER_ONLY */ 2689 }; 2690 #endif /* CONFIG_TCG */ 2691 2692 static void arm_cpu_class_init(ObjectClass *oc, void *data) 2693 { 2694 ARMCPUClass *acc = ARM_CPU_CLASS(oc); 2695 CPUClass *cc = CPU_CLASS(acc); 2696 DeviceClass *dc = DEVICE_CLASS(oc); 2697 ResettableClass *rc = RESETTABLE_CLASS(oc); 2698 2699 device_class_set_parent_realize(dc, arm_cpu_realizefn, 2700 &acc->parent_realize); 2701 2702 device_class_set_props(dc, arm_cpu_properties); 2703 2704 resettable_class_set_parent_phases(rc, NULL, arm_cpu_reset_hold, NULL, 2705 &acc->parent_phases); 2706 2707 cc->class_by_name = arm_cpu_class_by_name; 2708 cc->has_work = arm_cpu_has_work; 2709 cc->mmu_index = arm_cpu_mmu_index; 2710 cc->dump_state = arm_cpu_dump_state; 2711 cc->set_pc = arm_cpu_set_pc; 2712 cc->get_pc = arm_cpu_get_pc; 2713 cc->gdb_read_register = arm_cpu_gdb_read_register; 2714 cc->gdb_write_register = arm_cpu_gdb_write_register; 2715 #ifndef CONFIG_USER_ONLY 2716 cc->sysemu_ops = &arm_sysemu_ops; 2717 #endif 2718 cc->gdb_arch_name = arm_gdb_arch_name; 2719 cc->gdb_stop_before_watchpoint = true; 2720 cc->disas_set_info = arm_disas_set_info; 2721 2722 #ifdef CONFIG_TCG 2723 cc->tcg_ops = &arm_tcg_ops; 2724 #endif /* CONFIG_TCG */ 2725 } 2726 2727 static void arm_cpu_instance_init(Object *obj) 2728 { 2729 ARMCPUClass *acc = ARM_CPU_GET_CLASS(obj); 2730 2731 acc->info->initfn(obj); 2732 arm_cpu_post_init(obj); 2733 } 2734 2735 static void cpu_register_class_init(ObjectClass *oc, void *data) 2736 { 2737 ARMCPUClass *acc = ARM_CPU_CLASS(oc); 2738 CPUClass *cc = CPU_CLASS(acc); 2739 2740 acc->info = data; 2741 cc->gdb_core_xml_file = "arm-core.xml"; 2742 if (acc->info->deprecation_note) { 2743 cc->deprecation_note = acc->info->deprecation_note; 2744 } 2745 } 2746 2747 void arm_cpu_register(const ARMCPUInfo *info) 2748 { 2749 TypeInfo type_info = { 2750 .parent = TYPE_ARM_CPU, 2751 .instance_init = arm_cpu_instance_init, 2752 .class_init = info->class_init ?: cpu_register_class_init, 2753 .class_data = (void *)info, 2754 }; 2755 2756 type_info.name = g_strdup_printf("%s-" TYPE_ARM_CPU, info->name); 2757 type_register_static(&type_info); 2758 g_free((void *)type_info.name); 2759 } 2760 2761 static const TypeInfo arm_cpu_type_info = { 2762 .name = TYPE_ARM_CPU, 2763 .parent = TYPE_CPU, 2764 .instance_size = sizeof(ARMCPU), 2765 .instance_align = __alignof__(ARMCPU), 2766 .instance_init = arm_cpu_initfn, 2767 .instance_finalize = arm_cpu_finalizefn, 2768 .abstract = true, 2769 .class_size = sizeof(ARMCPUClass), 2770 .class_init = arm_cpu_class_init, 2771 }; 2772 2773 static void arm_cpu_register_types(void) 2774 { 2775 type_register_static(&arm_cpu_type_info); 2776 } 2777 2778 type_init(arm_cpu_register_types) 2779