1 /* 2 * QEMU ARM CPU 3 * 4 * Copyright (c) 2012 SUSE LINUX Products GmbH 5 * 6 * This program is free software; you can redistribute it and/or 7 * modify it under the terms of the GNU General Public License 8 * as published by the Free Software Foundation; either version 2 9 * of the License, or (at your option) any later version. 10 * 11 * This program is distributed in the hope that it will be useful, 12 * but WITHOUT ANY WARRANTY; without even the implied warranty of 13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 14 * GNU General Public License for more details. 15 * 16 * You should have received a copy of the GNU General Public License 17 * along with this program; if not, see 18 * <http://www.gnu.org/licenses/gpl-2.0.html> 19 */ 20 21 #include "qemu/osdep.h" 22 #include "qemu/qemu-print.h" 23 #include "qemu-common.h" 24 #include "target/arm/idau.h" 25 #include "qemu/module.h" 26 #include "qapi/error.h" 27 #include "qapi/visitor.h" 28 #include "cpu.h" 29 #include "internals.h" 30 #include "exec/exec-all.h" 31 #include "hw/qdev-properties.h" 32 #if !defined(CONFIG_USER_ONLY) 33 #include "hw/loader.h" 34 #include "hw/boards.h" 35 #endif 36 #include "sysemu/sysemu.h" 37 #include "sysemu/tcg.h" 38 #include "sysemu/hw_accel.h" 39 #include "kvm_arm.h" 40 #include "disas/capstone.h" 41 #include "fpu/softfloat.h" 42 43 static void arm_cpu_set_pc(CPUState *cs, vaddr value) 44 { 45 ARMCPU *cpu = ARM_CPU(cs); 46 CPUARMState *env = &cpu->env; 47 48 if (is_a64(env)) { 49 env->pc = value; 50 env->thumb = 0; 51 } else { 52 env->regs[15] = value & ~1; 53 env->thumb = value & 1; 54 } 55 } 56 57 static void arm_cpu_synchronize_from_tb(CPUState *cs, TranslationBlock *tb) 58 { 59 ARMCPU *cpu = ARM_CPU(cs); 60 CPUARMState *env = &cpu->env; 61 62 /* 63 * It's OK to look at env for the current mode here, because it's 64 * never possible for an AArch64 TB to chain to an AArch32 TB. 65 */ 66 if (is_a64(env)) { 67 env->pc = tb->pc; 68 } else { 69 env->regs[15] = tb->pc; 70 } 71 } 72 73 static bool arm_cpu_has_work(CPUState *cs) 74 { 75 ARMCPU *cpu = ARM_CPU(cs); 76 77 return (cpu->power_state != PSCI_OFF) 78 && cs->interrupt_request & 79 (CPU_INTERRUPT_FIQ | CPU_INTERRUPT_HARD 80 | CPU_INTERRUPT_VFIQ | CPU_INTERRUPT_VIRQ 81 | CPU_INTERRUPT_EXITTB); 82 } 83 84 void arm_register_pre_el_change_hook(ARMCPU *cpu, ARMELChangeHookFn *hook, 85 void *opaque) 86 { 87 ARMELChangeHook *entry = g_new0(ARMELChangeHook, 1); 88 89 entry->hook = hook; 90 entry->opaque = opaque; 91 92 QLIST_INSERT_HEAD(&cpu->pre_el_change_hooks, entry, node); 93 } 94 95 void arm_register_el_change_hook(ARMCPU *cpu, ARMELChangeHookFn *hook, 96 void *opaque) 97 { 98 ARMELChangeHook *entry = g_new0(ARMELChangeHook, 1); 99 100 entry->hook = hook; 101 entry->opaque = opaque; 102 103 QLIST_INSERT_HEAD(&cpu->el_change_hooks, entry, node); 104 } 105 106 static void cp_reg_reset(gpointer key, gpointer value, gpointer opaque) 107 { 108 /* Reset a single ARMCPRegInfo register */ 109 ARMCPRegInfo *ri = value; 110 ARMCPU *cpu = opaque; 111 112 if (ri->type & (ARM_CP_SPECIAL | ARM_CP_ALIAS)) { 113 return; 114 } 115 116 if (ri->resetfn) { 117 ri->resetfn(&cpu->env, ri); 118 return; 119 } 120 121 /* A zero offset is never possible as it would be regs[0] 122 * so we use it to indicate that reset is being handled elsewhere. 123 * This is basically only used for fields in non-core coprocessors 124 * (like the pxa2xx ones). 125 */ 126 if (!ri->fieldoffset) { 127 return; 128 } 129 130 if (cpreg_field_is_64bit(ri)) { 131 CPREG_FIELD64(&cpu->env, ri) = ri->resetvalue; 132 } else { 133 CPREG_FIELD32(&cpu->env, ri) = ri->resetvalue; 134 } 135 } 136 137 static void cp_reg_check_reset(gpointer key, gpointer value, gpointer opaque) 138 { 139 /* Purely an assertion check: we've already done reset once, 140 * so now check that running the reset for the cpreg doesn't 141 * change its value. This traps bugs where two different cpregs 142 * both try to reset the same state field but to different values. 143 */ 144 ARMCPRegInfo *ri = value; 145 ARMCPU *cpu = opaque; 146 uint64_t oldvalue, newvalue; 147 148 if (ri->type & (ARM_CP_SPECIAL | ARM_CP_ALIAS | ARM_CP_NO_RAW)) { 149 return; 150 } 151 152 oldvalue = read_raw_cp_reg(&cpu->env, ri); 153 cp_reg_reset(key, value, opaque); 154 newvalue = read_raw_cp_reg(&cpu->env, ri); 155 assert(oldvalue == newvalue); 156 } 157 158 static void arm_cpu_reset(DeviceState *dev) 159 { 160 CPUState *s = CPU(dev); 161 ARMCPU *cpu = ARM_CPU(s); 162 ARMCPUClass *acc = ARM_CPU_GET_CLASS(cpu); 163 CPUARMState *env = &cpu->env; 164 165 acc->parent_reset(dev); 166 167 memset(env, 0, offsetof(CPUARMState, end_reset_fields)); 168 169 g_hash_table_foreach(cpu->cp_regs, cp_reg_reset, cpu); 170 g_hash_table_foreach(cpu->cp_regs, cp_reg_check_reset, cpu); 171 172 env->vfp.xregs[ARM_VFP_FPSID] = cpu->reset_fpsid; 173 env->vfp.xregs[ARM_VFP_MVFR0] = cpu->isar.mvfr0; 174 env->vfp.xregs[ARM_VFP_MVFR1] = cpu->isar.mvfr1; 175 env->vfp.xregs[ARM_VFP_MVFR2] = cpu->isar.mvfr2; 176 177 cpu->power_state = cpu->start_powered_off ? PSCI_OFF : PSCI_ON; 178 s->halted = cpu->start_powered_off; 179 180 if (arm_feature(env, ARM_FEATURE_IWMMXT)) { 181 env->iwmmxt.cregs[ARM_IWMMXT_wCID] = 0x69051000 | 'Q'; 182 } 183 184 if (arm_feature(env, ARM_FEATURE_AARCH64)) { 185 /* 64 bit CPUs always start in 64 bit mode */ 186 env->aarch64 = 1; 187 #if defined(CONFIG_USER_ONLY) 188 env->pstate = PSTATE_MODE_EL0t; 189 /* Userspace expects access to DC ZVA, CTL_EL0 and the cache ops */ 190 env->cp15.sctlr_el[1] |= SCTLR_UCT | SCTLR_UCI | SCTLR_DZE; 191 /* Enable all PAC keys. */ 192 env->cp15.sctlr_el[1] |= (SCTLR_EnIA | SCTLR_EnIB | 193 SCTLR_EnDA | SCTLR_EnDB); 194 /* and to the FP/Neon instructions */ 195 env->cp15.cpacr_el1 = deposit64(env->cp15.cpacr_el1, 20, 2, 3); 196 /* and to the SVE instructions */ 197 env->cp15.cpacr_el1 = deposit64(env->cp15.cpacr_el1, 16, 2, 3); 198 /* with reasonable vector length */ 199 if (cpu_isar_feature(aa64_sve, cpu)) { 200 env->vfp.zcr_el[1] = MIN(cpu->sve_max_vq - 1, 3); 201 } 202 /* 203 * Enable TBI0 and TBI1. While the real kernel only enables TBI0, 204 * turning on both here will produce smaller code and otherwise 205 * make no difference to the user-level emulation. 206 * 207 * In sve_probe_page, we assume that this is set. 208 * Do not modify this without other changes. 209 */ 210 env->cp15.tcr_el[1].raw_tcr = (3ULL << 37); 211 #else 212 /* Reset into the highest available EL */ 213 if (arm_feature(env, ARM_FEATURE_EL3)) { 214 env->pstate = PSTATE_MODE_EL3h; 215 } else if (arm_feature(env, ARM_FEATURE_EL2)) { 216 env->pstate = PSTATE_MODE_EL2h; 217 } else { 218 env->pstate = PSTATE_MODE_EL1h; 219 } 220 env->pc = cpu->rvbar; 221 #endif 222 } else { 223 #if defined(CONFIG_USER_ONLY) 224 /* Userspace expects access to cp10 and cp11 for FP/Neon */ 225 env->cp15.cpacr_el1 = deposit64(env->cp15.cpacr_el1, 20, 4, 0xf); 226 #endif 227 } 228 229 #if defined(CONFIG_USER_ONLY) 230 env->uncached_cpsr = ARM_CPU_MODE_USR; 231 /* For user mode we must enable access to coprocessors */ 232 env->vfp.xregs[ARM_VFP_FPEXC] = 1 << 30; 233 if (arm_feature(env, ARM_FEATURE_IWMMXT)) { 234 env->cp15.c15_cpar = 3; 235 } else if (arm_feature(env, ARM_FEATURE_XSCALE)) { 236 env->cp15.c15_cpar = 1; 237 } 238 #else 239 240 /* 241 * If the highest available EL is EL2, AArch32 will start in Hyp 242 * mode; otherwise it starts in SVC. Note that if we start in 243 * AArch64 then these values in the uncached_cpsr will be ignored. 244 */ 245 if (arm_feature(env, ARM_FEATURE_EL2) && 246 !arm_feature(env, ARM_FEATURE_EL3)) { 247 env->uncached_cpsr = ARM_CPU_MODE_HYP; 248 } else { 249 env->uncached_cpsr = ARM_CPU_MODE_SVC; 250 } 251 env->daif = PSTATE_D | PSTATE_A | PSTATE_I | PSTATE_F; 252 253 if (arm_feature(env, ARM_FEATURE_M)) { 254 uint32_t initial_msp; /* Loaded from 0x0 */ 255 uint32_t initial_pc; /* Loaded from 0x4 */ 256 uint8_t *rom; 257 uint32_t vecbase; 258 259 if (arm_feature(env, ARM_FEATURE_M_SECURITY)) { 260 env->v7m.secure = true; 261 } else { 262 /* This bit resets to 0 if security is supported, but 1 if 263 * it is not. The bit is not present in v7M, but we set it 264 * here so we can avoid having to make checks on it conditional 265 * on ARM_FEATURE_V8 (we don't let the guest see the bit). 266 */ 267 env->v7m.aircr = R_V7M_AIRCR_BFHFNMINS_MASK; 268 /* 269 * Set NSACR to indicate "NS access permitted to everything"; 270 * this avoids having to have all the tests of it being 271 * conditional on ARM_FEATURE_M_SECURITY. Note also that from 272 * v8.1M the guest-visible value of NSACR in a CPU without the 273 * Security Extension is 0xcff. 274 */ 275 env->v7m.nsacr = 0xcff; 276 } 277 278 /* In v7M the reset value of this bit is IMPDEF, but ARM recommends 279 * that it resets to 1, so QEMU always does that rather than making 280 * it dependent on CPU model. In v8M it is RES1. 281 */ 282 env->v7m.ccr[M_REG_NS] = R_V7M_CCR_STKALIGN_MASK; 283 env->v7m.ccr[M_REG_S] = R_V7M_CCR_STKALIGN_MASK; 284 if (arm_feature(env, ARM_FEATURE_V8)) { 285 /* in v8M the NONBASETHRDENA bit [0] is RES1 */ 286 env->v7m.ccr[M_REG_NS] |= R_V7M_CCR_NONBASETHRDENA_MASK; 287 env->v7m.ccr[M_REG_S] |= R_V7M_CCR_NONBASETHRDENA_MASK; 288 } 289 if (!arm_feature(env, ARM_FEATURE_M_MAIN)) { 290 env->v7m.ccr[M_REG_NS] |= R_V7M_CCR_UNALIGN_TRP_MASK; 291 env->v7m.ccr[M_REG_S] |= R_V7M_CCR_UNALIGN_TRP_MASK; 292 } 293 294 if (cpu_isar_feature(aa32_vfp_simd, cpu)) { 295 env->v7m.fpccr[M_REG_NS] = R_V7M_FPCCR_ASPEN_MASK; 296 env->v7m.fpccr[M_REG_S] = R_V7M_FPCCR_ASPEN_MASK | 297 R_V7M_FPCCR_LSPEN_MASK | R_V7M_FPCCR_S_MASK; 298 } 299 /* Unlike A/R profile, M profile defines the reset LR value */ 300 env->regs[14] = 0xffffffff; 301 302 env->v7m.vecbase[M_REG_S] = cpu->init_svtor & 0xffffff80; 303 304 /* Load the initial SP and PC from offset 0 and 4 in the vector table */ 305 vecbase = env->v7m.vecbase[env->v7m.secure]; 306 rom = rom_ptr(vecbase, 8); 307 if (rom) { 308 /* Address zero is covered by ROM which hasn't yet been 309 * copied into physical memory. 310 */ 311 initial_msp = ldl_p(rom); 312 initial_pc = ldl_p(rom + 4); 313 } else { 314 /* Address zero not covered by a ROM blob, or the ROM blob 315 * is in non-modifiable memory and this is a second reset after 316 * it got copied into memory. In the latter case, rom_ptr 317 * will return a NULL pointer and we should use ldl_phys instead. 318 */ 319 initial_msp = ldl_phys(s->as, vecbase); 320 initial_pc = ldl_phys(s->as, vecbase + 4); 321 } 322 323 env->regs[13] = initial_msp & 0xFFFFFFFC; 324 env->regs[15] = initial_pc & ~1; 325 env->thumb = initial_pc & 1; 326 } 327 328 /* AArch32 has a hard highvec setting of 0xFFFF0000. If we are currently 329 * executing as AArch32 then check if highvecs are enabled and 330 * adjust the PC accordingly. 331 */ 332 if (A32_BANKED_CURRENT_REG_GET(env, sctlr) & SCTLR_V) { 333 env->regs[15] = 0xFFFF0000; 334 } 335 336 /* M profile requires that reset clears the exclusive monitor; 337 * A profile does not, but clearing it makes more sense than having it 338 * set with an exclusive access on address zero. 339 */ 340 arm_clear_exclusive(env); 341 342 env->vfp.xregs[ARM_VFP_FPEXC] = 0; 343 #endif 344 345 if (arm_feature(env, ARM_FEATURE_PMSA)) { 346 if (cpu->pmsav7_dregion > 0) { 347 if (arm_feature(env, ARM_FEATURE_V8)) { 348 memset(env->pmsav8.rbar[M_REG_NS], 0, 349 sizeof(*env->pmsav8.rbar[M_REG_NS]) 350 * cpu->pmsav7_dregion); 351 memset(env->pmsav8.rlar[M_REG_NS], 0, 352 sizeof(*env->pmsav8.rlar[M_REG_NS]) 353 * cpu->pmsav7_dregion); 354 if (arm_feature(env, ARM_FEATURE_M_SECURITY)) { 355 memset(env->pmsav8.rbar[M_REG_S], 0, 356 sizeof(*env->pmsav8.rbar[M_REG_S]) 357 * cpu->pmsav7_dregion); 358 memset(env->pmsav8.rlar[M_REG_S], 0, 359 sizeof(*env->pmsav8.rlar[M_REG_S]) 360 * cpu->pmsav7_dregion); 361 } 362 } else if (arm_feature(env, ARM_FEATURE_V7)) { 363 memset(env->pmsav7.drbar, 0, 364 sizeof(*env->pmsav7.drbar) * cpu->pmsav7_dregion); 365 memset(env->pmsav7.drsr, 0, 366 sizeof(*env->pmsav7.drsr) * cpu->pmsav7_dregion); 367 memset(env->pmsav7.dracr, 0, 368 sizeof(*env->pmsav7.dracr) * cpu->pmsav7_dregion); 369 } 370 } 371 env->pmsav7.rnr[M_REG_NS] = 0; 372 env->pmsav7.rnr[M_REG_S] = 0; 373 env->pmsav8.mair0[M_REG_NS] = 0; 374 env->pmsav8.mair0[M_REG_S] = 0; 375 env->pmsav8.mair1[M_REG_NS] = 0; 376 env->pmsav8.mair1[M_REG_S] = 0; 377 } 378 379 if (arm_feature(env, ARM_FEATURE_M_SECURITY)) { 380 if (cpu->sau_sregion > 0) { 381 memset(env->sau.rbar, 0, sizeof(*env->sau.rbar) * cpu->sau_sregion); 382 memset(env->sau.rlar, 0, sizeof(*env->sau.rlar) * cpu->sau_sregion); 383 } 384 env->sau.rnr = 0; 385 /* SAU_CTRL reset value is IMPDEF; we choose 0, which is what 386 * the Cortex-M33 does. 387 */ 388 env->sau.ctrl = 0; 389 } 390 391 set_flush_to_zero(1, &env->vfp.standard_fp_status); 392 set_flush_inputs_to_zero(1, &env->vfp.standard_fp_status); 393 set_default_nan_mode(1, &env->vfp.standard_fp_status); 394 set_default_nan_mode(1, &env->vfp.standard_fp_status_f16); 395 set_float_detect_tininess(float_tininess_before_rounding, 396 &env->vfp.fp_status); 397 set_float_detect_tininess(float_tininess_before_rounding, 398 &env->vfp.standard_fp_status); 399 set_float_detect_tininess(float_tininess_before_rounding, 400 &env->vfp.fp_status_f16); 401 set_float_detect_tininess(float_tininess_before_rounding, 402 &env->vfp.standard_fp_status_f16); 403 #ifndef CONFIG_USER_ONLY 404 if (kvm_enabled()) { 405 kvm_arm_reset_vcpu(cpu); 406 } 407 #endif 408 409 hw_breakpoint_update_all(cpu); 410 hw_watchpoint_update_all(cpu); 411 arm_rebuild_hflags(env); 412 } 413 414 static inline bool arm_excp_unmasked(CPUState *cs, unsigned int excp_idx, 415 unsigned int target_el, 416 unsigned int cur_el, bool secure, 417 uint64_t hcr_el2) 418 { 419 CPUARMState *env = cs->env_ptr; 420 bool pstate_unmasked; 421 bool unmasked = false; 422 423 /* 424 * Don't take exceptions if they target a lower EL. 425 * This check should catch any exceptions that would not be taken 426 * but left pending. 427 */ 428 if (cur_el > target_el) { 429 return false; 430 } 431 432 switch (excp_idx) { 433 case EXCP_FIQ: 434 pstate_unmasked = !(env->daif & PSTATE_F); 435 break; 436 437 case EXCP_IRQ: 438 pstate_unmasked = !(env->daif & PSTATE_I); 439 break; 440 441 case EXCP_VFIQ: 442 if (secure || !(hcr_el2 & HCR_FMO) || (hcr_el2 & HCR_TGE)) { 443 /* VFIQs are only taken when hypervized and non-secure. */ 444 return false; 445 } 446 return !(env->daif & PSTATE_F); 447 case EXCP_VIRQ: 448 if (secure || !(hcr_el2 & HCR_IMO) || (hcr_el2 & HCR_TGE)) { 449 /* VIRQs are only taken when hypervized and non-secure. */ 450 return false; 451 } 452 return !(env->daif & PSTATE_I); 453 default: 454 g_assert_not_reached(); 455 } 456 457 /* 458 * Use the target EL, current execution state and SCR/HCR settings to 459 * determine whether the corresponding CPSR bit is used to mask the 460 * interrupt. 461 */ 462 if ((target_el > cur_el) && (target_el != 1)) { 463 /* Exceptions targeting a higher EL may not be maskable */ 464 if (arm_feature(env, ARM_FEATURE_AARCH64)) { 465 /* 466 * 64-bit masking rules are simple: exceptions to EL3 467 * can't be masked, and exceptions to EL2 can only be 468 * masked from Secure state. The HCR and SCR settings 469 * don't affect the masking logic, only the interrupt routing. 470 */ 471 if (target_el == 3 || !secure) { 472 unmasked = true; 473 } 474 } else { 475 /* 476 * The old 32-bit-only environment has a more complicated 477 * masking setup. HCR and SCR bits not only affect interrupt 478 * routing but also change the behaviour of masking. 479 */ 480 bool hcr, scr; 481 482 switch (excp_idx) { 483 case EXCP_FIQ: 484 /* 485 * If FIQs are routed to EL3 or EL2 then there are cases where 486 * we override the CPSR.F in determining if the exception is 487 * masked or not. If neither of these are set then we fall back 488 * to the CPSR.F setting otherwise we further assess the state 489 * below. 490 */ 491 hcr = hcr_el2 & HCR_FMO; 492 scr = (env->cp15.scr_el3 & SCR_FIQ); 493 494 /* 495 * When EL3 is 32-bit, the SCR.FW bit controls whether the 496 * CPSR.F bit masks FIQ interrupts when taken in non-secure 497 * state. If SCR.FW is set then FIQs can be masked by CPSR.F 498 * when non-secure but only when FIQs are only routed to EL3. 499 */ 500 scr = scr && !((env->cp15.scr_el3 & SCR_FW) && !hcr); 501 break; 502 case EXCP_IRQ: 503 /* 504 * When EL3 execution state is 32-bit, if HCR.IMO is set then 505 * we may override the CPSR.I masking when in non-secure state. 506 * The SCR.IRQ setting has already been taken into consideration 507 * when setting the target EL, so it does not have a further 508 * affect here. 509 */ 510 hcr = hcr_el2 & HCR_IMO; 511 scr = false; 512 break; 513 default: 514 g_assert_not_reached(); 515 } 516 517 if ((scr || hcr) && !secure) { 518 unmasked = true; 519 } 520 } 521 } 522 523 /* 524 * The PSTATE bits only mask the interrupt if we have not overriden the 525 * ability above. 526 */ 527 return unmasked || pstate_unmasked; 528 } 529 530 bool arm_cpu_exec_interrupt(CPUState *cs, int interrupt_request) 531 { 532 CPUClass *cc = CPU_GET_CLASS(cs); 533 CPUARMState *env = cs->env_ptr; 534 uint32_t cur_el = arm_current_el(env); 535 bool secure = arm_is_secure(env); 536 uint64_t hcr_el2 = arm_hcr_el2_eff(env); 537 uint32_t target_el; 538 uint32_t excp_idx; 539 540 /* The prioritization of interrupts is IMPLEMENTATION DEFINED. */ 541 542 if (interrupt_request & CPU_INTERRUPT_FIQ) { 543 excp_idx = EXCP_FIQ; 544 target_el = arm_phys_excp_target_el(cs, excp_idx, cur_el, secure); 545 if (arm_excp_unmasked(cs, excp_idx, target_el, 546 cur_el, secure, hcr_el2)) { 547 goto found; 548 } 549 } 550 if (interrupt_request & CPU_INTERRUPT_HARD) { 551 excp_idx = EXCP_IRQ; 552 target_el = arm_phys_excp_target_el(cs, excp_idx, cur_el, secure); 553 if (arm_excp_unmasked(cs, excp_idx, target_el, 554 cur_el, secure, hcr_el2)) { 555 goto found; 556 } 557 } 558 if (interrupt_request & CPU_INTERRUPT_VIRQ) { 559 excp_idx = EXCP_VIRQ; 560 target_el = 1; 561 if (arm_excp_unmasked(cs, excp_idx, target_el, 562 cur_el, secure, hcr_el2)) { 563 goto found; 564 } 565 } 566 if (interrupt_request & CPU_INTERRUPT_VFIQ) { 567 excp_idx = EXCP_VFIQ; 568 target_el = 1; 569 if (arm_excp_unmasked(cs, excp_idx, target_el, 570 cur_el, secure, hcr_el2)) { 571 goto found; 572 } 573 } 574 return false; 575 576 found: 577 cs->exception_index = excp_idx; 578 env->exception.target_el = target_el; 579 cc->do_interrupt(cs); 580 return true; 581 } 582 583 void arm_cpu_update_virq(ARMCPU *cpu) 584 { 585 /* 586 * Update the interrupt level for VIRQ, which is the logical OR of 587 * the HCR_EL2.VI bit and the input line level from the GIC. 588 */ 589 CPUARMState *env = &cpu->env; 590 CPUState *cs = CPU(cpu); 591 592 bool new_state = (env->cp15.hcr_el2 & HCR_VI) || 593 (env->irq_line_state & CPU_INTERRUPT_VIRQ); 594 595 if (new_state != ((cs->interrupt_request & CPU_INTERRUPT_VIRQ) != 0)) { 596 if (new_state) { 597 cpu_interrupt(cs, CPU_INTERRUPT_VIRQ); 598 } else { 599 cpu_reset_interrupt(cs, CPU_INTERRUPT_VIRQ); 600 } 601 } 602 } 603 604 void arm_cpu_update_vfiq(ARMCPU *cpu) 605 { 606 /* 607 * Update the interrupt level for VFIQ, which is the logical OR of 608 * the HCR_EL2.VF bit and the input line level from the GIC. 609 */ 610 CPUARMState *env = &cpu->env; 611 CPUState *cs = CPU(cpu); 612 613 bool new_state = (env->cp15.hcr_el2 & HCR_VF) || 614 (env->irq_line_state & CPU_INTERRUPT_VFIQ); 615 616 if (new_state != ((cs->interrupt_request & CPU_INTERRUPT_VFIQ) != 0)) { 617 if (new_state) { 618 cpu_interrupt(cs, CPU_INTERRUPT_VFIQ); 619 } else { 620 cpu_reset_interrupt(cs, CPU_INTERRUPT_VFIQ); 621 } 622 } 623 } 624 625 #ifndef CONFIG_USER_ONLY 626 static void arm_cpu_set_irq(void *opaque, int irq, int level) 627 { 628 ARMCPU *cpu = opaque; 629 CPUARMState *env = &cpu->env; 630 CPUState *cs = CPU(cpu); 631 static const int mask[] = { 632 [ARM_CPU_IRQ] = CPU_INTERRUPT_HARD, 633 [ARM_CPU_FIQ] = CPU_INTERRUPT_FIQ, 634 [ARM_CPU_VIRQ] = CPU_INTERRUPT_VIRQ, 635 [ARM_CPU_VFIQ] = CPU_INTERRUPT_VFIQ 636 }; 637 638 if (level) { 639 env->irq_line_state |= mask[irq]; 640 } else { 641 env->irq_line_state &= ~mask[irq]; 642 } 643 644 switch (irq) { 645 case ARM_CPU_VIRQ: 646 assert(arm_feature(env, ARM_FEATURE_EL2)); 647 arm_cpu_update_virq(cpu); 648 break; 649 case ARM_CPU_VFIQ: 650 assert(arm_feature(env, ARM_FEATURE_EL2)); 651 arm_cpu_update_vfiq(cpu); 652 break; 653 case ARM_CPU_IRQ: 654 case ARM_CPU_FIQ: 655 if (level) { 656 cpu_interrupt(cs, mask[irq]); 657 } else { 658 cpu_reset_interrupt(cs, mask[irq]); 659 } 660 break; 661 default: 662 g_assert_not_reached(); 663 } 664 } 665 666 static void arm_cpu_kvm_set_irq(void *opaque, int irq, int level) 667 { 668 #ifdef CONFIG_KVM 669 ARMCPU *cpu = opaque; 670 CPUARMState *env = &cpu->env; 671 CPUState *cs = CPU(cpu); 672 uint32_t linestate_bit; 673 int irq_id; 674 675 switch (irq) { 676 case ARM_CPU_IRQ: 677 irq_id = KVM_ARM_IRQ_CPU_IRQ; 678 linestate_bit = CPU_INTERRUPT_HARD; 679 break; 680 case ARM_CPU_FIQ: 681 irq_id = KVM_ARM_IRQ_CPU_FIQ; 682 linestate_bit = CPU_INTERRUPT_FIQ; 683 break; 684 default: 685 g_assert_not_reached(); 686 } 687 688 if (level) { 689 env->irq_line_state |= linestate_bit; 690 } else { 691 env->irq_line_state &= ~linestate_bit; 692 } 693 kvm_arm_set_irq(cs->cpu_index, KVM_ARM_IRQ_TYPE_CPU, irq_id, !!level); 694 #endif 695 } 696 697 static bool arm_cpu_virtio_is_big_endian(CPUState *cs) 698 { 699 ARMCPU *cpu = ARM_CPU(cs); 700 CPUARMState *env = &cpu->env; 701 702 cpu_synchronize_state(cs); 703 return arm_cpu_data_is_big_endian(env); 704 } 705 706 #endif 707 708 static int 709 print_insn_thumb1(bfd_vma pc, disassemble_info *info) 710 { 711 return print_insn_arm(pc | 1, info); 712 } 713 714 static void arm_disas_set_info(CPUState *cpu, disassemble_info *info) 715 { 716 ARMCPU *ac = ARM_CPU(cpu); 717 CPUARMState *env = &ac->env; 718 bool sctlr_b; 719 720 if (is_a64(env)) { 721 /* We might not be compiled with the A64 disassembler 722 * because it needs a C++ compiler. Leave print_insn 723 * unset in this case to use the caller default behaviour. 724 */ 725 #if defined(CONFIG_ARM_A64_DIS) 726 info->print_insn = print_insn_arm_a64; 727 #endif 728 info->cap_arch = CS_ARCH_ARM64; 729 info->cap_insn_unit = 4; 730 info->cap_insn_split = 4; 731 } else { 732 int cap_mode; 733 if (env->thumb) { 734 info->print_insn = print_insn_thumb1; 735 info->cap_insn_unit = 2; 736 info->cap_insn_split = 4; 737 cap_mode = CS_MODE_THUMB; 738 } else { 739 info->print_insn = print_insn_arm; 740 info->cap_insn_unit = 4; 741 info->cap_insn_split = 4; 742 cap_mode = CS_MODE_ARM; 743 } 744 if (arm_feature(env, ARM_FEATURE_V8)) { 745 cap_mode |= CS_MODE_V8; 746 } 747 if (arm_feature(env, ARM_FEATURE_M)) { 748 cap_mode |= CS_MODE_MCLASS; 749 } 750 info->cap_arch = CS_ARCH_ARM; 751 info->cap_mode = cap_mode; 752 } 753 754 sctlr_b = arm_sctlr_b(env); 755 if (bswap_code(sctlr_b)) { 756 #ifdef TARGET_WORDS_BIGENDIAN 757 info->endian = BFD_ENDIAN_LITTLE; 758 #else 759 info->endian = BFD_ENDIAN_BIG; 760 #endif 761 } 762 info->flags &= ~INSN_ARM_BE32; 763 #ifndef CONFIG_USER_ONLY 764 if (sctlr_b) { 765 info->flags |= INSN_ARM_BE32; 766 } 767 #endif 768 } 769 770 #ifdef TARGET_AARCH64 771 772 static void aarch64_cpu_dump_state(CPUState *cs, FILE *f, int flags) 773 { 774 ARMCPU *cpu = ARM_CPU(cs); 775 CPUARMState *env = &cpu->env; 776 uint32_t psr = pstate_read(env); 777 int i; 778 int el = arm_current_el(env); 779 const char *ns_status; 780 781 qemu_fprintf(f, " PC=%016" PRIx64 " ", env->pc); 782 for (i = 0; i < 32; i++) { 783 if (i == 31) { 784 qemu_fprintf(f, " SP=%016" PRIx64 "\n", env->xregs[i]); 785 } else { 786 qemu_fprintf(f, "X%02d=%016" PRIx64 "%s", i, env->xregs[i], 787 (i + 2) % 3 ? " " : "\n"); 788 } 789 } 790 791 if (arm_feature(env, ARM_FEATURE_EL3) && el != 3) { 792 ns_status = env->cp15.scr_el3 & SCR_NS ? "NS " : "S "; 793 } else { 794 ns_status = ""; 795 } 796 qemu_fprintf(f, "PSTATE=%08x %c%c%c%c %sEL%d%c", 797 psr, 798 psr & PSTATE_N ? 'N' : '-', 799 psr & PSTATE_Z ? 'Z' : '-', 800 psr & PSTATE_C ? 'C' : '-', 801 psr & PSTATE_V ? 'V' : '-', 802 ns_status, 803 el, 804 psr & PSTATE_SP ? 'h' : 't'); 805 806 if (cpu_isar_feature(aa64_bti, cpu)) { 807 qemu_fprintf(f, " BTYPE=%d", (psr & PSTATE_BTYPE) >> 10); 808 } 809 if (!(flags & CPU_DUMP_FPU)) { 810 qemu_fprintf(f, "\n"); 811 return; 812 } 813 if (fp_exception_el(env, el) != 0) { 814 qemu_fprintf(f, " FPU disabled\n"); 815 return; 816 } 817 qemu_fprintf(f, " FPCR=%08x FPSR=%08x\n", 818 vfp_get_fpcr(env), vfp_get_fpsr(env)); 819 820 if (cpu_isar_feature(aa64_sve, cpu) && sve_exception_el(env, el) == 0) { 821 int j, zcr_len = sve_zcr_len_for_el(env, el); 822 823 for (i = 0; i <= FFR_PRED_NUM; i++) { 824 bool eol; 825 if (i == FFR_PRED_NUM) { 826 qemu_fprintf(f, "FFR="); 827 /* It's last, so end the line. */ 828 eol = true; 829 } else { 830 qemu_fprintf(f, "P%02d=", i); 831 switch (zcr_len) { 832 case 0: 833 eol = i % 8 == 7; 834 break; 835 case 1: 836 eol = i % 6 == 5; 837 break; 838 case 2: 839 case 3: 840 eol = i % 3 == 2; 841 break; 842 default: 843 /* More than one quadword per predicate. */ 844 eol = true; 845 break; 846 } 847 } 848 for (j = zcr_len / 4; j >= 0; j--) { 849 int digits; 850 if (j * 4 + 4 <= zcr_len + 1) { 851 digits = 16; 852 } else { 853 digits = (zcr_len % 4 + 1) * 4; 854 } 855 qemu_fprintf(f, "%0*" PRIx64 "%s", digits, 856 env->vfp.pregs[i].p[j], 857 j ? ":" : eol ? "\n" : " "); 858 } 859 } 860 861 for (i = 0; i < 32; i++) { 862 if (zcr_len == 0) { 863 qemu_fprintf(f, "Z%02d=%016" PRIx64 ":%016" PRIx64 "%s", 864 i, env->vfp.zregs[i].d[1], 865 env->vfp.zregs[i].d[0], i & 1 ? "\n" : " "); 866 } else if (zcr_len == 1) { 867 qemu_fprintf(f, "Z%02d=%016" PRIx64 ":%016" PRIx64 868 ":%016" PRIx64 ":%016" PRIx64 "\n", 869 i, env->vfp.zregs[i].d[3], env->vfp.zregs[i].d[2], 870 env->vfp.zregs[i].d[1], env->vfp.zregs[i].d[0]); 871 } else { 872 for (j = zcr_len; j >= 0; j--) { 873 bool odd = (zcr_len - j) % 2 != 0; 874 if (j == zcr_len) { 875 qemu_fprintf(f, "Z%02d[%x-%x]=", i, j, j - 1); 876 } else if (!odd) { 877 if (j > 0) { 878 qemu_fprintf(f, " [%x-%x]=", j, j - 1); 879 } else { 880 qemu_fprintf(f, " [%x]=", j); 881 } 882 } 883 qemu_fprintf(f, "%016" PRIx64 ":%016" PRIx64 "%s", 884 env->vfp.zregs[i].d[j * 2 + 1], 885 env->vfp.zregs[i].d[j * 2], 886 odd || j == 0 ? "\n" : ":"); 887 } 888 } 889 } 890 } else { 891 for (i = 0; i < 32; i++) { 892 uint64_t *q = aa64_vfp_qreg(env, i); 893 qemu_fprintf(f, "Q%02d=%016" PRIx64 ":%016" PRIx64 "%s", 894 i, q[1], q[0], (i & 1 ? "\n" : " ")); 895 } 896 } 897 } 898 899 #else 900 901 static inline void aarch64_cpu_dump_state(CPUState *cs, FILE *f, int flags) 902 { 903 g_assert_not_reached(); 904 } 905 906 #endif 907 908 static void arm_cpu_dump_state(CPUState *cs, FILE *f, int flags) 909 { 910 ARMCPU *cpu = ARM_CPU(cs); 911 CPUARMState *env = &cpu->env; 912 int i; 913 914 if (is_a64(env)) { 915 aarch64_cpu_dump_state(cs, f, flags); 916 return; 917 } 918 919 for (i = 0; i < 16; i++) { 920 qemu_fprintf(f, "R%02d=%08x", i, env->regs[i]); 921 if ((i % 4) == 3) { 922 qemu_fprintf(f, "\n"); 923 } else { 924 qemu_fprintf(f, " "); 925 } 926 } 927 928 if (arm_feature(env, ARM_FEATURE_M)) { 929 uint32_t xpsr = xpsr_read(env); 930 const char *mode; 931 const char *ns_status = ""; 932 933 if (arm_feature(env, ARM_FEATURE_M_SECURITY)) { 934 ns_status = env->v7m.secure ? "S " : "NS "; 935 } 936 937 if (xpsr & XPSR_EXCP) { 938 mode = "handler"; 939 } else { 940 if (env->v7m.control[env->v7m.secure] & R_V7M_CONTROL_NPRIV_MASK) { 941 mode = "unpriv-thread"; 942 } else { 943 mode = "priv-thread"; 944 } 945 } 946 947 qemu_fprintf(f, "XPSR=%08x %c%c%c%c %c %s%s\n", 948 xpsr, 949 xpsr & XPSR_N ? 'N' : '-', 950 xpsr & XPSR_Z ? 'Z' : '-', 951 xpsr & XPSR_C ? 'C' : '-', 952 xpsr & XPSR_V ? 'V' : '-', 953 xpsr & XPSR_T ? 'T' : 'A', 954 ns_status, 955 mode); 956 } else { 957 uint32_t psr = cpsr_read(env); 958 const char *ns_status = ""; 959 960 if (arm_feature(env, ARM_FEATURE_EL3) && 961 (psr & CPSR_M) != ARM_CPU_MODE_MON) { 962 ns_status = env->cp15.scr_el3 & SCR_NS ? "NS " : "S "; 963 } 964 965 qemu_fprintf(f, "PSR=%08x %c%c%c%c %c %s%s%d\n", 966 psr, 967 psr & CPSR_N ? 'N' : '-', 968 psr & CPSR_Z ? 'Z' : '-', 969 psr & CPSR_C ? 'C' : '-', 970 psr & CPSR_V ? 'V' : '-', 971 psr & CPSR_T ? 'T' : 'A', 972 ns_status, 973 aarch32_mode_name(psr), (psr & 0x10) ? 32 : 26); 974 } 975 976 if (flags & CPU_DUMP_FPU) { 977 int numvfpregs = 0; 978 if (cpu_isar_feature(aa32_simd_r32, cpu)) { 979 numvfpregs = 32; 980 } else if (cpu_isar_feature(aa32_vfp_simd, cpu)) { 981 numvfpregs = 16; 982 } 983 for (i = 0; i < numvfpregs; i++) { 984 uint64_t v = *aa32_vfp_dreg(env, i); 985 qemu_fprintf(f, "s%02d=%08x s%02d=%08x d%02d=%016" PRIx64 "\n", 986 i * 2, (uint32_t)v, 987 i * 2 + 1, (uint32_t)(v >> 32), 988 i, v); 989 } 990 qemu_fprintf(f, "FPSCR: %08x\n", vfp_get_fpscr(env)); 991 } 992 } 993 994 uint64_t arm_cpu_mp_affinity(int idx, uint8_t clustersz) 995 { 996 uint32_t Aff1 = idx / clustersz; 997 uint32_t Aff0 = idx % clustersz; 998 return (Aff1 << ARM_AFF1_SHIFT) | Aff0; 999 } 1000 1001 static void cpreg_hashtable_data_destroy(gpointer data) 1002 { 1003 /* 1004 * Destroy function for cpu->cp_regs hashtable data entries. 1005 * We must free the name string because it was g_strdup()ed in 1006 * add_cpreg_to_hashtable(). It's OK to cast away the 'const' 1007 * from r->name because we know we definitely allocated it. 1008 */ 1009 ARMCPRegInfo *r = data; 1010 1011 g_free((void *)r->name); 1012 g_free(r); 1013 } 1014 1015 static void arm_cpu_initfn(Object *obj) 1016 { 1017 ARMCPU *cpu = ARM_CPU(obj); 1018 1019 cpu_set_cpustate_pointers(cpu); 1020 cpu->cp_regs = g_hash_table_new_full(g_int_hash, g_int_equal, 1021 g_free, cpreg_hashtable_data_destroy); 1022 1023 QLIST_INIT(&cpu->pre_el_change_hooks); 1024 QLIST_INIT(&cpu->el_change_hooks); 1025 1026 #ifndef CONFIG_USER_ONLY 1027 /* Our inbound IRQ and FIQ lines */ 1028 if (kvm_enabled()) { 1029 /* VIRQ and VFIQ are unused with KVM but we add them to maintain 1030 * the same interface as non-KVM CPUs. 1031 */ 1032 qdev_init_gpio_in(DEVICE(cpu), arm_cpu_kvm_set_irq, 4); 1033 } else { 1034 qdev_init_gpio_in(DEVICE(cpu), arm_cpu_set_irq, 4); 1035 } 1036 1037 qdev_init_gpio_out(DEVICE(cpu), cpu->gt_timer_outputs, 1038 ARRAY_SIZE(cpu->gt_timer_outputs)); 1039 1040 qdev_init_gpio_out_named(DEVICE(cpu), &cpu->gicv3_maintenance_interrupt, 1041 "gicv3-maintenance-interrupt", 1); 1042 qdev_init_gpio_out_named(DEVICE(cpu), &cpu->pmu_interrupt, 1043 "pmu-interrupt", 1); 1044 #endif 1045 1046 /* DTB consumers generally don't in fact care what the 'compatible' 1047 * string is, so always provide some string and trust that a hypothetical 1048 * picky DTB consumer will also provide a helpful error message. 1049 */ 1050 cpu->dtb_compatible = "qemu,unknown"; 1051 cpu->psci_version = 1; /* By default assume PSCI v0.1 */ 1052 cpu->kvm_target = QEMU_KVM_ARM_TARGET_NONE; 1053 1054 if (tcg_enabled()) { 1055 cpu->psci_version = 2; /* TCG implements PSCI 0.2 */ 1056 } 1057 } 1058 1059 static Property arm_cpu_gt_cntfrq_property = 1060 DEFINE_PROP_UINT64("cntfrq", ARMCPU, gt_cntfrq_hz, 1061 NANOSECONDS_PER_SECOND / GTIMER_SCALE); 1062 1063 static Property arm_cpu_reset_cbar_property = 1064 DEFINE_PROP_UINT64("reset-cbar", ARMCPU, reset_cbar, 0); 1065 1066 static Property arm_cpu_reset_hivecs_property = 1067 DEFINE_PROP_BOOL("reset-hivecs", ARMCPU, reset_hivecs, false); 1068 1069 static Property arm_cpu_rvbar_property = 1070 DEFINE_PROP_UINT64("rvbar", ARMCPU, rvbar, 0); 1071 1072 #ifndef CONFIG_USER_ONLY 1073 static Property arm_cpu_has_el2_property = 1074 DEFINE_PROP_BOOL("has_el2", ARMCPU, has_el2, true); 1075 1076 static Property arm_cpu_has_el3_property = 1077 DEFINE_PROP_BOOL("has_el3", ARMCPU, has_el3, true); 1078 #endif 1079 1080 static Property arm_cpu_cfgend_property = 1081 DEFINE_PROP_BOOL("cfgend", ARMCPU, cfgend, false); 1082 1083 static Property arm_cpu_has_vfp_property = 1084 DEFINE_PROP_BOOL("vfp", ARMCPU, has_vfp, true); 1085 1086 static Property arm_cpu_has_neon_property = 1087 DEFINE_PROP_BOOL("neon", ARMCPU, has_neon, true); 1088 1089 static Property arm_cpu_has_dsp_property = 1090 DEFINE_PROP_BOOL("dsp", ARMCPU, has_dsp, true); 1091 1092 static Property arm_cpu_has_mpu_property = 1093 DEFINE_PROP_BOOL("has-mpu", ARMCPU, has_mpu, true); 1094 1095 /* This is like DEFINE_PROP_UINT32 but it doesn't set the default value, 1096 * because the CPU initfn will have already set cpu->pmsav7_dregion to 1097 * the right value for that particular CPU type, and we don't want 1098 * to override that with an incorrect constant value. 1099 */ 1100 static Property arm_cpu_pmsav7_dregion_property = 1101 DEFINE_PROP_UNSIGNED_NODEFAULT("pmsav7-dregion", ARMCPU, 1102 pmsav7_dregion, 1103 qdev_prop_uint32, uint32_t); 1104 1105 static bool arm_get_pmu(Object *obj, Error **errp) 1106 { 1107 ARMCPU *cpu = ARM_CPU(obj); 1108 1109 return cpu->has_pmu; 1110 } 1111 1112 static void arm_set_pmu(Object *obj, bool value, Error **errp) 1113 { 1114 ARMCPU *cpu = ARM_CPU(obj); 1115 1116 if (value) { 1117 if (kvm_enabled() && !kvm_arm_pmu_supported()) { 1118 error_setg(errp, "'pmu' feature not supported by KVM on this host"); 1119 return; 1120 } 1121 set_feature(&cpu->env, ARM_FEATURE_PMU); 1122 } else { 1123 unset_feature(&cpu->env, ARM_FEATURE_PMU); 1124 } 1125 cpu->has_pmu = value; 1126 } 1127 1128 unsigned int gt_cntfrq_period_ns(ARMCPU *cpu) 1129 { 1130 /* 1131 * The exact approach to calculating guest ticks is: 1132 * 1133 * muldiv64(qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL), cpu->gt_cntfrq_hz, 1134 * NANOSECONDS_PER_SECOND); 1135 * 1136 * We don't do that. Rather we intentionally use integer division 1137 * truncation below and in the caller for the conversion of host monotonic 1138 * time to guest ticks to provide the exact inverse for the semantics of 1139 * the QEMUTimer scale factor. QEMUTimer's scale facter is an integer, so 1140 * it loses precision when representing frequencies where 1141 * `(NANOSECONDS_PER_SECOND % cpu->gt_cntfrq) > 0` holds. Failing to 1142 * provide an exact inverse leads to scheduling timers with negative 1143 * periods, which in turn leads to sticky behaviour in the guest. 1144 * 1145 * Finally, CNTFRQ is effectively capped at 1GHz to ensure our scale factor 1146 * cannot become zero. 1147 */ 1148 return NANOSECONDS_PER_SECOND > cpu->gt_cntfrq_hz ? 1149 NANOSECONDS_PER_SECOND / cpu->gt_cntfrq_hz : 1; 1150 } 1151 1152 void arm_cpu_post_init(Object *obj) 1153 { 1154 ARMCPU *cpu = ARM_CPU(obj); 1155 1156 /* M profile implies PMSA. We have to do this here rather than 1157 * in realize with the other feature-implication checks because 1158 * we look at the PMSA bit to see if we should add some properties. 1159 */ 1160 if (arm_feature(&cpu->env, ARM_FEATURE_M)) { 1161 set_feature(&cpu->env, ARM_FEATURE_PMSA); 1162 } 1163 1164 if (arm_feature(&cpu->env, ARM_FEATURE_CBAR) || 1165 arm_feature(&cpu->env, ARM_FEATURE_CBAR_RO)) { 1166 qdev_property_add_static(DEVICE(obj), &arm_cpu_reset_cbar_property); 1167 } 1168 1169 if (!arm_feature(&cpu->env, ARM_FEATURE_M)) { 1170 qdev_property_add_static(DEVICE(obj), &arm_cpu_reset_hivecs_property); 1171 } 1172 1173 if (arm_feature(&cpu->env, ARM_FEATURE_AARCH64)) { 1174 qdev_property_add_static(DEVICE(obj), &arm_cpu_rvbar_property); 1175 } 1176 1177 #ifndef CONFIG_USER_ONLY 1178 if (arm_feature(&cpu->env, ARM_FEATURE_EL3)) { 1179 /* Add the has_el3 state CPU property only if EL3 is allowed. This will 1180 * prevent "has_el3" from existing on CPUs which cannot support EL3. 1181 */ 1182 qdev_property_add_static(DEVICE(obj), &arm_cpu_has_el3_property); 1183 1184 object_property_add_link(obj, "secure-memory", 1185 TYPE_MEMORY_REGION, 1186 (Object **)&cpu->secure_memory, 1187 qdev_prop_allow_set_link_before_realize, 1188 OBJ_PROP_LINK_STRONG); 1189 } 1190 1191 if (arm_feature(&cpu->env, ARM_FEATURE_EL2)) { 1192 qdev_property_add_static(DEVICE(obj), &arm_cpu_has_el2_property); 1193 } 1194 #endif 1195 1196 if (arm_feature(&cpu->env, ARM_FEATURE_PMU)) { 1197 cpu->has_pmu = true; 1198 object_property_add_bool(obj, "pmu", arm_get_pmu, arm_set_pmu); 1199 } 1200 1201 /* 1202 * Allow user to turn off VFP and Neon support, but only for TCG -- 1203 * KVM does not currently allow us to lie to the guest about its 1204 * ID/feature registers, so the guest always sees what the host has. 1205 */ 1206 if (arm_feature(&cpu->env, ARM_FEATURE_AARCH64) 1207 ? cpu_isar_feature(aa64_fp_simd, cpu) 1208 : cpu_isar_feature(aa32_vfp, cpu)) { 1209 cpu->has_vfp = true; 1210 if (!kvm_enabled()) { 1211 qdev_property_add_static(DEVICE(obj), &arm_cpu_has_vfp_property); 1212 } 1213 } 1214 1215 if (arm_feature(&cpu->env, ARM_FEATURE_NEON)) { 1216 cpu->has_neon = true; 1217 if (!kvm_enabled()) { 1218 qdev_property_add_static(DEVICE(obj), &arm_cpu_has_neon_property); 1219 } 1220 } 1221 1222 if (arm_feature(&cpu->env, ARM_FEATURE_M) && 1223 arm_feature(&cpu->env, ARM_FEATURE_THUMB_DSP)) { 1224 qdev_property_add_static(DEVICE(obj), &arm_cpu_has_dsp_property); 1225 } 1226 1227 if (arm_feature(&cpu->env, ARM_FEATURE_PMSA)) { 1228 qdev_property_add_static(DEVICE(obj), &arm_cpu_has_mpu_property); 1229 if (arm_feature(&cpu->env, ARM_FEATURE_V7)) { 1230 qdev_property_add_static(DEVICE(obj), 1231 &arm_cpu_pmsav7_dregion_property); 1232 } 1233 } 1234 1235 if (arm_feature(&cpu->env, ARM_FEATURE_M_SECURITY)) { 1236 object_property_add_link(obj, "idau", TYPE_IDAU_INTERFACE, &cpu->idau, 1237 qdev_prop_allow_set_link_before_realize, 1238 OBJ_PROP_LINK_STRONG); 1239 /* 1240 * M profile: initial value of the Secure VTOR. We can't just use 1241 * a simple DEFINE_PROP_UINT32 for this because we want to permit 1242 * the property to be set after realize. 1243 */ 1244 object_property_add_uint32_ptr(obj, "init-svtor", 1245 &cpu->init_svtor, 1246 OBJ_PROP_FLAG_READWRITE); 1247 } 1248 1249 qdev_property_add_static(DEVICE(obj), &arm_cpu_cfgend_property); 1250 1251 if (arm_feature(&cpu->env, ARM_FEATURE_GENERIC_TIMER)) { 1252 qdev_property_add_static(DEVICE(cpu), &arm_cpu_gt_cntfrq_property); 1253 } 1254 1255 if (kvm_enabled()) { 1256 kvm_arm_add_vcpu_properties(obj); 1257 } 1258 1259 #ifndef CONFIG_USER_ONLY 1260 if (arm_feature(&cpu->env, ARM_FEATURE_AARCH64) && 1261 cpu_isar_feature(aa64_mte, cpu)) { 1262 object_property_add_link(obj, "tag-memory", 1263 TYPE_MEMORY_REGION, 1264 (Object **)&cpu->tag_memory, 1265 qdev_prop_allow_set_link_before_realize, 1266 OBJ_PROP_LINK_STRONG); 1267 1268 if (arm_feature(&cpu->env, ARM_FEATURE_EL3)) { 1269 object_property_add_link(obj, "secure-tag-memory", 1270 TYPE_MEMORY_REGION, 1271 (Object **)&cpu->secure_tag_memory, 1272 qdev_prop_allow_set_link_before_realize, 1273 OBJ_PROP_LINK_STRONG); 1274 } 1275 } 1276 #endif 1277 } 1278 1279 static void arm_cpu_finalizefn(Object *obj) 1280 { 1281 ARMCPU *cpu = ARM_CPU(obj); 1282 ARMELChangeHook *hook, *next; 1283 1284 g_hash_table_destroy(cpu->cp_regs); 1285 1286 QLIST_FOREACH_SAFE(hook, &cpu->pre_el_change_hooks, node, next) { 1287 QLIST_REMOVE(hook, node); 1288 g_free(hook); 1289 } 1290 QLIST_FOREACH_SAFE(hook, &cpu->el_change_hooks, node, next) { 1291 QLIST_REMOVE(hook, node); 1292 g_free(hook); 1293 } 1294 #ifndef CONFIG_USER_ONLY 1295 if (cpu->pmu_timer) { 1296 timer_del(cpu->pmu_timer); 1297 timer_deinit(cpu->pmu_timer); 1298 timer_free(cpu->pmu_timer); 1299 } 1300 #endif 1301 } 1302 1303 void arm_cpu_finalize_features(ARMCPU *cpu, Error **errp) 1304 { 1305 Error *local_err = NULL; 1306 1307 if (arm_feature(&cpu->env, ARM_FEATURE_AARCH64)) { 1308 arm_cpu_sve_finalize(cpu, &local_err); 1309 if (local_err != NULL) { 1310 error_propagate(errp, local_err); 1311 return; 1312 } 1313 } 1314 } 1315 1316 static void arm_cpu_realizefn(DeviceState *dev, Error **errp) 1317 { 1318 CPUState *cs = CPU(dev); 1319 ARMCPU *cpu = ARM_CPU(dev); 1320 ARMCPUClass *acc = ARM_CPU_GET_CLASS(dev); 1321 CPUARMState *env = &cpu->env; 1322 int pagebits; 1323 Error *local_err = NULL; 1324 bool no_aa32 = false; 1325 1326 /* If we needed to query the host kernel for the CPU features 1327 * then it's possible that might have failed in the initfn, but 1328 * this is the first point where we can report it. 1329 */ 1330 if (cpu->host_cpu_probe_failed) { 1331 if (!kvm_enabled()) { 1332 error_setg(errp, "The 'host' CPU type can only be used with KVM"); 1333 } else { 1334 error_setg(errp, "Failed to retrieve host CPU features"); 1335 } 1336 return; 1337 } 1338 1339 #ifndef CONFIG_USER_ONLY 1340 /* The NVIC and M-profile CPU are two halves of a single piece of 1341 * hardware; trying to use one without the other is a command line 1342 * error and will result in segfaults if not caught here. 1343 */ 1344 if (arm_feature(env, ARM_FEATURE_M)) { 1345 if (!env->nvic) { 1346 error_setg(errp, "This board cannot be used with Cortex-M CPUs"); 1347 return; 1348 } 1349 } else { 1350 if (env->nvic) { 1351 error_setg(errp, "This board can only be used with Cortex-M CPUs"); 1352 return; 1353 } 1354 } 1355 1356 { 1357 uint64_t scale; 1358 1359 if (arm_feature(env, ARM_FEATURE_GENERIC_TIMER)) { 1360 if (!cpu->gt_cntfrq_hz) { 1361 error_setg(errp, "Invalid CNTFRQ: %"PRId64"Hz", 1362 cpu->gt_cntfrq_hz); 1363 return; 1364 } 1365 scale = gt_cntfrq_period_ns(cpu); 1366 } else { 1367 scale = GTIMER_SCALE; 1368 } 1369 1370 cpu->gt_timer[GTIMER_PHYS] = timer_new(QEMU_CLOCK_VIRTUAL, scale, 1371 arm_gt_ptimer_cb, cpu); 1372 cpu->gt_timer[GTIMER_VIRT] = timer_new(QEMU_CLOCK_VIRTUAL, scale, 1373 arm_gt_vtimer_cb, cpu); 1374 cpu->gt_timer[GTIMER_HYP] = timer_new(QEMU_CLOCK_VIRTUAL, scale, 1375 arm_gt_htimer_cb, cpu); 1376 cpu->gt_timer[GTIMER_SEC] = timer_new(QEMU_CLOCK_VIRTUAL, scale, 1377 arm_gt_stimer_cb, cpu); 1378 cpu->gt_timer[GTIMER_HYPVIRT] = timer_new(QEMU_CLOCK_VIRTUAL, scale, 1379 arm_gt_hvtimer_cb, cpu); 1380 } 1381 #endif 1382 1383 cpu_exec_realizefn(cs, &local_err); 1384 if (local_err != NULL) { 1385 error_propagate(errp, local_err); 1386 return; 1387 } 1388 1389 arm_cpu_finalize_features(cpu, &local_err); 1390 if (local_err != NULL) { 1391 error_propagate(errp, local_err); 1392 return; 1393 } 1394 1395 if (arm_feature(env, ARM_FEATURE_AARCH64) && 1396 cpu->has_vfp != cpu->has_neon) { 1397 /* 1398 * This is an architectural requirement for AArch64; AArch32 is 1399 * more flexible and permits VFP-no-Neon and Neon-no-VFP. 1400 */ 1401 error_setg(errp, 1402 "AArch64 CPUs must have both VFP and Neon or neither"); 1403 return; 1404 } 1405 1406 if (!cpu->has_vfp) { 1407 uint64_t t; 1408 uint32_t u; 1409 1410 t = cpu->isar.id_aa64isar1; 1411 t = FIELD_DP64(t, ID_AA64ISAR1, JSCVT, 0); 1412 cpu->isar.id_aa64isar1 = t; 1413 1414 t = cpu->isar.id_aa64pfr0; 1415 t = FIELD_DP64(t, ID_AA64PFR0, FP, 0xf); 1416 cpu->isar.id_aa64pfr0 = t; 1417 1418 u = cpu->isar.id_isar6; 1419 u = FIELD_DP32(u, ID_ISAR6, JSCVT, 0); 1420 cpu->isar.id_isar6 = u; 1421 1422 u = cpu->isar.mvfr0; 1423 u = FIELD_DP32(u, MVFR0, FPSP, 0); 1424 u = FIELD_DP32(u, MVFR0, FPDP, 0); 1425 u = FIELD_DP32(u, MVFR0, FPTRAP, 0); 1426 u = FIELD_DP32(u, MVFR0, FPDIVIDE, 0); 1427 u = FIELD_DP32(u, MVFR0, FPSQRT, 0); 1428 u = FIELD_DP32(u, MVFR0, FPSHVEC, 0); 1429 u = FIELD_DP32(u, MVFR0, FPROUND, 0); 1430 cpu->isar.mvfr0 = u; 1431 1432 u = cpu->isar.mvfr1; 1433 u = FIELD_DP32(u, MVFR1, FPFTZ, 0); 1434 u = FIELD_DP32(u, MVFR1, FPDNAN, 0); 1435 u = FIELD_DP32(u, MVFR1, FPHP, 0); 1436 cpu->isar.mvfr1 = u; 1437 1438 u = cpu->isar.mvfr2; 1439 u = FIELD_DP32(u, MVFR2, FPMISC, 0); 1440 cpu->isar.mvfr2 = u; 1441 } 1442 1443 if (!cpu->has_neon) { 1444 uint64_t t; 1445 uint32_t u; 1446 1447 unset_feature(env, ARM_FEATURE_NEON); 1448 1449 t = cpu->isar.id_aa64isar0; 1450 t = FIELD_DP64(t, ID_AA64ISAR0, DP, 0); 1451 cpu->isar.id_aa64isar0 = t; 1452 1453 t = cpu->isar.id_aa64isar1; 1454 t = FIELD_DP64(t, ID_AA64ISAR1, FCMA, 0); 1455 cpu->isar.id_aa64isar1 = t; 1456 1457 t = cpu->isar.id_aa64pfr0; 1458 t = FIELD_DP64(t, ID_AA64PFR0, ADVSIMD, 0xf); 1459 cpu->isar.id_aa64pfr0 = t; 1460 1461 u = cpu->isar.id_isar5; 1462 u = FIELD_DP32(u, ID_ISAR5, RDM, 0); 1463 u = FIELD_DP32(u, ID_ISAR5, VCMA, 0); 1464 cpu->isar.id_isar5 = u; 1465 1466 u = cpu->isar.id_isar6; 1467 u = FIELD_DP32(u, ID_ISAR6, DP, 0); 1468 u = FIELD_DP32(u, ID_ISAR6, FHM, 0); 1469 cpu->isar.id_isar6 = u; 1470 1471 u = cpu->isar.mvfr1; 1472 u = FIELD_DP32(u, MVFR1, SIMDLS, 0); 1473 u = FIELD_DP32(u, MVFR1, SIMDINT, 0); 1474 u = FIELD_DP32(u, MVFR1, SIMDSP, 0); 1475 u = FIELD_DP32(u, MVFR1, SIMDHP, 0); 1476 cpu->isar.mvfr1 = u; 1477 1478 u = cpu->isar.mvfr2; 1479 u = FIELD_DP32(u, MVFR2, SIMDMISC, 0); 1480 cpu->isar.mvfr2 = u; 1481 } 1482 1483 if (!cpu->has_neon && !cpu->has_vfp) { 1484 uint64_t t; 1485 uint32_t u; 1486 1487 t = cpu->isar.id_aa64isar0; 1488 t = FIELD_DP64(t, ID_AA64ISAR0, FHM, 0); 1489 cpu->isar.id_aa64isar0 = t; 1490 1491 t = cpu->isar.id_aa64isar1; 1492 t = FIELD_DP64(t, ID_AA64ISAR1, FRINTTS, 0); 1493 cpu->isar.id_aa64isar1 = t; 1494 1495 u = cpu->isar.mvfr0; 1496 u = FIELD_DP32(u, MVFR0, SIMDREG, 0); 1497 cpu->isar.mvfr0 = u; 1498 1499 /* Despite the name, this field covers both VFP and Neon */ 1500 u = cpu->isar.mvfr1; 1501 u = FIELD_DP32(u, MVFR1, SIMDFMAC, 0); 1502 cpu->isar.mvfr1 = u; 1503 } 1504 1505 if (arm_feature(env, ARM_FEATURE_M) && !cpu->has_dsp) { 1506 uint32_t u; 1507 1508 unset_feature(env, ARM_FEATURE_THUMB_DSP); 1509 1510 u = cpu->isar.id_isar1; 1511 u = FIELD_DP32(u, ID_ISAR1, EXTEND, 1); 1512 cpu->isar.id_isar1 = u; 1513 1514 u = cpu->isar.id_isar2; 1515 u = FIELD_DP32(u, ID_ISAR2, MULTU, 1); 1516 u = FIELD_DP32(u, ID_ISAR2, MULTS, 1); 1517 cpu->isar.id_isar2 = u; 1518 1519 u = cpu->isar.id_isar3; 1520 u = FIELD_DP32(u, ID_ISAR3, SIMD, 1); 1521 u = FIELD_DP32(u, ID_ISAR3, SATURATE, 0); 1522 cpu->isar.id_isar3 = u; 1523 } 1524 1525 /* Some features automatically imply others: */ 1526 if (arm_feature(env, ARM_FEATURE_V8)) { 1527 if (arm_feature(env, ARM_FEATURE_M)) { 1528 set_feature(env, ARM_FEATURE_V7); 1529 } else { 1530 set_feature(env, ARM_FEATURE_V7VE); 1531 } 1532 } 1533 1534 /* 1535 * There exist AArch64 cpus without AArch32 support. When KVM 1536 * queries ID_ISAR0_EL1 on such a host, the value is UNKNOWN. 1537 * Similarly, we cannot check ID_AA64PFR0 without AArch64 support. 1538 * As a general principle, we also do not make ID register 1539 * consistency checks anywhere unless using TCG, because only 1540 * for TCG would a consistency-check failure be a QEMU bug. 1541 */ 1542 if (arm_feature(&cpu->env, ARM_FEATURE_AARCH64)) { 1543 no_aa32 = !cpu_isar_feature(aa64_aa32, cpu); 1544 } 1545 1546 if (arm_feature(env, ARM_FEATURE_V7VE)) { 1547 /* v7 Virtualization Extensions. In real hardware this implies 1548 * EL2 and also the presence of the Security Extensions. 1549 * For QEMU, for backwards-compatibility we implement some 1550 * CPUs or CPU configs which have no actual EL2 or EL3 but do 1551 * include the various other features that V7VE implies. 1552 * Presence of EL2 itself is ARM_FEATURE_EL2, and of the 1553 * Security Extensions is ARM_FEATURE_EL3. 1554 */ 1555 assert(!tcg_enabled() || no_aa32 || 1556 cpu_isar_feature(aa32_arm_div, cpu)); 1557 set_feature(env, ARM_FEATURE_LPAE); 1558 set_feature(env, ARM_FEATURE_V7); 1559 } 1560 if (arm_feature(env, ARM_FEATURE_V7)) { 1561 set_feature(env, ARM_FEATURE_VAPA); 1562 set_feature(env, ARM_FEATURE_THUMB2); 1563 set_feature(env, ARM_FEATURE_MPIDR); 1564 if (!arm_feature(env, ARM_FEATURE_M)) { 1565 set_feature(env, ARM_FEATURE_V6K); 1566 } else { 1567 set_feature(env, ARM_FEATURE_V6); 1568 } 1569 1570 /* Always define VBAR for V7 CPUs even if it doesn't exist in 1571 * non-EL3 configs. This is needed by some legacy boards. 1572 */ 1573 set_feature(env, ARM_FEATURE_VBAR); 1574 } 1575 if (arm_feature(env, ARM_FEATURE_V6K)) { 1576 set_feature(env, ARM_FEATURE_V6); 1577 set_feature(env, ARM_FEATURE_MVFR); 1578 } 1579 if (arm_feature(env, ARM_FEATURE_V6)) { 1580 set_feature(env, ARM_FEATURE_V5); 1581 if (!arm_feature(env, ARM_FEATURE_M)) { 1582 assert(!tcg_enabled() || no_aa32 || 1583 cpu_isar_feature(aa32_jazelle, cpu)); 1584 set_feature(env, ARM_FEATURE_AUXCR); 1585 } 1586 } 1587 if (arm_feature(env, ARM_FEATURE_V5)) { 1588 set_feature(env, ARM_FEATURE_V4T); 1589 } 1590 if (arm_feature(env, ARM_FEATURE_LPAE)) { 1591 set_feature(env, ARM_FEATURE_V7MP); 1592 set_feature(env, ARM_FEATURE_PXN); 1593 } 1594 if (arm_feature(env, ARM_FEATURE_CBAR_RO)) { 1595 set_feature(env, ARM_FEATURE_CBAR); 1596 } 1597 if (arm_feature(env, ARM_FEATURE_THUMB2) && 1598 !arm_feature(env, ARM_FEATURE_M)) { 1599 set_feature(env, ARM_FEATURE_THUMB_DSP); 1600 } 1601 1602 /* 1603 * We rely on no XScale CPU having VFP so we can use the same bits in the 1604 * TB flags field for VECSTRIDE and XSCALE_CPAR. 1605 */ 1606 assert(arm_feature(&cpu->env, ARM_FEATURE_AARCH64) || 1607 !cpu_isar_feature(aa32_vfp_simd, cpu) || 1608 !arm_feature(env, ARM_FEATURE_XSCALE)); 1609 1610 if (arm_feature(env, ARM_FEATURE_V7) && 1611 !arm_feature(env, ARM_FEATURE_M) && 1612 !arm_feature(env, ARM_FEATURE_PMSA)) { 1613 /* v7VMSA drops support for the old ARMv5 tiny pages, so we 1614 * can use 4K pages. 1615 */ 1616 pagebits = 12; 1617 } else { 1618 /* For CPUs which might have tiny 1K pages, or which have an 1619 * MPU and might have small region sizes, stick with 1K pages. 1620 */ 1621 pagebits = 10; 1622 } 1623 if (!set_preferred_target_page_bits(pagebits)) { 1624 /* This can only ever happen for hotplugging a CPU, or if 1625 * the board code incorrectly creates a CPU which it has 1626 * promised via minimum_page_size that it will not. 1627 */ 1628 error_setg(errp, "This CPU requires a smaller page size than the " 1629 "system is using"); 1630 return; 1631 } 1632 1633 /* This cpu-id-to-MPIDR affinity is used only for TCG; KVM will override it. 1634 * We don't support setting cluster ID ([16..23]) (known as Aff2 1635 * in later ARM ARM versions), or any of the higher affinity level fields, 1636 * so these bits always RAZ. 1637 */ 1638 if (cpu->mp_affinity == ARM64_AFFINITY_INVALID) { 1639 cpu->mp_affinity = arm_cpu_mp_affinity(cs->cpu_index, 1640 ARM_DEFAULT_CPUS_PER_CLUSTER); 1641 } 1642 1643 if (cpu->reset_hivecs) { 1644 cpu->reset_sctlr |= (1 << 13); 1645 } 1646 1647 if (cpu->cfgend) { 1648 if (arm_feature(&cpu->env, ARM_FEATURE_V7)) { 1649 cpu->reset_sctlr |= SCTLR_EE; 1650 } else { 1651 cpu->reset_sctlr |= SCTLR_B; 1652 } 1653 } 1654 1655 if (!cpu->has_el3) { 1656 /* If the has_el3 CPU property is disabled then we need to disable the 1657 * feature. 1658 */ 1659 unset_feature(env, ARM_FEATURE_EL3); 1660 1661 /* Disable the security extension feature bits in the processor feature 1662 * registers as well. These are id_pfr1[7:4] and id_aa64pfr0[15:12]. 1663 */ 1664 cpu->id_pfr1 &= ~0xf0; 1665 cpu->isar.id_aa64pfr0 &= ~0xf000; 1666 } 1667 1668 if (!cpu->has_el2) { 1669 unset_feature(env, ARM_FEATURE_EL2); 1670 } 1671 1672 if (!cpu->has_pmu) { 1673 unset_feature(env, ARM_FEATURE_PMU); 1674 } 1675 if (arm_feature(env, ARM_FEATURE_PMU)) { 1676 pmu_init(cpu); 1677 1678 if (!kvm_enabled()) { 1679 arm_register_pre_el_change_hook(cpu, &pmu_pre_el_change, 0); 1680 arm_register_el_change_hook(cpu, &pmu_post_el_change, 0); 1681 } 1682 1683 #ifndef CONFIG_USER_ONLY 1684 cpu->pmu_timer = timer_new_ns(QEMU_CLOCK_VIRTUAL, arm_pmu_timer_cb, 1685 cpu); 1686 #endif 1687 } else { 1688 cpu->isar.id_aa64dfr0 = 1689 FIELD_DP64(cpu->isar.id_aa64dfr0, ID_AA64DFR0, PMUVER, 0); 1690 cpu->isar.id_dfr0 = FIELD_DP32(cpu->isar.id_dfr0, ID_DFR0, PERFMON, 0); 1691 cpu->pmceid0 = 0; 1692 cpu->pmceid1 = 0; 1693 } 1694 1695 if (!arm_feature(env, ARM_FEATURE_EL2)) { 1696 /* Disable the hypervisor feature bits in the processor feature 1697 * registers if we don't have EL2. These are id_pfr1[15:12] and 1698 * id_aa64pfr0_el1[11:8]. 1699 */ 1700 cpu->isar.id_aa64pfr0 &= ~0xf00; 1701 cpu->id_pfr1 &= ~0xf000; 1702 } 1703 1704 #ifndef CONFIG_USER_ONLY 1705 if (cpu->tag_memory == NULL && cpu_isar_feature(aa64_mte, cpu)) { 1706 /* 1707 * Disable the MTE feature bits if we do not have tag-memory 1708 * provided by the machine. 1709 */ 1710 cpu->isar.id_aa64pfr1 = 1711 FIELD_DP64(cpu->isar.id_aa64pfr1, ID_AA64PFR1, MTE, 0); 1712 } 1713 #endif 1714 1715 /* MPU can be configured out of a PMSA CPU either by setting has-mpu 1716 * to false or by setting pmsav7-dregion to 0. 1717 */ 1718 if (!cpu->has_mpu) { 1719 cpu->pmsav7_dregion = 0; 1720 } 1721 if (cpu->pmsav7_dregion == 0) { 1722 cpu->has_mpu = false; 1723 } 1724 1725 if (arm_feature(env, ARM_FEATURE_PMSA) && 1726 arm_feature(env, ARM_FEATURE_V7)) { 1727 uint32_t nr = cpu->pmsav7_dregion; 1728 1729 if (nr > 0xff) { 1730 error_setg(errp, "PMSAv7 MPU #regions invalid %" PRIu32, nr); 1731 return; 1732 } 1733 1734 if (nr) { 1735 if (arm_feature(env, ARM_FEATURE_V8)) { 1736 /* PMSAv8 */ 1737 env->pmsav8.rbar[M_REG_NS] = g_new0(uint32_t, nr); 1738 env->pmsav8.rlar[M_REG_NS] = g_new0(uint32_t, nr); 1739 if (arm_feature(env, ARM_FEATURE_M_SECURITY)) { 1740 env->pmsav8.rbar[M_REG_S] = g_new0(uint32_t, nr); 1741 env->pmsav8.rlar[M_REG_S] = g_new0(uint32_t, nr); 1742 } 1743 } else { 1744 env->pmsav7.drbar = g_new0(uint32_t, nr); 1745 env->pmsav7.drsr = g_new0(uint32_t, nr); 1746 env->pmsav7.dracr = g_new0(uint32_t, nr); 1747 } 1748 } 1749 } 1750 1751 if (arm_feature(env, ARM_FEATURE_M_SECURITY)) { 1752 uint32_t nr = cpu->sau_sregion; 1753 1754 if (nr > 0xff) { 1755 error_setg(errp, "v8M SAU #regions invalid %" PRIu32, nr); 1756 return; 1757 } 1758 1759 if (nr) { 1760 env->sau.rbar = g_new0(uint32_t, nr); 1761 env->sau.rlar = g_new0(uint32_t, nr); 1762 } 1763 } 1764 1765 if (arm_feature(env, ARM_FEATURE_EL3)) { 1766 set_feature(env, ARM_FEATURE_VBAR); 1767 } 1768 1769 register_cp_regs_for_features(cpu); 1770 arm_cpu_register_gdb_regs_for_features(cpu); 1771 1772 init_cpreg_list(cpu); 1773 1774 #ifndef CONFIG_USER_ONLY 1775 MachineState *ms = MACHINE(qdev_get_machine()); 1776 unsigned int smp_cpus = ms->smp.cpus; 1777 bool has_secure = cpu->has_el3 || arm_feature(env, ARM_FEATURE_M_SECURITY); 1778 1779 /* 1780 * We must set cs->num_ases to the final value before 1781 * the first call to cpu_address_space_init. 1782 */ 1783 if (cpu->tag_memory != NULL) { 1784 cs->num_ases = 3 + has_secure; 1785 } else { 1786 cs->num_ases = 1 + has_secure; 1787 } 1788 1789 if (has_secure) { 1790 if (!cpu->secure_memory) { 1791 cpu->secure_memory = cs->memory; 1792 } 1793 cpu_address_space_init(cs, ARMASIdx_S, "cpu-secure-memory", 1794 cpu->secure_memory); 1795 } 1796 1797 if (cpu->tag_memory != NULL) { 1798 cpu_address_space_init(cs, ARMASIdx_TagNS, "cpu-tag-memory", 1799 cpu->tag_memory); 1800 if (has_secure) { 1801 cpu_address_space_init(cs, ARMASIdx_TagS, "cpu-tag-memory", 1802 cpu->secure_tag_memory); 1803 } 1804 } 1805 1806 cpu_address_space_init(cs, ARMASIdx_NS, "cpu-memory", cs->memory); 1807 1808 /* No core_count specified, default to smp_cpus. */ 1809 if (cpu->core_count == -1) { 1810 cpu->core_count = smp_cpus; 1811 } 1812 #endif 1813 1814 if (tcg_enabled()) { 1815 int dcz_blocklen = 4 << cpu->dcz_blocksize; 1816 1817 /* 1818 * We only support DCZ blocklen that fits on one page. 1819 * 1820 * Architectually this is always true. However TARGET_PAGE_SIZE 1821 * is variable and, for compatibility with -machine virt-2.7, 1822 * is only 1KiB, as an artifact of legacy ARMv5 subpage support. 1823 * But even then, while the largest architectural DCZ blocklen 1824 * is 2KiB, no cpu actually uses such a large blocklen. 1825 */ 1826 assert(dcz_blocklen <= TARGET_PAGE_SIZE); 1827 1828 /* 1829 * We only support DCZ blocksize >= 2*TAG_GRANULE, which is to say 1830 * both nibbles of each byte storing tag data may be written at once. 1831 * Since TAG_GRANULE is 16, this means that blocklen must be >= 32. 1832 */ 1833 if (cpu_isar_feature(aa64_mte, cpu)) { 1834 assert(dcz_blocklen >= 2 * TAG_GRANULE); 1835 } 1836 } 1837 1838 qemu_init_vcpu(cs); 1839 cpu_reset(cs); 1840 1841 acc->parent_realize(dev, errp); 1842 } 1843 1844 static ObjectClass *arm_cpu_class_by_name(const char *cpu_model) 1845 { 1846 ObjectClass *oc; 1847 char *typename; 1848 char **cpuname; 1849 const char *cpunamestr; 1850 1851 cpuname = g_strsplit(cpu_model, ",", 1); 1852 cpunamestr = cpuname[0]; 1853 #ifdef CONFIG_USER_ONLY 1854 /* For backwards compatibility usermode emulation allows "-cpu any", 1855 * which has the same semantics as "-cpu max". 1856 */ 1857 if (!strcmp(cpunamestr, "any")) { 1858 cpunamestr = "max"; 1859 } 1860 #endif 1861 typename = g_strdup_printf(ARM_CPU_TYPE_NAME("%s"), cpunamestr); 1862 oc = object_class_by_name(typename); 1863 g_strfreev(cpuname); 1864 g_free(typename); 1865 if (!oc || !object_class_dynamic_cast(oc, TYPE_ARM_CPU) || 1866 object_class_is_abstract(oc)) { 1867 return NULL; 1868 } 1869 return oc; 1870 } 1871 1872 /* CPU models. These are not needed for the AArch64 linux-user build. */ 1873 #if !defined(CONFIG_USER_ONLY) || !defined(TARGET_AARCH64) 1874 1875 static const ARMCPRegInfo cortexa8_cp_reginfo[] = { 1876 { .name = "L2LOCKDOWN", .cp = 15, .crn = 9, .crm = 0, .opc1 = 1, .opc2 = 0, 1877 .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0 }, 1878 { .name = "L2AUXCR", .cp = 15, .crn = 9, .crm = 0, .opc1 = 1, .opc2 = 2, 1879 .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0 }, 1880 REGINFO_SENTINEL 1881 }; 1882 1883 static void cortex_a8_initfn(Object *obj) 1884 { 1885 ARMCPU *cpu = ARM_CPU(obj); 1886 1887 cpu->dtb_compatible = "arm,cortex-a8"; 1888 set_feature(&cpu->env, ARM_FEATURE_V7); 1889 set_feature(&cpu->env, ARM_FEATURE_NEON); 1890 set_feature(&cpu->env, ARM_FEATURE_THUMB2EE); 1891 set_feature(&cpu->env, ARM_FEATURE_DUMMY_C15_REGS); 1892 set_feature(&cpu->env, ARM_FEATURE_EL3); 1893 cpu->midr = 0x410fc080; 1894 cpu->reset_fpsid = 0x410330c0; 1895 cpu->isar.mvfr0 = 0x11110222; 1896 cpu->isar.mvfr1 = 0x00011111; 1897 cpu->ctr = 0x82048004; 1898 cpu->reset_sctlr = 0x00c50078; 1899 cpu->id_pfr0 = 0x1031; 1900 cpu->id_pfr1 = 0x11; 1901 cpu->isar.id_dfr0 = 0x400; 1902 cpu->id_afr0 = 0; 1903 cpu->isar.id_mmfr0 = 0x31100003; 1904 cpu->isar.id_mmfr1 = 0x20000000; 1905 cpu->isar.id_mmfr2 = 0x01202000; 1906 cpu->isar.id_mmfr3 = 0x11; 1907 cpu->isar.id_isar0 = 0x00101111; 1908 cpu->isar.id_isar1 = 0x12112111; 1909 cpu->isar.id_isar2 = 0x21232031; 1910 cpu->isar.id_isar3 = 0x11112131; 1911 cpu->isar.id_isar4 = 0x00111142; 1912 cpu->isar.dbgdidr = 0x15141000; 1913 cpu->clidr = (1 << 27) | (2 << 24) | 3; 1914 cpu->ccsidr[0] = 0xe007e01a; /* 16k L1 dcache. */ 1915 cpu->ccsidr[1] = 0x2007e01a; /* 16k L1 icache. */ 1916 cpu->ccsidr[2] = 0xf0000000; /* No L2 icache. */ 1917 cpu->reset_auxcr = 2; 1918 define_arm_cp_regs(cpu, cortexa8_cp_reginfo); 1919 } 1920 1921 static const ARMCPRegInfo cortexa9_cp_reginfo[] = { 1922 /* power_control should be set to maximum latency. Again, 1923 * default to 0 and set by private hook 1924 */ 1925 { .name = "A9_PWRCTL", .cp = 15, .crn = 15, .crm = 0, .opc1 = 0, .opc2 = 0, 1926 .access = PL1_RW, .resetvalue = 0, 1927 .fieldoffset = offsetof(CPUARMState, cp15.c15_power_control) }, 1928 { .name = "A9_DIAG", .cp = 15, .crn = 15, .crm = 0, .opc1 = 0, .opc2 = 1, 1929 .access = PL1_RW, .resetvalue = 0, 1930 .fieldoffset = offsetof(CPUARMState, cp15.c15_diagnostic) }, 1931 { .name = "A9_PWRDIAG", .cp = 15, .crn = 15, .crm = 0, .opc1 = 0, .opc2 = 2, 1932 .access = PL1_RW, .resetvalue = 0, 1933 .fieldoffset = offsetof(CPUARMState, cp15.c15_power_diagnostic) }, 1934 { .name = "NEONBUSY", .cp = 15, .crn = 15, .crm = 1, .opc1 = 0, .opc2 = 0, 1935 .access = PL1_RW, .resetvalue = 0, .type = ARM_CP_CONST }, 1936 /* TLB lockdown control */ 1937 { .name = "TLB_LOCKR", .cp = 15, .crn = 15, .crm = 4, .opc1 = 5, .opc2 = 2, 1938 .access = PL1_W, .resetvalue = 0, .type = ARM_CP_NOP }, 1939 { .name = "TLB_LOCKW", .cp = 15, .crn = 15, .crm = 4, .opc1 = 5, .opc2 = 4, 1940 .access = PL1_W, .resetvalue = 0, .type = ARM_CP_NOP }, 1941 { .name = "TLB_VA", .cp = 15, .crn = 15, .crm = 5, .opc1 = 5, .opc2 = 2, 1942 .access = PL1_RW, .resetvalue = 0, .type = ARM_CP_CONST }, 1943 { .name = "TLB_PA", .cp = 15, .crn = 15, .crm = 6, .opc1 = 5, .opc2 = 2, 1944 .access = PL1_RW, .resetvalue = 0, .type = ARM_CP_CONST }, 1945 { .name = "TLB_ATTR", .cp = 15, .crn = 15, .crm = 7, .opc1 = 5, .opc2 = 2, 1946 .access = PL1_RW, .resetvalue = 0, .type = ARM_CP_CONST }, 1947 REGINFO_SENTINEL 1948 }; 1949 1950 static void cortex_a9_initfn(Object *obj) 1951 { 1952 ARMCPU *cpu = ARM_CPU(obj); 1953 1954 cpu->dtb_compatible = "arm,cortex-a9"; 1955 set_feature(&cpu->env, ARM_FEATURE_V7); 1956 set_feature(&cpu->env, ARM_FEATURE_NEON); 1957 set_feature(&cpu->env, ARM_FEATURE_THUMB2EE); 1958 set_feature(&cpu->env, ARM_FEATURE_EL3); 1959 /* Note that A9 supports the MP extensions even for 1960 * A9UP and single-core A9MP (which are both different 1961 * and valid configurations; we don't model A9UP). 1962 */ 1963 set_feature(&cpu->env, ARM_FEATURE_V7MP); 1964 set_feature(&cpu->env, ARM_FEATURE_CBAR); 1965 cpu->midr = 0x410fc090; 1966 cpu->reset_fpsid = 0x41033090; 1967 cpu->isar.mvfr0 = 0x11110222; 1968 cpu->isar.mvfr1 = 0x01111111; 1969 cpu->ctr = 0x80038003; 1970 cpu->reset_sctlr = 0x00c50078; 1971 cpu->id_pfr0 = 0x1031; 1972 cpu->id_pfr1 = 0x11; 1973 cpu->isar.id_dfr0 = 0x000; 1974 cpu->id_afr0 = 0; 1975 cpu->isar.id_mmfr0 = 0x00100103; 1976 cpu->isar.id_mmfr1 = 0x20000000; 1977 cpu->isar.id_mmfr2 = 0x01230000; 1978 cpu->isar.id_mmfr3 = 0x00002111; 1979 cpu->isar.id_isar0 = 0x00101111; 1980 cpu->isar.id_isar1 = 0x13112111; 1981 cpu->isar.id_isar2 = 0x21232041; 1982 cpu->isar.id_isar3 = 0x11112131; 1983 cpu->isar.id_isar4 = 0x00111142; 1984 cpu->isar.dbgdidr = 0x35141000; 1985 cpu->clidr = (1 << 27) | (1 << 24) | 3; 1986 cpu->ccsidr[0] = 0xe00fe019; /* 16k L1 dcache. */ 1987 cpu->ccsidr[1] = 0x200fe019; /* 16k L1 icache. */ 1988 define_arm_cp_regs(cpu, cortexa9_cp_reginfo); 1989 } 1990 1991 #ifndef CONFIG_USER_ONLY 1992 static uint64_t a15_l2ctlr_read(CPUARMState *env, const ARMCPRegInfo *ri) 1993 { 1994 MachineState *ms = MACHINE(qdev_get_machine()); 1995 1996 /* Linux wants the number of processors from here. 1997 * Might as well set the interrupt-controller bit too. 1998 */ 1999 return ((ms->smp.cpus - 1) << 24) | (1 << 23); 2000 } 2001 #endif 2002 2003 static const ARMCPRegInfo cortexa15_cp_reginfo[] = { 2004 #ifndef CONFIG_USER_ONLY 2005 { .name = "L2CTLR", .cp = 15, .crn = 9, .crm = 0, .opc1 = 1, .opc2 = 2, 2006 .access = PL1_RW, .resetvalue = 0, .readfn = a15_l2ctlr_read, 2007 .writefn = arm_cp_write_ignore, }, 2008 #endif 2009 { .name = "L2ECTLR", .cp = 15, .crn = 9, .crm = 0, .opc1 = 1, .opc2 = 3, 2010 .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0 }, 2011 REGINFO_SENTINEL 2012 }; 2013 2014 static void cortex_a7_initfn(Object *obj) 2015 { 2016 ARMCPU *cpu = ARM_CPU(obj); 2017 2018 cpu->dtb_compatible = "arm,cortex-a7"; 2019 set_feature(&cpu->env, ARM_FEATURE_V7VE); 2020 set_feature(&cpu->env, ARM_FEATURE_NEON); 2021 set_feature(&cpu->env, ARM_FEATURE_THUMB2EE); 2022 set_feature(&cpu->env, ARM_FEATURE_GENERIC_TIMER); 2023 set_feature(&cpu->env, ARM_FEATURE_DUMMY_C15_REGS); 2024 set_feature(&cpu->env, ARM_FEATURE_CBAR_RO); 2025 set_feature(&cpu->env, ARM_FEATURE_EL2); 2026 set_feature(&cpu->env, ARM_FEATURE_EL3); 2027 set_feature(&cpu->env, ARM_FEATURE_PMU); 2028 cpu->kvm_target = QEMU_KVM_ARM_TARGET_CORTEX_A7; 2029 cpu->midr = 0x410fc075; 2030 cpu->reset_fpsid = 0x41023075; 2031 cpu->isar.mvfr0 = 0x10110222; 2032 cpu->isar.mvfr1 = 0x11111111; 2033 cpu->ctr = 0x84448003; 2034 cpu->reset_sctlr = 0x00c50078; 2035 cpu->id_pfr0 = 0x00001131; 2036 cpu->id_pfr1 = 0x00011011; 2037 cpu->isar.id_dfr0 = 0x02010555; 2038 cpu->id_afr0 = 0x00000000; 2039 cpu->isar.id_mmfr0 = 0x10101105; 2040 cpu->isar.id_mmfr1 = 0x40000000; 2041 cpu->isar.id_mmfr2 = 0x01240000; 2042 cpu->isar.id_mmfr3 = 0x02102211; 2043 /* a7_mpcore_r0p5_trm, page 4-4 gives 0x01101110; but 2044 * table 4-41 gives 0x02101110, which includes the arm div insns. 2045 */ 2046 cpu->isar.id_isar0 = 0x02101110; 2047 cpu->isar.id_isar1 = 0x13112111; 2048 cpu->isar.id_isar2 = 0x21232041; 2049 cpu->isar.id_isar3 = 0x11112131; 2050 cpu->isar.id_isar4 = 0x10011142; 2051 cpu->isar.dbgdidr = 0x3515f005; 2052 cpu->clidr = 0x0a200023; 2053 cpu->ccsidr[0] = 0x701fe00a; /* 32K L1 dcache */ 2054 cpu->ccsidr[1] = 0x201fe00a; /* 32K L1 icache */ 2055 cpu->ccsidr[2] = 0x711fe07a; /* 4096K L2 unified cache */ 2056 define_arm_cp_regs(cpu, cortexa15_cp_reginfo); /* Same as A15 */ 2057 } 2058 2059 static void cortex_a15_initfn(Object *obj) 2060 { 2061 ARMCPU *cpu = ARM_CPU(obj); 2062 2063 cpu->dtb_compatible = "arm,cortex-a15"; 2064 set_feature(&cpu->env, ARM_FEATURE_V7VE); 2065 set_feature(&cpu->env, ARM_FEATURE_NEON); 2066 set_feature(&cpu->env, ARM_FEATURE_THUMB2EE); 2067 set_feature(&cpu->env, ARM_FEATURE_GENERIC_TIMER); 2068 set_feature(&cpu->env, ARM_FEATURE_DUMMY_C15_REGS); 2069 set_feature(&cpu->env, ARM_FEATURE_CBAR_RO); 2070 set_feature(&cpu->env, ARM_FEATURE_EL2); 2071 set_feature(&cpu->env, ARM_FEATURE_EL3); 2072 set_feature(&cpu->env, ARM_FEATURE_PMU); 2073 cpu->kvm_target = QEMU_KVM_ARM_TARGET_CORTEX_A15; 2074 cpu->midr = 0x412fc0f1; 2075 cpu->reset_fpsid = 0x410430f0; 2076 cpu->isar.mvfr0 = 0x10110222; 2077 cpu->isar.mvfr1 = 0x11111111; 2078 cpu->ctr = 0x8444c004; 2079 cpu->reset_sctlr = 0x00c50078; 2080 cpu->id_pfr0 = 0x00001131; 2081 cpu->id_pfr1 = 0x00011011; 2082 cpu->isar.id_dfr0 = 0x02010555; 2083 cpu->id_afr0 = 0x00000000; 2084 cpu->isar.id_mmfr0 = 0x10201105; 2085 cpu->isar.id_mmfr1 = 0x20000000; 2086 cpu->isar.id_mmfr2 = 0x01240000; 2087 cpu->isar.id_mmfr3 = 0x02102211; 2088 cpu->isar.id_isar0 = 0x02101110; 2089 cpu->isar.id_isar1 = 0x13112111; 2090 cpu->isar.id_isar2 = 0x21232041; 2091 cpu->isar.id_isar3 = 0x11112131; 2092 cpu->isar.id_isar4 = 0x10011142; 2093 cpu->isar.dbgdidr = 0x3515f021; 2094 cpu->clidr = 0x0a200023; 2095 cpu->ccsidr[0] = 0x701fe00a; /* 32K L1 dcache */ 2096 cpu->ccsidr[1] = 0x201fe00a; /* 32K L1 icache */ 2097 cpu->ccsidr[2] = 0x711fe07a; /* 4096K L2 unified cache */ 2098 define_arm_cp_regs(cpu, cortexa15_cp_reginfo); 2099 } 2100 2101 #ifndef TARGET_AARCH64 2102 /* -cpu max: if KVM is enabled, like -cpu host (best possible with this host); 2103 * otherwise, a CPU with as many features enabled as our emulation supports. 2104 * The version of '-cpu max' for qemu-system-aarch64 is defined in cpu64.c; 2105 * this only needs to handle 32 bits. 2106 */ 2107 static void arm_max_initfn(Object *obj) 2108 { 2109 ARMCPU *cpu = ARM_CPU(obj); 2110 2111 if (kvm_enabled()) { 2112 kvm_arm_set_cpu_features_from_host(cpu); 2113 } else { 2114 cortex_a15_initfn(obj); 2115 2116 /* old-style VFP short-vector support */ 2117 cpu->isar.mvfr0 = FIELD_DP32(cpu->isar.mvfr0, MVFR0, FPSHVEC, 1); 2118 2119 #ifdef CONFIG_USER_ONLY 2120 /* We don't set these in system emulation mode for the moment, 2121 * since we don't correctly set (all of) the ID registers to 2122 * advertise them. 2123 */ 2124 set_feature(&cpu->env, ARM_FEATURE_V8); 2125 { 2126 uint32_t t; 2127 2128 t = cpu->isar.id_isar5; 2129 t = FIELD_DP32(t, ID_ISAR5, AES, 2); 2130 t = FIELD_DP32(t, ID_ISAR5, SHA1, 1); 2131 t = FIELD_DP32(t, ID_ISAR5, SHA2, 1); 2132 t = FIELD_DP32(t, ID_ISAR5, CRC32, 1); 2133 t = FIELD_DP32(t, ID_ISAR5, RDM, 1); 2134 t = FIELD_DP32(t, ID_ISAR5, VCMA, 1); 2135 cpu->isar.id_isar5 = t; 2136 2137 t = cpu->isar.id_isar6; 2138 t = FIELD_DP32(t, ID_ISAR6, JSCVT, 1); 2139 t = FIELD_DP32(t, ID_ISAR6, DP, 1); 2140 t = FIELD_DP32(t, ID_ISAR6, FHM, 1); 2141 t = FIELD_DP32(t, ID_ISAR6, SB, 1); 2142 t = FIELD_DP32(t, ID_ISAR6, SPECRES, 1); 2143 cpu->isar.id_isar6 = t; 2144 2145 t = cpu->isar.mvfr1; 2146 t = FIELD_DP32(t, MVFR1, FPHP, 3); /* v8.2-FP16 */ 2147 t = FIELD_DP32(t, MVFR1, SIMDHP, 2); /* v8.2-FP16 */ 2148 cpu->isar.mvfr1 = t; 2149 2150 t = cpu->isar.mvfr2; 2151 t = FIELD_DP32(t, MVFR2, SIMDMISC, 3); /* SIMD MaxNum */ 2152 t = FIELD_DP32(t, MVFR2, FPMISC, 4); /* FP MaxNum */ 2153 cpu->isar.mvfr2 = t; 2154 2155 t = cpu->isar.id_mmfr3; 2156 t = FIELD_DP32(t, ID_MMFR3, PAN, 2); /* ATS1E1 */ 2157 cpu->isar.id_mmfr3 = t; 2158 2159 t = cpu->isar.id_mmfr4; 2160 t = FIELD_DP32(t, ID_MMFR4, HPDS, 1); /* AA32HPD */ 2161 t = FIELD_DP32(t, ID_MMFR4, AC2, 1); /* ACTLR2, HACTLR2 */ 2162 t = FIELD_DP32(t, ID_MMFR4, CNP, 1); /* TTCNP */ 2163 t = FIELD_DP32(t, ID_MMFR4, XNX, 1); /* TTS2UXN */ 2164 cpu->isar.id_mmfr4 = t; 2165 } 2166 #endif 2167 } 2168 } 2169 #endif 2170 2171 #endif /* !defined(CONFIG_USER_ONLY) || !defined(TARGET_AARCH64) */ 2172 2173 static const ARMCPUInfo arm_cpus[] = { 2174 #if !defined(CONFIG_USER_ONLY) || !defined(TARGET_AARCH64) 2175 { .name = "cortex-a7", .initfn = cortex_a7_initfn }, 2176 { .name = "cortex-a8", .initfn = cortex_a8_initfn }, 2177 { .name = "cortex-a9", .initfn = cortex_a9_initfn }, 2178 { .name = "cortex-a15", .initfn = cortex_a15_initfn }, 2179 #ifndef TARGET_AARCH64 2180 { .name = "max", .initfn = arm_max_initfn }, 2181 #endif 2182 #ifdef CONFIG_USER_ONLY 2183 { .name = "any", .initfn = arm_max_initfn }, 2184 #endif 2185 #endif 2186 }; 2187 2188 static Property arm_cpu_properties[] = { 2189 DEFINE_PROP_BOOL("start-powered-off", ARMCPU, start_powered_off, false), 2190 DEFINE_PROP_UINT32("psci-conduit", ARMCPU, psci_conduit, 0), 2191 DEFINE_PROP_UINT64("midr", ARMCPU, midr, 0), 2192 DEFINE_PROP_UINT64("mp-affinity", ARMCPU, 2193 mp_affinity, ARM64_AFFINITY_INVALID), 2194 DEFINE_PROP_INT32("node-id", ARMCPU, node_id, CPU_UNSET_NUMA_NODE_ID), 2195 DEFINE_PROP_INT32("core-count", ARMCPU, core_count, -1), 2196 DEFINE_PROP_END_OF_LIST() 2197 }; 2198 2199 static gchar *arm_gdb_arch_name(CPUState *cs) 2200 { 2201 ARMCPU *cpu = ARM_CPU(cs); 2202 CPUARMState *env = &cpu->env; 2203 2204 if (arm_feature(env, ARM_FEATURE_IWMMXT)) { 2205 return g_strdup("iwmmxt"); 2206 } 2207 return g_strdup("arm"); 2208 } 2209 2210 static void arm_cpu_class_init(ObjectClass *oc, void *data) 2211 { 2212 ARMCPUClass *acc = ARM_CPU_CLASS(oc); 2213 CPUClass *cc = CPU_CLASS(acc); 2214 DeviceClass *dc = DEVICE_CLASS(oc); 2215 2216 device_class_set_parent_realize(dc, arm_cpu_realizefn, 2217 &acc->parent_realize); 2218 2219 device_class_set_props(dc, arm_cpu_properties); 2220 device_class_set_parent_reset(dc, arm_cpu_reset, &acc->parent_reset); 2221 2222 cc->class_by_name = arm_cpu_class_by_name; 2223 cc->has_work = arm_cpu_has_work; 2224 cc->cpu_exec_interrupt = arm_cpu_exec_interrupt; 2225 cc->dump_state = arm_cpu_dump_state; 2226 cc->set_pc = arm_cpu_set_pc; 2227 cc->synchronize_from_tb = arm_cpu_synchronize_from_tb; 2228 cc->gdb_read_register = arm_cpu_gdb_read_register; 2229 cc->gdb_write_register = arm_cpu_gdb_write_register; 2230 #ifndef CONFIG_USER_ONLY 2231 cc->do_interrupt = arm_cpu_do_interrupt; 2232 cc->get_phys_page_attrs_debug = arm_cpu_get_phys_page_attrs_debug; 2233 cc->asidx_from_attrs = arm_asidx_from_attrs; 2234 cc->vmsd = &vmstate_arm_cpu; 2235 cc->virtio_is_big_endian = arm_cpu_virtio_is_big_endian; 2236 cc->write_elf64_note = arm_cpu_write_elf64_note; 2237 cc->write_elf32_note = arm_cpu_write_elf32_note; 2238 #endif 2239 cc->gdb_num_core_regs = 26; 2240 cc->gdb_core_xml_file = "arm-core.xml"; 2241 cc->gdb_arch_name = arm_gdb_arch_name; 2242 cc->gdb_get_dynamic_xml = arm_gdb_get_dynamic_xml; 2243 cc->gdb_stop_before_watchpoint = true; 2244 cc->disas_set_info = arm_disas_set_info; 2245 #ifdef CONFIG_TCG 2246 cc->tcg_initialize = arm_translate_init; 2247 cc->tlb_fill = arm_cpu_tlb_fill; 2248 cc->debug_excp_handler = arm_debug_excp_handler; 2249 cc->debug_check_watchpoint = arm_debug_check_watchpoint; 2250 cc->do_unaligned_access = arm_cpu_do_unaligned_access; 2251 #if !defined(CONFIG_USER_ONLY) 2252 cc->do_transaction_failed = arm_cpu_do_transaction_failed; 2253 cc->adjust_watchpoint_address = arm_adjust_watchpoint_address; 2254 #endif /* CONFIG_TCG && !CONFIG_USER_ONLY */ 2255 #endif 2256 } 2257 2258 #ifdef CONFIG_KVM 2259 static void arm_host_initfn(Object *obj) 2260 { 2261 ARMCPU *cpu = ARM_CPU(obj); 2262 2263 kvm_arm_set_cpu_features_from_host(cpu); 2264 if (arm_feature(&cpu->env, ARM_FEATURE_AARCH64)) { 2265 aarch64_add_sve_properties(obj); 2266 } 2267 arm_cpu_post_init(obj); 2268 } 2269 2270 static const TypeInfo host_arm_cpu_type_info = { 2271 .name = TYPE_ARM_HOST_CPU, 2272 #ifdef TARGET_AARCH64 2273 .parent = TYPE_AARCH64_CPU, 2274 #else 2275 .parent = TYPE_ARM_CPU, 2276 #endif 2277 .instance_init = arm_host_initfn, 2278 }; 2279 2280 #endif 2281 2282 static void arm_cpu_instance_init(Object *obj) 2283 { 2284 ARMCPUClass *acc = ARM_CPU_GET_CLASS(obj); 2285 2286 acc->info->initfn(obj); 2287 arm_cpu_post_init(obj); 2288 } 2289 2290 static void cpu_register_class_init(ObjectClass *oc, void *data) 2291 { 2292 ARMCPUClass *acc = ARM_CPU_CLASS(oc); 2293 2294 acc->info = data; 2295 } 2296 2297 void arm_cpu_register(const ARMCPUInfo *info) 2298 { 2299 TypeInfo type_info = { 2300 .parent = TYPE_ARM_CPU, 2301 .instance_size = sizeof(ARMCPU), 2302 .instance_init = arm_cpu_instance_init, 2303 .class_size = sizeof(ARMCPUClass), 2304 .class_init = info->class_init ?: cpu_register_class_init, 2305 .class_data = (void *)info, 2306 }; 2307 2308 type_info.name = g_strdup_printf("%s-" TYPE_ARM_CPU, info->name); 2309 type_register(&type_info); 2310 g_free((void *)type_info.name); 2311 } 2312 2313 static const TypeInfo arm_cpu_type_info = { 2314 .name = TYPE_ARM_CPU, 2315 .parent = TYPE_CPU, 2316 .instance_size = sizeof(ARMCPU), 2317 .instance_init = arm_cpu_initfn, 2318 .instance_finalize = arm_cpu_finalizefn, 2319 .abstract = true, 2320 .class_size = sizeof(ARMCPUClass), 2321 .class_init = arm_cpu_class_init, 2322 }; 2323 2324 static const TypeInfo idau_interface_type_info = { 2325 .name = TYPE_IDAU_INTERFACE, 2326 .parent = TYPE_INTERFACE, 2327 .class_size = sizeof(IDAUInterfaceClass), 2328 }; 2329 2330 static void arm_cpu_register_types(void) 2331 { 2332 const size_t cpu_count = ARRAY_SIZE(arm_cpus); 2333 2334 type_register_static(&arm_cpu_type_info); 2335 2336 #ifdef CONFIG_KVM 2337 type_register_static(&host_arm_cpu_type_info); 2338 #endif 2339 2340 if (cpu_count) { 2341 size_t i; 2342 2343 type_register_static(&idau_interface_type_info); 2344 for (i = 0; i < cpu_count; ++i) { 2345 arm_cpu_register(&arm_cpus[i]); 2346 } 2347 } 2348 } 2349 2350 type_init(arm_cpu_register_types) 2351