1 /* 2 * QEMU ARM CPU 3 * 4 * Copyright (c) 2012 SUSE LINUX Products GmbH 5 * 6 * This program is free software; you can redistribute it and/or 7 * modify it under the terms of the GNU General Public License 8 * as published by the Free Software Foundation; either version 2 9 * of the License, or (at your option) any later version. 10 * 11 * This program is distributed in the hope that it will be useful, 12 * but WITHOUT ANY WARRANTY; without even the implied warranty of 13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 14 * GNU General Public License for more details. 15 * 16 * You should have received a copy of the GNU General Public License 17 * along with this program; if not, see 18 * <http://www.gnu.org/licenses/gpl-2.0.html> 19 */ 20 21 #include "qemu/osdep.h" 22 #include "qemu/qemu-print.h" 23 #include "qemu/timer.h" 24 #include "qemu/log.h" 25 #include "exec/page-vary.h" 26 #include "target/arm/idau.h" 27 #include "qemu/module.h" 28 #include "qapi/error.h" 29 #include "cpu.h" 30 #ifdef CONFIG_TCG 31 #include "hw/core/tcg-cpu-ops.h" 32 #endif /* CONFIG_TCG */ 33 #include "internals.h" 34 #include "exec/exec-all.h" 35 #include "hw/qdev-properties.h" 36 #if !defined(CONFIG_USER_ONLY) 37 #include "hw/loader.h" 38 #include "hw/boards.h" 39 #ifdef CONFIG_TCG 40 #include "hw/intc/armv7m_nvic.h" 41 #endif /* CONFIG_TCG */ 42 #endif /* !CONFIG_USER_ONLY */ 43 #include "sysemu/tcg.h" 44 #include "sysemu/qtest.h" 45 #include "sysemu/hw_accel.h" 46 #include "kvm_arm.h" 47 #include "disas/capstone.h" 48 #include "fpu/softfloat.h" 49 #include "cpregs.h" 50 51 static void arm_cpu_set_pc(CPUState *cs, vaddr value) 52 { 53 ARMCPU *cpu = ARM_CPU(cs); 54 CPUARMState *env = &cpu->env; 55 56 if (is_a64(env)) { 57 env->pc = value; 58 env->thumb = false; 59 } else { 60 env->regs[15] = value & ~1; 61 env->thumb = value & 1; 62 } 63 } 64 65 static vaddr arm_cpu_get_pc(CPUState *cs) 66 { 67 ARMCPU *cpu = ARM_CPU(cs); 68 CPUARMState *env = &cpu->env; 69 70 if (is_a64(env)) { 71 return env->pc; 72 } else { 73 return env->regs[15]; 74 } 75 } 76 77 #ifdef CONFIG_TCG 78 void arm_cpu_synchronize_from_tb(CPUState *cs, 79 const TranslationBlock *tb) 80 { 81 /* The program counter is always up to date with CF_PCREL. */ 82 if (!(tb_cflags(tb) & CF_PCREL)) { 83 CPUARMState *env = cs->env_ptr; 84 /* 85 * It's OK to look at env for the current mode here, because it's 86 * never possible for an AArch64 TB to chain to an AArch32 TB. 87 */ 88 if (is_a64(env)) { 89 env->pc = tb->pc; 90 } else { 91 env->regs[15] = tb->pc; 92 } 93 } 94 } 95 96 void arm_restore_state_to_opc(CPUState *cs, 97 const TranslationBlock *tb, 98 const uint64_t *data) 99 { 100 CPUARMState *env = cs->env_ptr; 101 102 if (is_a64(env)) { 103 if (tb_cflags(tb) & CF_PCREL) { 104 env->pc = (env->pc & TARGET_PAGE_MASK) | data[0]; 105 } else { 106 env->pc = data[0]; 107 } 108 env->condexec_bits = 0; 109 env->exception.syndrome = data[2] << ARM_INSN_START_WORD2_SHIFT; 110 } else { 111 if (tb_cflags(tb) & CF_PCREL) { 112 env->regs[15] = (env->regs[15] & TARGET_PAGE_MASK) | data[0]; 113 } else { 114 env->regs[15] = data[0]; 115 } 116 env->condexec_bits = data[1]; 117 env->exception.syndrome = data[2] << ARM_INSN_START_WORD2_SHIFT; 118 } 119 } 120 #endif /* CONFIG_TCG */ 121 122 static bool arm_cpu_has_work(CPUState *cs) 123 { 124 ARMCPU *cpu = ARM_CPU(cs); 125 126 return (cpu->power_state != PSCI_OFF) 127 && cs->interrupt_request & 128 (CPU_INTERRUPT_FIQ | CPU_INTERRUPT_HARD 129 | CPU_INTERRUPT_VFIQ | CPU_INTERRUPT_VIRQ | CPU_INTERRUPT_VSERR 130 | CPU_INTERRUPT_EXITTB); 131 } 132 133 void arm_register_pre_el_change_hook(ARMCPU *cpu, ARMELChangeHookFn *hook, 134 void *opaque) 135 { 136 ARMELChangeHook *entry = g_new0(ARMELChangeHook, 1); 137 138 entry->hook = hook; 139 entry->opaque = opaque; 140 141 QLIST_INSERT_HEAD(&cpu->pre_el_change_hooks, entry, node); 142 } 143 144 void arm_register_el_change_hook(ARMCPU *cpu, ARMELChangeHookFn *hook, 145 void *opaque) 146 { 147 ARMELChangeHook *entry = g_new0(ARMELChangeHook, 1); 148 149 entry->hook = hook; 150 entry->opaque = opaque; 151 152 QLIST_INSERT_HEAD(&cpu->el_change_hooks, entry, node); 153 } 154 155 static void cp_reg_reset(gpointer key, gpointer value, gpointer opaque) 156 { 157 /* Reset a single ARMCPRegInfo register */ 158 ARMCPRegInfo *ri = value; 159 ARMCPU *cpu = opaque; 160 161 if (ri->type & (ARM_CP_SPECIAL_MASK | ARM_CP_ALIAS)) { 162 return; 163 } 164 165 if (ri->resetfn) { 166 ri->resetfn(&cpu->env, ri); 167 return; 168 } 169 170 /* A zero offset is never possible as it would be regs[0] 171 * so we use it to indicate that reset is being handled elsewhere. 172 * This is basically only used for fields in non-core coprocessors 173 * (like the pxa2xx ones). 174 */ 175 if (!ri->fieldoffset) { 176 return; 177 } 178 179 if (cpreg_field_is_64bit(ri)) { 180 CPREG_FIELD64(&cpu->env, ri) = ri->resetvalue; 181 } else { 182 CPREG_FIELD32(&cpu->env, ri) = ri->resetvalue; 183 } 184 } 185 186 static void cp_reg_check_reset(gpointer key, gpointer value, gpointer opaque) 187 { 188 /* Purely an assertion check: we've already done reset once, 189 * so now check that running the reset for the cpreg doesn't 190 * change its value. This traps bugs where two different cpregs 191 * both try to reset the same state field but to different values. 192 */ 193 ARMCPRegInfo *ri = value; 194 ARMCPU *cpu = opaque; 195 uint64_t oldvalue, newvalue; 196 197 if (ri->type & (ARM_CP_SPECIAL_MASK | ARM_CP_ALIAS | ARM_CP_NO_RAW)) { 198 return; 199 } 200 201 oldvalue = read_raw_cp_reg(&cpu->env, ri); 202 cp_reg_reset(key, value, opaque); 203 newvalue = read_raw_cp_reg(&cpu->env, ri); 204 assert(oldvalue == newvalue); 205 } 206 207 static void arm_cpu_reset_hold(Object *obj) 208 { 209 CPUState *s = CPU(obj); 210 ARMCPU *cpu = ARM_CPU(s); 211 ARMCPUClass *acc = ARM_CPU_GET_CLASS(cpu); 212 CPUARMState *env = &cpu->env; 213 214 if (acc->parent_phases.hold) { 215 acc->parent_phases.hold(obj); 216 } 217 218 memset(env, 0, offsetof(CPUARMState, end_reset_fields)); 219 220 g_hash_table_foreach(cpu->cp_regs, cp_reg_reset, cpu); 221 g_hash_table_foreach(cpu->cp_regs, cp_reg_check_reset, cpu); 222 223 env->vfp.xregs[ARM_VFP_FPSID] = cpu->reset_fpsid; 224 env->vfp.xregs[ARM_VFP_MVFR0] = cpu->isar.mvfr0; 225 env->vfp.xregs[ARM_VFP_MVFR1] = cpu->isar.mvfr1; 226 env->vfp.xregs[ARM_VFP_MVFR2] = cpu->isar.mvfr2; 227 228 cpu->power_state = s->start_powered_off ? PSCI_OFF : PSCI_ON; 229 230 if (arm_feature(env, ARM_FEATURE_IWMMXT)) { 231 env->iwmmxt.cregs[ARM_IWMMXT_wCID] = 0x69051000 | 'Q'; 232 } 233 234 if (arm_feature(env, ARM_FEATURE_AARCH64)) { 235 /* 64 bit CPUs always start in 64 bit mode */ 236 env->aarch64 = true; 237 #if defined(CONFIG_USER_ONLY) 238 env->pstate = PSTATE_MODE_EL0t; 239 /* Userspace expects access to DC ZVA, CTL_EL0 and the cache ops */ 240 env->cp15.sctlr_el[1] |= SCTLR_UCT | SCTLR_UCI | SCTLR_DZE; 241 /* Enable all PAC keys. */ 242 env->cp15.sctlr_el[1] |= (SCTLR_EnIA | SCTLR_EnIB | 243 SCTLR_EnDA | SCTLR_EnDB); 244 /* Trap on btype=3 for PACIxSP. */ 245 env->cp15.sctlr_el[1] |= SCTLR_BT0; 246 /* and to the FP/Neon instructions */ 247 env->cp15.cpacr_el1 = FIELD_DP64(env->cp15.cpacr_el1, 248 CPACR_EL1, FPEN, 3); 249 /* and to the SVE instructions, with default vector length */ 250 if (cpu_isar_feature(aa64_sve, cpu)) { 251 env->cp15.cpacr_el1 = FIELD_DP64(env->cp15.cpacr_el1, 252 CPACR_EL1, ZEN, 3); 253 env->vfp.zcr_el[1] = cpu->sve_default_vq - 1; 254 } 255 /* and for SME instructions, with default vector length, and TPIDR2 */ 256 if (cpu_isar_feature(aa64_sme, cpu)) { 257 env->cp15.sctlr_el[1] |= SCTLR_EnTP2; 258 env->cp15.cpacr_el1 = FIELD_DP64(env->cp15.cpacr_el1, 259 CPACR_EL1, SMEN, 3); 260 env->vfp.smcr_el[1] = cpu->sme_default_vq - 1; 261 if (cpu_isar_feature(aa64_sme_fa64, cpu)) { 262 env->vfp.smcr_el[1] = FIELD_DP64(env->vfp.smcr_el[1], 263 SMCR, FA64, 1); 264 } 265 } 266 /* 267 * Enable 48-bit address space (TODO: take reserved_va into account). 268 * Enable TBI0 but not TBI1. 269 * Note that this must match useronly_clean_ptr. 270 */ 271 env->cp15.tcr_el[1] = 5 | (1ULL << 37); 272 273 /* Enable MTE */ 274 if (cpu_isar_feature(aa64_mte, cpu)) { 275 /* Enable tag access, but leave TCF0 as No Effect (0). */ 276 env->cp15.sctlr_el[1] |= SCTLR_ATA0; 277 /* 278 * Exclude all tags, so that tag 0 is always used. 279 * This corresponds to Linux current->thread.gcr_incl = 0. 280 * 281 * Set RRND, so that helper_irg() will generate a seed later. 282 * Here in cpu_reset(), the crypto subsystem has not yet been 283 * initialized. 284 */ 285 env->cp15.gcr_el1 = 0x1ffff; 286 } 287 /* 288 * Disable access to SCXTNUM_EL0 from CSV2_1p2. 289 * This is not yet exposed from the Linux kernel in any way. 290 */ 291 env->cp15.sctlr_el[1] |= SCTLR_TSCXT; 292 /* Disable access to Debug Communication Channel (DCC). */ 293 env->cp15.mdscr_el1 |= 1 << 12; 294 #else 295 /* Reset into the highest available EL */ 296 if (arm_feature(env, ARM_FEATURE_EL3)) { 297 env->pstate = PSTATE_MODE_EL3h; 298 } else if (arm_feature(env, ARM_FEATURE_EL2)) { 299 env->pstate = PSTATE_MODE_EL2h; 300 } else { 301 env->pstate = PSTATE_MODE_EL1h; 302 } 303 304 /* Sample rvbar at reset. */ 305 env->cp15.rvbar = cpu->rvbar_prop; 306 env->pc = env->cp15.rvbar; 307 #endif 308 } else { 309 #if defined(CONFIG_USER_ONLY) 310 /* Userspace expects access to cp10 and cp11 for FP/Neon */ 311 env->cp15.cpacr_el1 = FIELD_DP64(env->cp15.cpacr_el1, 312 CPACR, CP10, 3); 313 env->cp15.cpacr_el1 = FIELD_DP64(env->cp15.cpacr_el1, 314 CPACR, CP11, 3); 315 #endif 316 if (arm_feature(env, ARM_FEATURE_V8)) { 317 env->cp15.rvbar = cpu->rvbar_prop; 318 env->regs[15] = cpu->rvbar_prop; 319 } 320 } 321 322 #if defined(CONFIG_USER_ONLY) 323 env->uncached_cpsr = ARM_CPU_MODE_USR; 324 /* For user mode we must enable access to coprocessors */ 325 env->vfp.xregs[ARM_VFP_FPEXC] = 1 << 30; 326 if (arm_feature(env, ARM_FEATURE_IWMMXT)) { 327 env->cp15.c15_cpar = 3; 328 } else if (arm_feature(env, ARM_FEATURE_XSCALE)) { 329 env->cp15.c15_cpar = 1; 330 } 331 #else 332 333 /* 334 * If the highest available EL is EL2, AArch32 will start in Hyp 335 * mode; otherwise it starts in SVC. Note that if we start in 336 * AArch64 then these values in the uncached_cpsr will be ignored. 337 */ 338 if (arm_feature(env, ARM_FEATURE_EL2) && 339 !arm_feature(env, ARM_FEATURE_EL3)) { 340 env->uncached_cpsr = ARM_CPU_MODE_HYP; 341 } else { 342 env->uncached_cpsr = ARM_CPU_MODE_SVC; 343 } 344 env->daif = PSTATE_D | PSTATE_A | PSTATE_I | PSTATE_F; 345 346 /* AArch32 has a hard highvec setting of 0xFFFF0000. If we are currently 347 * executing as AArch32 then check if highvecs are enabled and 348 * adjust the PC accordingly. 349 */ 350 if (A32_BANKED_CURRENT_REG_GET(env, sctlr) & SCTLR_V) { 351 env->regs[15] = 0xFFFF0000; 352 } 353 354 env->vfp.xregs[ARM_VFP_FPEXC] = 0; 355 #endif 356 357 if (arm_feature(env, ARM_FEATURE_M)) { 358 #ifndef CONFIG_USER_ONLY 359 uint32_t initial_msp; /* Loaded from 0x0 */ 360 uint32_t initial_pc; /* Loaded from 0x4 */ 361 uint8_t *rom; 362 uint32_t vecbase; 363 #endif 364 365 if (cpu_isar_feature(aa32_lob, cpu)) { 366 /* 367 * LTPSIZE is constant 4 if MVE not implemented, and resets 368 * to an UNKNOWN value if MVE is implemented. We choose to 369 * always reset to 4. 370 */ 371 env->v7m.ltpsize = 4; 372 /* The LTPSIZE field in FPDSCR is constant and reads as 4. */ 373 env->v7m.fpdscr[M_REG_NS] = 4 << FPCR_LTPSIZE_SHIFT; 374 env->v7m.fpdscr[M_REG_S] = 4 << FPCR_LTPSIZE_SHIFT; 375 } 376 377 if (arm_feature(env, ARM_FEATURE_M_SECURITY)) { 378 env->v7m.secure = true; 379 } else { 380 /* This bit resets to 0 if security is supported, but 1 if 381 * it is not. The bit is not present in v7M, but we set it 382 * here so we can avoid having to make checks on it conditional 383 * on ARM_FEATURE_V8 (we don't let the guest see the bit). 384 */ 385 env->v7m.aircr = R_V7M_AIRCR_BFHFNMINS_MASK; 386 /* 387 * Set NSACR to indicate "NS access permitted to everything"; 388 * this avoids having to have all the tests of it being 389 * conditional on ARM_FEATURE_M_SECURITY. Note also that from 390 * v8.1M the guest-visible value of NSACR in a CPU without the 391 * Security Extension is 0xcff. 392 */ 393 env->v7m.nsacr = 0xcff; 394 } 395 396 /* In v7M the reset value of this bit is IMPDEF, but ARM recommends 397 * that it resets to 1, so QEMU always does that rather than making 398 * it dependent on CPU model. In v8M it is RES1. 399 */ 400 env->v7m.ccr[M_REG_NS] = R_V7M_CCR_STKALIGN_MASK; 401 env->v7m.ccr[M_REG_S] = R_V7M_CCR_STKALIGN_MASK; 402 if (arm_feature(env, ARM_FEATURE_V8)) { 403 /* in v8M the NONBASETHRDENA bit [0] is RES1 */ 404 env->v7m.ccr[M_REG_NS] |= R_V7M_CCR_NONBASETHRDENA_MASK; 405 env->v7m.ccr[M_REG_S] |= R_V7M_CCR_NONBASETHRDENA_MASK; 406 } 407 if (!arm_feature(env, ARM_FEATURE_M_MAIN)) { 408 env->v7m.ccr[M_REG_NS] |= R_V7M_CCR_UNALIGN_TRP_MASK; 409 env->v7m.ccr[M_REG_S] |= R_V7M_CCR_UNALIGN_TRP_MASK; 410 } 411 412 if (cpu_isar_feature(aa32_vfp_simd, cpu)) { 413 env->v7m.fpccr[M_REG_NS] = R_V7M_FPCCR_ASPEN_MASK; 414 env->v7m.fpccr[M_REG_S] = R_V7M_FPCCR_ASPEN_MASK | 415 R_V7M_FPCCR_LSPEN_MASK | R_V7M_FPCCR_S_MASK; 416 } 417 418 #ifndef CONFIG_USER_ONLY 419 /* Unlike A/R profile, M profile defines the reset LR value */ 420 env->regs[14] = 0xffffffff; 421 422 env->v7m.vecbase[M_REG_S] = cpu->init_svtor & 0xffffff80; 423 env->v7m.vecbase[M_REG_NS] = cpu->init_nsvtor & 0xffffff80; 424 425 /* Load the initial SP and PC from offset 0 and 4 in the vector table */ 426 vecbase = env->v7m.vecbase[env->v7m.secure]; 427 rom = rom_ptr_for_as(s->as, vecbase, 8); 428 if (rom) { 429 /* Address zero is covered by ROM which hasn't yet been 430 * copied into physical memory. 431 */ 432 initial_msp = ldl_p(rom); 433 initial_pc = ldl_p(rom + 4); 434 } else { 435 /* Address zero not covered by a ROM blob, or the ROM blob 436 * is in non-modifiable memory and this is a second reset after 437 * it got copied into memory. In the latter case, rom_ptr 438 * will return a NULL pointer and we should use ldl_phys instead. 439 */ 440 initial_msp = ldl_phys(s->as, vecbase); 441 initial_pc = ldl_phys(s->as, vecbase + 4); 442 } 443 444 qemu_log_mask(CPU_LOG_INT, 445 "Loaded reset SP 0x%x PC 0x%x from vector table\n", 446 initial_msp, initial_pc); 447 448 env->regs[13] = initial_msp & 0xFFFFFFFC; 449 env->regs[15] = initial_pc & ~1; 450 env->thumb = initial_pc & 1; 451 #else 452 /* 453 * For user mode we run non-secure and with access to the FPU. 454 * The FPU context is active (ie does not need further setup) 455 * and is owned by non-secure. 456 */ 457 env->v7m.secure = false; 458 env->v7m.nsacr = 0xcff; 459 env->v7m.cpacr[M_REG_NS] = 0xf0ffff; 460 env->v7m.fpccr[M_REG_S] &= 461 ~(R_V7M_FPCCR_LSPEN_MASK | R_V7M_FPCCR_S_MASK); 462 env->v7m.control[M_REG_S] |= R_V7M_CONTROL_FPCA_MASK; 463 #endif 464 } 465 466 /* M profile requires that reset clears the exclusive monitor; 467 * A profile does not, but clearing it makes more sense than having it 468 * set with an exclusive access on address zero. 469 */ 470 arm_clear_exclusive(env); 471 472 if (arm_feature(env, ARM_FEATURE_PMSA)) { 473 if (cpu->pmsav7_dregion > 0) { 474 if (arm_feature(env, ARM_FEATURE_V8)) { 475 memset(env->pmsav8.rbar[M_REG_NS], 0, 476 sizeof(*env->pmsav8.rbar[M_REG_NS]) 477 * cpu->pmsav7_dregion); 478 memset(env->pmsav8.rlar[M_REG_NS], 0, 479 sizeof(*env->pmsav8.rlar[M_REG_NS]) 480 * cpu->pmsav7_dregion); 481 if (arm_feature(env, ARM_FEATURE_M_SECURITY)) { 482 memset(env->pmsav8.rbar[M_REG_S], 0, 483 sizeof(*env->pmsav8.rbar[M_REG_S]) 484 * cpu->pmsav7_dregion); 485 memset(env->pmsav8.rlar[M_REG_S], 0, 486 sizeof(*env->pmsav8.rlar[M_REG_S]) 487 * cpu->pmsav7_dregion); 488 } 489 } else if (arm_feature(env, ARM_FEATURE_V7)) { 490 memset(env->pmsav7.drbar, 0, 491 sizeof(*env->pmsav7.drbar) * cpu->pmsav7_dregion); 492 memset(env->pmsav7.drsr, 0, 493 sizeof(*env->pmsav7.drsr) * cpu->pmsav7_dregion); 494 memset(env->pmsav7.dracr, 0, 495 sizeof(*env->pmsav7.dracr) * cpu->pmsav7_dregion); 496 } 497 } 498 499 if (cpu->pmsav8r_hdregion > 0) { 500 memset(env->pmsav8.hprbar, 0, 501 sizeof(*env->pmsav8.hprbar) * cpu->pmsav8r_hdregion); 502 memset(env->pmsav8.hprlar, 0, 503 sizeof(*env->pmsav8.hprlar) * cpu->pmsav8r_hdregion); 504 } 505 506 env->pmsav7.rnr[M_REG_NS] = 0; 507 env->pmsav7.rnr[M_REG_S] = 0; 508 env->pmsav8.mair0[M_REG_NS] = 0; 509 env->pmsav8.mair0[M_REG_S] = 0; 510 env->pmsav8.mair1[M_REG_NS] = 0; 511 env->pmsav8.mair1[M_REG_S] = 0; 512 } 513 514 if (arm_feature(env, ARM_FEATURE_M_SECURITY)) { 515 if (cpu->sau_sregion > 0) { 516 memset(env->sau.rbar, 0, sizeof(*env->sau.rbar) * cpu->sau_sregion); 517 memset(env->sau.rlar, 0, sizeof(*env->sau.rlar) * cpu->sau_sregion); 518 } 519 env->sau.rnr = 0; 520 /* SAU_CTRL reset value is IMPDEF; we choose 0, which is what 521 * the Cortex-M33 does. 522 */ 523 env->sau.ctrl = 0; 524 } 525 526 set_flush_to_zero(1, &env->vfp.standard_fp_status); 527 set_flush_inputs_to_zero(1, &env->vfp.standard_fp_status); 528 set_default_nan_mode(1, &env->vfp.standard_fp_status); 529 set_default_nan_mode(1, &env->vfp.standard_fp_status_f16); 530 set_float_detect_tininess(float_tininess_before_rounding, 531 &env->vfp.fp_status); 532 set_float_detect_tininess(float_tininess_before_rounding, 533 &env->vfp.standard_fp_status); 534 set_float_detect_tininess(float_tininess_before_rounding, 535 &env->vfp.fp_status_f16); 536 set_float_detect_tininess(float_tininess_before_rounding, 537 &env->vfp.standard_fp_status_f16); 538 #ifndef CONFIG_USER_ONLY 539 if (kvm_enabled()) { 540 kvm_arm_reset_vcpu(cpu); 541 } 542 #endif 543 544 if (tcg_enabled()) { 545 hw_breakpoint_update_all(cpu); 546 hw_watchpoint_update_all(cpu); 547 548 arm_rebuild_hflags(env); 549 } 550 } 551 552 #if defined(CONFIG_TCG) && !defined(CONFIG_USER_ONLY) 553 554 static inline bool arm_excp_unmasked(CPUState *cs, unsigned int excp_idx, 555 unsigned int target_el, 556 unsigned int cur_el, bool secure, 557 uint64_t hcr_el2) 558 { 559 CPUARMState *env = cs->env_ptr; 560 bool pstate_unmasked; 561 bool unmasked = false; 562 563 /* 564 * Don't take exceptions if they target a lower EL. 565 * This check should catch any exceptions that would not be taken 566 * but left pending. 567 */ 568 if (cur_el > target_el) { 569 return false; 570 } 571 572 switch (excp_idx) { 573 case EXCP_FIQ: 574 pstate_unmasked = !(env->daif & PSTATE_F); 575 break; 576 577 case EXCP_IRQ: 578 pstate_unmasked = !(env->daif & PSTATE_I); 579 break; 580 581 case EXCP_VFIQ: 582 if (!(hcr_el2 & HCR_FMO) || (hcr_el2 & HCR_TGE)) { 583 /* VFIQs are only taken when hypervized. */ 584 return false; 585 } 586 return !(env->daif & PSTATE_F); 587 case EXCP_VIRQ: 588 if (!(hcr_el2 & HCR_IMO) || (hcr_el2 & HCR_TGE)) { 589 /* VIRQs are only taken when hypervized. */ 590 return false; 591 } 592 return !(env->daif & PSTATE_I); 593 case EXCP_VSERR: 594 if (!(hcr_el2 & HCR_AMO) || (hcr_el2 & HCR_TGE)) { 595 /* VIRQs are only taken when hypervized. */ 596 return false; 597 } 598 return !(env->daif & PSTATE_A); 599 default: 600 g_assert_not_reached(); 601 } 602 603 /* 604 * Use the target EL, current execution state and SCR/HCR settings to 605 * determine whether the corresponding CPSR bit is used to mask the 606 * interrupt. 607 */ 608 if ((target_el > cur_el) && (target_el != 1)) { 609 /* Exceptions targeting a higher EL may not be maskable */ 610 if (arm_feature(env, ARM_FEATURE_AARCH64)) { 611 switch (target_el) { 612 case 2: 613 /* 614 * According to ARM DDI 0487H.a, an interrupt can be masked 615 * when HCR_E2H and HCR_TGE are both set regardless of the 616 * current Security state. Note that we need to revisit this 617 * part again once we need to support NMI. 618 */ 619 if ((hcr_el2 & (HCR_E2H | HCR_TGE)) != (HCR_E2H | HCR_TGE)) { 620 unmasked = true; 621 } 622 break; 623 case 3: 624 /* Interrupt cannot be masked when the target EL is 3 */ 625 unmasked = true; 626 break; 627 default: 628 g_assert_not_reached(); 629 } 630 } else { 631 /* 632 * The old 32-bit-only environment has a more complicated 633 * masking setup. HCR and SCR bits not only affect interrupt 634 * routing but also change the behaviour of masking. 635 */ 636 bool hcr, scr; 637 638 switch (excp_idx) { 639 case EXCP_FIQ: 640 /* 641 * If FIQs are routed to EL3 or EL2 then there are cases where 642 * we override the CPSR.F in determining if the exception is 643 * masked or not. If neither of these are set then we fall back 644 * to the CPSR.F setting otherwise we further assess the state 645 * below. 646 */ 647 hcr = hcr_el2 & HCR_FMO; 648 scr = (env->cp15.scr_el3 & SCR_FIQ); 649 650 /* 651 * When EL3 is 32-bit, the SCR.FW bit controls whether the 652 * CPSR.F bit masks FIQ interrupts when taken in non-secure 653 * state. If SCR.FW is set then FIQs can be masked by CPSR.F 654 * when non-secure but only when FIQs are only routed to EL3. 655 */ 656 scr = scr && !((env->cp15.scr_el3 & SCR_FW) && !hcr); 657 break; 658 case EXCP_IRQ: 659 /* 660 * When EL3 execution state is 32-bit, if HCR.IMO is set then 661 * we may override the CPSR.I masking when in non-secure state. 662 * The SCR.IRQ setting has already been taken into consideration 663 * when setting the target EL, so it does not have a further 664 * affect here. 665 */ 666 hcr = hcr_el2 & HCR_IMO; 667 scr = false; 668 break; 669 default: 670 g_assert_not_reached(); 671 } 672 673 if ((scr || hcr) && !secure) { 674 unmasked = true; 675 } 676 } 677 } 678 679 /* 680 * The PSTATE bits only mask the interrupt if we have not overridden the 681 * ability above. 682 */ 683 return unmasked || pstate_unmasked; 684 } 685 686 static bool arm_cpu_exec_interrupt(CPUState *cs, int interrupt_request) 687 { 688 CPUClass *cc = CPU_GET_CLASS(cs); 689 CPUARMState *env = cs->env_ptr; 690 uint32_t cur_el = arm_current_el(env); 691 bool secure = arm_is_secure(env); 692 uint64_t hcr_el2 = arm_hcr_el2_eff(env); 693 uint32_t target_el; 694 uint32_t excp_idx; 695 696 /* The prioritization of interrupts is IMPLEMENTATION DEFINED. */ 697 698 if (interrupt_request & CPU_INTERRUPT_FIQ) { 699 excp_idx = EXCP_FIQ; 700 target_el = arm_phys_excp_target_el(cs, excp_idx, cur_el, secure); 701 if (arm_excp_unmasked(cs, excp_idx, target_el, 702 cur_el, secure, hcr_el2)) { 703 goto found; 704 } 705 } 706 if (interrupt_request & CPU_INTERRUPT_HARD) { 707 excp_idx = EXCP_IRQ; 708 target_el = arm_phys_excp_target_el(cs, excp_idx, cur_el, secure); 709 if (arm_excp_unmasked(cs, excp_idx, target_el, 710 cur_el, secure, hcr_el2)) { 711 goto found; 712 } 713 } 714 if (interrupt_request & CPU_INTERRUPT_VIRQ) { 715 excp_idx = EXCP_VIRQ; 716 target_el = 1; 717 if (arm_excp_unmasked(cs, excp_idx, target_el, 718 cur_el, secure, hcr_el2)) { 719 goto found; 720 } 721 } 722 if (interrupt_request & CPU_INTERRUPT_VFIQ) { 723 excp_idx = EXCP_VFIQ; 724 target_el = 1; 725 if (arm_excp_unmasked(cs, excp_idx, target_el, 726 cur_el, secure, hcr_el2)) { 727 goto found; 728 } 729 } 730 if (interrupt_request & CPU_INTERRUPT_VSERR) { 731 excp_idx = EXCP_VSERR; 732 target_el = 1; 733 if (arm_excp_unmasked(cs, excp_idx, target_el, 734 cur_el, secure, hcr_el2)) { 735 /* Taking a virtual abort clears HCR_EL2.VSE */ 736 env->cp15.hcr_el2 &= ~HCR_VSE; 737 cpu_reset_interrupt(cs, CPU_INTERRUPT_VSERR); 738 goto found; 739 } 740 } 741 return false; 742 743 found: 744 cs->exception_index = excp_idx; 745 env->exception.target_el = target_el; 746 cc->tcg_ops->do_interrupt(cs); 747 return true; 748 } 749 750 #endif /* CONFIG_TCG && !CONFIG_USER_ONLY */ 751 752 void arm_cpu_update_virq(ARMCPU *cpu) 753 { 754 /* 755 * Update the interrupt level for VIRQ, which is the logical OR of 756 * the HCR_EL2.VI bit and the input line level from the GIC. 757 */ 758 CPUARMState *env = &cpu->env; 759 CPUState *cs = CPU(cpu); 760 761 bool new_state = (env->cp15.hcr_el2 & HCR_VI) || 762 (env->irq_line_state & CPU_INTERRUPT_VIRQ); 763 764 if (new_state != ((cs->interrupt_request & CPU_INTERRUPT_VIRQ) != 0)) { 765 if (new_state) { 766 cpu_interrupt(cs, CPU_INTERRUPT_VIRQ); 767 } else { 768 cpu_reset_interrupt(cs, CPU_INTERRUPT_VIRQ); 769 } 770 } 771 } 772 773 void arm_cpu_update_vfiq(ARMCPU *cpu) 774 { 775 /* 776 * Update the interrupt level for VFIQ, which is the logical OR of 777 * the HCR_EL2.VF bit and the input line level from the GIC. 778 */ 779 CPUARMState *env = &cpu->env; 780 CPUState *cs = CPU(cpu); 781 782 bool new_state = (env->cp15.hcr_el2 & HCR_VF) || 783 (env->irq_line_state & CPU_INTERRUPT_VFIQ); 784 785 if (new_state != ((cs->interrupt_request & CPU_INTERRUPT_VFIQ) != 0)) { 786 if (new_state) { 787 cpu_interrupt(cs, CPU_INTERRUPT_VFIQ); 788 } else { 789 cpu_reset_interrupt(cs, CPU_INTERRUPT_VFIQ); 790 } 791 } 792 } 793 794 void arm_cpu_update_vserr(ARMCPU *cpu) 795 { 796 /* 797 * Update the interrupt level for VSERR, which is the HCR_EL2.VSE bit. 798 */ 799 CPUARMState *env = &cpu->env; 800 CPUState *cs = CPU(cpu); 801 802 bool new_state = env->cp15.hcr_el2 & HCR_VSE; 803 804 if (new_state != ((cs->interrupt_request & CPU_INTERRUPT_VSERR) != 0)) { 805 if (new_state) { 806 cpu_interrupt(cs, CPU_INTERRUPT_VSERR); 807 } else { 808 cpu_reset_interrupt(cs, CPU_INTERRUPT_VSERR); 809 } 810 } 811 } 812 813 #ifndef CONFIG_USER_ONLY 814 static void arm_cpu_set_irq(void *opaque, int irq, int level) 815 { 816 ARMCPU *cpu = opaque; 817 CPUARMState *env = &cpu->env; 818 CPUState *cs = CPU(cpu); 819 static const int mask[] = { 820 [ARM_CPU_IRQ] = CPU_INTERRUPT_HARD, 821 [ARM_CPU_FIQ] = CPU_INTERRUPT_FIQ, 822 [ARM_CPU_VIRQ] = CPU_INTERRUPT_VIRQ, 823 [ARM_CPU_VFIQ] = CPU_INTERRUPT_VFIQ 824 }; 825 826 if (!arm_feature(env, ARM_FEATURE_EL2) && 827 (irq == ARM_CPU_VIRQ || irq == ARM_CPU_VFIQ)) { 828 /* 829 * The GIC might tell us about VIRQ and VFIQ state, but if we don't 830 * have EL2 support we don't care. (Unless the guest is doing something 831 * silly this will only be calls saying "level is still 0".) 832 */ 833 return; 834 } 835 836 if (level) { 837 env->irq_line_state |= mask[irq]; 838 } else { 839 env->irq_line_state &= ~mask[irq]; 840 } 841 842 switch (irq) { 843 case ARM_CPU_VIRQ: 844 arm_cpu_update_virq(cpu); 845 break; 846 case ARM_CPU_VFIQ: 847 arm_cpu_update_vfiq(cpu); 848 break; 849 case ARM_CPU_IRQ: 850 case ARM_CPU_FIQ: 851 if (level) { 852 cpu_interrupt(cs, mask[irq]); 853 } else { 854 cpu_reset_interrupt(cs, mask[irq]); 855 } 856 break; 857 default: 858 g_assert_not_reached(); 859 } 860 } 861 862 static void arm_cpu_kvm_set_irq(void *opaque, int irq, int level) 863 { 864 #ifdef CONFIG_KVM 865 ARMCPU *cpu = opaque; 866 CPUARMState *env = &cpu->env; 867 CPUState *cs = CPU(cpu); 868 uint32_t linestate_bit; 869 int irq_id; 870 871 switch (irq) { 872 case ARM_CPU_IRQ: 873 irq_id = KVM_ARM_IRQ_CPU_IRQ; 874 linestate_bit = CPU_INTERRUPT_HARD; 875 break; 876 case ARM_CPU_FIQ: 877 irq_id = KVM_ARM_IRQ_CPU_FIQ; 878 linestate_bit = CPU_INTERRUPT_FIQ; 879 break; 880 default: 881 g_assert_not_reached(); 882 } 883 884 if (level) { 885 env->irq_line_state |= linestate_bit; 886 } else { 887 env->irq_line_state &= ~linestate_bit; 888 } 889 kvm_arm_set_irq(cs->cpu_index, KVM_ARM_IRQ_TYPE_CPU, irq_id, !!level); 890 #endif 891 } 892 893 static bool arm_cpu_virtio_is_big_endian(CPUState *cs) 894 { 895 ARMCPU *cpu = ARM_CPU(cs); 896 CPUARMState *env = &cpu->env; 897 898 cpu_synchronize_state(cs); 899 return arm_cpu_data_is_big_endian(env); 900 } 901 902 #endif 903 904 static void arm_disas_set_info(CPUState *cpu, disassemble_info *info) 905 { 906 ARMCPU *ac = ARM_CPU(cpu); 907 CPUARMState *env = &ac->env; 908 bool sctlr_b; 909 910 if (is_a64(env)) { 911 info->cap_arch = CS_ARCH_ARM64; 912 info->cap_insn_unit = 4; 913 info->cap_insn_split = 4; 914 } else { 915 int cap_mode; 916 if (env->thumb) { 917 info->cap_insn_unit = 2; 918 info->cap_insn_split = 4; 919 cap_mode = CS_MODE_THUMB; 920 } else { 921 info->cap_insn_unit = 4; 922 info->cap_insn_split = 4; 923 cap_mode = CS_MODE_ARM; 924 } 925 if (arm_feature(env, ARM_FEATURE_V8)) { 926 cap_mode |= CS_MODE_V8; 927 } 928 if (arm_feature(env, ARM_FEATURE_M)) { 929 cap_mode |= CS_MODE_MCLASS; 930 } 931 info->cap_arch = CS_ARCH_ARM; 932 info->cap_mode = cap_mode; 933 } 934 935 sctlr_b = arm_sctlr_b(env); 936 if (bswap_code(sctlr_b)) { 937 #if TARGET_BIG_ENDIAN 938 info->endian = BFD_ENDIAN_LITTLE; 939 #else 940 info->endian = BFD_ENDIAN_BIG; 941 #endif 942 } 943 info->flags &= ~INSN_ARM_BE32; 944 #ifndef CONFIG_USER_ONLY 945 if (sctlr_b) { 946 info->flags |= INSN_ARM_BE32; 947 } 948 #endif 949 } 950 951 #ifdef TARGET_AARCH64 952 953 static void aarch64_cpu_dump_state(CPUState *cs, FILE *f, int flags) 954 { 955 ARMCPU *cpu = ARM_CPU(cs); 956 CPUARMState *env = &cpu->env; 957 uint32_t psr = pstate_read(env); 958 int i, j; 959 int el = arm_current_el(env); 960 const char *ns_status; 961 bool sve; 962 963 qemu_fprintf(f, " PC=%016" PRIx64 " ", env->pc); 964 for (i = 0; i < 32; i++) { 965 if (i == 31) { 966 qemu_fprintf(f, " SP=%016" PRIx64 "\n", env->xregs[i]); 967 } else { 968 qemu_fprintf(f, "X%02d=%016" PRIx64 "%s", i, env->xregs[i], 969 (i + 2) % 3 ? " " : "\n"); 970 } 971 } 972 973 if (arm_feature(env, ARM_FEATURE_EL3) && el != 3) { 974 ns_status = env->cp15.scr_el3 & SCR_NS ? "NS " : "S "; 975 } else { 976 ns_status = ""; 977 } 978 qemu_fprintf(f, "PSTATE=%08x %c%c%c%c %sEL%d%c", 979 psr, 980 psr & PSTATE_N ? 'N' : '-', 981 psr & PSTATE_Z ? 'Z' : '-', 982 psr & PSTATE_C ? 'C' : '-', 983 psr & PSTATE_V ? 'V' : '-', 984 ns_status, 985 el, 986 psr & PSTATE_SP ? 'h' : 't'); 987 988 if (cpu_isar_feature(aa64_sme, cpu)) { 989 qemu_fprintf(f, " SVCR=%08" PRIx64 " %c%c", 990 env->svcr, 991 (FIELD_EX64(env->svcr, SVCR, ZA) ? 'Z' : '-'), 992 (FIELD_EX64(env->svcr, SVCR, SM) ? 'S' : '-')); 993 } 994 if (cpu_isar_feature(aa64_bti, cpu)) { 995 qemu_fprintf(f, " BTYPE=%d", (psr & PSTATE_BTYPE) >> 10); 996 } 997 if (!(flags & CPU_DUMP_FPU)) { 998 qemu_fprintf(f, "\n"); 999 return; 1000 } 1001 if (fp_exception_el(env, el) != 0) { 1002 qemu_fprintf(f, " FPU disabled\n"); 1003 return; 1004 } 1005 qemu_fprintf(f, " FPCR=%08x FPSR=%08x\n", 1006 vfp_get_fpcr(env), vfp_get_fpsr(env)); 1007 1008 if (cpu_isar_feature(aa64_sme, cpu) && FIELD_EX64(env->svcr, SVCR, SM)) { 1009 sve = sme_exception_el(env, el) == 0; 1010 } else if (cpu_isar_feature(aa64_sve, cpu)) { 1011 sve = sve_exception_el(env, el) == 0; 1012 } else { 1013 sve = false; 1014 } 1015 1016 if (sve) { 1017 int zcr_len = sve_vqm1_for_el(env, el); 1018 1019 for (i = 0; i <= FFR_PRED_NUM; i++) { 1020 bool eol; 1021 if (i == FFR_PRED_NUM) { 1022 qemu_fprintf(f, "FFR="); 1023 /* It's last, so end the line. */ 1024 eol = true; 1025 } else { 1026 qemu_fprintf(f, "P%02d=", i); 1027 switch (zcr_len) { 1028 case 0: 1029 eol = i % 8 == 7; 1030 break; 1031 case 1: 1032 eol = i % 6 == 5; 1033 break; 1034 case 2: 1035 case 3: 1036 eol = i % 3 == 2; 1037 break; 1038 default: 1039 /* More than one quadword per predicate. */ 1040 eol = true; 1041 break; 1042 } 1043 } 1044 for (j = zcr_len / 4; j >= 0; j--) { 1045 int digits; 1046 if (j * 4 + 4 <= zcr_len + 1) { 1047 digits = 16; 1048 } else { 1049 digits = (zcr_len % 4 + 1) * 4; 1050 } 1051 qemu_fprintf(f, "%0*" PRIx64 "%s", digits, 1052 env->vfp.pregs[i].p[j], 1053 j ? ":" : eol ? "\n" : " "); 1054 } 1055 } 1056 1057 if (zcr_len == 0) { 1058 /* 1059 * With vl=16, there are only 37 columns per register, 1060 * so output two registers per line. 1061 */ 1062 for (i = 0; i < 32; i++) { 1063 qemu_fprintf(f, "Z%02d=%016" PRIx64 ":%016" PRIx64 "%s", 1064 i, env->vfp.zregs[i].d[1], 1065 env->vfp.zregs[i].d[0], i & 1 ? "\n" : " "); 1066 } 1067 } else { 1068 for (i = 0; i < 32; i++) { 1069 qemu_fprintf(f, "Z%02d=", i); 1070 for (j = zcr_len; j >= 0; j--) { 1071 qemu_fprintf(f, "%016" PRIx64 ":%016" PRIx64 "%s", 1072 env->vfp.zregs[i].d[j * 2 + 1], 1073 env->vfp.zregs[i].d[j * 2 + 0], 1074 j ? ":" : "\n"); 1075 } 1076 } 1077 } 1078 } else { 1079 for (i = 0; i < 32; i++) { 1080 uint64_t *q = aa64_vfp_qreg(env, i); 1081 qemu_fprintf(f, "Q%02d=%016" PRIx64 ":%016" PRIx64 "%s", 1082 i, q[1], q[0], (i & 1 ? "\n" : " ")); 1083 } 1084 } 1085 1086 if (cpu_isar_feature(aa64_sme, cpu) && 1087 FIELD_EX64(env->svcr, SVCR, ZA) && 1088 sme_exception_el(env, el) == 0) { 1089 int zcr_len = sve_vqm1_for_el_sm(env, el, true); 1090 int svl = (zcr_len + 1) * 16; 1091 int svl_lg10 = svl < 100 ? 2 : 3; 1092 1093 for (i = 0; i < svl; i++) { 1094 qemu_fprintf(f, "ZA[%0*d]=", svl_lg10, i); 1095 for (j = zcr_len; j >= 0; --j) { 1096 qemu_fprintf(f, "%016" PRIx64 ":%016" PRIx64 "%c", 1097 env->zarray[i].d[2 * j + 1], 1098 env->zarray[i].d[2 * j], 1099 j ? ':' : '\n'); 1100 } 1101 } 1102 } 1103 } 1104 1105 #else 1106 1107 static inline void aarch64_cpu_dump_state(CPUState *cs, FILE *f, int flags) 1108 { 1109 g_assert_not_reached(); 1110 } 1111 1112 #endif 1113 1114 static void arm_cpu_dump_state(CPUState *cs, FILE *f, int flags) 1115 { 1116 ARMCPU *cpu = ARM_CPU(cs); 1117 CPUARMState *env = &cpu->env; 1118 int i; 1119 1120 if (is_a64(env)) { 1121 aarch64_cpu_dump_state(cs, f, flags); 1122 return; 1123 } 1124 1125 for (i = 0; i < 16; i++) { 1126 qemu_fprintf(f, "R%02d=%08x", i, env->regs[i]); 1127 if ((i % 4) == 3) { 1128 qemu_fprintf(f, "\n"); 1129 } else { 1130 qemu_fprintf(f, " "); 1131 } 1132 } 1133 1134 if (arm_feature(env, ARM_FEATURE_M)) { 1135 uint32_t xpsr = xpsr_read(env); 1136 const char *mode; 1137 const char *ns_status = ""; 1138 1139 if (arm_feature(env, ARM_FEATURE_M_SECURITY)) { 1140 ns_status = env->v7m.secure ? "S " : "NS "; 1141 } 1142 1143 if (xpsr & XPSR_EXCP) { 1144 mode = "handler"; 1145 } else { 1146 if (env->v7m.control[env->v7m.secure] & R_V7M_CONTROL_NPRIV_MASK) { 1147 mode = "unpriv-thread"; 1148 } else { 1149 mode = "priv-thread"; 1150 } 1151 } 1152 1153 qemu_fprintf(f, "XPSR=%08x %c%c%c%c %c %s%s\n", 1154 xpsr, 1155 xpsr & XPSR_N ? 'N' : '-', 1156 xpsr & XPSR_Z ? 'Z' : '-', 1157 xpsr & XPSR_C ? 'C' : '-', 1158 xpsr & XPSR_V ? 'V' : '-', 1159 xpsr & XPSR_T ? 'T' : 'A', 1160 ns_status, 1161 mode); 1162 } else { 1163 uint32_t psr = cpsr_read(env); 1164 const char *ns_status = ""; 1165 1166 if (arm_feature(env, ARM_FEATURE_EL3) && 1167 (psr & CPSR_M) != ARM_CPU_MODE_MON) { 1168 ns_status = env->cp15.scr_el3 & SCR_NS ? "NS " : "S "; 1169 } 1170 1171 qemu_fprintf(f, "PSR=%08x %c%c%c%c %c %s%s%d\n", 1172 psr, 1173 psr & CPSR_N ? 'N' : '-', 1174 psr & CPSR_Z ? 'Z' : '-', 1175 psr & CPSR_C ? 'C' : '-', 1176 psr & CPSR_V ? 'V' : '-', 1177 psr & CPSR_T ? 'T' : 'A', 1178 ns_status, 1179 aarch32_mode_name(psr), (psr & 0x10) ? 32 : 26); 1180 } 1181 1182 if (flags & CPU_DUMP_FPU) { 1183 int numvfpregs = 0; 1184 if (cpu_isar_feature(aa32_simd_r32, cpu)) { 1185 numvfpregs = 32; 1186 } else if (cpu_isar_feature(aa32_vfp_simd, cpu)) { 1187 numvfpregs = 16; 1188 } 1189 for (i = 0; i < numvfpregs; i++) { 1190 uint64_t v = *aa32_vfp_dreg(env, i); 1191 qemu_fprintf(f, "s%02d=%08x s%02d=%08x d%02d=%016" PRIx64 "\n", 1192 i * 2, (uint32_t)v, 1193 i * 2 + 1, (uint32_t)(v >> 32), 1194 i, v); 1195 } 1196 qemu_fprintf(f, "FPSCR: %08x\n", vfp_get_fpscr(env)); 1197 if (cpu_isar_feature(aa32_mve, cpu)) { 1198 qemu_fprintf(f, "VPR: %08x\n", env->v7m.vpr); 1199 } 1200 } 1201 } 1202 1203 uint64_t arm_cpu_mp_affinity(int idx, uint8_t clustersz) 1204 { 1205 uint32_t Aff1 = idx / clustersz; 1206 uint32_t Aff0 = idx % clustersz; 1207 return (Aff1 << ARM_AFF1_SHIFT) | Aff0; 1208 } 1209 1210 static void arm_cpu_initfn(Object *obj) 1211 { 1212 ARMCPU *cpu = ARM_CPU(obj); 1213 1214 cpu_set_cpustate_pointers(cpu); 1215 cpu->cp_regs = g_hash_table_new_full(g_direct_hash, g_direct_equal, 1216 NULL, g_free); 1217 1218 QLIST_INIT(&cpu->pre_el_change_hooks); 1219 QLIST_INIT(&cpu->el_change_hooks); 1220 1221 #ifdef CONFIG_USER_ONLY 1222 # ifdef TARGET_AARCH64 1223 /* 1224 * The linux kernel defaults to 512-bit for SVE, and 256-bit for SME. 1225 * These values were chosen to fit within the default signal frame. 1226 * See documentation for /proc/sys/abi/{sve,sme}_default_vector_length, 1227 * and our corresponding cpu property. 1228 */ 1229 cpu->sve_default_vq = 4; 1230 cpu->sme_default_vq = 2; 1231 # endif 1232 #else 1233 /* Our inbound IRQ and FIQ lines */ 1234 if (kvm_enabled()) { 1235 /* VIRQ and VFIQ are unused with KVM but we add them to maintain 1236 * the same interface as non-KVM CPUs. 1237 */ 1238 qdev_init_gpio_in(DEVICE(cpu), arm_cpu_kvm_set_irq, 4); 1239 } else { 1240 qdev_init_gpio_in(DEVICE(cpu), arm_cpu_set_irq, 4); 1241 } 1242 1243 qdev_init_gpio_out(DEVICE(cpu), cpu->gt_timer_outputs, 1244 ARRAY_SIZE(cpu->gt_timer_outputs)); 1245 1246 qdev_init_gpio_out_named(DEVICE(cpu), &cpu->gicv3_maintenance_interrupt, 1247 "gicv3-maintenance-interrupt", 1); 1248 qdev_init_gpio_out_named(DEVICE(cpu), &cpu->pmu_interrupt, 1249 "pmu-interrupt", 1); 1250 #endif 1251 1252 /* DTB consumers generally don't in fact care what the 'compatible' 1253 * string is, so always provide some string and trust that a hypothetical 1254 * picky DTB consumer will also provide a helpful error message. 1255 */ 1256 cpu->dtb_compatible = "qemu,unknown"; 1257 cpu->psci_version = QEMU_PSCI_VERSION_0_1; /* By default assume PSCI v0.1 */ 1258 cpu->kvm_target = QEMU_KVM_ARM_TARGET_NONE; 1259 1260 if (tcg_enabled() || hvf_enabled()) { 1261 /* TCG and HVF implement PSCI 1.1 */ 1262 cpu->psci_version = QEMU_PSCI_VERSION_1_1; 1263 } 1264 } 1265 1266 static Property arm_cpu_gt_cntfrq_property = 1267 DEFINE_PROP_UINT64("cntfrq", ARMCPU, gt_cntfrq_hz, 1268 NANOSECONDS_PER_SECOND / GTIMER_SCALE); 1269 1270 static Property arm_cpu_reset_cbar_property = 1271 DEFINE_PROP_UINT64("reset-cbar", ARMCPU, reset_cbar, 0); 1272 1273 static Property arm_cpu_reset_hivecs_property = 1274 DEFINE_PROP_BOOL("reset-hivecs", ARMCPU, reset_hivecs, false); 1275 1276 #ifndef CONFIG_USER_ONLY 1277 static Property arm_cpu_has_el2_property = 1278 DEFINE_PROP_BOOL("has_el2", ARMCPU, has_el2, true); 1279 1280 static Property arm_cpu_has_el3_property = 1281 DEFINE_PROP_BOOL("has_el3", ARMCPU, has_el3, true); 1282 #endif 1283 1284 static Property arm_cpu_cfgend_property = 1285 DEFINE_PROP_BOOL("cfgend", ARMCPU, cfgend, false); 1286 1287 static Property arm_cpu_has_vfp_property = 1288 DEFINE_PROP_BOOL("vfp", ARMCPU, has_vfp, true); 1289 1290 static Property arm_cpu_has_vfp_d32_property = 1291 DEFINE_PROP_BOOL("vfp-d32", ARMCPU, has_vfp_d32, true); 1292 1293 static Property arm_cpu_has_neon_property = 1294 DEFINE_PROP_BOOL("neon", ARMCPU, has_neon, true); 1295 1296 static Property arm_cpu_has_dsp_property = 1297 DEFINE_PROP_BOOL("dsp", ARMCPU, has_dsp, true); 1298 1299 static Property arm_cpu_has_mpu_property = 1300 DEFINE_PROP_BOOL("has-mpu", ARMCPU, has_mpu, true); 1301 1302 /* This is like DEFINE_PROP_UINT32 but it doesn't set the default value, 1303 * because the CPU initfn will have already set cpu->pmsav7_dregion to 1304 * the right value for that particular CPU type, and we don't want 1305 * to override that with an incorrect constant value. 1306 */ 1307 static Property arm_cpu_pmsav7_dregion_property = 1308 DEFINE_PROP_UNSIGNED_NODEFAULT("pmsav7-dregion", ARMCPU, 1309 pmsav7_dregion, 1310 qdev_prop_uint32, uint32_t); 1311 1312 static bool arm_get_pmu(Object *obj, Error **errp) 1313 { 1314 ARMCPU *cpu = ARM_CPU(obj); 1315 1316 return cpu->has_pmu; 1317 } 1318 1319 static void arm_set_pmu(Object *obj, bool value, Error **errp) 1320 { 1321 ARMCPU *cpu = ARM_CPU(obj); 1322 1323 if (value) { 1324 if (kvm_enabled() && !kvm_arm_pmu_supported()) { 1325 error_setg(errp, "'pmu' feature not supported by KVM on this host"); 1326 return; 1327 } 1328 set_feature(&cpu->env, ARM_FEATURE_PMU); 1329 } else { 1330 unset_feature(&cpu->env, ARM_FEATURE_PMU); 1331 } 1332 cpu->has_pmu = value; 1333 } 1334 1335 unsigned int gt_cntfrq_period_ns(ARMCPU *cpu) 1336 { 1337 /* 1338 * The exact approach to calculating guest ticks is: 1339 * 1340 * muldiv64(qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL), cpu->gt_cntfrq_hz, 1341 * NANOSECONDS_PER_SECOND); 1342 * 1343 * We don't do that. Rather we intentionally use integer division 1344 * truncation below and in the caller for the conversion of host monotonic 1345 * time to guest ticks to provide the exact inverse for the semantics of 1346 * the QEMUTimer scale factor. QEMUTimer's scale facter is an integer, so 1347 * it loses precision when representing frequencies where 1348 * `(NANOSECONDS_PER_SECOND % cpu->gt_cntfrq) > 0` holds. Failing to 1349 * provide an exact inverse leads to scheduling timers with negative 1350 * periods, which in turn leads to sticky behaviour in the guest. 1351 * 1352 * Finally, CNTFRQ is effectively capped at 1GHz to ensure our scale factor 1353 * cannot become zero. 1354 */ 1355 return NANOSECONDS_PER_SECOND > cpu->gt_cntfrq_hz ? 1356 NANOSECONDS_PER_SECOND / cpu->gt_cntfrq_hz : 1; 1357 } 1358 1359 static void arm_cpu_propagate_feature_implications(ARMCPU *cpu) 1360 { 1361 CPUARMState *env = &cpu->env; 1362 bool no_aa32 = false; 1363 1364 /* 1365 * Some features automatically imply others: set the feature 1366 * bits explicitly for these cases. 1367 */ 1368 1369 if (arm_feature(env, ARM_FEATURE_M)) { 1370 set_feature(env, ARM_FEATURE_PMSA); 1371 } 1372 1373 if (arm_feature(env, ARM_FEATURE_V8)) { 1374 if (arm_feature(env, ARM_FEATURE_M)) { 1375 set_feature(env, ARM_FEATURE_V7); 1376 } else { 1377 set_feature(env, ARM_FEATURE_V7VE); 1378 } 1379 } 1380 1381 /* 1382 * There exist AArch64 cpus without AArch32 support. When KVM 1383 * queries ID_ISAR0_EL1 on such a host, the value is UNKNOWN. 1384 * Similarly, we cannot check ID_AA64PFR0 without AArch64 support. 1385 * As a general principle, we also do not make ID register 1386 * consistency checks anywhere unless using TCG, because only 1387 * for TCG would a consistency-check failure be a QEMU bug. 1388 */ 1389 if (arm_feature(&cpu->env, ARM_FEATURE_AARCH64)) { 1390 no_aa32 = !cpu_isar_feature(aa64_aa32, cpu); 1391 } 1392 1393 if (arm_feature(env, ARM_FEATURE_V7VE)) { 1394 /* 1395 * v7 Virtualization Extensions. In real hardware this implies 1396 * EL2 and also the presence of the Security Extensions. 1397 * For QEMU, for backwards-compatibility we implement some 1398 * CPUs or CPU configs which have no actual EL2 or EL3 but do 1399 * include the various other features that V7VE implies. 1400 * Presence of EL2 itself is ARM_FEATURE_EL2, and of the 1401 * Security Extensions is ARM_FEATURE_EL3. 1402 */ 1403 assert(!tcg_enabled() || no_aa32 || 1404 cpu_isar_feature(aa32_arm_div, cpu)); 1405 set_feature(env, ARM_FEATURE_LPAE); 1406 set_feature(env, ARM_FEATURE_V7); 1407 } 1408 if (arm_feature(env, ARM_FEATURE_V7)) { 1409 set_feature(env, ARM_FEATURE_VAPA); 1410 set_feature(env, ARM_FEATURE_THUMB2); 1411 set_feature(env, ARM_FEATURE_MPIDR); 1412 if (!arm_feature(env, ARM_FEATURE_M)) { 1413 set_feature(env, ARM_FEATURE_V6K); 1414 } else { 1415 set_feature(env, ARM_FEATURE_V6); 1416 } 1417 1418 /* 1419 * Always define VBAR for V7 CPUs even if it doesn't exist in 1420 * non-EL3 configs. This is needed by some legacy boards. 1421 */ 1422 set_feature(env, ARM_FEATURE_VBAR); 1423 } 1424 if (arm_feature(env, ARM_FEATURE_V6K)) { 1425 set_feature(env, ARM_FEATURE_V6); 1426 set_feature(env, ARM_FEATURE_MVFR); 1427 } 1428 if (arm_feature(env, ARM_FEATURE_V6)) { 1429 set_feature(env, ARM_FEATURE_V5); 1430 if (!arm_feature(env, ARM_FEATURE_M)) { 1431 assert(!tcg_enabled() || no_aa32 || 1432 cpu_isar_feature(aa32_jazelle, cpu)); 1433 set_feature(env, ARM_FEATURE_AUXCR); 1434 } 1435 } 1436 if (arm_feature(env, ARM_FEATURE_V5)) { 1437 set_feature(env, ARM_FEATURE_V4T); 1438 } 1439 if (arm_feature(env, ARM_FEATURE_LPAE)) { 1440 set_feature(env, ARM_FEATURE_V7MP); 1441 } 1442 if (arm_feature(env, ARM_FEATURE_CBAR_RO)) { 1443 set_feature(env, ARM_FEATURE_CBAR); 1444 } 1445 if (arm_feature(env, ARM_FEATURE_THUMB2) && 1446 !arm_feature(env, ARM_FEATURE_M)) { 1447 set_feature(env, ARM_FEATURE_THUMB_DSP); 1448 } 1449 } 1450 1451 void arm_cpu_post_init(Object *obj) 1452 { 1453 ARMCPU *cpu = ARM_CPU(obj); 1454 1455 /* 1456 * Some features imply others. Figure this out now, because we 1457 * are going to look at the feature bits in deciding which 1458 * properties to add. 1459 */ 1460 arm_cpu_propagate_feature_implications(cpu); 1461 1462 if (arm_feature(&cpu->env, ARM_FEATURE_CBAR) || 1463 arm_feature(&cpu->env, ARM_FEATURE_CBAR_RO)) { 1464 qdev_property_add_static(DEVICE(obj), &arm_cpu_reset_cbar_property); 1465 } 1466 1467 if (!arm_feature(&cpu->env, ARM_FEATURE_M)) { 1468 qdev_property_add_static(DEVICE(obj), &arm_cpu_reset_hivecs_property); 1469 } 1470 1471 if (arm_feature(&cpu->env, ARM_FEATURE_V8)) { 1472 object_property_add_uint64_ptr(obj, "rvbar", 1473 &cpu->rvbar_prop, 1474 OBJ_PROP_FLAG_READWRITE); 1475 } 1476 1477 #ifndef CONFIG_USER_ONLY 1478 if (arm_feature(&cpu->env, ARM_FEATURE_EL3)) { 1479 /* Add the has_el3 state CPU property only if EL3 is allowed. This will 1480 * prevent "has_el3" from existing on CPUs which cannot support EL3. 1481 */ 1482 qdev_property_add_static(DEVICE(obj), &arm_cpu_has_el3_property); 1483 1484 object_property_add_link(obj, "secure-memory", 1485 TYPE_MEMORY_REGION, 1486 (Object **)&cpu->secure_memory, 1487 qdev_prop_allow_set_link_before_realize, 1488 OBJ_PROP_LINK_STRONG); 1489 } 1490 1491 if (arm_feature(&cpu->env, ARM_FEATURE_EL2)) { 1492 qdev_property_add_static(DEVICE(obj), &arm_cpu_has_el2_property); 1493 } 1494 #endif 1495 1496 if (arm_feature(&cpu->env, ARM_FEATURE_PMU)) { 1497 cpu->has_pmu = true; 1498 object_property_add_bool(obj, "pmu", arm_get_pmu, arm_set_pmu); 1499 } 1500 1501 /* 1502 * Allow user to turn off VFP and Neon support, but only for TCG -- 1503 * KVM does not currently allow us to lie to the guest about its 1504 * ID/feature registers, so the guest always sees what the host has. 1505 */ 1506 if (arm_feature(&cpu->env, ARM_FEATURE_AARCH64)) { 1507 if (cpu_isar_feature(aa64_fp_simd, cpu)) { 1508 cpu->has_vfp = true; 1509 cpu->has_vfp_d32 = true; 1510 if (tcg_enabled() || qtest_enabled()) { 1511 qdev_property_add_static(DEVICE(obj), 1512 &arm_cpu_has_vfp_property); 1513 } 1514 } 1515 } else if (cpu_isar_feature(aa32_vfp, cpu)) { 1516 cpu->has_vfp = true; 1517 if (cpu_isar_feature(aa32_simd_r32, cpu)) { 1518 cpu->has_vfp_d32 = true; 1519 /* 1520 * The permitted values of the SIMDReg bits [3:0] on 1521 * Armv8-A are either 0b0000 and 0b0010. On such CPUs, 1522 * make sure that has_vfp_d32 can not be set to false. 1523 */ 1524 if ((tcg_enabled() || qtest_enabled()) 1525 && !(arm_feature(&cpu->env, ARM_FEATURE_V8) 1526 && !arm_feature(&cpu->env, ARM_FEATURE_M))) { 1527 qdev_property_add_static(DEVICE(obj), 1528 &arm_cpu_has_vfp_d32_property); 1529 } 1530 } 1531 } 1532 1533 if (arm_feature(&cpu->env, ARM_FEATURE_NEON)) { 1534 cpu->has_neon = true; 1535 if (!kvm_enabled()) { 1536 qdev_property_add_static(DEVICE(obj), &arm_cpu_has_neon_property); 1537 } 1538 } 1539 1540 if (arm_feature(&cpu->env, ARM_FEATURE_M) && 1541 arm_feature(&cpu->env, ARM_FEATURE_THUMB_DSP)) { 1542 qdev_property_add_static(DEVICE(obj), &arm_cpu_has_dsp_property); 1543 } 1544 1545 if (arm_feature(&cpu->env, ARM_FEATURE_PMSA)) { 1546 qdev_property_add_static(DEVICE(obj), &arm_cpu_has_mpu_property); 1547 if (arm_feature(&cpu->env, ARM_FEATURE_V7)) { 1548 qdev_property_add_static(DEVICE(obj), 1549 &arm_cpu_pmsav7_dregion_property); 1550 } 1551 } 1552 1553 if (arm_feature(&cpu->env, ARM_FEATURE_M_SECURITY)) { 1554 object_property_add_link(obj, "idau", TYPE_IDAU_INTERFACE, &cpu->idau, 1555 qdev_prop_allow_set_link_before_realize, 1556 OBJ_PROP_LINK_STRONG); 1557 /* 1558 * M profile: initial value of the Secure VTOR. We can't just use 1559 * a simple DEFINE_PROP_UINT32 for this because we want to permit 1560 * the property to be set after realize. 1561 */ 1562 object_property_add_uint32_ptr(obj, "init-svtor", 1563 &cpu->init_svtor, 1564 OBJ_PROP_FLAG_READWRITE); 1565 } 1566 if (arm_feature(&cpu->env, ARM_FEATURE_M)) { 1567 /* 1568 * Initial value of the NS VTOR (for cores without the Security 1569 * extension, this is the only VTOR) 1570 */ 1571 object_property_add_uint32_ptr(obj, "init-nsvtor", 1572 &cpu->init_nsvtor, 1573 OBJ_PROP_FLAG_READWRITE); 1574 } 1575 1576 /* Not DEFINE_PROP_UINT32: we want this to be settable after realize */ 1577 object_property_add_uint32_ptr(obj, "psci-conduit", 1578 &cpu->psci_conduit, 1579 OBJ_PROP_FLAG_READWRITE); 1580 1581 qdev_property_add_static(DEVICE(obj), &arm_cpu_cfgend_property); 1582 1583 if (arm_feature(&cpu->env, ARM_FEATURE_GENERIC_TIMER)) { 1584 qdev_property_add_static(DEVICE(cpu), &arm_cpu_gt_cntfrq_property); 1585 } 1586 1587 if (kvm_enabled()) { 1588 kvm_arm_add_vcpu_properties(obj); 1589 } 1590 1591 #ifndef CONFIG_USER_ONLY 1592 if (arm_feature(&cpu->env, ARM_FEATURE_AARCH64) && 1593 cpu_isar_feature(aa64_mte, cpu)) { 1594 object_property_add_link(obj, "tag-memory", 1595 TYPE_MEMORY_REGION, 1596 (Object **)&cpu->tag_memory, 1597 qdev_prop_allow_set_link_before_realize, 1598 OBJ_PROP_LINK_STRONG); 1599 1600 if (arm_feature(&cpu->env, ARM_FEATURE_EL3)) { 1601 object_property_add_link(obj, "secure-tag-memory", 1602 TYPE_MEMORY_REGION, 1603 (Object **)&cpu->secure_tag_memory, 1604 qdev_prop_allow_set_link_before_realize, 1605 OBJ_PROP_LINK_STRONG); 1606 } 1607 } 1608 #endif 1609 } 1610 1611 static void arm_cpu_finalizefn(Object *obj) 1612 { 1613 ARMCPU *cpu = ARM_CPU(obj); 1614 ARMELChangeHook *hook, *next; 1615 1616 g_hash_table_destroy(cpu->cp_regs); 1617 1618 QLIST_FOREACH_SAFE(hook, &cpu->pre_el_change_hooks, node, next) { 1619 QLIST_REMOVE(hook, node); 1620 g_free(hook); 1621 } 1622 QLIST_FOREACH_SAFE(hook, &cpu->el_change_hooks, node, next) { 1623 QLIST_REMOVE(hook, node); 1624 g_free(hook); 1625 } 1626 #ifndef CONFIG_USER_ONLY 1627 if (cpu->pmu_timer) { 1628 timer_free(cpu->pmu_timer); 1629 } 1630 #endif 1631 } 1632 1633 void arm_cpu_finalize_features(ARMCPU *cpu, Error **errp) 1634 { 1635 Error *local_err = NULL; 1636 1637 #ifdef TARGET_AARCH64 1638 if (arm_feature(&cpu->env, ARM_FEATURE_AARCH64)) { 1639 arm_cpu_sve_finalize(cpu, &local_err); 1640 if (local_err != NULL) { 1641 error_propagate(errp, local_err); 1642 return; 1643 } 1644 1645 arm_cpu_sme_finalize(cpu, &local_err); 1646 if (local_err != NULL) { 1647 error_propagate(errp, local_err); 1648 return; 1649 } 1650 1651 arm_cpu_pauth_finalize(cpu, &local_err); 1652 if (local_err != NULL) { 1653 error_propagate(errp, local_err); 1654 return; 1655 } 1656 1657 arm_cpu_lpa2_finalize(cpu, &local_err); 1658 if (local_err != NULL) { 1659 error_propagate(errp, local_err); 1660 return; 1661 } 1662 } 1663 #endif 1664 1665 if (kvm_enabled()) { 1666 kvm_arm_steal_time_finalize(cpu, &local_err); 1667 if (local_err != NULL) { 1668 error_propagate(errp, local_err); 1669 return; 1670 } 1671 } 1672 } 1673 1674 static void arm_cpu_realizefn(DeviceState *dev, Error **errp) 1675 { 1676 CPUState *cs = CPU(dev); 1677 ARMCPU *cpu = ARM_CPU(dev); 1678 ARMCPUClass *acc = ARM_CPU_GET_CLASS(dev); 1679 CPUARMState *env = &cpu->env; 1680 int pagebits; 1681 Error *local_err = NULL; 1682 1683 /* Use pc-relative instructions in system-mode */ 1684 #ifndef CONFIG_USER_ONLY 1685 cs->tcg_cflags |= CF_PCREL; 1686 #endif 1687 1688 /* If we needed to query the host kernel for the CPU features 1689 * then it's possible that might have failed in the initfn, but 1690 * this is the first point where we can report it. 1691 */ 1692 if (cpu->host_cpu_probe_failed) { 1693 if (!kvm_enabled() && !hvf_enabled()) { 1694 error_setg(errp, "The 'host' CPU type can only be used with KVM or HVF"); 1695 } else { 1696 error_setg(errp, "Failed to retrieve host CPU features"); 1697 } 1698 return; 1699 } 1700 1701 #ifndef CONFIG_USER_ONLY 1702 /* The NVIC and M-profile CPU are two halves of a single piece of 1703 * hardware; trying to use one without the other is a command line 1704 * error and will result in segfaults if not caught here. 1705 */ 1706 if (arm_feature(env, ARM_FEATURE_M)) { 1707 if (!env->nvic) { 1708 error_setg(errp, "This board cannot be used with Cortex-M CPUs"); 1709 return; 1710 } 1711 } else { 1712 if (env->nvic) { 1713 error_setg(errp, "This board can only be used with Cortex-M CPUs"); 1714 return; 1715 } 1716 } 1717 1718 if (!tcg_enabled() && !qtest_enabled()) { 1719 /* 1720 * We assume that no accelerator except TCG (and the "not really an 1721 * accelerator" qtest) can handle these features, because Arm hardware 1722 * virtualization can't virtualize them. 1723 * 1724 * Catch all the cases which might cause us to create more than one 1725 * address space for the CPU (otherwise we will assert() later in 1726 * cpu_address_space_init()). 1727 */ 1728 if (arm_feature(env, ARM_FEATURE_M)) { 1729 error_setg(errp, 1730 "Cannot enable %s when using an M-profile guest CPU", 1731 current_accel_name()); 1732 return; 1733 } 1734 if (cpu->has_el3) { 1735 error_setg(errp, 1736 "Cannot enable %s when guest CPU has EL3 enabled", 1737 current_accel_name()); 1738 return; 1739 } 1740 if (cpu->tag_memory) { 1741 error_setg(errp, 1742 "Cannot enable %s when guest CPUs has MTE enabled", 1743 current_accel_name()); 1744 return; 1745 } 1746 } 1747 1748 { 1749 uint64_t scale; 1750 1751 if (arm_feature(env, ARM_FEATURE_GENERIC_TIMER)) { 1752 if (!cpu->gt_cntfrq_hz) { 1753 error_setg(errp, "Invalid CNTFRQ: %"PRId64"Hz", 1754 cpu->gt_cntfrq_hz); 1755 return; 1756 } 1757 scale = gt_cntfrq_period_ns(cpu); 1758 } else { 1759 scale = GTIMER_SCALE; 1760 } 1761 1762 cpu->gt_timer[GTIMER_PHYS] = timer_new(QEMU_CLOCK_VIRTUAL, scale, 1763 arm_gt_ptimer_cb, cpu); 1764 cpu->gt_timer[GTIMER_VIRT] = timer_new(QEMU_CLOCK_VIRTUAL, scale, 1765 arm_gt_vtimer_cb, cpu); 1766 cpu->gt_timer[GTIMER_HYP] = timer_new(QEMU_CLOCK_VIRTUAL, scale, 1767 arm_gt_htimer_cb, cpu); 1768 cpu->gt_timer[GTIMER_SEC] = timer_new(QEMU_CLOCK_VIRTUAL, scale, 1769 arm_gt_stimer_cb, cpu); 1770 cpu->gt_timer[GTIMER_HYPVIRT] = timer_new(QEMU_CLOCK_VIRTUAL, scale, 1771 arm_gt_hvtimer_cb, cpu); 1772 } 1773 #endif 1774 1775 cpu_exec_realizefn(cs, &local_err); 1776 if (local_err != NULL) { 1777 error_propagate(errp, local_err); 1778 return; 1779 } 1780 1781 arm_cpu_finalize_features(cpu, &local_err); 1782 if (local_err != NULL) { 1783 error_propagate(errp, local_err); 1784 return; 1785 } 1786 1787 #ifdef CONFIG_USER_ONLY 1788 /* 1789 * User mode relies on IC IVAU instructions to catch modification of 1790 * dual-mapped code. 1791 * 1792 * Clear CTR_EL0.DIC to ensure that software that honors these flags uses 1793 * IC IVAU even if the emulated processor does not normally require it. 1794 */ 1795 cpu->ctr = FIELD_DP64(cpu->ctr, CTR_EL0, DIC, 0); 1796 #endif 1797 1798 if (arm_feature(env, ARM_FEATURE_AARCH64) && 1799 cpu->has_vfp != cpu->has_neon) { 1800 /* 1801 * This is an architectural requirement for AArch64; AArch32 is 1802 * more flexible and permits VFP-no-Neon and Neon-no-VFP. 1803 */ 1804 error_setg(errp, 1805 "AArch64 CPUs must have both VFP and Neon or neither"); 1806 return; 1807 } 1808 1809 if (cpu->has_vfp_d32 != cpu->has_neon) { 1810 error_setg(errp, "ARM CPUs must have both VFP-D32 and Neon or neither"); 1811 return; 1812 } 1813 1814 if (!cpu->has_vfp_d32) { 1815 uint32_t u; 1816 1817 u = cpu->isar.mvfr0; 1818 u = FIELD_DP32(u, MVFR0, SIMDREG, 1); /* 16 registers */ 1819 cpu->isar.mvfr0 = u; 1820 } 1821 1822 if (!cpu->has_vfp) { 1823 uint64_t t; 1824 uint32_t u; 1825 1826 t = cpu->isar.id_aa64isar1; 1827 t = FIELD_DP64(t, ID_AA64ISAR1, JSCVT, 0); 1828 cpu->isar.id_aa64isar1 = t; 1829 1830 t = cpu->isar.id_aa64pfr0; 1831 t = FIELD_DP64(t, ID_AA64PFR0, FP, 0xf); 1832 cpu->isar.id_aa64pfr0 = t; 1833 1834 u = cpu->isar.id_isar6; 1835 u = FIELD_DP32(u, ID_ISAR6, JSCVT, 0); 1836 u = FIELD_DP32(u, ID_ISAR6, BF16, 0); 1837 cpu->isar.id_isar6 = u; 1838 1839 u = cpu->isar.mvfr0; 1840 u = FIELD_DP32(u, MVFR0, FPSP, 0); 1841 u = FIELD_DP32(u, MVFR0, FPDP, 0); 1842 u = FIELD_DP32(u, MVFR0, FPDIVIDE, 0); 1843 u = FIELD_DP32(u, MVFR0, FPSQRT, 0); 1844 u = FIELD_DP32(u, MVFR0, FPROUND, 0); 1845 if (!arm_feature(env, ARM_FEATURE_M)) { 1846 u = FIELD_DP32(u, MVFR0, FPTRAP, 0); 1847 u = FIELD_DP32(u, MVFR0, FPSHVEC, 0); 1848 } 1849 cpu->isar.mvfr0 = u; 1850 1851 u = cpu->isar.mvfr1; 1852 u = FIELD_DP32(u, MVFR1, FPFTZ, 0); 1853 u = FIELD_DP32(u, MVFR1, FPDNAN, 0); 1854 u = FIELD_DP32(u, MVFR1, FPHP, 0); 1855 if (arm_feature(env, ARM_FEATURE_M)) { 1856 u = FIELD_DP32(u, MVFR1, FP16, 0); 1857 } 1858 cpu->isar.mvfr1 = u; 1859 1860 u = cpu->isar.mvfr2; 1861 u = FIELD_DP32(u, MVFR2, FPMISC, 0); 1862 cpu->isar.mvfr2 = u; 1863 } 1864 1865 if (!cpu->has_neon) { 1866 uint64_t t; 1867 uint32_t u; 1868 1869 unset_feature(env, ARM_FEATURE_NEON); 1870 1871 t = cpu->isar.id_aa64isar0; 1872 t = FIELD_DP64(t, ID_AA64ISAR0, AES, 0); 1873 t = FIELD_DP64(t, ID_AA64ISAR0, SHA1, 0); 1874 t = FIELD_DP64(t, ID_AA64ISAR0, SHA2, 0); 1875 t = FIELD_DP64(t, ID_AA64ISAR0, SHA3, 0); 1876 t = FIELD_DP64(t, ID_AA64ISAR0, SM3, 0); 1877 t = FIELD_DP64(t, ID_AA64ISAR0, SM4, 0); 1878 t = FIELD_DP64(t, ID_AA64ISAR0, DP, 0); 1879 cpu->isar.id_aa64isar0 = t; 1880 1881 t = cpu->isar.id_aa64isar1; 1882 t = FIELD_DP64(t, ID_AA64ISAR1, FCMA, 0); 1883 t = FIELD_DP64(t, ID_AA64ISAR1, BF16, 0); 1884 t = FIELD_DP64(t, ID_AA64ISAR1, I8MM, 0); 1885 cpu->isar.id_aa64isar1 = t; 1886 1887 t = cpu->isar.id_aa64pfr0; 1888 t = FIELD_DP64(t, ID_AA64PFR0, ADVSIMD, 0xf); 1889 cpu->isar.id_aa64pfr0 = t; 1890 1891 u = cpu->isar.id_isar5; 1892 u = FIELD_DP32(u, ID_ISAR5, AES, 0); 1893 u = FIELD_DP32(u, ID_ISAR5, SHA1, 0); 1894 u = FIELD_DP32(u, ID_ISAR5, SHA2, 0); 1895 u = FIELD_DP32(u, ID_ISAR5, RDM, 0); 1896 u = FIELD_DP32(u, ID_ISAR5, VCMA, 0); 1897 cpu->isar.id_isar5 = u; 1898 1899 u = cpu->isar.id_isar6; 1900 u = FIELD_DP32(u, ID_ISAR6, DP, 0); 1901 u = FIELD_DP32(u, ID_ISAR6, FHM, 0); 1902 u = FIELD_DP32(u, ID_ISAR6, BF16, 0); 1903 u = FIELD_DP32(u, ID_ISAR6, I8MM, 0); 1904 cpu->isar.id_isar6 = u; 1905 1906 if (!arm_feature(env, ARM_FEATURE_M)) { 1907 u = cpu->isar.mvfr1; 1908 u = FIELD_DP32(u, MVFR1, SIMDLS, 0); 1909 u = FIELD_DP32(u, MVFR1, SIMDINT, 0); 1910 u = FIELD_DP32(u, MVFR1, SIMDSP, 0); 1911 u = FIELD_DP32(u, MVFR1, SIMDHP, 0); 1912 cpu->isar.mvfr1 = u; 1913 1914 u = cpu->isar.mvfr2; 1915 u = FIELD_DP32(u, MVFR2, SIMDMISC, 0); 1916 cpu->isar.mvfr2 = u; 1917 } 1918 } 1919 1920 if (!cpu->has_neon && !cpu->has_vfp) { 1921 uint64_t t; 1922 uint32_t u; 1923 1924 t = cpu->isar.id_aa64isar0; 1925 t = FIELD_DP64(t, ID_AA64ISAR0, FHM, 0); 1926 cpu->isar.id_aa64isar0 = t; 1927 1928 t = cpu->isar.id_aa64isar1; 1929 t = FIELD_DP64(t, ID_AA64ISAR1, FRINTTS, 0); 1930 cpu->isar.id_aa64isar1 = t; 1931 1932 u = cpu->isar.mvfr0; 1933 u = FIELD_DP32(u, MVFR0, SIMDREG, 0); 1934 cpu->isar.mvfr0 = u; 1935 1936 /* Despite the name, this field covers both VFP and Neon */ 1937 u = cpu->isar.mvfr1; 1938 u = FIELD_DP32(u, MVFR1, SIMDFMAC, 0); 1939 cpu->isar.mvfr1 = u; 1940 } 1941 1942 if (arm_feature(env, ARM_FEATURE_M) && !cpu->has_dsp) { 1943 uint32_t u; 1944 1945 unset_feature(env, ARM_FEATURE_THUMB_DSP); 1946 1947 u = cpu->isar.id_isar1; 1948 u = FIELD_DP32(u, ID_ISAR1, EXTEND, 1); 1949 cpu->isar.id_isar1 = u; 1950 1951 u = cpu->isar.id_isar2; 1952 u = FIELD_DP32(u, ID_ISAR2, MULTU, 1); 1953 u = FIELD_DP32(u, ID_ISAR2, MULTS, 1); 1954 cpu->isar.id_isar2 = u; 1955 1956 u = cpu->isar.id_isar3; 1957 u = FIELD_DP32(u, ID_ISAR3, SIMD, 1); 1958 u = FIELD_DP32(u, ID_ISAR3, SATURATE, 0); 1959 cpu->isar.id_isar3 = u; 1960 } 1961 1962 1963 /* 1964 * We rely on no XScale CPU having VFP so we can use the same bits in the 1965 * TB flags field for VECSTRIDE and XSCALE_CPAR. 1966 */ 1967 assert(arm_feature(&cpu->env, ARM_FEATURE_AARCH64) || 1968 !cpu_isar_feature(aa32_vfp_simd, cpu) || 1969 !arm_feature(env, ARM_FEATURE_XSCALE)); 1970 1971 if (arm_feature(env, ARM_FEATURE_V7) && 1972 !arm_feature(env, ARM_FEATURE_M) && 1973 !arm_feature(env, ARM_FEATURE_PMSA)) { 1974 /* v7VMSA drops support for the old ARMv5 tiny pages, so we 1975 * can use 4K pages. 1976 */ 1977 pagebits = 12; 1978 } else { 1979 /* For CPUs which might have tiny 1K pages, or which have an 1980 * MPU and might have small region sizes, stick with 1K pages. 1981 */ 1982 pagebits = 10; 1983 } 1984 if (!set_preferred_target_page_bits(pagebits)) { 1985 /* This can only ever happen for hotplugging a CPU, or if 1986 * the board code incorrectly creates a CPU which it has 1987 * promised via minimum_page_size that it will not. 1988 */ 1989 error_setg(errp, "This CPU requires a smaller page size than the " 1990 "system is using"); 1991 return; 1992 } 1993 1994 /* This cpu-id-to-MPIDR affinity is used only for TCG; KVM will override it. 1995 * We don't support setting cluster ID ([16..23]) (known as Aff2 1996 * in later ARM ARM versions), or any of the higher affinity level fields, 1997 * so these bits always RAZ. 1998 */ 1999 if (cpu->mp_affinity == ARM64_AFFINITY_INVALID) { 2000 cpu->mp_affinity = arm_cpu_mp_affinity(cs->cpu_index, 2001 ARM_DEFAULT_CPUS_PER_CLUSTER); 2002 } 2003 2004 if (cpu->reset_hivecs) { 2005 cpu->reset_sctlr |= (1 << 13); 2006 } 2007 2008 if (cpu->cfgend) { 2009 if (arm_feature(&cpu->env, ARM_FEATURE_V7)) { 2010 cpu->reset_sctlr |= SCTLR_EE; 2011 } else { 2012 cpu->reset_sctlr |= SCTLR_B; 2013 } 2014 } 2015 2016 if (!arm_feature(env, ARM_FEATURE_M) && !cpu->has_el3) { 2017 /* If the has_el3 CPU property is disabled then we need to disable the 2018 * feature. 2019 */ 2020 unset_feature(env, ARM_FEATURE_EL3); 2021 2022 /* 2023 * Disable the security extension feature bits in the processor 2024 * feature registers as well. 2025 */ 2026 cpu->isar.id_pfr1 = FIELD_DP32(cpu->isar.id_pfr1, ID_PFR1, SECURITY, 0); 2027 cpu->isar.id_dfr0 = FIELD_DP32(cpu->isar.id_dfr0, ID_DFR0, COPSDBG, 0); 2028 cpu->isar.id_aa64pfr0 = FIELD_DP64(cpu->isar.id_aa64pfr0, 2029 ID_AA64PFR0, EL3, 0); 2030 2031 /* Disable the realm management extension, which requires EL3. */ 2032 cpu->isar.id_aa64pfr0 = FIELD_DP64(cpu->isar.id_aa64pfr0, 2033 ID_AA64PFR0, RME, 0); 2034 } 2035 2036 if (!cpu->has_el2) { 2037 unset_feature(env, ARM_FEATURE_EL2); 2038 } 2039 2040 if (!cpu->has_pmu) { 2041 unset_feature(env, ARM_FEATURE_PMU); 2042 } 2043 if (arm_feature(env, ARM_FEATURE_PMU)) { 2044 pmu_init(cpu); 2045 2046 if (!kvm_enabled()) { 2047 arm_register_pre_el_change_hook(cpu, &pmu_pre_el_change, 0); 2048 arm_register_el_change_hook(cpu, &pmu_post_el_change, 0); 2049 } 2050 2051 #ifndef CONFIG_USER_ONLY 2052 cpu->pmu_timer = timer_new_ns(QEMU_CLOCK_VIRTUAL, arm_pmu_timer_cb, 2053 cpu); 2054 #endif 2055 } else { 2056 cpu->isar.id_aa64dfr0 = 2057 FIELD_DP64(cpu->isar.id_aa64dfr0, ID_AA64DFR0, PMUVER, 0); 2058 cpu->isar.id_dfr0 = FIELD_DP32(cpu->isar.id_dfr0, ID_DFR0, PERFMON, 0); 2059 cpu->pmceid0 = 0; 2060 cpu->pmceid1 = 0; 2061 } 2062 2063 if (!arm_feature(env, ARM_FEATURE_EL2)) { 2064 /* 2065 * Disable the hypervisor feature bits in the processor feature 2066 * registers if we don't have EL2. 2067 */ 2068 cpu->isar.id_aa64pfr0 = FIELD_DP64(cpu->isar.id_aa64pfr0, 2069 ID_AA64PFR0, EL2, 0); 2070 cpu->isar.id_pfr1 = FIELD_DP32(cpu->isar.id_pfr1, 2071 ID_PFR1, VIRTUALIZATION, 0); 2072 } 2073 2074 if (cpu_isar_feature(aa64_mte, cpu)) { 2075 /* 2076 * The architectural range of GM blocksize is 2-6, however qemu 2077 * doesn't support blocksize of 2 (see HELPER(ldgm)). 2078 */ 2079 if (tcg_enabled()) { 2080 assert(cpu->gm_blocksize >= 3 && cpu->gm_blocksize <= 6); 2081 } 2082 2083 #ifndef CONFIG_USER_ONLY 2084 /* 2085 * If we do not have tag-memory provided by the machine, 2086 * reduce MTE support to instructions enabled at EL0. 2087 * This matches Cortex-A710 BROADCASTMTE input being LOW. 2088 */ 2089 if (cpu->tag_memory == NULL) { 2090 cpu->isar.id_aa64pfr1 = 2091 FIELD_DP64(cpu->isar.id_aa64pfr1, ID_AA64PFR1, MTE, 1); 2092 } 2093 #endif 2094 } 2095 2096 if (tcg_enabled()) { 2097 /* 2098 * Don't report some architectural features in the ID registers 2099 * where TCG does not yet implement it (not even a minimal 2100 * stub version). This avoids guests falling over when they 2101 * try to access the non-existent system registers for them. 2102 */ 2103 /* FEAT_SPE (Statistical Profiling Extension) */ 2104 cpu->isar.id_aa64dfr0 = 2105 FIELD_DP64(cpu->isar.id_aa64dfr0, ID_AA64DFR0, PMSVER, 0); 2106 /* FEAT_TRBE (Trace Buffer Extension) */ 2107 cpu->isar.id_aa64dfr0 = 2108 FIELD_DP64(cpu->isar.id_aa64dfr0, ID_AA64DFR0, TRACEBUFFER, 0); 2109 /* FEAT_TRF (Self-hosted Trace Extension) */ 2110 cpu->isar.id_aa64dfr0 = 2111 FIELD_DP64(cpu->isar.id_aa64dfr0, ID_AA64DFR0, TRACEFILT, 0); 2112 cpu->isar.id_dfr0 = 2113 FIELD_DP32(cpu->isar.id_dfr0, ID_DFR0, TRACEFILT, 0); 2114 /* Trace Macrocell system register access */ 2115 cpu->isar.id_aa64dfr0 = 2116 FIELD_DP64(cpu->isar.id_aa64dfr0, ID_AA64DFR0, TRACEVER, 0); 2117 cpu->isar.id_dfr0 = 2118 FIELD_DP32(cpu->isar.id_dfr0, ID_DFR0, COPTRC, 0); 2119 /* Memory mapped trace */ 2120 cpu->isar.id_dfr0 = 2121 FIELD_DP32(cpu->isar.id_dfr0, ID_DFR0, MMAPTRC, 0); 2122 /* FEAT_AMU (Activity Monitors Extension) */ 2123 cpu->isar.id_aa64pfr0 = 2124 FIELD_DP64(cpu->isar.id_aa64pfr0, ID_AA64PFR0, AMU, 0); 2125 cpu->isar.id_pfr0 = 2126 FIELD_DP32(cpu->isar.id_pfr0, ID_PFR0, AMU, 0); 2127 /* FEAT_MPAM (Memory Partitioning and Monitoring Extension) */ 2128 cpu->isar.id_aa64pfr0 = 2129 FIELD_DP64(cpu->isar.id_aa64pfr0, ID_AA64PFR0, MPAM, 0); 2130 /* FEAT_NV (Nested Virtualization) */ 2131 cpu->isar.id_aa64mmfr2 = 2132 FIELD_DP64(cpu->isar.id_aa64mmfr2, ID_AA64MMFR2, NV, 0); 2133 } 2134 2135 /* MPU can be configured out of a PMSA CPU either by setting has-mpu 2136 * to false or by setting pmsav7-dregion to 0. 2137 */ 2138 if (!cpu->has_mpu || cpu->pmsav7_dregion == 0) { 2139 cpu->has_mpu = false; 2140 cpu->pmsav7_dregion = 0; 2141 cpu->pmsav8r_hdregion = 0; 2142 } 2143 2144 if (arm_feature(env, ARM_FEATURE_PMSA) && 2145 arm_feature(env, ARM_FEATURE_V7)) { 2146 uint32_t nr = cpu->pmsav7_dregion; 2147 2148 if (nr > 0xff) { 2149 error_setg(errp, "PMSAv7 MPU #regions invalid %" PRIu32, nr); 2150 return; 2151 } 2152 2153 if (nr) { 2154 if (arm_feature(env, ARM_FEATURE_V8)) { 2155 /* PMSAv8 */ 2156 env->pmsav8.rbar[M_REG_NS] = g_new0(uint32_t, nr); 2157 env->pmsav8.rlar[M_REG_NS] = g_new0(uint32_t, nr); 2158 if (arm_feature(env, ARM_FEATURE_M_SECURITY)) { 2159 env->pmsav8.rbar[M_REG_S] = g_new0(uint32_t, nr); 2160 env->pmsav8.rlar[M_REG_S] = g_new0(uint32_t, nr); 2161 } 2162 } else { 2163 env->pmsav7.drbar = g_new0(uint32_t, nr); 2164 env->pmsav7.drsr = g_new0(uint32_t, nr); 2165 env->pmsav7.dracr = g_new0(uint32_t, nr); 2166 } 2167 } 2168 2169 if (cpu->pmsav8r_hdregion > 0xff) { 2170 error_setg(errp, "PMSAv8 MPU EL2 #regions invalid %" PRIu32, 2171 cpu->pmsav8r_hdregion); 2172 return; 2173 } 2174 2175 if (cpu->pmsav8r_hdregion) { 2176 env->pmsav8.hprbar = g_new0(uint32_t, 2177 cpu->pmsav8r_hdregion); 2178 env->pmsav8.hprlar = g_new0(uint32_t, 2179 cpu->pmsav8r_hdregion); 2180 } 2181 } 2182 2183 if (arm_feature(env, ARM_FEATURE_M_SECURITY)) { 2184 uint32_t nr = cpu->sau_sregion; 2185 2186 if (nr > 0xff) { 2187 error_setg(errp, "v8M SAU #regions invalid %" PRIu32, nr); 2188 return; 2189 } 2190 2191 if (nr) { 2192 env->sau.rbar = g_new0(uint32_t, nr); 2193 env->sau.rlar = g_new0(uint32_t, nr); 2194 } 2195 } 2196 2197 if (arm_feature(env, ARM_FEATURE_EL3)) { 2198 set_feature(env, ARM_FEATURE_VBAR); 2199 } 2200 2201 #ifndef CONFIG_USER_ONLY 2202 if (tcg_enabled() && cpu_isar_feature(aa64_rme, cpu)) { 2203 arm_register_el_change_hook(cpu, >_rme_post_el_change, 0); 2204 } 2205 #endif 2206 2207 register_cp_regs_for_features(cpu); 2208 arm_cpu_register_gdb_regs_for_features(cpu); 2209 2210 init_cpreg_list(cpu); 2211 2212 #ifndef CONFIG_USER_ONLY 2213 MachineState *ms = MACHINE(qdev_get_machine()); 2214 unsigned int smp_cpus = ms->smp.cpus; 2215 bool has_secure = cpu->has_el3 || arm_feature(env, ARM_FEATURE_M_SECURITY); 2216 2217 /* 2218 * We must set cs->num_ases to the final value before 2219 * the first call to cpu_address_space_init. 2220 */ 2221 if (cpu->tag_memory != NULL) { 2222 cs->num_ases = 3 + has_secure; 2223 } else { 2224 cs->num_ases = 1 + has_secure; 2225 } 2226 2227 if (has_secure) { 2228 if (!cpu->secure_memory) { 2229 cpu->secure_memory = cs->memory; 2230 } 2231 cpu_address_space_init(cs, ARMASIdx_S, "cpu-secure-memory", 2232 cpu->secure_memory); 2233 } 2234 2235 if (cpu->tag_memory != NULL) { 2236 cpu_address_space_init(cs, ARMASIdx_TagNS, "cpu-tag-memory", 2237 cpu->tag_memory); 2238 if (has_secure) { 2239 cpu_address_space_init(cs, ARMASIdx_TagS, "cpu-tag-memory", 2240 cpu->secure_tag_memory); 2241 } 2242 } 2243 2244 cpu_address_space_init(cs, ARMASIdx_NS, "cpu-memory", cs->memory); 2245 2246 /* No core_count specified, default to smp_cpus. */ 2247 if (cpu->core_count == -1) { 2248 cpu->core_count = smp_cpus; 2249 } 2250 #endif 2251 2252 if (tcg_enabled()) { 2253 int dcz_blocklen = 4 << cpu->dcz_blocksize; 2254 2255 /* 2256 * We only support DCZ blocklen that fits on one page. 2257 * 2258 * Architectually this is always true. However TARGET_PAGE_SIZE 2259 * is variable and, for compatibility with -machine virt-2.7, 2260 * is only 1KiB, as an artifact of legacy ARMv5 subpage support. 2261 * But even then, while the largest architectural DCZ blocklen 2262 * is 2KiB, no cpu actually uses such a large blocklen. 2263 */ 2264 assert(dcz_blocklen <= TARGET_PAGE_SIZE); 2265 2266 /* 2267 * We only support DCZ blocksize >= 2*TAG_GRANULE, which is to say 2268 * both nibbles of each byte storing tag data may be written at once. 2269 * Since TAG_GRANULE is 16, this means that blocklen must be >= 32. 2270 */ 2271 if (cpu_isar_feature(aa64_mte, cpu)) { 2272 assert(dcz_blocklen >= 2 * TAG_GRANULE); 2273 } 2274 } 2275 2276 qemu_init_vcpu(cs); 2277 cpu_reset(cs); 2278 2279 acc->parent_realize(dev, errp); 2280 } 2281 2282 static ObjectClass *arm_cpu_class_by_name(const char *cpu_model) 2283 { 2284 ObjectClass *oc; 2285 char *typename; 2286 char **cpuname; 2287 const char *cpunamestr; 2288 2289 cpuname = g_strsplit(cpu_model, ",", 1); 2290 cpunamestr = cpuname[0]; 2291 #ifdef CONFIG_USER_ONLY 2292 /* For backwards compatibility usermode emulation allows "-cpu any", 2293 * which has the same semantics as "-cpu max". 2294 */ 2295 if (!strcmp(cpunamestr, "any")) { 2296 cpunamestr = "max"; 2297 } 2298 #endif 2299 typename = g_strdup_printf(ARM_CPU_TYPE_NAME("%s"), cpunamestr); 2300 oc = object_class_by_name(typename); 2301 g_strfreev(cpuname); 2302 g_free(typename); 2303 if (!oc || !object_class_dynamic_cast(oc, TYPE_ARM_CPU) || 2304 object_class_is_abstract(oc)) { 2305 return NULL; 2306 } 2307 return oc; 2308 } 2309 2310 static Property arm_cpu_properties[] = { 2311 DEFINE_PROP_UINT64("midr", ARMCPU, midr, 0), 2312 DEFINE_PROP_UINT64("mp-affinity", ARMCPU, 2313 mp_affinity, ARM64_AFFINITY_INVALID), 2314 DEFINE_PROP_INT32("node-id", ARMCPU, node_id, CPU_UNSET_NUMA_NODE_ID), 2315 DEFINE_PROP_INT32("core-count", ARMCPU, core_count, -1), 2316 DEFINE_PROP_END_OF_LIST() 2317 }; 2318 2319 static gchar *arm_gdb_arch_name(CPUState *cs) 2320 { 2321 ARMCPU *cpu = ARM_CPU(cs); 2322 CPUARMState *env = &cpu->env; 2323 2324 if (arm_feature(env, ARM_FEATURE_IWMMXT)) { 2325 return g_strdup("iwmmxt"); 2326 } 2327 return g_strdup("arm"); 2328 } 2329 2330 #ifndef CONFIG_USER_ONLY 2331 #include "hw/core/sysemu-cpu-ops.h" 2332 2333 static const struct SysemuCPUOps arm_sysemu_ops = { 2334 .get_phys_page_attrs_debug = arm_cpu_get_phys_page_attrs_debug, 2335 .asidx_from_attrs = arm_asidx_from_attrs, 2336 .write_elf32_note = arm_cpu_write_elf32_note, 2337 .write_elf64_note = arm_cpu_write_elf64_note, 2338 .virtio_is_big_endian = arm_cpu_virtio_is_big_endian, 2339 .legacy_vmsd = &vmstate_arm_cpu, 2340 }; 2341 #endif 2342 2343 #ifdef CONFIG_TCG 2344 static const struct TCGCPUOps arm_tcg_ops = { 2345 .initialize = arm_translate_init, 2346 .synchronize_from_tb = arm_cpu_synchronize_from_tb, 2347 .debug_excp_handler = arm_debug_excp_handler, 2348 .restore_state_to_opc = arm_restore_state_to_opc, 2349 2350 #ifdef CONFIG_USER_ONLY 2351 .record_sigsegv = arm_cpu_record_sigsegv, 2352 .record_sigbus = arm_cpu_record_sigbus, 2353 #else 2354 .tlb_fill = arm_cpu_tlb_fill, 2355 .cpu_exec_interrupt = arm_cpu_exec_interrupt, 2356 .do_interrupt = arm_cpu_do_interrupt, 2357 .do_transaction_failed = arm_cpu_do_transaction_failed, 2358 .do_unaligned_access = arm_cpu_do_unaligned_access, 2359 .adjust_watchpoint_address = arm_adjust_watchpoint_address, 2360 .debug_check_watchpoint = arm_debug_check_watchpoint, 2361 .debug_check_breakpoint = arm_debug_check_breakpoint, 2362 #endif /* !CONFIG_USER_ONLY */ 2363 }; 2364 #endif /* CONFIG_TCG */ 2365 2366 static void arm_cpu_class_init(ObjectClass *oc, void *data) 2367 { 2368 ARMCPUClass *acc = ARM_CPU_CLASS(oc); 2369 CPUClass *cc = CPU_CLASS(acc); 2370 DeviceClass *dc = DEVICE_CLASS(oc); 2371 ResettableClass *rc = RESETTABLE_CLASS(oc); 2372 2373 device_class_set_parent_realize(dc, arm_cpu_realizefn, 2374 &acc->parent_realize); 2375 2376 device_class_set_props(dc, arm_cpu_properties); 2377 2378 resettable_class_set_parent_phases(rc, NULL, arm_cpu_reset_hold, NULL, 2379 &acc->parent_phases); 2380 2381 cc->class_by_name = arm_cpu_class_by_name; 2382 cc->has_work = arm_cpu_has_work; 2383 cc->dump_state = arm_cpu_dump_state; 2384 cc->set_pc = arm_cpu_set_pc; 2385 cc->get_pc = arm_cpu_get_pc; 2386 cc->gdb_read_register = arm_cpu_gdb_read_register; 2387 cc->gdb_write_register = arm_cpu_gdb_write_register; 2388 #ifndef CONFIG_USER_ONLY 2389 cc->sysemu_ops = &arm_sysemu_ops; 2390 #endif 2391 cc->gdb_num_core_regs = 26; 2392 cc->gdb_core_xml_file = "arm-core.xml"; 2393 cc->gdb_arch_name = arm_gdb_arch_name; 2394 cc->gdb_get_dynamic_xml = arm_gdb_get_dynamic_xml; 2395 cc->gdb_stop_before_watchpoint = true; 2396 cc->disas_set_info = arm_disas_set_info; 2397 2398 #ifdef CONFIG_TCG 2399 cc->tcg_ops = &arm_tcg_ops; 2400 #endif /* CONFIG_TCG */ 2401 } 2402 2403 static void arm_cpu_instance_init(Object *obj) 2404 { 2405 ARMCPUClass *acc = ARM_CPU_GET_CLASS(obj); 2406 2407 acc->info->initfn(obj); 2408 arm_cpu_post_init(obj); 2409 } 2410 2411 static void cpu_register_class_init(ObjectClass *oc, void *data) 2412 { 2413 ARMCPUClass *acc = ARM_CPU_CLASS(oc); 2414 2415 acc->info = data; 2416 } 2417 2418 void arm_cpu_register(const ARMCPUInfo *info) 2419 { 2420 TypeInfo type_info = { 2421 .parent = TYPE_ARM_CPU, 2422 .instance_size = sizeof(ARMCPU), 2423 .instance_align = __alignof__(ARMCPU), 2424 .instance_init = arm_cpu_instance_init, 2425 .class_size = sizeof(ARMCPUClass), 2426 .class_init = info->class_init ?: cpu_register_class_init, 2427 .class_data = (void *)info, 2428 }; 2429 2430 type_info.name = g_strdup_printf("%s-" TYPE_ARM_CPU, info->name); 2431 type_register(&type_info); 2432 g_free((void *)type_info.name); 2433 } 2434 2435 static const TypeInfo arm_cpu_type_info = { 2436 .name = TYPE_ARM_CPU, 2437 .parent = TYPE_CPU, 2438 .instance_size = sizeof(ARMCPU), 2439 .instance_align = __alignof__(ARMCPU), 2440 .instance_init = arm_cpu_initfn, 2441 .instance_finalize = arm_cpu_finalizefn, 2442 .abstract = true, 2443 .class_size = sizeof(ARMCPUClass), 2444 .class_init = arm_cpu_class_init, 2445 }; 2446 2447 static void arm_cpu_register_types(void) 2448 { 2449 type_register_static(&arm_cpu_type_info); 2450 } 2451 2452 type_init(arm_cpu_register_types) 2453