1 /* 2 * QEMU ARM CPU 3 * 4 * Copyright (c) 2012 SUSE LINUX Products GmbH 5 * 6 * This program is free software; you can redistribute it and/or 7 * modify it under the terms of the GNU General Public License 8 * as published by the Free Software Foundation; either version 2 9 * of the License, or (at your option) any later version. 10 * 11 * This program is distributed in the hope that it will be useful, 12 * but WITHOUT ANY WARRANTY; without even the implied warranty of 13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 14 * GNU General Public License for more details. 15 * 16 * You should have received a copy of the GNU General Public License 17 * along with this program; if not, see 18 * <http://www.gnu.org/licenses/gpl-2.0.html> 19 */ 20 21 #include "qemu/osdep.h" 22 #include "qemu/error-report.h" 23 #include "qapi/error.h" 24 #include "cpu.h" 25 #include "internals.h" 26 #include "qemu-common.h" 27 #include "exec/exec-all.h" 28 #include "hw/qdev-properties.h" 29 #if !defined(CONFIG_USER_ONLY) 30 #include "hw/loader.h" 31 #endif 32 #include "hw/arm/arm.h" 33 #include "sysemu/sysemu.h" 34 #include "sysemu/hw_accel.h" 35 #include "kvm_arm.h" 36 #include "disas/capstone.h" 37 38 static void arm_cpu_set_pc(CPUState *cs, vaddr value) 39 { 40 ARMCPU *cpu = ARM_CPU(cs); 41 42 cpu->env.regs[15] = value; 43 } 44 45 static bool arm_cpu_has_work(CPUState *cs) 46 { 47 ARMCPU *cpu = ARM_CPU(cs); 48 49 return (cpu->power_state != PSCI_OFF) 50 && cs->interrupt_request & 51 (CPU_INTERRUPT_FIQ | CPU_INTERRUPT_HARD 52 | CPU_INTERRUPT_VFIQ | CPU_INTERRUPT_VIRQ 53 | CPU_INTERRUPT_EXITTB); 54 } 55 56 void arm_register_el_change_hook(ARMCPU *cpu, ARMELChangeHook *hook, 57 void *opaque) 58 { 59 /* We currently only support registering a single hook function */ 60 assert(!cpu->el_change_hook); 61 cpu->el_change_hook = hook; 62 cpu->el_change_hook_opaque = opaque; 63 } 64 65 static void cp_reg_reset(gpointer key, gpointer value, gpointer opaque) 66 { 67 /* Reset a single ARMCPRegInfo register */ 68 ARMCPRegInfo *ri = value; 69 ARMCPU *cpu = opaque; 70 71 if (ri->type & (ARM_CP_SPECIAL | ARM_CP_ALIAS)) { 72 return; 73 } 74 75 if (ri->resetfn) { 76 ri->resetfn(&cpu->env, ri); 77 return; 78 } 79 80 /* A zero offset is never possible as it would be regs[0] 81 * so we use it to indicate that reset is being handled elsewhere. 82 * This is basically only used for fields in non-core coprocessors 83 * (like the pxa2xx ones). 84 */ 85 if (!ri->fieldoffset) { 86 return; 87 } 88 89 if (cpreg_field_is_64bit(ri)) { 90 CPREG_FIELD64(&cpu->env, ri) = ri->resetvalue; 91 } else { 92 CPREG_FIELD32(&cpu->env, ri) = ri->resetvalue; 93 } 94 } 95 96 static void cp_reg_check_reset(gpointer key, gpointer value, gpointer opaque) 97 { 98 /* Purely an assertion check: we've already done reset once, 99 * so now check that running the reset for the cpreg doesn't 100 * change its value. This traps bugs where two different cpregs 101 * both try to reset the same state field but to different values. 102 */ 103 ARMCPRegInfo *ri = value; 104 ARMCPU *cpu = opaque; 105 uint64_t oldvalue, newvalue; 106 107 if (ri->type & (ARM_CP_SPECIAL | ARM_CP_ALIAS | ARM_CP_NO_RAW)) { 108 return; 109 } 110 111 oldvalue = read_raw_cp_reg(&cpu->env, ri); 112 cp_reg_reset(key, value, opaque); 113 newvalue = read_raw_cp_reg(&cpu->env, ri); 114 assert(oldvalue == newvalue); 115 } 116 117 /* CPUClass::reset() */ 118 static void arm_cpu_reset(CPUState *s) 119 { 120 ARMCPU *cpu = ARM_CPU(s); 121 ARMCPUClass *acc = ARM_CPU_GET_CLASS(cpu); 122 CPUARMState *env = &cpu->env; 123 124 acc->parent_reset(s); 125 126 memset(env, 0, offsetof(CPUARMState, end_reset_fields)); 127 128 g_hash_table_foreach(cpu->cp_regs, cp_reg_reset, cpu); 129 g_hash_table_foreach(cpu->cp_regs, cp_reg_check_reset, cpu); 130 131 env->vfp.xregs[ARM_VFP_FPSID] = cpu->reset_fpsid; 132 env->vfp.xregs[ARM_VFP_MVFR0] = cpu->mvfr0; 133 env->vfp.xregs[ARM_VFP_MVFR1] = cpu->mvfr1; 134 env->vfp.xregs[ARM_VFP_MVFR2] = cpu->mvfr2; 135 136 cpu->power_state = cpu->start_powered_off ? PSCI_OFF : PSCI_ON; 137 s->halted = cpu->start_powered_off; 138 139 if (arm_feature(env, ARM_FEATURE_IWMMXT)) { 140 env->iwmmxt.cregs[ARM_IWMMXT_wCID] = 0x69051000 | 'Q'; 141 } 142 143 if (arm_feature(env, ARM_FEATURE_AARCH64)) { 144 /* 64 bit CPUs always start in 64 bit mode */ 145 env->aarch64 = 1; 146 #if defined(CONFIG_USER_ONLY) 147 env->pstate = PSTATE_MODE_EL0t; 148 /* Userspace expects access to DC ZVA, CTL_EL0 and the cache ops */ 149 env->cp15.sctlr_el[1] |= SCTLR_UCT | SCTLR_UCI | SCTLR_DZE; 150 /* and to the FP/Neon instructions */ 151 env->cp15.cpacr_el1 = deposit64(env->cp15.cpacr_el1, 20, 2, 3); 152 #else 153 /* Reset into the highest available EL */ 154 if (arm_feature(env, ARM_FEATURE_EL3)) { 155 env->pstate = PSTATE_MODE_EL3h; 156 } else if (arm_feature(env, ARM_FEATURE_EL2)) { 157 env->pstate = PSTATE_MODE_EL2h; 158 } else { 159 env->pstate = PSTATE_MODE_EL1h; 160 } 161 env->pc = cpu->rvbar; 162 #endif 163 } else { 164 #if defined(CONFIG_USER_ONLY) 165 /* Userspace expects access to cp10 and cp11 for FP/Neon */ 166 env->cp15.cpacr_el1 = deposit64(env->cp15.cpacr_el1, 20, 4, 0xf); 167 #endif 168 } 169 170 #if defined(CONFIG_USER_ONLY) 171 env->uncached_cpsr = ARM_CPU_MODE_USR; 172 /* For user mode we must enable access to coprocessors */ 173 env->vfp.xregs[ARM_VFP_FPEXC] = 1 << 30; 174 if (arm_feature(env, ARM_FEATURE_IWMMXT)) { 175 env->cp15.c15_cpar = 3; 176 } else if (arm_feature(env, ARM_FEATURE_XSCALE)) { 177 env->cp15.c15_cpar = 1; 178 } 179 #else 180 /* SVC mode with interrupts disabled. */ 181 env->uncached_cpsr = ARM_CPU_MODE_SVC; 182 env->daif = PSTATE_D | PSTATE_A | PSTATE_I | PSTATE_F; 183 184 if (arm_feature(env, ARM_FEATURE_M)) { 185 uint32_t initial_msp; /* Loaded from 0x0 */ 186 uint32_t initial_pc; /* Loaded from 0x4 */ 187 uint8_t *rom; 188 189 if (arm_feature(env, ARM_FEATURE_M_SECURITY)) { 190 env->v7m.secure = true; 191 } else { 192 /* This bit resets to 0 if security is supported, but 1 if 193 * it is not. The bit is not present in v7M, but we set it 194 * here so we can avoid having to make checks on it conditional 195 * on ARM_FEATURE_V8 (we don't let the guest see the bit). 196 */ 197 env->v7m.aircr = R_V7M_AIRCR_BFHFNMINS_MASK; 198 } 199 200 /* In v7M the reset value of this bit is IMPDEF, but ARM recommends 201 * that it resets to 1, so QEMU always does that rather than making 202 * it dependent on CPU model. In v8M it is RES1. 203 */ 204 env->v7m.ccr[M_REG_NS] = R_V7M_CCR_STKALIGN_MASK; 205 env->v7m.ccr[M_REG_S] = R_V7M_CCR_STKALIGN_MASK; 206 if (arm_feature(env, ARM_FEATURE_V8)) { 207 /* in v8M the NONBASETHRDENA bit [0] is RES1 */ 208 env->v7m.ccr[M_REG_NS] |= R_V7M_CCR_NONBASETHRDENA_MASK; 209 env->v7m.ccr[M_REG_S] |= R_V7M_CCR_NONBASETHRDENA_MASK; 210 } 211 212 /* Unlike A/R profile, M profile defines the reset LR value */ 213 env->regs[14] = 0xffffffff; 214 215 /* Load the initial SP and PC from the vector table at address 0 */ 216 rom = rom_ptr(0); 217 if (rom) { 218 /* Address zero is covered by ROM which hasn't yet been 219 * copied into physical memory. 220 */ 221 initial_msp = ldl_p(rom); 222 initial_pc = ldl_p(rom + 4); 223 } else { 224 /* Address zero not covered by a ROM blob, or the ROM blob 225 * is in non-modifiable memory and this is a second reset after 226 * it got copied into memory. In the latter case, rom_ptr 227 * will return a NULL pointer and we should use ldl_phys instead. 228 */ 229 initial_msp = ldl_phys(s->as, 0); 230 initial_pc = ldl_phys(s->as, 4); 231 } 232 233 env->regs[13] = initial_msp & 0xFFFFFFFC; 234 env->regs[15] = initial_pc & ~1; 235 env->thumb = initial_pc & 1; 236 } 237 238 /* AArch32 has a hard highvec setting of 0xFFFF0000. If we are currently 239 * executing as AArch32 then check if highvecs are enabled and 240 * adjust the PC accordingly. 241 */ 242 if (A32_BANKED_CURRENT_REG_GET(env, sctlr) & SCTLR_V) { 243 env->regs[15] = 0xFFFF0000; 244 } 245 246 /* M profile requires that reset clears the exclusive monitor; 247 * A profile does not, but clearing it makes more sense than having it 248 * set with an exclusive access on address zero. 249 */ 250 arm_clear_exclusive(env); 251 252 env->vfp.xregs[ARM_VFP_FPEXC] = 0; 253 #endif 254 255 if (arm_feature(env, ARM_FEATURE_PMSA)) { 256 if (cpu->pmsav7_dregion > 0) { 257 if (arm_feature(env, ARM_FEATURE_V8)) { 258 memset(env->pmsav8.rbar[M_REG_NS], 0, 259 sizeof(*env->pmsav8.rbar[M_REG_NS]) 260 * cpu->pmsav7_dregion); 261 memset(env->pmsav8.rlar[M_REG_NS], 0, 262 sizeof(*env->pmsav8.rlar[M_REG_NS]) 263 * cpu->pmsav7_dregion); 264 if (arm_feature(env, ARM_FEATURE_M_SECURITY)) { 265 memset(env->pmsav8.rbar[M_REG_S], 0, 266 sizeof(*env->pmsav8.rbar[M_REG_S]) 267 * cpu->pmsav7_dregion); 268 memset(env->pmsav8.rlar[M_REG_S], 0, 269 sizeof(*env->pmsav8.rlar[M_REG_S]) 270 * cpu->pmsav7_dregion); 271 } 272 } else if (arm_feature(env, ARM_FEATURE_V7)) { 273 memset(env->pmsav7.drbar, 0, 274 sizeof(*env->pmsav7.drbar) * cpu->pmsav7_dregion); 275 memset(env->pmsav7.drsr, 0, 276 sizeof(*env->pmsav7.drsr) * cpu->pmsav7_dregion); 277 memset(env->pmsav7.dracr, 0, 278 sizeof(*env->pmsav7.dracr) * cpu->pmsav7_dregion); 279 } 280 } 281 env->pmsav7.rnr[M_REG_NS] = 0; 282 env->pmsav7.rnr[M_REG_S] = 0; 283 env->pmsav8.mair0[M_REG_NS] = 0; 284 env->pmsav8.mair0[M_REG_S] = 0; 285 env->pmsav8.mair1[M_REG_NS] = 0; 286 env->pmsav8.mair1[M_REG_S] = 0; 287 } 288 289 if (arm_feature(env, ARM_FEATURE_M_SECURITY)) { 290 if (cpu->sau_sregion > 0) { 291 memset(env->sau.rbar, 0, sizeof(*env->sau.rbar) * cpu->sau_sregion); 292 memset(env->sau.rlar, 0, sizeof(*env->sau.rlar) * cpu->sau_sregion); 293 } 294 env->sau.rnr = 0; 295 /* SAU_CTRL reset value is IMPDEF; we choose 0, which is what 296 * the Cortex-M33 does. 297 */ 298 env->sau.ctrl = 0; 299 } 300 301 set_flush_to_zero(1, &env->vfp.standard_fp_status); 302 set_flush_inputs_to_zero(1, &env->vfp.standard_fp_status); 303 set_default_nan_mode(1, &env->vfp.standard_fp_status); 304 set_float_detect_tininess(float_tininess_before_rounding, 305 &env->vfp.fp_status); 306 set_float_detect_tininess(float_tininess_before_rounding, 307 &env->vfp.standard_fp_status); 308 #ifndef CONFIG_USER_ONLY 309 if (kvm_enabled()) { 310 kvm_arm_reset_vcpu(cpu); 311 } 312 #endif 313 314 hw_breakpoint_update_all(cpu); 315 hw_watchpoint_update_all(cpu); 316 } 317 318 bool arm_cpu_exec_interrupt(CPUState *cs, int interrupt_request) 319 { 320 CPUClass *cc = CPU_GET_CLASS(cs); 321 CPUARMState *env = cs->env_ptr; 322 uint32_t cur_el = arm_current_el(env); 323 bool secure = arm_is_secure(env); 324 uint32_t target_el; 325 uint32_t excp_idx; 326 bool ret = false; 327 328 if (interrupt_request & CPU_INTERRUPT_FIQ) { 329 excp_idx = EXCP_FIQ; 330 target_el = arm_phys_excp_target_el(cs, excp_idx, cur_el, secure); 331 if (arm_excp_unmasked(cs, excp_idx, target_el)) { 332 cs->exception_index = excp_idx; 333 env->exception.target_el = target_el; 334 cc->do_interrupt(cs); 335 ret = true; 336 } 337 } 338 if (interrupt_request & CPU_INTERRUPT_HARD) { 339 excp_idx = EXCP_IRQ; 340 target_el = arm_phys_excp_target_el(cs, excp_idx, cur_el, secure); 341 if (arm_excp_unmasked(cs, excp_idx, target_el)) { 342 cs->exception_index = excp_idx; 343 env->exception.target_el = target_el; 344 cc->do_interrupt(cs); 345 ret = true; 346 } 347 } 348 if (interrupt_request & CPU_INTERRUPT_VIRQ) { 349 excp_idx = EXCP_VIRQ; 350 target_el = 1; 351 if (arm_excp_unmasked(cs, excp_idx, target_el)) { 352 cs->exception_index = excp_idx; 353 env->exception.target_el = target_el; 354 cc->do_interrupt(cs); 355 ret = true; 356 } 357 } 358 if (interrupt_request & CPU_INTERRUPT_VFIQ) { 359 excp_idx = EXCP_VFIQ; 360 target_el = 1; 361 if (arm_excp_unmasked(cs, excp_idx, target_el)) { 362 cs->exception_index = excp_idx; 363 env->exception.target_el = target_el; 364 cc->do_interrupt(cs); 365 ret = true; 366 } 367 } 368 369 return ret; 370 } 371 372 #if !defined(CONFIG_USER_ONLY) || !defined(TARGET_AARCH64) 373 static bool arm_v7m_cpu_exec_interrupt(CPUState *cs, int interrupt_request) 374 { 375 CPUClass *cc = CPU_GET_CLASS(cs); 376 ARMCPU *cpu = ARM_CPU(cs); 377 CPUARMState *env = &cpu->env; 378 bool ret = false; 379 380 /* ARMv7-M interrupt masking works differently than -A or -R. 381 * There is no FIQ/IRQ distinction. Instead of I and F bits 382 * masking FIQ and IRQ interrupts, an exception is taken only 383 * if it is higher priority than the current execution priority 384 * (which depends on state like BASEPRI, FAULTMASK and the 385 * currently active exception). 386 */ 387 if (interrupt_request & CPU_INTERRUPT_HARD 388 && (armv7m_nvic_can_take_pending_exception(env->nvic))) { 389 cs->exception_index = EXCP_IRQ; 390 cc->do_interrupt(cs); 391 ret = true; 392 } 393 return ret; 394 } 395 #endif 396 397 #ifndef CONFIG_USER_ONLY 398 static void arm_cpu_set_irq(void *opaque, int irq, int level) 399 { 400 ARMCPU *cpu = opaque; 401 CPUARMState *env = &cpu->env; 402 CPUState *cs = CPU(cpu); 403 static const int mask[] = { 404 [ARM_CPU_IRQ] = CPU_INTERRUPT_HARD, 405 [ARM_CPU_FIQ] = CPU_INTERRUPT_FIQ, 406 [ARM_CPU_VIRQ] = CPU_INTERRUPT_VIRQ, 407 [ARM_CPU_VFIQ] = CPU_INTERRUPT_VFIQ 408 }; 409 410 switch (irq) { 411 case ARM_CPU_VIRQ: 412 case ARM_CPU_VFIQ: 413 assert(arm_feature(env, ARM_FEATURE_EL2)); 414 /* fall through */ 415 case ARM_CPU_IRQ: 416 case ARM_CPU_FIQ: 417 if (level) { 418 cpu_interrupt(cs, mask[irq]); 419 } else { 420 cpu_reset_interrupt(cs, mask[irq]); 421 } 422 break; 423 default: 424 g_assert_not_reached(); 425 } 426 } 427 428 static void arm_cpu_kvm_set_irq(void *opaque, int irq, int level) 429 { 430 #ifdef CONFIG_KVM 431 ARMCPU *cpu = opaque; 432 CPUState *cs = CPU(cpu); 433 int kvm_irq = KVM_ARM_IRQ_TYPE_CPU << KVM_ARM_IRQ_TYPE_SHIFT; 434 435 switch (irq) { 436 case ARM_CPU_IRQ: 437 kvm_irq |= KVM_ARM_IRQ_CPU_IRQ; 438 break; 439 case ARM_CPU_FIQ: 440 kvm_irq |= KVM_ARM_IRQ_CPU_FIQ; 441 break; 442 default: 443 g_assert_not_reached(); 444 } 445 kvm_irq |= cs->cpu_index << KVM_ARM_IRQ_VCPU_SHIFT; 446 kvm_set_irq(kvm_state, kvm_irq, level ? 1 : 0); 447 #endif 448 } 449 450 static bool arm_cpu_virtio_is_big_endian(CPUState *cs) 451 { 452 ARMCPU *cpu = ARM_CPU(cs); 453 CPUARMState *env = &cpu->env; 454 455 cpu_synchronize_state(cs); 456 return arm_cpu_data_is_big_endian(env); 457 } 458 459 #endif 460 461 static inline void set_feature(CPUARMState *env, int feature) 462 { 463 env->features |= 1ULL << feature; 464 } 465 466 static inline void unset_feature(CPUARMState *env, int feature) 467 { 468 env->features &= ~(1ULL << feature); 469 } 470 471 static int 472 print_insn_thumb1(bfd_vma pc, disassemble_info *info) 473 { 474 return print_insn_arm(pc | 1, info); 475 } 476 477 static void arm_disas_set_info(CPUState *cpu, disassemble_info *info) 478 { 479 ARMCPU *ac = ARM_CPU(cpu); 480 CPUARMState *env = &ac->env; 481 bool sctlr_b; 482 483 if (is_a64(env)) { 484 /* We might not be compiled with the A64 disassembler 485 * because it needs a C++ compiler. Leave print_insn 486 * unset in this case to use the caller default behaviour. 487 */ 488 #if defined(CONFIG_ARM_A64_DIS) 489 info->print_insn = print_insn_arm_a64; 490 #endif 491 info->cap_arch = CS_ARCH_ARM64; 492 } else { 493 int cap_mode; 494 if (env->thumb) { 495 info->print_insn = print_insn_thumb1; 496 cap_mode = CS_MODE_THUMB; 497 } else { 498 info->print_insn = print_insn_arm; 499 cap_mode = CS_MODE_ARM; 500 } 501 if (arm_feature(env, ARM_FEATURE_V8)) { 502 cap_mode |= CS_MODE_V8; 503 } 504 if (arm_feature(env, ARM_FEATURE_M)) { 505 cap_mode |= CS_MODE_MCLASS; 506 } 507 info->cap_arch = CS_ARCH_ARM; 508 info->cap_mode = cap_mode; 509 } 510 511 sctlr_b = arm_sctlr_b(env); 512 if (bswap_code(sctlr_b)) { 513 #ifdef TARGET_WORDS_BIGENDIAN 514 info->endian = BFD_ENDIAN_LITTLE; 515 #else 516 info->endian = BFD_ENDIAN_BIG; 517 #endif 518 } 519 info->flags &= ~INSN_ARM_BE32; 520 #ifndef CONFIG_USER_ONLY 521 if (sctlr_b) { 522 info->flags |= INSN_ARM_BE32; 523 } 524 #endif 525 } 526 527 uint64_t arm_cpu_mp_affinity(int idx, uint8_t clustersz) 528 { 529 uint32_t Aff1 = idx / clustersz; 530 uint32_t Aff0 = idx % clustersz; 531 return (Aff1 << ARM_AFF1_SHIFT) | Aff0; 532 } 533 534 static void arm_cpu_initfn(Object *obj) 535 { 536 CPUState *cs = CPU(obj); 537 ARMCPU *cpu = ARM_CPU(obj); 538 539 cs->env_ptr = &cpu->env; 540 cpu->cp_regs = g_hash_table_new_full(g_int_hash, g_int_equal, 541 g_free, g_free); 542 543 #ifndef CONFIG_USER_ONLY 544 /* Our inbound IRQ and FIQ lines */ 545 if (kvm_enabled()) { 546 /* VIRQ and VFIQ are unused with KVM but we add them to maintain 547 * the same interface as non-KVM CPUs. 548 */ 549 qdev_init_gpio_in(DEVICE(cpu), arm_cpu_kvm_set_irq, 4); 550 } else { 551 qdev_init_gpio_in(DEVICE(cpu), arm_cpu_set_irq, 4); 552 } 553 554 cpu->gt_timer[GTIMER_PHYS] = timer_new(QEMU_CLOCK_VIRTUAL, GTIMER_SCALE, 555 arm_gt_ptimer_cb, cpu); 556 cpu->gt_timer[GTIMER_VIRT] = timer_new(QEMU_CLOCK_VIRTUAL, GTIMER_SCALE, 557 arm_gt_vtimer_cb, cpu); 558 cpu->gt_timer[GTIMER_HYP] = timer_new(QEMU_CLOCK_VIRTUAL, GTIMER_SCALE, 559 arm_gt_htimer_cb, cpu); 560 cpu->gt_timer[GTIMER_SEC] = timer_new(QEMU_CLOCK_VIRTUAL, GTIMER_SCALE, 561 arm_gt_stimer_cb, cpu); 562 qdev_init_gpio_out(DEVICE(cpu), cpu->gt_timer_outputs, 563 ARRAY_SIZE(cpu->gt_timer_outputs)); 564 565 qdev_init_gpio_out_named(DEVICE(cpu), &cpu->gicv3_maintenance_interrupt, 566 "gicv3-maintenance-interrupt", 1); 567 qdev_init_gpio_out_named(DEVICE(cpu), &cpu->pmu_interrupt, 568 "pmu-interrupt", 1); 569 #endif 570 571 /* DTB consumers generally don't in fact care what the 'compatible' 572 * string is, so always provide some string and trust that a hypothetical 573 * picky DTB consumer will also provide a helpful error message. 574 */ 575 cpu->dtb_compatible = "qemu,unknown"; 576 cpu->psci_version = 1; /* By default assume PSCI v0.1 */ 577 cpu->kvm_target = QEMU_KVM_ARM_TARGET_NONE; 578 579 if (tcg_enabled()) { 580 cpu->psci_version = 2; /* TCG implements PSCI 0.2 */ 581 } 582 } 583 584 static Property arm_cpu_reset_cbar_property = 585 DEFINE_PROP_UINT64("reset-cbar", ARMCPU, reset_cbar, 0); 586 587 static Property arm_cpu_reset_hivecs_property = 588 DEFINE_PROP_BOOL("reset-hivecs", ARMCPU, reset_hivecs, false); 589 590 static Property arm_cpu_rvbar_property = 591 DEFINE_PROP_UINT64("rvbar", ARMCPU, rvbar, 0); 592 593 static Property arm_cpu_has_el2_property = 594 DEFINE_PROP_BOOL("has_el2", ARMCPU, has_el2, true); 595 596 static Property arm_cpu_has_el3_property = 597 DEFINE_PROP_BOOL("has_el3", ARMCPU, has_el3, true); 598 599 static Property arm_cpu_cfgend_property = 600 DEFINE_PROP_BOOL("cfgend", ARMCPU, cfgend, false); 601 602 /* use property name "pmu" to match other archs and virt tools */ 603 static Property arm_cpu_has_pmu_property = 604 DEFINE_PROP_BOOL("pmu", ARMCPU, has_pmu, true); 605 606 static Property arm_cpu_has_mpu_property = 607 DEFINE_PROP_BOOL("has-mpu", ARMCPU, has_mpu, true); 608 609 /* This is like DEFINE_PROP_UINT32 but it doesn't set the default value, 610 * because the CPU initfn will have already set cpu->pmsav7_dregion to 611 * the right value for that particular CPU type, and we don't want 612 * to override that with an incorrect constant value. 613 */ 614 static Property arm_cpu_pmsav7_dregion_property = 615 DEFINE_PROP_UNSIGNED_NODEFAULT("pmsav7-dregion", ARMCPU, 616 pmsav7_dregion, 617 qdev_prop_uint32, uint32_t); 618 619 static void arm_cpu_post_init(Object *obj) 620 { 621 ARMCPU *cpu = ARM_CPU(obj); 622 623 /* M profile implies PMSA. We have to do this here rather than 624 * in realize with the other feature-implication checks because 625 * we look at the PMSA bit to see if we should add some properties. 626 */ 627 if (arm_feature(&cpu->env, ARM_FEATURE_M)) { 628 set_feature(&cpu->env, ARM_FEATURE_PMSA); 629 } 630 631 if (arm_feature(&cpu->env, ARM_FEATURE_CBAR) || 632 arm_feature(&cpu->env, ARM_FEATURE_CBAR_RO)) { 633 qdev_property_add_static(DEVICE(obj), &arm_cpu_reset_cbar_property, 634 &error_abort); 635 } 636 637 if (!arm_feature(&cpu->env, ARM_FEATURE_M)) { 638 qdev_property_add_static(DEVICE(obj), &arm_cpu_reset_hivecs_property, 639 &error_abort); 640 } 641 642 if (arm_feature(&cpu->env, ARM_FEATURE_AARCH64)) { 643 qdev_property_add_static(DEVICE(obj), &arm_cpu_rvbar_property, 644 &error_abort); 645 } 646 647 if (arm_feature(&cpu->env, ARM_FEATURE_EL3)) { 648 /* Add the has_el3 state CPU property only if EL3 is allowed. This will 649 * prevent "has_el3" from existing on CPUs which cannot support EL3. 650 */ 651 qdev_property_add_static(DEVICE(obj), &arm_cpu_has_el3_property, 652 &error_abort); 653 654 #ifndef CONFIG_USER_ONLY 655 object_property_add_link(obj, "secure-memory", 656 TYPE_MEMORY_REGION, 657 (Object **)&cpu->secure_memory, 658 qdev_prop_allow_set_link_before_realize, 659 OBJ_PROP_LINK_UNREF_ON_RELEASE, 660 &error_abort); 661 #endif 662 } 663 664 if (arm_feature(&cpu->env, ARM_FEATURE_EL2)) { 665 qdev_property_add_static(DEVICE(obj), &arm_cpu_has_el2_property, 666 &error_abort); 667 } 668 669 if (arm_feature(&cpu->env, ARM_FEATURE_PMU)) { 670 qdev_property_add_static(DEVICE(obj), &arm_cpu_has_pmu_property, 671 &error_abort); 672 } 673 674 if (arm_feature(&cpu->env, ARM_FEATURE_PMSA)) { 675 qdev_property_add_static(DEVICE(obj), &arm_cpu_has_mpu_property, 676 &error_abort); 677 if (arm_feature(&cpu->env, ARM_FEATURE_V7)) { 678 qdev_property_add_static(DEVICE(obj), 679 &arm_cpu_pmsav7_dregion_property, 680 &error_abort); 681 } 682 } 683 684 qdev_property_add_static(DEVICE(obj), &arm_cpu_cfgend_property, 685 &error_abort); 686 } 687 688 static void arm_cpu_finalizefn(Object *obj) 689 { 690 ARMCPU *cpu = ARM_CPU(obj); 691 g_hash_table_destroy(cpu->cp_regs); 692 } 693 694 static void arm_cpu_realizefn(DeviceState *dev, Error **errp) 695 { 696 CPUState *cs = CPU(dev); 697 ARMCPU *cpu = ARM_CPU(dev); 698 ARMCPUClass *acc = ARM_CPU_GET_CLASS(dev); 699 CPUARMState *env = &cpu->env; 700 int pagebits; 701 Error *local_err = NULL; 702 #ifndef CONFIG_USER_ONLY 703 AddressSpace *as; 704 #endif 705 706 cpu_exec_realizefn(cs, &local_err); 707 if (local_err != NULL) { 708 error_propagate(errp, local_err); 709 return; 710 } 711 712 /* Some features automatically imply others: */ 713 if (arm_feature(env, ARM_FEATURE_V8)) { 714 set_feature(env, ARM_FEATURE_V7); 715 set_feature(env, ARM_FEATURE_ARM_DIV); 716 set_feature(env, ARM_FEATURE_LPAE); 717 } 718 if (arm_feature(env, ARM_FEATURE_V7)) { 719 set_feature(env, ARM_FEATURE_VAPA); 720 set_feature(env, ARM_FEATURE_THUMB2); 721 set_feature(env, ARM_FEATURE_MPIDR); 722 if (!arm_feature(env, ARM_FEATURE_M)) { 723 set_feature(env, ARM_FEATURE_V6K); 724 } else { 725 set_feature(env, ARM_FEATURE_V6); 726 } 727 728 /* Always define VBAR for V7 CPUs even if it doesn't exist in 729 * non-EL3 configs. This is needed by some legacy boards. 730 */ 731 set_feature(env, ARM_FEATURE_VBAR); 732 } 733 if (arm_feature(env, ARM_FEATURE_V6K)) { 734 set_feature(env, ARM_FEATURE_V6); 735 set_feature(env, ARM_FEATURE_MVFR); 736 } 737 if (arm_feature(env, ARM_FEATURE_V6)) { 738 set_feature(env, ARM_FEATURE_V5); 739 set_feature(env, ARM_FEATURE_JAZELLE); 740 if (!arm_feature(env, ARM_FEATURE_M)) { 741 set_feature(env, ARM_FEATURE_AUXCR); 742 } 743 } 744 if (arm_feature(env, ARM_FEATURE_V5)) { 745 set_feature(env, ARM_FEATURE_V4T); 746 } 747 if (arm_feature(env, ARM_FEATURE_M)) { 748 set_feature(env, ARM_FEATURE_THUMB_DIV); 749 } 750 if (arm_feature(env, ARM_FEATURE_ARM_DIV)) { 751 set_feature(env, ARM_FEATURE_THUMB_DIV); 752 } 753 if (arm_feature(env, ARM_FEATURE_VFP4)) { 754 set_feature(env, ARM_FEATURE_VFP3); 755 set_feature(env, ARM_FEATURE_VFP_FP16); 756 } 757 if (arm_feature(env, ARM_FEATURE_VFP3)) { 758 set_feature(env, ARM_FEATURE_VFP); 759 } 760 if (arm_feature(env, ARM_FEATURE_LPAE)) { 761 set_feature(env, ARM_FEATURE_V7MP); 762 set_feature(env, ARM_FEATURE_PXN); 763 } 764 if (arm_feature(env, ARM_FEATURE_CBAR_RO)) { 765 set_feature(env, ARM_FEATURE_CBAR); 766 } 767 if (arm_feature(env, ARM_FEATURE_THUMB2) && 768 !arm_feature(env, ARM_FEATURE_M)) { 769 set_feature(env, ARM_FEATURE_THUMB_DSP); 770 } 771 772 if (arm_feature(env, ARM_FEATURE_V7) && 773 !arm_feature(env, ARM_FEATURE_M) && 774 !arm_feature(env, ARM_FEATURE_PMSA)) { 775 /* v7VMSA drops support for the old ARMv5 tiny pages, so we 776 * can use 4K pages. 777 */ 778 pagebits = 12; 779 } else { 780 /* For CPUs which might have tiny 1K pages, or which have an 781 * MPU and might have small region sizes, stick with 1K pages. 782 */ 783 pagebits = 10; 784 } 785 if (!set_preferred_target_page_bits(pagebits)) { 786 /* This can only ever happen for hotplugging a CPU, or if 787 * the board code incorrectly creates a CPU which it has 788 * promised via minimum_page_size that it will not. 789 */ 790 error_setg(errp, "This CPU requires a smaller page size than the " 791 "system is using"); 792 return; 793 } 794 795 /* This cpu-id-to-MPIDR affinity is used only for TCG; KVM will override it. 796 * We don't support setting cluster ID ([16..23]) (known as Aff2 797 * in later ARM ARM versions), or any of the higher affinity level fields, 798 * so these bits always RAZ. 799 */ 800 if (cpu->mp_affinity == ARM64_AFFINITY_INVALID) { 801 cpu->mp_affinity = arm_cpu_mp_affinity(cs->cpu_index, 802 ARM_DEFAULT_CPUS_PER_CLUSTER); 803 } 804 805 if (cpu->reset_hivecs) { 806 cpu->reset_sctlr |= (1 << 13); 807 } 808 809 if (cpu->cfgend) { 810 if (arm_feature(&cpu->env, ARM_FEATURE_V7)) { 811 cpu->reset_sctlr |= SCTLR_EE; 812 } else { 813 cpu->reset_sctlr |= SCTLR_B; 814 } 815 } 816 817 if (!cpu->has_el3) { 818 /* If the has_el3 CPU property is disabled then we need to disable the 819 * feature. 820 */ 821 unset_feature(env, ARM_FEATURE_EL3); 822 823 /* Disable the security extension feature bits in the processor feature 824 * registers as well. These are id_pfr1[7:4] and id_aa64pfr0[15:12]. 825 */ 826 cpu->id_pfr1 &= ~0xf0; 827 cpu->id_aa64pfr0 &= ~0xf000; 828 } 829 830 if (!cpu->has_el2) { 831 unset_feature(env, ARM_FEATURE_EL2); 832 } 833 834 if (!cpu->has_pmu) { 835 unset_feature(env, ARM_FEATURE_PMU); 836 cpu->id_aa64dfr0 &= ~0xf00; 837 } 838 839 if (!arm_feature(env, ARM_FEATURE_EL2)) { 840 /* Disable the hypervisor feature bits in the processor feature 841 * registers if we don't have EL2. These are id_pfr1[15:12] and 842 * id_aa64pfr0_el1[11:8]. 843 */ 844 cpu->id_aa64pfr0 &= ~0xf00; 845 cpu->id_pfr1 &= ~0xf000; 846 } 847 848 /* MPU can be configured out of a PMSA CPU either by setting has-mpu 849 * to false or by setting pmsav7-dregion to 0. 850 */ 851 if (!cpu->has_mpu) { 852 cpu->pmsav7_dregion = 0; 853 } 854 if (cpu->pmsav7_dregion == 0) { 855 cpu->has_mpu = false; 856 } 857 858 if (arm_feature(env, ARM_FEATURE_PMSA) && 859 arm_feature(env, ARM_FEATURE_V7)) { 860 uint32_t nr = cpu->pmsav7_dregion; 861 862 if (nr > 0xff) { 863 error_setg(errp, "PMSAv7 MPU #regions invalid %" PRIu32, nr); 864 return; 865 } 866 867 if (nr) { 868 if (arm_feature(env, ARM_FEATURE_V8)) { 869 /* PMSAv8 */ 870 env->pmsav8.rbar[M_REG_NS] = g_new0(uint32_t, nr); 871 env->pmsav8.rlar[M_REG_NS] = g_new0(uint32_t, nr); 872 if (arm_feature(env, ARM_FEATURE_M_SECURITY)) { 873 env->pmsav8.rbar[M_REG_S] = g_new0(uint32_t, nr); 874 env->pmsav8.rlar[M_REG_S] = g_new0(uint32_t, nr); 875 } 876 } else { 877 env->pmsav7.drbar = g_new0(uint32_t, nr); 878 env->pmsav7.drsr = g_new0(uint32_t, nr); 879 env->pmsav7.dracr = g_new0(uint32_t, nr); 880 } 881 } 882 } 883 884 if (arm_feature(env, ARM_FEATURE_M_SECURITY)) { 885 uint32_t nr = cpu->sau_sregion; 886 887 if (nr > 0xff) { 888 error_setg(errp, "v8M SAU #regions invalid %" PRIu32, nr); 889 return; 890 } 891 892 if (nr) { 893 env->sau.rbar = g_new0(uint32_t, nr); 894 env->sau.rlar = g_new0(uint32_t, nr); 895 } 896 } 897 898 if (arm_feature(env, ARM_FEATURE_EL3)) { 899 set_feature(env, ARM_FEATURE_VBAR); 900 } 901 902 register_cp_regs_for_features(cpu); 903 arm_cpu_register_gdb_regs_for_features(cpu); 904 905 init_cpreg_list(cpu); 906 907 #ifndef CONFIG_USER_ONLY 908 if (cpu->has_el3 || arm_feature(env, ARM_FEATURE_M_SECURITY)) { 909 as = g_new0(AddressSpace, 1); 910 911 cs->num_ases = 2; 912 913 if (!cpu->secure_memory) { 914 cpu->secure_memory = cs->memory; 915 } 916 address_space_init(as, cpu->secure_memory, "cpu-secure-memory"); 917 cpu_address_space_init(cs, as, ARMASIdx_S); 918 } else { 919 cs->num_ases = 1; 920 } 921 as = g_new0(AddressSpace, 1); 922 address_space_init(as, cs->memory, "cpu-memory"); 923 cpu_address_space_init(cs, as, ARMASIdx_NS); 924 #endif 925 926 qemu_init_vcpu(cs); 927 cpu_reset(cs); 928 929 acc->parent_realize(dev, errp); 930 } 931 932 static ObjectClass *arm_cpu_class_by_name(const char *cpu_model) 933 { 934 ObjectClass *oc; 935 char *typename; 936 char **cpuname; 937 938 cpuname = g_strsplit(cpu_model, ",", 1); 939 typename = g_strdup_printf(ARM_CPU_TYPE_NAME("%s"), cpuname[0]); 940 oc = object_class_by_name(typename); 941 g_strfreev(cpuname); 942 g_free(typename); 943 if (!oc || !object_class_dynamic_cast(oc, TYPE_ARM_CPU) || 944 object_class_is_abstract(oc)) { 945 return NULL; 946 } 947 return oc; 948 } 949 950 /* CPU models. These are not needed for the AArch64 linux-user build. */ 951 #if !defined(CONFIG_USER_ONLY) || !defined(TARGET_AARCH64) 952 953 static void arm926_initfn(Object *obj) 954 { 955 ARMCPU *cpu = ARM_CPU(obj); 956 957 cpu->dtb_compatible = "arm,arm926"; 958 set_feature(&cpu->env, ARM_FEATURE_V5); 959 set_feature(&cpu->env, ARM_FEATURE_VFP); 960 set_feature(&cpu->env, ARM_FEATURE_DUMMY_C15_REGS); 961 set_feature(&cpu->env, ARM_FEATURE_CACHE_TEST_CLEAN); 962 set_feature(&cpu->env, ARM_FEATURE_JAZELLE); 963 cpu->midr = 0x41069265; 964 cpu->reset_fpsid = 0x41011090; 965 cpu->ctr = 0x1dd20d2; 966 cpu->reset_sctlr = 0x00090078; 967 } 968 969 static void arm946_initfn(Object *obj) 970 { 971 ARMCPU *cpu = ARM_CPU(obj); 972 973 cpu->dtb_compatible = "arm,arm946"; 974 set_feature(&cpu->env, ARM_FEATURE_V5); 975 set_feature(&cpu->env, ARM_FEATURE_PMSA); 976 set_feature(&cpu->env, ARM_FEATURE_DUMMY_C15_REGS); 977 cpu->midr = 0x41059461; 978 cpu->ctr = 0x0f004006; 979 cpu->reset_sctlr = 0x00000078; 980 } 981 982 static void arm1026_initfn(Object *obj) 983 { 984 ARMCPU *cpu = ARM_CPU(obj); 985 986 cpu->dtb_compatible = "arm,arm1026"; 987 set_feature(&cpu->env, ARM_FEATURE_V5); 988 set_feature(&cpu->env, ARM_FEATURE_VFP); 989 set_feature(&cpu->env, ARM_FEATURE_AUXCR); 990 set_feature(&cpu->env, ARM_FEATURE_DUMMY_C15_REGS); 991 set_feature(&cpu->env, ARM_FEATURE_CACHE_TEST_CLEAN); 992 set_feature(&cpu->env, ARM_FEATURE_JAZELLE); 993 cpu->midr = 0x4106a262; 994 cpu->reset_fpsid = 0x410110a0; 995 cpu->ctr = 0x1dd20d2; 996 cpu->reset_sctlr = 0x00090078; 997 cpu->reset_auxcr = 1; 998 { 999 /* The 1026 had an IFAR at c6,c0,0,1 rather than the ARMv6 c6,c0,0,2 */ 1000 ARMCPRegInfo ifar = { 1001 .name = "IFAR", .cp = 15, .crn = 6, .crm = 0, .opc1 = 0, .opc2 = 1, 1002 .access = PL1_RW, 1003 .fieldoffset = offsetof(CPUARMState, cp15.ifar_ns), 1004 .resetvalue = 0 1005 }; 1006 define_one_arm_cp_reg(cpu, &ifar); 1007 } 1008 } 1009 1010 static void arm1136_r2_initfn(Object *obj) 1011 { 1012 ARMCPU *cpu = ARM_CPU(obj); 1013 /* What qemu calls "arm1136_r2" is actually the 1136 r0p2, ie an 1014 * older core than plain "arm1136". In particular this does not 1015 * have the v6K features. 1016 * These ID register values are correct for 1136 but may be wrong 1017 * for 1136_r2 (in particular r0p2 does not actually implement most 1018 * of the ID registers). 1019 */ 1020 1021 cpu->dtb_compatible = "arm,arm1136"; 1022 set_feature(&cpu->env, ARM_FEATURE_V6); 1023 set_feature(&cpu->env, ARM_FEATURE_VFP); 1024 set_feature(&cpu->env, ARM_FEATURE_DUMMY_C15_REGS); 1025 set_feature(&cpu->env, ARM_FEATURE_CACHE_DIRTY_REG); 1026 set_feature(&cpu->env, ARM_FEATURE_CACHE_BLOCK_OPS); 1027 cpu->midr = 0x4107b362; 1028 cpu->reset_fpsid = 0x410120b4; 1029 cpu->mvfr0 = 0x11111111; 1030 cpu->mvfr1 = 0x00000000; 1031 cpu->ctr = 0x1dd20d2; 1032 cpu->reset_sctlr = 0x00050078; 1033 cpu->id_pfr0 = 0x111; 1034 cpu->id_pfr1 = 0x1; 1035 cpu->id_dfr0 = 0x2; 1036 cpu->id_afr0 = 0x3; 1037 cpu->id_mmfr0 = 0x01130003; 1038 cpu->id_mmfr1 = 0x10030302; 1039 cpu->id_mmfr2 = 0x01222110; 1040 cpu->id_isar0 = 0x00140011; 1041 cpu->id_isar1 = 0x12002111; 1042 cpu->id_isar2 = 0x11231111; 1043 cpu->id_isar3 = 0x01102131; 1044 cpu->id_isar4 = 0x141; 1045 cpu->reset_auxcr = 7; 1046 } 1047 1048 static void arm1136_initfn(Object *obj) 1049 { 1050 ARMCPU *cpu = ARM_CPU(obj); 1051 1052 cpu->dtb_compatible = "arm,arm1136"; 1053 set_feature(&cpu->env, ARM_FEATURE_V6K); 1054 set_feature(&cpu->env, ARM_FEATURE_V6); 1055 set_feature(&cpu->env, ARM_FEATURE_VFP); 1056 set_feature(&cpu->env, ARM_FEATURE_DUMMY_C15_REGS); 1057 set_feature(&cpu->env, ARM_FEATURE_CACHE_DIRTY_REG); 1058 set_feature(&cpu->env, ARM_FEATURE_CACHE_BLOCK_OPS); 1059 cpu->midr = 0x4117b363; 1060 cpu->reset_fpsid = 0x410120b4; 1061 cpu->mvfr0 = 0x11111111; 1062 cpu->mvfr1 = 0x00000000; 1063 cpu->ctr = 0x1dd20d2; 1064 cpu->reset_sctlr = 0x00050078; 1065 cpu->id_pfr0 = 0x111; 1066 cpu->id_pfr1 = 0x1; 1067 cpu->id_dfr0 = 0x2; 1068 cpu->id_afr0 = 0x3; 1069 cpu->id_mmfr0 = 0x01130003; 1070 cpu->id_mmfr1 = 0x10030302; 1071 cpu->id_mmfr2 = 0x01222110; 1072 cpu->id_isar0 = 0x00140011; 1073 cpu->id_isar1 = 0x12002111; 1074 cpu->id_isar2 = 0x11231111; 1075 cpu->id_isar3 = 0x01102131; 1076 cpu->id_isar4 = 0x141; 1077 cpu->reset_auxcr = 7; 1078 } 1079 1080 static void arm1176_initfn(Object *obj) 1081 { 1082 ARMCPU *cpu = ARM_CPU(obj); 1083 1084 cpu->dtb_compatible = "arm,arm1176"; 1085 set_feature(&cpu->env, ARM_FEATURE_V6K); 1086 set_feature(&cpu->env, ARM_FEATURE_VFP); 1087 set_feature(&cpu->env, ARM_FEATURE_VAPA); 1088 set_feature(&cpu->env, ARM_FEATURE_DUMMY_C15_REGS); 1089 set_feature(&cpu->env, ARM_FEATURE_CACHE_DIRTY_REG); 1090 set_feature(&cpu->env, ARM_FEATURE_CACHE_BLOCK_OPS); 1091 set_feature(&cpu->env, ARM_FEATURE_EL3); 1092 cpu->midr = 0x410fb767; 1093 cpu->reset_fpsid = 0x410120b5; 1094 cpu->mvfr0 = 0x11111111; 1095 cpu->mvfr1 = 0x00000000; 1096 cpu->ctr = 0x1dd20d2; 1097 cpu->reset_sctlr = 0x00050078; 1098 cpu->id_pfr0 = 0x111; 1099 cpu->id_pfr1 = 0x11; 1100 cpu->id_dfr0 = 0x33; 1101 cpu->id_afr0 = 0; 1102 cpu->id_mmfr0 = 0x01130003; 1103 cpu->id_mmfr1 = 0x10030302; 1104 cpu->id_mmfr2 = 0x01222100; 1105 cpu->id_isar0 = 0x0140011; 1106 cpu->id_isar1 = 0x12002111; 1107 cpu->id_isar2 = 0x11231121; 1108 cpu->id_isar3 = 0x01102131; 1109 cpu->id_isar4 = 0x01141; 1110 cpu->reset_auxcr = 7; 1111 } 1112 1113 static void arm11mpcore_initfn(Object *obj) 1114 { 1115 ARMCPU *cpu = ARM_CPU(obj); 1116 1117 cpu->dtb_compatible = "arm,arm11mpcore"; 1118 set_feature(&cpu->env, ARM_FEATURE_V6K); 1119 set_feature(&cpu->env, ARM_FEATURE_VFP); 1120 set_feature(&cpu->env, ARM_FEATURE_VAPA); 1121 set_feature(&cpu->env, ARM_FEATURE_MPIDR); 1122 set_feature(&cpu->env, ARM_FEATURE_DUMMY_C15_REGS); 1123 cpu->midr = 0x410fb022; 1124 cpu->reset_fpsid = 0x410120b4; 1125 cpu->mvfr0 = 0x11111111; 1126 cpu->mvfr1 = 0x00000000; 1127 cpu->ctr = 0x1d192992; /* 32K icache 32K dcache */ 1128 cpu->id_pfr0 = 0x111; 1129 cpu->id_pfr1 = 0x1; 1130 cpu->id_dfr0 = 0; 1131 cpu->id_afr0 = 0x2; 1132 cpu->id_mmfr0 = 0x01100103; 1133 cpu->id_mmfr1 = 0x10020302; 1134 cpu->id_mmfr2 = 0x01222000; 1135 cpu->id_isar0 = 0x00100011; 1136 cpu->id_isar1 = 0x12002111; 1137 cpu->id_isar2 = 0x11221011; 1138 cpu->id_isar3 = 0x01102131; 1139 cpu->id_isar4 = 0x141; 1140 cpu->reset_auxcr = 1; 1141 } 1142 1143 static void cortex_m3_initfn(Object *obj) 1144 { 1145 ARMCPU *cpu = ARM_CPU(obj); 1146 set_feature(&cpu->env, ARM_FEATURE_V7); 1147 set_feature(&cpu->env, ARM_FEATURE_M); 1148 cpu->midr = 0x410fc231; 1149 cpu->pmsav7_dregion = 8; 1150 } 1151 1152 static void cortex_m4_initfn(Object *obj) 1153 { 1154 ARMCPU *cpu = ARM_CPU(obj); 1155 1156 set_feature(&cpu->env, ARM_FEATURE_V7); 1157 set_feature(&cpu->env, ARM_FEATURE_M); 1158 set_feature(&cpu->env, ARM_FEATURE_THUMB_DSP); 1159 cpu->midr = 0x410fc240; /* r0p0 */ 1160 cpu->pmsav7_dregion = 8; 1161 } 1162 1163 static void arm_v7m_class_init(ObjectClass *oc, void *data) 1164 { 1165 CPUClass *cc = CPU_CLASS(oc); 1166 1167 #ifndef CONFIG_USER_ONLY 1168 cc->do_interrupt = arm_v7m_cpu_do_interrupt; 1169 #endif 1170 1171 cc->cpu_exec_interrupt = arm_v7m_cpu_exec_interrupt; 1172 } 1173 1174 static const ARMCPRegInfo cortexr5_cp_reginfo[] = { 1175 /* Dummy the TCM region regs for the moment */ 1176 { .name = "ATCM", .cp = 15, .opc1 = 0, .crn = 9, .crm = 1, .opc2 = 0, 1177 .access = PL1_RW, .type = ARM_CP_CONST }, 1178 { .name = "BTCM", .cp = 15, .opc1 = 0, .crn = 9, .crm = 1, .opc2 = 1, 1179 .access = PL1_RW, .type = ARM_CP_CONST }, 1180 { .name = "DCACHE_INVAL", .cp = 15, .opc1 = 0, .crn = 15, .crm = 5, 1181 .opc2 = 0, .access = PL1_W, .type = ARM_CP_NOP }, 1182 REGINFO_SENTINEL 1183 }; 1184 1185 static void cortex_r5_initfn(Object *obj) 1186 { 1187 ARMCPU *cpu = ARM_CPU(obj); 1188 1189 set_feature(&cpu->env, ARM_FEATURE_V7); 1190 set_feature(&cpu->env, ARM_FEATURE_THUMB_DIV); 1191 set_feature(&cpu->env, ARM_FEATURE_ARM_DIV); 1192 set_feature(&cpu->env, ARM_FEATURE_V7MP); 1193 set_feature(&cpu->env, ARM_FEATURE_PMSA); 1194 cpu->midr = 0x411fc153; /* r1p3 */ 1195 cpu->id_pfr0 = 0x0131; 1196 cpu->id_pfr1 = 0x001; 1197 cpu->id_dfr0 = 0x010400; 1198 cpu->id_afr0 = 0x0; 1199 cpu->id_mmfr0 = 0x0210030; 1200 cpu->id_mmfr1 = 0x00000000; 1201 cpu->id_mmfr2 = 0x01200000; 1202 cpu->id_mmfr3 = 0x0211; 1203 cpu->id_isar0 = 0x2101111; 1204 cpu->id_isar1 = 0x13112111; 1205 cpu->id_isar2 = 0x21232141; 1206 cpu->id_isar3 = 0x01112131; 1207 cpu->id_isar4 = 0x0010142; 1208 cpu->id_isar5 = 0x0; 1209 cpu->mp_is_up = true; 1210 cpu->pmsav7_dregion = 16; 1211 define_arm_cp_regs(cpu, cortexr5_cp_reginfo); 1212 } 1213 1214 static const ARMCPRegInfo cortexa8_cp_reginfo[] = { 1215 { .name = "L2LOCKDOWN", .cp = 15, .crn = 9, .crm = 0, .opc1 = 1, .opc2 = 0, 1216 .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0 }, 1217 { .name = "L2AUXCR", .cp = 15, .crn = 9, .crm = 0, .opc1 = 1, .opc2 = 2, 1218 .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0 }, 1219 REGINFO_SENTINEL 1220 }; 1221 1222 static void cortex_a8_initfn(Object *obj) 1223 { 1224 ARMCPU *cpu = ARM_CPU(obj); 1225 1226 cpu->dtb_compatible = "arm,cortex-a8"; 1227 set_feature(&cpu->env, ARM_FEATURE_V7); 1228 set_feature(&cpu->env, ARM_FEATURE_VFP3); 1229 set_feature(&cpu->env, ARM_FEATURE_NEON); 1230 set_feature(&cpu->env, ARM_FEATURE_THUMB2EE); 1231 set_feature(&cpu->env, ARM_FEATURE_DUMMY_C15_REGS); 1232 set_feature(&cpu->env, ARM_FEATURE_EL3); 1233 cpu->midr = 0x410fc080; 1234 cpu->reset_fpsid = 0x410330c0; 1235 cpu->mvfr0 = 0x11110222; 1236 cpu->mvfr1 = 0x00011111; 1237 cpu->ctr = 0x82048004; 1238 cpu->reset_sctlr = 0x00c50078; 1239 cpu->id_pfr0 = 0x1031; 1240 cpu->id_pfr1 = 0x11; 1241 cpu->id_dfr0 = 0x400; 1242 cpu->id_afr0 = 0; 1243 cpu->id_mmfr0 = 0x31100003; 1244 cpu->id_mmfr1 = 0x20000000; 1245 cpu->id_mmfr2 = 0x01202000; 1246 cpu->id_mmfr3 = 0x11; 1247 cpu->id_isar0 = 0x00101111; 1248 cpu->id_isar1 = 0x12112111; 1249 cpu->id_isar2 = 0x21232031; 1250 cpu->id_isar3 = 0x11112131; 1251 cpu->id_isar4 = 0x00111142; 1252 cpu->dbgdidr = 0x15141000; 1253 cpu->clidr = (1 << 27) | (2 << 24) | 3; 1254 cpu->ccsidr[0] = 0xe007e01a; /* 16k L1 dcache. */ 1255 cpu->ccsidr[1] = 0x2007e01a; /* 16k L1 icache. */ 1256 cpu->ccsidr[2] = 0xf0000000; /* No L2 icache. */ 1257 cpu->reset_auxcr = 2; 1258 define_arm_cp_regs(cpu, cortexa8_cp_reginfo); 1259 } 1260 1261 static const ARMCPRegInfo cortexa9_cp_reginfo[] = { 1262 /* power_control should be set to maximum latency. Again, 1263 * default to 0 and set by private hook 1264 */ 1265 { .name = "A9_PWRCTL", .cp = 15, .crn = 15, .crm = 0, .opc1 = 0, .opc2 = 0, 1266 .access = PL1_RW, .resetvalue = 0, 1267 .fieldoffset = offsetof(CPUARMState, cp15.c15_power_control) }, 1268 { .name = "A9_DIAG", .cp = 15, .crn = 15, .crm = 0, .opc1 = 0, .opc2 = 1, 1269 .access = PL1_RW, .resetvalue = 0, 1270 .fieldoffset = offsetof(CPUARMState, cp15.c15_diagnostic) }, 1271 { .name = "A9_PWRDIAG", .cp = 15, .crn = 15, .crm = 0, .opc1 = 0, .opc2 = 2, 1272 .access = PL1_RW, .resetvalue = 0, 1273 .fieldoffset = offsetof(CPUARMState, cp15.c15_power_diagnostic) }, 1274 { .name = "NEONBUSY", .cp = 15, .crn = 15, .crm = 1, .opc1 = 0, .opc2 = 0, 1275 .access = PL1_RW, .resetvalue = 0, .type = ARM_CP_CONST }, 1276 /* TLB lockdown control */ 1277 { .name = "TLB_LOCKR", .cp = 15, .crn = 15, .crm = 4, .opc1 = 5, .opc2 = 2, 1278 .access = PL1_W, .resetvalue = 0, .type = ARM_CP_NOP }, 1279 { .name = "TLB_LOCKW", .cp = 15, .crn = 15, .crm = 4, .opc1 = 5, .opc2 = 4, 1280 .access = PL1_W, .resetvalue = 0, .type = ARM_CP_NOP }, 1281 { .name = "TLB_VA", .cp = 15, .crn = 15, .crm = 5, .opc1 = 5, .opc2 = 2, 1282 .access = PL1_RW, .resetvalue = 0, .type = ARM_CP_CONST }, 1283 { .name = "TLB_PA", .cp = 15, .crn = 15, .crm = 6, .opc1 = 5, .opc2 = 2, 1284 .access = PL1_RW, .resetvalue = 0, .type = ARM_CP_CONST }, 1285 { .name = "TLB_ATTR", .cp = 15, .crn = 15, .crm = 7, .opc1 = 5, .opc2 = 2, 1286 .access = PL1_RW, .resetvalue = 0, .type = ARM_CP_CONST }, 1287 REGINFO_SENTINEL 1288 }; 1289 1290 static void cortex_a9_initfn(Object *obj) 1291 { 1292 ARMCPU *cpu = ARM_CPU(obj); 1293 1294 cpu->dtb_compatible = "arm,cortex-a9"; 1295 set_feature(&cpu->env, ARM_FEATURE_V7); 1296 set_feature(&cpu->env, ARM_FEATURE_VFP3); 1297 set_feature(&cpu->env, ARM_FEATURE_VFP_FP16); 1298 set_feature(&cpu->env, ARM_FEATURE_NEON); 1299 set_feature(&cpu->env, ARM_FEATURE_THUMB2EE); 1300 set_feature(&cpu->env, ARM_FEATURE_EL3); 1301 /* Note that A9 supports the MP extensions even for 1302 * A9UP and single-core A9MP (which are both different 1303 * and valid configurations; we don't model A9UP). 1304 */ 1305 set_feature(&cpu->env, ARM_FEATURE_V7MP); 1306 set_feature(&cpu->env, ARM_FEATURE_CBAR); 1307 cpu->midr = 0x410fc090; 1308 cpu->reset_fpsid = 0x41033090; 1309 cpu->mvfr0 = 0x11110222; 1310 cpu->mvfr1 = 0x01111111; 1311 cpu->ctr = 0x80038003; 1312 cpu->reset_sctlr = 0x00c50078; 1313 cpu->id_pfr0 = 0x1031; 1314 cpu->id_pfr1 = 0x11; 1315 cpu->id_dfr0 = 0x000; 1316 cpu->id_afr0 = 0; 1317 cpu->id_mmfr0 = 0x00100103; 1318 cpu->id_mmfr1 = 0x20000000; 1319 cpu->id_mmfr2 = 0x01230000; 1320 cpu->id_mmfr3 = 0x00002111; 1321 cpu->id_isar0 = 0x00101111; 1322 cpu->id_isar1 = 0x13112111; 1323 cpu->id_isar2 = 0x21232041; 1324 cpu->id_isar3 = 0x11112131; 1325 cpu->id_isar4 = 0x00111142; 1326 cpu->dbgdidr = 0x35141000; 1327 cpu->clidr = (1 << 27) | (1 << 24) | 3; 1328 cpu->ccsidr[0] = 0xe00fe019; /* 16k L1 dcache. */ 1329 cpu->ccsidr[1] = 0x200fe019; /* 16k L1 icache. */ 1330 define_arm_cp_regs(cpu, cortexa9_cp_reginfo); 1331 } 1332 1333 #ifndef CONFIG_USER_ONLY 1334 static uint64_t a15_l2ctlr_read(CPUARMState *env, const ARMCPRegInfo *ri) 1335 { 1336 /* Linux wants the number of processors from here. 1337 * Might as well set the interrupt-controller bit too. 1338 */ 1339 return ((smp_cpus - 1) << 24) | (1 << 23); 1340 } 1341 #endif 1342 1343 static const ARMCPRegInfo cortexa15_cp_reginfo[] = { 1344 #ifndef CONFIG_USER_ONLY 1345 { .name = "L2CTLR", .cp = 15, .crn = 9, .crm = 0, .opc1 = 1, .opc2 = 2, 1346 .access = PL1_RW, .resetvalue = 0, .readfn = a15_l2ctlr_read, 1347 .writefn = arm_cp_write_ignore, }, 1348 #endif 1349 { .name = "L2ECTLR", .cp = 15, .crn = 9, .crm = 0, .opc1 = 1, .opc2 = 3, 1350 .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0 }, 1351 REGINFO_SENTINEL 1352 }; 1353 1354 static void cortex_a7_initfn(Object *obj) 1355 { 1356 ARMCPU *cpu = ARM_CPU(obj); 1357 1358 cpu->dtb_compatible = "arm,cortex-a7"; 1359 set_feature(&cpu->env, ARM_FEATURE_V7); 1360 set_feature(&cpu->env, ARM_FEATURE_VFP4); 1361 set_feature(&cpu->env, ARM_FEATURE_NEON); 1362 set_feature(&cpu->env, ARM_FEATURE_THUMB2EE); 1363 set_feature(&cpu->env, ARM_FEATURE_ARM_DIV); 1364 set_feature(&cpu->env, ARM_FEATURE_GENERIC_TIMER); 1365 set_feature(&cpu->env, ARM_FEATURE_DUMMY_C15_REGS); 1366 set_feature(&cpu->env, ARM_FEATURE_CBAR_RO); 1367 set_feature(&cpu->env, ARM_FEATURE_LPAE); 1368 set_feature(&cpu->env, ARM_FEATURE_EL3); 1369 cpu->kvm_target = QEMU_KVM_ARM_TARGET_CORTEX_A7; 1370 cpu->midr = 0x410fc075; 1371 cpu->reset_fpsid = 0x41023075; 1372 cpu->mvfr0 = 0x10110222; 1373 cpu->mvfr1 = 0x11111111; 1374 cpu->ctr = 0x84448003; 1375 cpu->reset_sctlr = 0x00c50078; 1376 cpu->id_pfr0 = 0x00001131; 1377 cpu->id_pfr1 = 0x00011011; 1378 cpu->id_dfr0 = 0x02010555; 1379 cpu->pmceid0 = 0x00000000; 1380 cpu->pmceid1 = 0x00000000; 1381 cpu->id_afr0 = 0x00000000; 1382 cpu->id_mmfr0 = 0x10101105; 1383 cpu->id_mmfr1 = 0x40000000; 1384 cpu->id_mmfr2 = 0x01240000; 1385 cpu->id_mmfr3 = 0x02102211; 1386 cpu->id_isar0 = 0x01101110; 1387 cpu->id_isar1 = 0x13112111; 1388 cpu->id_isar2 = 0x21232041; 1389 cpu->id_isar3 = 0x11112131; 1390 cpu->id_isar4 = 0x10011142; 1391 cpu->dbgdidr = 0x3515f005; 1392 cpu->clidr = 0x0a200023; 1393 cpu->ccsidr[0] = 0x701fe00a; /* 32K L1 dcache */ 1394 cpu->ccsidr[1] = 0x201fe00a; /* 32K L1 icache */ 1395 cpu->ccsidr[2] = 0x711fe07a; /* 4096K L2 unified cache */ 1396 define_arm_cp_regs(cpu, cortexa15_cp_reginfo); /* Same as A15 */ 1397 } 1398 1399 static void cortex_a15_initfn(Object *obj) 1400 { 1401 ARMCPU *cpu = ARM_CPU(obj); 1402 1403 cpu->dtb_compatible = "arm,cortex-a15"; 1404 set_feature(&cpu->env, ARM_FEATURE_V7); 1405 set_feature(&cpu->env, ARM_FEATURE_VFP4); 1406 set_feature(&cpu->env, ARM_FEATURE_NEON); 1407 set_feature(&cpu->env, ARM_FEATURE_THUMB2EE); 1408 set_feature(&cpu->env, ARM_FEATURE_ARM_DIV); 1409 set_feature(&cpu->env, ARM_FEATURE_GENERIC_TIMER); 1410 set_feature(&cpu->env, ARM_FEATURE_DUMMY_C15_REGS); 1411 set_feature(&cpu->env, ARM_FEATURE_CBAR_RO); 1412 set_feature(&cpu->env, ARM_FEATURE_LPAE); 1413 set_feature(&cpu->env, ARM_FEATURE_EL3); 1414 cpu->kvm_target = QEMU_KVM_ARM_TARGET_CORTEX_A15; 1415 cpu->midr = 0x412fc0f1; 1416 cpu->reset_fpsid = 0x410430f0; 1417 cpu->mvfr0 = 0x10110222; 1418 cpu->mvfr1 = 0x11111111; 1419 cpu->ctr = 0x8444c004; 1420 cpu->reset_sctlr = 0x00c50078; 1421 cpu->id_pfr0 = 0x00001131; 1422 cpu->id_pfr1 = 0x00011011; 1423 cpu->id_dfr0 = 0x02010555; 1424 cpu->pmceid0 = 0x0000000; 1425 cpu->pmceid1 = 0x00000000; 1426 cpu->id_afr0 = 0x00000000; 1427 cpu->id_mmfr0 = 0x10201105; 1428 cpu->id_mmfr1 = 0x20000000; 1429 cpu->id_mmfr2 = 0x01240000; 1430 cpu->id_mmfr3 = 0x02102211; 1431 cpu->id_isar0 = 0x02101110; 1432 cpu->id_isar1 = 0x13112111; 1433 cpu->id_isar2 = 0x21232041; 1434 cpu->id_isar3 = 0x11112131; 1435 cpu->id_isar4 = 0x10011142; 1436 cpu->dbgdidr = 0x3515f021; 1437 cpu->clidr = 0x0a200023; 1438 cpu->ccsidr[0] = 0x701fe00a; /* 32K L1 dcache */ 1439 cpu->ccsidr[1] = 0x201fe00a; /* 32K L1 icache */ 1440 cpu->ccsidr[2] = 0x711fe07a; /* 4096K L2 unified cache */ 1441 define_arm_cp_regs(cpu, cortexa15_cp_reginfo); 1442 } 1443 1444 static void ti925t_initfn(Object *obj) 1445 { 1446 ARMCPU *cpu = ARM_CPU(obj); 1447 set_feature(&cpu->env, ARM_FEATURE_V4T); 1448 set_feature(&cpu->env, ARM_FEATURE_OMAPCP); 1449 cpu->midr = ARM_CPUID_TI925T; 1450 cpu->ctr = 0x5109149; 1451 cpu->reset_sctlr = 0x00000070; 1452 } 1453 1454 static void sa1100_initfn(Object *obj) 1455 { 1456 ARMCPU *cpu = ARM_CPU(obj); 1457 1458 cpu->dtb_compatible = "intel,sa1100"; 1459 set_feature(&cpu->env, ARM_FEATURE_STRONGARM); 1460 set_feature(&cpu->env, ARM_FEATURE_DUMMY_C15_REGS); 1461 cpu->midr = 0x4401A11B; 1462 cpu->reset_sctlr = 0x00000070; 1463 } 1464 1465 static void sa1110_initfn(Object *obj) 1466 { 1467 ARMCPU *cpu = ARM_CPU(obj); 1468 set_feature(&cpu->env, ARM_FEATURE_STRONGARM); 1469 set_feature(&cpu->env, ARM_FEATURE_DUMMY_C15_REGS); 1470 cpu->midr = 0x6901B119; 1471 cpu->reset_sctlr = 0x00000070; 1472 } 1473 1474 static void pxa250_initfn(Object *obj) 1475 { 1476 ARMCPU *cpu = ARM_CPU(obj); 1477 1478 cpu->dtb_compatible = "marvell,xscale"; 1479 set_feature(&cpu->env, ARM_FEATURE_V5); 1480 set_feature(&cpu->env, ARM_FEATURE_XSCALE); 1481 cpu->midr = 0x69052100; 1482 cpu->ctr = 0xd172172; 1483 cpu->reset_sctlr = 0x00000078; 1484 } 1485 1486 static void pxa255_initfn(Object *obj) 1487 { 1488 ARMCPU *cpu = ARM_CPU(obj); 1489 1490 cpu->dtb_compatible = "marvell,xscale"; 1491 set_feature(&cpu->env, ARM_FEATURE_V5); 1492 set_feature(&cpu->env, ARM_FEATURE_XSCALE); 1493 cpu->midr = 0x69052d00; 1494 cpu->ctr = 0xd172172; 1495 cpu->reset_sctlr = 0x00000078; 1496 } 1497 1498 static void pxa260_initfn(Object *obj) 1499 { 1500 ARMCPU *cpu = ARM_CPU(obj); 1501 1502 cpu->dtb_compatible = "marvell,xscale"; 1503 set_feature(&cpu->env, ARM_FEATURE_V5); 1504 set_feature(&cpu->env, ARM_FEATURE_XSCALE); 1505 cpu->midr = 0x69052903; 1506 cpu->ctr = 0xd172172; 1507 cpu->reset_sctlr = 0x00000078; 1508 } 1509 1510 static void pxa261_initfn(Object *obj) 1511 { 1512 ARMCPU *cpu = ARM_CPU(obj); 1513 1514 cpu->dtb_compatible = "marvell,xscale"; 1515 set_feature(&cpu->env, ARM_FEATURE_V5); 1516 set_feature(&cpu->env, ARM_FEATURE_XSCALE); 1517 cpu->midr = 0x69052d05; 1518 cpu->ctr = 0xd172172; 1519 cpu->reset_sctlr = 0x00000078; 1520 } 1521 1522 static void pxa262_initfn(Object *obj) 1523 { 1524 ARMCPU *cpu = ARM_CPU(obj); 1525 1526 cpu->dtb_compatible = "marvell,xscale"; 1527 set_feature(&cpu->env, ARM_FEATURE_V5); 1528 set_feature(&cpu->env, ARM_FEATURE_XSCALE); 1529 cpu->midr = 0x69052d06; 1530 cpu->ctr = 0xd172172; 1531 cpu->reset_sctlr = 0x00000078; 1532 } 1533 1534 static void pxa270a0_initfn(Object *obj) 1535 { 1536 ARMCPU *cpu = ARM_CPU(obj); 1537 1538 cpu->dtb_compatible = "marvell,xscale"; 1539 set_feature(&cpu->env, ARM_FEATURE_V5); 1540 set_feature(&cpu->env, ARM_FEATURE_XSCALE); 1541 set_feature(&cpu->env, ARM_FEATURE_IWMMXT); 1542 cpu->midr = 0x69054110; 1543 cpu->ctr = 0xd172172; 1544 cpu->reset_sctlr = 0x00000078; 1545 } 1546 1547 static void pxa270a1_initfn(Object *obj) 1548 { 1549 ARMCPU *cpu = ARM_CPU(obj); 1550 1551 cpu->dtb_compatible = "marvell,xscale"; 1552 set_feature(&cpu->env, ARM_FEATURE_V5); 1553 set_feature(&cpu->env, ARM_FEATURE_XSCALE); 1554 set_feature(&cpu->env, ARM_FEATURE_IWMMXT); 1555 cpu->midr = 0x69054111; 1556 cpu->ctr = 0xd172172; 1557 cpu->reset_sctlr = 0x00000078; 1558 } 1559 1560 static void pxa270b0_initfn(Object *obj) 1561 { 1562 ARMCPU *cpu = ARM_CPU(obj); 1563 1564 cpu->dtb_compatible = "marvell,xscale"; 1565 set_feature(&cpu->env, ARM_FEATURE_V5); 1566 set_feature(&cpu->env, ARM_FEATURE_XSCALE); 1567 set_feature(&cpu->env, ARM_FEATURE_IWMMXT); 1568 cpu->midr = 0x69054112; 1569 cpu->ctr = 0xd172172; 1570 cpu->reset_sctlr = 0x00000078; 1571 } 1572 1573 static void pxa270b1_initfn(Object *obj) 1574 { 1575 ARMCPU *cpu = ARM_CPU(obj); 1576 1577 cpu->dtb_compatible = "marvell,xscale"; 1578 set_feature(&cpu->env, ARM_FEATURE_V5); 1579 set_feature(&cpu->env, ARM_FEATURE_XSCALE); 1580 set_feature(&cpu->env, ARM_FEATURE_IWMMXT); 1581 cpu->midr = 0x69054113; 1582 cpu->ctr = 0xd172172; 1583 cpu->reset_sctlr = 0x00000078; 1584 } 1585 1586 static void pxa270c0_initfn(Object *obj) 1587 { 1588 ARMCPU *cpu = ARM_CPU(obj); 1589 1590 cpu->dtb_compatible = "marvell,xscale"; 1591 set_feature(&cpu->env, ARM_FEATURE_V5); 1592 set_feature(&cpu->env, ARM_FEATURE_XSCALE); 1593 set_feature(&cpu->env, ARM_FEATURE_IWMMXT); 1594 cpu->midr = 0x69054114; 1595 cpu->ctr = 0xd172172; 1596 cpu->reset_sctlr = 0x00000078; 1597 } 1598 1599 static void pxa270c5_initfn(Object *obj) 1600 { 1601 ARMCPU *cpu = ARM_CPU(obj); 1602 1603 cpu->dtb_compatible = "marvell,xscale"; 1604 set_feature(&cpu->env, ARM_FEATURE_V5); 1605 set_feature(&cpu->env, ARM_FEATURE_XSCALE); 1606 set_feature(&cpu->env, ARM_FEATURE_IWMMXT); 1607 cpu->midr = 0x69054117; 1608 cpu->ctr = 0xd172172; 1609 cpu->reset_sctlr = 0x00000078; 1610 } 1611 1612 #ifdef CONFIG_USER_ONLY 1613 static void arm_any_initfn(Object *obj) 1614 { 1615 ARMCPU *cpu = ARM_CPU(obj); 1616 set_feature(&cpu->env, ARM_FEATURE_V8); 1617 set_feature(&cpu->env, ARM_FEATURE_VFP4); 1618 set_feature(&cpu->env, ARM_FEATURE_NEON); 1619 set_feature(&cpu->env, ARM_FEATURE_THUMB2EE); 1620 set_feature(&cpu->env, ARM_FEATURE_V8_AES); 1621 set_feature(&cpu->env, ARM_FEATURE_V8_SHA1); 1622 set_feature(&cpu->env, ARM_FEATURE_V8_SHA256); 1623 set_feature(&cpu->env, ARM_FEATURE_V8_PMULL); 1624 set_feature(&cpu->env, ARM_FEATURE_CRC); 1625 cpu->midr = 0xffffffff; 1626 } 1627 #endif 1628 1629 #endif /* !defined(CONFIG_USER_ONLY) || !defined(TARGET_AARCH64) */ 1630 1631 typedef struct ARMCPUInfo { 1632 const char *name; 1633 void (*initfn)(Object *obj); 1634 void (*class_init)(ObjectClass *oc, void *data); 1635 } ARMCPUInfo; 1636 1637 static const ARMCPUInfo arm_cpus[] = { 1638 #if !defined(CONFIG_USER_ONLY) || !defined(TARGET_AARCH64) 1639 { .name = "arm926", .initfn = arm926_initfn }, 1640 { .name = "arm946", .initfn = arm946_initfn }, 1641 { .name = "arm1026", .initfn = arm1026_initfn }, 1642 /* What QEMU calls "arm1136-r2" is actually the 1136 r0p2, i.e. an 1643 * older core than plain "arm1136". In particular this does not 1644 * have the v6K features. 1645 */ 1646 { .name = "arm1136-r2", .initfn = arm1136_r2_initfn }, 1647 { .name = "arm1136", .initfn = arm1136_initfn }, 1648 { .name = "arm1176", .initfn = arm1176_initfn }, 1649 { .name = "arm11mpcore", .initfn = arm11mpcore_initfn }, 1650 { .name = "cortex-m3", .initfn = cortex_m3_initfn, 1651 .class_init = arm_v7m_class_init }, 1652 { .name = "cortex-m4", .initfn = cortex_m4_initfn, 1653 .class_init = arm_v7m_class_init }, 1654 { .name = "cortex-r5", .initfn = cortex_r5_initfn }, 1655 { .name = "cortex-a7", .initfn = cortex_a7_initfn }, 1656 { .name = "cortex-a8", .initfn = cortex_a8_initfn }, 1657 { .name = "cortex-a9", .initfn = cortex_a9_initfn }, 1658 { .name = "cortex-a15", .initfn = cortex_a15_initfn }, 1659 { .name = "ti925t", .initfn = ti925t_initfn }, 1660 { .name = "sa1100", .initfn = sa1100_initfn }, 1661 { .name = "sa1110", .initfn = sa1110_initfn }, 1662 { .name = "pxa250", .initfn = pxa250_initfn }, 1663 { .name = "pxa255", .initfn = pxa255_initfn }, 1664 { .name = "pxa260", .initfn = pxa260_initfn }, 1665 { .name = "pxa261", .initfn = pxa261_initfn }, 1666 { .name = "pxa262", .initfn = pxa262_initfn }, 1667 /* "pxa270" is an alias for "pxa270-a0" */ 1668 { .name = "pxa270", .initfn = pxa270a0_initfn }, 1669 { .name = "pxa270-a0", .initfn = pxa270a0_initfn }, 1670 { .name = "pxa270-a1", .initfn = pxa270a1_initfn }, 1671 { .name = "pxa270-b0", .initfn = pxa270b0_initfn }, 1672 { .name = "pxa270-b1", .initfn = pxa270b1_initfn }, 1673 { .name = "pxa270-c0", .initfn = pxa270c0_initfn }, 1674 { .name = "pxa270-c5", .initfn = pxa270c5_initfn }, 1675 #ifdef CONFIG_USER_ONLY 1676 { .name = "any", .initfn = arm_any_initfn }, 1677 #endif 1678 #endif 1679 { .name = NULL } 1680 }; 1681 1682 static Property arm_cpu_properties[] = { 1683 DEFINE_PROP_BOOL("start-powered-off", ARMCPU, start_powered_off, false), 1684 DEFINE_PROP_UINT32("psci-conduit", ARMCPU, psci_conduit, 0), 1685 DEFINE_PROP_UINT32("midr", ARMCPU, midr, 0), 1686 DEFINE_PROP_UINT64("mp-affinity", ARMCPU, 1687 mp_affinity, ARM64_AFFINITY_INVALID), 1688 DEFINE_PROP_INT32("node-id", ARMCPU, node_id, CPU_UNSET_NUMA_NODE_ID), 1689 DEFINE_PROP_END_OF_LIST() 1690 }; 1691 1692 #ifdef CONFIG_USER_ONLY 1693 static int arm_cpu_handle_mmu_fault(CPUState *cs, vaddr address, int rw, 1694 int mmu_idx) 1695 { 1696 ARMCPU *cpu = ARM_CPU(cs); 1697 CPUARMState *env = &cpu->env; 1698 1699 env->exception.vaddress = address; 1700 if (rw == 2) { 1701 cs->exception_index = EXCP_PREFETCH_ABORT; 1702 } else { 1703 cs->exception_index = EXCP_DATA_ABORT; 1704 } 1705 return 1; 1706 } 1707 #endif 1708 1709 static gchar *arm_gdb_arch_name(CPUState *cs) 1710 { 1711 ARMCPU *cpu = ARM_CPU(cs); 1712 CPUARMState *env = &cpu->env; 1713 1714 if (arm_feature(env, ARM_FEATURE_IWMMXT)) { 1715 return g_strdup("iwmmxt"); 1716 } 1717 return g_strdup("arm"); 1718 } 1719 1720 static void arm_cpu_class_init(ObjectClass *oc, void *data) 1721 { 1722 ARMCPUClass *acc = ARM_CPU_CLASS(oc); 1723 CPUClass *cc = CPU_CLASS(acc); 1724 DeviceClass *dc = DEVICE_CLASS(oc); 1725 1726 acc->parent_realize = dc->realize; 1727 dc->realize = arm_cpu_realizefn; 1728 dc->props = arm_cpu_properties; 1729 1730 acc->parent_reset = cc->reset; 1731 cc->reset = arm_cpu_reset; 1732 1733 cc->class_by_name = arm_cpu_class_by_name; 1734 cc->has_work = arm_cpu_has_work; 1735 cc->cpu_exec_interrupt = arm_cpu_exec_interrupt; 1736 cc->dump_state = arm_cpu_dump_state; 1737 cc->set_pc = arm_cpu_set_pc; 1738 cc->gdb_read_register = arm_cpu_gdb_read_register; 1739 cc->gdb_write_register = arm_cpu_gdb_write_register; 1740 #ifdef CONFIG_USER_ONLY 1741 cc->handle_mmu_fault = arm_cpu_handle_mmu_fault; 1742 #else 1743 cc->do_interrupt = arm_cpu_do_interrupt; 1744 cc->do_unaligned_access = arm_cpu_do_unaligned_access; 1745 cc->do_transaction_failed = arm_cpu_do_transaction_failed; 1746 cc->get_phys_page_attrs_debug = arm_cpu_get_phys_page_attrs_debug; 1747 cc->asidx_from_attrs = arm_asidx_from_attrs; 1748 cc->vmsd = &vmstate_arm_cpu; 1749 cc->virtio_is_big_endian = arm_cpu_virtio_is_big_endian; 1750 cc->write_elf64_note = arm_cpu_write_elf64_note; 1751 cc->write_elf32_note = arm_cpu_write_elf32_note; 1752 #endif 1753 cc->gdb_num_core_regs = 26; 1754 cc->gdb_core_xml_file = "arm-core.xml"; 1755 cc->gdb_arch_name = arm_gdb_arch_name; 1756 cc->gdb_stop_before_watchpoint = true; 1757 cc->debug_excp_handler = arm_debug_excp_handler; 1758 cc->debug_check_watchpoint = arm_debug_check_watchpoint; 1759 #if !defined(CONFIG_USER_ONLY) 1760 cc->adjust_watchpoint_address = arm_adjust_watchpoint_address; 1761 #endif 1762 1763 cc->disas_set_info = arm_disas_set_info; 1764 #ifdef CONFIG_TCG 1765 cc->tcg_initialize = arm_translate_init; 1766 #endif 1767 } 1768 1769 static void cpu_register(const ARMCPUInfo *info) 1770 { 1771 TypeInfo type_info = { 1772 .parent = TYPE_ARM_CPU, 1773 .instance_size = sizeof(ARMCPU), 1774 .instance_init = info->initfn, 1775 .class_size = sizeof(ARMCPUClass), 1776 .class_init = info->class_init, 1777 }; 1778 1779 type_info.name = g_strdup_printf("%s-" TYPE_ARM_CPU, info->name); 1780 type_register(&type_info); 1781 g_free((void *)type_info.name); 1782 } 1783 1784 static const TypeInfo arm_cpu_type_info = { 1785 .name = TYPE_ARM_CPU, 1786 .parent = TYPE_CPU, 1787 .instance_size = sizeof(ARMCPU), 1788 .instance_init = arm_cpu_initfn, 1789 .instance_post_init = arm_cpu_post_init, 1790 .instance_finalize = arm_cpu_finalizefn, 1791 .abstract = true, 1792 .class_size = sizeof(ARMCPUClass), 1793 .class_init = arm_cpu_class_init, 1794 }; 1795 1796 static void arm_cpu_register_types(void) 1797 { 1798 const ARMCPUInfo *info = arm_cpus; 1799 1800 type_register_static(&arm_cpu_type_info); 1801 1802 while (info->name) { 1803 cpu_register(info); 1804 info++; 1805 } 1806 } 1807 1808 type_init(arm_cpu_register_types) 1809