1 /* 2 * QEMU ARM CPU 3 * 4 * Copyright (c) 2012 SUSE LINUX Products GmbH 5 * 6 * This program is free software; you can redistribute it and/or 7 * modify it under the terms of the GNU General Public License 8 * as published by the Free Software Foundation; either version 2 9 * of the License, or (at your option) any later version. 10 * 11 * This program is distributed in the hope that it will be useful, 12 * but WITHOUT ANY WARRANTY; without even the implied warranty of 13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 14 * GNU General Public License for more details. 15 * 16 * You should have received a copy of the GNU General Public License 17 * along with this program; if not, see 18 * <http://www.gnu.org/licenses/gpl-2.0.html> 19 */ 20 21 #include "qemu/osdep.h" 22 #include "qemu/error-report.h" 23 #include "qapi/error.h" 24 #include "cpu.h" 25 #include "internals.h" 26 #include "qemu-common.h" 27 #include "exec/exec-all.h" 28 #include "hw/qdev-properties.h" 29 #if !defined(CONFIG_USER_ONLY) 30 #include "hw/loader.h" 31 #endif 32 #include "hw/arm/arm.h" 33 #include "sysemu/sysemu.h" 34 #include "sysemu/hw_accel.h" 35 #include "kvm_arm.h" 36 37 static void arm_cpu_set_pc(CPUState *cs, vaddr value) 38 { 39 ARMCPU *cpu = ARM_CPU(cs); 40 41 cpu->env.regs[15] = value; 42 } 43 44 static bool arm_cpu_has_work(CPUState *cs) 45 { 46 ARMCPU *cpu = ARM_CPU(cs); 47 48 return (cpu->power_state != PSCI_OFF) 49 && cs->interrupt_request & 50 (CPU_INTERRUPT_FIQ | CPU_INTERRUPT_HARD 51 | CPU_INTERRUPT_VFIQ | CPU_INTERRUPT_VIRQ 52 | CPU_INTERRUPT_EXITTB); 53 } 54 55 void arm_register_el_change_hook(ARMCPU *cpu, ARMELChangeHook *hook, 56 void *opaque) 57 { 58 /* We currently only support registering a single hook function */ 59 assert(!cpu->el_change_hook); 60 cpu->el_change_hook = hook; 61 cpu->el_change_hook_opaque = opaque; 62 } 63 64 static void cp_reg_reset(gpointer key, gpointer value, gpointer opaque) 65 { 66 /* Reset a single ARMCPRegInfo register */ 67 ARMCPRegInfo *ri = value; 68 ARMCPU *cpu = opaque; 69 70 if (ri->type & (ARM_CP_SPECIAL | ARM_CP_ALIAS)) { 71 return; 72 } 73 74 if (ri->resetfn) { 75 ri->resetfn(&cpu->env, ri); 76 return; 77 } 78 79 /* A zero offset is never possible as it would be regs[0] 80 * so we use it to indicate that reset is being handled elsewhere. 81 * This is basically only used for fields in non-core coprocessors 82 * (like the pxa2xx ones). 83 */ 84 if (!ri->fieldoffset) { 85 return; 86 } 87 88 if (cpreg_field_is_64bit(ri)) { 89 CPREG_FIELD64(&cpu->env, ri) = ri->resetvalue; 90 } else { 91 CPREG_FIELD32(&cpu->env, ri) = ri->resetvalue; 92 } 93 } 94 95 static void cp_reg_check_reset(gpointer key, gpointer value, gpointer opaque) 96 { 97 /* Purely an assertion check: we've already done reset once, 98 * so now check that running the reset for the cpreg doesn't 99 * change its value. This traps bugs where two different cpregs 100 * both try to reset the same state field but to different values. 101 */ 102 ARMCPRegInfo *ri = value; 103 ARMCPU *cpu = opaque; 104 uint64_t oldvalue, newvalue; 105 106 if (ri->type & (ARM_CP_SPECIAL | ARM_CP_ALIAS | ARM_CP_NO_RAW)) { 107 return; 108 } 109 110 oldvalue = read_raw_cp_reg(&cpu->env, ri); 111 cp_reg_reset(key, value, opaque); 112 newvalue = read_raw_cp_reg(&cpu->env, ri); 113 assert(oldvalue == newvalue); 114 } 115 116 /* CPUClass::reset() */ 117 static void arm_cpu_reset(CPUState *s) 118 { 119 ARMCPU *cpu = ARM_CPU(s); 120 ARMCPUClass *acc = ARM_CPU_GET_CLASS(cpu); 121 CPUARMState *env = &cpu->env; 122 123 acc->parent_reset(s); 124 125 memset(env, 0, offsetof(CPUARMState, end_reset_fields)); 126 127 g_hash_table_foreach(cpu->cp_regs, cp_reg_reset, cpu); 128 g_hash_table_foreach(cpu->cp_regs, cp_reg_check_reset, cpu); 129 130 env->vfp.xregs[ARM_VFP_FPSID] = cpu->reset_fpsid; 131 env->vfp.xregs[ARM_VFP_MVFR0] = cpu->mvfr0; 132 env->vfp.xregs[ARM_VFP_MVFR1] = cpu->mvfr1; 133 env->vfp.xregs[ARM_VFP_MVFR2] = cpu->mvfr2; 134 135 cpu->power_state = cpu->start_powered_off ? PSCI_OFF : PSCI_ON; 136 s->halted = cpu->start_powered_off; 137 138 if (arm_feature(env, ARM_FEATURE_IWMMXT)) { 139 env->iwmmxt.cregs[ARM_IWMMXT_wCID] = 0x69051000 | 'Q'; 140 } 141 142 if (arm_feature(env, ARM_FEATURE_AARCH64)) { 143 /* 64 bit CPUs always start in 64 bit mode */ 144 env->aarch64 = 1; 145 #if defined(CONFIG_USER_ONLY) 146 env->pstate = PSTATE_MODE_EL0t; 147 /* Userspace expects access to DC ZVA, CTL_EL0 and the cache ops */ 148 env->cp15.sctlr_el[1] |= SCTLR_UCT | SCTLR_UCI | SCTLR_DZE; 149 /* and to the FP/Neon instructions */ 150 env->cp15.cpacr_el1 = deposit64(env->cp15.cpacr_el1, 20, 2, 3); 151 #else 152 /* Reset into the highest available EL */ 153 if (arm_feature(env, ARM_FEATURE_EL3)) { 154 env->pstate = PSTATE_MODE_EL3h; 155 } else if (arm_feature(env, ARM_FEATURE_EL2)) { 156 env->pstate = PSTATE_MODE_EL2h; 157 } else { 158 env->pstate = PSTATE_MODE_EL1h; 159 } 160 env->pc = cpu->rvbar; 161 #endif 162 } else { 163 #if defined(CONFIG_USER_ONLY) 164 /* Userspace expects access to cp10 and cp11 for FP/Neon */ 165 env->cp15.cpacr_el1 = deposit64(env->cp15.cpacr_el1, 20, 4, 0xf); 166 #endif 167 } 168 169 #if defined(CONFIG_USER_ONLY) 170 env->uncached_cpsr = ARM_CPU_MODE_USR; 171 /* For user mode we must enable access to coprocessors */ 172 env->vfp.xregs[ARM_VFP_FPEXC] = 1 << 30; 173 if (arm_feature(env, ARM_FEATURE_IWMMXT)) { 174 env->cp15.c15_cpar = 3; 175 } else if (arm_feature(env, ARM_FEATURE_XSCALE)) { 176 env->cp15.c15_cpar = 1; 177 } 178 #else 179 /* SVC mode with interrupts disabled. */ 180 env->uncached_cpsr = ARM_CPU_MODE_SVC; 181 env->daif = PSTATE_D | PSTATE_A | PSTATE_I | PSTATE_F; 182 183 if (arm_feature(env, ARM_FEATURE_M)) { 184 uint32_t initial_msp; /* Loaded from 0x0 */ 185 uint32_t initial_pc; /* Loaded from 0x4 */ 186 uint8_t *rom; 187 188 if (arm_feature(env, ARM_FEATURE_M_SECURITY)) { 189 env->v7m.secure = true; 190 } 191 192 /* In v7M the reset value of this bit is IMPDEF, but ARM recommends 193 * that it resets to 1, so QEMU always does that rather than making 194 * it dependent on CPU model. In v8M it is RES1. 195 */ 196 env->v7m.ccr[M_REG_NS] = R_V7M_CCR_STKALIGN_MASK; 197 env->v7m.ccr[M_REG_S] = R_V7M_CCR_STKALIGN_MASK; 198 if (arm_feature(env, ARM_FEATURE_V8)) { 199 /* in v8M the NONBASETHRDENA bit [0] is RES1 */ 200 env->v7m.ccr[M_REG_NS] |= R_V7M_CCR_NONBASETHRDENA_MASK; 201 env->v7m.ccr[M_REG_S] |= R_V7M_CCR_NONBASETHRDENA_MASK; 202 } 203 204 /* Unlike A/R profile, M profile defines the reset LR value */ 205 env->regs[14] = 0xffffffff; 206 207 /* Load the initial SP and PC from the vector table at address 0 */ 208 rom = rom_ptr(0); 209 if (rom) { 210 /* Address zero is covered by ROM which hasn't yet been 211 * copied into physical memory. 212 */ 213 initial_msp = ldl_p(rom); 214 initial_pc = ldl_p(rom + 4); 215 } else { 216 /* Address zero not covered by a ROM blob, or the ROM blob 217 * is in non-modifiable memory and this is a second reset after 218 * it got copied into memory. In the latter case, rom_ptr 219 * will return a NULL pointer and we should use ldl_phys instead. 220 */ 221 initial_msp = ldl_phys(s->as, 0); 222 initial_pc = ldl_phys(s->as, 4); 223 } 224 225 env->regs[13] = initial_msp & 0xFFFFFFFC; 226 env->regs[15] = initial_pc & ~1; 227 env->thumb = initial_pc & 1; 228 } 229 230 /* AArch32 has a hard highvec setting of 0xFFFF0000. If we are currently 231 * executing as AArch32 then check if highvecs are enabled and 232 * adjust the PC accordingly. 233 */ 234 if (A32_BANKED_CURRENT_REG_GET(env, sctlr) & SCTLR_V) { 235 env->regs[15] = 0xFFFF0000; 236 } 237 238 env->vfp.xregs[ARM_VFP_FPEXC] = 0; 239 #endif 240 241 if (arm_feature(env, ARM_FEATURE_PMSA)) { 242 if (cpu->pmsav7_dregion > 0) { 243 if (arm_feature(env, ARM_FEATURE_V8)) { 244 memset(env->pmsav8.rbar[M_REG_NS], 0, 245 sizeof(*env->pmsav8.rbar[M_REG_NS]) 246 * cpu->pmsav7_dregion); 247 memset(env->pmsav8.rlar[M_REG_NS], 0, 248 sizeof(*env->pmsav8.rlar[M_REG_NS]) 249 * cpu->pmsav7_dregion); 250 if (arm_feature(env, ARM_FEATURE_M_SECURITY)) { 251 memset(env->pmsav8.rbar[M_REG_S], 0, 252 sizeof(*env->pmsav8.rbar[M_REG_S]) 253 * cpu->pmsav7_dregion); 254 memset(env->pmsav8.rlar[M_REG_S], 0, 255 sizeof(*env->pmsav8.rlar[M_REG_S]) 256 * cpu->pmsav7_dregion); 257 } 258 } else if (arm_feature(env, ARM_FEATURE_V7)) { 259 memset(env->pmsav7.drbar, 0, 260 sizeof(*env->pmsav7.drbar) * cpu->pmsav7_dregion); 261 memset(env->pmsav7.drsr, 0, 262 sizeof(*env->pmsav7.drsr) * cpu->pmsav7_dregion); 263 memset(env->pmsav7.dracr, 0, 264 sizeof(*env->pmsav7.dracr) * cpu->pmsav7_dregion); 265 } 266 } 267 env->pmsav7.rnr[M_REG_NS] = 0; 268 env->pmsav7.rnr[M_REG_S] = 0; 269 env->pmsav8.mair0[M_REG_NS] = 0; 270 env->pmsav8.mair0[M_REG_S] = 0; 271 env->pmsav8.mair1[M_REG_NS] = 0; 272 env->pmsav8.mair1[M_REG_S] = 0; 273 } 274 275 set_flush_to_zero(1, &env->vfp.standard_fp_status); 276 set_flush_inputs_to_zero(1, &env->vfp.standard_fp_status); 277 set_default_nan_mode(1, &env->vfp.standard_fp_status); 278 set_float_detect_tininess(float_tininess_before_rounding, 279 &env->vfp.fp_status); 280 set_float_detect_tininess(float_tininess_before_rounding, 281 &env->vfp.standard_fp_status); 282 #ifndef CONFIG_USER_ONLY 283 if (kvm_enabled()) { 284 kvm_arm_reset_vcpu(cpu); 285 } 286 #endif 287 288 hw_breakpoint_update_all(cpu); 289 hw_watchpoint_update_all(cpu); 290 } 291 292 bool arm_cpu_exec_interrupt(CPUState *cs, int interrupt_request) 293 { 294 CPUClass *cc = CPU_GET_CLASS(cs); 295 CPUARMState *env = cs->env_ptr; 296 uint32_t cur_el = arm_current_el(env); 297 bool secure = arm_is_secure(env); 298 uint32_t target_el; 299 uint32_t excp_idx; 300 bool ret = false; 301 302 if (interrupt_request & CPU_INTERRUPT_FIQ) { 303 excp_idx = EXCP_FIQ; 304 target_el = arm_phys_excp_target_el(cs, excp_idx, cur_el, secure); 305 if (arm_excp_unmasked(cs, excp_idx, target_el)) { 306 cs->exception_index = excp_idx; 307 env->exception.target_el = target_el; 308 cc->do_interrupt(cs); 309 ret = true; 310 } 311 } 312 if (interrupt_request & CPU_INTERRUPT_HARD) { 313 excp_idx = EXCP_IRQ; 314 target_el = arm_phys_excp_target_el(cs, excp_idx, cur_el, secure); 315 if (arm_excp_unmasked(cs, excp_idx, target_el)) { 316 cs->exception_index = excp_idx; 317 env->exception.target_el = target_el; 318 cc->do_interrupt(cs); 319 ret = true; 320 } 321 } 322 if (interrupt_request & CPU_INTERRUPT_VIRQ) { 323 excp_idx = EXCP_VIRQ; 324 target_el = 1; 325 if (arm_excp_unmasked(cs, excp_idx, target_el)) { 326 cs->exception_index = excp_idx; 327 env->exception.target_el = target_el; 328 cc->do_interrupt(cs); 329 ret = true; 330 } 331 } 332 if (interrupt_request & CPU_INTERRUPT_VFIQ) { 333 excp_idx = EXCP_VFIQ; 334 target_el = 1; 335 if (arm_excp_unmasked(cs, excp_idx, target_el)) { 336 cs->exception_index = excp_idx; 337 env->exception.target_el = target_el; 338 cc->do_interrupt(cs); 339 ret = true; 340 } 341 } 342 343 return ret; 344 } 345 346 #if !defined(CONFIG_USER_ONLY) || !defined(TARGET_AARCH64) 347 static bool arm_v7m_cpu_exec_interrupt(CPUState *cs, int interrupt_request) 348 { 349 CPUClass *cc = CPU_GET_CLASS(cs); 350 ARMCPU *cpu = ARM_CPU(cs); 351 CPUARMState *env = &cpu->env; 352 bool ret = false; 353 354 /* ARMv7-M interrupt masking works differently than -A or -R. 355 * There is no FIQ/IRQ distinction. Instead of I and F bits 356 * masking FIQ and IRQ interrupts, an exception is taken only 357 * if it is higher priority than the current execution priority 358 * (which depends on state like BASEPRI, FAULTMASK and the 359 * currently active exception). 360 */ 361 if (interrupt_request & CPU_INTERRUPT_HARD 362 && (armv7m_nvic_can_take_pending_exception(env->nvic))) { 363 cs->exception_index = EXCP_IRQ; 364 cc->do_interrupt(cs); 365 ret = true; 366 } 367 return ret; 368 } 369 #endif 370 371 #ifndef CONFIG_USER_ONLY 372 static void arm_cpu_set_irq(void *opaque, int irq, int level) 373 { 374 ARMCPU *cpu = opaque; 375 CPUARMState *env = &cpu->env; 376 CPUState *cs = CPU(cpu); 377 static const int mask[] = { 378 [ARM_CPU_IRQ] = CPU_INTERRUPT_HARD, 379 [ARM_CPU_FIQ] = CPU_INTERRUPT_FIQ, 380 [ARM_CPU_VIRQ] = CPU_INTERRUPT_VIRQ, 381 [ARM_CPU_VFIQ] = CPU_INTERRUPT_VFIQ 382 }; 383 384 switch (irq) { 385 case ARM_CPU_VIRQ: 386 case ARM_CPU_VFIQ: 387 assert(arm_feature(env, ARM_FEATURE_EL2)); 388 /* fall through */ 389 case ARM_CPU_IRQ: 390 case ARM_CPU_FIQ: 391 if (level) { 392 cpu_interrupt(cs, mask[irq]); 393 } else { 394 cpu_reset_interrupt(cs, mask[irq]); 395 } 396 break; 397 default: 398 g_assert_not_reached(); 399 } 400 } 401 402 static void arm_cpu_kvm_set_irq(void *opaque, int irq, int level) 403 { 404 #ifdef CONFIG_KVM 405 ARMCPU *cpu = opaque; 406 CPUState *cs = CPU(cpu); 407 int kvm_irq = KVM_ARM_IRQ_TYPE_CPU << KVM_ARM_IRQ_TYPE_SHIFT; 408 409 switch (irq) { 410 case ARM_CPU_IRQ: 411 kvm_irq |= KVM_ARM_IRQ_CPU_IRQ; 412 break; 413 case ARM_CPU_FIQ: 414 kvm_irq |= KVM_ARM_IRQ_CPU_FIQ; 415 break; 416 default: 417 g_assert_not_reached(); 418 } 419 kvm_irq |= cs->cpu_index << KVM_ARM_IRQ_VCPU_SHIFT; 420 kvm_set_irq(kvm_state, kvm_irq, level ? 1 : 0); 421 #endif 422 } 423 424 static bool arm_cpu_virtio_is_big_endian(CPUState *cs) 425 { 426 ARMCPU *cpu = ARM_CPU(cs); 427 CPUARMState *env = &cpu->env; 428 429 cpu_synchronize_state(cs); 430 return arm_cpu_data_is_big_endian(env); 431 } 432 433 #endif 434 435 static inline void set_feature(CPUARMState *env, int feature) 436 { 437 env->features |= 1ULL << feature; 438 } 439 440 static inline void unset_feature(CPUARMState *env, int feature) 441 { 442 env->features &= ~(1ULL << feature); 443 } 444 445 static int 446 print_insn_thumb1(bfd_vma pc, disassemble_info *info) 447 { 448 return print_insn_arm(pc | 1, info); 449 } 450 451 static int arm_read_memory_func(bfd_vma memaddr, bfd_byte *b, 452 int length, struct disassemble_info *info) 453 { 454 assert(info->read_memory_inner_func); 455 assert((info->flags & INSN_ARM_BE32) == 0 || length == 2 || length == 4); 456 457 if ((info->flags & INSN_ARM_BE32) != 0 && length == 2) { 458 assert(info->endian == BFD_ENDIAN_LITTLE); 459 return info->read_memory_inner_func(memaddr ^ 2, (bfd_byte *)b, 2, 460 info); 461 } else { 462 return info->read_memory_inner_func(memaddr, b, length, info); 463 } 464 } 465 466 static void arm_disas_set_info(CPUState *cpu, disassemble_info *info) 467 { 468 ARMCPU *ac = ARM_CPU(cpu); 469 CPUARMState *env = &ac->env; 470 471 if (is_a64(env)) { 472 /* We might not be compiled with the A64 disassembler 473 * because it needs a C++ compiler. Leave print_insn 474 * unset in this case to use the caller default behaviour. 475 */ 476 #if defined(CONFIG_ARM_A64_DIS) 477 info->print_insn = print_insn_arm_a64; 478 #endif 479 } else if (env->thumb) { 480 info->print_insn = print_insn_thumb1; 481 } else { 482 info->print_insn = print_insn_arm; 483 } 484 if (bswap_code(arm_sctlr_b(env))) { 485 #ifdef TARGET_WORDS_BIGENDIAN 486 info->endian = BFD_ENDIAN_LITTLE; 487 #else 488 info->endian = BFD_ENDIAN_BIG; 489 #endif 490 } 491 if (info->read_memory_inner_func == NULL) { 492 info->read_memory_inner_func = info->read_memory_func; 493 info->read_memory_func = arm_read_memory_func; 494 } 495 info->flags &= ~INSN_ARM_BE32; 496 if (arm_sctlr_b(env)) { 497 info->flags |= INSN_ARM_BE32; 498 } 499 } 500 501 uint64_t arm_cpu_mp_affinity(int idx, uint8_t clustersz) 502 { 503 uint32_t Aff1 = idx / clustersz; 504 uint32_t Aff0 = idx % clustersz; 505 return (Aff1 << ARM_AFF1_SHIFT) | Aff0; 506 } 507 508 static void arm_cpu_initfn(Object *obj) 509 { 510 CPUState *cs = CPU(obj); 511 ARMCPU *cpu = ARM_CPU(obj); 512 static bool inited; 513 514 cs->env_ptr = &cpu->env; 515 cpu->cp_regs = g_hash_table_new_full(g_int_hash, g_int_equal, 516 g_free, g_free); 517 518 #ifndef CONFIG_USER_ONLY 519 /* Our inbound IRQ and FIQ lines */ 520 if (kvm_enabled()) { 521 /* VIRQ and VFIQ are unused with KVM but we add them to maintain 522 * the same interface as non-KVM CPUs. 523 */ 524 qdev_init_gpio_in(DEVICE(cpu), arm_cpu_kvm_set_irq, 4); 525 } else { 526 qdev_init_gpio_in(DEVICE(cpu), arm_cpu_set_irq, 4); 527 } 528 529 cpu->gt_timer[GTIMER_PHYS] = timer_new(QEMU_CLOCK_VIRTUAL, GTIMER_SCALE, 530 arm_gt_ptimer_cb, cpu); 531 cpu->gt_timer[GTIMER_VIRT] = timer_new(QEMU_CLOCK_VIRTUAL, GTIMER_SCALE, 532 arm_gt_vtimer_cb, cpu); 533 cpu->gt_timer[GTIMER_HYP] = timer_new(QEMU_CLOCK_VIRTUAL, GTIMER_SCALE, 534 arm_gt_htimer_cb, cpu); 535 cpu->gt_timer[GTIMER_SEC] = timer_new(QEMU_CLOCK_VIRTUAL, GTIMER_SCALE, 536 arm_gt_stimer_cb, cpu); 537 qdev_init_gpio_out(DEVICE(cpu), cpu->gt_timer_outputs, 538 ARRAY_SIZE(cpu->gt_timer_outputs)); 539 540 qdev_init_gpio_out_named(DEVICE(cpu), &cpu->gicv3_maintenance_interrupt, 541 "gicv3-maintenance-interrupt", 1); 542 qdev_init_gpio_out_named(DEVICE(cpu), &cpu->pmu_interrupt, 543 "pmu-interrupt", 1); 544 #endif 545 546 /* DTB consumers generally don't in fact care what the 'compatible' 547 * string is, so always provide some string and trust that a hypothetical 548 * picky DTB consumer will also provide a helpful error message. 549 */ 550 cpu->dtb_compatible = "qemu,unknown"; 551 cpu->psci_version = 1; /* By default assume PSCI v0.1 */ 552 cpu->kvm_target = QEMU_KVM_ARM_TARGET_NONE; 553 554 if (tcg_enabled()) { 555 cpu->psci_version = 2; /* TCG implements PSCI 0.2 */ 556 if (!inited) { 557 inited = true; 558 arm_translate_init(); 559 } 560 } 561 } 562 563 static Property arm_cpu_reset_cbar_property = 564 DEFINE_PROP_UINT64("reset-cbar", ARMCPU, reset_cbar, 0); 565 566 static Property arm_cpu_reset_hivecs_property = 567 DEFINE_PROP_BOOL("reset-hivecs", ARMCPU, reset_hivecs, false); 568 569 static Property arm_cpu_rvbar_property = 570 DEFINE_PROP_UINT64("rvbar", ARMCPU, rvbar, 0); 571 572 static Property arm_cpu_has_el2_property = 573 DEFINE_PROP_BOOL("has_el2", ARMCPU, has_el2, true); 574 575 static Property arm_cpu_has_el3_property = 576 DEFINE_PROP_BOOL("has_el3", ARMCPU, has_el3, true); 577 578 static Property arm_cpu_cfgend_property = 579 DEFINE_PROP_BOOL("cfgend", ARMCPU, cfgend, false); 580 581 /* use property name "pmu" to match other archs and virt tools */ 582 static Property arm_cpu_has_pmu_property = 583 DEFINE_PROP_BOOL("pmu", ARMCPU, has_pmu, true); 584 585 static Property arm_cpu_has_mpu_property = 586 DEFINE_PROP_BOOL("has-mpu", ARMCPU, has_mpu, true); 587 588 /* This is like DEFINE_PROP_UINT32 but it doesn't set the default value, 589 * because the CPU initfn will have already set cpu->pmsav7_dregion to 590 * the right value for that particular CPU type, and we don't want 591 * to override that with an incorrect constant value. 592 */ 593 static Property arm_cpu_pmsav7_dregion_property = 594 DEFINE_PROP_UNSIGNED_NODEFAULT("pmsav7-dregion", ARMCPU, 595 pmsav7_dregion, 596 qdev_prop_uint32, uint32_t); 597 598 static void arm_cpu_post_init(Object *obj) 599 { 600 ARMCPU *cpu = ARM_CPU(obj); 601 602 /* M profile implies PMSA. We have to do this here rather than 603 * in realize with the other feature-implication checks because 604 * we look at the PMSA bit to see if we should add some properties. 605 */ 606 if (arm_feature(&cpu->env, ARM_FEATURE_M)) { 607 set_feature(&cpu->env, ARM_FEATURE_PMSA); 608 } 609 610 if (arm_feature(&cpu->env, ARM_FEATURE_CBAR) || 611 arm_feature(&cpu->env, ARM_FEATURE_CBAR_RO)) { 612 qdev_property_add_static(DEVICE(obj), &arm_cpu_reset_cbar_property, 613 &error_abort); 614 } 615 616 if (!arm_feature(&cpu->env, ARM_FEATURE_M)) { 617 qdev_property_add_static(DEVICE(obj), &arm_cpu_reset_hivecs_property, 618 &error_abort); 619 } 620 621 if (arm_feature(&cpu->env, ARM_FEATURE_AARCH64)) { 622 qdev_property_add_static(DEVICE(obj), &arm_cpu_rvbar_property, 623 &error_abort); 624 } 625 626 if (arm_feature(&cpu->env, ARM_FEATURE_EL3)) { 627 /* Add the has_el3 state CPU property only if EL3 is allowed. This will 628 * prevent "has_el3" from existing on CPUs which cannot support EL3. 629 */ 630 qdev_property_add_static(DEVICE(obj), &arm_cpu_has_el3_property, 631 &error_abort); 632 633 #ifndef CONFIG_USER_ONLY 634 object_property_add_link(obj, "secure-memory", 635 TYPE_MEMORY_REGION, 636 (Object **)&cpu->secure_memory, 637 qdev_prop_allow_set_link_before_realize, 638 OBJ_PROP_LINK_UNREF_ON_RELEASE, 639 &error_abort); 640 #endif 641 } 642 643 if (arm_feature(&cpu->env, ARM_FEATURE_EL2)) { 644 qdev_property_add_static(DEVICE(obj), &arm_cpu_has_el2_property, 645 &error_abort); 646 } 647 648 if (arm_feature(&cpu->env, ARM_FEATURE_PMU)) { 649 qdev_property_add_static(DEVICE(obj), &arm_cpu_has_pmu_property, 650 &error_abort); 651 } 652 653 if (arm_feature(&cpu->env, ARM_FEATURE_PMSA)) { 654 qdev_property_add_static(DEVICE(obj), &arm_cpu_has_mpu_property, 655 &error_abort); 656 if (arm_feature(&cpu->env, ARM_FEATURE_V7)) { 657 qdev_property_add_static(DEVICE(obj), 658 &arm_cpu_pmsav7_dregion_property, 659 &error_abort); 660 } 661 } 662 663 qdev_property_add_static(DEVICE(obj), &arm_cpu_cfgend_property, 664 &error_abort); 665 } 666 667 static void arm_cpu_finalizefn(Object *obj) 668 { 669 ARMCPU *cpu = ARM_CPU(obj); 670 g_hash_table_destroy(cpu->cp_regs); 671 } 672 673 static void arm_cpu_realizefn(DeviceState *dev, Error **errp) 674 { 675 CPUState *cs = CPU(dev); 676 ARMCPU *cpu = ARM_CPU(dev); 677 ARMCPUClass *acc = ARM_CPU_GET_CLASS(dev); 678 CPUARMState *env = &cpu->env; 679 int pagebits; 680 Error *local_err = NULL; 681 682 cpu_exec_realizefn(cs, &local_err); 683 if (local_err != NULL) { 684 error_propagate(errp, local_err); 685 return; 686 } 687 688 /* Some features automatically imply others: */ 689 if (arm_feature(env, ARM_FEATURE_V8)) { 690 set_feature(env, ARM_FEATURE_V7); 691 set_feature(env, ARM_FEATURE_ARM_DIV); 692 set_feature(env, ARM_FEATURE_LPAE); 693 } 694 if (arm_feature(env, ARM_FEATURE_V7)) { 695 set_feature(env, ARM_FEATURE_VAPA); 696 set_feature(env, ARM_FEATURE_THUMB2); 697 set_feature(env, ARM_FEATURE_MPIDR); 698 if (!arm_feature(env, ARM_FEATURE_M)) { 699 set_feature(env, ARM_FEATURE_V6K); 700 } else { 701 set_feature(env, ARM_FEATURE_V6); 702 } 703 704 /* Always define VBAR for V7 CPUs even if it doesn't exist in 705 * non-EL3 configs. This is needed by some legacy boards. 706 */ 707 set_feature(env, ARM_FEATURE_VBAR); 708 } 709 if (arm_feature(env, ARM_FEATURE_V6K)) { 710 set_feature(env, ARM_FEATURE_V6); 711 set_feature(env, ARM_FEATURE_MVFR); 712 } 713 if (arm_feature(env, ARM_FEATURE_V6)) { 714 set_feature(env, ARM_FEATURE_V5); 715 set_feature(env, ARM_FEATURE_JAZELLE); 716 if (!arm_feature(env, ARM_FEATURE_M)) { 717 set_feature(env, ARM_FEATURE_AUXCR); 718 } 719 } 720 if (arm_feature(env, ARM_FEATURE_V5)) { 721 set_feature(env, ARM_FEATURE_V4T); 722 } 723 if (arm_feature(env, ARM_FEATURE_M)) { 724 set_feature(env, ARM_FEATURE_THUMB_DIV); 725 } 726 if (arm_feature(env, ARM_FEATURE_ARM_DIV)) { 727 set_feature(env, ARM_FEATURE_THUMB_DIV); 728 } 729 if (arm_feature(env, ARM_FEATURE_VFP4)) { 730 set_feature(env, ARM_FEATURE_VFP3); 731 set_feature(env, ARM_FEATURE_VFP_FP16); 732 } 733 if (arm_feature(env, ARM_FEATURE_VFP3)) { 734 set_feature(env, ARM_FEATURE_VFP); 735 } 736 if (arm_feature(env, ARM_FEATURE_LPAE)) { 737 set_feature(env, ARM_FEATURE_V7MP); 738 set_feature(env, ARM_FEATURE_PXN); 739 } 740 if (arm_feature(env, ARM_FEATURE_CBAR_RO)) { 741 set_feature(env, ARM_FEATURE_CBAR); 742 } 743 if (arm_feature(env, ARM_FEATURE_THUMB2) && 744 !arm_feature(env, ARM_FEATURE_M)) { 745 set_feature(env, ARM_FEATURE_THUMB_DSP); 746 } 747 748 if (arm_feature(env, ARM_FEATURE_V7) && 749 !arm_feature(env, ARM_FEATURE_M) && 750 !arm_feature(env, ARM_FEATURE_PMSA)) { 751 /* v7VMSA drops support for the old ARMv5 tiny pages, so we 752 * can use 4K pages. 753 */ 754 pagebits = 12; 755 } else { 756 /* For CPUs which might have tiny 1K pages, or which have an 757 * MPU and might have small region sizes, stick with 1K pages. 758 */ 759 pagebits = 10; 760 } 761 if (!set_preferred_target_page_bits(pagebits)) { 762 /* This can only ever happen for hotplugging a CPU, or if 763 * the board code incorrectly creates a CPU which it has 764 * promised via minimum_page_size that it will not. 765 */ 766 error_setg(errp, "This CPU requires a smaller page size than the " 767 "system is using"); 768 return; 769 } 770 771 /* This cpu-id-to-MPIDR affinity is used only for TCG; KVM will override it. 772 * We don't support setting cluster ID ([16..23]) (known as Aff2 773 * in later ARM ARM versions), or any of the higher affinity level fields, 774 * so these bits always RAZ. 775 */ 776 if (cpu->mp_affinity == ARM64_AFFINITY_INVALID) { 777 cpu->mp_affinity = arm_cpu_mp_affinity(cs->cpu_index, 778 ARM_DEFAULT_CPUS_PER_CLUSTER); 779 } 780 781 if (cpu->reset_hivecs) { 782 cpu->reset_sctlr |= (1 << 13); 783 } 784 785 if (cpu->cfgend) { 786 if (arm_feature(&cpu->env, ARM_FEATURE_V7)) { 787 cpu->reset_sctlr |= SCTLR_EE; 788 } else { 789 cpu->reset_sctlr |= SCTLR_B; 790 } 791 } 792 793 if (!cpu->has_el3) { 794 /* If the has_el3 CPU property is disabled then we need to disable the 795 * feature. 796 */ 797 unset_feature(env, ARM_FEATURE_EL3); 798 799 /* Disable the security extension feature bits in the processor feature 800 * registers as well. These are id_pfr1[7:4] and id_aa64pfr0[15:12]. 801 */ 802 cpu->id_pfr1 &= ~0xf0; 803 cpu->id_aa64pfr0 &= ~0xf000; 804 } 805 806 if (!cpu->has_el2) { 807 unset_feature(env, ARM_FEATURE_EL2); 808 } 809 810 if (!cpu->has_pmu) { 811 unset_feature(env, ARM_FEATURE_PMU); 812 cpu->id_aa64dfr0 &= ~0xf00; 813 } 814 815 if (!arm_feature(env, ARM_FEATURE_EL2)) { 816 /* Disable the hypervisor feature bits in the processor feature 817 * registers if we don't have EL2. These are id_pfr1[15:12] and 818 * id_aa64pfr0_el1[11:8]. 819 */ 820 cpu->id_aa64pfr0 &= ~0xf00; 821 cpu->id_pfr1 &= ~0xf000; 822 } 823 824 /* MPU can be configured out of a PMSA CPU either by setting has-mpu 825 * to false or by setting pmsav7-dregion to 0. 826 */ 827 if (!cpu->has_mpu) { 828 cpu->pmsav7_dregion = 0; 829 } 830 if (cpu->pmsav7_dregion == 0) { 831 cpu->has_mpu = false; 832 } 833 834 if (arm_feature(env, ARM_FEATURE_PMSA) && 835 arm_feature(env, ARM_FEATURE_V7)) { 836 uint32_t nr = cpu->pmsav7_dregion; 837 838 if (nr > 0xff) { 839 error_setg(errp, "PMSAv7 MPU #regions invalid %" PRIu32, nr); 840 return; 841 } 842 843 if (nr) { 844 if (arm_feature(env, ARM_FEATURE_V8)) { 845 /* PMSAv8 */ 846 env->pmsav8.rbar[M_REG_NS] = g_new0(uint32_t, nr); 847 env->pmsav8.rlar[M_REG_NS] = g_new0(uint32_t, nr); 848 if (arm_feature(env, ARM_FEATURE_M_SECURITY)) { 849 env->pmsav8.rbar[M_REG_S] = g_new0(uint32_t, nr); 850 env->pmsav8.rlar[M_REG_S] = g_new0(uint32_t, nr); 851 } 852 } else { 853 env->pmsav7.drbar = g_new0(uint32_t, nr); 854 env->pmsav7.drsr = g_new0(uint32_t, nr); 855 env->pmsav7.dracr = g_new0(uint32_t, nr); 856 } 857 } 858 } 859 860 if (arm_feature(env, ARM_FEATURE_EL3)) { 861 set_feature(env, ARM_FEATURE_VBAR); 862 } 863 864 register_cp_regs_for_features(cpu); 865 arm_cpu_register_gdb_regs_for_features(cpu); 866 867 init_cpreg_list(cpu); 868 869 #ifndef CONFIG_USER_ONLY 870 if (cpu->has_el3 || arm_feature(env, ARM_FEATURE_M_SECURITY)) { 871 AddressSpace *as; 872 873 cs->num_ases = 2; 874 875 if (!cpu->secure_memory) { 876 cpu->secure_memory = cs->memory; 877 } 878 as = address_space_init_shareable(cpu->secure_memory, 879 "cpu-secure-memory"); 880 cpu_address_space_init(cs, as, ARMASIdx_S); 881 } else { 882 cs->num_ases = 1; 883 } 884 885 cpu_address_space_init(cs, 886 address_space_init_shareable(cs->memory, 887 "cpu-memory"), 888 ARMASIdx_NS); 889 #endif 890 891 qemu_init_vcpu(cs); 892 cpu_reset(cs); 893 894 acc->parent_realize(dev, errp); 895 } 896 897 static ObjectClass *arm_cpu_class_by_name(const char *cpu_model) 898 { 899 ObjectClass *oc; 900 char *typename; 901 char **cpuname; 902 903 if (!cpu_model) { 904 return NULL; 905 } 906 907 cpuname = g_strsplit(cpu_model, ",", 1); 908 typename = g_strdup_printf("%s-" TYPE_ARM_CPU, cpuname[0]); 909 oc = object_class_by_name(typename); 910 g_strfreev(cpuname); 911 g_free(typename); 912 if (!oc || !object_class_dynamic_cast(oc, TYPE_ARM_CPU) || 913 object_class_is_abstract(oc)) { 914 return NULL; 915 } 916 return oc; 917 } 918 919 /* CPU models. These are not needed for the AArch64 linux-user build. */ 920 #if !defined(CONFIG_USER_ONLY) || !defined(TARGET_AARCH64) 921 922 static void arm926_initfn(Object *obj) 923 { 924 ARMCPU *cpu = ARM_CPU(obj); 925 926 cpu->dtb_compatible = "arm,arm926"; 927 set_feature(&cpu->env, ARM_FEATURE_V5); 928 set_feature(&cpu->env, ARM_FEATURE_VFP); 929 set_feature(&cpu->env, ARM_FEATURE_DUMMY_C15_REGS); 930 set_feature(&cpu->env, ARM_FEATURE_CACHE_TEST_CLEAN); 931 set_feature(&cpu->env, ARM_FEATURE_JAZELLE); 932 cpu->midr = 0x41069265; 933 cpu->reset_fpsid = 0x41011090; 934 cpu->ctr = 0x1dd20d2; 935 cpu->reset_sctlr = 0x00090078; 936 } 937 938 static void arm946_initfn(Object *obj) 939 { 940 ARMCPU *cpu = ARM_CPU(obj); 941 942 cpu->dtb_compatible = "arm,arm946"; 943 set_feature(&cpu->env, ARM_FEATURE_V5); 944 set_feature(&cpu->env, ARM_FEATURE_PMSA); 945 set_feature(&cpu->env, ARM_FEATURE_DUMMY_C15_REGS); 946 cpu->midr = 0x41059461; 947 cpu->ctr = 0x0f004006; 948 cpu->reset_sctlr = 0x00000078; 949 } 950 951 static void arm1026_initfn(Object *obj) 952 { 953 ARMCPU *cpu = ARM_CPU(obj); 954 955 cpu->dtb_compatible = "arm,arm1026"; 956 set_feature(&cpu->env, ARM_FEATURE_V5); 957 set_feature(&cpu->env, ARM_FEATURE_VFP); 958 set_feature(&cpu->env, ARM_FEATURE_AUXCR); 959 set_feature(&cpu->env, ARM_FEATURE_DUMMY_C15_REGS); 960 set_feature(&cpu->env, ARM_FEATURE_CACHE_TEST_CLEAN); 961 set_feature(&cpu->env, ARM_FEATURE_JAZELLE); 962 cpu->midr = 0x4106a262; 963 cpu->reset_fpsid = 0x410110a0; 964 cpu->ctr = 0x1dd20d2; 965 cpu->reset_sctlr = 0x00090078; 966 cpu->reset_auxcr = 1; 967 { 968 /* The 1026 had an IFAR at c6,c0,0,1 rather than the ARMv6 c6,c0,0,2 */ 969 ARMCPRegInfo ifar = { 970 .name = "IFAR", .cp = 15, .crn = 6, .crm = 0, .opc1 = 0, .opc2 = 1, 971 .access = PL1_RW, 972 .fieldoffset = offsetof(CPUARMState, cp15.ifar_ns), 973 .resetvalue = 0 974 }; 975 define_one_arm_cp_reg(cpu, &ifar); 976 } 977 } 978 979 static void arm1136_r2_initfn(Object *obj) 980 { 981 ARMCPU *cpu = ARM_CPU(obj); 982 /* What qemu calls "arm1136_r2" is actually the 1136 r0p2, ie an 983 * older core than plain "arm1136". In particular this does not 984 * have the v6K features. 985 * These ID register values are correct for 1136 but may be wrong 986 * for 1136_r2 (in particular r0p2 does not actually implement most 987 * of the ID registers). 988 */ 989 990 cpu->dtb_compatible = "arm,arm1136"; 991 set_feature(&cpu->env, ARM_FEATURE_V6); 992 set_feature(&cpu->env, ARM_FEATURE_VFP); 993 set_feature(&cpu->env, ARM_FEATURE_DUMMY_C15_REGS); 994 set_feature(&cpu->env, ARM_FEATURE_CACHE_DIRTY_REG); 995 set_feature(&cpu->env, ARM_FEATURE_CACHE_BLOCK_OPS); 996 cpu->midr = 0x4107b362; 997 cpu->reset_fpsid = 0x410120b4; 998 cpu->mvfr0 = 0x11111111; 999 cpu->mvfr1 = 0x00000000; 1000 cpu->ctr = 0x1dd20d2; 1001 cpu->reset_sctlr = 0x00050078; 1002 cpu->id_pfr0 = 0x111; 1003 cpu->id_pfr1 = 0x1; 1004 cpu->id_dfr0 = 0x2; 1005 cpu->id_afr0 = 0x3; 1006 cpu->id_mmfr0 = 0x01130003; 1007 cpu->id_mmfr1 = 0x10030302; 1008 cpu->id_mmfr2 = 0x01222110; 1009 cpu->id_isar0 = 0x00140011; 1010 cpu->id_isar1 = 0x12002111; 1011 cpu->id_isar2 = 0x11231111; 1012 cpu->id_isar3 = 0x01102131; 1013 cpu->id_isar4 = 0x141; 1014 cpu->reset_auxcr = 7; 1015 } 1016 1017 static void arm1136_initfn(Object *obj) 1018 { 1019 ARMCPU *cpu = ARM_CPU(obj); 1020 1021 cpu->dtb_compatible = "arm,arm1136"; 1022 set_feature(&cpu->env, ARM_FEATURE_V6K); 1023 set_feature(&cpu->env, ARM_FEATURE_V6); 1024 set_feature(&cpu->env, ARM_FEATURE_VFP); 1025 set_feature(&cpu->env, ARM_FEATURE_DUMMY_C15_REGS); 1026 set_feature(&cpu->env, ARM_FEATURE_CACHE_DIRTY_REG); 1027 set_feature(&cpu->env, ARM_FEATURE_CACHE_BLOCK_OPS); 1028 cpu->midr = 0x4117b363; 1029 cpu->reset_fpsid = 0x410120b4; 1030 cpu->mvfr0 = 0x11111111; 1031 cpu->mvfr1 = 0x00000000; 1032 cpu->ctr = 0x1dd20d2; 1033 cpu->reset_sctlr = 0x00050078; 1034 cpu->id_pfr0 = 0x111; 1035 cpu->id_pfr1 = 0x1; 1036 cpu->id_dfr0 = 0x2; 1037 cpu->id_afr0 = 0x3; 1038 cpu->id_mmfr0 = 0x01130003; 1039 cpu->id_mmfr1 = 0x10030302; 1040 cpu->id_mmfr2 = 0x01222110; 1041 cpu->id_isar0 = 0x00140011; 1042 cpu->id_isar1 = 0x12002111; 1043 cpu->id_isar2 = 0x11231111; 1044 cpu->id_isar3 = 0x01102131; 1045 cpu->id_isar4 = 0x141; 1046 cpu->reset_auxcr = 7; 1047 } 1048 1049 static void arm1176_initfn(Object *obj) 1050 { 1051 ARMCPU *cpu = ARM_CPU(obj); 1052 1053 cpu->dtb_compatible = "arm,arm1176"; 1054 set_feature(&cpu->env, ARM_FEATURE_V6K); 1055 set_feature(&cpu->env, ARM_FEATURE_VFP); 1056 set_feature(&cpu->env, ARM_FEATURE_VAPA); 1057 set_feature(&cpu->env, ARM_FEATURE_DUMMY_C15_REGS); 1058 set_feature(&cpu->env, ARM_FEATURE_CACHE_DIRTY_REG); 1059 set_feature(&cpu->env, ARM_FEATURE_CACHE_BLOCK_OPS); 1060 set_feature(&cpu->env, ARM_FEATURE_EL3); 1061 cpu->midr = 0x410fb767; 1062 cpu->reset_fpsid = 0x410120b5; 1063 cpu->mvfr0 = 0x11111111; 1064 cpu->mvfr1 = 0x00000000; 1065 cpu->ctr = 0x1dd20d2; 1066 cpu->reset_sctlr = 0x00050078; 1067 cpu->id_pfr0 = 0x111; 1068 cpu->id_pfr1 = 0x11; 1069 cpu->id_dfr0 = 0x33; 1070 cpu->id_afr0 = 0; 1071 cpu->id_mmfr0 = 0x01130003; 1072 cpu->id_mmfr1 = 0x10030302; 1073 cpu->id_mmfr2 = 0x01222100; 1074 cpu->id_isar0 = 0x0140011; 1075 cpu->id_isar1 = 0x12002111; 1076 cpu->id_isar2 = 0x11231121; 1077 cpu->id_isar3 = 0x01102131; 1078 cpu->id_isar4 = 0x01141; 1079 cpu->reset_auxcr = 7; 1080 } 1081 1082 static void arm11mpcore_initfn(Object *obj) 1083 { 1084 ARMCPU *cpu = ARM_CPU(obj); 1085 1086 cpu->dtb_compatible = "arm,arm11mpcore"; 1087 set_feature(&cpu->env, ARM_FEATURE_V6K); 1088 set_feature(&cpu->env, ARM_FEATURE_VFP); 1089 set_feature(&cpu->env, ARM_FEATURE_VAPA); 1090 set_feature(&cpu->env, ARM_FEATURE_MPIDR); 1091 set_feature(&cpu->env, ARM_FEATURE_DUMMY_C15_REGS); 1092 cpu->midr = 0x410fb022; 1093 cpu->reset_fpsid = 0x410120b4; 1094 cpu->mvfr0 = 0x11111111; 1095 cpu->mvfr1 = 0x00000000; 1096 cpu->ctr = 0x1d192992; /* 32K icache 32K dcache */ 1097 cpu->id_pfr0 = 0x111; 1098 cpu->id_pfr1 = 0x1; 1099 cpu->id_dfr0 = 0; 1100 cpu->id_afr0 = 0x2; 1101 cpu->id_mmfr0 = 0x01100103; 1102 cpu->id_mmfr1 = 0x10020302; 1103 cpu->id_mmfr2 = 0x01222000; 1104 cpu->id_isar0 = 0x00100011; 1105 cpu->id_isar1 = 0x12002111; 1106 cpu->id_isar2 = 0x11221011; 1107 cpu->id_isar3 = 0x01102131; 1108 cpu->id_isar4 = 0x141; 1109 cpu->reset_auxcr = 1; 1110 } 1111 1112 static void cortex_m3_initfn(Object *obj) 1113 { 1114 ARMCPU *cpu = ARM_CPU(obj); 1115 set_feature(&cpu->env, ARM_FEATURE_V7); 1116 set_feature(&cpu->env, ARM_FEATURE_M); 1117 cpu->midr = 0x410fc231; 1118 cpu->pmsav7_dregion = 8; 1119 } 1120 1121 static void cortex_m4_initfn(Object *obj) 1122 { 1123 ARMCPU *cpu = ARM_CPU(obj); 1124 1125 set_feature(&cpu->env, ARM_FEATURE_V7); 1126 set_feature(&cpu->env, ARM_FEATURE_M); 1127 set_feature(&cpu->env, ARM_FEATURE_THUMB_DSP); 1128 cpu->midr = 0x410fc240; /* r0p0 */ 1129 cpu->pmsav7_dregion = 8; 1130 } 1131 static void arm_v7m_class_init(ObjectClass *oc, void *data) 1132 { 1133 CPUClass *cc = CPU_CLASS(oc); 1134 1135 #ifndef CONFIG_USER_ONLY 1136 cc->do_interrupt = arm_v7m_cpu_do_interrupt; 1137 #endif 1138 1139 cc->cpu_exec_interrupt = arm_v7m_cpu_exec_interrupt; 1140 } 1141 1142 static const ARMCPRegInfo cortexr5_cp_reginfo[] = { 1143 /* Dummy the TCM region regs for the moment */ 1144 { .name = "ATCM", .cp = 15, .opc1 = 0, .crn = 9, .crm = 1, .opc2 = 0, 1145 .access = PL1_RW, .type = ARM_CP_CONST }, 1146 { .name = "BTCM", .cp = 15, .opc1 = 0, .crn = 9, .crm = 1, .opc2 = 1, 1147 .access = PL1_RW, .type = ARM_CP_CONST }, 1148 { .name = "DCACHE_INVAL", .cp = 15, .opc1 = 0, .crn = 15, .crm = 5, 1149 .opc2 = 0, .access = PL1_W, .type = ARM_CP_NOP }, 1150 REGINFO_SENTINEL 1151 }; 1152 1153 static void cortex_r5_initfn(Object *obj) 1154 { 1155 ARMCPU *cpu = ARM_CPU(obj); 1156 1157 set_feature(&cpu->env, ARM_FEATURE_V7); 1158 set_feature(&cpu->env, ARM_FEATURE_THUMB_DIV); 1159 set_feature(&cpu->env, ARM_FEATURE_ARM_DIV); 1160 set_feature(&cpu->env, ARM_FEATURE_V7MP); 1161 set_feature(&cpu->env, ARM_FEATURE_PMSA); 1162 cpu->midr = 0x411fc153; /* r1p3 */ 1163 cpu->id_pfr0 = 0x0131; 1164 cpu->id_pfr1 = 0x001; 1165 cpu->id_dfr0 = 0x010400; 1166 cpu->id_afr0 = 0x0; 1167 cpu->id_mmfr0 = 0x0210030; 1168 cpu->id_mmfr1 = 0x00000000; 1169 cpu->id_mmfr2 = 0x01200000; 1170 cpu->id_mmfr3 = 0x0211; 1171 cpu->id_isar0 = 0x2101111; 1172 cpu->id_isar1 = 0x13112111; 1173 cpu->id_isar2 = 0x21232141; 1174 cpu->id_isar3 = 0x01112131; 1175 cpu->id_isar4 = 0x0010142; 1176 cpu->id_isar5 = 0x0; 1177 cpu->mp_is_up = true; 1178 cpu->pmsav7_dregion = 16; 1179 define_arm_cp_regs(cpu, cortexr5_cp_reginfo); 1180 } 1181 1182 static const ARMCPRegInfo cortexa8_cp_reginfo[] = { 1183 { .name = "L2LOCKDOWN", .cp = 15, .crn = 9, .crm = 0, .opc1 = 1, .opc2 = 0, 1184 .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0 }, 1185 { .name = "L2AUXCR", .cp = 15, .crn = 9, .crm = 0, .opc1 = 1, .opc2 = 2, 1186 .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0 }, 1187 REGINFO_SENTINEL 1188 }; 1189 1190 static void cortex_a8_initfn(Object *obj) 1191 { 1192 ARMCPU *cpu = ARM_CPU(obj); 1193 1194 cpu->dtb_compatible = "arm,cortex-a8"; 1195 set_feature(&cpu->env, ARM_FEATURE_V7); 1196 set_feature(&cpu->env, ARM_FEATURE_VFP3); 1197 set_feature(&cpu->env, ARM_FEATURE_NEON); 1198 set_feature(&cpu->env, ARM_FEATURE_THUMB2EE); 1199 set_feature(&cpu->env, ARM_FEATURE_DUMMY_C15_REGS); 1200 set_feature(&cpu->env, ARM_FEATURE_EL3); 1201 cpu->midr = 0x410fc080; 1202 cpu->reset_fpsid = 0x410330c0; 1203 cpu->mvfr0 = 0x11110222; 1204 cpu->mvfr1 = 0x00011111; 1205 cpu->ctr = 0x82048004; 1206 cpu->reset_sctlr = 0x00c50078; 1207 cpu->id_pfr0 = 0x1031; 1208 cpu->id_pfr1 = 0x11; 1209 cpu->id_dfr0 = 0x400; 1210 cpu->id_afr0 = 0; 1211 cpu->id_mmfr0 = 0x31100003; 1212 cpu->id_mmfr1 = 0x20000000; 1213 cpu->id_mmfr2 = 0x01202000; 1214 cpu->id_mmfr3 = 0x11; 1215 cpu->id_isar0 = 0x00101111; 1216 cpu->id_isar1 = 0x12112111; 1217 cpu->id_isar2 = 0x21232031; 1218 cpu->id_isar3 = 0x11112131; 1219 cpu->id_isar4 = 0x00111142; 1220 cpu->dbgdidr = 0x15141000; 1221 cpu->clidr = (1 << 27) | (2 << 24) | 3; 1222 cpu->ccsidr[0] = 0xe007e01a; /* 16k L1 dcache. */ 1223 cpu->ccsidr[1] = 0x2007e01a; /* 16k L1 icache. */ 1224 cpu->ccsidr[2] = 0xf0000000; /* No L2 icache. */ 1225 cpu->reset_auxcr = 2; 1226 define_arm_cp_regs(cpu, cortexa8_cp_reginfo); 1227 } 1228 1229 static const ARMCPRegInfo cortexa9_cp_reginfo[] = { 1230 /* power_control should be set to maximum latency. Again, 1231 * default to 0 and set by private hook 1232 */ 1233 { .name = "A9_PWRCTL", .cp = 15, .crn = 15, .crm = 0, .opc1 = 0, .opc2 = 0, 1234 .access = PL1_RW, .resetvalue = 0, 1235 .fieldoffset = offsetof(CPUARMState, cp15.c15_power_control) }, 1236 { .name = "A9_DIAG", .cp = 15, .crn = 15, .crm = 0, .opc1 = 0, .opc2 = 1, 1237 .access = PL1_RW, .resetvalue = 0, 1238 .fieldoffset = offsetof(CPUARMState, cp15.c15_diagnostic) }, 1239 { .name = "A9_PWRDIAG", .cp = 15, .crn = 15, .crm = 0, .opc1 = 0, .opc2 = 2, 1240 .access = PL1_RW, .resetvalue = 0, 1241 .fieldoffset = offsetof(CPUARMState, cp15.c15_power_diagnostic) }, 1242 { .name = "NEONBUSY", .cp = 15, .crn = 15, .crm = 1, .opc1 = 0, .opc2 = 0, 1243 .access = PL1_RW, .resetvalue = 0, .type = ARM_CP_CONST }, 1244 /* TLB lockdown control */ 1245 { .name = "TLB_LOCKR", .cp = 15, .crn = 15, .crm = 4, .opc1 = 5, .opc2 = 2, 1246 .access = PL1_W, .resetvalue = 0, .type = ARM_CP_NOP }, 1247 { .name = "TLB_LOCKW", .cp = 15, .crn = 15, .crm = 4, .opc1 = 5, .opc2 = 4, 1248 .access = PL1_W, .resetvalue = 0, .type = ARM_CP_NOP }, 1249 { .name = "TLB_VA", .cp = 15, .crn = 15, .crm = 5, .opc1 = 5, .opc2 = 2, 1250 .access = PL1_RW, .resetvalue = 0, .type = ARM_CP_CONST }, 1251 { .name = "TLB_PA", .cp = 15, .crn = 15, .crm = 6, .opc1 = 5, .opc2 = 2, 1252 .access = PL1_RW, .resetvalue = 0, .type = ARM_CP_CONST }, 1253 { .name = "TLB_ATTR", .cp = 15, .crn = 15, .crm = 7, .opc1 = 5, .opc2 = 2, 1254 .access = PL1_RW, .resetvalue = 0, .type = ARM_CP_CONST }, 1255 REGINFO_SENTINEL 1256 }; 1257 1258 static void cortex_a9_initfn(Object *obj) 1259 { 1260 ARMCPU *cpu = ARM_CPU(obj); 1261 1262 cpu->dtb_compatible = "arm,cortex-a9"; 1263 set_feature(&cpu->env, ARM_FEATURE_V7); 1264 set_feature(&cpu->env, ARM_FEATURE_VFP3); 1265 set_feature(&cpu->env, ARM_FEATURE_VFP_FP16); 1266 set_feature(&cpu->env, ARM_FEATURE_NEON); 1267 set_feature(&cpu->env, ARM_FEATURE_THUMB2EE); 1268 set_feature(&cpu->env, ARM_FEATURE_EL3); 1269 /* Note that A9 supports the MP extensions even for 1270 * A9UP and single-core A9MP (which are both different 1271 * and valid configurations; we don't model A9UP). 1272 */ 1273 set_feature(&cpu->env, ARM_FEATURE_V7MP); 1274 set_feature(&cpu->env, ARM_FEATURE_CBAR); 1275 cpu->midr = 0x410fc090; 1276 cpu->reset_fpsid = 0x41033090; 1277 cpu->mvfr0 = 0x11110222; 1278 cpu->mvfr1 = 0x01111111; 1279 cpu->ctr = 0x80038003; 1280 cpu->reset_sctlr = 0x00c50078; 1281 cpu->id_pfr0 = 0x1031; 1282 cpu->id_pfr1 = 0x11; 1283 cpu->id_dfr0 = 0x000; 1284 cpu->id_afr0 = 0; 1285 cpu->id_mmfr0 = 0x00100103; 1286 cpu->id_mmfr1 = 0x20000000; 1287 cpu->id_mmfr2 = 0x01230000; 1288 cpu->id_mmfr3 = 0x00002111; 1289 cpu->id_isar0 = 0x00101111; 1290 cpu->id_isar1 = 0x13112111; 1291 cpu->id_isar2 = 0x21232041; 1292 cpu->id_isar3 = 0x11112131; 1293 cpu->id_isar4 = 0x00111142; 1294 cpu->dbgdidr = 0x35141000; 1295 cpu->clidr = (1 << 27) | (1 << 24) | 3; 1296 cpu->ccsidr[0] = 0xe00fe019; /* 16k L1 dcache. */ 1297 cpu->ccsidr[1] = 0x200fe019; /* 16k L1 icache. */ 1298 define_arm_cp_regs(cpu, cortexa9_cp_reginfo); 1299 } 1300 1301 #ifndef CONFIG_USER_ONLY 1302 static uint64_t a15_l2ctlr_read(CPUARMState *env, const ARMCPRegInfo *ri) 1303 { 1304 /* Linux wants the number of processors from here. 1305 * Might as well set the interrupt-controller bit too. 1306 */ 1307 return ((smp_cpus - 1) << 24) | (1 << 23); 1308 } 1309 #endif 1310 1311 static const ARMCPRegInfo cortexa15_cp_reginfo[] = { 1312 #ifndef CONFIG_USER_ONLY 1313 { .name = "L2CTLR", .cp = 15, .crn = 9, .crm = 0, .opc1 = 1, .opc2 = 2, 1314 .access = PL1_RW, .resetvalue = 0, .readfn = a15_l2ctlr_read, 1315 .writefn = arm_cp_write_ignore, }, 1316 #endif 1317 { .name = "L2ECTLR", .cp = 15, .crn = 9, .crm = 0, .opc1 = 1, .opc2 = 3, 1318 .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0 }, 1319 REGINFO_SENTINEL 1320 }; 1321 1322 static void cortex_a7_initfn(Object *obj) 1323 { 1324 ARMCPU *cpu = ARM_CPU(obj); 1325 1326 cpu->dtb_compatible = "arm,cortex-a7"; 1327 set_feature(&cpu->env, ARM_FEATURE_V7); 1328 set_feature(&cpu->env, ARM_FEATURE_VFP4); 1329 set_feature(&cpu->env, ARM_FEATURE_NEON); 1330 set_feature(&cpu->env, ARM_FEATURE_THUMB2EE); 1331 set_feature(&cpu->env, ARM_FEATURE_ARM_DIV); 1332 set_feature(&cpu->env, ARM_FEATURE_GENERIC_TIMER); 1333 set_feature(&cpu->env, ARM_FEATURE_DUMMY_C15_REGS); 1334 set_feature(&cpu->env, ARM_FEATURE_CBAR_RO); 1335 set_feature(&cpu->env, ARM_FEATURE_LPAE); 1336 set_feature(&cpu->env, ARM_FEATURE_EL3); 1337 cpu->kvm_target = QEMU_KVM_ARM_TARGET_CORTEX_A7; 1338 cpu->midr = 0x410fc075; 1339 cpu->reset_fpsid = 0x41023075; 1340 cpu->mvfr0 = 0x10110222; 1341 cpu->mvfr1 = 0x11111111; 1342 cpu->ctr = 0x84448003; 1343 cpu->reset_sctlr = 0x00c50078; 1344 cpu->id_pfr0 = 0x00001131; 1345 cpu->id_pfr1 = 0x00011011; 1346 cpu->id_dfr0 = 0x02010555; 1347 cpu->pmceid0 = 0x00000000; 1348 cpu->pmceid1 = 0x00000000; 1349 cpu->id_afr0 = 0x00000000; 1350 cpu->id_mmfr0 = 0x10101105; 1351 cpu->id_mmfr1 = 0x40000000; 1352 cpu->id_mmfr2 = 0x01240000; 1353 cpu->id_mmfr3 = 0x02102211; 1354 cpu->id_isar0 = 0x01101110; 1355 cpu->id_isar1 = 0x13112111; 1356 cpu->id_isar2 = 0x21232041; 1357 cpu->id_isar3 = 0x11112131; 1358 cpu->id_isar4 = 0x10011142; 1359 cpu->dbgdidr = 0x3515f005; 1360 cpu->clidr = 0x0a200023; 1361 cpu->ccsidr[0] = 0x701fe00a; /* 32K L1 dcache */ 1362 cpu->ccsidr[1] = 0x201fe00a; /* 32K L1 icache */ 1363 cpu->ccsidr[2] = 0x711fe07a; /* 4096K L2 unified cache */ 1364 define_arm_cp_regs(cpu, cortexa15_cp_reginfo); /* Same as A15 */ 1365 } 1366 1367 static void cortex_a15_initfn(Object *obj) 1368 { 1369 ARMCPU *cpu = ARM_CPU(obj); 1370 1371 cpu->dtb_compatible = "arm,cortex-a15"; 1372 set_feature(&cpu->env, ARM_FEATURE_V7); 1373 set_feature(&cpu->env, ARM_FEATURE_VFP4); 1374 set_feature(&cpu->env, ARM_FEATURE_NEON); 1375 set_feature(&cpu->env, ARM_FEATURE_THUMB2EE); 1376 set_feature(&cpu->env, ARM_FEATURE_ARM_DIV); 1377 set_feature(&cpu->env, ARM_FEATURE_GENERIC_TIMER); 1378 set_feature(&cpu->env, ARM_FEATURE_DUMMY_C15_REGS); 1379 set_feature(&cpu->env, ARM_FEATURE_CBAR_RO); 1380 set_feature(&cpu->env, ARM_FEATURE_LPAE); 1381 set_feature(&cpu->env, ARM_FEATURE_EL3); 1382 cpu->kvm_target = QEMU_KVM_ARM_TARGET_CORTEX_A15; 1383 cpu->midr = 0x412fc0f1; 1384 cpu->reset_fpsid = 0x410430f0; 1385 cpu->mvfr0 = 0x10110222; 1386 cpu->mvfr1 = 0x11111111; 1387 cpu->ctr = 0x8444c004; 1388 cpu->reset_sctlr = 0x00c50078; 1389 cpu->id_pfr0 = 0x00001131; 1390 cpu->id_pfr1 = 0x00011011; 1391 cpu->id_dfr0 = 0x02010555; 1392 cpu->pmceid0 = 0x0000000; 1393 cpu->pmceid1 = 0x00000000; 1394 cpu->id_afr0 = 0x00000000; 1395 cpu->id_mmfr0 = 0x10201105; 1396 cpu->id_mmfr1 = 0x20000000; 1397 cpu->id_mmfr2 = 0x01240000; 1398 cpu->id_mmfr3 = 0x02102211; 1399 cpu->id_isar0 = 0x02101110; 1400 cpu->id_isar1 = 0x13112111; 1401 cpu->id_isar2 = 0x21232041; 1402 cpu->id_isar3 = 0x11112131; 1403 cpu->id_isar4 = 0x10011142; 1404 cpu->dbgdidr = 0x3515f021; 1405 cpu->clidr = 0x0a200023; 1406 cpu->ccsidr[0] = 0x701fe00a; /* 32K L1 dcache */ 1407 cpu->ccsidr[1] = 0x201fe00a; /* 32K L1 icache */ 1408 cpu->ccsidr[2] = 0x711fe07a; /* 4096K L2 unified cache */ 1409 define_arm_cp_regs(cpu, cortexa15_cp_reginfo); 1410 } 1411 1412 static void ti925t_initfn(Object *obj) 1413 { 1414 ARMCPU *cpu = ARM_CPU(obj); 1415 set_feature(&cpu->env, ARM_FEATURE_V4T); 1416 set_feature(&cpu->env, ARM_FEATURE_OMAPCP); 1417 cpu->midr = ARM_CPUID_TI925T; 1418 cpu->ctr = 0x5109149; 1419 cpu->reset_sctlr = 0x00000070; 1420 } 1421 1422 static void sa1100_initfn(Object *obj) 1423 { 1424 ARMCPU *cpu = ARM_CPU(obj); 1425 1426 cpu->dtb_compatible = "intel,sa1100"; 1427 set_feature(&cpu->env, ARM_FEATURE_STRONGARM); 1428 set_feature(&cpu->env, ARM_FEATURE_DUMMY_C15_REGS); 1429 cpu->midr = 0x4401A11B; 1430 cpu->reset_sctlr = 0x00000070; 1431 } 1432 1433 static void sa1110_initfn(Object *obj) 1434 { 1435 ARMCPU *cpu = ARM_CPU(obj); 1436 set_feature(&cpu->env, ARM_FEATURE_STRONGARM); 1437 set_feature(&cpu->env, ARM_FEATURE_DUMMY_C15_REGS); 1438 cpu->midr = 0x6901B119; 1439 cpu->reset_sctlr = 0x00000070; 1440 } 1441 1442 static void pxa250_initfn(Object *obj) 1443 { 1444 ARMCPU *cpu = ARM_CPU(obj); 1445 1446 cpu->dtb_compatible = "marvell,xscale"; 1447 set_feature(&cpu->env, ARM_FEATURE_V5); 1448 set_feature(&cpu->env, ARM_FEATURE_XSCALE); 1449 cpu->midr = 0x69052100; 1450 cpu->ctr = 0xd172172; 1451 cpu->reset_sctlr = 0x00000078; 1452 } 1453 1454 static void pxa255_initfn(Object *obj) 1455 { 1456 ARMCPU *cpu = ARM_CPU(obj); 1457 1458 cpu->dtb_compatible = "marvell,xscale"; 1459 set_feature(&cpu->env, ARM_FEATURE_V5); 1460 set_feature(&cpu->env, ARM_FEATURE_XSCALE); 1461 cpu->midr = 0x69052d00; 1462 cpu->ctr = 0xd172172; 1463 cpu->reset_sctlr = 0x00000078; 1464 } 1465 1466 static void pxa260_initfn(Object *obj) 1467 { 1468 ARMCPU *cpu = ARM_CPU(obj); 1469 1470 cpu->dtb_compatible = "marvell,xscale"; 1471 set_feature(&cpu->env, ARM_FEATURE_V5); 1472 set_feature(&cpu->env, ARM_FEATURE_XSCALE); 1473 cpu->midr = 0x69052903; 1474 cpu->ctr = 0xd172172; 1475 cpu->reset_sctlr = 0x00000078; 1476 } 1477 1478 static void pxa261_initfn(Object *obj) 1479 { 1480 ARMCPU *cpu = ARM_CPU(obj); 1481 1482 cpu->dtb_compatible = "marvell,xscale"; 1483 set_feature(&cpu->env, ARM_FEATURE_V5); 1484 set_feature(&cpu->env, ARM_FEATURE_XSCALE); 1485 cpu->midr = 0x69052d05; 1486 cpu->ctr = 0xd172172; 1487 cpu->reset_sctlr = 0x00000078; 1488 } 1489 1490 static void pxa262_initfn(Object *obj) 1491 { 1492 ARMCPU *cpu = ARM_CPU(obj); 1493 1494 cpu->dtb_compatible = "marvell,xscale"; 1495 set_feature(&cpu->env, ARM_FEATURE_V5); 1496 set_feature(&cpu->env, ARM_FEATURE_XSCALE); 1497 cpu->midr = 0x69052d06; 1498 cpu->ctr = 0xd172172; 1499 cpu->reset_sctlr = 0x00000078; 1500 } 1501 1502 static void pxa270a0_initfn(Object *obj) 1503 { 1504 ARMCPU *cpu = ARM_CPU(obj); 1505 1506 cpu->dtb_compatible = "marvell,xscale"; 1507 set_feature(&cpu->env, ARM_FEATURE_V5); 1508 set_feature(&cpu->env, ARM_FEATURE_XSCALE); 1509 set_feature(&cpu->env, ARM_FEATURE_IWMMXT); 1510 cpu->midr = 0x69054110; 1511 cpu->ctr = 0xd172172; 1512 cpu->reset_sctlr = 0x00000078; 1513 } 1514 1515 static void pxa270a1_initfn(Object *obj) 1516 { 1517 ARMCPU *cpu = ARM_CPU(obj); 1518 1519 cpu->dtb_compatible = "marvell,xscale"; 1520 set_feature(&cpu->env, ARM_FEATURE_V5); 1521 set_feature(&cpu->env, ARM_FEATURE_XSCALE); 1522 set_feature(&cpu->env, ARM_FEATURE_IWMMXT); 1523 cpu->midr = 0x69054111; 1524 cpu->ctr = 0xd172172; 1525 cpu->reset_sctlr = 0x00000078; 1526 } 1527 1528 static void pxa270b0_initfn(Object *obj) 1529 { 1530 ARMCPU *cpu = ARM_CPU(obj); 1531 1532 cpu->dtb_compatible = "marvell,xscale"; 1533 set_feature(&cpu->env, ARM_FEATURE_V5); 1534 set_feature(&cpu->env, ARM_FEATURE_XSCALE); 1535 set_feature(&cpu->env, ARM_FEATURE_IWMMXT); 1536 cpu->midr = 0x69054112; 1537 cpu->ctr = 0xd172172; 1538 cpu->reset_sctlr = 0x00000078; 1539 } 1540 1541 static void pxa270b1_initfn(Object *obj) 1542 { 1543 ARMCPU *cpu = ARM_CPU(obj); 1544 1545 cpu->dtb_compatible = "marvell,xscale"; 1546 set_feature(&cpu->env, ARM_FEATURE_V5); 1547 set_feature(&cpu->env, ARM_FEATURE_XSCALE); 1548 set_feature(&cpu->env, ARM_FEATURE_IWMMXT); 1549 cpu->midr = 0x69054113; 1550 cpu->ctr = 0xd172172; 1551 cpu->reset_sctlr = 0x00000078; 1552 } 1553 1554 static void pxa270c0_initfn(Object *obj) 1555 { 1556 ARMCPU *cpu = ARM_CPU(obj); 1557 1558 cpu->dtb_compatible = "marvell,xscale"; 1559 set_feature(&cpu->env, ARM_FEATURE_V5); 1560 set_feature(&cpu->env, ARM_FEATURE_XSCALE); 1561 set_feature(&cpu->env, ARM_FEATURE_IWMMXT); 1562 cpu->midr = 0x69054114; 1563 cpu->ctr = 0xd172172; 1564 cpu->reset_sctlr = 0x00000078; 1565 } 1566 1567 static void pxa270c5_initfn(Object *obj) 1568 { 1569 ARMCPU *cpu = ARM_CPU(obj); 1570 1571 cpu->dtb_compatible = "marvell,xscale"; 1572 set_feature(&cpu->env, ARM_FEATURE_V5); 1573 set_feature(&cpu->env, ARM_FEATURE_XSCALE); 1574 set_feature(&cpu->env, ARM_FEATURE_IWMMXT); 1575 cpu->midr = 0x69054117; 1576 cpu->ctr = 0xd172172; 1577 cpu->reset_sctlr = 0x00000078; 1578 } 1579 1580 #ifdef CONFIG_USER_ONLY 1581 static void arm_any_initfn(Object *obj) 1582 { 1583 ARMCPU *cpu = ARM_CPU(obj); 1584 set_feature(&cpu->env, ARM_FEATURE_V8); 1585 set_feature(&cpu->env, ARM_FEATURE_VFP4); 1586 set_feature(&cpu->env, ARM_FEATURE_NEON); 1587 set_feature(&cpu->env, ARM_FEATURE_THUMB2EE); 1588 set_feature(&cpu->env, ARM_FEATURE_V8_AES); 1589 set_feature(&cpu->env, ARM_FEATURE_V8_SHA1); 1590 set_feature(&cpu->env, ARM_FEATURE_V8_SHA256); 1591 set_feature(&cpu->env, ARM_FEATURE_V8_PMULL); 1592 set_feature(&cpu->env, ARM_FEATURE_CRC); 1593 cpu->midr = 0xffffffff; 1594 } 1595 #endif 1596 1597 #endif /* !defined(CONFIG_USER_ONLY) || !defined(TARGET_AARCH64) */ 1598 1599 typedef struct ARMCPUInfo { 1600 const char *name; 1601 void (*initfn)(Object *obj); 1602 void (*class_init)(ObjectClass *oc, void *data); 1603 } ARMCPUInfo; 1604 1605 static const ARMCPUInfo arm_cpus[] = { 1606 #if !defined(CONFIG_USER_ONLY) || !defined(TARGET_AARCH64) 1607 { .name = "arm926", .initfn = arm926_initfn }, 1608 { .name = "arm946", .initfn = arm946_initfn }, 1609 { .name = "arm1026", .initfn = arm1026_initfn }, 1610 /* What QEMU calls "arm1136-r2" is actually the 1136 r0p2, i.e. an 1611 * older core than plain "arm1136". In particular this does not 1612 * have the v6K features. 1613 */ 1614 { .name = "arm1136-r2", .initfn = arm1136_r2_initfn }, 1615 { .name = "arm1136", .initfn = arm1136_initfn }, 1616 { .name = "arm1176", .initfn = arm1176_initfn }, 1617 { .name = "arm11mpcore", .initfn = arm11mpcore_initfn }, 1618 { .name = "cortex-m3", .initfn = cortex_m3_initfn, 1619 .class_init = arm_v7m_class_init }, 1620 { .name = "cortex-m4", .initfn = cortex_m4_initfn, 1621 .class_init = arm_v7m_class_init }, 1622 { .name = "cortex-r5", .initfn = cortex_r5_initfn }, 1623 { .name = "cortex-a7", .initfn = cortex_a7_initfn }, 1624 { .name = "cortex-a8", .initfn = cortex_a8_initfn }, 1625 { .name = "cortex-a9", .initfn = cortex_a9_initfn }, 1626 { .name = "cortex-a15", .initfn = cortex_a15_initfn }, 1627 { .name = "ti925t", .initfn = ti925t_initfn }, 1628 { .name = "sa1100", .initfn = sa1100_initfn }, 1629 { .name = "sa1110", .initfn = sa1110_initfn }, 1630 { .name = "pxa250", .initfn = pxa250_initfn }, 1631 { .name = "pxa255", .initfn = pxa255_initfn }, 1632 { .name = "pxa260", .initfn = pxa260_initfn }, 1633 { .name = "pxa261", .initfn = pxa261_initfn }, 1634 { .name = "pxa262", .initfn = pxa262_initfn }, 1635 /* "pxa270" is an alias for "pxa270-a0" */ 1636 { .name = "pxa270", .initfn = pxa270a0_initfn }, 1637 { .name = "pxa270-a0", .initfn = pxa270a0_initfn }, 1638 { .name = "pxa270-a1", .initfn = pxa270a1_initfn }, 1639 { .name = "pxa270-b0", .initfn = pxa270b0_initfn }, 1640 { .name = "pxa270-b1", .initfn = pxa270b1_initfn }, 1641 { .name = "pxa270-c0", .initfn = pxa270c0_initfn }, 1642 { .name = "pxa270-c5", .initfn = pxa270c5_initfn }, 1643 #ifdef CONFIG_USER_ONLY 1644 { .name = "any", .initfn = arm_any_initfn }, 1645 #endif 1646 #endif 1647 { .name = NULL } 1648 }; 1649 1650 static Property arm_cpu_properties[] = { 1651 DEFINE_PROP_BOOL("start-powered-off", ARMCPU, start_powered_off, false), 1652 DEFINE_PROP_UINT32("psci-conduit", ARMCPU, psci_conduit, 0), 1653 DEFINE_PROP_UINT32("midr", ARMCPU, midr, 0), 1654 DEFINE_PROP_UINT64("mp-affinity", ARMCPU, 1655 mp_affinity, ARM64_AFFINITY_INVALID), 1656 DEFINE_PROP_INT32("node-id", ARMCPU, node_id, CPU_UNSET_NUMA_NODE_ID), 1657 DEFINE_PROP_END_OF_LIST() 1658 }; 1659 1660 #ifdef CONFIG_USER_ONLY 1661 static int arm_cpu_handle_mmu_fault(CPUState *cs, vaddr address, int rw, 1662 int mmu_idx) 1663 { 1664 ARMCPU *cpu = ARM_CPU(cs); 1665 CPUARMState *env = &cpu->env; 1666 1667 env->exception.vaddress = address; 1668 if (rw == 2) { 1669 cs->exception_index = EXCP_PREFETCH_ABORT; 1670 } else { 1671 cs->exception_index = EXCP_DATA_ABORT; 1672 } 1673 return 1; 1674 } 1675 #endif 1676 1677 static gchar *arm_gdb_arch_name(CPUState *cs) 1678 { 1679 ARMCPU *cpu = ARM_CPU(cs); 1680 CPUARMState *env = &cpu->env; 1681 1682 if (arm_feature(env, ARM_FEATURE_IWMMXT)) { 1683 return g_strdup("iwmmxt"); 1684 } 1685 return g_strdup("arm"); 1686 } 1687 1688 static void arm_cpu_class_init(ObjectClass *oc, void *data) 1689 { 1690 ARMCPUClass *acc = ARM_CPU_CLASS(oc); 1691 CPUClass *cc = CPU_CLASS(acc); 1692 DeviceClass *dc = DEVICE_CLASS(oc); 1693 1694 acc->parent_realize = dc->realize; 1695 dc->realize = arm_cpu_realizefn; 1696 dc->props = arm_cpu_properties; 1697 1698 acc->parent_reset = cc->reset; 1699 cc->reset = arm_cpu_reset; 1700 1701 cc->class_by_name = arm_cpu_class_by_name; 1702 cc->has_work = arm_cpu_has_work; 1703 cc->cpu_exec_interrupt = arm_cpu_exec_interrupt; 1704 cc->dump_state = arm_cpu_dump_state; 1705 cc->set_pc = arm_cpu_set_pc; 1706 cc->gdb_read_register = arm_cpu_gdb_read_register; 1707 cc->gdb_write_register = arm_cpu_gdb_write_register; 1708 #ifdef CONFIG_USER_ONLY 1709 cc->handle_mmu_fault = arm_cpu_handle_mmu_fault; 1710 #else 1711 cc->do_interrupt = arm_cpu_do_interrupt; 1712 cc->do_unaligned_access = arm_cpu_do_unaligned_access; 1713 cc->do_transaction_failed = arm_cpu_do_transaction_failed; 1714 cc->get_phys_page_attrs_debug = arm_cpu_get_phys_page_attrs_debug; 1715 cc->asidx_from_attrs = arm_asidx_from_attrs; 1716 cc->vmsd = &vmstate_arm_cpu; 1717 cc->virtio_is_big_endian = arm_cpu_virtio_is_big_endian; 1718 cc->write_elf64_note = arm_cpu_write_elf64_note; 1719 cc->write_elf32_note = arm_cpu_write_elf32_note; 1720 #endif 1721 cc->gdb_num_core_regs = 26; 1722 cc->gdb_core_xml_file = "arm-core.xml"; 1723 cc->gdb_arch_name = arm_gdb_arch_name; 1724 cc->gdb_stop_before_watchpoint = true; 1725 cc->debug_excp_handler = arm_debug_excp_handler; 1726 cc->debug_check_watchpoint = arm_debug_check_watchpoint; 1727 #if !defined(CONFIG_USER_ONLY) 1728 cc->adjust_watchpoint_address = arm_adjust_watchpoint_address; 1729 #endif 1730 1731 cc->disas_set_info = arm_disas_set_info; 1732 } 1733 1734 static void cpu_register(const ARMCPUInfo *info) 1735 { 1736 TypeInfo type_info = { 1737 .parent = TYPE_ARM_CPU, 1738 .instance_size = sizeof(ARMCPU), 1739 .instance_init = info->initfn, 1740 .class_size = sizeof(ARMCPUClass), 1741 .class_init = info->class_init, 1742 }; 1743 1744 type_info.name = g_strdup_printf("%s-" TYPE_ARM_CPU, info->name); 1745 type_register(&type_info); 1746 g_free((void *)type_info.name); 1747 } 1748 1749 static const TypeInfo arm_cpu_type_info = { 1750 .name = TYPE_ARM_CPU, 1751 .parent = TYPE_CPU, 1752 .instance_size = sizeof(ARMCPU), 1753 .instance_init = arm_cpu_initfn, 1754 .instance_post_init = arm_cpu_post_init, 1755 .instance_finalize = arm_cpu_finalizefn, 1756 .abstract = true, 1757 .class_size = sizeof(ARMCPUClass), 1758 .class_init = arm_cpu_class_init, 1759 }; 1760 1761 static void arm_cpu_register_types(void) 1762 { 1763 const ARMCPUInfo *info = arm_cpus; 1764 1765 type_register_static(&arm_cpu_type_info); 1766 1767 while (info->name) { 1768 cpu_register(info); 1769 info++; 1770 } 1771 } 1772 1773 type_init(arm_cpu_register_types) 1774