1 /* 2 * QEMU ARM CPU 3 * 4 * Copyright (c) 2012 SUSE LINUX Products GmbH 5 * 6 * This program is free software; you can redistribute it and/or 7 * modify it under the terms of the GNU General Public License 8 * as published by the Free Software Foundation; either version 2 9 * of the License, or (at your option) any later version. 10 * 11 * This program is distributed in the hope that it will be useful, 12 * but WITHOUT ANY WARRANTY; without even the implied warranty of 13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 14 * GNU General Public License for more details. 15 * 16 * You should have received a copy of the GNU General Public License 17 * along with this program; if not, see 18 * <http://www.gnu.org/licenses/gpl-2.0.html> 19 */ 20 21 #include "qemu/osdep.h" 22 #include "target/arm/idau.h" 23 #include "qemu/error-report.h" 24 #include "qapi/error.h" 25 #include "cpu.h" 26 #include "internals.h" 27 #include "qemu-common.h" 28 #include "exec/exec-all.h" 29 #include "hw/qdev-properties.h" 30 #if !defined(CONFIG_USER_ONLY) 31 #include "hw/loader.h" 32 #endif 33 #include "hw/arm/arm.h" 34 #include "sysemu/sysemu.h" 35 #include "sysemu/hw_accel.h" 36 #include "kvm_arm.h" 37 #include "disas/capstone.h" 38 #include "fpu/softfloat.h" 39 40 static void arm_cpu_set_pc(CPUState *cs, vaddr value) 41 { 42 ARMCPU *cpu = ARM_CPU(cs); 43 44 cpu->env.regs[15] = value; 45 } 46 47 static bool arm_cpu_has_work(CPUState *cs) 48 { 49 ARMCPU *cpu = ARM_CPU(cs); 50 51 return (cpu->power_state != PSCI_OFF) 52 && cs->interrupt_request & 53 (CPU_INTERRUPT_FIQ | CPU_INTERRUPT_HARD 54 | CPU_INTERRUPT_VFIQ | CPU_INTERRUPT_VIRQ 55 | CPU_INTERRUPT_EXITTB); 56 } 57 58 void arm_register_pre_el_change_hook(ARMCPU *cpu, ARMELChangeHookFn *hook, 59 void *opaque) 60 { 61 ARMELChangeHook *entry = g_new0(ARMELChangeHook, 1); 62 63 entry->hook = hook; 64 entry->opaque = opaque; 65 66 QLIST_INSERT_HEAD(&cpu->pre_el_change_hooks, entry, node); 67 } 68 69 void arm_register_el_change_hook(ARMCPU *cpu, ARMELChangeHookFn *hook, 70 void *opaque) 71 { 72 ARMELChangeHook *entry = g_new0(ARMELChangeHook, 1); 73 74 entry->hook = hook; 75 entry->opaque = opaque; 76 77 QLIST_INSERT_HEAD(&cpu->el_change_hooks, entry, node); 78 } 79 80 static void cp_reg_reset(gpointer key, gpointer value, gpointer opaque) 81 { 82 /* Reset a single ARMCPRegInfo register */ 83 ARMCPRegInfo *ri = value; 84 ARMCPU *cpu = opaque; 85 86 if (ri->type & (ARM_CP_SPECIAL | ARM_CP_ALIAS)) { 87 return; 88 } 89 90 if (ri->resetfn) { 91 ri->resetfn(&cpu->env, ri); 92 return; 93 } 94 95 /* A zero offset is never possible as it would be regs[0] 96 * so we use it to indicate that reset is being handled elsewhere. 97 * This is basically only used for fields in non-core coprocessors 98 * (like the pxa2xx ones). 99 */ 100 if (!ri->fieldoffset) { 101 return; 102 } 103 104 if (cpreg_field_is_64bit(ri)) { 105 CPREG_FIELD64(&cpu->env, ri) = ri->resetvalue; 106 } else { 107 CPREG_FIELD32(&cpu->env, ri) = ri->resetvalue; 108 } 109 } 110 111 static void cp_reg_check_reset(gpointer key, gpointer value, gpointer opaque) 112 { 113 /* Purely an assertion check: we've already done reset once, 114 * so now check that running the reset for the cpreg doesn't 115 * change its value. This traps bugs where two different cpregs 116 * both try to reset the same state field but to different values. 117 */ 118 ARMCPRegInfo *ri = value; 119 ARMCPU *cpu = opaque; 120 uint64_t oldvalue, newvalue; 121 122 if (ri->type & (ARM_CP_SPECIAL | ARM_CP_ALIAS | ARM_CP_NO_RAW)) { 123 return; 124 } 125 126 oldvalue = read_raw_cp_reg(&cpu->env, ri); 127 cp_reg_reset(key, value, opaque); 128 newvalue = read_raw_cp_reg(&cpu->env, ri); 129 assert(oldvalue == newvalue); 130 } 131 132 /* CPUClass::reset() */ 133 static void arm_cpu_reset(CPUState *s) 134 { 135 ARMCPU *cpu = ARM_CPU(s); 136 ARMCPUClass *acc = ARM_CPU_GET_CLASS(cpu); 137 CPUARMState *env = &cpu->env; 138 139 acc->parent_reset(s); 140 141 memset(env, 0, offsetof(CPUARMState, end_reset_fields)); 142 143 g_hash_table_foreach(cpu->cp_regs, cp_reg_reset, cpu); 144 g_hash_table_foreach(cpu->cp_regs, cp_reg_check_reset, cpu); 145 146 env->vfp.xregs[ARM_VFP_FPSID] = cpu->reset_fpsid; 147 env->vfp.xregs[ARM_VFP_MVFR0] = cpu->isar.mvfr0; 148 env->vfp.xregs[ARM_VFP_MVFR1] = cpu->isar.mvfr1; 149 env->vfp.xregs[ARM_VFP_MVFR2] = cpu->isar.mvfr2; 150 151 cpu->power_state = cpu->start_powered_off ? PSCI_OFF : PSCI_ON; 152 s->halted = cpu->start_powered_off; 153 154 if (arm_feature(env, ARM_FEATURE_IWMMXT)) { 155 env->iwmmxt.cregs[ARM_IWMMXT_wCID] = 0x69051000 | 'Q'; 156 } 157 158 if (arm_feature(env, ARM_FEATURE_AARCH64)) { 159 /* 64 bit CPUs always start in 64 bit mode */ 160 env->aarch64 = 1; 161 #if defined(CONFIG_USER_ONLY) 162 env->pstate = PSTATE_MODE_EL0t; 163 /* Userspace expects access to DC ZVA, CTL_EL0 and the cache ops */ 164 env->cp15.sctlr_el[1] |= SCTLR_UCT | SCTLR_UCI | SCTLR_DZE; 165 /* and to the FP/Neon instructions */ 166 env->cp15.cpacr_el1 = deposit64(env->cp15.cpacr_el1, 20, 2, 3); 167 /* and to the SVE instructions */ 168 env->cp15.cpacr_el1 = deposit64(env->cp15.cpacr_el1, 16, 2, 3); 169 env->cp15.cptr_el[3] |= CPTR_EZ; 170 /* with maximum vector length */ 171 env->vfp.zcr_el[1] = cpu->sve_max_vq - 1; 172 env->vfp.zcr_el[2] = env->vfp.zcr_el[1]; 173 env->vfp.zcr_el[3] = env->vfp.zcr_el[1]; 174 #else 175 /* Reset into the highest available EL */ 176 if (arm_feature(env, ARM_FEATURE_EL3)) { 177 env->pstate = PSTATE_MODE_EL3h; 178 } else if (arm_feature(env, ARM_FEATURE_EL2)) { 179 env->pstate = PSTATE_MODE_EL2h; 180 } else { 181 env->pstate = PSTATE_MODE_EL1h; 182 } 183 env->pc = cpu->rvbar; 184 #endif 185 } else { 186 #if defined(CONFIG_USER_ONLY) 187 /* Userspace expects access to cp10 and cp11 for FP/Neon */ 188 env->cp15.cpacr_el1 = deposit64(env->cp15.cpacr_el1, 20, 4, 0xf); 189 #endif 190 } 191 192 #if defined(CONFIG_USER_ONLY) 193 env->uncached_cpsr = ARM_CPU_MODE_USR; 194 /* For user mode we must enable access to coprocessors */ 195 env->vfp.xregs[ARM_VFP_FPEXC] = 1 << 30; 196 if (arm_feature(env, ARM_FEATURE_IWMMXT)) { 197 env->cp15.c15_cpar = 3; 198 } else if (arm_feature(env, ARM_FEATURE_XSCALE)) { 199 env->cp15.c15_cpar = 1; 200 } 201 #else 202 203 /* 204 * If the highest available EL is EL2, AArch32 will start in Hyp 205 * mode; otherwise it starts in SVC. Note that if we start in 206 * AArch64 then these values in the uncached_cpsr will be ignored. 207 */ 208 if (arm_feature(env, ARM_FEATURE_EL2) && 209 !arm_feature(env, ARM_FEATURE_EL3)) { 210 env->uncached_cpsr = ARM_CPU_MODE_HYP; 211 } else { 212 env->uncached_cpsr = ARM_CPU_MODE_SVC; 213 } 214 env->daif = PSTATE_D | PSTATE_A | PSTATE_I | PSTATE_F; 215 216 if (arm_feature(env, ARM_FEATURE_M)) { 217 uint32_t initial_msp; /* Loaded from 0x0 */ 218 uint32_t initial_pc; /* Loaded from 0x4 */ 219 uint8_t *rom; 220 uint32_t vecbase; 221 222 if (arm_feature(env, ARM_FEATURE_M_SECURITY)) { 223 env->v7m.secure = true; 224 } else { 225 /* This bit resets to 0 if security is supported, but 1 if 226 * it is not. The bit is not present in v7M, but we set it 227 * here so we can avoid having to make checks on it conditional 228 * on ARM_FEATURE_V8 (we don't let the guest see the bit). 229 */ 230 env->v7m.aircr = R_V7M_AIRCR_BFHFNMINS_MASK; 231 } 232 233 /* In v7M the reset value of this bit is IMPDEF, but ARM recommends 234 * that it resets to 1, so QEMU always does that rather than making 235 * it dependent on CPU model. In v8M it is RES1. 236 */ 237 env->v7m.ccr[M_REG_NS] = R_V7M_CCR_STKALIGN_MASK; 238 env->v7m.ccr[M_REG_S] = R_V7M_CCR_STKALIGN_MASK; 239 if (arm_feature(env, ARM_FEATURE_V8)) { 240 /* in v8M the NONBASETHRDENA bit [0] is RES1 */ 241 env->v7m.ccr[M_REG_NS] |= R_V7M_CCR_NONBASETHRDENA_MASK; 242 env->v7m.ccr[M_REG_S] |= R_V7M_CCR_NONBASETHRDENA_MASK; 243 } 244 if (!arm_feature(env, ARM_FEATURE_M_MAIN)) { 245 env->v7m.ccr[M_REG_NS] |= R_V7M_CCR_UNALIGN_TRP_MASK; 246 env->v7m.ccr[M_REG_S] |= R_V7M_CCR_UNALIGN_TRP_MASK; 247 } 248 249 /* Unlike A/R profile, M profile defines the reset LR value */ 250 env->regs[14] = 0xffffffff; 251 252 env->v7m.vecbase[M_REG_S] = cpu->init_svtor & 0xffffff80; 253 254 /* Load the initial SP and PC from offset 0 and 4 in the vector table */ 255 vecbase = env->v7m.vecbase[env->v7m.secure]; 256 rom = rom_ptr(vecbase, 8); 257 if (rom) { 258 /* Address zero is covered by ROM which hasn't yet been 259 * copied into physical memory. 260 */ 261 initial_msp = ldl_p(rom); 262 initial_pc = ldl_p(rom + 4); 263 } else { 264 /* Address zero not covered by a ROM blob, or the ROM blob 265 * is in non-modifiable memory and this is a second reset after 266 * it got copied into memory. In the latter case, rom_ptr 267 * will return a NULL pointer and we should use ldl_phys instead. 268 */ 269 initial_msp = ldl_phys(s->as, vecbase); 270 initial_pc = ldl_phys(s->as, vecbase + 4); 271 } 272 273 env->regs[13] = initial_msp & 0xFFFFFFFC; 274 env->regs[15] = initial_pc & ~1; 275 env->thumb = initial_pc & 1; 276 } 277 278 /* AArch32 has a hard highvec setting of 0xFFFF0000. If we are currently 279 * executing as AArch32 then check if highvecs are enabled and 280 * adjust the PC accordingly. 281 */ 282 if (A32_BANKED_CURRENT_REG_GET(env, sctlr) & SCTLR_V) { 283 env->regs[15] = 0xFFFF0000; 284 } 285 286 /* M profile requires that reset clears the exclusive monitor; 287 * A profile does not, but clearing it makes more sense than having it 288 * set with an exclusive access on address zero. 289 */ 290 arm_clear_exclusive(env); 291 292 env->vfp.xregs[ARM_VFP_FPEXC] = 0; 293 #endif 294 295 if (arm_feature(env, ARM_FEATURE_PMSA)) { 296 if (cpu->pmsav7_dregion > 0) { 297 if (arm_feature(env, ARM_FEATURE_V8)) { 298 memset(env->pmsav8.rbar[M_REG_NS], 0, 299 sizeof(*env->pmsav8.rbar[M_REG_NS]) 300 * cpu->pmsav7_dregion); 301 memset(env->pmsav8.rlar[M_REG_NS], 0, 302 sizeof(*env->pmsav8.rlar[M_REG_NS]) 303 * cpu->pmsav7_dregion); 304 if (arm_feature(env, ARM_FEATURE_M_SECURITY)) { 305 memset(env->pmsav8.rbar[M_REG_S], 0, 306 sizeof(*env->pmsav8.rbar[M_REG_S]) 307 * cpu->pmsav7_dregion); 308 memset(env->pmsav8.rlar[M_REG_S], 0, 309 sizeof(*env->pmsav8.rlar[M_REG_S]) 310 * cpu->pmsav7_dregion); 311 } 312 } else if (arm_feature(env, ARM_FEATURE_V7)) { 313 memset(env->pmsav7.drbar, 0, 314 sizeof(*env->pmsav7.drbar) * cpu->pmsav7_dregion); 315 memset(env->pmsav7.drsr, 0, 316 sizeof(*env->pmsav7.drsr) * cpu->pmsav7_dregion); 317 memset(env->pmsav7.dracr, 0, 318 sizeof(*env->pmsav7.dracr) * cpu->pmsav7_dregion); 319 } 320 } 321 env->pmsav7.rnr[M_REG_NS] = 0; 322 env->pmsav7.rnr[M_REG_S] = 0; 323 env->pmsav8.mair0[M_REG_NS] = 0; 324 env->pmsav8.mair0[M_REG_S] = 0; 325 env->pmsav8.mair1[M_REG_NS] = 0; 326 env->pmsav8.mair1[M_REG_S] = 0; 327 } 328 329 if (arm_feature(env, ARM_FEATURE_M_SECURITY)) { 330 if (cpu->sau_sregion > 0) { 331 memset(env->sau.rbar, 0, sizeof(*env->sau.rbar) * cpu->sau_sregion); 332 memset(env->sau.rlar, 0, sizeof(*env->sau.rlar) * cpu->sau_sregion); 333 } 334 env->sau.rnr = 0; 335 /* SAU_CTRL reset value is IMPDEF; we choose 0, which is what 336 * the Cortex-M33 does. 337 */ 338 env->sau.ctrl = 0; 339 } 340 341 set_flush_to_zero(1, &env->vfp.standard_fp_status); 342 set_flush_inputs_to_zero(1, &env->vfp.standard_fp_status); 343 set_default_nan_mode(1, &env->vfp.standard_fp_status); 344 set_float_detect_tininess(float_tininess_before_rounding, 345 &env->vfp.fp_status); 346 set_float_detect_tininess(float_tininess_before_rounding, 347 &env->vfp.standard_fp_status); 348 set_float_detect_tininess(float_tininess_before_rounding, 349 &env->vfp.fp_status_f16); 350 #ifndef CONFIG_USER_ONLY 351 if (kvm_enabled()) { 352 kvm_arm_reset_vcpu(cpu); 353 } 354 #endif 355 356 hw_breakpoint_update_all(cpu); 357 hw_watchpoint_update_all(cpu); 358 } 359 360 bool arm_cpu_exec_interrupt(CPUState *cs, int interrupt_request) 361 { 362 CPUClass *cc = CPU_GET_CLASS(cs); 363 CPUARMState *env = cs->env_ptr; 364 uint32_t cur_el = arm_current_el(env); 365 bool secure = arm_is_secure(env); 366 uint32_t target_el; 367 uint32_t excp_idx; 368 bool ret = false; 369 370 if (interrupt_request & CPU_INTERRUPT_FIQ) { 371 excp_idx = EXCP_FIQ; 372 target_el = arm_phys_excp_target_el(cs, excp_idx, cur_el, secure); 373 if (arm_excp_unmasked(cs, excp_idx, target_el)) { 374 cs->exception_index = excp_idx; 375 env->exception.target_el = target_el; 376 cc->do_interrupt(cs); 377 ret = true; 378 } 379 } 380 if (interrupt_request & CPU_INTERRUPT_HARD) { 381 excp_idx = EXCP_IRQ; 382 target_el = arm_phys_excp_target_el(cs, excp_idx, cur_el, secure); 383 if (arm_excp_unmasked(cs, excp_idx, target_el)) { 384 cs->exception_index = excp_idx; 385 env->exception.target_el = target_el; 386 cc->do_interrupt(cs); 387 ret = true; 388 } 389 } 390 if (interrupt_request & CPU_INTERRUPT_VIRQ) { 391 excp_idx = EXCP_VIRQ; 392 target_el = 1; 393 if (arm_excp_unmasked(cs, excp_idx, target_el)) { 394 cs->exception_index = excp_idx; 395 env->exception.target_el = target_el; 396 cc->do_interrupt(cs); 397 ret = true; 398 } 399 } 400 if (interrupt_request & CPU_INTERRUPT_VFIQ) { 401 excp_idx = EXCP_VFIQ; 402 target_el = 1; 403 if (arm_excp_unmasked(cs, excp_idx, target_el)) { 404 cs->exception_index = excp_idx; 405 env->exception.target_el = target_el; 406 cc->do_interrupt(cs); 407 ret = true; 408 } 409 } 410 411 return ret; 412 } 413 414 #if !defined(CONFIG_USER_ONLY) || !defined(TARGET_AARCH64) 415 static bool arm_v7m_cpu_exec_interrupt(CPUState *cs, int interrupt_request) 416 { 417 CPUClass *cc = CPU_GET_CLASS(cs); 418 ARMCPU *cpu = ARM_CPU(cs); 419 CPUARMState *env = &cpu->env; 420 bool ret = false; 421 422 /* ARMv7-M interrupt masking works differently than -A or -R. 423 * There is no FIQ/IRQ distinction. Instead of I and F bits 424 * masking FIQ and IRQ interrupts, an exception is taken only 425 * if it is higher priority than the current execution priority 426 * (which depends on state like BASEPRI, FAULTMASK and the 427 * currently active exception). 428 */ 429 if (interrupt_request & CPU_INTERRUPT_HARD 430 && (armv7m_nvic_can_take_pending_exception(env->nvic))) { 431 cs->exception_index = EXCP_IRQ; 432 cc->do_interrupt(cs); 433 ret = true; 434 } 435 return ret; 436 } 437 #endif 438 439 void arm_cpu_update_virq(ARMCPU *cpu) 440 { 441 /* 442 * Update the interrupt level for VIRQ, which is the logical OR of 443 * the HCR_EL2.VI bit and the input line level from the GIC. 444 */ 445 CPUARMState *env = &cpu->env; 446 CPUState *cs = CPU(cpu); 447 448 bool new_state = (env->cp15.hcr_el2 & HCR_VI) || 449 (env->irq_line_state & CPU_INTERRUPT_VIRQ); 450 451 if (new_state != ((cs->interrupt_request & CPU_INTERRUPT_VIRQ) != 0)) { 452 if (new_state) { 453 cpu_interrupt(cs, CPU_INTERRUPT_VIRQ); 454 } else { 455 cpu_reset_interrupt(cs, CPU_INTERRUPT_VIRQ); 456 } 457 } 458 } 459 460 void arm_cpu_update_vfiq(ARMCPU *cpu) 461 { 462 /* 463 * Update the interrupt level for VFIQ, which is the logical OR of 464 * the HCR_EL2.VF bit and the input line level from the GIC. 465 */ 466 CPUARMState *env = &cpu->env; 467 CPUState *cs = CPU(cpu); 468 469 bool new_state = (env->cp15.hcr_el2 & HCR_VF) || 470 (env->irq_line_state & CPU_INTERRUPT_VFIQ); 471 472 if (new_state != ((cs->interrupt_request & CPU_INTERRUPT_VFIQ) != 0)) { 473 if (new_state) { 474 cpu_interrupt(cs, CPU_INTERRUPT_VFIQ); 475 } else { 476 cpu_reset_interrupt(cs, CPU_INTERRUPT_VFIQ); 477 } 478 } 479 } 480 481 #ifndef CONFIG_USER_ONLY 482 static void arm_cpu_set_irq(void *opaque, int irq, int level) 483 { 484 ARMCPU *cpu = opaque; 485 CPUARMState *env = &cpu->env; 486 CPUState *cs = CPU(cpu); 487 static const int mask[] = { 488 [ARM_CPU_IRQ] = CPU_INTERRUPT_HARD, 489 [ARM_CPU_FIQ] = CPU_INTERRUPT_FIQ, 490 [ARM_CPU_VIRQ] = CPU_INTERRUPT_VIRQ, 491 [ARM_CPU_VFIQ] = CPU_INTERRUPT_VFIQ 492 }; 493 494 if (level) { 495 env->irq_line_state |= mask[irq]; 496 } else { 497 env->irq_line_state &= ~mask[irq]; 498 } 499 500 switch (irq) { 501 case ARM_CPU_VIRQ: 502 assert(arm_feature(env, ARM_FEATURE_EL2)); 503 arm_cpu_update_virq(cpu); 504 break; 505 case ARM_CPU_VFIQ: 506 assert(arm_feature(env, ARM_FEATURE_EL2)); 507 arm_cpu_update_vfiq(cpu); 508 break; 509 case ARM_CPU_IRQ: 510 case ARM_CPU_FIQ: 511 if (level) { 512 cpu_interrupt(cs, mask[irq]); 513 } else { 514 cpu_reset_interrupt(cs, mask[irq]); 515 } 516 break; 517 default: 518 g_assert_not_reached(); 519 } 520 } 521 522 static void arm_cpu_kvm_set_irq(void *opaque, int irq, int level) 523 { 524 #ifdef CONFIG_KVM 525 ARMCPU *cpu = opaque; 526 CPUARMState *env = &cpu->env; 527 CPUState *cs = CPU(cpu); 528 int kvm_irq = KVM_ARM_IRQ_TYPE_CPU << KVM_ARM_IRQ_TYPE_SHIFT; 529 uint32_t linestate_bit; 530 531 switch (irq) { 532 case ARM_CPU_IRQ: 533 kvm_irq |= KVM_ARM_IRQ_CPU_IRQ; 534 linestate_bit = CPU_INTERRUPT_HARD; 535 break; 536 case ARM_CPU_FIQ: 537 kvm_irq |= KVM_ARM_IRQ_CPU_FIQ; 538 linestate_bit = CPU_INTERRUPT_FIQ; 539 break; 540 default: 541 g_assert_not_reached(); 542 } 543 544 if (level) { 545 env->irq_line_state |= linestate_bit; 546 } else { 547 env->irq_line_state &= ~linestate_bit; 548 } 549 550 kvm_irq |= cs->cpu_index << KVM_ARM_IRQ_VCPU_SHIFT; 551 kvm_set_irq(kvm_state, kvm_irq, level ? 1 : 0); 552 #endif 553 } 554 555 static bool arm_cpu_virtio_is_big_endian(CPUState *cs) 556 { 557 ARMCPU *cpu = ARM_CPU(cs); 558 CPUARMState *env = &cpu->env; 559 560 cpu_synchronize_state(cs); 561 return arm_cpu_data_is_big_endian(env); 562 } 563 564 #endif 565 566 static inline void set_feature(CPUARMState *env, int feature) 567 { 568 env->features |= 1ULL << feature; 569 } 570 571 static inline void unset_feature(CPUARMState *env, int feature) 572 { 573 env->features &= ~(1ULL << feature); 574 } 575 576 static int 577 print_insn_thumb1(bfd_vma pc, disassemble_info *info) 578 { 579 return print_insn_arm(pc | 1, info); 580 } 581 582 static void arm_disas_set_info(CPUState *cpu, disassemble_info *info) 583 { 584 ARMCPU *ac = ARM_CPU(cpu); 585 CPUARMState *env = &ac->env; 586 bool sctlr_b; 587 588 if (is_a64(env)) { 589 /* We might not be compiled with the A64 disassembler 590 * because it needs a C++ compiler. Leave print_insn 591 * unset in this case to use the caller default behaviour. 592 */ 593 #if defined(CONFIG_ARM_A64_DIS) 594 info->print_insn = print_insn_arm_a64; 595 #endif 596 info->cap_arch = CS_ARCH_ARM64; 597 info->cap_insn_unit = 4; 598 info->cap_insn_split = 4; 599 } else { 600 int cap_mode; 601 if (env->thumb) { 602 info->print_insn = print_insn_thumb1; 603 info->cap_insn_unit = 2; 604 info->cap_insn_split = 4; 605 cap_mode = CS_MODE_THUMB; 606 } else { 607 info->print_insn = print_insn_arm; 608 info->cap_insn_unit = 4; 609 info->cap_insn_split = 4; 610 cap_mode = CS_MODE_ARM; 611 } 612 if (arm_feature(env, ARM_FEATURE_V8)) { 613 cap_mode |= CS_MODE_V8; 614 } 615 if (arm_feature(env, ARM_FEATURE_M)) { 616 cap_mode |= CS_MODE_MCLASS; 617 } 618 info->cap_arch = CS_ARCH_ARM; 619 info->cap_mode = cap_mode; 620 } 621 622 sctlr_b = arm_sctlr_b(env); 623 if (bswap_code(sctlr_b)) { 624 #ifdef TARGET_WORDS_BIGENDIAN 625 info->endian = BFD_ENDIAN_LITTLE; 626 #else 627 info->endian = BFD_ENDIAN_BIG; 628 #endif 629 } 630 info->flags &= ~INSN_ARM_BE32; 631 #ifndef CONFIG_USER_ONLY 632 if (sctlr_b) { 633 info->flags |= INSN_ARM_BE32; 634 } 635 #endif 636 } 637 638 uint64_t arm_cpu_mp_affinity(int idx, uint8_t clustersz) 639 { 640 uint32_t Aff1 = idx / clustersz; 641 uint32_t Aff0 = idx % clustersz; 642 return (Aff1 << ARM_AFF1_SHIFT) | Aff0; 643 } 644 645 static void cpreg_hashtable_data_destroy(gpointer data) 646 { 647 /* 648 * Destroy function for cpu->cp_regs hashtable data entries. 649 * We must free the name string because it was g_strdup()ed in 650 * add_cpreg_to_hashtable(). It's OK to cast away the 'const' 651 * from r->name because we know we definitely allocated it. 652 */ 653 ARMCPRegInfo *r = data; 654 655 g_free((void *)r->name); 656 g_free(r); 657 } 658 659 static void arm_cpu_initfn(Object *obj) 660 { 661 CPUState *cs = CPU(obj); 662 ARMCPU *cpu = ARM_CPU(obj); 663 664 cs->env_ptr = &cpu->env; 665 cpu->cp_regs = g_hash_table_new_full(g_int_hash, g_int_equal, 666 g_free, cpreg_hashtable_data_destroy); 667 668 QLIST_INIT(&cpu->pre_el_change_hooks); 669 QLIST_INIT(&cpu->el_change_hooks); 670 671 #ifndef CONFIG_USER_ONLY 672 /* Our inbound IRQ and FIQ lines */ 673 if (kvm_enabled()) { 674 /* VIRQ and VFIQ are unused with KVM but we add them to maintain 675 * the same interface as non-KVM CPUs. 676 */ 677 qdev_init_gpio_in(DEVICE(cpu), arm_cpu_kvm_set_irq, 4); 678 } else { 679 qdev_init_gpio_in(DEVICE(cpu), arm_cpu_set_irq, 4); 680 } 681 682 qdev_init_gpio_out(DEVICE(cpu), cpu->gt_timer_outputs, 683 ARRAY_SIZE(cpu->gt_timer_outputs)); 684 685 qdev_init_gpio_out_named(DEVICE(cpu), &cpu->gicv3_maintenance_interrupt, 686 "gicv3-maintenance-interrupt", 1); 687 qdev_init_gpio_out_named(DEVICE(cpu), &cpu->pmu_interrupt, 688 "pmu-interrupt", 1); 689 #endif 690 691 /* DTB consumers generally don't in fact care what the 'compatible' 692 * string is, so always provide some string and trust that a hypothetical 693 * picky DTB consumer will also provide a helpful error message. 694 */ 695 cpu->dtb_compatible = "qemu,unknown"; 696 cpu->psci_version = 1; /* By default assume PSCI v0.1 */ 697 cpu->kvm_target = QEMU_KVM_ARM_TARGET_NONE; 698 699 if (tcg_enabled()) { 700 cpu->psci_version = 2; /* TCG implements PSCI 0.2 */ 701 } 702 } 703 704 static Property arm_cpu_reset_cbar_property = 705 DEFINE_PROP_UINT64("reset-cbar", ARMCPU, reset_cbar, 0); 706 707 static Property arm_cpu_reset_hivecs_property = 708 DEFINE_PROP_BOOL("reset-hivecs", ARMCPU, reset_hivecs, false); 709 710 static Property arm_cpu_rvbar_property = 711 DEFINE_PROP_UINT64("rvbar", ARMCPU, rvbar, 0); 712 713 static Property arm_cpu_has_el2_property = 714 DEFINE_PROP_BOOL("has_el2", ARMCPU, has_el2, true); 715 716 static Property arm_cpu_has_el3_property = 717 DEFINE_PROP_BOOL("has_el3", ARMCPU, has_el3, true); 718 719 static Property arm_cpu_cfgend_property = 720 DEFINE_PROP_BOOL("cfgend", ARMCPU, cfgend, false); 721 722 /* use property name "pmu" to match other archs and virt tools */ 723 static Property arm_cpu_has_pmu_property = 724 DEFINE_PROP_BOOL("pmu", ARMCPU, has_pmu, true); 725 726 static Property arm_cpu_has_mpu_property = 727 DEFINE_PROP_BOOL("has-mpu", ARMCPU, has_mpu, true); 728 729 /* This is like DEFINE_PROP_UINT32 but it doesn't set the default value, 730 * because the CPU initfn will have already set cpu->pmsav7_dregion to 731 * the right value for that particular CPU type, and we don't want 732 * to override that with an incorrect constant value. 733 */ 734 static Property arm_cpu_pmsav7_dregion_property = 735 DEFINE_PROP_UNSIGNED_NODEFAULT("pmsav7-dregion", ARMCPU, 736 pmsav7_dregion, 737 qdev_prop_uint32, uint32_t); 738 739 /* M profile: initial value of the Secure VTOR */ 740 static Property arm_cpu_initsvtor_property = 741 DEFINE_PROP_UINT32("init-svtor", ARMCPU, init_svtor, 0); 742 743 static void arm_cpu_post_init(Object *obj) 744 { 745 ARMCPU *cpu = ARM_CPU(obj); 746 747 /* M profile implies PMSA. We have to do this here rather than 748 * in realize with the other feature-implication checks because 749 * we look at the PMSA bit to see if we should add some properties. 750 */ 751 if (arm_feature(&cpu->env, ARM_FEATURE_M)) { 752 set_feature(&cpu->env, ARM_FEATURE_PMSA); 753 } 754 755 if (arm_feature(&cpu->env, ARM_FEATURE_CBAR) || 756 arm_feature(&cpu->env, ARM_FEATURE_CBAR_RO)) { 757 qdev_property_add_static(DEVICE(obj), &arm_cpu_reset_cbar_property, 758 &error_abort); 759 } 760 761 if (!arm_feature(&cpu->env, ARM_FEATURE_M)) { 762 qdev_property_add_static(DEVICE(obj), &arm_cpu_reset_hivecs_property, 763 &error_abort); 764 } 765 766 if (arm_feature(&cpu->env, ARM_FEATURE_AARCH64)) { 767 qdev_property_add_static(DEVICE(obj), &arm_cpu_rvbar_property, 768 &error_abort); 769 } 770 771 if (arm_feature(&cpu->env, ARM_FEATURE_EL3)) { 772 /* Add the has_el3 state CPU property only if EL3 is allowed. This will 773 * prevent "has_el3" from existing on CPUs which cannot support EL3. 774 */ 775 qdev_property_add_static(DEVICE(obj), &arm_cpu_has_el3_property, 776 &error_abort); 777 778 #ifndef CONFIG_USER_ONLY 779 object_property_add_link(obj, "secure-memory", 780 TYPE_MEMORY_REGION, 781 (Object **)&cpu->secure_memory, 782 qdev_prop_allow_set_link_before_realize, 783 OBJ_PROP_LINK_STRONG, 784 &error_abort); 785 #endif 786 } 787 788 if (arm_feature(&cpu->env, ARM_FEATURE_EL2)) { 789 qdev_property_add_static(DEVICE(obj), &arm_cpu_has_el2_property, 790 &error_abort); 791 } 792 793 if (arm_feature(&cpu->env, ARM_FEATURE_PMU)) { 794 qdev_property_add_static(DEVICE(obj), &arm_cpu_has_pmu_property, 795 &error_abort); 796 } 797 798 if (arm_feature(&cpu->env, ARM_FEATURE_PMSA)) { 799 qdev_property_add_static(DEVICE(obj), &arm_cpu_has_mpu_property, 800 &error_abort); 801 if (arm_feature(&cpu->env, ARM_FEATURE_V7)) { 802 qdev_property_add_static(DEVICE(obj), 803 &arm_cpu_pmsav7_dregion_property, 804 &error_abort); 805 } 806 } 807 808 if (arm_feature(&cpu->env, ARM_FEATURE_M_SECURITY)) { 809 object_property_add_link(obj, "idau", TYPE_IDAU_INTERFACE, &cpu->idau, 810 qdev_prop_allow_set_link_before_realize, 811 OBJ_PROP_LINK_STRONG, 812 &error_abort); 813 qdev_property_add_static(DEVICE(obj), &arm_cpu_initsvtor_property, 814 &error_abort); 815 } 816 817 qdev_property_add_static(DEVICE(obj), &arm_cpu_cfgend_property, 818 &error_abort); 819 } 820 821 static void arm_cpu_finalizefn(Object *obj) 822 { 823 ARMCPU *cpu = ARM_CPU(obj); 824 ARMELChangeHook *hook, *next; 825 826 g_hash_table_destroy(cpu->cp_regs); 827 828 QLIST_FOREACH_SAFE(hook, &cpu->pre_el_change_hooks, node, next) { 829 QLIST_REMOVE(hook, node); 830 g_free(hook); 831 } 832 QLIST_FOREACH_SAFE(hook, &cpu->el_change_hooks, node, next) { 833 QLIST_REMOVE(hook, node); 834 g_free(hook); 835 } 836 } 837 838 static void arm_cpu_realizefn(DeviceState *dev, Error **errp) 839 { 840 CPUState *cs = CPU(dev); 841 ARMCPU *cpu = ARM_CPU(dev); 842 ARMCPUClass *acc = ARM_CPU_GET_CLASS(dev); 843 CPUARMState *env = &cpu->env; 844 int pagebits; 845 Error *local_err = NULL; 846 bool no_aa32 = false; 847 848 /* If we needed to query the host kernel for the CPU features 849 * then it's possible that might have failed in the initfn, but 850 * this is the first point where we can report it. 851 */ 852 if (cpu->host_cpu_probe_failed) { 853 if (!kvm_enabled()) { 854 error_setg(errp, "The 'host' CPU type can only be used with KVM"); 855 } else { 856 error_setg(errp, "Failed to retrieve host CPU features"); 857 } 858 return; 859 } 860 861 #ifndef CONFIG_USER_ONLY 862 /* The NVIC and M-profile CPU are two halves of a single piece of 863 * hardware; trying to use one without the other is a command line 864 * error and will result in segfaults if not caught here. 865 */ 866 if (arm_feature(env, ARM_FEATURE_M)) { 867 if (!env->nvic) { 868 error_setg(errp, "This board cannot be used with Cortex-M CPUs"); 869 return; 870 } 871 } else { 872 if (env->nvic) { 873 error_setg(errp, "This board can only be used with Cortex-M CPUs"); 874 return; 875 } 876 } 877 878 cpu->gt_timer[GTIMER_PHYS] = timer_new(QEMU_CLOCK_VIRTUAL, GTIMER_SCALE, 879 arm_gt_ptimer_cb, cpu); 880 cpu->gt_timer[GTIMER_VIRT] = timer_new(QEMU_CLOCK_VIRTUAL, GTIMER_SCALE, 881 arm_gt_vtimer_cb, cpu); 882 cpu->gt_timer[GTIMER_HYP] = timer_new(QEMU_CLOCK_VIRTUAL, GTIMER_SCALE, 883 arm_gt_htimer_cb, cpu); 884 cpu->gt_timer[GTIMER_SEC] = timer_new(QEMU_CLOCK_VIRTUAL, GTIMER_SCALE, 885 arm_gt_stimer_cb, cpu); 886 #endif 887 888 cpu_exec_realizefn(cs, &local_err); 889 if (local_err != NULL) { 890 error_propagate(errp, local_err); 891 return; 892 } 893 894 /* Some features automatically imply others: */ 895 if (arm_feature(env, ARM_FEATURE_V8)) { 896 if (arm_feature(env, ARM_FEATURE_M)) { 897 set_feature(env, ARM_FEATURE_V7); 898 } else { 899 set_feature(env, ARM_FEATURE_V7VE); 900 } 901 } 902 903 /* 904 * There exist AArch64 cpus without AArch32 support. When KVM 905 * queries ID_ISAR0_EL1 on such a host, the value is UNKNOWN. 906 * Similarly, we cannot check ID_AA64PFR0 without AArch64 support. 907 */ 908 if (arm_feature(&cpu->env, ARM_FEATURE_AARCH64)) { 909 no_aa32 = !cpu_isar_feature(aa64_aa32, cpu); 910 } 911 912 if (arm_feature(env, ARM_FEATURE_V7VE)) { 913 /* v7 Virtualization Extensions. In real hardware this implies 914 * EL2 and also the presence of the Security Extensions. 915 * For QEMU, for backwards-compatibility we implement some 916 * CPUs or CPU configs which have no actual EL2 or EL3 but do 917 * include the various other features that V7VE implies. 918 * Presence of EL2 itself is ARM_FEATURE_EL2, and of the 919 * Security Extensions is ARM_FEATURE_EL3. 920 */ 921 assert(no_aa32 || cpu_isar_feature(arm_div, cpu)); 922 set_feature(env, ARM_FEATURE_LPAE); 923 set_feature(env, ARM_FEATURE_V7); 924 } 925 if (arm_feature(env, ARM_FEATURE_V7)) { 926 set_feature(env, ARM_FEATURE_VAPA); 927 set_feature(env, ARM_FEATURE_THUMB2); 928 set_feature(env, ARM_FEATURE_MPIDR); 929 if (!arm_feature(env, ARM_FEATURE_M)) { 930 set_feature(env, ARM_FEATURE_V6K); 931 } else { 932 set_feature(env, ARM_FEATURE_V6); 933 } 934 935 /* Always define VBAR for V7 CPUs even if it doesn't exist in 936 * non-EL3 configs. This is needed by some legacy boards. 937 */ 938 set_feature(env, ARM_FEATURE_VBAR); 939 } 940 if (arm_feature(env, ARM_FEATURE_V6K)) { 941 set_feature(env, ARM_FEATURE_V6); 942 set_feature(env, ARM_FEATURE_MVFR); 943 } 944 if (arm_feature(env, ARM_FEATURE_V6)) { 945 set_feature(env, ARM_FEATURE_V5); 946 if (!arm_feature(env, ARM_FEATURE_M)) { 947 assert(no_aa32 || cpu_isar_feature(jazelle, cpu)); 948 set_feature(env, ARM_FEATURE_AUXCR); 949 } 950 } 951 if (arm_feature(env, ARM_FEATURE_V5)) { 952 set_feature(env, ARM_FEATURE_V4T); 953 } 954 if (arm_feature(env, ARM_FEATURE_VFP4)) { 955 set_feature(env, ARM_FEATURE_VFP3); 956 set_feature(env, ARM_FEATURE_VFP_FP16); 957 } 958 if (arm_feature(env, ARM_FEATURE_VFP3)) { 959 set_feature(env, ARM_FEATURE_VFP); 960 } 961 if (arm_feature(env, ARM_FEATURE_LPAE)) { 962 set_feature(env, ARM_FEATURE_V7MP); 963 set_feature(env, ARM_FEATURE_PXN); 964 } 965 if (arm_feature(env, ARM_FEATURE_CBAR_RO)) { 966 set_feature(env, ARM_FEATURE_CBAR); 967 } 968 if (arm_feature(env, ARM_FEATURE_THUMB2) && 969 !arm_feature(env, ARM_FEATURE_M)) { 970 set_feature(env, ARM_FEATURE_THUMB_DSP); 971 } 972 973 if (arm_feature(env, ARM_FEATURE_V7) && 974 !arm_feature(env, ARM_FEATURE_M) && 975 !arm_feature(env, ARM_FEATURE_PMSA)) { 976 /* v7VMSA drops support for the old ARMv5 tiny pages, so we 977 * can use 4K pages. 978 */ 979 pagebits = 12; 980 } else { 981 /* For CPUs which might have tiny 1K pages, or which have an 982 * MPU and might have small region sizes, stick with 1K pages. 983 */ 984 pagebits = 10; 985 } 986 if (!set_preferred_target_page_bits(pagebits)) { 987 /* This can only ever happen for hotplugging a CPU, or if 988 * the board code incorrectly creates a CPU which it has 989 * promised via minimum_page_size that it will not. 990 */ 991 error_setg(errp, "This CPU requires a smaller page size than the " 992 "system is using"); 993 return; 994 } 995 996 /* This cpu-id-to-MPIDR affinity is used only for TCG; KVM will override it. 997 * We don't support setting cluster ID ([16..23]) (known as Aff2 998 * in later ARM ARM versions), or any of the higher affinity level fields, 999 * so these bits always RAZ. 1000 */ 1001 if (cpu->mp_affinity == ARM64_AFFINITY_INVALID) { 1002 cpu->mp_affinity = arm_cpu_mp_affinity(cs->cpu_index, 1003 ARM_DEFAULT_CPUS_PER_CLUSTER); 1004 } 1005 1006 if (cpu->reset_hivecs) { 1007 cpu->reset_sctlr |= (1 << 13); 1008 } 1009 1010 if (cpu->cfgend) { 1011 if (arm_feature(&cpu->env, ARM_FEATURE_V7)) { 1012 cpu->reset_sctlr |= SCTLR_EE; 1013 } else { 1014 cpu->reset_sctlr |= SCTLR_B; 1015 } 1016 } 1017 1018 if (!cpu->has_el3) { 1019 /* If the has_el3 CPU property is disabled then we need to disable the 1020 * feature. 1021 */ 1022 unset_feature(env, ARM_FEATURE_EL3); 1023 1024 /* Disable the security extension feature bits in the processor feature 1025 * registers as well. These are id_pfr1[7:4] and id_aa64pfr0[15:12]. 1026 */ 1027 cpu->id_pfr1 &= ~0xf0; 1028 cpu->isar.id_aa64pfr0 &= ~0xf000; 1029 } 1030 1031 if (!cpu->has_el2) { 1032 unset_feature(env, ARM_FEATURE_EL2); 1033 } 1034 1035 if (!cpu->has_pmu) { 1036 unset_feature(env, ARM_FEATURE_PMU); 1037 cpu->id_aa64dfr0 &= ~0xf00; 1038 } 1039 1040 if (!arm_feature(env, ARM_FEATURE_EL2)) { 1041 /* Disable the hypervisor feature bits in the processor feature 1042 * registers if we don't have EL2. These are id_pfr1[15:12] and 1043 * id_aa64pfr0_el1[11:8]. 1044 */ 1045 cpu->isar.id_aa64pfr0 &= ~0xf00; 1046 cpu->id_pfr1 &= ~0xf000; 1047 } 1048 1049 /* MPU can be configured out of a PMSA CPU either by setting has-mpu 1050 * to false or by setting pmsav7-dregion to 0. 1051 */ 1052 if (!cpu->has_mpu) { 1053 cpu->pmsav7_dregion = 0; 1054 } 1055 if (cpu->pmsav7_dregion == 0) { 1056 cpu->has_mpu = false; 1057 } 1058 1059 if (arm_feature(env, ARM_FEATURE_PMSA) && 1060 arm_feature(env, ARM_FEATURE_V7)) { 1061 uint32_t nr = cpu->pmsav7_dregion; 1062 1063 if (nr > 0xff) { 1064 error_setg(errp, "PMSAv7 MPU #regions invalid %" PRIu32, nr); 1065 return; 1066 } 1067 1068 if (nr) { 1069 if (arm_feature(env, ARM_FEATURE_V8)) { 1070 /* PMSAv8 */ 1071 env->pmsav8.rbar[M_REG_NS] = g_new0(uint32_t, nr); 1072 env->pmsav8.rlar[M_REG_NS] = g_new0(uint32_t, nr); 1073 if (arm_feature(env, ARM_FEATURE_M_SECURITY)) { 1074 env->pmsav8.rbar[M_REG_S] = g_new0(uint32_t, nr); 1075 env->pmsav8.rlar[M_REG_S] = g_new0(uint32_t, nr); 1076 } 1077 } else { 1078 env->pmsav7.drbar = g_new0(uint32_t, nr); 1079 env->pmsav7.drsr = g_new0(uint32_t, nr); 1080 env->pmsav7.dracr = g_new0(uint32_t, nr); 1081 } 1082 } 1083 } 1084 1085 if (arm_feature(env, ARM_FEATURE_M_SECURITY)) { 1086 uint32_t nr = cpu->sau_sregion; 1087 1088 if (nr > 0xff) { 1089 error_setg(errp, "v8M SAU #regions invalid %" PRIu32, nr); 1090 return; 1091 } 1092 1093 if (nr) { 1094 env->sau.rbar = g_new0(uint32_t, nr); 1095 env->sau.rlar = g_new0(uint32_t, nr); 1096 } 1097 } 1098 1099 if (arm_feature(env, ARM_FEATURE_EL3)) { 1100 set_feature(env, ARM_FEATURE_VBAR); 1101 } 1102 1103 register_cp_regs_for_features(cpu); 1104 arm_cpu_register_gdb_regs_for_features(cpu); 1105 1106 init_cpreg_list(cpu); 1107 1108 #ifndef CONFIG_USER_ONLY 1109 if (cpu->has_el3 || arm_feature(env, ARM_FEATURE_M_SECURITY)) { 1110 cs->num_ases = 2; 1111 1112 if (!cpu->secure_memory) { 1113 cpu->secure_memory = cs->memory; 1114 } 1115 cpu_address_space_init(cs, ARMASIdx_S, "cpu-secure-memory", 1116 cpu->secure_memory); 1117 } else { 1118 cs->num_ases = 1; 1119 } 1120 cpu_address_space_init(cs, ARMASIdx_NS, "cpu-memory", cs->memory); 1121 1122 /* No core_count specified, default to smp_cpus. */ 1123 if (cpu->core_count == -1) { 1124 cpu->core_count = smp_cpus; 1125 } 1126 #endif 1127 1128 qemu_init_vcpu(cs); 1129 cpu_reset(cs); 1130 1131 acc->parent_realize(dev, errp); 1132 } 1133 1134 static ObjectClass *arm_cpu_class_by_name(const char *cpu_model) 1135 { 1136 ObjectClass *oc; 1137 char *typename; 1138 char **cpuname; 1139 const char *cpunamestr; 1140 1141 cpuname = g_strsplit(cpu_model, ",", 1); 1142 cpunamestr = cpuname[0]; 1143 #ifdef CONFIG_USER_ONLY 1144 /* For backwards compatibility usermode emulation allows "-cpu any", 1145 * which has the same semantics as "-cpu max". 1146 */ 1147 if (!strcmp(cpunamestr, "any")) { 1148 cpunamestr = "max"; 1149 } 1150 #endif 1151 typename = g_strdup_printf(ARM_CPU_TYPE_NAME("%s"), cpunamestr); 1152 oc = object_class_by_name(typename); 1153 g_strfreev(cpuname); 1154 g_free(typename); 1155 if (!oc || !object_class_dynamic_cast(oc, TYPE_ARM_CPU) || 1156 object_class_is_abstract(oc)) { 1157 return NULL; 1158 } 1159 return oc; 1160 } 1161 1162 /* CPU models. These are not needed for the AArch64 linux-user build. */ 1163 #if !defined(CONFIG_USER_ONLY) || !defined(TARGET_AARCH64) 1164 1165 static void arm926_initfn(Object *obj) 1166 { 1167 ARMCPU *cpu = ARM_CPU(obj); 1168 1169 cpu->dtb_compatible = "arm,arm926"; 1170 set_feature(&cpu->env, ARM_FEATURE_V5); 1171 set_feature(&cpu->env, ARM_FEATURE_VFP); 1172 set_feature(&cpu->env, ARM_FEATURE_DUMMY_C15_REGS); 1173 set_feature(&cpu->env, ARM_FEATURE_CACHE_TEST_CLEAN); 1174 cpu->midr = 0x41069265; 1175 cpu->reset_fpsid = 0x41011090; 1176 cpu->ctr = 0x1dd20d2; 1177 cpu->reset_sctlr = 0x00090078; 1178 1179 /* 1180 * ARMv5 does not have the ID_ISAR registers, but we can still 1181 * set the field to indicate Jazelle support within QEMU. 1182 */ 1183 cpu->isar.id_isar1 = FIELD_DP32(cpu->isar.id_isar1, ID_ISAR1, JAZELLE, 1); 1184 } 1185 1186 static void arm946_initfn(Object *obj) 1187 { 1188 ARMCPU *cpu = ARM_CPU(obj); 1189 1190 cpu->dtb_compatible = "arm,arm946"; 1191 set_feature(&cpu->env, ARM_FEATURE_V5); 1192 set_feature(&cpu->env, ARM_FEATURE_PMSA); 1193 set_feature(&cpu->env, ARM_FEATURE_DUMMY_C15_REGS); 1194 cpu->midr = 0x41059461; 1195 cpu->ctr = 0x0f004006; 1196 cpu->reset_sctlr = 0x00000078; 1197 } 1198 1199 static void arm1026_initfn(Object *obj) 1200 { 1201 ARMCPU *cpu = ARM_CPU(obj); 1202 1203 cpu->dtb_compatible = "arm,arm1026"; 1204 set_feature(&cpu->env, ARM_FEATURE_V5); 1205 set_feature(&cpu->env, ARM_FEATURE_VFP); 1206 set_feature(&cpu->env, ARM_FEATURE_AUXCR); 1207 set_feature(&cpu->env, ARM_FEATURE_DUMMY_C15_REGS); 1208 set_feature(&cpu->env, ARM_FEATURE_CACHE_TEST_CLEAN); 1209 cpu->midr = 0x4106a262; 1210 cpu->reset_fpsid = 0x410110a0; 1211 cpu->ctr = 0x1dd20d2; 1212 cpu->reset_sctlr = 0x00090078; 1213 cpu->reset_auxcr = 1; 1214 1215 /* 1216 * ARMv5 does not have the ID_ISAR registers, but we can still 1217 * set the field to indicate Jazelle support within QEMU. 1218 */ 1219 cpu->isar.id_isar1 = FIELD_DP32(cpu->isar.id_isar1, ID_ISAR1, JAZELLE, 1); 1220 1221 { 1222 /* The 1026 had an IFAR at c6,c0,0,1 rather than the ARMv6 c6,c0,0,2 */ 1223 ARMCPRegInfo ifar = { 1224 .name = "IFAR", .cp = 15, .crn = 6, .crm = 0, .opc1 = 0, .opc2 = 1, 1225 .access = PL1_RW, 1226 .fieldoffset = offsetof(CPUARMState, cp15.ifar_ns), 1227 .resetvalue = 0 1228 }; 1229 define_one_arm_cp_reg(cpu, &ifar); 1230 } 1231 } 1232 1233 static void arm1136_r2_initfn(Object *obj) 1234 { 1235 ARMCPU *cpu = ARM_CPU(obj); 1236 /* What qemu calls "arm1136_r2" is actually the 1136 r0p2, ie an 1237 * older core than plain "arm1136". In particular this does not 1238 * have the v6K features. 1239 * These ID register values are correct for 1136 but may be wrong 1240 * for 1136_r2 (in particular r0p2 does not actually implement most 1241 * of the ID registers). 1242 */ 1243 1244 cpu->dtb_compatible = "arm,arm1136"; 1245 set_feature(&cpu->env, ARM_FEATURE_V6); 1246 set_feature(&cpu->env, ARM_FEATURE_VFP); 1247 set_feature(&cpu->env, ARM_FEATURE_DUMMY_C15_REGS); 1248 set_feature(&cpu->env, ARM_FEATURE_CACHE_DIRTY_REG); 1249 set_feature(&cpu->env, ARM_FEATURE_CACHE_BLOCK_OPS); 1250 cpu->midr = 0x4107b362; 1251 cpu->reset_fpsid = 0x410120b4; 1252 cpu->isar.mvfr0 = 0x11111111; 1253 cpu->isar.mvfr1 = 0x00000000; 1254 cpu->ctr = 0x1dd20d2; 1255 cpu->reset_sctlr = 0x00050078; 1256 cpu->id_pfr0 = 0x111; 1257 cpu->id_pfr1 = 0x1; 1258 cpu->id_dfr0 = 0x2; 1259 cpu->id_afr0 = 0x3; 1260 cpu->id_mmfr0 = 0x01130003; 1261 cpu->id_mmfr1 = 0x10030302; 1262 cpu->id_mmfr2 = 0x01222110; 1263 cpu->isar.id_isar0 = 0x00140011; 1264 cpu->isar.id_isar1 = 0x12002111; 1265 cpu->isar.id_isar2 = 0x11231111; 1266 cpu->isar.id_isar3 = 0x01102131; 1267 cpu->isar.id_isar4 = 0x141; 1268 cpu->reset_auxcr = 7; 1269 } 1270 1271 static void arm1136_initfn(Object *obj) 1272 { 1273 ARMCPU *cpu = ARM_CPU(obj); 1274 1275 cpu->dtb_compatible = "arm,arm1136"; 1276 set_feature(&cpu->env, ARM_FEATURE_V6K); 1277 set_feature(&cpu->env, ARM_FEATURE_V6); 1278 set_feature(&cpu->env, ARM_FEATURE_VFP); 1279 set_feature(&cpu->env, ARM_FEATURE_DUMMY_C15_REGS); 1280 set_feature(&cpu->env, ARM_FEATURE_CACHE_DIRTY_REG); 1281 set_feature(&cpu->env, ARM_FEATURE_CACHE_BLOCK_OPS); 1282 cpu->midr = 0x4117b363; 1283 cpu->reset_fpsid = 0x410120b4; 1284 cpu->isar.mvfr0 = 0x11111111; 1285 cpu->isar.mvfr1 = 0x00000000; 1286 cpu->ctr = 0x1dd20d2; 1287 cpu->reset_sctlr = 0x00050078; 1288 cpu->id_pfr0 = 0x111; 1289 cpu->id_pfr1 = 0x1; 1290 cpu->id_dfr0 = 0x2; 1291 cpu->id_afr0 = 0x3; 1292 cpu->id_mmfr0 = 0x01130003; 1293 cpu->id_mmfr1 = 0x10030302; 1294 cpu->id_mmfr2 = 0x01222110; 1295 cpu->isar.id_isar0 = 0x00140011; 1296 cpu->isar.id_isar1 = 0x12002111; 1297 cpu->isar.id_isar2 = 0x11231111; 1298 cpu->isar.id_isar3 = 0x01102131; 1299 cpu->isar.id_isar4 = 0x141; 1300 cpu->reset_auxcr = 7; 1301 } 1302 1303 static void arm1176_initfn(Object *obj) 1304 { 1305 ARMCPU *cpu = ARM_CPU(obj); 1306 1307 cpu->dtb_compatible = "arm,arm1176"; 1308 set_feature(&cpu->env, ARM_FEATURE_V6K); 1309 set_feature(&cpu->env, ARM_FEATURE_VFP); 1310 set_feature(&cpu->env, ARM_FEATURE_VAPA); 1311 set_feature(&cpu->env, ARM_FEATURE_DUMMY_C15_REGS); 1312 set_feature(&cpu->env, ARM_FEATURE_CACHE_DIRTY_REG); 1313 set_feature(&cpu->env, ARM_FEATURE_CACHE_BLOCK_OPS); 1314 set_feature(&cpu->env, ARM_FEATURE_EL3); 1315 cpu->midr = 0x410fb767; 1316 cpu->reset_fpsid = 0x410120b5; 1317 cpu->isar.mvfr0 = 0x11111111; 1318 cpu->isar.mvfr1 = 0x00000000; 1319 cpu->ctr = 0x1dd20d2; 1320 cpu->reset_sctlr = 0x00050078; 1321 cpu->id_pfr0 = 0x111; 1322 cpu->id_pfr1 = 0x11; 1323 cpu->id_dfr0 = 0x33; 1324 cpu->id_afr0 = 0; 1325 cpu->id_mmfr0 = 0x01130003; 1326 cpu->id_mmfr1 = 0x10030302; 1327 cpu->id_mmfr2 = 0x01222100; 1328 cpu->isar.id_isar0 = 0x0140011; 1329 cpu->isar.id_isar1 = 0x12002111; 1330 cpu->isar.id_isar2 = 0x11231121; 1331 cpu->isar.id_isar3 = 0x01102131; 1332 cpu->isar.id_isar4 = 0x01141; 1333 cpu->reset_auxcr = 7; 1334 } 1335 1336 static void arm11mpcore_initfn(Object *obj) 1337 { 1338 ARMCPU *cpu = ARM_CPU(obj); 1339 1340 cpu->dtb_compatible = "arm,arm11mpcore"; 1341 set_feature(&cpu->env, ARM_FEATURE_V6K); 1342 set_feature(&cpu->env, ARM_FEATURE_VFP); 1343 set_feature(&cpu->env, ARM_FEATURE_VAPA); 1344 set_feature(&cpu->env, ARM_FEATURE_MPIDR); 1345 set_feature(&cpu->env, ARM_FEATURE_DUMMY_C15_REGS); 1346 cpu->midr = 0x410fb022; 1347 cpu->reset_fpsid = 0x410120b4; 1348 cpu->isar.mvfr0 = 0x11111111; 1349 cpu->isar.mvfr1 = 0x00000000; 1350 cpu->ctr = 0x1d192992; /* 32K icache 32K dcache */ 1351 cpu->id_pfr0 = 0x111; 1352 cpu->id_pfr1 = 0x1; 1353 cpu->id_dfr0 = 0; 1354 cpu->id_afr0 = 0x2; 1355 cpu->id_mmfr0 = 0x01100103; 1356 cpu->id_mmfr1 = 0x10020302; 1357 cpu->id_mmfr2 = 0x01222000; 1358 cpu->isar.id_isar0 = 0x00100011; 1359 cpu->isar.id_isar1 = 0x12002111; 1360 cpu->isar.id_isar2 = 0x11221011; 1361 cpu->isar.id_isar3 = 0x01102131; 1362 cpu->isar.id_isar4 = 0x141; 1363 cpu->reset_auxcr = 1; 1364 } 1365 1366 static void cortex_m0_initfn(Object *obj) 1367 { 1368 ARMCPU *cpu = ARM_CPU(obj); 1369 set_feature(&cpu->env, ARM_FEATURE_V6); 1370 set_feature(&cpu->env, ARM_FEATURE_M); 1371 1372 cpu->midr = 0x410cc200; 1373 } 1374 1375 static void cortex_m3_initfn(Object *obj) 1376 { 1377 ARMCPU *cpu = ARM_CPU(obj); 1378 set_feature(&cpu->env, ARM_FEATURE_V7); 1379 set_feature(&cpu->env, ARM_FEATURE_M); 1380 set_feature(&cpu->env, ARM_FEATURE_M_MAIN); 1381 cpu->midr = 0x410fc231; 1382 cpu->pmsav7_dregion = 8; 1383 cpu->id_pfr0 = 0x00000030; 1384 cpu->id_pfr1 = 0x00000200; 1385 cpu->id_dfr0 = 0x00100000; 1386 cpu->id_afr0 = 0x00000000; 1387 cpu->id_mmfr0 = 0x00000030; 1388 cpu->id_mmfr1 = 0x00000000; 1389 cpu->id_mmfr2 = 0x00000000; 1390 cpu->id_mmfr3 = 0x00000000; 1391 cpu->isar.id_isar0 = 0x01141110; 1392 cpu->isar.id_isar1 = 0x02111000; 1393 cpu->isar.id_isar2 = 0x21112231; 1394 cpu->isar.id_isar3 = 0x01111110; 1395 cpu->isar.id_isar4 = 0x01310102; 1396 cpu->isar.id_isar5 = 0x00000000; 1397 cpu->isar.id_isar6 = 0x00000000; 1398 } 1399 1400 static void cortex_m4_initfn(Object *obj) 1401 { 1402 ARMCPU *cpu = ARM_CPU(obj); 1403 1404 set_feature(&cpu->env, ARM_FEATURE_V7); 1405 set_feature(&cpu->env, ARM_FEATURE_M); 1406 set_feature(&cpu->env, ARM_FEATURE_M_MAIN); 1407 set_feature(&cpu->env, ARM_FEATURE_THUMB_DSP); 1408 cpu->midr = 0x410fc240; /* r0p0 */ 1409 cpu->pmsav7_dregion = 8; 1410 cpu->id_pfr0 = 0x00000030; 1411 cpu->id_pfr1 = 0x00000200; 1412 cpu->id_dfr0 = 0x00100000; 1413 cpu->id_afr0 = 0x00000000; 1414 cpu->id_mmfr0 = 0x00000030; 1415 cpu->id_mmfr1 = 0x00000000; 1416 cpu->id_mmfr2 = 0x00000000; 1417 cpu->id_mmfr3 = 0x00000000; 1418 cpu->isar.id_isar0 = 0x01141110; 1419 cpu->isar.id_isar1 = 0x02111000; 1420 cpu->isar.id_isar2 = 0x21112231; 1421 cpu->isar.id_isar3 = 0x01111110; 1422 cpu->isar.id_isar4 = 0x01310102; 1423 cpu->isar.id_isar5 = 0x00000000; 1424 cpu->isar.id_isar6 = 0x00000000; 1425 } 1426 1427 static void cortex_m33_initfn(Object *obj) 1428 { 1429 ARMCPU *cpu = ARM_CPU(obj); 1430 1431 set_feature(&cpu->env, ARM_FEATURE_V8); 1432 set_feature(&cpu->env, ARM_FEATURE_M); 1433 set_feature(&cpu->env, ARM_FEATURE_M_MAIN); 1434 set_feature(&cpu->env, ARM_FEATURE_M_SECURITY); 1435 set_feature(&cpu->env, ARM_FEATURE_THUMB_DSP); 1436 cpu->midr = 0x410fd213; /* r0p3 */ 1437 cpu->pmsav7_dregion = 16; 1438 cpu->sau_sregion = 8; 1439 cpu->id_pfr0 = 0x00000030; 1440 cpu->id_pfr1 = 0x00000210; 1441 cpu->id_dfr0 = 0x00200000; 1442 cpu->id_afr0 = 0x00000000; 1443 cpu->id_mmfr0 = 0x00101F40; 1444 cpu->id_mmfr1 = 0x00000000; 1445 cpu->id_mmfr2 = 0x01000000; 1446 cpu->id_mmfr3 = 0x00000000; 1447 cpu->isar.id_isar0 = 0x01101110; 1448 cpu->isar.id_isar1 = 0x02212000; 1449 cpu->isar.id_isar2 = 0x20232232; 1450 cpu->isar.id_isar3 = 0x01111131; 1451 cpu->isar.id_isar4 = 0x01310132; 1452 cpu->isar.id_isar5 = 0x00000000; 1453 cpu->isar.id_isar6 = 0x00000000; 1454 cpu->clidr = 0x00000000; 1455 cpu->ctr = 0x8000c000; 1456 } 1457 1458 static void arm_v7m_class_init(ObjectClass *oc, void *data) 1459 { 1460 CPUClass *cc = CPU_CLASS(oc); 1461 1462 #ifndef CONFIG_USER_ONLY 1463 cc->do_interrupt = arm_v7m_cpu_do_interrupt; 1464 #endif 1465 1466 cc->cpu_exec_interrupt = arm_v7m_cpu_exec_interrupt; 1467 } 1468 1469 static const ARMCPRegInfo cortexr5_cp_reginfo[] = { 1470 /* Dummy the TCM region regs for the moment */ 1471 { .name = "ATCM", .cp = 15, .opc1 = 0, .crn = 9, .crm = 1, .opc2 = 0, 1472 .access = PL1_RW, .type = ARM_CP_CONST }, 1473 { .name = "BTCM", .cp = 15, .opc1 = 0, .crn = 9, .crm = 1, .opc2 = 1, 1474 .access = PL1_RW, .type = ARM_CP_CONST }, 1475 { .name = "DCACHE_INVAL", .cp = 15, .opc1 = 0, .crn = 15, .crm = 5, 1476 .opc2 = 0, .access = PL1_W, .type = ARM_CP_NOP }, 1477 REGINFO_SENTINEL 1478 }; 1479 1480 static void cortex_r5_initfn(Object *obj) 1481 { 1482 ARMCPU *cpu = ARM_CPU(obj); 1483 1484 set_feature(&cpu->env, ARM_FEATURE_V7); 1485 set_feature(&cpu->env, ARM_FEATURE_V7MP); 1486 set_feature(&cpu->env, ARM_FEATURE_PMSA); 1487 cpu->midr = 0x411fc153; /* r1p3 */ 1488 cpu->id_pfr0 = 0x0131; 1489 cpu->id_pfr1 = 0x001; 1490 cpu->id_dfr0 = 0x010400; 1491 cpu->id_afr0 = 0x0; 1492 cpu->id_mmfr0 = 0x0210030; 1493 cpu->id_mmfr1 = 0x00000000; 1494 cpu->id_mmfr2 = 0x01200000; 1495 cpu->id_mmfr3 = 0x0211; 1496 cpu->isar.id_isar0 = 0x02101111; 1497 cpu->isar.id_isar1 = 0x13112111; 1498 cpu->isar.id_isar2 = 0x21232141; 1499 cpu->isar.id_isar3 = 0x01112131; 1500 cpu->isar.id_isar4 = 0x0010142; 1501 cpu->isar.id_isar5 = 0x0; 1502 cpu->isar.id_isar6 = 0x0; 1503 cpu->mp_is_up = true; 1504 cpu->pmsav7_dregion = 16; 1505 define_arm_cp_regs(cpu, cortexr5_cp_reginfo); 1506 } 1507 1508 static void cortex_r5f_initfn(Object *obj) 1509 { 1510 ARMCPU *cpu = ARM_CPU(obj); 1511 1512 cortex_r5_initfn(obj); 1513 set_feature(&cpu->env, ARM_FEATURE_VFP3); 1514 } 1515 1516 static const ARMCPRegInfo cortexa8_cp_reginfo[] = { 1517 { .name = "L2LOCKDOWN", .cp = 15, .crn = 9, .crm = 0, .opc1 = 1, .opc2 = 0, 1518 .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0 }, 1519 { .name = "L2AUXCR", .cp = 15, .crn = 9, .crm = 0, .opc1 = 1, .opc2 = 2, 1520 .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0 }, 1521 REGINFO_SENTINEL 1522 }; 1523 1524 static void cortex_a8_initfn(Object *obj) 1525 { 1526 ARMCPU *cpu = ARM_CPU(obj); 1527 1528 cpu->dtb_compatible = "arm,cortex-a8"; 1529 set_feature(&cpu->env, ARM_FEATURE_V7); 1530 set_feature(&cpu->env, ARM_FEATURE_VFP3); 1531 set_feature(&cpu->env, ARM_FEATURE_NEON); 1532 set_feature(&cpu->env, ARM_FEATURE_THUMB2EE); 1533 set_feature(&cpu->env, ARM_FEATURE_DUMMY_C15_REGS); 1534 set_feature(&cpu->env, ARM_FEATURE_EL3); 1535 cpu->midr = 0x410fc080; 1536 cpu->reset_fpsid = 0x410330c0; 1537 cpu->isar.mvfr0 = 0x11110222; 1538 cpu->isar.mvfr1 = 0x00011111; 1539 cpu->ctr = 0x82048004; 1540 cpu->reset_sctlr = 0x00c50078; 1541 cpu->id_pfr0 = 0x1031; 1542 cpu->id_pfr1 = 0x11; 1543 cpu->id_dfr0 = 0x400; 1544 cpu->id_afr0 = 0; 1545 cpu->id_mmfr0 = 0x31100003; 1546 cpu->id_mmfr1 = 0x20000000; 1547 cpu->id_mmfr2 = 0x01202000; 1548 cpu->id_mmfr3 = 0x11; 1549 cpu->isar.id_isar0 = 0x00101111; 1550 cpu->isar.id_isar1 = 0x12112111; 1551 cpu->isar.id_isar2 = 0x21232031; 1552 cpu->isar.id_isar3 = 0x11112131; 1553 cpu->isar.id_isar4 = 0x00111142; 1554 cpu->dbgdidr = 0x15141000; 1555 cpu->clidr = (1 << 27) | (2 << 24) | 3; 1556 cpu->ccsidr[0] = 0xe007e01a; /* 16k L1 dcache. */ 1557 cpu->ccsidr[1] = 0x2007e01a; /* 16k L1 icache. */ 1558 cpu->ccsidr[2] = 0xf0000000; /* No L2 icache. */ 1559 cpu->reset_auxcr = 2; 1560 define_arm_cp_regs(cpu, cortexa8_cp_reginfo); 1561 } 1562 1563 static const ARMCPRegInfo cortexa9_cp_reginfo[] = { 1564 /* power_control should be set to maximum latency. Again, 1565 * default to 0 and set by private hook 1566 */ 1567 { .name = "A9_PWRCTL", .cp = 15, .crn = 15, .crm = 0, .opc1 = 0, .opc2 = 0, 1568 .access = PL1_RW, .resetvalue = 0, 1569 .fieldoffset = offsetof(CPUARMState, cp15.c15_power_control) }, 1570 { .name = "A9_DIAG", .cp = 15, .crn = 15, .crm = 0, .opc1 = 0, .opc2 = 1, 1571 .access = PL1_RW, .resetvalue = 0, 1572 .fieldoffset = offsetof(CPUARMState, cp15.c15_diagnostic) }, 1573 { .name = "A9_PWRDIAG", .cp = 15, .crn = 15, .crm = 0, .opc1 = 0, .opc2 = 2, 1574 .access = PL1_RW, .resetvalue = 0, 1575 .fieldoffset = offsetof(CPUARMState, cp15.c15_power_diagnostic) }, 1576 { .name = "NEONBUSY", .cp = 15, .crn = 15, .crm = 1, .opc1 = 0, .opc2 = 0, 1577 .access = PL1_RW, .resetvalue = 0, .type = ARM_CP_CONST }, 1578 /* TLB lockdown control */ 1579 { .name = "TLB_LOCKR", .cp = 15, .crn = 15, .crm = 4, .opc1 = 5, .opc2 = 2, 1580 .access = PL1_W, .resetvalue = 0, .type = ARM_CP_NOP }, 1581 { .name = "TLB_LOCKW", .cp = 15, .crn = 15, .crm = 4, .opc1 = 5, .opc2 = 4, 1582 .access = PL1_W, .resetvalue = 0, .type = ARM_CP_NOP }, 1583 { .name = "TLB_VA", .cp = 15, .crn = 15, .crm = 5, .opc1 = 5, .opc2 = 2, 1584 .access = PL1_RW, .resetvalue = 0, .type = ARM_CP_CONST }, 1585 { .name = "TLB_PA", .cp = 15, .crn = 15, .crm = 6, .opc1 = 5, .opc2 = 2, 1586 .access = PL1_RW, .resetvalue = 0, .type = ARM_CP_CONST }, 1587 { .name = "TLB_ATTR", .cp = 15, .crn = 15, .crm = 7, .opc1 = 5, .opc2 = 2, 1588 .access = PL1_RW, .resetvalue = 0, .type = ARM_CP_CONST }, 1589 REGINFO_SENTINEL 1590 }; 1591 1592 static void cortex_a9_initfn(Object *obj) 1593 { 1594 ARMCPU *cpu = ARM_CPU(obj); 1595 1596 cpu->dtb_compatible = "arm,cortex-a9"; 1597 set_feature(&cpu->env, ARM_FEATURE_V7); 1598 set_feature(&cpu->env, ARM_FEATURE_VFP3); 1599 set_feature(&cpu->env, ARM_FEATURE_VFP_FP16); 1600 set_feature(&cpu->env, ARM_FEATURE_NEON); 1601 set_feature(&cpu->env, ARM_FEATURE_THUMB2EE); 1602 set_feature(&cpu->env, ARM_FEATURE_EL3); 1603 /* Note that A9 supports the MP extensions even for 1604 * A9UP and single-core A9MP (which are both different 1605 * and valid configurations; we don't model A9UP). 1606 */ 1607 set_feature(&cpu->env, ARM_FEATURE_V7MP); 1608 set_feature(&cpu->env, ARM_FEATURE_CBAR); 1609 cpu->midr = 0x410fc090; 1610 cpu->reset_fpsid = 0x41033090; 1611 cpu->isar.mvfr0 = 0x11110222; 1612 cpu->isar.mvfr1 = 0x01111111; 1613 cpu->ctr = 0x80038003; 1614 cpu->reset_sctlr = 0x00c50078; 1615 cpu->id_pfr0 = 0x1031; 1616 cpu->id_pfr1 = 0x11; 1617 cpu->id_dfr0 = 0x000; 1618 cpu->id_afr0 = 0; 1619 cpu->id_mmfr0 = 0x00100103; 1620 cpu->id_mmfr1 = 0x20000000; 1621 cpu->id_mmfr2 = 0x01230000; 1622 cpu->id_mmfr3 = 0x00002111; 1623 cpu->isar.id_isar0 = 0x00101111; 1624 cpu->isar.id_isar1 = 0x13112111; 1625 cpu->isar.id_isar2 = 0x21232041; 1626 cpu->isar.id_isar3 = 0x11112131; 1627 cpu->isar.id_isar4 = 0x00111142; 1628 cpu->dbgdidr = 0x35141000; 1629 cpu->clidr = (1 << 27) | (1 << 24) | 3; 1630 cpu->ccsidr[0] = 0xe00fe019; /* 16k L1 dcache. */ 1631 cpu->ccsidr[1] = 0x200fe019; /* 16k L1 icache. */ 1632 define_arm_cp_regs(cpu, cortexa9_cp_reginfo); 1633 } 1634 1635 #ifndef CONFIG_USER_ONLY 1636 static uint64_t a15_l2ctlr_read(CPUARMState *env, const ARMCPRegInfo *ri) 1637 { 1638 /* Linux wants the number of processors from here. 1639 * Might as well set the interrupt-controller bit too. 1640 */ 1641 return ((smp_cpus - 1) << 24) | (1 << 23); 1642 } 1643 #endif 1644 1645 static const ARMCPRegInfo cortexa15_cp_reginfo[] = { 1646 #ifndef CONFIG_USER_ONLY 1647 { .name = "L2CTLR", .cp = 15, .crn = 9, .crm = 0, .opc1 = 1, .opc2 = 2, 1648 .access = PL1_RW, .resetvalue = 0, .readfn = a15_l2ctlr_read, 1649 .writefn = arm_cp_write_ignore, }, 1650 #endif 1651 { .name = "L2ECTLR", .cp = 15, .crn = 9, .crm = 0, .opc1 = 1, .opc2 = 3, 1652 .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0 }, 1653 REGINFO_SENTINEL 1654 }; 1655 1656 static void cortex_a7_initfn(Object *obj) 1657 { 1658 ARMCPU *cpu = ARM_CPU(obj); 1659 1660 cpu->dtb_compatible = "arm,cortex-a7"; 1661 set_feature(&cpu->env, ARM_FEATURE_V7VE); 1662 set_feature(&cpu->env, ARM_FEATURE_VFP4); 1663 set_feature(&cpu->env, ARM_FEATURE_NEON); 1664 set_feature(&cpu->env, ARM_FEATURE_THUMB2EE); 1665 set_feature(&cpu->env, ARM_FEATURE_GENERIC_TIMER); 1666 set_feature(&cpu->env, ARM_FEATURE_DUMMY_C15_REGS); 1667 set_feature(&cpu->env, ARM_FEATURE_CBAR_RO); 1668 set_feature(&cpu->env, ARM_FEATURE_EL2); 1669 set_feature(&cpu->env, ARM_FEATURE_EL3); 1670 cpu->kvm_target = QEMU_KVM_ARM_TARGET_CORTEX_A7; 1671 cpu->midr = 0x410fc075; 1672 cpu->reset_fpsid = 0x41023075; 1673 cpu->isar.mvfr0 = 0x10110222; 1674 cpu->isar.mvfr1 = 0x11111111; 1675 cpu->ctr = 0x84448003; 1676 cpu->reset_sctlr = 0x00c50078; 1677 cpu->id_pfr0 = 0x00001131; 1678 cpu->id_pfr1 = 0x00011011; 1679 cpu->id_dfr0 = 0x02010555; 1680 cpu->pmceid0 = 0x00000000; 1681 cpu->pmceid1 = 0x00000000; 1682 cpu->id_afr0 = 0x00000000; 1683 cpu->id_mmfr0 = 0x10101105; 1684 cpu->id_mmfr1 = 0x40000000; 1685 cpu->id_mmfr2 = 0x01240000; 1686 cpu->id_mmfr3 = 0x02102211; 1687 /* a7_mpcore_r0p5_trm, page 4-4 gives 0x01101110; but 1688 * table 4-41 gives 0x02101110, which includes the arm div insns. 1689 */ 1690 cpu->isar.id_isar0 = 0x02101110; 1691 cpu->isar.id_isar1 = 0x13112111; 1692 cpu->isar.id_isar2 = 0x21232041; 1693 cpu->isar.id_isar3 = 0x11112131; 1694 cpu->isar.id_isar4 = 0x10011142; 1695 cpu->dbgdidr = 0x3515f005; 1696 cpu->clidr = 0x0a200023; 1697 cpu->ccsidr[0] = 0x701fe00a; /* 32K L1 dcache */ 1698 cpu->ccsidr[1] = 0x201fe00a; /* 32K L1 icache */ 1699 cpu->ccsidr[2] = 0x711fe07a; /* 4096K L2 unified cache */ 1700 define_arm_cp_regs(cpu, cortexa15_cp_reginfo); /* Same as A15 */ 1701 } 1702 1703 static void cortex_a15_initfn(Object *obj) 1704 { 1705 ARMCPU *cpu = ARM_CPU(obj); 1706 1707 cpu->dtb_compatible = "arm,cortex-a15"; 1708 set_feature(&cpu->env, ARM_FEATURE_V7VE); 1709 set_feature(&cpu->env, ARM_FEATURE_VFP4); 1710 set_feature(&cpu->env, ARM_FEATURE_NEON); 1711 set_feature(&cpu->env, ARM_FEATURE_THUMB2EE); 1712 set_feature(&cpu->env, ARM_FEATURE_GENERIC_TIMER); 1713 set_feature(&cpu->env, ARM_FEATURE_DUMMY_C15_REGS); 1714 set_feature(&cpu->env, ARM_FEATURE_CBAR_RO); 1715 set_feature(&cpu->env, ARM_FEATURE_EL2); 1716 set_feature(&cpu->env, ARM_FEATURE_EL3); 1717 cpu->kvm_target = QEMU_KVM_ARM_TARGET_CORTEX_A15; 1718 cpu->midr = 0x412fc0f1; 1719 cpu->reset_fpsid = 0x410430f0; 1720 cpu->isar.mvfr0 = 0x10110222; 1721 cpu->isar.mvfr1 = 0x11111111; 1722 cpu->ctr = 0x8444c004; 1723 cpu->reset_sctlr = 0x00c50078; 1724 cpu->id_pfr0 = 0x00001131; 1725 cpu->id_pfr1 = 0x00011011; 1726 cpu->id_dfr0 = 0x02010555; 1727 cpu->pmceid0 = 0x0000000; 1728 cpu->pmceid1 = 0x00000000; 1729 cpu->id_afr0 = 0x00000000; 1730 cpu->id_mmfr0 = 0x10201105; 1731 cpu->id_mmfr1 = 0x20000000; 1732 cpu->id_mmfr2 = 0x01240000; 1733 cpu->id_mmfr3 = 0x02102211; 1734 cpu->isar.id_isar0 = 0x02101110; 1735 cpu->isar.id_isar1 = 0x13112111; 1736 cpu->isar.id_isar2 = 0x21232041; 1737 cpu->isar.id_isar3 = 0x11112131; 1738 cpu->isar.id_isar4 = 0x10011142; 1739 cpu->dbgdidr = 0x3515f021; 1740 cpu->clidr = 0x0a200023; 1741 cpu->ccsidr[0] = 0x701fe00a; /* 32K L1 dcache */ 1742 cpu->ccsidr[1] = 0x201fe00a; /* 32K L1 icache */ 1743 cpu->ccsidr[2] = 0x711fe07a; /* 4096K L2 unified cache */ 1744 define_arm_cp_regs(cpu, cortexa15_cp_reginfo); 1745 } 1746 1747 static void ti925t_initfn(Object *obj) 1748 { 1749 ARMCPU *cpu = ARM_CPU(obj); 1750 set_feature(&cpu->env, ARM_FEATURE_V4T); 1751 set_feature(&cpu->env, ARM_FEATURE_OMAPCP); 1752 cpu->midr = ARM_CPUID_TI925T; 1753 cpu->ctr = 0x5109149; 1754 cpu->reset_sctlr = 0x00000070; 1755 } 1756 1757 static void sa1100_initfn(Object *obj) 1758 { 1759 ARMCPU *cpu = ARM_CPU(obj); 1760 1761 cpu->dtb_compatible = "intel,sa1100"; 1762 set_feature(&cpu->env, ARM_FEATURE_STRONGARM); 1763 set_feature(&cpu->env, ARM_FEATURE_DUMMY_C15_REGS); 1764 cpu->midr = 0x4401A11B; 1765 cpu->reset_sctlr = 0x00000070; 1766 } 1767 1768 static void sa1110_initfn(Object *obj) 1769 { 1770 ARMCPU *cpu = ARM_CPU(obj); 1771 set_feature(&cpu->env, ARM_FEATURE_STRONGARM); 1772 set_feature(&cpu->env, ARM_FEATURE_DUMMY_C15_REGS); 1773 cpu->midr = 0x6901B119; 1774 cpu->reset_sctlr = 0x00000070; 1775 } 1776 1777 static void pxa250_initfn(Object *obj) 1778 { 1779 ARMCPU *cpu = ARM_CPU(obj); 1780 1781 cpu->dtb_compatible = "marvell,xscale"; 1782 set_feature(&cpu->env, ARM_FEATURE_V5); 1783 set_feature(&cpu->env, ARM_FEATURE_XSCALE); 1784 cpu->midr = 0x69052100; 1785 cpu->ctr = 0xd172172; 1786 cpu->reset_sctlr = 0x00000078; 1787 } 1788 1789 static void pxa255_initfn(Object *obj) 1790 { 1791 ARMCPU *cpu = ARM_CPU(obj); 1792 1793 cpu->dtb_compatible = "marvell,xscale"; 1794 set_feature(&cpu->env, ARM_FEATURE_V5); 1795 set_feature(&cpu->env, ARM_FEATURE_XSCALE); 1796 cpu->midr = 0x69052d00; 1797 cpu->ctr = 0xd172172; 1798 cpu->reset_sctlr = 0x00000078; 1799 } 1800 1801 static void pxa260_initfn(Object *obj) 1802 { 1803 ARMCPU *cpu = ARM_CPU(obj); 1804 1805 cpu->dtb_compatible = "marvell,xscale"; 1806 set_feature(&cpu->env, ARM_FEATURE_V5); 1807 set_feature(&cpu->env, ARM_FEATURE_XSCALE); 1808 cpu->midr = 0x69052903; 1809 cpu->ctr = 0xd172172; 1810 cpu->reset_sctlr = 0x00000078; 1811 } 1812 1813 static void pxa261_initfn(Object *obj) 1814 { 1815 ARMCPU *cpu = ARM_CPU(obj); 1816 1817 cpu->dtb_compatible = "marvell,xscale"; 1818 set_feature(&cpu->env, ARM_FEATURE_V5); 1819 set_feature(&cpu->env, ARM_FEATURE_XSCALE); 1820 cpu->midr = 0x69052d05; 1821 cpu->ctr = 0xd172172; 1822 cpu->reset_sctlr = 0x00000078; 1823 } 1824 1825 static void pxa262_initfn(Object *obj) 1826 { 1827 ARMCPU *cpu = ARM_CPU(obj); 1828 1829 cpu->dtb_compatible = "marvell,xscale"; 1830 set_feature(&cpu->env, ARM_FEATURE_V5); 1831 set_feature(&cpu->env, ARM_FEATURE_XSCALE); 1832 cpu->midr = 0x69052d06; 1833 cpu->ctr = 0xd172172; 1834 cpu->reset_sctlr = 0x00000078; 1835 } 1836 1837 static void pxa270a0_initfn(Object *obj) 1838 { 1839 ARMCPU *cpu = ARM_CPU(obj); 1840 1841 cpu->dtb_compatible = "marvell,xscale"; 1842 set_feature(&cpu->env, ARM_FEATURE_V5); 1843 set_feature(&cpu->env, ARM_FEATURE_XSCALE); 1844 set_feature(&cpu->env, ARM_FEATURE_IWMMXT); 1845 cpu->midr = 0x69054110; 1846 cpu->ctr = 0xd172172; 1847 cpu->reset_sctlr = 0x00000078; 1848 } 1849 1850 static void pxa270a1_initfn(Object *obj) 1851 { 1852 ARMCPU *cpu = ARM_CPU(obj); 1853 1854 cpu->dtb_compatible = "marvell,xscale"; 1855 set_feature(&cpu->env, ARM_FEATURE_V5); 1856 set_feature(&cpu->env, ARM_FEATURE_XSCALE); 1857 set_feature(&cpu->env, ARM_FEATURE_IWMMXT); 1858 cpu->midr = 0x69054111; 1859 cpu->ctr = 0xd172172; 1860 cpu->reset_sctlr = 0x00000078; 1861 } 1862 1863 static void pxa270b0_initfn(Object *obj) 1864 { 1865 ARMCPU *cpu = ARM_CPU(obj); 1866 1867 cpu->dtb_compatible = "marvell,xscale"; 1868 set_feature(&cpu->env, ARM_FEATURE_V5); 1869 set_feature(&cpu->env, ARM_FEATURE_XSCALE); 1870 set_feature(&cpu->env, ARM_FEATURE_IWMMXT); 1871 cpu->midr = 0x69054112; 1872 cpu->ctr = 0xd172172; 1873 cpu->reset_sctlr = 0x00000078; 1874 } 1875 1876 static void pxa270b1_initfn(Object *obj) 1877 { 1878 ARMCPU *cpu = ARM_CPU(obj); 1879 1880 cpu->dtb_compatible = "marvell,xscale"; 1881 set_feature(&cpu->env, ARM_FEATURE_V5); 1882 set_feature(&cpu->env, ARM_FEATURE_XSCALE); 1883 set_feature(&cpu->env, ARM_FEATURE_IWMMXT); 1884 cpu->midr = 0x69054113; 1885 cpu->ctr = 0xd172172; 1886 cpu->reset_sctlr = 0x00000078; 1887 } 1888 1889 static void pxa270c0_initfn(Object *obj) 1890 { 1891 ARMCPU *cpu = ARM_CPU(obj); 1892 1893 cpu->dtb_compatible = "marvell,xscale"; 1894 set_feature(&cpu->env, ARM_FEATURE_V5); 1895 set_feature(&cpu->env, ARM_FEATURE_XSCALE); 1896 set_feature(&cpu->env, ARM_FEATURE_IWMMXT); 1897 cpu->midr = 0x69054114; 1898 cpu->ctr = 0xd172172; 1899 cpu->reset_sctlr = 0x00000078; 1900 } 1901 1902 static void pxa270c5_initfn(Object *obj) 1903 { 1904 ARMCPU *cpu = ARM_CPU(obj); 1905 1906 cpu->dtb_compatible = "marvell,xscale"; 1907 set_feature(&cpu->env, ARM_FEATURE_V5); 1908 set_feature(&cpu->env, ARM_FEATURE_XSCALE); 1909 set_feature(&cpu->env, ARM_FEATURE_IWMMXT); 1910 cpu->midr = 0x69054117; 1911 cpu->ctr = 0xd172172; 1912 cpu->reset_sctlr = 0x00000078; 1913 } 1914 1915 #ifndef TARGET_AARCH64 1916 /* -cpu max: if KVM is enabled, like -cpu host (best possible with this host); 1917 * otherwise, a CPU with as many features enabled as our emulation supports. 1918 * The version of '-cpu max' for qemu-system-aarch64 is defined in cpu64.c; 1919 * this only needs to handle 32 bits. 1920 */ 1921 static void arm_max_initfn(Object *obj) 1922 { 1923 ARMCPU *cpu = ARM_CPU(obj); 1924 1925 if (kvm_enabled()) { 1926 kvm_arm_set_cpu_features_from_host(cpu); 1927 } else { 1928 cortex_a15_initfn(obj); 1929 #ifdef CONFIG_USER_ONLY 1930 /* We don't set these in system emulation mode for the moment, 1931 * since we don't correctly set (all of) the ID registers to 1932 * advertise them. 1933 */ 1934 set_feature(&cpu->env, ARM_FEATURE_V8); 1935 { 1936 uint32_t t; 1937 1938 t = cpu->isar.id_isar5; 1939 t = FIELD_DP32(t, ID_ISAR5, AES, 2); 1940 t = FIELD_DP32(t, ID_ISAR5, SHA1, 1); 1941 t = FIELD_DP32(t, ID_ISAR5, SHA2, 1); 1942 t = FIELD_DP32(t, ID_ISAR5, CRC32, 1); 1943 t = FIELD_DP32(t, ID_ISAR5, RDM, 1); 1944 t = FIELD_DP32(t, ID_ISAR5, VCMA, 1); 1945 cpu->isar.id_isar5 = t; 1946 1947 t = cpu->isar.id_isar6; 1948 t = FIELD_DP32(t, ID_ISAR6, DP, 1); 1949 cpu->isar.id_isar6 = t; 1950 1951 t = cpu->id_mmfr4; 1952 t = FIELD_DP32(t, ID_MMFR4, HPDS, 1); /* AA32HPD */ 1953 cpu->id_mmfr4 = t; 1954 } 1955 #endif 1956 } 1957 } 1958 #endif 1959 1960 #endif /* !defined(CONFIG_USER_ONLY) || !defined(TARGET_AARCH64) */ 1961 1962 typedef struct ARMCPUInfo { 1963 const char *name; 1964 void (*initfn)(Object *obj); 1965 void (*class_init)(ObjectClass *oc, void *data); 1966 } ARMCPUInfo; 1967 1968 static const ARMCPUInfo arm_cpus[] = { 1969 #if !defined(CONFIG_USER_ONLY) || !defined(TARGET_AARCH64) 1970 { .name = "arm926", .initfn = arm926_initfn }, 1971 { .name = "arm946", .initfn = arm946_initfn }, 1972 { .name = "arm1026", .initfn = arm1026_initfn }, 1973 /* What QEMU calls "arm1136-r2" is actually the 1136 r0p2, i.e. an 1974 * older core than plain "arm1136". In particular this does not 1975 * have the v6K features. 1976 */ 1977 { .name = "arm1136-r2", .initfn = arm1136_r2_initfn }, 1978 { .name = "arm1136", .initfn = arm1136_initfn }, 1979 { .name = "arm1176", .initfn = arm1176_initfn }, 1980 { .name = "arm11mpcore", .initfn = arm11mpcore_initfn }, 1981 { .name = "cortex-m0", .initfn = cortex_m0_initfn, 1982 .class_init = arm_v7m_class_init }, 1983 { .name = "cortex-m3", .initfn = cortex_m3_initfn, 1984 .class_init = arm_v7m_class_init }, 1985 { .name = "cortex-m4", .initfn = cortex_m4_initfn, 1986 .class_init = arm_v7m_class_init }, 1987 { .name = "cortex-m33", .initfn = cortex_m33_initfn, 1988 .class_init = arm_v7m_class_init }, 1989 { .name = "cortex-r5", .initfn = cortex_r5_initfn }, 1990 { .name = "cortex-r5f", .initfn = cortex_r5f_initfn }, 1991 { .name = "cortex-a7", .initfn = cortex_a7_initfn }, 1992 { .name = "cortex-a8", .initfn = cortex_a8_initfn }, 1993 { .name = "cortex-a9", .initfn = cortex_a9_initfn }, 1994 { .name = "cortex-a15", .initfn = cortex_a15_initfn }, 1995 { .name = "ti925t", .initfn = ti925t_initfn }, 1996 { .name = "sa1100", .initfn = sa1100_initfn }, 1997 { .name = "sa1110", .initfn = sa1110_initfn }, 1998 { .name = "pxa250", .initfn = pxa250_initfn }, 1999 { .name = "pxa255", .initfn = pxa255_initfn }, 2000 { .name = "pxa260", .initfn = pxa260_initfn }, 2001 { .name = "pxa261", .initfn = pxa261_initfn }, 2002 { .name = "pxa262", .initfn = pxa262_initfn }, 2003 /* "pxa270" is an alias for "pxa270-a0" */ 2004 { .name = "pxa270", .initfn = pxa270a0_initfn }, 2005 { .name = "pxa270-a0", .initfn = pxa270a0_initfn }, 2006 { .name = "pxa270-a1", .initfn = pxa270a1_initfn }, 2007 { .name = "pxa270-b0", .initfn = pxa270b0_initfn }, 2008 { .name = "pxa270-b1", .initfn = pxa270b1_initfn }, 2009 { .name = "pxa270-c0", .initfn = pxa270c0_initfn }, 2010 { .name = "pxa270-c5", .initfn = pxa270c5_initfn }, 2011 #ifndef TARGET_AARCH64 2012 { .name = "max", .initfn = arm_max_initfn }, 2013 #endif 2014 #ifdef CONFIG_USER_ONLY 2015 { .name = "any", .initfn = arm_max_initfn }, 2016 #endif 2017 #endif 2018 { .name = NULL } 2019 }; 2020 2021 static Property arm_cpu_properties[] = { 2022 DEFINE_PROP_BOOL("start-powered-off", ARMCPU, start_powered_off, false), 2023 DEFINE_PROP_UINT32("psci-conduit", ARMCPU, psci_conduit, 0), 2024 DEFINE_PROP_UINT32("midr", ARMCPU, midr, 0), 2025 DEFINE_PROP_UINT64("mp-affinity", ARMCPU, 2026 mp_affinity, ARM64_AFFINITY_INVALID), 2027 DEFINE_PROP_INT32("node-id", ARMCPU, node_id, CPU_UNSET_NUMA_NODE_ID), 2028 DEFINE_PROP_INT32("core-count", ARMCPU, core_count, -1), 2029 DEFINE_PROP_END_OF_LIST() 2030 }; 2031 2032 #ifdef CONFIG_USER_ONLY 2033 static int arm_cpu_handle_mmu_fault(CPUState *cs, vaddr address, int size, 2034 int rw, int mmu_idx) 2035 { 2036 ARMCPU *cpu = ARM_CPU(cs); 2037 CPUARMState *env = &cpu->env; 2038 2039 env->exception.vaddress = address; 2040 if (rw == 2) { 2041 cs->exception_index = EXCP_PREFETCH_ABORT; 2042 } else { 2043 cs->exception_index = EXCP_DATA_ABORT; 2044 } 2045 return 1; 2046 } 2047 #endif 2048 2049 static gchar *arm_gdb_arch_name(CPUState *cs) 2050 { 2051 ARMCPU *cpu = ARM_CPU(cs); 2052 CPUARMState *env = &cpu->env; 2053 2054 if (arm_feature(env, ARM_FEATURE_IWMMXT)) { 2055 return g_strdup("iwmmxt"); 2056 } 2057 return g_strdup("arm"); 2058 } 2059 2060 static void arm_cpu_class_init(ObjectClass *oc, void *data) 2061 { 2062 ARMCPUClass *acc = ARM_CPU_CLASS(oc); 2063 CPUClass *cc = CPU_CLASS(acc); 2064 DeviceClass *dc = DEVICE_CLASS(oc); 2065 2066 device_class_set_parent_realize(dc, arm_cpu_realizefn, 2067 &acc->parent_realize); 2068 dc->props = arm_cpu_properties; 2069 2070 acc->parent_reset = cc->reset; 2071 cc->reset = arm_cpu_reset; 2072 2073 cc->class_by_name = arm_cpu_class_by_name; 2074 cc->has_work = arm_cpu_has_work; 2075 cc->cpu_exec_interrupt = arm_cpu_exec_interrupt; 2076 cc->dump_state = arm_cpu_dump_state; 2077 cc->set_pc = arm_cpu_set_pc; 2078 cc->gdb_read_register = arm_cpu_gdb_read_register; 2079 cc->gdb_write_register = arm_cpu_gdb_write_register; 2080 #ifdef CONFIG_USER_ONLY 2081 cc->handle_mmu_fault = arm_cpu_handle_mmu_fault; 2082 #else 2083 cc->do_interrupt = arm_cpu_do_interrupt; 2084 cc->do_unaligned_access = arm_cpu_do_unaligned_access; 2085 cc->do_transaction_failed = arm_cpu_do_transaction_failed; 2086 cc->get_phys_page_attrs_debug = arm_cpu_get_phys_page_attrs_debug; 2087 cc->asidx_from_attrs = arm_asidx_from_attrs; 2088 cc->vmsd = &vmstate_arm_cpu; 2089 cc->virtio_is_big_endian = arm_cpu_virtio_is_big_endian; 2090 cc->write_elf64_note = arm_cpu_write_elf64_note; 2091 cc->write_elf32_note = arm_cpu_write_elf32_note; 2092 #endif 2093 cc->gdb_num_core_regs = 26; 2094 cc->gdb_core_xml_file = "arm-core.xml"; 2095 cc->gdb_arch_name = arm_gdb_arch_name; 2096 cc->gdb_get_dynamic_xml = arm_gdb_get_dynamic_xml; 2097 cc->gdb_stop_before_watchpoint = true; 2098 cc->debug_excp_handler = arm_debug_excp_handler; 2099 cc->debug_check_watchpoint = arm_debug_check_watchpoint; 2100 #if !defined(CONFIG_USER_ONLY) 2101 cc->adjust_watchpoint_address = arm_adjust_watchpoint_address; 2102 #endif 2103 2104 cc->disas_set_info = arm_disas_set_info; 2105 #ifdef CONFIG_TCG 2106 cc->tcg_initialize = arm_translate_init; 2107 #endif 2108 } 2109 2110 #ifdef CONFIG_KVM 2111 static void arm_host_initfn(Object *obj) 2112 { 2113 ARMCPU *cpu = ARM_CPU(obj); 2114 2115 kvm_arm_set_cpu_features_from_host(cpu); 2116 } 2117 2118 static const TypeInfo host_arm_cpu_type_info = { 2119 .name = TYPE_ARM_HOST_CPU, 2120 #ifdef TARGET_AARCH64 2121 .parent = TYPE_AARCH64_CPU, 2122 #else 2123 .parent = TYPE_ARM_CPU, 2124 #endif 2125 .instance_init = arm_host_initfn, 2126 }; 2127 2128 #endif 2129 2130 static void cpu_register(const ARMCPUInfo *info) 2131 { 2132 TypeInfo type_info = { 2133 .parent = TYPE_ARM_CPU, 2134 .instance_size = sizeof(ARMCPU), 2135 .instance_init = info->initfn, 2136 .class_size = sizeof(ARMCPUClass), 2137 .class_init = info->class_init, 2138 }; 2139 2140 type_info.name = g_strdup_printf("%s-" TYPE_ARM_CPU, info->name); 2141 type_register(&type_info); 2142 g_free((void *)type_info.name); 2143 } 2144 2145 static const TypeInfo arm_cpu_type_info = { 2146 .name = TYPE_ARM_CPU, 2147 .parent = TYPE_CPU, 2148 .instance_size = sizeof(ARMCPU), 2149 .instance_init = arm_cpu_initfn, 2150 .instance_post_init = arm_cpu_post_init, 2151 .instance_finalize = arm_cpu_finalizefn, 2152 .abstract = true, 2153 .class_size = sizeof(ARMCPUClass), 2154 .class_init = arm_cpu_class_init, 2155 }; 2156 2157 static const TypeInfo idau_interface_type_info = { 2158 .name = TYPE_IDAU_INTERFACE, 2159 .parent = TYPE_INTERFACE, 2160 .class_size = sizeof(IDAUInterfaceClass), 2161 }; 2162 2163 static void arm_cpu_register_types(void) 2164 { 2165 const ARMCPUInfo *info = arm_cpus; 2166 2167 type_register_static(&arm_cpu_type_info); 2168 type_register_static(&idau_interface_type_info); 2169 2170 while (info->name) { 2171 cpu_register(info); 2172 info++; 2173 } 2174 2175 #ifdef CONFIG_KVM 2176 type_register_static(&host_arm_cpu_type_info); 2177 #endif 2178 } 2179 2180 type_init(arm_cpu_register_types) 2181