1 /* 2 * QEMU ARM CPU 3 * 4 * Copyright (c) 2012 SUSE LINUX Products GmbH 5 * 6 * This program is free software; you can redistribute it and/or 7 * modify it under the terms of the GNU General Public License 8 * as published by the Free Software Foundation; either version 2 9 * of the License, or (at your option) any later version. 10 * 11 * This program is distributed in the hope that it will be useful, 12 * but WITHOUT ANY WARRANTY; without even the implied warranty of 13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 14 * GNU General Public License for more details. 15 * 16 * You should have received a copy of the GNU General Public License 17 * along with this program; if not, see 18 * <http://www.gnu.org/licenses/gpl-2.0.html> 19 */ 20 21 #include "qemu/osdep.h" 22 #include "target/arm/idau.h" 23 #include "qapi/error.h" 24 #include "qapi/visitor.h" 25 #include "cpu.h" 26 #include "internals.h" 27 #include "qemu-common.h" 28 #include "exec/exec-all.h" 29 #include "hw/qdev-properties.h" 30 #if !defined(CONFIG_USER_ONLY) 31 #include "hw/loader.h" 32 #endif 33 #include "hw/arm/arm.h" 34 #include "sysemu/sysemu.h" 35 #include "sysemu/hw_accel.h" 36 #include "kvm_arm.h" 37 #include "disas/capstone.h" 38 #include "fpu/softfloat.h" 39 40 static void arm_cpu_set_pc(CPUState *cs, vaddr value) 41 { 42 ARMCPU *cpu = ARM_CPU(cs); 43 CPUARMState *env = &cpu->env; 44 45 if (is_a64(env)) { 46 env->pc = value; 47 env->thumb = 0; 48 } else { 49 env->regs[15] = value & ~1; 50 env->thumb = value & 1; 51 } 52 } 53 54 static void arm_cpu_synchronize_from_tb(CPUState *cs, TranslationBlock *tb) 55 { 56 ARMCPU *cpu = ARM_CPU(cs); 57 CPUARMState *env = &cpu->env; 58 59 /* 60 * It's OK to look at env for the current mode here, because it's 61 * never possible for an AArch64 TB to chain to an AArch32 TB. 62 */ 63 if (is_a64(env)) { 64 env->pc = tb->pc; 65 } else { 66 env->regs[15] = tb->pc; 67 } 68 } 69 70 static bool arm_cpu_has_work(CPUState *cs) 71 { 72 ARMCPU *cpu = ARM_CPU(cs); 73 74 return (cpu->power_state != PSCI_OFF) 75 && cs->interrupt_request & 76 (CPU_INTERRUPT_FIQ | CPU_INTERRUPT_HARD 77 | CPU_INTERRUPT_VFIQ | CPU_INTERRUPT_VIRQ 78 | CPU_INTERRUPT_EXITTB); 79 } 80 81 void arm_register_pre_el_change_hook(ARMCPU *cpu, ARMELChangeHookFn *hook, 82 void *opaque) 83 { 84 ARMELChangeHook *entry = g_new0(ARMELChangeHook, 1); 85 86 entry->hook = hook; 87 entry->opaque = opaque; 88 89 QLIST_INSERT_HEAD(&cpu->pre_el_change_hooks, entry, node); 90 } 91 92 void arm_register_el_change_hook(ARMCPU *cpu, ARMELChangeHookFn *hook, 93 void *opaque) 94 { 95 ARMELChangeHook *entry = g_new0(ARMELChangeHook, 1); 96 97 entry->hook = hook; 98 entry->opaque = opaque; 99 100 QLIST_INSERT_HEAD(&cpu->el_change_hooks, entry, node); 101 } 102 103 static void cp_reg_reset(gpointer key, gpointer value, gpointer opaque) 104 { 105 /* Reset a single ARMCPRegInfo register */ 106 ARMCPRegInfo *ri = value; 107 ARMCPU *cpu = opaque; 108 109 if (ri->type & (ARM_CP_SPECIAL | ARM_CP_ALIAS)) { 110 return; 111 } 112 113 if (ri->resetfn) { 114 ri->resetfn(&cpu->env, ri); 115 return; 116 } 117 118 /* A zero offset is never possible as it would be regs[0] 119 * so we use it to indicate that reset is being handled elsewhere. 120 * This is basically only used for fields in non-core coprocessors 121 * (like the pxa2xx ones). 122 */ 123 if (!ri->fieldoffset) { 124 return; 125 } 126 127 if (cpreg_field_is_64bit(ri)) { 128 CPREG_FIELD64(&cpu->env, ri) = ri->resetvalue; 129 } else { 130 CPREG_FIELD32(&cpu->env, ri) = ri->resetvalue; 131 } 132 } 133 134 static void cp_reg_check_reset(gpointer key, gpointer value, gpointer opaque) 135 { 136 /* Purely an assertion check: we've already done reset once, 137 * so now check that running the reset for the cpreg doesn't 138 * change its value. This traps bugs where two different cpregs 139 * both try to reset the same state field but to different values. 140 */ 141 ARMCPRegInfo *ri = value; 142 ARMCPU *cpu = opaque; 143 uint64_t oldvalue, newvalue; 144 145 if (ri->type & (ARM_CP_SPECIAL | ARM_CP_ALIAS | ARM_CP_NO_RAW)) { 146 return; 147 } 148 149 oldvalue = read_raw_cp_reg(&cpu->env, ri); 150 cp_reg_reset(key, value, opaque); 151 newvalue = read_raw_cp_reg(&cpu->env, ri); 152 assert(oldvalue == newvalue); 153 } 154 155 /* CPUClass::reset() */ 156 static void arm_cpu_reset(CPUState *s) 157 { 158 ARMCPU *cpu = ARM_CPU(s); 159 ARMCPUClass *acc = ARM_CPU_GET_CLASS(cpu); 160 CPUARMState *env = &cpu->env; 161 162 acc->parent_reset(s); 163 164 memset(env, 0, offsetof(CPUARMState, end_reset_fields)); 165 166 g_hash_table_foreach(cpu->cp_regs, cp_reg_reset, cpu); 167 g_hash_table_foreach(cpu->cp_regs, cp_reg_check_reset, cpu); 168 169 env->vfp.xregs[ARM_VFP_FPSID] = cpu->reset_fpsid; 170 env->vfp.xregs[ARM_VFP_MVFR0] = cpu->isar.mvfr0; 171 env->vfp.xregs[ARM_VFP_MVFR1] = cpu->isar.mvfr1; 172 env->vfp.xregs[ARM_VFP_MVFR2] = cpu->isar.mvfr2; 173 174 cpu->power_state = cpu->start_powered_off ? PSCI_OFF : PSCI_ON; 175 s->halted = cpu->start_powered_off; 176 177 if (arm_feature(env, ARM_FEATURE_IWMMXT)) { 178 env->iwmmxt.cregs[ARM_IWMMXT_wCID] = 0x69051000 | 'Q'; 179 } 180 181 if (arm_feature(env, ARM_FEATURE_AARCH64)) { 182 /* 64 bit CPUs always start in 64 bit mode */ 183 env->aarch64 = 1; 184 #if defined(CONFIG_USER_ONLY) 185 env->pstate = PSTATE_MODE_EL0t; 186 /* Userspace expects access to DC ZVA, CTL_EL0 and the cache ops */ 187 env->cp15.sctlr_el[1] |= SCTLR_UCT | SCTLR_UCI | SCTLR_DZE; 188 /* Enable all PAC keys. */ 189 env->cp15.sctlr_el[1] |= (SCTLR_EnIA | SCTLR_EnIB | 190 SCTLR_EnDA | SCTLR_EnDB); 191 /* Enable all PAC instructions */ 192 env->cp15.hcr_el2 |= HCR_API; 193 env->cp15.scr_el3 |= SCR_API; 194 /* and to the FP/Neon instructions */ 195 env->cp15.cpacr_el1 = deposit64(env->cp15.cpacr_el1, 20, 2, 3); 196 /* and to the SVE instructions */ 197 env->cp15.cpacr_el1 = deposit64(env->cp15.cpacr_el1, 16, 2, 3); 198 env->cp15.cptr_el[3] |= CPTR_EZ; 199 /* with maximum vector length */ 200 env->vfp.zcr_el[1] = cpu->sve_max_vq - 1; 201 env->vfp.zcr_el[2] = env->vfp.zcr_el[1]; 202 env->vfp.zcr_el[3] = env->vfp.zcr_el[1]; 203 /* 204 * Enable TBI0 and TBI1. While the real kernel only enables TBI0, 205 * turning on both here will produce smaller code and otherwise 206 * make no difference to the user-level emulation. 207 */ 208 env->cp15.tcr_el[1].raw_tcr = (3ULL << 37); 209 #else 210 /* Reset into the highest available EL */ 211 if (arm_feature(env, ARM_FEATURE_EL3)) { 212 env->pstate = PSTATE_MODE_EL3h; 213 } else if (arm_feature(env, ARM_FEATURE_EL2)) { 214 env->pstate = PSTATE_MODE_EL2h; 215 } else { 216 env->pstate = PSTATE_MODE_EL1h; 217 } 218 env->pc = cpu->rvbar; 219 #endif 220 } else { 221 #if defined(CONFIG_USER_ONLY) 222 /* Userspace expects access to cp10 and cp11 for FP/Neon */ 223 env->cp15.cpacr_el1 = deposit64(env->cp15.cpacr_el1, 20, 4, 0xf); 224 #endif 225 } 226 227 #if defined(CONFIG_USER_ONLY) 228 env->uncached_cpsr = ARM_CPU_MODE_USR; 229 /* For user mode we must enable access to coprocessors */ 230 env->vfp.xregs[ARM_VFP_FPEXC] = 1 << 30; 231 if (arm_feature(env, ARM_FEATURE_IWMMXT)) { 232 env->cp15.c15_cpar = 3; 233 } else if (arm_feature(env, ARM_FEATURE_XSCALE)) { 234 env->cp15.c15_cpar = 1; 235 } 236 #else 237 238 /* 239 * If the highest available EL is EL2, AArch32 will start in Hyp 240 * mode; otherwise it starts in SVC. Note that if we start in 241 * AArch64 then these values in the uncached_cpsr will be ignored. 242 */ 243 if (arm_feature(env, ARM_FEATURE_EL2) && 244 !arm_feature(env, ARM_FEATURE_EL3)) { 245 env->uncached_cpsr = ARM_CPU_MODE_HYP; 246 } else { 247 env->uncached_cpsr = ARM_CPU_MODE_SVC; 248 } 249 env->daif = PSTATE_D | PSTATE_A | PSTATE_I | PSTATE_F; 250 251 if (arm_feature(env, ARM_FEATURE_M)) { 252 uint32_t initial_msp; /* Loaded from 0x0 */ 253 uint32_t initial_pc; /* Loaded from 0x4 */ 254 uint8_t *rom; 255 uint32_t vecbase; 256 257 if (arm_feature(env, ARM_FEATURE_M_SECURITY)) { 258 env->v7m.secure = true; 259 } else { 260 /* This bit resets to 0 if security is supported, but 1 if 261 * it is not. The bit is not present in v7M, but we set it 262 * here so we can avoid having to make checks on it conditional 263 * on ARM_FEATURE_V8 (we don't let the guest see the bit). 264 */ 265 env->v7m.aircr = R_V7M_AIRCR_BFHFNMINS_MASK; 266 } 267 268 /* In v7M the reset value of this bit is IMPDEF, but ARM recommends 269 * that it resets to 1, so QEMU always does that rather than making 270 * it dependent on CPU model. In v8M it is RES1. 271 */ 272 env->v7m.ccr[M_REG_NS] = R_V7M_CCR_STKALIGN_MASK; 273 env->v7m.ccr[M_REG_S] = R_V7M_CCR_STKALIGN_MASK; 274 if (arm_feature(env, ARM_FEATURE_V8)) { 275 /* in v8M the NONBASETHRDENA bit [0] is RES1 */ 276 env->v7m.ccr[M_REG_NS] |= R_V7M_CCR_NONBASETHRDENA_MASK; 277 env->v7m.ccr[M_REG_S] |= R_V7M_CCR_NONBASETHRDENA_MASK; 278 } 279 if (!arm_feature(env, ARM_FEATURE_M_MAIN)) { 280 env->v7m.ccr[M_REG_NS] |= R_V7M_CCR_UNALIGN_TRP_MASK; 281 env->v7m.ccr[M_REG_S] |= R_V7M_CCR_UNALIGN_TRP_MASK; 282 } 283 284 /* Unlike A/R profile, M profile defines the reset LR value */ 285 env->regs[14] = 0xffffffff; 286 287 env->v7m.vecbase[M_REG_S] = cpu->init_svtor & 0xffffff80; 288 289 /* Load the initial SP and PC from offset 0 and 4 in the vector table */ 290 vecbase = env->v7m.vecbase[env->v7m.secure]; 291 rom = rom_ptr(vecbase, 8); 292 if (rom) { 293 /* Address zero is covered by ROM which hasn't yet been 294 * copied into physical memory. 295 */ 296 initial_msp = ldl_p(rom); 297 initial_pc = ldl_p(rom + 4); 298 } else { 299 /* Address zero not covered by a ROM blob, or the ROM blob 300 * is in non-modifiable memory and this is a second reset after 301 * it got copied into memory. In the latter case, rom_ptr 302 * will return a NULL pointer and we should use ldl_phys instead. 303 */ 304 initial_msp = ldl_phys(s->as, vecbase); 305 initial_pc = ldl_phys(s->as, vecbase + 4); 306 } 307 308 env->regs[13] = initial_msp & 0xFFFFFFFC; 309 env->regs[15] = initial_pc & ~1; 310 env->thumb = initial_pc & 1; 311 } 312 313 /* AArch32 has a hard highvec setting of 0xFFFF0000. If we are currently 314 * executing as AArch32 then check if highvecs are enabled and 315 * adjust the PC accordingly. 316 */ 317 if (A32_BANKED_CURRENT_REG_GET(env, sctlr) & SCTLR_V) { 318 env->regs[15] = 0xFFFF0000; 319 } 320 321 /* M profile requires that reset clears the exclusive monitor; 322 * A profile does not, but clearing it makes more sense than having it 323 * set with an exclusive access on address zero. 324 */ 325 arm_clear_exclusive(env); 326 327 env->vfp.xregs[ARM_VFP_FPEXC] = 0; 328 #endif 329 330 if (arm_feature(env, ARM_FEATURE_PMSA)) { 331 if (cpu->pmsav7_dregion > 0) { 332 if (arm_feature(env, ARM_FEATURE_V8)) { 333 memset(env->pmsav8.rbar[M_REG_NS], 0, 334 sizeof(*env->pmsav8.rbar[M_REG_NS]) 335 * cpu->pmsav7_dregion); 336 memset(env->pmsav8.rlar[M_REG_NS], 0, 337 sizeof(*env->pmsav8.rlar[M_REG_NS]) 338 * cpu->pmsav7_dregion); 339 if (arm_feature(env, ARM_FEATURE_M_SECURITY)) { 340 memset(env->pmsav8.rbar[M_REG_S], 0, 341 sizeof(*env->pmsav8.rbar[M_REG_S]) 342 * cpu->pmsav7_dregion); 343 memset(env->pmsav8.rlar[M_REG_S], 0, 344 sizeof(*env->pmsav8.rlar[M_REG_S]) 345 * cpu->pmsav7_dregion); 346 } 347 } else if (arm_feature(env, ARM_FEATURE_V7)) { 348 memset(env->pmsav7.drbar, 0, 349 sizeof(*env->pmsav7.drbar) * cpu->pmsav7_dregion); 350 memset(env->pmsav7.drsr, 0, 351 sizeof(*env->pmsav7.drsr) * cpu->pmsav7_dregion); 352 memset(env->pmsav7.dracr, 0, 353 sizeof(*env->pmsav7.dracr) * cpu->pmsav7_dregion); 354 } 355 } 356 env->pmsav7.rnr[M_REG_NS] = 0; 357 env->pmsav7.rnr[M_REG_S] = 0; 358 env->pmsav8.mair0[M_REG_NS] = 0; 359 env->pmsav8.mair0[M_REG_S] = 0; 360 env->pmsav8.mair1[M_REG_NS] = 0; 361 env->pmsav8.mair1[M_REG_S] = 0; 362 } 363 364 if (arm_feature(env, ARM_FEATURE_M_SECURITY)) { 365 if (cpu->sau_sregion > 0) { 366 memset(env->sau.rbar, 0, sizeof(*env->sau.rbar) * cpu->sau_sregion); 367 memset(env->sau.rlar, 0, sizeof(*env->sau.rlar) * cpu->sau_sregion); 368 } 369 env->sau.rnr = 0; 370 /* SAU_CTRL reset value is IMPDEF; we choose 0, which is what 371 * the Cortex-M33 does. 372 */ 373 env->sau.ctrl = 0; 374 } 375 376 set_flush_to_zero(1, &env->vfp.standard_fp_status); 377 set_flush_inputs_to_zero(1, &env->vfp.standard_fp_status); 378 set_default_nan_mode(1, &env->vfp.standard_fp_status); 379 set_float_detect_tininess(float_tininess_before_rounding, 380 &env->vfp.fp_status); 381 set_float_detect_tininess(float_tininess_before_rounding, 382 &env->vfp.standard_fp_status); 383 set_float_detect_tininess(float_tininess_before_rounding, 384 &env->vfp.fp_status_f16); 385 #ifndef CONFIG_USER_ONLY 386 if (kvm_enabled()) { 387 kvm_arm_reset_vcpu(cpu); 388 } 389 #endif 390 391 hw_breakpoint_update_all(cpu); 392 hw_watchpoint_update_all(cpu); 393 } 394 395 bool arm_cpu_exec_interrupt(CPUState *cs, int interrupt_request) 396 { 397 CPUClass *cc = CPU_GET_CLASS(cs); 398 CPUARMState *env = cs->env_ptr; 399 uint32_t cur_el = arm_current_el(env); 400 bool secure = arm_is_secure(env); 401 uint32_t target_el; 402 uint32_t excp_idx; 403 bool ret = false; 404 405 if (interrupt_request & CPU_INTERRUPT_FIQ) { 406 excp_idx = EXCP_FIQ; 407 target_el = arm_phys_excp_target_el(cs, excp_idx, cur_el, secure); 408 if (arm_excp_unmasked(cs, excp_idx, target_el)) { 409 cs->exception_index = excp_idx; 410 env->exception.target_el = target_el; 411 cc->do_interrupt(cs); 412 ret = true; 413 } 414 } 415 if (interrupt_request & CPU_INTERRUPT_HARD) { 416 excp_idx = EXCP_IRQ; 417 target_el = arm_phys_excp_target_el(cs, excp_idx, cur_el, secure); 418 if (arm_excp_unmasked(cs, excp_idx, target_el)) { 419 cs->exception_index = excp_idx; 420 env->exception.target_el = target_el; 421 cc->do_interrupt(cs); 422 ret = true; 423 } 424 } 425 if (interrupt_request & CPU_INTERRUPT_VIRQ) { 426 excp_idx = EXCP_VIRQ; 427 target_el = 1; 428 if (arm_excp_unmasked(cs, excp_idx, target_el)) { 429 cs->exception_index = excp_idx; 430 env->exception.target_el = target_el; 431 cc->do_interrupt(cs); 432 ret = true; 433 } 434 } 435 if (interrupt_request & CPU_INTERRUPT_VFIQ) { 436 excp_idx = EXCP_VFIQ; 437 target_el = 1; 438 if (arm_excp_unmasked(cs, excp_idx, target_el)) { 439 cs->exception_index = excp_idx; 440 env->exception.target_el = target_el; 441 cc->do_interrupt(cs); 442 ret = true; 443 } 444 } 445 446 return ret; 447 } 448 449 #if !defined(CONFIG_USER_ONLY) || !defined(TARGET_AARCH64) 450 static bool arm_v7m_cpu_exec_interrupt(CPUState *cs, int interrupt_request) 451 { 452 CPUClass *cc = CPU_GET_CLASS(cs); 453 ARMCPU *cpu = ARM_CPU(cs); 454 CPUARMState *env = &cpu->env; 455 bool ret = false; 456 457 /* ARMv7-M interrupt masking works differently than -A or -R. 458 * There is no FIQ/IRQ distinction. Instead of I and F bits 459 * masking FIQ and IRQ interrupts, an exception is taken only 460 * if it is higher priority than the current execution priority 461 * (which depends on state like BASEPRI, FAULTMASK and the 462 * currently active exception). 463 */ 464 if (interrupt_request & CPU_INTERRUPT_HARD 465 && (armv7m_nvic_can_take_pending_exception(env->nvic))) { 466 cs->exception_index = EXCP_IRQ; 467 cc->do_interrupt(cs); 468 ret = true; 469 } 470 return ret; 471 } 472 #endif 473 474 void arm_cpu_update_virq(ARMCPU *cpu) 475 { 476 /* 477 * Update the interrupt level for VIRQ, which is the logical OR of 478 * the HCR_EL2.VI bit and the input line level from the GIC. 479 */ 480 CPUARMState *env = &cpu->env; 481 CPUState *cs = CPU(cpu); 482 483 bool new_state = (env->cp15.hcr_el2 & HCR_VI) || 484 (env->irq_line_state & CPU_INTERRUPT_VIRQ); 485 486 if (new_state != ((cs->interrupt_request & CPU_INTERRUPT_VIRQ) != 0)) { 487 if (new_state) { 488 cpu_interrupt(cs, CPU_INTERRUPT_VIRQ); 489 } else { 490 cpu_reset_interrupt(cs, CPU_INTERRUPT_VIRQ); 491 } 492 } 493 } 494 495 void arm_cpu_update_vfiq(ARMCPU *cpu) 496 { 497 /* 498 * Update the interrupt level for VFIQ, which is the logical OR of 499 * the HCR_EL2.VF bit and the input line level from the GIC. 500 */ 501 CPUARMState *env = &cpu->env; 502 CPUState *cs = CPU(cpu); 503 504 bool new_state = (env->cp15.hcr_el2 & HCR_VF) || 505 (env->irq_line_state & CPU_INTERRUPT_VFIQ); 506 507 if (new_state != ((cs->interrupt_request & CPU_INTERRUPT_VFIQ) != 0)) { 508 if (new_state) { 509 cpu_interrupt(cs, CPU_INTERRUPT_VFIQ); 510 } else { 511 cpu_reset_interrupt(cs, CPU_INTERRUPT_VFIQ); 512 } 513 } 514 } 515 516 #ifndef CONFIG_USER_ONLY 517 static void arm_cpu_set_irq(void *opaque, int irq, int level) 518 { 519 ARMCPU *cpu = opaque; 520 CPUARMState *env = &cpu->env; 521 CPUState *cs = CPU(cpu); 522 static const int mask[] = { 523 [ARM_CPU_IRQ] = CPU_INTERRUPT_HARD, 524 [ARM_CPU_FIQ] = CPU_INTERRUPT_FIQ, 525 [ARM_CPU_VIRQ] = CPU_INTERRUPT_VIRQ, 526 [ARM_CPU_VFIQ] = CPU_INTERRUPT_VFIQ 527 }; 528 529 if (level) { 530 env->irq_line_state |= mask[irq]; 531 } else { 532 env->irq_line_state &= ~mask[irq]; 533 } 534 535 switch (irq) { 536 case ARM_CPU_VIRQ: 537 assert(arm_feature(env, ARM_FEATURE_EL2)); 538 arm_cpu_update_virq(cpu); 539 break; 540 case ARM_CPU_VFIQ: 541 assert(arm_feature(env, ARM_FEATURE_EL2)); 542 arm_cpu_update_vfiq(cpu); 543 break; 544 case ARM_CPU_IRQ: 545 case ARM_CPU_FIQ: 546 if (level) { 547 cpu_interrupt(cs, mask[irq]); 548 } else { 549 cpu_reset_interrupt(cs, mask[irq]); 550 } 551 break; 552 default: 553 g_assert_not_reached(); 554 } 555 } 556 557 static void arm_cpu_kvm_set_irq(void *opaque, int irq, int level) 558 { 559 #ifdef CONFIG_KVM 560 ARMCPU *cpu = opaque; 561 CPUARMState *env = &cpu->env; 562 CPUState *cs = CPU(cpu); 563 int kvm_irq = KVM_ARM_IRQ_TYPE_CPU << KVM_ARM_IRQ_TYPE_SHIFT; 564 uint32_t linestate_bit; 565 566 switch (irq) { 567 case ARM_CPU_IRQ: 568 kvm_irq |= KVM_ARM_IRQ_CPU_IRQ; 569 linestate_bit = CPU_INTERRUPT_HARD; 570 break; 571 case ARM_CPU_FIQ: 572 kvm_irq |= KVM_ARM_IRQ_CPU_FIQ; 573 linestate_bit = CPU_INTERRUPT_FIQ; 574 break; 575 default: 576 g_assert_not_reached(); 577 } 578 579 if (level) { 580 env->irq_line_state |= linestate_bit; 581 } else { 582 env->irq_line_state &= ~linestate_bit; 583 } 584 585 kvm_irq |= cs->cpu_index << KVM_ARM_IRQ_VCPU_SHIFT; 586 kvm_set_irq(kvm_state, kvm_irq, level ? 1 : 0); 587 #endif 588 } 589 590 static bool arm_cpu_virtio_is_big_endian(CPUState *cs) 591 { 592 ARMCPU *cpu = ARM_CPU(cs); 593 CPUARMState *env = &cpu->env; 594 595 cpu_synchronize_state(cs); 596 return arm_cpu_data_is_big_endian(env); 597 } 598 599 #endif 600 601 static inline void set_feature(CPUARMState *env, int feature) 602 { 603 env->features |= 1ULL << feature; 604 } 605 606 static inline void unset_feature(CPUARMState *env, int feature) 607 { 608 env->features &= ~(1ULL << feature); 609 } 610 611 static int 612 print_insn_thumb1(bfd_vma pc, disassemble_info *info) 613 { 614 return print_insn_arm(pc | 1, info); 615 } 616 617 static void arm_disas_set_info(CPUState *cpu, disassemble_info *info) 618 { 619 ARMCPU *ac = ARM_CPU(cpu); 620 CPUARMState *env = &ac->env; 621 bool sctlr_b; 622 623 if (is_a64(env)) { 624 /* We might not be compiled with the A64 disassembler 625 * because it needs a C++ compiler. Leave print_insn 626 * unset in this case to use the caller default behaviour. 627 */ 628 #if defined(CONFIG_ARM_A64_DIS) 629 info->print_insn = print_insn_arm_a64; 630 #endif 631 info->cap_arch = CS_ARCH_ARM64; 632 info->cap_insn_unit = 4; 633 info->cap_insn_split = 4; 634 } else { 635 int cap_mode; 636 if (env->thumb) { 637 info->print_insn = print_insn_thumb1; 638 info->cap_insn_unit = 2; 639 info->cap_insn_split = 4; 640 cap_mode = CS_MODE_THUMB; 641 } else { 642 info->print_insn = print_insn_arm; 643 info->cap_insn_unit = 4; 644 info->cap_insn_split = 4; 645 cap_mode = CS_MODE_ARM; 646 } 647 if (arm_feature(env, ARM_FEATURE_V8)) { 648 cap_mode |= CS_MODE_V8; 649 } 650 if (arm_feature(env, ARM_FEATURE_M)) { 651 cap_mode |= CS_MODE_MCLASS; 652 } 653 info->cap_arch = CS_ARCH_ARM; 654 info->cap_mode = cap_mode; 655 } 656 657 sctlr_b = arm_sctlr_b(env); 658 if (bswap_code(sctlr_b)) { 659 #ifdef TARGET_WORDS_BIGENDIAN 660 info->endian = BFD_ENDIAN_LITTLE; 661 #else 662 info->endian = BFD_ENDIAN_BIG; 663 #endif 664 } 665 info->flags &= ~INSN_ARM_BE32; 666 #ifndef CONFIG_USER_ONLY 667 if (sctlr_b) { 668 info->flags |= INSN_ARM_BE32; 669 } 670 #endif 671 } 672 673 uint64_t arm_cpu_mp_affinity(int idx, uint8_t clustersz) 674 { 675 uint32_t Aff1 = idx / clustersz; 676 uint32_t Aff0 = idx % clustersz; 677 return (Aff1 << ARM_AFF1_SHIFT) | Aff0; 678 } 679 680 static void cpreg_hashtable_data_destroy(gpointer data) 681 { 682 /* 683 * Destroy function for cpu->cp_regs hashtable data entries. 684 * We must free the name string because it was g_strdup()ed in 685 * add_cpreg_to_hashtable(). It's OK to cast away the 'const' 686 * from r->name because we know we definitely allocated it. 687 */ 688 ARMCPRegInfo *r = data; 689 690 g_free((void *)r->name); 691 g_free(r); 692 } 693 694 static void arm_cpu_initfn(Object *obj) 695 { 696 CPUState *cs = CPU(obj); 697 ARMCPU *cpu = ARM_CPU(obj); 698 699 cs->env_ptr = &cpu->env; 700 cpu->cp_regs = g_hash_table_new_full(g_int_hash, g_int_equal, 701 g_free, cpreg_hashtable_data_destroy); 702 703 QLIST_INIT(&cpu->pre_el_change_hooks); 704 QLIST_INIT(&cpu->el_change_hooks); 705 706 #ifndef CONFIG_USER_ONLY 707 /* Our inbound IRQ and FIQ lines */ 708 if (kvm_enabled()) { 709 /* VIRQ and VFIQ are unused with KVM but we add them to maintain 710 * the same interface as non-KVM CPUs. 711 */ 712 qdev_init_gpio_in(DEVICE(cpu), arm_cpu_kvm_set_irq, 4); 713 } else { 714 qdev_init_gpio_in(DEVICE(cpu), arm_cpu_set_irq, 4); 715 } 716 717 qdev_init_gpio_out(DEVICE(cpu), cpu->gt_timer_outputs, 718 ARRAY_SIZE(cpu->gt_timer_outputs)); 719 720 qdev_init_gpio_out_named(DEVICE(cpu), &cpu->gicv3_maintenance_interrupt, 721 "gicv3-maintenance-interrupt", 1); 722 qdev_init_gpio_out_named(DEVICE(cpu), &cpu->pmu_interrupt, 723 "pmu-interrupt", 1); 724 #endif 725 726 /* DTB consumers generally don't in fact care what the 'compatible' 727 * string is, so always provide some string and trust that a hypothetical 728 * picky DTB consumer will also provide a helpful error message. 729 */ 730 cpu->dtb_compatible = "qemu,unknown"; 731 cpu->psci_version = 1; /* By default assume PSCI v0.1 */ 732 cpu->kvm_target = QEMU_KVM_ARM_TARGET_NONE; 733 734 if (tcg_enabled()) { 735 cpu->psci_version = 2; /* TCG implements PSCI 0.2 */ 736 } 737 } 738 739 static Property arm_cpu_reset_cbar_property = 740 DEFINE_PROP_UINT64("reset-cbar", ARMCPU, reset_cbar, 0); 741 742 static Property arm_cpu_reset_hivecs_property = 743 DEFINE_PROP_BOOL("reset-hivecs", ARMCPU, reset_hivecs, false); 744 745 static Property arm_cpu_rvbar_property = 746 DEFINE_PROP_UINT64("rvbar", ARMCPU, rvbar, 0); 747 748 static Property arm_cpu_has_el2_property = 749 DEFINE_PROP_BOOL("has_el2", ARMCPU, has_el2, true); 750 751 static Property arm_cpu_has_el3_property = 752 DEFINE_PROP_BOOL("has_el3", ARMCPU, has_el3, true); 753 754 static Property arm_cpu_cfgend_property = 755 DEFINE_PROP_BOOL("cfgend", ARMCPU, cfgend, false); 756 757 /* use property name "pmu" to match other archs and virt tools */ 758 static Property arm_cpu_has_pmu_property = 759 DEFINE_PROP_BOOL("pmu", ARMCPU, has_pmu, true); 760 761 static Property arm_cpu_has_mpu_property = 762 DEFINE_PROP_BOOL("has-mpu", ARMCPU, has_mpu, true); 763 764 /* This is like DEFINE_PROP_UINT32 but it doesn't set the default value, 765 * because the CPU initfn will have already set cpu->pmsav7_dregion to 766 * the right value for that particular CPU type, and we don't want 767 * to override that with an incorrect constant value. 768 */ 769 static Property arm_cpu_pmsav7_dregion_property = 770 DEFINE_PROP_UNSIGNED_NODEFAULT("pmsav7-dregion", ARMCPU, 771 pmsav7_dregion, 772 qdev_prop_uint32, uint32_t); 773 774 static void arm_get_init_svtor(Object *obj, Visitor *v, const char *name, 775 void *opaque, Error **errp) 776 { 777 ARMCPU *cpu = ARM_CPU(obj); 778 779 visit_type_uint32(v, name, &cpu->init_svtor, errp); 780 } 781 782 static void arm_set_init_svtor(Object *obj, Visitor *v, const char *name, 783 void *opaque, Error **errp) 784 { 785 ARMCPU *cpu = ARM_CPU(obj); 786 787 visit_type_uint32(v, name, &cpu->init_svtor, errp); 788 } 789 790 void arm_cpu_post_init(Object *obj) 791 { 792 ARMCPU *cpu = ARM_CPU(obj); 793 794 /* M profile implies PMSA. We have to do this here rather than 795 * in realize with the other feature-implication checks because 796 * we look at the PMSA bit to see if we should add some properties. 797 */ 798 if (arm_feature(&cpu->env, ARM_FEATURE_M)) { 799 set_feature(&cpu->env, ARM_FEATURE_PMSA); 800 } 801 802 if (arm_feature(&cpu->env, ARM_FEATURE_CBAR) || 803 arm_feature(&cpu->env, ARM_FEATURE_CBAR_RO)) { 804 qdev_property_add_static(DEVICE(obj), &arm_cpu_reset_cbar_property, 805 &error_abort); 806 } 807 808 if (!arm_feature(&cpu->env, ARM_FEATURE_M)) { 809 qdev_property_add_static(DEVICE(obj), &arm_cpu_reset_hivecs_property, 810 &error_abort); 811 } 812 813 if (arm_feature(&cpu->env, ARM_FEATURE_AARCH64)) { 814 qdev_property_add_static(DEVICE(obj), &arm_cpu_rvbar_property, 815 &error_abort); 816 } 817 818 if (arm_feature(&cpu->env, ARM_FEATURE_EL3)) { 819 /* Add the has_el3 state CPU property only if EL3 is allowed. This will 820 * prevent "has_el3" from existing on CPUs which cannot support EL3. 821 */ 822 qdev_property_add_static(DEVICE(obj), &arm_cpu_has_el3_property, 823 &error_abort); 824 825 #ifndef CONFIG_USER_ONLY 826 object_property_add_link(obj, "secure-memory", 827 TYPE_MEMORY_REGION, 828 (Object **)&cpu->secure_memory, 829 qdev_prop_allow_set_link_before_realize, 830 OBJ_PROP_LINK_STRONG, 831 &error_abort); 832 #endif 833 } 834 835 if (arm_feature(&cpu->env, ARM_FEATURE_EL2)) { 836 qdev_property_add_static(DEVICE(obj), &arm_cpu_has_el2_property, 837 &error_abort); 838 } 839 840 if (arm_feature(&cpu->env, ARM_FEATURE_PMU)) { 841 qdev_property_add_static(DEVICE(obj), &arm_cpu_has_pmu_property, 842 &error_abort); 843 } 844 845 if (arm_feature(&cpu->env, ARM_FEATURE_PMSA)) { 846 qdev_property_add_static(DEVICE(obj), &arm_cpu_has_mpu_property, 847 &error_abort); 848 if (arm_feature(&cpu->env, ARM_FEATURE_V7)) { 849 qdev_property_add_static(DEVICE(obj), 850 &arm_cpu_pmsav7_dregion_property, 851 &error_abort); 852 } 853 } 854 855 if (arm_feature(&cpu->env, ARM_FEATURE_M_SECURITY)) { 856 object_property_add_link(obj, "idau", TYPE_IDAU_INTERFACE, &cpu->idau, 857 qdev_prop_allow_set_link_before_realize, 858 OBJ_PROP_LINK_STRONG, 859 &error_abort); 860 /* 861 * M profile: initial value of the Secure VTOR. We can't just use 862 * a simple DEFINE_PROP_UINT32 for this because we want to permit 863 * the property to be set after realize. 864 */ 865 object_property_add(obj, "init-svtor", "uint32", 866 arm_get_init_svtor, arm_set_init_svtor, 867 NULL, NULL, &error_abort); 868 } 869 870 qdev_property_add_static(DEVICE(obj), &arm_cpu_cfgend_property, 871 &error_abort); 872 } 873 874 static void arm_cpu_finalizefn(Object *obj) 875 { 876 ARMCPU *cpu = ARM_CPU(obj); 877 ARMELChangeHook *hook, *next; 878 879 g_hash_table_destroy(cpu->cp_regs); 880 881 QLIST_FOREACH_SAFE(hook, &cpu->pre_el_change_hooks, node, next) { 882 QLIST_REMOVE(hook, node); 883 g_free(hook); 884 } 885 QLIST_FOREACH_SAFE(hook, &cpu->el_change_hooks, node, next) { 886 QLIST_REMOVE(hook, node); 887 g_free(hook); 888 } 889 #ifndef CONFIG_USER_ONLY 890 if (cpu->pmu_timer) { 891 timer_del(cpu->pmu_timer); 892 timer_deinit(cpu->pmu_timer); 893 timer_free(cpu->pmu_timer); 894 } 895 #endif 896 } 897 898 static void arm_cpu_realizefn(DeviceState *dev, Error **errp) 899 { 900 CPUState *cs = CPU(dev); 901 ARMCPU *cpu = ARM_CPU(dev); 902 ARMCPUClass *acc = ARM_CPU_GET_CLASS(dev); 903 CPUARMState *env = &cpu->env; 904 int pagebits; 905 Error *local_err = NULL; 906 bool no_aa32 = false; 907 908 /* If we needed to query the host kernel for the CPU features 909 * then it's possible that might have failed in the initfn, but 910 * this is the first point where we can report it. 911 */ 912 if (cpu->host_cpu_probe_failed) { 913 if (!kvm_enabled()) { 914 error_setg(errp, "The 'host' CPU type can only be used with KVM"); 915 } else { 916 error_setg(errp, "Failed to retrieve host CPU features"); 917 } 918 return; 919 } 920 921 #ifndef CONFIG_USER_ONLY 922 /* The NVIC and M-profile CPU are two halves of a single piece of 923 * hardware; trying to use one without the other is a command line 924 * error and will result in segfaults if not caught here. 925 */ 926 if (arm_feature(env, ARM_FEATURE_M)) { 927 if (!env->nvic) { 928 error_setg(errp, "This board cannot be used with Cortex-M CPUs"); 929 return; 930 } 931 } else { 932 if (env->nvic) { 933 error_setg(errp, "This board can only be used with Cortex-M CPUs"); 934 return; 935 } 936 } 937 938 cpu->gt_timer[GTIMER_PHYS] = timer_new(QEMU_CLOCK_VIRTUAL, GTIMER_SCALE, 939 arm_gt_ptimer_cb, cpu); 940 cpu->gt_timer[GTIMER_VIRT] = timer_new(QEMU_CLOCK_VIRTUAL, GTIMER_SCALE, 941 arm_gt_vtimer_cb, cpu); 942 cpu->gt_timer[GTIMER_HYP] = timer_new(QEMU_CLOCK_VIRTUAL, GTIMER_SCALE, 943 arm_gt_htimer_cb, cpu); 944 cpu->gt_timer[GTIMER_SEC] = timer_new(QEMU_CLOCK_VIRTUAL, GTIMER_SCALE, 945 arm_gt_stimer_cb, cpu); 946 #endif 947 948 cpu_exec_realizefn(cs, &local_err); 949 if (local_err != NULL) { 950 error_propagate(errp, local_err); 951 return; 952 } 953 954 /* Some features automatically imply others: */ 955 if (arm_feature(env, ARM_FEATURE_V8)) { 956 if (arm_feature(env, ARM_FEATURE_M)) { 957 set_feature(env, ARM_FEATURE_V7); 958 } else { 959 set_feature(env, ARM_FEATURE_V7VE); 960 } 961 } 962 963 /* 964 * There exist AArch64 cpus without AArch32 support. When KVM 965 * queries ID_ISAR0_EL1 on such a host, the value is UNKNOWN. 966 * Similarly, we cannot check ID_AA64PFR0 without AArch64 support. 967 */ 968 if (arm_feature(&cpu->env, ARM_FEATURE_AARCH64)) { 969 no_aa32 = !cpu_isar_feature(aa64_aa32, cpu); 970 } 971 972 if (arm_feature(env, ARM_FEATURE_V7VE)) { 973 /* v7 Virtualization Extensions. In real hardware this implies 974 * EL2 and also the presence of the Security Extensions. 975 * For QEMU, for backwards-compatibility we implement some 976 * CPUs or CPU configs which have no actual EL2 or EL3 but do 977 * include the various other features that V7VE implies. 978 * Presence of EL2 itself is ARM_FEATURE_EL2, and of the 979 * Security Extensions is ARM_FEATURE_EL3. 980 */ 981 assert(no_aa32 || cpu_isar_feature(arm_div, cpu)); 982 set_feature(env, ARM_FEATURE_LPAE); 983 set_feature(env, ARM_FEATURE_V7); 984 } 985 if (arm_feature(env, ARM_FEATURE_V7)) { 986 set_feature(env, ARM_FEATURE_VAPA); 987 set_feature(env, ARM_FEATURE_THUMB2); 988 set_feature(env, ARM_FEATURE_MPIDR); 989 if (!arm_feature(env, ARM_FEATURE_M)) { 990 set_feature(env, ARM_FEATURE_V6K); 991 } else { 992 set_feature(env, ARM_FEATURE_V6); 993 } 994 995 /* Always define VBAR for V7 CPUs even if it doesn't exist in 996 * non-EL3 configs. This is needed by some legacy boards. 997 */ 998 set_feature(env, ARM_FEATURE_VBAR); 999 } 1000 if (arm_feature(env, ARM_FEATURE_V6K)) { 1001 set_feature(env, ARM_FEATURE_V6); 1002 set_feature(env, ARM_FEATURE_MVFR); 1003 } 1004 if (arm_feature(env, ARM_FEATURE_V6)) { 1005 set_feature(env, ARM_FEATURE_V5); 1006 if (!arm_feature(env, ARM_FEATURE_M)) { 1007 assert(no_aa32 || cpu_isar_feature(jazelle, cpu)); 1008 set_feature(env, ARM_FEATURE_AUXCR); 1009 } 1010 } 1011 if (arm_feature(env, ARM_FEATURE_V5)) { 1012 set_feature(env, ARM_FEATURE_V4T); 1013 } 1014 if (arm_feature(env, ARM_FEATURE_VFP4)) { 1015 set_feature(env, ARM_FEATURE_VFP3); 1016 } 1017 if (arm_feature(env, ARM_FEATURE_VFP3)) { 1018 set_feature(env, ARM_FEATURE_VFP); 1019 } 1020 if (arm_feature(env, ARM_FEATURE_LPAE)) { 1021 set_feature(env, ARM_FEATURE_V7MP); 1022 set_feature(env, ARM_FEATURE_PXN); 1023 } 1024 if (arm_feature(env, ARM_FEATURE_CBAR_RO)) { 1025 set_feature(env, ARM_FEATURE_CBAR); 1026 } 1027 if (arm_feature(env, ARM_FEATURE_THUMB2) && 1028 !arm_feature(env, ARM_FEATURE_M)) { 1029 set_feature(env, ARM_FEATURE_THUMB_DSP); 1030 } 1031 1032 if (arm_feature(env, ARM_FEATURE_V7) && 1033 !arm_feature(env, ARM_FEATURE_M) && 1034 !arm_feature(env, ARM_FEATURE_PMSA)) { 1035 /* v7VMSA drops support for the old ARMv5 tiny pages, so we 1036 * can use 4K pages. 1037 */ 1038 pagebits = 12; 1039 } else { 1040 /* For CPUs which might have tiny 1K pages, or which have an 1041 * MPU and might have small region sizes, stick with 1K pages. 1042 */ 1043 pagebits = 10; 1044 } 1045 if (!set_preferred_target_page_bits(pagebits)) { 1046 /* This can only ever happen for hotplugging a CPU, or if 1047 * the board code incorrectly creates a CPU which it has 1048 * promised via minimum_page_size that it will not. 1049 */ 1050 error_setg(errp, "This CPU requires a smaller page size than the " 1051 "system is using"); 1052 return; 1053 } 1054 1055 /* This cpu-id-to-MPIDR affinity is used only for TCG; KVM will override it. 1056 * We don't support setting cluster ID ([16..23]) (known as Aff2 1057 * in later ARM ARM versions), or any of the higher affinity level fields, 1058 * so these bits always RAZ. 1059 */ 1060 if (cpu->mp_affinity == ARM64_AFFINITY_INVALID) { 1061 cpu->mp_affinity = arm_cpu_mp_affinity(cs->cpu_index, 1062 ARM_DEFAULT_CPUS_PER_CLUSTER); 1063 } 1064 1065 if (cpu->reset_hivecs) { 1066 cpu->reset_sctlr |= (1 << 13); 1067 } 1068 1069 if (cpu->cfgend) { 1070 if (arm_feature(&cpu->env, ARM_FEATURE_V7)) { 1071 cpu->reset_sctlr |= SCTLR_EE; 1072 } else { 1073 cpu->reset_sctlr |= SCTLR_B; 1074 } 1075 } 1076 1077 if (!cpu->has_el3) { 1078 /* If the has_el3 CPU property is disabled then we need to disable the 1079 * feature. 1080 */ 1081 unset_feature(env, ARM_FEATURE_EL3); 1082 1083 /* Disable the security extension feature bits in the processor feature 1084 * registers as well. These are id_pfr1[7:4] and id_aa64pfr0[15:12]. 1085 */ 1086 cpu->id_pfr1 &= ~0xf0; 1087 cpu->isar.id_aa64pfr0 &= ~0xf000; 1088 } 1089 1090 if (!cpu->has_el2) { 1091 unset_feature(env, ARM_FEATURE_EL2); 1092 } 1093 1094 if (!cpu->has_pmu) { 1095 unset_feature(env, ARM_FEATURE_PMU); 1096 } 1097 if (arm_feature(env, ARM_FEATURE_PMU)) { 1098 pmu_init(cpu); 1099 1100 if (!kvm_enabled()) { 1101 arm_register_pre_el_change_hook(cpu, &pmu_pre_el_change, 0); 1102 arm_register_el_change_hook(cpu, &pmu_post_el_change, 0); 1103 } 1104 1105 #ifndef CONFIG_USER_ONLY 1106 cpu->pmu_timer = timer_new_ns(QEMU_CLOCK_VIRTUAL, arm_pmu_timer_cb, 1107 cpu); 1108 #endif 1109 } else { 1110 cpu->id_aa64dfr0 &= ~0xf00; 1111 cpu->id_dfr0 &= ~(0xf << 24); 1112 cpu->pmceid0 = 0; 1113 cpu->pmceid1 = 0; 1114 } 1115 1116 if (!arm_feature(env, ARM_FEATURE_EL2)) { 1117 /* Disable the hypervisor feature bits in the processor feature 1118 * registers if we don't have EL2. These are id_pfr1[15:12] and 1119 * id_aa64pfr0_el1[11:8]. 1120 */ 1121 cpu->isar.id_aa64pfr0 &= ~0xf00; 1122 cpu->id_pfr1 &= ~0xf000; 1123 } 1124 1125 /* MPU can be configured out of a PMSA CPU either by setting has-mpu 1126 * to false or by setting pmsav7-dregion to 0. 1127 */ 1128 if (!cpu->has_mpu) { 1129 cpu->pmsav7_dregion = 0; 1130 } 1131 if (cpu->pmsav7_dregion == 0) { 1132 cpu->has_mpu = false; 1133 } 1134 1135 if (arm_feature(env, ARM_FEATURE_PMSA) && 1136 arm_feature(env, ARM_FEATURE_V7)) { 1137 uint32_t nr = cpu->pmsav7_dregion; 1138 1139 if (nr > 0xff) { 1140 error_setg(errp, "PMSAv7 MPU #regions invalid %" PRIu32, nr); 1141 return; 1142 } 1143 1144 if (nr) { 1145 if (arm_feature(env, ARM_FEATURE_V8)) { 1146 /* PMSAv8 */ 1147 env->pmsav8.rbar[M_REG_NS] = g_new0(uint32_t, nr); 1148 env->pmsav8.rlar[M_REG_NS] = g_new0(uint32_t, nr); 1149 if (arm_feature(env, ARM_FEATURE_M_SECURITY)) { 1150 env->pmsav8.rbar[M_REG_S] = g_new0(uint32_t, nr); 1151 env->pmsav8.rlar[M_REG_S] = g_new0(uint32_t, nr); 1152 } 1153 } else { 1154 env->pmsav7.drbar = g_new0(uint32_t, nr); 1155 env->pmsav7.drsr = g_new0(uint32_t, nr); 1156 env->pmsav7.dracr = g_new0(uint32_t, nr); 1157 } 1158 } 1159 } 1160 1161 if (arm_feature(env, ARM_FEATURE_M_SECURITY)) { 1162 uint32_t nr = cpu->sau_sregion; 1163 1164 if (nr > 0xff) { 1165 error_setg(errp, "v8M SAU #regions invalid %" PRIu32, nr); 1166 return; 1167 } 1168 1169 if (nr) { 1170 env->sau.rbar = g_new0(uint32_t, nr); 1171 env->sau.rlar = g_new0(uint32_t, nr); 1172 } 1173 } 1174 1175 if (arm_feature(env, ARM_FEATURE_EL3)) { 1176 set_feature(env, ARM_FEATURE_VBAR); 1177 } 1178 1179 register_cp_regs_for_features(cpu); 1180 arm_cpu_register_gdb_regs_for_features(cpu); 1181 1182 init_cpreg_list(cpu); 1183 1184 #ifndef CONFIG_USER_ONLY 1185 if (cpu->has_el3 || arm_feature(env, ARM_FEATURE_M_SECURITY)) { 1186 cs->num_ases = 2; 1187 1188 if (!cpu->secure_memory) { 1189 cpu->secure_memory = cs->memory; 1190 } 1191 cpu_address_space_init(cs, ARMASIdx_S, "cpu-secure-memory", 1192 cpu->secure_memory); 1193 } else { 1194 cs->num_ases = 1; 1195 } 1196 cpu_address_space_init(cs, ARMASIdx_NS, "cpu-memory", cs->memory); 1197 1198 /* No core_count specified, default to smp_cpus. */ 1199 if (cpu->core_count == -1) { 1200 cpu->core_count = smp_cpus; 1201 } 1202 #endif 1203 1204 qemu_init_vcpu(cs); 1205 cpu_reset(cs); 1206 1207 acc->parent_realize(dev, errp); 1208 } 1209 1210 static ObjectClass *arm_cpu_class_by_name(const char *cpu_model) 1211 { 1212 ObjectClass *oc; 1213 char *typename; 1214 char **cpuname; 1215 const char *cpunamestr; 1216 1217 cpuname = g_strsplit(cpu_model, ",", 1); 1218 cpunamestr = cpuname[0]; 1219 #ifdef CONFIG_USER_ONLY 1220 /* For backwards compatibility usermode emulation allows "-cpu any", 1221 * which has the same semantics as "-cpu max". 1222 */ 1223 if (!strcmp(cpunamestr, "any")) { 1224 cpunamestr = "max"; 1225 } 1226 #endif 1227 typename = g_strdup_printf(ARM_CPU_TYPE_NAME("%s"), cpunamestr); 1228 oc = object_class_by_name(typename); 1229 g_strfreev(cpuname); 1230 g_free(typename); 1231 if (!oc || !object_class_dynamic_cast(oc, TYPE_ARM_CPU) || 1232 object_class_is_abstract(oc)) { 1233 return NULL; 1234 } 1235 return oc; 1236 } 1237 1238 /* CPU models. These are not needed for the AArch64 linux-user build. */ 1239 #if !defined(CONFIG_USER_ONLY) || !defined(TARGET_AARCH64) 1240 1241 static void arm926_initfn(Object *obj) 1242 { 1243 ARMCPU *cpu = ARM_CPU(obj); 1244 1245 cpu->dtb_compatible = "arm,arm926"; 1246 set_feature(&cpu->env, ARM_FEATURE_V5); 1247 set_feature(&cpu->env, ARM_FEATURE_VFP); 1248 set_feature(&cpu->env, ARM_FEATURE_DUMMY_C15_REGS); 1249 set_feature(&cpu->env, ARM_FEATURE_CACHE_TEST_CLEAN); 1250 cpu->midr = 0x41069265; 1251 cpu->reset_fpsid = 0x41011090; 1252 cpu->ctr = 0x1dd20d2; 1253 cpu->reset_sctlr = 0x00090078; 1254 1255 /* 1256 * ARMv5 does not have the ID_ISAR registers, but we can still 1257 * set the field to indicate Jazelle support within QEMU. 1258 */ 1259 cpu->isar.id_isar1 = FIELD_DP32(cpu->isar.id_isar1, ID_ISAR1, JAZELLE, 1); 1260 } 1261 1262 static void arm946_initfn(Object *obj) 1263 { 1264 ARMCPU *cpu = ARM_CPU(obj); 1265 1266 cpu->dtb_compatible = "arm,arm946"; 1267 set_feature(&cpu->env, ARM_FEATURE_V5); 1268 set_feature(&cpu->env, ARM_FEATURE_PMSA); 1269 set_feature(&cpu->env, ARM_FEATURE_DUMMY_C15_REGS); 1270 cpu->midr = 0x41059461; 1271 cpu->ctr = 0x0f004006; 1272 cpu->reset_sctlr = 0x00000078; 1273 } 1274 1275 static void arm1026_initfn(Object *obj) 1276 { 1277 ARMCPU *cpu = ARM_CPU(obj); 1278 1279 cpu->dtb_compatible = "arm,arm1026"; 1280 set_feature(&cpu->env, ARM_FEATURE_V5); 1281 set_feature(&cpu->env, ARM_FEATURE_VFP); 1282 set_feature(&cpu->env, ARM_FEATURE_AUXCR); 1283 set_feature(&cpu->env, ARM_FEATURE_DUMMY_C15_REGS); 1284 set_feature(&cpu->env, ARM_FEATURE_CACHE_TEST_CLEAN); 1285 cpu->midr = 0x4106a262; 1286 cpu->reset_fpsid = 0x410110a0; 1287 cpu->ctr = 0x1dd20d2; 1288 cpu->reset_sctlr = 0x00090078; 1289 cpu->reset_auxcr = 1; 1290 1291 /* 1292 * ARMv5 does not have the ID_ISAR registers, but we can still 1293 * set the field to indicate Jazelle support within QEMU. 1294 */ 1295 cpu->isar.id_isar1 = FIELD_DP32(cpu->isar.id_isar1, ID_ISAR1, JAZELLE, 1); 1296 1297 { 1298 /* The 1026 had an IFAR at c6,c0,0,1 rather than the ARMv6 c6,c0,0,2 */ 1299 ARMCPRegInfo ifar = { 1300 .name = "IFAR", .cp = 15, .crn = 6, .crm = 0, .opc1 = 0, .opc2 = 1, 1301 .access = PL1_RW, 1302 .fieldoffset = offsetof(CPUARMState, cp15.ifar_ns), 1303 .resetvalue = 0 1304 }; 1305 define_one_arm_cp_reg(cpu, &ifar); 1306 } 1307 } 1308 1309 static void arm1136_r2_initfn(Object *obj) 1310 { 1311 ARMCPU *cpu = ARM_CPU(obj); 1312 /* What qemu calls "arm1136_r2" is actually the 1136 r0p2, ie an 1313 * older core than plain "arm1136". In particular this does not 1314 * have the v6K features. 1315 * These ID register values are correct for 1136 but may be wrong 1316 * for 1136_r2 (in particular r0p2 does not actually implement most 1317 * of the ID registers). 1318 */ 1319 1320 cpu->dtb_compatible = "arm,arm1136"; 1321 set_feature(&cpu->env, ARM_FEATURE_V6); 1322 set_feature(&cpu->env, ARM_FEATURE_VFP); 1323 set_feature(&cpu->env, ARM_FEATURE_DUMMY_C15_REGS); 1324 set_feature(&cpu->env, ARM_FEATURE_CACHE_DIRTY_REG); 1325 set_feature(&cpu->env, ARM_FEATURE_CACHE_BLOCK_OPS); 1326 cpu->midr = 0x4107b362; 1327 cpu->reset_fpsid = 0x410120b4; 1328 cpu->isar.mvfr0 = 0x11111111; 1329 cpu->isar.mvfr1 = 0x00000000; 1330 cpu->ctr = 0x1dd20d2; 1331 cpu->reset_sctlr = 0x00050078; 1332 cpu->id_pfr0 = 0x111; 1333 cpu->id_pfr1 = 0x1; 1334 cpu->id_dfr0 = 0x2; 1335 cpu->id_afr0 = 0x3; 1336 cpu->id_mmfr0 = 0x01130003; 1337 cpu->id_mmfr1 = 0x10030302; 1338 cpu->id_mmfr2 = 0x01222110; 1339 cpu->isar.id_isar0 = 0x00140011; 1340 cpu->isar.id_isar1 = 0x12002111; 1341 cpu->isar.id_isar2 = 0x11231111; 1342 cpu->isar.id_isar3 = 0x01102131; 1343 cpu->isar.id_isar4 = 0x141; 1344 cpu->reset_auxcr = 7; 1345 } 1346 1347 static void arm1136_initfn(Object *obj) 1348 { 1349 ARMCPU *cpu = ARM_CPU(obj); 1350 1351 cpu->dtb_compatible = "arm,arm1136"; 1352 set_feature(&cpu->env, ARM_FEATURE_V6K); 1353 set_feature(&cpu->env, ARM_FEATURE_V6); 1354 set_feature(&cpu->env, ARM_FEATURE_VFP); 1355 set_feature(&cpu->env, ARM_FEATURE_DUMMY_C15_REGS); 1356 set_feature(&cpu->env, ARM_FEATURE_CACHE_DIRTY_REG); 1357 set_feature(&cpu->env, ARM_FEATURE_CACHE_BLOCK_OPS); 1358 cpu->midr = 0x4117b363; 1359 cpu->reset_fpsid = 0x410120b4; 1360 cpu->isar.mvfr0 = 0x11111111; 1361 cpu->isar.mvfr1 = 0x00000000; 1362 cpu->ctr = 0x1dd20d2; 1363 cpu->reset_sctlr = 0x00050078; 1364 cpu->id_pfr0 = 0x111; 1365 cpu->id_pfr1 = 0x1; 1366 cpu->id_dfr0 = 0x2; 1367 cpu->id_afr0 = 0x3; 1368 cpu->id_mmfr0 = 0x01130003; 1369 cpu->id_mmfr1 = 0x10030302; 1370 cpu->id_mmfr2 = 0x01222110; 1371 cpu->isar.id_isar0 = 0x00140011; 1372 cpu->isar.id_isar1 = 0x12002111; 1373 cpu->isar.id_isar2 = 0x11231111; 1374 cpu->isar.id_isar3 = 0x01102131; 1375 cpu->isar.id_isar4 = 0x141; 1376 cpu->reset_auxcr = 7; 1377 } 1378 1379 static void arm1176_initfn(Object *obj) 1380 { 1381 ARMCPU *cpu = ARM_CPU(obj); 1382 1383 cpu->dtb_compatible = "arm,arm1176"; 1384 set_feature(&cpu->env, ARM_FEATURE_V6K); 1385 set_feature(&cpu->env, ARM_FEATURE_VFP); 1386 set_feature(&cpu->env, ARM_FEATURE_VAPA); 1387 set_feature(&cpu->env, ARM_FEATURE_DUMMY_C15_REGS); 1388 set_feature(&cpu->env, ARM_FEATURE_CACHE_DIRTY_REG); 1389 set_feature(&cpu->env, ARM_FEATURE_CACHE_BLOCK_OPS); 1390 set_feature(&cpu->env, ARM_FEATURE_EL3); 1391 cpu->midr = 0x410fb767; 1392 cpu->reset_fpsid = 0x410120b5; 1393 cpu->isar.mvfr0 = 0x11111111; 1394 cpu->isar.mvfr1 = 0x00000000; 1395 cpu->ctr = 0x1dd20d2; 1396 cpu->reset_sctlr = 0x00050078; 1397 cpu->id_pfr0 = 0x111; 1398 cpu->id_pfr1 = 0x11; 1399 cpu->id_dfr0 = 0x33; 1400 cpu->id_afr0 = 0; 1401 cpu->id_mmfr0 = 0x01130003; 1402 cpu->id_mmfr1 = 0x10030302; 1403 cpu->id_mmfr2 = 0x01222100; 1404 cpu->isar.id_isar0 = 0x0140011; 1405 cpu->isar.id_isar1 = 0x12002111; 1406 cpu->isar.id_isar2 = 0x11231121; 1407 cpu->isar.id_isar3 = 0x01102131; 1408 cpu->isar.id_isar4 = 0x01141; 1409 cpu->reset_auxcr = 7; 1410 } 1411 1412 static void arm11mpcore_initfn(Object *obj) 1413 { 1414 ARMCPU *cpu = ARM_CPU(obj); 1415 1416 cpu->dtb_compatible = "arm,arm11mpcore"; 1417 set_feature(&cpu->env, ARM_FEATURE_V6K); 1418 set_feature(&cpu->env, ARM_FEATURE_VFP); 1419 set_feature(&cpu->env, ARM_FEATURE_VAPA); 1420 set_feature(&cpu->env, ARM_FEATURE_MPIDR); 1421 set_feature(&cpu->env, ARM_FEATURE_DUMMY_C15_REGS); 1422 cpu->midr = 0x410fb022; 1423 cpu->reset_fpsid = 0x410120b4; 1424 cpu->isar.mvfr0 = 0x11111111; 1425 cpu->isar.mvfr1 = 0x00000000; 1426 cpu->ctr = 0x1d192992; /* 32K icache 32K dcache */ 1427 cpu->id_pfr0 = 0x111; 1428 cpu->id_pfr1 = 0x1; 1429 cpu->id_dfr0 = 0; 1430 cpu->id_afr0 = 0x2; 1431 cpu->id_mmfr0 = 0x01100103; 1432 cpu->id_mmfr1 = 0x10020302; 1433 cpu->id_mmfr2 = 0x01222000; 1434 cpu->isar.id_isar0 = 0x00100011; 1435 cpu->isar.id_isar1 = 0x12002111; 1436 cpu->isar.id_isar2 = 0x11221011; 1437 cpu->isar.id_isar3 = 0x01102131; 1438 cpu->isar.id_isar4 = 0x141; 1439 cpu->reset_auxcr = 1; 1440 } 1441 1442 static void cortex_m0_initfn(Object *obj) 1443 { 1444 ARMCPU *cpu = ARM_CPU(obj); 1445 set_feature(&cpu->env, ARM_FEATURE_V6); 1446 set_feature(&cpu->env, ARM_FEATURE_M); 1447 1448 cpu->midr = 0x410cc200; 1449 } 1450 1451 static void cortex_m3_initfn(Object *obj) 1452 { 1453 ARMCPU *cpu = ARM_CPU(obj); 1454 set_feature(&cpu->env, ARM_FEATURE_V7); 1455 set_feature(&cpu->env, ARM_FEATURE_M); 1456 set_feature(&cpu->env, ARM_FEATURE_M_MAIN); 1457 cpu->midr = 0x410fc231; 1458 cpu->pmsav7_dregion = 8; 1459 cpu->id_pfr0 = 0x00000030; 1460 cpu->id_pfr1 = 0x00000200; 1461 cpu->id_dfr0 = 0x00100000; 1462 cpu->id_afr0 = 0x00000000; 1463 cpu->id_mmfr0 = 0x00000030; 1464 cpu->id_mmfr1 = 0x00000000; 1465 cpu->id_mmfr2 = 0x00000000; 1466 cpu->id_mmfr3 = 0x00000000; 1467 cpu->isar.id_isar0 = 0x01141110; 1468 cpu->isar.id_isar1 = 0x02111000; 1469 cpu->isar.id_isar2 = 0x21112231; 1470 cpu->isar.id_isar3 = 0x01111110; 1471 cpu->isar.id_isar4 = 0x01310102; 1472 cpu->isar.id_isar5 = 0x00000000; 1473 cpu->isar.id_isar6 = 0x00000000; 1474 } 1475 1476 static void cortex_m4_initfn(Object *obj) 1477 { 1478 ARMCPU *cpu = ARM_CPU(obj); 1479 1480 set_feature(&cpu->env, ARM_FEATURE_V7); 1481 set_feature(&cpu->env, ARM_FEATURE_M); 1482 set_feature(&cpu->env, ARM_FEATURE_M_MAIN); 1483 set_feature(&cpu->env, ARM_FEATURE_THUMB_DSP); 1484 cpu->midr = 0x410fc240; /* r0p0 */ 1485 cpu->pmsav7_dregion = 8; 1486 cpu->id_pfr0 = 0x00000030; 1487 cpu->id_pfr1 = 0x00000200; 1488 cpu->id_dfr0 = 0x00100000; 1489 cpu->id_afr0 = 0x00000000; 1490 cpu->id_mmfr0 = 0x00000030; 1491 cpu->id_mmfr1 = 0x00000000; 1492 cpu->id_mmfr2 = 0x00000000; 1493 cpu->id_mmfr3 = 0x00000000; 1494 cpu->isar.id_isar0 = 0x01141110; 1495 cpu->isar.id_isar1 = 0x02111000; 1496 cpu->isar.id_isar2 = 0x21112231; 1497 cpu->isar.id_isar3 = 0x01111110; 1498 cpu->isar.id_isar4 = 0x01310102; 1499 cpu->isar.id_isar5 = 0x00000000; 1500 cpu->isar.id_isar6 = 0x00000000; 1501 } 1502 1503 static void cortex_m33_initfn(Object *obj) 1504 { 1505 ARMCPU *cpu = ARM_CPU(obj); 1506 1507 set_feature(&cpu->env, ARM_FEATURE_V8); 1508 set_feature(&cpu->env, ARM_FEATURE_M); 1509 set_feature(&cpu->env, ARM_FEATURE_M_MAIN); 1510 set_feature(&cpu->env, ARM_FEATURE_M_SECURITY); 1511 set_feature(&cpu->env, ARM_FEATURE_THUMB_DSP); 1512 cpu->midr = 0x410fd213; /* r0p3 */ 1513 cpu->pmsav7_dregion = 16; 1514 cpu->sau_sregion = 8; 1515 cpu->id_pfr0 = 0x00000030; 1516 cpu->id_pfr1 = 0x00000210; 1517 cpu->id_dfr0 = 0x00200000; 1518 cpu->id_afr0 = 0x00000000; 1519 cpu->id_mmfr0 = 0x00101F40; 1520 cpu->id_mmfr1 = 0x00000000; 1521 cpu->id_mmfr2 = 0x01000000; 1522 cpu->id_mmfr3 = 0x00000000; 1523 cpu->isar.id_isar0 = 0x01101110; 1524 cpu->isar.id_isar1 = 0x02212000; 1525 cpu->isar.id_isar2 = 0x20232232; 1526 cpu->isar.id_isar3 = 0x01111131; 1527 cpu->isar.id_isar4 = 0x01310132; 1528 cpu->isar.id_isar5 = 0x00000000; 1529 cpu->isar.id_isar6 = 0x00000000; 1530 cpu->clidr = 0x00000000; 1531 cpu->ctr = 0x8000c000; 1532 } 1533 1534 static void arm_v7m_class_init(ObjectClass *oc, void *data) 1535 { 1536 ARMCPUClass *acc = ARM_CPU_CLASS(oc); 1537 CPUClass *cc = CPU_CLASS(oc); 1538 1539 acc->info = data; 1540 #ifndef CONFIG_USER_ONLY 1541 cc->do_interrupt = arm_v7m_cpu_do_interrupt; 1542 #endif 1543 1544 cc->cpu_exec_interrupt = arm_v7m_cpu_exec_interrupt; 1545 } 1546 1547 static const ARMCPRegInfo cortexr5_cp_reginfo[] = { 1548 /* Dummy the TCM region regs for the moment */ 1549 { .name = "ATCM", .cp = 15, .opc1 = 0, .crn = 9, .crm = 1, .opc2 = 0, 1550 .access = PL1_RW, .type = ARM_CP_CONST }, 1551 { .name = "BTCM", .cp = 15, .opc1 = 0, .crn = 9, .crm = 1, .opc2 = 1, 1552 .access = PL1_RW, .type = ARM_CP_CONST }, 1553 { .name = "DCACHE_INVAL", .cp = 15, .opc1 = 0, .crn = 15, .crm = 5, 1554 .opc2 = 0, .access = PL1_W, .type = ARM_CP_NOP }, 1555 REGINFO_SENTINEL 1556 }; 1557 1558 static void cortex_r5_initfn(Object *obj) 1559 { 1560 ARMCPU *cpu = ARM_CPU(obj); 1561 1562 set_feature(&cpu->env, ARM_FEATURE_V7); 1563 set_feature(&cpu->env, ARM_FEATURE_V7MP); 1564 set_feature(&cpu->env, ARM_FEATURE_PMSA); 1565 cpu->midr = 0x411fc153; /* r1p3 */ 1566 cpu->id_pfr0 = 0x0131; 1567 cpu->id_pfr1 = 0x001; 1568 cpu->id_dfr0 = 0x010400; 1569 cpu->id_afr0 = 0x0; 1570 cpu->id_mmfr0 = 0x0210030; 1571 cpu->id_mmfr1 = 0x00000000; 1572 cpu->id_mmfr2 = 0x01200000; 1573 cpu->id_mmfr3 = 0x0211; 1574 cpu->isar.id_isar0 = 0x02101111; 1575 cpu->isar.id_isar1 = 0x13112111; 1576 cpu->isar.id_isar2 = 0x21232141; 1577 cpu->isar.id_isar3 = 0x01112131; 1578 cpu->isar.id_isar4 = 0x0010142; 1579 cpu->isar.id_isar5 = 0x0; 1580 cpu->isar.id_isar6 = 0x0; 1581 cpu->mp_is_up = true; 1582 cpu->pmsav7_dregion = 16; 1583 define_arm_cp_regs(cpu, cortexr5_cp_reginfo); 1584 } 1585 1586 static void cortex_r5f_initfn(Object *obj) 1587 { 1588 ARMCPU *cpu = ARM_CPU(obj); 1589 1590 cortex_r5_initfn(obj); 1591 set_feature(&cpu->env, ARM_FEATURE_VFP3); 1592 } 1593 1594 static const ARMCPRegInfo cortexa8_cp_reginfo[] = { 1595 { .name = "L2LOCKDOWN", .cp = 15, .crn = 9, .crm = 0, .opc1 = 1, .opc2 = 0, 1596 .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0 }, 1597 { .name = "L2AUXCR", .cp = 15, .crn = 9, .crm = 0, .opc1 = 1, .opc2 = 2, 1598 .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0 }, 1599 REGINFO_SENTINEL 1600 }; 1601 1602 static void cortex_a8_initfn(Object *obj) 1603 { 1604 ARMCPU *cpu = ARM_CPU(obj); 1605 1606 cpu->dtb_compatible = "arm,cortex-a8"; 1607 set_feature(&cpu->env, ARM_FEATURE_V7); 1608 set_feature(&cpu->env, ARM_FEATURE_VFP3); 1609 set_feature(&cpu->env, ARM_FEATURE_NEON); 1610 set_feature(&cpu->env, ARM_FEATURE_THUMB2EE); 1611 set_feature(&cpu->env, ARM_FEATURE_DUMMY_C15_REGS); 1612 set_feature(&cpu->env, ARM_FEATURE_EL3); 1613 cpu->midr = 0x410fc080; 1614 cpu->reset_fpsid = 0x410330c0; 1615 cpu->isar.mvfr0 = 0x11110222; 1616 cpu->isar.mvfr1 = 0x00011111; 1617 cpu->ctr = 0x82048004; 1618 cpu->reset_sctlr = 0x00c50078; 1619 cpu->id_pfr0 = 0x1031; 1620 cpu->id_pfr1 = 0x11; 1621 cpu->id_dfr0 = 0x400; 1622 cpu->id_afr0 = 0; 1623 cpu->id_mmfr0 = 0x31100003; 1624 cpu->id_mmfr1 = 0x20000000; 1625 cpu->id_mmfr2 = 0x01202000; 1626 cpu->id_mmfr3 = 0x11; 1627 cpu->isar.id_isar0 = 0x00101111; 1628 cpu->isar.id_isar1 = 0x12112111; 1629 cpu->isar.id_isar2 = 0x21232031; 1630 cpu->isar.id_isar3 = 0x11112131; 1631 cpu->isar.id_isar4 = 0x00111142; 1632 cpu->dbgdidr = 0x15141000; 1633 cpu->clidr = (1 << 27) | (2 << 24) | 3; 1634 cpu->ccsidr[0] = 0xe007e01a; /* 16k L1 dcache. */ 1635 cpu->ccsidr[1] = 0x2007e01a; /* 16k L1 icache. */ 1636 cpu->ccsidr[2] = 0xf0000000; /* No L2 icache. */ 1637 cpu->reset_auxcr = 2; 1638 define_arm_cp_regs(cpu, cortexa8_cp_reginfo); 1639 } 1640 1641 static const ARMCPRegInfo cortexa9_cp_reginfo[] = { 1642 /* power_control should be set to maximum latency. Again, 1643 * default to 0 and set by private hook 1644 */ 1645 { .name = "A9_PWRCTL", .cp = 15, .crn = 15, .crm = 0, .opc1 = 0, .opc2 = 0, 1646 .access = PL1_RW, .resetvalue = 0, 1647 .fieldoffset = offsetof(CPUARMState, cp15.c15_power_control) }, 1648 { .name = "A9_DIAG", .cp = 15, .crn = 15, .crm = 0, .opc1 = 0, .opc2 = 1, 1649 .access = PL1_RW, .resetvalue = 0, 1650 .fieldoffset = offsetof(CPUARMState, cp15.c15_diagnostic) }, 1651 { .name = "A9_PWRDIAG", .cp = 15, .crn = 15, .crm = 0, .opc1 = 0, .opc2 = 2, 1652 .access = PL1_RW, .resetvalue = 0, 1653 .fieldoffset = offsetof(CPUARMState, cp15.c15_power_diagnostic) }, 1654 { .name = "NEONBUSY", .cp = 15, .crn = 15, .crm = 1, .opc1 = 0, .opc2 = 0, 1655 .access = PL1_RW, .resetvalue = 0, .type = ARM_CP_CONST }, 1656 /* TLB lockdown control */ 1657 { .name = "TLB_LOCKR", .cp = 15, .crn = 15, .crm = 4, .opc1 = 5, .opc2 = 2, 1658 .access = PL1_W, .resetvalue = 0, .type = ARM_CP_NOP }, 1659 { .name = "TLB_LOCKW", .cp = 15, .crn = 15, .crm = 4, .opc1 = 5, .opc2 = 4, 1660 .access = PL1_W, .resetvalue = 0, .type = ARM_CP_NOP }, 1661 { .name = "TLB_VA", .cp = 15, .crn = 15, .crm = 5, .opc1 = 5, .opc2 = 2, 1662 .access = PL1_RW, .resetvalue = 0, .type = ARM_CP_CONST }, 1663 { .name = "TLB_PA", .cp = 15, .crn = 15, .crm = 6, .opc1 = 5, .opc2 = 2, 1664 .access = PL1_RW, .resetvalue = 0, .type = ARM_CP_CONST }, 1665 { .name = "TLB_ATTR", .cp = 15, .crn = 15, .crm = 7, .opc1 = 5, .opc2 = 2, 1666 .access = PL1_RW, .resetvalue = 0, .type = ARM_CP_CONST }, 1667 REGINFO_SENTINEL 1668 }; 1669 1670 static void cortex_a9_initfn(Object *obj) 1671 { 1672 ARMCPU *cpu = ARM_CPU(obj); 1673 1674 cpu->dtb_compatible = "arm,cortex-a9"; 1675 set_feature(&cpu->env, ARM_FEATURE_V7); 1676 set_feature(&cpu->env, ARM_FEATURE_VFP3); 1677 set_feature(&cpu->env, ARM_FEATURE_NEON); 1678 set_feature(&cpu->env, ARM_FEATURE_THUMB2EE); 1679 set_feature(&cpu->env, ARM_FEATURE_EL3); 1680 /* Note that A9 supports the MP extensions even for 1681 * A9UP and single-core A9MP (which are both different 1682 * and valid configurations; we don't model A9UP). 1683 */ 1684 set_feature(&cpu->env, ARM_FEATURE_V7MP); 1685 set_feature(&cpu->env, ARM_FEATURE_CBAR); 1686 cpu->midr = 0x410fc090; 1687 cpu->reset_fpsid = 0x41033090; 1688 cpu->isar.mvfr0 = 0x11110222; 1689 cpu->isar.mvfr1 = 0x01111111; 1690 cpu->ctr = 0x80038003; 1691 cpu->reset_sctlr = 0x00c50078; 1692 cpu->id_pfr0 = 0x1031; 1693 cpu->id_pfr1 = 0x11; 1694 cpu->id_dfr0 = 0x000; 1695 cpu->id_afr0 = 0; 1696 cpu->id_mmfr0 = 0x00100103; 1697 cpu->id_mmfr1 = 0x20000000; 1698 cpu->id_mmfr2 = 0x01230000; 1699 cpu->id_mmfr3 = 0x00002111; 1700 cpu->isar.id_isar0 = 0x00101111; 1701 cpu->isar.id_isar1 = 0x13112111; 1702 cpu->isar.id_isar2 = 0x21232041; 1703 cpu->isar.id_isar3 = 0x11112131; 1704 cpu->isar.id_isar4 = 0x00111142; 1705 cpu->dbgdidr = 0x35141000; 1706 cpu->clidr = (1 << 27) | (1 << 24) | 3; 1707 cpu->ccsidr[0] = 0xe00fe019; /* 16k L1 dcache. */ 1708 cpu->ccsidr[1] = 0x200fe019; /* 16k L1 icache. */ 1709 define_arm_cp_regs(cpu, cortexa9_cp_reginfo); 1710 } 1711 1712 #ifndef CONFIG_USER_ONLY 1713 static uint64_t a15_l2ctlr_read(CPUARMState *env, const ARMCPRegInfo *ri) 1714 { 1715 /* Linux wants the number of processors from here. 1716 * Might as well set the interrupt-controller bit too. 1717 */ 1718 return ((smp_cpus - 1) << 24) | (1 << 23); 1719 } 1720 #endif 1721 1722 static const ARMCPRegInfo cortexa15_cp_reginfo[] = { 1723 #ifndef CONFIG_USER_ONLY 1724 { .name = "L2CTLR", .cp = 15, .crn = 9, .crm = 0, .opc1 = 1, .opc2 = 2, 1725 .access = PL1_RW, .resetvalue = 0, .readfn = a15_l2ctlr_read, 1726 .writefn = arm_cp_write_ignore, }, 1727 #endif 1728 { .name = "L2ECTLR", .cp = 15, .crn = 9, .crm = 0, .opc1 = 1, .opc2 = 3, 1729 .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0 }, 1730 REGINFO_SENTINEL 1731 }; 1732 1733 static void cortex_a7_initfn(Object *obj) 1734 { 1735 ARMCPU *cpu = ARM_CPU(obj); 1736 1737 cpu->dtb_compatible = "arm,cortex-a7"; 1738 set_feature(&cpu->env, ARM_FEATURE_V7VE); 1739 set_feature(&cpu->env, ARM_FEATURE_VFP4); 1740 set_feature(&cpu->env, ARM_FEATURE_NEON); 1741 set_feature(&cpu->env, ARM_FEATURE_THUMB2EE); 1742 set_feature(&cpu->env, ARM_FEATURE_GENERIC_TIMER); 1743 set_feature(&cpu->env, ARM_FEATURE_DUMMY_C15_REGS); 1744 set_feature(&cpu->env, ARM_FEATURE_CBAR_RO); 1745 set_feature(&cpu->env, ARM_FEATURE_EL2); 1746 set_feature(&cpu->env, ARM_FEATURE_EL3); 1747 set_feature(&cpu->env, ARM_FEATURE_PMU); 1748 cpu->kvm_target = QEMU_KVM_ARM_TARGET_CORTEX_A7; 1749 cpu->midr = 0x410fc075; 1750 cpu->reset_fpsid = 0x41023075; 1751 cpu->isar.mvfr0 = 0x10110222; 1752 cpu->isar.mvfr1 = 0x11111111; 1753 cpu->ctr = 0x84448003; 1754 cpu->reset_sctlr = 0x00c50078; 1755 cpu->id_pfr0 = 0x00001131; 1756 cpu->id_pfr1 = 0x00011011; 1757 cpu->id_dfr0 = 0x02010555; 1758 cpu->id_afr0 = 0x00000000; 1759 cpu->id_mmfr0 = 0x10101105; 1760 cpu->id_mmfr1 = 0x40000000; 1761 cpu->id_mmfr2 = 0x01240000; 1762 cpu->id_mmfr3 = 0x02102211; 1763 /* a7_mpcore_r0p5_trm, page 4-4 gives 0x01101110; but 1764 * table 4-41 gives 0x02101110, which includes the arm div insns. 1765 */ 1766 cpu->isar.id_isar0 = 0x02101110; 1767 cpu->isar.id_isar1 = 0x13112111; 1768 cpu->isar.id_isar2 = 0x21232041; 1769 cpu->isar.id_isar3 = 0x11112131; 1770 cpu->isar.id_isar4 = 0x10011142; 1771 cpu->dbgdidr = 0x3515f005; 1772 cpu->clidr = 0x0a200023; 1773 cpu->ccsidr[0] = 0x701fe00a; /* 32K L1 dcache */ 1774 cpu->ccsidr[1] = 0x201fe00a; /* 32K L1 icache */ 1775 cpu->ccsidr[2] = 0x711fe07a; /* 4096K L2 unified cache */ 1776 define_arm_cp_regs(cpu, cortexa15_cp_reginfo); /* Same as A15 */ 1777 } 1778 1779 static void cortex_a15_initfn(Object *obj) 1780 { 1781 ARMCPU *cpu = ARM_CPU(obj); 1782 1783 cpu->dtb_compatible = "arm,cortex-a15"; 1784 set_feature(&cpu->env, ARM_FEATURE_V7VE); 1785 set_feature(&cpu->env, ARM_FEATURE_VFP4); 1786 set_feature(&cpu->env, ARM_FEATURE_NEON); 1787 set_feature(&cpu->env, ARM_FEATURE_THUMB2EE); 1788 set_feature(&cpu->env, ARM_FEATURE_GENERIC_TIMER); 1789 set_feature(&cpu->env, ARM_FEATURE_DUMMY_C15_REGS); 1790 set_feature(&cpu->env, ARM_FEATURE_CBAR_RO); 1791 set_feature(&cpu->env, ARM_FEATURE_EL2); 1792 set_feature(&cpu->env, ARM_FEATURE_EL3); 1793 set_feature(&cpu->env, ARM_FEATURE_PMU); 1794 cpu->kvm_target = QEMU_KVM_ARM_TARGET_CORTEX_A15; 1795 cpu->midr = 0x412fc0f1; 1796 cpu->reset_fpsid = 0x410430f0; 1797 cpu->isar.mvfr0 = 0x10110222; 1798 cpu->isar.mvfr1 = 0x11111111; 1799 cpu->ctr = 0x8444c004; 1800 cpu->reset_sctlr = 0x00c50078; 1801 cpu->id_pfr0 = 0x00001131; 1802 cpu->id_pfr1 = 0x00011011; 1803 cpu->id_dfr0 = 0x02010555; 1804 cpu->id_afr0 = 0x00000000; 1805 cpu->id_mmfr0 = 0x10201105; 1806 cpu->id_mmfr1 = 0x20000000; 1807 cpu->id_mmfr2 = 0x01240000; 1808 cpu->id_mmfr3 = 0x02102211; 1809 cpu->isar.id_isar0 = 0x02101110; 1810 cpu->isar.id_isar1 = 0x13112111; 1811 cpu->isar.id_isar2 = 0x21232041; 1812 cpu->isar.id_isar3 = 0x11112131; 1813 cpu->isar.id_isar4 = 0x10011142; 1814 cpu->dbgdidr = 0x3515f021; 1815 cpu->clidr = 0x0a200023; 1816 cpu->ccsidr[0] = 0x701fe00a; /* 32K L1 dcache */ 1817 cpu->ccsidr[1] = 0x201fe00a; /* 32K L1 icache */ 1818 cpu->ccsidr[2] = 0x711fe07a; /* 4096K L2 unified cache */ 1819 define_arm_cp_regs(cpu, cortexa15_cp_reginfo); 1820 } 1821 1822 static void ti925t_initfn(Object *obj) 1823 { 1824 ARMCPU *cpu = ARM_CPU(obj); 1825 set_feature(&cpu->env, ARM_FEATURE_V4T); 1826 set_feature(&cpu->env, ARM_FEATURE_OMAPCP); 1827 cpu->midr = ARM_CPUID_TI925T; 1828 cpu->ctr = 0x5109149; 1829 cpu->reset_sctlr = 0x00000070; 1830 } 1831 1832 static void sa1100_initfn(Object *obj) 1833 { 1834 ARMCPU *cpu = ARM_CPU(obj); 1835 1836 cpu->dtb_compatible = "intel,sa1100"; 1837 set_feature(&cpu->env, ARM_FEATURE_STRONGARM); 1838 set_feature(&cpu->env, ARM_FEATURE_DUMMY_C15_REGS); 1839 cpu->midr = 0x4401A11B; 1840 cpu->reset_sctlr = 0x00000070; 1841 } 1842 1843 static void sa1110_initfn(Object *obj) 1844 { 1845 ARMCPU *cpu = ARM_CPU(obj); 1846 set_feature(&cpu->env, ARM_FEATURE_STRONGARM); 1847 set_feature(&cpu->env, ARM_FEATURE_DUMMY_C15_REGS); 1848 cpu->midr = 0x6901B119; 1849 cpu->reset_sctlr = 0x00000070; 1850 } 1851 1852 static void pxa250_initfn(Object *obj) 1853 { 1854 ARMCPU *cpu = ARM_CPU(obj); 1855 1856 cpu->dtb_compatible = "marvell,xscale"; 1857 set_feature(&cpu->env, ARM_FEATURE_V5); 1858 set_feature(&cpu->env, ARM_FEATURE_XSCALE); 1859 cpu->midr = 0x69052100; 1860 cpu->ctr = 0xd172172; 1861 cpu->reset_sctlr = 0x00000078; 1862 } 1863 1864 static void pxa255_initfn(Object *obj) 1865 { 1866 ARMCPU *cpu = ARM_CPU(obj); 1867 1868 cpu->dtb_compatible = "marvell,xscale"; 1869 set_feature(&cpu->env, ARM_FEATURE_V5); 1870 set_feature(&cpu->env, ARM_FEATURE_XSCALE); 1871 cpu->midr = 0x69052d00; 1872 cpu->ctr = 0xd172172; 1873 cpu->reset_sctlr = 0x00000078; 1874 } 1875 1876 static void pxa260_initfn(Object *obj) 1877 { 1878 ARMCPU *cpu = ARM_CPU(obj); 1879 1880 cpu->dtb_compatible = "marvell,xscale"; 1881 set_feature(&cpu->env, ARM_FEATURE_V5); 1882 set_feature(&cpu->env, ARM_FEATURE_XSCALE); 1883 cpu->midr = 0x69052903; 1884 cpu->ctr = 0xd172172; 1885 cpu->reset_sctlr = 0x00000078; 1886 } 1887 1888 static void pxa261_initfn(Object *obj) 1889 { 1890 ARMCPU *cpu = ARM_CPU(obj); 1891 1892 cpu->dtb_compatible = "marvell,xscale"; 1893 set_feature(&cpu->env, ARM_FEATURE_V5); 1894 set_feature(&cpu->env, ARM_FEATURE_XSCALE); 1895 cpu->midr = 0x69052d05; 1896 cpu->ctr = 0xd172172; 1897 cpu->reset_sctlr = 0x00000078; 1898 } 1899 1900 static void pxa262_initfn(Object *obj) 1901 { 1902 ARMCPU *cpu = ARM_CPU(obj); 1903 1904 cpu->dtb_compatible = "marvell,xscale"; 1905 set_feature(&cpu->env, ARM_FEATURE_V5); 1906 set_feature(&cpu->env, ARM_FEATURE_XSCALE); 1907 cpu->midr = 0x69052d06; 1908 cpu->ctr = 0xd172172; 1909 cpu->reset_sctlr = 0x00000078; 1910 } 1911 1912 static void pxa270a0_initfn(Object *obj) 1913 { 1914 ARMCPU *cpu = ARM_CPU(obj); 1915 1916 cpu->dtb_compatible = "marvell,xscale"; 1917 set_feature(&cpu->env, ARM_FEATURE_V5); 1918 set_feature(&cpu->env, ARM_FEATURE_XSCALE); 1919 set_feature(&cpu->env, ARM_FEATURE_IWMMXT); 1920 cpu->midr = 0x69054110; 1921 cpu->ctr = 0xd172172; 1922 cpu->reset_sctlr = 0x00000078; 1923 } 1924 1925 static void pxa270a1_initfn(Object *obj) 1926 { 1927 ARMCPU *cpu = ARM_CPU(obj); 1928 1929 cpu->dtb_compatible = "marvell,xscale"; 1930 set_feature(&cpu->env, ARM_FEATURE_V5); 1931 set_feature(&cpu->env, ARM_FEATURE_XSCALE); 1932 set_feature(&cpu->env, ARM_FEATURE_IWMMXT); 1933 cpu->midr = 0x69054111; 1934 cpu->ctr = 0xd172172; 1935 cpu->reset_sctlr = 0x00000078; 1936 } 1937 1938 static void pxa270b0_initfn(Object *obj) 1939 { 1940 ARMCPU *cpu = ARM_CPU(obj); 1941 1942 cpu->dtb_compatible = "marvell,xscale"; 1943 set_feature(&cpu->env, ARM_FEATURE_V5); 1944 set_feature(&cpu->env, ARM_FEATURE_XSCALE); 1945 set_feature(&cpu->env, ARM_FEATURE_IWMMXT); 1946 cpu->midr = 0x69054112; 1947 cpu->ctr = 0xd172172; 1948 cpu->reset_sctlr = 0x00000078; 1949 } 1950 1951 static void pxa270b1_initfn(Object *obj) 1952 { 1953 ARMCPU *cpu = ARM_CPU(obj); 1954 1955 cpu->dtb_compatible = "marvell,xscale"; 1956 set_feature(&cpu->env, ARM_FEATURE_V5); 1957 set_feature(&cpu->env, ARM_FEATURE_XSCALE); 1958 set_feature(&cpu->env, ARM_FEATURE_IWMMXT); 1959 cpu->midr = 0x69054113; 1960 cpu->ctr = 0xd172172; 1961 cpu->reset_sctlr = 0x00000078; 1962 } 1963 1964 static void pxa270c0_initfn(Object *obj) 1965 { 1966 ARMCPU *cpu = ARM_CPU(obj); 1967 1968 cpu->dtb_compatible = "marvell,xscale"; 1969 set_feature(&cpu->env, ARM_FEATURE_V5); 1970 set_feature(&cpu->env, ARM_FEATURE_XSCALE); 1971 set_feature(&cpu->env, ARM_FEATURE_IWMMXT); 1972 cpu->midr = 0x69054114; 1973 cpu->ctr = 0xd172172; 1974 cpu->reset_sctlr = 0x00000078; 1975 } 1976 1977 static void pxa270c5_initfn(Object *obj) 1978 { 1979 ARMCPU *cpu = ARM_CPU(obj); 1980 1981 cpu->dtb_compatible = "marvell,xscale"; 1982 set_feature(&cpu->env, ARM_FEATURE_V5); 1983 set_feature(&cpu->env, ARM_FEATURE_XSCALE); 1984 set_feature(&cpu->env, ARM_FEATURE_IWMMXT); 1985 cpu->midr = 0x69054117; 1986 cpu->ctr = 0xd172172; 1987 cpu->reset_sctlr = 0x00000078; 1988 } 1989 1990 #ifndef TARGET_AARCH64 1991 /* -cpu max: if KVM is enabled, like -cpu host (best possible with this host); 1992 * otherwise, a CPU with as many features enabled as our emulation supports. 1993 * The version of '-cpu max' for qemu-system-aarch64 is defined in cpu64.c; 1994 * this only needs to handle 32 bits. 1995 */ 1996 static void arm_max_initfn(Object *obj) 1997 { 1998 ARMCPU *cpu = ARM_CPU(obj); 1999 2000 if (kvm_enabled()) { 2001 kvm_arm_set_cpu_features_from_host(cpu); 2002 } else { 2003 cortex_a15_initfn(obj); 2004 #ifdef CONFIG_USER_ONLY 2005 /* We don't set these in system emulation mode for the moment, 2006 * since we don't correctly set (all of) the ID registers to 2007 * advertise them. 2008 */ 2009 set_feature(&cpu->env, ARM_FEATURE_V8); 2010 { 2011 uint32_t t; 2012 2013 t = cpu->isar.id_isar5; 2014 t = FIELD_DP32(t, ID_ISAR5, AES, 2); 2015 t = FIELD_DP32(t, ID_ISAR5, SHA1, 1); 2016 t = FIELD_DP32(t, ID_ISAR5, SHA2, 1); 2017 t = FIELD_DP32(t, ID_ISAR5, CRC32, 1); 2018 t = FIELD_DP32(t, ID_ISAR5, RDM, 1); 2019 t = FIELD_DP32(t, ID_ISAR5, VCMA, 1); 2020 cpu->isar.id_isar5 = t; 2021 2022 t = cpu->isar.id_isar6; 2023 t = FIELD_DP32(t, ID_ISAR6, JSCVT, 1); 2024 t = FIELD_DP32(t, ID_ISAR6, DP, 1); 2025 t = FIELD_DP32(t, ID_ISAR6, FHM, 1); 2026 t = FIELD_DP32(t, ID_ISAR6, SB, 1); 2027 t = FIELD_DP32(t, ID_ISAR6, SPECRES, 1); 2028 cpu->isar.id_isar6 = t; 2029 2030 t = cpu->isar.mvfr2; 2031 t = FIELD_DP32(t, MVFR2, SIMDMISC, 3); /* SIMD MaxNum */ 2032 t = FIELD_DP32(t, MVFR2, FPMISC, 4); /* FP MaxNum */ 2033 cpu->isar.mvfr2 = t; 2034 2035 t = cpu->id_mmfr4; 2036 t = FIELD_DP32(t, ID_MMFR4, HPDS, 1); /* AA32HPD */ 2037 cpu->id_mmfr4 = t; 2038 } 2039 #endif 2040 } 2041 } 2042 #endif 2043 2044 #endif /* !defined(CONFIG_USER_ONLY) || !defined(TARGET_AARCH64) */ 2045 2046 struct ARMCPUInfo { 2047 const char *name; 2048 void (*initfn)(Object *obj); 2049 void (*class_init)(ObjectClass *oc, void *data); 2050 }; 2051 2052 static const ARMCPUInfo arm_cpus[] = { 2053 #if !defined(CONFIG_USER_ONLY) || !defined(TARGET_AARCH64) 2054 { .name = "arm926", .initfn = arm926_initfn }, 2055 { .name = "arm946", .initfn = arm946_initfn }, 2056 { .name = "arm1026", .initfn = arm1026_initfn }, 2057 /* What QEMU calls "arm1136-r2" is actually the 1136 r0p2, i.e. an 2058 * older core than plain "arm1136". In particular this does not 2059 * have the v6K features. 2060 */ 2061 { .name = "arm1136-r2", .initfn = arm1136_r2_initfn }, 2062 { .name = "arm1136", .initfn = arm1136_initfn }, 2063 { .name = "arm1176", .initfn = arm1176_initfn }, 2064 { .name = "arm11mpcore", .initfn = arm11mpcore_initfn }, 2065 { .name = "cortex-m0", .initfn = cortex_m0_initfn, 2066 .class_init = arm_v7m_class_init }, 2067 { .name = "cortex-m3", .initfn = cortex_m3_initfn, 2068 .class_init = arm_v7m_class_init }, 2069 { .name = "cortex-m4", .initfn = cortex_m4_initfn, 2070 .class_init = arm_v7m_class_init }, 2071 { .name = "cortex-m33", .initfn = cortex_m33_initfn, 2072 .class_init = arm_v7m_class_init }, 2073 { .name = "cortex-r5", .initfn = cortex_r5_initfn }, 2074 { .name = "cortex-r5f", .initfn = cortex_r5f_initfn }, 2075 { .name = "cortex-a7", .initfn = cortex_a7_initfn }, 2076 { .name = "cortex-a8", .initfn = cortex_a8_initfn }, 2077 { .name = "cortex-a9", .initfn = cortex_a9_initfn }, 2078 { .name = "cortex-a15", .initfn = cortex_a15_initfn }, 2079 { .name = "ti925t", .initfn = ti925t_initfn }, 2080 { .name = "sa1100", .initfn = sa1100_initfn }, 2081 { .name = "sa1110", .initfn = sa1110_initfn }, 2082 { .name = "pxa250", .initfn = pxa250_initfn }, 2083 { .name = "pxa255", .initfn = pxa255_initfn }, 2084 { .name = "pxa260", .initfn = pxa260_initfn }, 2085 { .name = "pxa261", .initfn = pxa261_initfn }, 2086 { .name = "pxa262", .initfn = pxa262_initfn }, 2087 /* "pxa270" is an alias for "pxa270-a0" */ 2088 { .name = "pxa270", .initfn = pxa270a0_initfn }, 2089 { .name = "pxa270-a0", .initfn = pxa270a0_initfn }, 2090 { .name = "pxa270-a1", .initfn = pxa270a1_initfn }, 2091 { .name = "pxa270-b0", .initfn = pxa270b0_initfn }, 2092 { .name = "pxa270-b1", .initfn = pxa270b1_initfn }, 2093 { .name = "pxa270-c0", .initfn = pxa270c0_initfn }, 2094 { .name = "pxa270-c5", .initfn = pxa270c5_initfn }, 2095 #ifndef TARGET_AARCH64 2096 { .name = "max", .initfn = arm_max_initfn }, 2097 #endif 2098 #ifdef CONFIG_USER_ONLY 2099 { .name = "any", .initfn = arm_max_initfn }, 2100 #endif 2101 #endif 2102 { .name = NULL } 2103 }; 2104 2105 static Property arm_cpu_properties[] = { 2106 DEFINE_PROP_BOOL("start-powered-off", ARMCPU, start_powered_off, false), 2107 DEFINE_PROP_UINT32("psci-conduit", ARMCPU, psci_conduit, 0), 2108 DEFINE_PROP_UINT32("midr", ARMCPU, midr, 0), 2109 DEFINE_PROP_UINT64("mp-affinity", ARMCPU, 2110 mp_affinity, ARM64_AFFINITY_INVALID), 2111 DEFINE_PROP_INT32("node-id", ARMCPU, node_id, CPU_UNSET_NUMA_NODE_ID), 2112 DEFINE_PROP_INT32("core-count", ARMCPU, core_count, -1), 2113 DEFINE_PROP_END_OF_LIST() 2114 }; 2115 2116 #ifdef CONFIG_USER_ONLY 2117 static int arm_cpu_handle_mmu_fault(CPUState *cs, vaddr address, int size, 2118 int rw, int mmu_idx) 2119 { 2120 ARMCPU *cpu = ARM_CPU(cs); 2121 CPUARMState *env = &cpu->env; 2122 2123 env->exception.vaddress = address; 2124 if (rw == 2) { 2125 cs->exception_index = EXCP_PREFETCH_ABORT; 2126 } else { 2127 cs->exception_index = EXCP_DATA_ABORT; 2128 } 2129 return 1; 2130 } 2131 #endif 2132 2133 static gchar *arm_gdb_arch_name(CPUState *cs) 2134 { 2135 ARMCPU *cpu = ARM_CPU(cs); 2136 CPUARMState *env = &cpu->env; 2137 2138 if (arm_feature(env, ARM_FEATURE_IWMMXT)) { 2139 return g_strdup("iwmmxt"); 2140 } 2141 return g_strdup("arm"); 2142 } 2143 2144 static void arm_cpu_class_init(ObjectClass *oc, void *data) 2145 { 2146 ARMCPUClass *acc = ARM_CPU_CLASS(oc); 2147 CPUClass *cc = CPU_CLASS(acc); 2148 DeviceClass *dc = DEVICE_CLASS(oc); 2149 2150 device_class_set_parent_realize(dc, arm_cpu_realizefn, 2151 &acc->parent_realize); 2152 dc->props = arm_cpu_properties; 2153 2154 acc->parent_reset = cc->reset; 2155 cc->reset = arm_cpu_reset; 2156 2157 cc->class_by_name = arm_cpu_class_by_name; 2158 cc->has_work = arm_cpu_has_work; 2159 cc->cpu_exec_interrupt = arm_cpu_exec_interrupt; 2160 cc->dump_state = arm_cpu_dump_state; 2161 cc->set_pc = arm_cpu_set_pc; 2162 cc->synchronize_from_tb = arm_cpu_synchronize_from_tb; 2163 cc->gdb_read_register = arm_cpu_gdb_read_register; 2164 cc->gdb_write_register = arm_cpu_gdb_write_register; 2165 #ifdef CONFIG_USER_ONLY 2166 cc->handle_mmu_fault = arm_cpu_handle_mmu_fault; 2167 #else 2168 cc->do_interrupt = arm_cpu_do_interrupt; 2169 cc->do_unaligned_access = arm_cpu_do_unaligned_access; 2170 cc->do_transaction_failed = arm_cpu_do_transaction_failed; 2171 cc->get_phys_page_attrs_debug = arm_cpu_get_phys_page_attrs_debug; 2172 cc->asidx_from_attrs = arm_asidx_from_attrs; 2173 cc->vmsd = &vmstate_arm_cpu; 2174 cc->virtio_is_big_endian = arm_cpu_virtio_is_big_endian; 2175 cc->write_elf64_note = arm_cpu_write_elf64_note; 2176 cc->write_elf32_note = arm_cpu_write_elf32_note; 2177 #endif 2178 cc->gdb_num_core_regs = 26; 2179 cc->gdb_core_xml_file = "arm-core.xml"; 2180 cc->gdb_arch_name = arm_gdb_arch_name; 2181 cc->gdb_get_dynamic_xml = arm_gdb_get_dynamic_xml; 2182 cc->gdb_stop_before_watchpoint = true; 2183 cc->debug_excp_handler = arm_debug_excp_handler; 2184 cc->debug_check_watchpoint = arm_debug_check_watchpoint; 2185 #if !defined(CONFIG_USER_ONLY) 2186 cc->adjust_watchpoint_address = arm_adjust_watchpoint_address; 2187 #endif 2188 2189 cc->disas_set_info = arm_disas_set_info; 2190 #ifdef CONFIG_TCG 2191 cc->tcg_initialize = arm_translate_init; 2192 #endif 2193 } 2194 2195 #ifdef CONFIG_KVM 2196 static void arm_host_initfn(Object *obj) 2197 { 2198 ARMCPU *cpu = ARM_CPU(obj); 2199 2200 kvm_arm_set_cpu_features_from_host(cpu); 2201 arm_cpu_post_init(obj); 2202 } 2203 2204 static const TypeInfo host_arm_cpu_type_info = { 2205 .name = TYPE_ARM_HOST_CPU, 2206 #ifdef TARGET_AARCH64 2207 .parent = TYPE_AARCH64_CPU, 2208 #else 2209 .parent = TYPE_ARM_CPU, 2210 #endif 2211 .instance_init = arm_host_initfn, 2212 }; 2213 2214 #endif 2215 2216 static void arm_cpu_instance_init(Object *obj) 2217 { 2218 ARMCPUClass *acc = ARM_CPU_GET_CLASS(obj); 2219 2220 acc->info->initfn(obj); 2221 arm_cpu_post_init(obj); 2222 } 2223 2224 static void cpu_register_class_init(ObjectClass *oc, void *data) 2225 { 2226 ARMCPUClass *acc = ARM_CPU_CLASS(oc); 2227 2228 acc->info = data; 2229 } 2230 2231 static void cpu_register(const ARMCPUInfo *info) 2232 { 2233 TypeInfo type_info = { 2234 .parent = TYPE_ARM_CPU, 2235 .instance_size = sizeof(ARMCPU), 2236 .instance_init = arm_cpu_instance_init, 2237 .class_size = sizeof(ARMCPUClass), 2238 .class_init = info->class_init ?: cpu_register_class_init, 2239 .class_data = (void *)info, 2240 }; 2241 2242 type_info.name = g_strdup_printf("%s-" TYPE_ARM_CPU, info->name); 2243 type_register(&type_info); 2244 g_free((void *)type_info.name); 2245 } 2246 2247 static const TypeInfo arm_cpu_type_info = { 2248 .name = TYPE_ARM_CPU, 2249 .parent = TYPE_CPU, 2250 .instance_size = sizeof(ARMCPU), 2251 .instance_init = arm_cpu_initfn, 2252 .instance_finalize = arm_cpu_finalizefn, 2253 .abstract = true, 2254 .class_size = sizeof(ARMCPUClass), 2255 .class_init = arm_cpu_class_init, 2256 }; 2257 2258 static const TypeInfo idau_interface_type_info = { 2259 .name = TYPE_IDAU_INTERFACE, 2260 .parent = TYPE_INTERFACE, 2261 .class_size = sizeof(IDAUInterfaceClass), 2262 }; 2263 2264 static void arm_cpu_register_types(void) 2265 { 2266 const ARMCPUInfo *info = arm_cpus; 2267 2268 type_register_static(&arm_cpu_type_info); 2269 type_register_static(&idau_interface_type_info); 2270 2271 while (info->name) { 2272 cpu_register(info); 2273 info++; 2274 } 2275 2276 #ifdef CONFIG_KVM 2277 type_register_static(&host_arm_cpu_type_info); 2278 #endif 2279 } 2280 2281 type_init(arm_cpu_register_types) 2282