1 /* 2 * QEMU ARM CPU 3 * 4 * Copyright (c) 2012 SUSE LINUX Products GmbH 5 * 6 * This program is free software; you can redistribute it and/or 7 * modify it under the terms of the GNU General Public License 8 * as published by the Free Software Foundation; either version 2 9 * of the License, or (at your option) any later version. 10 * 11 * This program is distributed in the hope that it will be useful, 12 * but WITHOUT ANY WARRANTY; without even the implied warranty of 13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 14 * GNU General Public License for more details. 15 * 16 * You should have received a copy of the GNU General Public License 17 * along with this program; if not, see 18 * <http://www.gnu.org/licenses/gpl-2.0.html> 19 */ 20 21 #include "qemu/osdep.h" 22 #include "qemu/qemu-print.h" 23 #include "qemu/timer.h" 24 #include "qemu/log.h" 25 #include "exec/page-vary.h" 26 #include "target/arm/idau.h" 27 #include "qemu/module.h" 28 #include "qapi/error.h" 29 #include "cpu.h" 30 #ifdef CONFIG_TCG 31 #include "hw/core/tcg-cpu-ops.h" 32 #endif /* CONFIG_TCG */ 33 #include "internals.h" 34 #include "exec/exec-all.h" 35 #include "hw/qdev-properties.h" 36 #if !defined(CONFIG_USER_ONLY) 37 #include "hw/loader.h" 38 #include "hw/boards.h" 39 #include "hw/intc/armv7m_nvic.h" 40 #endif 41 #include "sysemu/tcg.h" 42 #include "sysemu/qtest.h" 43 #include "sysemu/hw_accel.h" 44 #include "kvm_arm.h" 45 #include "disas/capstone.h" 46 #include "fpu/softfloat.h" 47 #include "cpregs.h" 48 49 static void arm_cpu_set_pc(CPUState *cs, vaddr value) 50 { 51 ARMCPU *cpu = ARM_CPU(cs); 52 CPUARMState *env = &cpu->env; 53 54 if (is_a64(env)) { 55 env->pc = value; 56 env->thumb = false; 57 } else { 58 env->regs[15] = value & ~1; 59 env->thumb = value & 1; 60 } 61 } 62 63 static vaddr arm_cpu_get_pc(CPUState *cs) 64 { 65 ARMCPU *cpu = ARM_CPU(cs); 66 CPUARMState *env = &cpu->env; 67 68 if (is_a64(env)) { 69 return env->pc; 70 } else { 71 return env->regs[15]; 72 } 73 } 74 75 #ifdef CONFIG_TCG 76 void arm_cpu_synchronize_from_tb(CPUState *cs, 77 const TranslationBlock *tb) 78 { 79 /* The program counter is always up to date with TARGET_TB_PCREL. */ 80 if (!TARGET_TB_PCREL) { 81 CPUARMState *env = cs->env_ptr; 82 /* 83 * It's OK to look at env for the current mode here, because it's 84 * never possible for an AArch64 TB to chain to an AArch32 TB. 85 */ 86 if (is_a64(env)) { 87 env->pc = tb_pc(tb); 88 } else { 89 env->regs[15] = tb_pc(tb); 90 } 91 } 92 } 93 94 void arm_restore_state_to_opc(CPUState *cs, 95 const TranslationBlock *tb, 96 const uint64_t *data) 97 { 98 CPUARMState *env = cs->env_ptr; 99 100 if (is_a64(env)) { 101 if (TARGET_TB_PCREL) { 102 env->pc = (env->pc & TARGET_PAGE_MASK) | data[0]; 103 } else { 104 env->pc = data[0]; 105 } 106 env->condexec_bits = 0; 107 env->exception.syndrome = data[2] << ARM_INSN_START_WORD2_SHIFT; 108 } else { 109 if (TARGET_TB_PCREL) { 110 env->regs[15] = (env->regs[15] & TARGET_PAGE_MASK) | data[0]; 111 } else { 112 env->regs[15] = data[0]; 113 } 114 env->condexec_bits = data[1]; 115 env->exception.syndrome = data[2] << ARM_INSN_START_WORD2_SHIFT; 116 } 117 } 118 #endif /* CONFIG_TCG */ 119 120 static bool arm_cpu_has_work(CPUState *cs) 121 { 122 ARMCPU *cpu = ARM_CPU(cs); 123 124 return (cpu->power_state != PSCI_OFF) 125 && cs->interrupt_request & 126 (CPU_INTERRUPT_FIQ | CPU_INTERRUPT_HARD 127 | CPU_INTERRUPT_VFIQ | CPU_INTERRUPT_VIRQ | CPU_INTERRUPT_VSERR 128 | CPU_INTERRUPT_EXITTB); 129 } 130 131 void arm_register_pre_el_change_hook(ARMCPU *cpu, ARMELChangeHookFn *hook, 132 void *opaque) 133 { 134 ARMELChangeHook *entry = g_new0(ARMELChangeHook, 1); 135 136 entry->hook = hook; 137 entry->opaque = opaque; 138 139 QLIST_INSERT_HEAD(&cpu->pre_el_change_hooks, entry, node); 140 } 141 142 void arm_register_el_change_hook(ARMCPU *cpu, ARMELChangeHookFn *hook, 143 void *opaque) 144 { 145 ARMELChangeHook *entry = g_new0(ARMELChangeHook, 1); 146 147 entry->hook = hook; 148 entry->opaque = opaque; 149 150 QLIST_INSERT_HEAD(&cpu->el_change_hooks, entry, node); 151 } 152 153 static void cp_reg_reset(gpointer key, gpointer value, gpointer opaque) 154 { 155 /* Reset a single ARMCPRegInfo register */ 156 ARMCPRegInfo *ri = value; 157 ARMCPU *cpu = opaque; 158 159 if (ri->type & (ARM_CP_SPECIAL_MASK | ARM_CP_ALIAS)) { 160 return; 161 } 162 163 if (ri->resetfn) { 164 ri->resetfn(&cpu->env, ri); 165 return; 166 } 167 168 /* A zero offset is never possible as it would be regs[0] 169 * so we use it to indicate that reset is being handled elsewhere. 170 * This is basically only used for fields in non-core coprocessors 171 * (like the pxa2xx ones). 172 */ 173 if (!ri->fieldoffset) { 174 return; 175 } 176 177 if (cpreg_field_is_64bit(ri)) { 178 CPREG_FIELD64(&cpu->env, ri) = ri->resetvalue; 179 } else { 180 CPREG_FIELD32(&cpu->env, ri) = ri->resetvalue; 181 } 182 } 183 184 static void cp_reg_check_reset(gpointer key, gpointer value, gpointer opaque) 185 { 186 /* Purely an assertion check: we've already done reset once, 187 * so now check that running the reset for the cpreg doesn't 188 * change its value. This traps bugs where two different cpregs 189 * both try to reset the same state field but to different values. 190 */ 191 ARMCPRegInfo *ri = value; 192 ARMCPU *cpu = opaque; 193 uint64_t oldvalue, newvalue; 194 195 if (ri->type & (ARM_CP_SPECIAL_MASK | ARM_CP_ALIAS | ARM_CP_NO_RAW)) { 196 return; 197 } 198 199 oldvalue = read_raw_cp_reg(&cpu->env, ri); 200 cp_reg_reset(key, value, opaque); 201 newvalue = read_raw_cp_reg(&cpu->env, ri); 202 assert(oldvalue == newvalue); 203 } 204 205 static void arm_cpu_reset_hold(Object *obj) 206 { 207 CPUState *s = CPU(obj); 208 ARMCPU *cpu = ARM_CPU(s); 209 ARMCPUClass *acc = ARM_CPU_GET_CLASS(cpu); 210 CPUARMState *env = &cpu->env; 211 212 if (acc->parent_phases.hold) { 213 acc->parent_phases.hold(obj); 214 } 215 216 memset(env, 0, offsetof(CPUARMState, end_reset_fields)); 217 218 g_hash_table_foreach(cpu->cp_regs, cp_reg_reset, cpu); 219 g_hash_table_foreach(cpu->cp_regs, cp_reg_check_reset, cpu); 220 221 env->vfp.xregs[ARM_VFP_FPSID] = cpu->reset_fpsid; 222 env->vfp.xregs[ARM_VFP_MVFR0] = cpu->isar.mvfr0; 223 env->vfp.xregs[ARM_VFP_MVFR1] = cpu->isar.mvfr1; 224 env->vfp.xregs[ARM_VFP_MVFR2] = cpu->isar.mvfr2; 225 226 cpu->power_state = s->start_powered_off ? PSCI_OFF : PSCI_ON; 227 228 if (arm_feature(env, ARM_FEATURE_IWMMXT)) { 229 env->iwmmxt.cregs[ARM_IWMMXT_wCID] = 0x69051000 | 'Q'; 230 } 231 232 if (arm_feature(env, ARM_FEATURE_AARCH64)) { 233 /* 64 bit CPUs always start in 64 bit mode */ 234 env->aarch64 = true; 235 #if defined(CONFIG_USER_ONLY) 236 env->pstate = PSTATE_MODE_EL0t; 237 /* Userspace expects access to DC ZVA, CTL_EL0 and the cache ops */ 238 env->cp15.sctlr_el[1] |= SCTLR_UCT | SCTLR_UCI | SCTLR_DZE; 239 /* Enable all PAC keys. */ 240 env->cp15.sctlr_el[1] |= (SCTLR_EnIA | SCTLR_EnIB | 241 SCTLR_EnDA | SCTLR_EnDB); 242 /* Trap on btype=3 for PACIxSP. */ 243 env->cp15.sctlr_el[1] |= SCTLR_BT0; 244 /* and to the FP/Neon instructions */ 245 env->cp15.cpacr_el1 = FIELD_DP64(env->cp15.cpacr_el1, 246 CPACR_EL1, FPEN, 3); 247 /* and to the SVE instructions, with default vector length */ 248 if (cpu_isar_feature(aa64_sve, cpu)) { 249 env->cp15.cpacr_el1 = FIELD_DP64(env->cp15.cpacr_el1, 250 CPACR_EL1, ZEN, 3); 251 env->vfp.zcr_el[1] = cpu->sve_default_vq - 1; 252 } 253 /* and for SME instructions, with default vector length, and TPIDR2 */ 254 if (cpu_isar_feature(aa64_sme, cpu)) { 255 env->cp15.sctlr_el[1] |= SCTLR_EnTP2; 256 env->cp15.cpacr_el1 = FIELD_DP64(env->cp15.cpacr_el1, 257 CPACR_EL1, SMEN, 3); 258 env->vfp.smcr_el[1] = cpu->sme_default_vq - 1; 259 if (cpu_isar_feature(aa64_sme_fa64, cpu)) { 260 env->vfp.smcr_el[1] = FIELD_DP64(env->vfp.smcr_el[1], 261 SMCR, FA64, 1); 262 } 263 } 264 /* 265 * Enable 48-bit address space (TODO: take reserved_va into account). 266 * Enable TBI0 but not TBI1. 267 * Note that this must match useronly_clean_ptr. 268 */ 269 env->cp15.tcr_el[1] = 5 | (1ULL << 37); 270 271 /* Enable MTE */ 272 if (cpu_isar_feature(aa64_mte, cpu)) { 273 /* Enable tag access, but leave TCF0 as No Effect (0). */ 274 env->cp15.sctlr_el[1] |= SCTLR_ATA0; 275 /* 276 * Exclude all tags, so that tag 0 is always used. 277 * This corresponds to Linux current->thread.gcr_incl = 0. 278 * 279 * Set RRND, so that helper_irg() will generate a seed later. 280 * Here in cpu_reset(), the crypto subsystem has not yet been 281 * initialized. 282 */ 283 env->cp15.gcr_el1 = 0x1ffff; 284 } 285 /* 286 * Disable access to SCXTNUM_EL0 from CSV2_1p2. 287 * This is not yet exposed from the Linux kernel in any way. 288 */ 289 env->cp15.sctlr_el[1] |= SCTLR_TSCXT; 290 #else 291 /* Reset into the highest available EL */ 292 if (arm_feature(env, ARM_FEATURE_EL3)) { 293 env->pstate = PSTATE_MODE_EL3h; 294 } else if (arm_feature(env, ARM_FEATURE_EL2)) { 295 env->pstate = PSTATE_MODE_EL2h; 296 } else { 297 env->pstate = PSTATE_MODE_EL1h; 298 } 299 300 /* Sample rvbar at reset. */ 301 env->cp15.rvbar = cpu->rvbar_prop; 302 env->pc = env->cp15.rvbar; 303 #endif 304 } else { 305 #if defined(CONFIG_USER_ONLY) 306 /* Userspace expects access to cp10 and cp11 for FP/Neon */ 307 env->cp15.cpacr_el1 = FIELD_DP64(env->cp15.cpacr_el1, 308 CPACR, CP10, 3); 309 env->cp15.cpacr_el1 = FIELD_DP64(env->cp15.cpacr_el1, 310 CPACR, CP11, 3); 311 #endif 312 if (arm_feature(env, ARM_FEATURE_V8)) { 313 env->cp15.rvbar = cpu->rvbar_prop; 314 env->regs[15] = cpu->rvbar_prop; 315 } 316 } 317 318 #if defined(CONFIG_USER_ONLY) 319 env->uncached_cpsr = ARM_CPU_MODE_USR; 320 /* For user mode we must enable access to coprocessors */ 321 env->vfp.xregs[ARM_VFP_FPEXC] = 1 << 30; 322 if (arm_feature(env, ARM_FEATURE_IWMMXT)) { 323 env->cp15.c15_cpar = 3; 324 } else if (arm_feature(env, ARM_FEATURE_XSCALE)) { 325 env->cp15.c15_cpar = 1; 326 } 327 #else 328 329 /* 330 * If the highest available EL is EL2, AArch32 will start in Hyp 331 * mode; otherwise it starts in SVC. Note that if we start in 332 * AArch64 then these values in the uncached_cpsr will be ignored. 333 */ 334 if (arm_feature(env, ARM_FEATURE_EL2) && 335 !arm_feature(env, ARM_FEATURE_EL3)) { 336 env->uncached_cpsr = ARM_CPU_MODE_HYP; 337 } else { 338 env->uncached_cpsr = ARM_CPU_MODE_SVC; 339 } 340 env->daif = PSTATE_D | PSTATE_A | PSTATE_I | PSTATE_F; 341 342 /* AArch32 has a hard highvec setting of 0xFFFF0000. If we are currently 343 * executing as AArch32 then check if highvecs are enabled and 344 * adjust the PC accordingly. 345 */ 346 if (A32_BANKED_CURRENT_REG_GET(env, sctlr) & SCTLR_V) { 347 env->regs[15] = 0xFFFF0000; 348 } 349 350 env->vfp.xregs[ARM_VFP_FPEXC] = 0; 351 #endif 352 353 if (arm_feature(env, ARM_FEATURE_M)) { 354 #ifndef CONFIG_USER_ONLY 355 uint32_t initial_msp; /* Loaded from 0x0 */ 356 uint32_t initial_pc; /* Loaded from 0x4 */ 357 uint8_t *rom; 358 uint32_t vecbase; 359 #endif 360 361 if (cpu_isar_feature(aa32_lob, cpu)) { 362 /* 363 * LTPSIZE is constant 4 if MVE not implemented, and resets 364 * to an UNKNOWN value if MVE is implemented. We choose to 365 * always reset to 4. 366 */ 367 env->v7m.ltpsize = 4; 368 /* The LTPSIZE field in FPDSCR is constant and reads as 4. */ 369 env->v7m.fpdscr[M_REG_NS] = 4 << FPCR_LTPSIZE_SHIFT; 370 env->v7m.fpdscr[M_REG_S] = 4 << FPCR_LTPSIZE_SHIFT; 371 } 372 373 if (arm_feature(env, ARM_FEATURE_M_SECURITY)) { 374 env->v7m.secure = true; 375 } else { 376 /* This bit resets to 0 if security is supported, but 1 if 377 * it is not. The bit is not present in v7M, but we set it 378 * here so we can avoid having to make checks on it conditional 379 * on ARM_FEATURE_V8 (we don't let the guest see the bit). 380 */ 381 env->v7m.aircr = R_V7M_AIRCR_BFHFNMINS_MASK; 382 /* 383 * Set NSACR to indicate "NS access permitted to everything"; 384 * this avoids having to have all the tests of it being 385 * conditional on ARM_FEATURE_M_SECURITY. Note also that from 386 * v8.1M the guest-visible value of NSACR in a CPU without the 387 * Security Extension is 0xcff. 388 */ 389 env->v7m.nsacr = 0xcff; 390 } 391 392 /* In v7M the reset value of this bit is IMPDEF, but ARM recommends 393 * that it resets to 1, so QEMU always does that rather than making 394 * it dependent on CPU model. In v8M it is RES1. 395 */ 396 env->v7m.ccr[M_REG_NS] = R_V7M_CCR_STKALIGN_MASK; 397 env->v7m.ccr[M_REG_S] = R_V7M_CCR_STKALIGN_MASK; 398 if (arm_feature(env, ARM_FEATURE_V8)) { 399 /* in v8M the NONBASETHRDENA bit [0] is RES1 */ 400 env->v7m.ccr[M_REG_NS] |= R_V7M_CCR_NONBASETHRDENA_MASK; 401 env->v7m.ccr[M_REG_S] |= R_V7M_CCR_NONBASETHRDENA_MASK; 402 } 403 if (!arm_feature(env, ARM_FEATURE_M_MAIN)) { 404 env->v7m.ccr[M_REG_NS] |= R_V7M_CCR_UNALIGN_TRP_MASK; 405 env->v7m.ccr[M_REG_S] |= R_V7M_CCR_UNALIGN_TRP_MASK; 406 } 407 408 if (cpu_isar_feature(aa32_vfp_simd, cpu)) { 409 env->v7m.fpccr[M_REG_NS] = R_V7M_FPCCR_ASPEN_MASK; 410 env->v7m.fpccr[M_REG_S] = R_V7M_FPCCR_ASPEN_MASK | 411 R_V7M_FPCCR_LSPEN_MASK | R_V7M_FPCCR_S_MASK; 412 } 413 414 #ifndef CONFIG_USER_ONLY 415 /* Unlike A/R profile, M profile defines the reset LR value */ 416 env->regs[14] = 0xffffffff; 417 418 env->v7m.vecbase[M_REG_S] = cpu->init_svtor & 0xffffff80; 419 env->v7m.vecbase[M_REG_NS] = cpu->init_nsvtor & 0xffffff80; 420 421 /* Load the initial SP and PC from offset 0 and 4 in the vector table */ 422 vecbase = env->v7m.vecbase[env->v7m.secure]; 423 rom = rom_ptr_for_as(s->as, vecbase, 8); 424 if (rom) { 425 /* Address zero is covered by ROM which hasn't yet been 426 * copied into physical memory. 427 */ 428 initial_msp = ldl_p(rom); 429 initial_pc = ldl_p(rom + 4); 430 } else { 431 /* Address zero not covered by a ROM blob, or the ROM blob 432 * is in non-modifiable memory and this is a second reset after 433 * it got copied into memory. In the latter case, rom_ptr 434 * will return a NULL pointer and we should use ldl_phys instead. 435 */ 436 initial_msp = ldl_phys(s->as, vecbase); 437 initial_pc = ldl_phys(s->as, vecbase + 4); 438 } 439 440 qemu_log_mask(CPU_LOG_INT, 441 "Loaded reset SP 0x%x PC 0x%x from vector table\n", 442 initial_msp, initial_pc); 443 444 env->regs[13] = initial_msp & 0xFFFFFFFC; 445 env->regs[15] = initial_pc & ~1; 446 env->thumb = initial_pc & 1; 447 #else 448 /* 449 * For user mode we run non-secure and with access to the FPU. 450 * The FPU context is active (ie does not need further setup) 451 * and is owned by non-secure. 452 */ 453 env->v7m.secure = false; 454 env->v7m.nsacr = 0xcff; 455 env->v7m.cpacr[M_REG_NS] = 0xf0ffff; 456 env->v7m.fpccr[M_REG_S] &= 457 ~(R_V7M_FPCCR_LSPEN_MASK | R_V7M_FPCCR_S_MASK); 458 env->v7m.control[M_REG_S] |= R_V7M_CONTROL_FPCA_MASK; 459 #endif 460 } 461 462 /* M profile requires that reset clears the exclusive monitor; 463 * A profile does not, but clearing it makes more sense than having it 464 * set with an exclusive access on address zero. 465 */ 466 arm_clear_exclusive(env); 467 468 if (arm_feature(env, ARM_FEATURE_PMSA)) { 469 if (cpu->pmsav7_dregion > 0) { 470 if (arm_feature(env, ARM_FEATURE_V8)) { 471 memset(env->pmsav8.rbar[M_REG_NS], 0, 472 sizeof(*env->pmsav8.rbar[M_REG_NS]) 473 * cpu->pmsav7_dregion); 474 memset(env->pmsav8.rlar[M_REG_NS], 0, 475 sizeof(*env->pmsav8.rlar[M_REG_NS]) 476 * cpu->pmsav7_dregion); 477 if (arm_feature(env, ARM_FEATURE_M_SECURITY)) { 478 memset(env->pmsav8.rbar[M_REG_S], 0, 479 sizeof(*env->pmsav8.rbar[M_REG_S]) 480 * cpu->pmsav7_dregion); 481 memset(env->pmsav8.rlar[M_REG_S], 0, 482 sizeof(*env->pmsav8.rlar[M_REG_S]) 483 * cpu->pmsav7_dregion); 484 } 485 } else if (arm_feature(env, ARM_FEATURE_V7)) { 486 memset(env->pmsav7.drbar, 0, 487 sizeof(*env->pmsav7.drbar) * cpu->pmsav7_dregion); 488 memset(env->pmsav7.drsr, 0, 489 sizeof(*env->pmsav7.drsr) * cpu->pmsav7_dregion); 490 memset(env->pmsav7.dracr, 0, 491 sizeof(*env->pmsav7.dracr) * cpu->pmsav7_dregion); 492 } 493 } 494 495 if (cpu->pmsav8r_hdregion > 0) { 496 memset(env->pmsav8.hprbar, 0, 497 sizeof(*env->pmsav8.hprbar) * cpu->pmsav8r_hdregion); 498 memset(env->pmsav8.hprlar, 0, 499 sizeof(*env->pmsav8.hprlar) * cpu->pmsav8r_hdregion); 500 } 501 502 env->pmsav7.rnr[M_REG_NS] = 0; 503 env->pmsav7.rnr[M_REG_S] = 0; 504 env->pmsav8.mair0[M_REG_NS] = 0; 505 env->pmsav8.mair0[M_REG_S] = 0; 506 env->pmsav8.mair1[M_REG_NS] = 0; 507 env->pmsav8.mair1[M_REG_S] = 0; 508 } 509 510 if (arm_feature(env, ARM_FEATURE_M_SECURITY)) { 511 if (cpu->sau_sregion > 0) { 512 memset(env->sau.rbar, 0, sizeof(*env->sau.rbar) * cpu->sau_sregion); 513 memset(env->sau.rlar, 0, sizeof(*env->sau.rlar) * cpu->sau_sregion); 514 } 515 env->sau.rnr = 0; 516 /* SAU_CTRL reset value is IMPDEF; we choose 0, which is what 517 * the Cortex-M33 does. 518 */ 519 env->sau.ctrl = 0; 520 } 521 522 set_flush_to_zero(1, &env->vfp.standard_fp_status); 523 set_flush_inputs_to_zero(1, &env->vfp.standard_fp_status); 524 set_default_nan_mode(1, &env->vfp.standard_fp_status); 525 set_default_nan_mode(1, &env->vfp.standard_fp_status_f16); 526 set_float_detect_tininess(float_tininess_before_rounding, 527 &env->vfp.fp_status); 528 set_float_detect_tininess(float_tininess_before_rounding, 529 &env->vfp.standard_fp_status); 530 set_float_detect_tininess(float_tininess_before_rounding, 531 &env->vfp.fp_status_f16); 532 set_float_detect_tininess(float_tininess_before_rounding, 533 &env->vfp.standard_fp_status_f16); 534 #ifndef CONFIG_USER_ONLY 535 if (kvm_enabled()) { 536 kvm_arm_reset_vcpu(cpu); 537 } 538 #endif 539 540 hw_breakpoint_update_all(cpu); 541 hw_watchpoint_update_all(cpu); 542 arm_rebuild_hflags(env); 543 } 544 545 #if defined(CONFIG_TCG) && !defined(CONFIG_USER_ONLY) 546 547 static inline bool arm_excp_unmasked(CPUState *cs, unsigned int excp_idx, 548 unsigned int target_el, 549 unsigned int cur_el, bool secure, 550 uint64_t hcr_el2) 551 { 552 CPUARMState *env = cs->env_ptr; 553 bool pstate_unmasked; 554 bool unmasked = false; 555 556 /* 557 * Don't take exceptions if they target a lower EL. 558 * This check should catch any exceptions that would not be taken 559 * but left pending. 560 */ 561 if (cur_el > target_el) { 562 return false; 563 } 564 565 switch (excp_idx) { 566 case EXCP_FIQ: 567 pstate_unmasked = !(env->daif & PSTATE_F); 568 break; 569 570 case EXCP_IRQ: 571 pstate_unmasked = !(env->daif & PSTATE_I); 572 break; 573 574 case EXCP_VFIQ: 575 if (!(hcr_el2 & HCR_FMO) || (hcr_el2 & HCR_TGE)) { 576 /* VFIQs are only taken when hypervized. */ 577 return false; 578 } 579 return !(env->daif & PSTATE_F); 580 case EXCP_VIRQ: 581 if (!(hcr_el2 & HCR_IMO) || (hcr_el2 & HCR_TGE)) { 582 /* VIRQs are only taken when hypervized. */ 583 return false; 584 } 585 return !(env->daif & PSTATE_I); 586 case EXCP_VSERR: 587 if (!(hcr_el2 & HCR_AMO) || (hcr_el2 & HCR_TGE)) { 588 /* VIRQs are only taken when hypervized. */ 589 return false; 590 } 591 return !(env->daif & PSTATE_A); 592 default: 593 g_assert_not_reached(); 594 } 595 596 /* 597 * Use the target EL, current execution state and SCR/HCR settings to 598 * determine whether the corresponding CPSR bit is used to mask the 599 * interrupt. 600 */ 601 if ((target_el > cur_el) && (target_el != 1)) { 602 /* Exceptions targeting a higher EL may not be maskable */ 603 if (arm_feature(env, ARM_FEATURE_AARCH64)) { 604 switch (target_el) { 605 case 2: 606 /* 607 * According to ARM DDI 0487H.a, an interrupt can be masked 608 * when HCR_E2H and HCR_TGE are both set regardless of the 609 * current Security state. Note that we need to revisit this 610 * part again once we need to support NMI. 611 */ 612 if ((hcr_el2 & (HCR_E2H | HCR_TGE)) != (HCR_E2H | HCR_TGE)) { 613 unmasked = true; 614 } 615 break; 616 case 3: 617 /* Interrupt cannot be masked when the target EL is 3 */ 618 unmasked = true; 619 break; 620 default: 621 g_assert_not_reached(); 622 } 623 } else { 624 /* 625 * The old 32-bit-only environment has a more complicated 626 * masking setup. HCR and SCR bits not only affect interrupt 627 * routing but also change the behaviour of masking. 628 */ 629 bool hcr, scr; 630 631 switch (excp_idx) { 632 case EXCP_FIQ: 633 /* 634 * If FIQs are routed to EL3 or EL2 then there are cases where 635 * we override the CPSR.F in determining if the exception is 636 * masked or not. If neither of these are set then we fall back 637 * to the CPSR.F setting otherwise we further assess the state 638 * below. 639 */ 640 hcr = hcr_el2 & HCR_FMO; 641 scr = (env->cp15.scr_el3 & SCR_FIQ); 642 643 /* 644 * When EL3 is 32-bit, the SCR.FW bit controls whether the 645 * CPSR.F bit masks FIQ interrupts when taken in non-secure 646 * state. If SCR.FW is set then FIQs can be masked by CPSR.F 647 * when non-secure but only when FIQs are only routed to EL3. 648 */ 649 scr = scr && !((env->cp15.scr_el3 & SCR_FW) && !hcr); 650 break; 651 case EXCP_IRQ: 652 /* 653 * When EL3 execution state is 32-bit, if HCR.IMO is set then 654 * we may override the CPSR.I masking when in non-secure state. 655 * The SCR.IRQ setting has already been taken into consideration 656 * when setting the target EL, so it does not have a further 657 * affect here. 658 */ 659 hcr = hcr_el2 & HCR_IMO; 660 scr = false; 661 break; 662 default: 663 g_assert_not_reached(); 664 } 665 666 if ((scr || hcr) && !secure) { 667 unmasked = true; 668 } 669 } 670 } 671 672 /* 673 * The PSTATE bits only mask the interrupt if we have not overriden the 674 * ability above. 675 */ 676 return unmasked || pstate_unmasked; 677 } 678 679 static bool arm_cpu_exec_interrupt(CPUState *cs, int interrupt_request) 680 { 681 CPUClass *cc = CPU_GET_CLASS(cs); 682 CPUARMState *env = cs->env_ptr; 683 uint32_t cur_el = arm_current_el(env); 684 bool secure = arm_is_secure(env); 685 uint64_t hcr_el2 = arm_hcr_el2_eff(env); 686 uint32_t target_el; 687 uint32_t excp_idx; 688 689 /* The prioritization of interrupts is IMPLEMENTATION DEFINED. */ 690 691 if (interrupt_request & CPU_INTERRUPT_FIQ) { 692 excp_idx = EXCP_FIQ; 693 target_el = arm_phys_excp_target_el(cs, excp_idx, cur_el, secure); 694 if (arm_excp_unmasked(cs, excp_idx, target_el, 695 cur_el, secure, hcr_el2)) { 696 goto found; 697 } 698 } 699 if (interrupt_request & CPU_INTERRUPT_HARD) { 700 excp_idx = EXCP_IRQ; 701 target_el = arm_phys_excp_target_el(cs, excp_idx, cur_el, secure); 702 if (arm_excp_unmasked(cs, excp_idx, target_el, 703 cur_el, secure, hcr_el2)) { 704 goto found; 705 } 706 } 707 if (interrupt_request & CPU_INTERRUPT_VIRQ) { 708 excp_idx = EXCP_VIRQ; 709 target_el = 1; 710 if (arm_excp_unmasked(cs, excp_idx, target_el, 711 cur_el, secure, hcr_el2)) { 712 goto found; 713 } 714 } 715 if (interrupt_request & CPU_INTERRUPT_VFIQ) { 716 excp_idx = EXCP_VFIQ; 717 target_el = 1; 718 if (arm_excp_unmasked(cs, excp_idx, target_el, 719 cur_el, secure, hcr_el2)) { 720 goto found; 721 } 722 } 723 if (interrupt_request & CPU_INTERRUPT_VSERR) { 724 excp_idx = EXCP_VSERR; 725 target_el = 1; 726 if (arm_excp_unmasked(cs, excp_idx, target_el, 727 cur_el, secure, hcr_el2)) { 728 /* Taking a virtual abort clears HCR_EL2.VSE */ 729 env->cp15.hcr_el2 &= ~HCR_VSE; 730 cpu_reset_interrupt(cs, CPU_INTERRUPT_VSERR); 731 goto found; 732 } 733 } 734 return false; 735 736 found: 737 cs->exception_index = excp_idx; 738 env->exception.target_el = target_el; 739 cc->tcg_ops->do_interrupt(cs); 740 return true; 741 } 742 743 #endif /* CONFIG_TCG && !CONFIG_USER_ONLY */ 744 745 void arm_cpu_update_virq(ARMCPU *cpu) 746 { 747 /* 748 * Update the interrupt level for VIRQ, which is the logical OR of 749 * the HCR_EL2.VI bit and the input line level from the GIC. 750 */ 751 CPUARMState *env = &cpu->env; 752 CPUState *cs = CPU(cpu); 753 754 bool new_state = (env->cp15.hcr_el2 & HCR_VI) || 755 (env->irq_line_state & CPU_INTERRUPT_VIRQ); 756 757 if (new_state != ((cs->interrupt_request & CPU_INTERRUPT_VIRQ) != 0)) { 758 if (new_state) { 759 cpu_interrupt(cs, CPU_INTERRUPT_VIRQ); 760 } else { 761 cpu_reset_interrupt(cs, CPU_INTERRUPT_VIRQ); 762 } 763 } 764 } 765 766 void arm_cpu_update_vfiq(ARMCPU *cpu) 767 { 768 /* 769 * Update the interrupt level for VFIQ, which is the logical OR of 770 * the HCR_EL2.VF bit and the input line level from the GIC. 771 */ 772 CPUARMState *env = &cpu->env; 773 CPUState *cs = CPU(cpu); 774 775 bool new_state = (env->cp15.hcr_el2 & HCR_VF) || 776 (env->irq_line_state & CPU_INTERRUPT_VFIQ); 777 778 if (new_state != ((cs->interrupt_request & CPU_INTERRUPT_VFIQ) != 0)) { 779 if (new_state) { 780 cpu_interrupt(cs, CPU_INTERRUPT_VFIQ); 781 } else { 782 cpu_reset_interrupt(cs, CPU_INTERRUPT_VFIQ); 783 } 784 } 785 } 786 787 void arm_cpu_update_vserr(ARMCPU *cpu) 788 { 789 /* 790 * Update the interrupt level for VSERR, which is the HCR_EL2.VSE bit. 791 */ 792 CPUARMState *env = &cpu->env; 793 CPUState *cs = CPU(cpu); 794 795 bool new_state = env->cp15.hcr_el2 & HCR_VSE; 796 797 if (new_state != ((cs->interrupt_request & CPU_INTERRUPT_VSERR) != 0)) { 798 if (new_state) { 799 cpu_interrupt(cs, CPU_INTERRUPT_VSERR); 800 } else { 801 cpu_reset_interrupt(cs, CPU_INTERRUPT_VSERR); 802 } 803 } 804 } 805 806 #ifndef CONFIG_USER_ONLY 807 static void arm_cpu_set_irq(void *opaque, int irq, int level) 808 { 809 ARMCPU *cpu = opaque; 810 CPUARMState *env = &cpu->env; 811 CPUState *cs = CPU(cpu); 812 static const int mask[] = { 813 [ARM_CPU_IRQ] = CPU_INTERRUPT_HARD, 814 [ARM_CPU_FIQ] = CPU_INTERRUPT_FIQ, 815 [ARM_CPU_VIRQ] = CPU_INTERRUPT_VIRQ, 816 [ARM_CPU_VFIQ] = CPU_INTERRUPT_VFIQ 817 }; 818 819 if (!arm_feature(env, ARM_FEATURE_EL2) && 820 (irq == ARM_CPU_VIRQ || irq == ARM_CPU_VFIQ)) { 821 /* 822 * The GIC might tell us about VIRQ and VFIQ state, but if we don't 823 * have EL2 support we don't care. (Unless the guest is doing something 824 * silly this will only be calls saying "level is still 0".) 825 */ 826 return; 827 } 828 829 if (level) { 830 env->irq_line_state |= mask[irq]; 831 } else { 832 env->irq_line_state &= ~mask[irq]; 833 } 834 835 switch (irq) { 836 case ARM_CPU_VIRQ: 837 arm_cpu_update_virq(cpu); 838 break; 839 case ARM_CPU_VFIQ: 840 arm_cpu_update_vfiq(cpu); 841 break; 842 case ARM_CPU_IRQ: 843 case ARM_CPU_FIQ: 844 if (level) { 845 cpu_interrupt(cs, mask[irq]); 846 } else { 847 cpu_reset_interrupt(cs, mask[irq]); 848 } 849 break; 850 default: 851 g_assert_not_reached(); 852 } 853 } 854 855 static void arm_cpu_kvm_set_irq(void *opaque, int irq, int level) 856 { 857 #ifdef CONFIG_KVM 858 ARMCPU *cpu = opaque; 859 CPUARMState *env = &cpu->env; 860 CPUState *cs = CPU(cpu); 861 uint32_t linestate_bit; 862 int irq_id; 863 864 switch (irq) { 865 case ARM_CPU_IRQ: 866 irq_id = KVM_ARM_IRQ_CPU_IRQ; 867 linestate_bit = CPU_INTERRUPT_HARD; 868 break; 869 case ARM_CPU_FIQ: 870 irq_id = KVM_ARM_IRQ_CPU_FIQ; 871 linestate_bit = CPU_INTERRUPT_FIQ; 872 break; 873 default: 874 g_assert_not_reached(); 875 } 876 877 if (level) { 878 env->irq_line_state |= linestate_bit; 879 } else { 880 env->irq_line_state &= ~linestate_bit; 881 } 882 kvm_arm_set_irq(cs->cpu_index, KVM_ARM_IRQ_TYPE_CPU, irq_id, !!level); 883 #endif 884 } 885 886 static bool arm_cpu_virtio_is_big_endian(CPUState *cs) 887 { 888 ARMCPU *cpu = ARM_CPU(cs); 889 CPUARMState *env = &cpu->env; 890 891 cpu_synchronize_state(cs); 892 return arm_cpu_data_is_big_endian(env); 893 } 894 895 #endif 896 897 static void arm_disas_set_info(CPUState *cpu, disassemble_info *info) 898 { 899 ARMCPU *ac = ARM_CPU(cpu); 900 CPUARMState *env = &ac->env; 901 bool sctlr_b; 902 903 if (is_a64(env)) { 904 info->cap_arch = CS_ARCH_ARM64; 905 info->cap_insn_unit = 4; 906 info->cap_insn_split = 4; 907 } else { 908 int cap_mode; 909 if (env->thumb) { 910 info->cap_insn_unit = 2; 911 info->cap_insn_split = 4; 912 cap_mode = CS_MODE_THUMB; 913 } else { 914 info->cap_insn_unit = 4; 915 info->cap_insn_split = 4; 916 cap_mode = CS_MODE_ARM; 917 } 918 if (arm_feature(env, ARM_FEATURE_V8)) { 919 cap_mode |= CS_MODE_V8; 920 } 921 if (arm_feature(env, ARM_FEATURE_M)) { 922 cap_mode |= CS_MODE_MCLASS; 923 } 924 info->cap_arch = CS_ARCH_ARM; 925 info->cap_mode = cap_mode; 926 } 927 928 sctlr_b = arm_sctlr_b(env); 929 if (bswap_code(sctlr_b)) { 930 #if TARGET_BIG_ENDIAN 931 info->endian = BFD_ENDIAN_LITTLE; 932 #else 933 info->endian = BFD_ENDIAN_BIG; 934 #endif 935 } 936 info->flags &= ~INSN_ARM_BE32; 937 #ifndef CONFIG_USER_ONLY 938 if (sctlr_b) { 939 info->flags |= INSN_ARM_BE32; 940 } 941 #endif 942 } 943 944 #ifdef TARGET_AARCH64 945 946 static void aarch64_cpu_dump_state(CPUState *cs, FILE *f, int flags) 947 { 948 ARMCPU *cpu = ARM_CPU(cs); 949 CPUARMState *env = &cpu->env; 950 uint32_t psr = pstate_read(env); 951 int i; 952 int el = arm_current_el(env); 953 const char *ns_status; 954 bool sve; 955 956 qemu_fprintf(f, " PC=%016" PRIx64 " ", env->pc); 957 for (i = 0; i < 32; i++) { 958 if (i == 31) { 959 qemu_fprintf(f, " SP=%016" PRIx64 "\n", env->xregs[i]); 960 } else { 961 qemu_fprintf(f, "X%02d=%016" PRIx64 "%s", i, env->xregs[i], 962 (i + 2) % 3 ? " " : "\n"); 963 } 964 } 965 966 if (arm_feature(env, ARM_FEATURE_EL3) && el != 3) { 967 ns_status = env->cp15.scr_el3 & SCR_NS ? "NS " : "S "; 968 } else { 969 ns_status = ""; 970 } 971 qemu_fprintf(f, "PSTATE=%08x %c%c%c%c %sEL%d%c", 972 psr, 973 psr & PSTATE_N ? 'N' : '-', 974 psr & PSTATE_Z ? 'Z' : '-', 975 psr & PSTATE_C ? 'C' : '-', 976 psr & PSTATE_V ? 'V' : '-', 977 ns_status, 978 el, 979 psr & PSTATE_SP ? 'h' : 't'); 980 981 if (cpu_isar_feature(aa64_sme, cpu)) { 982 qemu_fprintf(f, " SVCR=%08" PRIx64 " %c%c", 983 env->svcr, 984 (FIELD_EX64(env->svcr, SVCR, ZA) ? 'Z' : '-'), 985 (FIELD_EX64(env->svcr, SVCR, SM) ? 'S' : '-')); 986 } 987 if (cpu_isar_feature(aa64_bti, cpu)) { 988 qemu_fprintf(f, " BTYPE=%d", (psr & PSTATE_BTYPE) >> 10); 989 } 990 if (!(flags & CPU_DUMP_FPU)) { 991 qemu_fprintf(f, "\n"); 992 return; 993 } 994 if (fp_exception_el(env, el) != 0) { 995 qemu_fprintf(f, " FPU disabled\n"); 996 return; 997 } 998 qemu_fprintf(f, " FPCR=%08x FPSR=%08x\n", 999 vfp_get_fpcr(env), vfp_get_fpsr(env)); 1000 1001 if (cpu_isar_feature(aa64_sme, cpu) && FIELD_EX64(env->svcr, SVCR, SM)) { 1002 sve = sme_exception_el(env, el) == 0; 1003 } else if (cpu_isar_feature(aa64_sve, cpu)) { 1004 sve = sve_exception_el(env, el) == 0; 1005 } else { 1006 sve = false; 1007 } 1008 1009 if (sve) { 1010 int j, zcr_len = sve_vqm1_for_el(env, el); 1011 1012 for (i = 0; i <= FFR_PRED_NUM; i++) { 1013 bool eol; 1014 if (i == FFR_PRED_NUM) { 1015 qemu_fprintf(f, "FFR="); 1016 /* It's last, so end the line. */ 1017 eol = true; 1018 } else { 1019 qemu_fprintf(f, "P%02d=", i); 1020 switch (zcr_len) { 1021 case 0: 1022 eol = i % 8 == 7; 1023 break; 1024 case 1: 1025 eol = i % 6 == 5; 1026 break; 1027 case 2: 1028 case 3: 1029 eol = i % 3 == 2; 1030 break; 1031 default: 1032 /* More than one quadword per predicate. */ 1033 eol = true; 1034 break; 1035 } 1036 } 1037 for (j = zcr_len / 4; j >= 0; j--) { 1038 int digits; 1039 if (j * 4 + 4 <= zcr_len + 1) { 1040 digits = 16; 1041 } else { 1042 digits = (zcr_len % 4 + 1) * 4; 1043 } 1044 qemu_fprintf(f, "%0*" PRIx64 "%s", digits, 1045 env->vfp.pregs[i].p[j], 1046 j ? ":" : eol ? "\n" : " "); 1047 } 1048 } 1049 1050 for (i = 0; i < 32; i++) { 1051 if (zcr_len == 0) { 1052 qemu_fprintf(f, "Z%02d=%016" PRIx64 ":%016" PRIx64 "%s", 1053 i, env->vfp.zregs[i].d[1], 1054 env->vfp.zregs[i].d[0], i & 1 ? "\n" : " "); 1055 } else if (zcr_len == 1) { 1056 qemu_fprintf(f, "Z%02d=%016" PRIx64 ":%016" PRIx64 1057 ":%016" PRIx64 ":%016" PRIx64 "\n", 1058 i, env->vfp.zregs[i].d[3], env->vfp.zregs[i].d[2], 1059 env->vfp.zregs[i].d[1], env->vfp.zregs[i].d[0]); 1060 } else { 1061 for (j = zcr_len; j >= 0; j--) { 1062 bool odd = (zcr_len - j) % 2 != 0; 1063 if (j == zcr_len) { 1064 qemu_fprintf(f, "Z%02d[%x-%x]=", i, j, j - 1); 1065 } else if (!odd) { 1066 if (j > 0) { 1067 qemu_fprintf(f, " [%x-%x]=", j, j - 1); 1068 } else { 1069 qemu_fprintf(f, " [%x]=", j); 1070 } 1071 } 1072 qemu_fprintf(f, "%016" PRIx64 ":%016" PRIx64 "%s", 1073 env->vfp.zregs[i].d[j * 2 + 1], 1074 env->vfp.zregs[i].d[j * 2], 1075 odd || j == 0 ? "\n" : ":"); 1076 } 1077 } 1078 } 1079 } else { 1080 for (i = 0; i < 32; i++) { 1081 uint64_t *q = aa64_vfp_qreg(env, i); 1082 qemu_fprintf(f, "Q%02d=%016" PRIx64 ":%016" PRIx64 "%s", 1083 i, q[1], q[0], (i & 1 ? "\n" : " ")); 1084 } 1085 } 1086 } 1087 1088 #else 1089 1090 static inline void aarch64_cpu_dump_state(CPUState *cs, FILE *f, int flags) 1091 { 1092 g_assert_not_reached(); 1093 } 1094 1095 #endif 1096 1097 static void arm_cpu_dump_state(CPUState *cs, FILE *f, int flags) 1098 { 1099 ARMCPU *cpu = ARM_CPU(cs); 1100 CPUARMState *env = &cpu->env; 1101 int i; 1102 1103 if (is_a64(env)) { 1104 aarch64_cpu_dump_state(cs, f, flags); 1105 return; 1106 } 1107 1108 for (i = 0; i < 16; i++) { 1109 qemu_fprintf(f, "R%02d=%08x", i, env->regs[i]); 1110 if ((i % 4) == 3) { 1111 qemu_fprintf(f, "\n"); 1112 } else { 1113 qemu_fprintf(f, " "); 1114 } 1115 } 1116 1117 if (arm_feature(env, ARM_FEATURE_M)) { 1118 uint32_t xpsr = xpsr_read(env); 1119 const char *mode; 1120 const char *ns_status = ""; 1121 1122 if (arm_feature(env, ARM_FEATURE_M_SECURITY)) { 1123 ns_status = env->v7m.secure ? "S " : "NS "; 1124 } 1125 1126 if (xpsr & XPSR_EXCP) { 1127 mode = "handler"; 1128 } else { 1129 if (env->v7m.control[env->v7m.secure] & R_V7M_CONTROL_NPRIV_MASK) { 1130 mode = "unpriv-thread"; 1131 } else { 1132 mode = "priv-thread"; 1133 } 1134 } 1135 1136 qemu_fprintf(f, "XPSR=%08x %c%c%c%c %c %s%s\n", 1137 xpsr, 1138 xpsr & XPSR_N ? 'N' : '-', 1139 xpsr & XPSR_Z ? 'Z' : '-', 1140 xpsr & XPSR_C ? 'C' : '-', 1141 xpsr & XPSR_V ? 'V' : '-', 1142 xpsr & XPSR_T ? 'T' : 'A', 1143 ns_status, 1144 mode); 1145 } else { 1146 uint32_t psr = cpsr_read(env); 1147 const char *ns_status = ""; 1148 1149 if (arm_feature(env, ARM_FEATURE_EL3) && 1150 (psr & CPSR_M) != ARM_CPU_MODE_MON) { 1151 ns_status = env->cp15.scr_el3 & SCR_NS ? "NS " : "S "; 1152 } 1153 1154 qemu_fprintf(f, "PSR=%08x %c%c%c%c %c %s%s%d\n", 1155 psr, 1156 psr & CPSR_N ? 'N' : '-', 1157 psr & CPSR_Z ? 'Z' : '-', 1158 psr & CPSR_C ? 'C' : '-', 1159 psr & CPSR_V ? 'V' : '-', 1160 psr & CPSR_T ? 'T' : 'A', 1161 ns_status, 1162 aarch32_mode_name(psr), (psr & 0x10) ? 32 : 26); 1163 } 1164 1165 if (flags & CPU_DUMP_FPU) { 1166 int numvfpregs = 0; 1167 if (cpu_isar_feature(aa32_simd_r32, cpu)) { 1168 numvfpregs = 32; 1169 } else if (cpu_isar_feature(aa32_vfp_simd, cpu)) { 1170 numvfpregs = 16; 1171 } 1172 for (i = 0; i < numvfpregs; i++) { 1173 uint64_t v = *aa32_vfp_dreg(env, i); 1174 qemu_fprintf(f, "s%02d=%08x s%02d=%08x d%02d=%016" PRIx64 "\n", 1175 i * 2, (uint32_t)v, 1176 i * 2 + 1, (uint32_t)(v >> 32), 1177 i, v); 1178 } 1179 qemu_fprintf(f, "FPSCR: %08x\n", vfp_get_fpscr(env)); 1180 if (cpu_isar_feature(aa32_mve, cpu)) { 1181 qemu_fprintf(f, "VPR: %08x\n", env->v7m.vpr); 1182 } 1183 } 1184 } 1185 1186 uint64_t arm_cpu_mp_affinity(int idx, uint8_t clustersz) 1187 { 1188 uint32_t Aff1 = idx / clustersz; 1189 uint32_t Aff0 = idx % clustersz; 1190 return (Aff1 << ARM_AFF1_SHIFT) | Aff0; 1191 } 1192 1193 static void arm_cpu_initfn(Object *obj) 1194 { 1195 ARMCPU *cpu = ARM_CPU(obj); 1196 1197 cpu_set_cpustate_pointers(cpu); 1198 cpu->cp_regs = g_hash_table_new_full(g_direct_hash, g_direct_equal, 1199 NULL, g_free); 1200 1201 QLIST_INIT(&cpu->pre_el_change_hooks); 1202 QLIST_INIT(&cpu->el_change_hooks); 1203 1204 #ifdef CONFIG_USER_ONLY 1205 # ifdef TARGET_AARCH64 1206 /* 1207 * The linux kernel defaults to 512-bit for SVE, and 256-bit for SME. 1208 * These values were chosen to fit within the default signal frame. 1209 * See documentation for /proc/sys/abi/{sve,sme}_default_vector_length, 1210 * and our corresponding cpu property. 1211 */ 1212 cpu->sve_default_vq = 4; 1213 cpu->sme_default_vq = 2; 1214 # endif 1215 #else 1216 /* Our inbound IRQ and FIQ lines */ 1217 if (kvm_enabled()) { 1218 /* VIRQ and VFIQ are unused with KVM but we add them to maintain 1219 * the same interface as non-KVM CPUs. 1220 */ 1221 qdev_init_gpio_in(DEVICE(cpu), arm_cpu_kvm_set_irq, 4); 1222 } else { 1223 qdev_init_gpio_in(DEVICE(cpu), arm_cpu_set_irq, 4); 1224 } 1225 1226 qdev_init_gpio_out(DEVICE(cpu), cpu->gt_timer_outputs, 1227 ARRAY_SIZE(cpu->gt_timer_outputs)); 1228 1229 qdev_init_gpio_out_named(DEVICE(cpu), &cpu->gicv3_maintenance_interrupt, 1230 "gicv3-maintenance-interrupt", 1); 1231 qdev_init_gpio_out_named(DEVICE(cpu), &cpu->pmu_interrupt, 1232 "pmu-interrupt", 1); 1233 #endif 1234 1235 /* DTB consumers generally don't in fact care what the 'compatible' 1236 * string is, so always provide some string and trust that a hypothetical 1237 * picky DTB consumer will also provide a helpful error message. 1238 */ 1239 cpu->dtb_compatible = "qemu,unknown"; 1240 cpu->psci_version = QEMU_PSCI_VERSION_0_1; /* By default assume PSCI v0.1 */ 1241 cpu->kvm_target = QEMU_KVM_ARM_TARGET_NONE; 1242 1243 if (tcg_enabled() || hvf_enabled()) { 1244 /* TCG and HVF implement PSCI 1.1 */ 1245 cpu->psci_version = QEMU_PSCI_VERSION_1_1; 1246 } 1247 } 1248 1249 static Property arm_cpu_gt_cntfrq_property = 1250 DEFINE_PROP_UINT64("cntfrq", ARMCPU, gt_cntfrq_hz, 1251 NANOSECONDS_PER_SECOND / GTIMER_SCALE); 1252 1253 static Property arm_cpu_reset_cbar_property = 1254 DEFINE_PROP_UINT64("reset-cbar", ARMCPU, reset_cbar, 0); 1255 1256 static Property arm_cpu_reset_hivecs_property = 1257 DEFINE_PROP_BOOL("reset-hivecs", ARMCPU, reset_hivecs, false); 1258 1259 #ifndef CONFIG_USER_ONLY 1260 static Property arm_cpu_has_el2_property = 1261 DEFINE_PROP_BOOL("has_el2", ARMCPU, has_el2, true); 1262 1263 static Property arm_cpu_has_el3_property = 1264 DEFINE_PROP_BOOL("has_el3", ARMCPU, has_el3, true); 1265 #endif 1266 1267 static Property arm_cpu_cfgend_property = 1268 DEFINE_PROP_BOOL("cfgend", ARMCPU, cfgend, false); 1269 1270 static Property arm_cpu_has_vfp_property = 1271 DEFINE_PROP_BOOL("vfp", ARMCPU, has_vfp, true); 1272 1273 static Property arm_cpu_has_neon_property = 1274 DEFINE_PROP_BOOL("neon", ARMCPU, has_neon, true); 1275 1276 static Property arm_cpu_has_dsp_property = 1277 DEFINE_PROP_BOOL("dsp", ARMCPU, has_dsp, true); 1278 1279 static Property arm_cpu_has_mpu_property = 1280 DEFINE_PROP_BOOL("has-mpu", ARMCPU, has_mpu, true); 1281 1282 /* This is like DEFINE_PROP_UINT32 but it doesn't set the default value, 1283 * because the CPU initfn will have already set cpu->pmsav7_dregion to 1284 * the right value for that particular CPU type, and we don't want 1285 * to override that with an incorrect constant value. 1286 */ 1287 static Property arm_cpu_pmsav7_dregion_property = 1288 DEFINE_PROP_UNSIGNED_NODEFAULT("pmsav7-dregion", ARMCPU, 1289 pmsav7_dregion, 1290 qdev_prop_uint32, uint32_t); 1291 1292 static bool arm_get_pmu(Object *obj, Error **errp) 1293 { 1294 ARMCPU *cpu = ARM_CPU(obj); 1295 1296 return cpu->has_pmu; 1297 } 1298 1299 static void arm_set_pmu(Object *obj, bool value, Error **errp) 1300 { 1301 ARMCPU *cpu = ARM_CPU(obj); 1302 1303 if (value) { 1304 if (kvm_enabled() && !kvm_arm_pmu_supported()) { 1305 error_setg(errp, "'pmu' feature not supported by KVM on this host"); 1306 return; 1307 } 1308 set_feature(&cpu->env, ARM_FEATURE_PMU); 1309 } else { 1310 unset_feature(&cpu->env, ARM_FEATURE_PMU); 1311 } 1312 cpu->has_pmu = value; 1313 } 1314 1315 unsigned int gt_cntfrq_period_ns(ARMCPU *cpu) 1316 { 1317 /* 1318 * The exact approach to calculating guest ticks is: 1319 * 1320 * muldiv64(qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL), cpu->gt_cntfrq_hz, 1321 * NANOSECONDS_PER_SECOND); 1322 * 1323 * We don't do that. Rather we intentionally use integer division 1324 * truncation below and in the caller for the conversion of host monotonic 1325 * time to guest ticks to provide the exact inverse for the semantics of 1326 * the QEMUTimer scale factor. QEMUTimer's scale facter is an integer, so 1327 * it loses precision when representing frequencies where 1328 * `(NANOSECONDS_PER_SECOND % cpu->gt_cntfrq) > 0` holds. Failing to 1329 * provide an exact inverse leads to scheduling timers with negative 1330 * periods, which in turn leads to sticky behaviour in the guest. 1331 * 1332 * Finally, CNTFRQ is effectively capped at 1GHz to ensure our scale factor 1333 * cannot become zero. 1334 */ 1335 return NANOSECONDS_PER_SECOND > cpu->gt_cntfrq_hz ? 1336 NANOSECONDS_PER_SECOND / cpu->gt_cntfrq_hz : 1; 1337 } 1338 1339 void arm_cpu_post_init(Object *obj) 1340 { 1341 ARMCPU *cpu = ARM_CPU(obj); 1342 1343 /* M profile implies PMSA. We have to do this here rather than 1344 * in realize with the other feature-implication checks because 1345 * we look at the PMSA bit to see if we should add some properties. 1346 */ 1347 if (arm_feature(&cpu->env, ARM_FEATURE_M)) { 1348 set_feature(&cpu->env, ARM_FEATURE_PMSA); 1349 } 1350 1351 if (arm_feature(&cpu->env, ARM_FEATURE_CBAR) || 1352 arm_feature(&cpu->env, ARM_FEATURE_CBAR_RO)) { 1353 qdev_property_add_static(DEVICE(obj), &arm_cpu_reset_cbar_property); 1354 } 1355 1356 if (!arm_feature(&cpu->env, ARM_FEATURE_M)) { 1357 qdev_property_add_static(DEVICE(obj), &arm_cpu_reset_hivecs_property); 1358 } 1359 1360 if (arm_feature(&cpu->env, ARM_FEATURE_V8)) { 1361 object_property_add_uint64_ptr(obj, "rvbar", 1362 &cpu->rvbar_prop, 1363 OBJ_PROP_FLAG_READWRITE); 1364 } 1365 1366 #ifndef CONFIG_USER_ONLY 1367 if (arm_feature(&cpu->env, ARM_FEATURE_EL3)) { 1368 /* Add the has_el3 state CPU property only if EL3 is allowed. This will 1369 * prevent "has_el3" from existing on CPUs which cannot support EL3. 1370 */ 1371 qdev_property_add_static(DEVICE(obj), &arm_cpu_has_el3_property); 1372 1373 object_property_add_link(obj, "secure-memory", 1374 TYPE_MEMORY_REGION, 1375 (Object **)&cpu->secure_memory, 1376 qdev_prop_allow_set_link_before_realize, 1377 OBJ_PROP_LINK_STRONG); 1378 } 1379 1380 if (arm_feature(&cpu->env, ARM_FEATURE_EL2)) { 1381 qdev_property_add_static(DEVICE(obj), &arm_cpu_has_el2_property); 1382 } 1383 #endif 1384 1385 if (arm_feature(&cpu->env, ARM_FEATURE_PMU)) { 1386 cpu->has_pmu = true; 1387 object_property_add_bool(obj, "pmu", arm_get_pmu, arm_set_pmu); 1388 } 1389 1390 /* 1391 * Allow user to turn off VFP and Neon support, but only for TCG -- 1392 * KVM does not currently allow us to lie to the guest about its 1393 * ID/feature registers, so the guest always sees what the host has. 1394 */ 1395 if (arm_feature(&cpu->env, ARM_FEATURE_AARCH64) 1396 ? cpu_isar_feature(aa64_fp_simd, cpu) 1397 : cpu_isar_feature(aa32_vfp, cpu)) { 1398 cpu->has_vfp = true; 1399 if (!kvm_enabled()) { 1400 qdev_property_add_static(DEVICE(obj), &arm_cpu_has_vfp_property); 1401 } 1402 } 1403 1404 if (arm_feature(&cpu->env, ARM_FEATURE_NEON)) { 1405 cpu->has_neon = true; 1406 if (!kvm_enabled()) { 1407 qdev_property_add_static(DEVICE(obj), &arm_cpu_has_neon_property); 1408 } 1409 } 1410 1411 if (arm_feature(&cpu->env, ARM_FEATURE_M) && 1412 arm_feature(&cpu->env, ARM_FEATURE_THUMB_DSP)) { 1413 qdev_property_add_static(DEVICE(obj), &arm_cpu_has_dsp_property); 1414 } 1415 1416 if (arm_feature(&cpu->env, ARM_FEATURE_PMSA)) { 1417 qdev_property_add_static(DEVICE(obj), &arm_cpu_has_mpu_property); 1418 if (arm_feature(&cpu->env, ARM_FEATURE_V7)) { 1419 qdev_property_add_static(DEVICE(obj), 1420 &arm_cpu_pmsav7_dregion_property); 1421 } 1422 } 1423 1424 if (arm_feature(&cpu->env, ARM_FEATURE_M_SECURITY)) { 1425 object_property_add_link(obj, "idau", TYPE_IDAU_INTERFACE, &cpu->idau, 1426 qdev_prop_allow_set_link_before_realize, 1427 OBJ_PROP_LINK_STRONG); 1428 /* 1429 * M profile: initial value of the Secure VTOR. We can't just use 1430 * a simple DEFINE_PROP_UINT32 for this because we want to permit 1431 * the property to be set after realize. 1432 */ 1433 object_property_add_uint32_ptr(obj, "init-svtor", 1434 &cpu->init_svtor, 1435 OBJ_PROP_FLAG_READWRITE); 1436 } 1437 if (arm_feature(&cpu->env, ARM_FEATURE_M)) { 1438 /* 1439 * Initial value of the NS VTOR (for cores without the Security 1440 * extension, this is the only VTOR) 1441 */ 1442 object_property_add_uint32_ptr(obj, "init-nsvtor", 1443 &cpu->init_nsvtor, 1444 OBJ_PROP_FLAG_READWRITE); 1445 } 1446 1447 /* Not DEFINE_PROP_UINT32: we want this to be settable after realize */ 1448 object_property_add_uint32_ptr(obj, "psci-conduit", 1449 &cpu->psci_conduit, 1450 OBJ_PROP_FLAG_READWRITE); 1451 1452 qdev_property_add_static(DEVICE(obj), &arm_cpu_cfgend_property); 1453 1454 if (arm_feature(&cpu->env, ARM_FEATURE_GENERIC_TIMER)) { 1455 qdev_property_add_static(DEVICE(cpu), &arm_cpu_gt_cntfrq_property); 1456 } 1457 1458 if (kvm_enabled()) { 1459 kvm_arm_add_vcpu_properties(obj); 1460 } 1461 1462 #ifndef CONFIG_USER_ONLY 1463 if (arm_feature(&cpu->env, ARM_FEATURE_AARCH64) && 1464 cpu_isar_feature(aa64_mte, cpu)) { 1465 object_property_add_link(obj, "tag-memory", 1466 TYPE_MEMORY_REGION, 1467 (Object **)&cpu->tag_memory, 1468 qdev_prop_allow_set_link_before_realize, 1469 OBJ_PROP_LINK_STRONG); 1470 1471 if (arm_feature(&cpu->env, ARM_FEATURE_EL3)) { 1472 object_property_add_link(obj, "secure-tag-memory", 1473 TYPE_MEMORY_REGION, 1474 (Object **)&cpu->secure_tag_memory, 1475 qdev_prop_allow_set_link_before_realize, 1476 OBJ_PROP_LINK_STRONG); 1477 } 1478 } 1479 #endif 1480 } 1481 1482 static void arm_cpu_finalizefn(Object *obj) 1483 { 1484 ARMCPU *cpu = ARM_CPU(obj); 1485 ARMELChangeHook *hook, *next; 1486 1487 g_hash_table_destroy(cpu->cp_regs); 1488 1489 QLIST_FOREACH_SAFE(hook, &cpu->pre_el_change_hooks, node, next) { 1490 QLIST_REMOVE(hook, node); 1491 g_free(hook); 1492 } 1493 QLIST_FOREACH_SAFE(hook, &cpu->el_change_hooks, node, next) { 1494 QLIST_REMOVE(hook, node); 1495 g_free(hook); 1496 } 1497 #ifndef CONFIG_USER_ONLY 1498 if (cpu->pmu_timer) { 1499 timer_free(cpu->pmu_timer); 1500 } 1501 #endif 1502 } 1503 1504 void arm_cpu_finalize_features(ARMCPU *cpu, Error **errp) 1505 { 1506 Error *local_err = NULL; 1507 1508 #ifdef TARGET_AARCH64 1509 if (arm_feature(&cpu->env, ARM_FEATURE_AARCH64)) { 1510 arm_cpu_sve_finalize(cpu, &local_err); 1511 if (local_err != NULL) { 1512 error_propagate(errp, local_err); 1513 return; 1514 } 1515 1516 arm_cpu_sme_finalize(cpu, &local_err); 1517 if (local_err != NULL) { 1518 error_propagate(errp, local_err); 1519 return; 1520 } 1521 1522 arm_cpu_pauth_finalize(cpu, &local_err); 1523 if (local_err != NULL) { 1524 error_propagate(errp, local_err); 1525 return; 1526 } 1527 1528 arm_cpu_lpa2_finalize(cpu, &local_err); 1529 if (local_err != NULL) { 1530 error_propagate(errp, local_err); 1531 return; 1532 } 1533 } 1534 #endif 1535 1536 if (kvm_enabled()) { 1537 kvm_arm_steal_time_finalize(cpu, &local_err); 1538 if (local_err != NULL) { 1539 error_propagate(errp, local_err); 1540 return; 1541 } 1542 } 1543 } 1544 1545 static void arm_cpu_realizefn(DeviceState *dev, Error **errp) 1546 { 1547 CPUState *cs = CPU(dev); 1548 ARMCPU *cpu = ARM_CPU(dev); 1549 ARMCPUClass *acc = ARM_CPU_GET_CLASS(dev); 1550 CPUARMState *env = &cpu->env; 1551 int pagebits; 1552 Error *local_err = NULL; 1553 bool no_aa32 = false; 1554 1555 /* If we needed to query the host kernel for the CPU features 1556 * then it's possible that might have failed in the initfn, but 1557 * this is the first point where we can report it. 1558 */ 1559 if (cpu->host_cpu_probe_failed) { 1560 if (!kvm_enabled() && !hvf_enabled()) { 1561 error_setg(errp, "The 'host' CPU type can only be used with KVM or HVF"); 1562 } else { 1563 error_setg(errp, "Failed to retrieve host CPU features"); 1564 } 1565 return; 1566 } 1567 1568 #ifndef CONFIG_USER_ONLY 1569 /* The NVIC and M-profile CPU are two halves of a single piece of 1570 * hardware; trying to use one without the other is a command line 1571 * error and will result in segfaults if not caught here. 1572 */ 1573 if (arm_feature(env, ARM_FEATURE_M)) { 1574 if (!env->nvic) { 1575 error_setg(errp, "This board cannot be used with Cortex-M CPUs"); 1576 return; 1577 } 1578 } else { 1579 if (env->nvic) { 1580 error_setg(errp, "This board can only be used with Cortex-M CPUs"); 1581 return; 1582 } 1583 } 1584 1585 if (!tcg_enabled() && !qtest_enabled()) { 1586 /* 1587 * We assume that no accelerator except TCG (and the "not really an 1588 * accelerator" qtest) can handle these features, because Arm hardware 1589 * virtualization can't virtualize them. 1590 * 1591 * Catch all the cases which might cause us to create more than one 1592 * address space for the CPU (otherwise we will assert() later in 1593 * cpu_address_space_init()). 1594 */ 1595 if (arm_feature(env, ARM_FEATURE_M)) { 1596 error_setg(errp, 1597 "Cannot enable %s when using an M-profile guest CPU", 1598 current_accel_name()); 1599 return; 1600 } 1601 if (cpu->has_el3) { 1602 error_setg(errp, 1603 "Cannot enable %s when guest CPU has EL3 enabled", 1604 current_accel_name()); 1605 return; 1606 } 1607 if (cpu->tag_memory) { 1608 error_setg(errp, 1609 "Cannot enable %s when guest CPUs has MTE enabled", 1610 current_accel_name()); 1611 return; 1612 } 1613 } 1614 1615 { 1616 uint64_t scale; 1617 1618 if (arm_feature(env, ARM_FEATURE_GENERIC_TIMER)) { 1619 if (!cpu->gt_cntfrq_hz) { 1620 error_setg(errp, "Invalid CNTFRQ: %"PRId64"Hz", 1621 cpu->gt_cntfrq_hz); 1622 return; 1623 } 1624 scale = gt_cntfrq_period_ns(cpu); 1625 } else { 1626 scale = GTIMER_SCALE; 1627 } 1628 1629 cpu->gt_timer[GTIMER_PHYS] = timer_new(QEMU_CLOCK_VIRTUAL, scale, 1630 arm_gt_ptimer_cb, cpu); 1631 cpu->gt_timer[GTIMER_VIRT] = timer_new(QEMU_CLOCK_VIRTUAL, scale, 1632 arm_gt_vtimer_cb, cpu); 1633 cpu->gt_timer[GTIMER_HYP] = timer_new(QEMU_CLOCK_VIRTUAL, scale, 1634 arm_gt_htimer_cb, cpu); 1635 cpu->gt_timer[GTIMER_SEC] = timer_new(QEMU_CLOCK_VIRTUAL, scale, 1636 arm_gt_stimer_cb, cpu); 1637 cpu->gt_timer[GTIMER_HYPVIRT] = timer_new(QEMU_CLOCK_VIRTUAL, scale, 1638 arm_gt_hvtimer_cb, cpu); 1639 } 1640 #endif 1641 1642 cpu_exec_realizefn(cs, &local_err); 1643 if (local_err != NULL) { 1644 error_propagate(errp, local_err); 1645 return; 1646 } 1647 1648 arm_cpu_finalize_features(cpu, &local_err); 1649 if (local_err != NULL) { 1650 error_propagate(errp, local_err); 1651 return; 1652 } 1653 1654 if (arm_feature(env, ARM_FEATURE_AARCH64) && 1655 cpu->has_vfp != cpu->has_neon) { 1656 /* 1657 * This is an architectural requirement for AArch64; AArch32 is 1658 * more flexible and permits VFP-no-Neon and Neon-no-VFP. 1659 */ 1660 error_setg(errp, 1661 "AArch64 CPUs must have both VFP and Neon or neither"); 1662 return; 1663 } 1664 1665 if (!cpu->has_vfp) { 1666 uint64_t t; 1667 uint32_t u; 1668 1669 t = cpu->isar.id_aa64isar1; 1670 t = FIELD_DP64(t, ID_AA64ISAR1, JSCVT, 0); 1671 cpu->isar.id_aa64isar1 = t; 1672 1673 t = cpu->isar.id_aa64pfr0; 1674 t = FIELD_DP64(t, ID_AA64PFR0, FP, 0xf); 1675 cpu->isar.id_aa64pfr0 = t; 1676 1677 u = cpu->isar.id_isar6; 1678 u = FIELD_DP32(u, ID_ISAR6, JSCVT, 0); 1679 u = FIELD_DP32(u, ID_ISAR6, BF16, 0); 1680 cpu->isar.id_isar6 = u; 1681 1682 u = cpu->isar.mvfr0; 1683 u = FIELD_DP32(u, MVFR0, FPSP, 0); 1684 u = FIELD_DP32(u, MVFR0, FPDP, 0); 1685 u = FIELD_DP32(u, MVFR0, FPDIVIDE, 0); 1686 u = FIELD_DP32(u, MVFR0, FPSQRT, 0); 1687 u = FIELD_DP32(u, MVFR0, FPROUND, 0); 1688 if (!arm_feature(env, ARM_FEATURE_M)) { 1689 u = FIELD_DP32(u, MVFR0, FPTRAP, 0); 1690 u = FIELD_DP32(u, MVFR0, FPSHVEC, 0); 1691 } 1692 cpu->isar.mvfr0 = u; 1693 1694 u = cpu->isar.mvfr1; 1695 u = FIELD_DP32(u, MVFR1, FPFTZ, 0); 1696 u = FIELD_DP32(u, MVFR1, FPDNAN, 0); 1697 u = FIELD_DP32(u, MVFR1, FPHP, 0); 1698 if (arm_feature(env, ARM_FEATURE_M)) { 1699 u = FIELD_DP32(u, MVFR1, FP16, 0); 1700 } 1701 cpu->isar.mvfr1 = u; 1702 1703 u = cpu->isar.mvfr2; 1704 u = FIELD_DP32(u, MVFR2, FPMISC, 0); 1705 cpu->isar.mvfr2 = u; 1706 } 1707 1708 if (!cpu->has_neon) { 1709 uint64_t t; 1710 uint32_t u; 1711 1712 unset_feature(env, ARM_FEATURE_NEON); 1713 1714 t = cpu->isar.id_aa64isar0; 1715 t = FIELD_DP64(t, ID_AA64ISAR0, AES, 0); 1716 t = FIELD_DP64(t, ID_AA64ISAR0, SHA1, 0); 1717 t = FIELD_DP64(t, ID_AA64ISAR0, SHA2, 0); 1718 t = FIELD_DP64(t, ID_AA64ISAR0, SHA3, 0); 1719 t = FIELD_DP64(t, ID_AA64ISAR0, SM3, 0); 1720 t = FIELD_DP64(t, ID_AA64ISAR0, SM4, 0); 1721 t = FIELD_DP64(t, ID_AA64ISAR0, DP, 0); 1722 cpu->isar.id_aa64isar0 = t; 1723 1724 t = cpu->isar.id_aa64isar1; 1725 t = FIELD_DP64(t, ID_AA64ISAR1, FCMA, 0); 1726 t = FIELD_DP64(t, ID_AA64ISAR1, BF16, 0); 1727 t = FIELD_DP64(t, ID_AA64ISAR1, I8MM, 0); 1728 cpu->isar.id_aa64isar1 = t; 1729 1730 t = cpu->isar.id_aa64pfr0; 1731 t = FIELD_DP64(t, ID_AA64PFR0, ADVSIMD, 0xf); 1732 cpu->isar.id_aa64pfr0 = t; 1733 1734 u = cpu->isar.id_isar5; 1735 u = FIELD_DP32(u, ID_ISAR5, AES, 0); 1736 u = FIELD_DP32(u, ID_ISAR5, SHA1, 0); 1737 u = FIELD_DP32(u, ID_ISAR5, SHA2, 0); 1738 u = FIELD_DP32(u, ID_ISAR5, RDM, 0); 1739 u = FIELD_DP32(u, ID_ISAR5, VCMA, 0); 1740 cpu->isar.id_isar5 = u; 1741 1742 u = cpu->isar.id_isar6; 1743 u = FIELD_DP32(u, ID_ISAR6, DP, 0); 1744 u = FIELD_DP32(u, ID_ISAR6, FHM, 0); 1745 u = FIELD_DP32(u, ID_ISAR6, BF16, 0); 1746 u = FIELD_DP32(u, ID_ISAR6, I8MM, 0); 1747 cpu->isar.id_isar6 = u; 1748 1749 if (!arm_feature(env, ARM_FEATURE_M)) { 1750 u = cpu->isar.mvfr1; 1751 u = FIELD_DP32(u, MVFR1, SIMDLS, 0); 1752 u = FIELD_DP32(u, MVFR1, SIMDINT, 0); 1753 u = FIELD_DP32(u, MVFR1, SIMDSP, 0); 1754 u = FIELD_DP32(u, MVFR1, SIMDHP, 0); 1755 cpu->isar.mvfr1 = u; 1756 1757 u = cpu->isar.mvfr2; 1758 u = FIELD_DP32(u, MVFR2, SIMDMISC, 0); 1759 cpu->isar.mvfr2 = u; 1760 } 1761 } 1762 1763 if (!cpu->has_neon && !cpu->has_vfp) { 1764 uint64_t t; 1765 uint32_t u; 1766 1767 t = cpu->isar.id_aa64isar0; 1768 t = FIELD_DP64(t, ID_AA64ISAR0, FHM, 0); 1769 cpu->isar.id_aa64isar0 = t; 1770 1771 t = cpu->isar.id_aa64isar1; 1772 t = FIELD_DP64(t, ID_AA64ISAR1, FRINTTS, 0); 1773 cpu->isar.id_aa64isar1 = t; 1774 1775 u = cpu->isar.mvfr0; 1776 u = FIELD_DP32(u, MVFR0, SIMDREG, 0); 1777 cpu->isar.mvfr0 = u; 1778 1779 /* Despite the name, this field covers both VFP and Neon */ 1780 u = cpu->isar.mvfr1; 1781 u = FIELD_DP32(u, MVFR1, SIMDFMAC, 0); 1782 cpu->isar.mvfr1 = u; 1783 } 1784 1785 if (arm_feature(env, ARM_FEATURE_M) && !cpu->has_dsp) { 1786 uint32_t u; 1787 1788 unset_feature(env, ARM_FEATURE_THUMB_DSP); 1789 1790 u = cpu->isar.id_isar1; 1791 u = FIELD_DP32(u, ID_ISAR1, EXTEND, 1); 1792 cpu->isar.id_isar1 = u; 1793 1794 u = cpu->isar.id_isar2; 1795 u = FIELD_DP32(u, ID_ISAR2, MULTU, 1); 1796 u = FIELD_DP32(u, ID_ISAR2, MULTS, 1); 1797 cpu->isar.id_isar2 = u; 1798 1799 u = cpu->isar.id_isar3; 1800 u = FIELD_DP32(u, ID_ISAR3, SIMD, 1); 1801 u = FIELD_DP32(u, ID_ISAR3, SATURATE, 0); 1802 cpu->isar.id_isar3 = u; 1803 } 1804 1805 /* Some features automatically imply others: */ 1806 if (arm_feature(env, ARM_FEATURE_V8)) { 1807 if (arm_feature(env, ARM_FEATURE_M)) { 1808 set_feature(env, ARM_FEATURE_V7); 1809 } else { 1810 set_feature(env, ARM_FEATURE_V7VE); 1811 } 1812 } 1813 1814 /* 1815 * There exist AArch64 cpus without AArch32 support. When KVM 1816 * queries ID_ISAR0_EL1 on such a host, the value is UNKNOWN. 1817 * Similarly, we cannot check ID_AA64PFR0 without AArch64 support. 1818 * As a general principle, we also do not make ID register 1819 * consistency checks anywhere unless using TCG, because only 1820 * for TCG would a consistency-check failure be a QEMU bug. 1821 */ 1822 if (arm_feature(&cpu->env, ARM_FEATURE_AARCH64)) { 1823 no_aa32 = !cpu_isar_feature(aa64_aa32, cpu); 1824 } 1825 1826 if (arm_feature(env, ARM_FEATURE_V7VE)) { 1827 /* v7 Virtualization Extensions. In real hardware this implies 1828 * EL2 and also the presence of the Security Extensions. 1829 * For QEMU, for backwards-compatibility we implement some 1830 * CPUs or CPU configs which have no actual EL2 or EL3 but do 1831 * include the various other features that V7VE implies. 1832 * Presence of EL2 itself is ARM_FEATURE_EL2, and of the 1833 * Security Extensions is ARM_FEATURE_EL3. 1834 */ 1835 assert(!tcg_enabled() || no_aa32 || 1836 cpu_isar_feature(aa32_arm_div, cpu)); 1837 set_feature(env, ARM_FEATURE_LPAE); 1838 set_feature(env, ARM_FEATURE_V7); 1839 } 1840 if (arm_feature(env, ARM_FEATURE_V7)) { 1841 set_feature(env, ARM_FEATURE_VAPA); 1842 set_feature(env, ARM_FEATURE_THUMB2); 1843 set_feature(env, ARM_FEATURE_MPIDR); 1844 if (!arm_feature(env, ARM_FEATURE_M)) { 1845 set_feature(env, ARM_FEATURE_V6K); 1846 } else { 1847 set_feature(env, ARM_FEATURE_V6); 1848 } 1849 1850 /* Always define VBAR for V7 CPUs even if it doesn't exist in 1851 * non-EL3 configs. This is needed by some legacy boards. 1852 */ 1853 set_feature(env, ARM_FEATURE_VBAR); 1854 } 1855 if (arm_feature(env, ARM_FEATURE_V6K)) { 1856 set_feature(env, ARM_FEATURE_V6); 1857 set_feature(env, ARM_FEATURE_MVFR); 1858 } 1859 if (arm_feature(env, ARM_FEATURE_V6)) { 1860 set_feature(env, ARM_FEATURE_V5); 1861 if (!arm_feature(env, ARM_FEATURE_M)) { 1862 assert(!tcg_enabled() || no_aa32 || 1863 cpu_isar_feature(aa32_jazelle, cpu)); 1864 set_feature(env, ARM_FEATURE_AUXCR); 1865 } 1866 } 1867 if (arm_feature(env, ARM_FEATURE_V5)) { 1868 set_feature(env, ARM_FEATURE_V4T); 1869 } 1870 if (arm_feature(env, ARM_FEATURE_LPAE)) { 1871 set_feature(env, ARM_FEATURE_V7MP); 1872 } 1873 if (arm_feature(env, ARM_FEATURE_CBAR_RO)) { 1874 set_feature(env, ARM_FEATURE_CBAR); 1875 } 1876 if (arm_feature(env, ARM_FEATURE_THUMB2) && 1877 !arm_feature(env, ARM_FEATURE_M)) { 1878 set_feature(env, ARM_FEATURE_THUMB_DSP); 1879 } 1880 1881 /* 1882 * We rely on no XScale CPU having VFP so we can use the same bits in the 1883 * TB flags field for VECSTRIDE and XSCALE_CPAR. 1884 */ 1885 assert(arm_feature(&cpu->env, ARM_FEATURE_AARCH64) || 1886 !cpu_isar_feature(aa32_vfp_simd, cpu) || 1887 !arm_feature(env, ARM_FEATURE_XSCALE)); 1888 1889 if (arm_feature(env, ARM_FEATURE_V7) && 1890 !arm_feature(env, ARM_FEATURE_M) && 1891 !arm_feature(env, ARM_FEATURE_PMSA)) { 1892 /* v7VMSA drops support for the old ARMv5 tiny pages, so we 1893 * can use 4K pages. 1894 */ 1895 pagebits = 12; 1896 } else { 1897 /* For CPUs which might have tiny 1K pages, or which have an 1898 * MPU and might have small region sizes, stick with 1K pages. 1899 */ 1900 pagebits = 10; 1901 } 1902 if (!set_preferred_target_page_bits(pagebits)) { 1903 /* This can only ever happen for hotplugging a CPU, or if 1904 * the board code incorrectly creates a CPU which it has 1905 * promised via minimum_page_size that it will not. 1906 */ 1907 error_setg(errp, "This CPU requires a smaller page size than the " 1908 "system is using"); 1909 return; 1910 } 1911 1912 /* This cpu-id-to-MPIDR affinity is used only for TCG; KVM will override it. 1913 * We don't support setting cluster ID ([16..23]) (known as Aff2 1914 * in later ARM ARM versions), or any of the higher affinity level fields, 1915 * so these bits always RAZ. 1916 */ 1917 if (cpu->mp_affinity == ARM64_AFFINITY_INVALID) { 1918 cpu->mp_affinity = arm_cpu_mp_affinity(cs->cpu_index, 1919 ARM_DEFAULT_CPUS_PER_CLUSTER); 1920 } 1921 1922 if (cpu->reset_hivecs) { 1923 cpu->reset_sctlr |= (1 << 13); 1924 } 1925 1926 if (cpu->cfgend) { 1927 if (arm_feature(&cpu->env, ARM_FEATURE_V7)) { 1928 cpu->reset_sctlr |= SCTLR_EE; 1929 } else { 1930 cpu->reset_sctlr |= SCTLR_B; 1931 } 1932 } 1933 1934 if (!arm_feature(env, ARM_FEATURE_M) && !cpu->has_el3) { 1935 /* If the has_el3 CPU property is disabled then we need to disable the 1936 * feature. 1937 */ 1938 unset_feature(env, ARM_FEATURE_EL3); 1939 1940 /* 1941 * Disable the security extension feature bits in the processor 1942 * feature registers as well. 1943 */ 1944 cpu->isar.id_pfr1 = FIELD_DP32(cpu->isar.id_pfr1, ID_PFR1, SECURITY, 0); 1945 cpu->isar.id_dfr0 = FIELD_DP32(cpu->isar.id_dfr0, ID_DFR0, COPSDBG, 0); 1946 cpu->isar.id_aa64pfr0 = FIELD_DP64(cpu->isar.id_aa64pfr0, 1947 ID_AA64PFR0, EL3, 0); 1948 } 1949 1950 if (!cpu->has_el2) { 1951 unset_feature(env, ARM_FEATURE_EL2); 1952 } 1953 1954 if (!cpu->has_pmu) { 1955 unset_feature(env, ARM_FEATURE_PMU); 1956 } 1957 if (arm_feature(env, ARM_FEATURE_PMU)) { 1958 pmu_init(cpu); 1959 1960 if (!kvm_enabled()) { 1961 arm_register_pre_el_change_hook(cpu, &pmu_pre_el_change, 0); 1962 arm_register_el_change_hook(cpu, &pmu_post_el_change, 0); 1963 } 1964 1965 #ifndef CONFIG_USER_ONLY 1966 cpu->pmu_timer = timer_new_ns(QEMU_CLOCK_VIRTUAL, arm_pmu_timer_cb, 1967 cpu); 1968 #endif 1969 } else { 1970 cpu->isar.id_aa64dfr0 = 1971 FIELD_DP64(cpu->isar.id_aa64dfr0, ID_AA64DFR0, PMUVER, 0); 1972 cpu->isar.id_dfr0 = FIELD_DP32(cpu->isar.id_dfr0, ID_DFR0, PERFMON, 0); 1973 cpu->pmceid0 = 0; 1974 cpu->pmceid1 = 0; 1975 } 1976 1977 if (!arm_feature(env, ARM_FEATURE_EL2)) { 1978 /* 1979 * Disable the hypervisor feature bits in the processor feature 1980 * registers if we don't have EL2. 1981 */ 1982 cpu->isar.id_aa64pfr0 = FIELD_DP64(cpu->isar.id_aa64pfr0, 1983 ID_AA64PFR0, EL2, 0); 1984 cpu->isar.id_pfr1 = FIELD_DP32(cpu->isar.id_pfr1, 1985 ID_PFR1, VIRTUALIZATION, 0); 1986 } 1987 1988 #ifndef CONFIG_USER_ONLY 1989 if (cpu->tag_memory == NULL && cpu_isar_feature(aa64_mte, cpu)) { 1990 /* 1991 * Disable the MTE feature bits if we do not have tag-memory 1992 * provided by the machine. 1993 */ 1994 cpu->isar.id_aa64pfr1 = 1995 FIELD_DP64(cpu->isar.id_aa64pfr1, ID_AA64PFR1, MTE, 0); 1996 } 1997 #endif 1998 1999 if (tcg_enabled()) { 2000 /* 2001 * Don't report the Statistical Profiling Extension in the ID 2002 * registers, because TCG doesn't implement it yet (not even a 2003 * minimal stub version) and guests will fall over when they 2004 * try to access the non-existent system registers for it. 2005 */ 2006 cpu->isar.id_aa64dfr0 = 2007 FIELD_DP64(cpu->isar.id_aa64dfr0, ID_AA64DFR0, PMSVER, 0); 2008 } 2009 2010 /* MPU can be configured out of a PMSA CPU either by setting has-mpu 2011 * to false or by setting pmsav7-dregion to 0. 2012 */ 2013 if (!cpu->has_mpu || cpu->pmsav7_dregion == 0) { 2014 cpu->has_mpu = false; 2015 cpu->pmsav7_dregion = 0; 2016 cpu->pmsav8r_hdregion = 0; 2017 } 2018 2019 if (arm_feature(env, ARM_FEATURE_PMSA) && 2020 arm_feature(env, ARM_FEATURE_V7)) { 2021 uint32_t nr = cpu->pmsav7_dregion; 2022 2023 if (nr > 0xff) { 2024 error_setg(errp, "PMSAv7 MPU #regions invalid %" PRIu32, nr); 2025 return; 2026 } 2027 2028 if (nr) { 2029 if (arm_feature(env, ARM_FEATURE_V8)) { 2030 /* PMSAv8 */ 2031 env->pmsav8.rbar[M_REG_NS] = g_new0(uint32_t, nr); 2032 env->pmsav8.rlar[M_REG_NS] = g_new0(uint32_t, nr); 2033 if (arm_feature(env, ARM_FEATURE_M_SECURITY)) { 2034 env->pmsav8.rbar[M_REG_S] = g_new0(uint32_t, nr); 2035 env->pmsav8.rlar[M_REG_S] = g_new0(uint32_t, nr); 2036 } 2037 } else { 2038 env->pmsav7.drbar = g_new0(uint32_t, nr); 2039 env->pmsav7.drsr = g_new0(uint32_t, nr); 2040 env->pmsav7.dracr = g_new0(uint32_t, nr); 2041 } 2042 } 2043 2044 if (cpu->pmsav8r_hdregion > 0xff) { 2045 error_setg(errp, "PMSAv8 MPU EL2 #regions invalid %" PRIu32, 2046 cpu->pmsav8r_hdregion); 2047 return; 2048 } 2049 2050 if (cpu->pmsav8r_hdregion) { 2051 env->pmsav8.hprbar = g_new0(uint32_t, 2052 cpu->pmsav8r_hdregion); 2053 env->pmsav8.hprlar = g_new0(uint32_t, 2054 cpu->pmsav8r_hdregion); 2055 } 2056 } 2057 2058 if (arm_feature(env, ARM_FEATURE_M_SECURITY)) { 2059 uint32_t nr = cpu->sau_sregion; 2060 2061 if (nr > 0xff) { 2062 error_setg(errp, "v8M SAU #regions invalid %" PRIu32, nr); 2063 return; 2064 } 2065 2066 if (nr) { 2067 env->sau.rbar = g_new0(uint32_t, nr); 2068 env->sau.rlar = g_new0(uint32_t, nr); 2069 } 2070 } 2071 2072 if (arm_feature(env, ARM_FEATURE_EL3)) { 2073 set_feature(env, ARM_FEATURE_VBAR); 2074 } 2075 2076 register_cp_regs_for_features(cpu); 2077 arm_cpu_register_gdb_regs_for_features(cpu); 2078 2079 init_cpreg_list(cpu); 2080 2081 #ifndef CONFIG_USER_ONLY 2082 MachineState *ms = MACHINE(qdev_get_machine()); 2083 unsigned int smp_cpus = ms->smp.cpus; 2084 bool has_secure = cpu->has_el3 || arm_feature(env, ARM_FEATURE_M_SECURITY); 2085 2086 /* 2087 * We must set cs->num_ases to the final value before 2088 * the first call to cpu_address_space_init. 2089 */ 2090 if (cpu->tag_memory != NULL) { 2091 cs->num_ases = 3 + has_secure; 2092 } else { 2093 cs->num_ases = 1 + has_secure; 2094 } 2095 2096 if (has_secure) { 2097 if (!cpu->secure_memory) { 2098 cpu->secure_memory = cs->memory; 2099 } 2100 cpu_address_space_init(cs, ARMASIdx_S, "cpu-secure-memory", 2101 cpu->secure_memory); 2102 } 2103 2104 if (cpu->tag_memory != NULL) { 2105 cpu_address_space_init(cs, ARMASIdx_TagNS, "cpu-tag-memory", 2106 cpu->tag_memory); 2107 if (has_secure) { 2108 cpu_address_space_init(cs, ARMASIdx_TagS, "cpu-tag-memory", 2109 cpu->secure_tag_memory); 2110 } 2111 } 2112 2113 cpu_address_space_init(cs, ARMASIdx_NS, "cpu-memory", cs->memory); 2114 2115 /* No core_count specified, default to smp_cpus. */ 2116 if (cpu->core_count == -1) { 2117 cpu->core_count = smp_cpus; 2118 } 2119 #endif 2120 2121 if (tcg_enabled()) { 2122 int dcz_blocklen = 4 << cpu->dcz_blocksize; 2123 2124 /* 2125 * We only support DCZ blocklen that fits on one page. 2126 * 2127 * Architectually this is always true. However TARGET_PAGE_SIZE 2128 * is variable and, for compatibility with -machine virt-2.7, 2129 * is only 1KiB, as an artifact of legacy ARMv5 subpage support. 2130 * But even then, while the largest architectural DCZ blocklen 2131 * is 2KiB, no cpu actually uses such a large blocklen. 2132 */ 2133 assert(dcz_blocklen <= TARGET_PAGE_SIZE); 2134 2135 /* 2136 * We only support DCZ blocksize >= 2*TAG_GRANULE, which is to say 2137 * both nibbles of each byte storing tag data may be written at once. 2138 * Since TAG_GRANULE is 16, this means that blocklen must be >= 32. 2139 */ 2140 if (cpu_isar_feature(aa64_mte, cpu)) { 2141 assert(dcz_blocklen >= 2 * TAG_GRANULE); 2142 } 2143 } 2144 2145 qemu_init_vcpu(cs); 2146 cpu_reset(cs); 2147 2148 acc->parent_realize(dev, errp); 2149 } 2150 2151 static ObjectClass *arm_cpu_class_by_name(const char *cpu_model) 2152 { 2153 ObjectClass *oc; 2154 char *typename; 2155 char **cpuname; 2156 const char *cpunamestr; 2157 2158 cpuname = g_strsplit(cpu_model, ",", 1); 2159 cpunamestr = cpuname[0]; 2160 #ifdef CONFIG_USER_ONLY 2161 /* For backwards compatibility usermode emulation allows "-cpu any", 2162 * which has the same semantics as "-cpu max". 2163 */ 2164 if (!strcmp(cpunamestr, "any")) { 2165 cpunamestr = "max"; 2166 } 2167 #endif 2168 typename = g_strdup_printf(ARM_CPU_TYPE_NAME("%s"), cpunamestr); 2169 oc = object_class_by_name(typename); 2170 g_strfreev(cpuname); 2171 g_free(typename); 2172 if (!oc || !object_class_dynamic_cast(oc, TYPE_ARM_CPU) || 2173 object_class_is_abstract(oc)) { 2174 return NULL; 2175 } 2176 return oc; 2177 } 2178 2179 static Property arm_cpu_properties[] = { 2180 DEFINE_PROP_UINT64("midr", ARMCPU, midr, 0), 2181 DEFINE_PROP_UINT64("mp-affinity", ARMCPU, 2182 mp_affinity, ARM64_AFFINITY_INVALID), 2183 DEFINE_PROP_INT32("node-id", ARMCPU, node_id, CPU_UNSET_NUMA_NODE_ID), 2184 DEFINE_PROP_INT32("core-count", ARMCPU, core_count, -1), 2185 DEFINE_PROP_END_OF_LIST() 2186 }; 2187 2188 static gchar *arm_gdb_arch_name(CPUState *cs) 2189 { 2190 ARMCPU *cpu = ARM_CPU(cs); 2191 CPUARMState *env = &cpu->env; 2192 2193 if (arm_feature(env, ARM_FEATURE_IWMMXT)) { 2194 return g_strdup("iwmmxt"); 2195 } 2196 return g_strdup("arm"); 2197 } 2198 2199 #ifndef CONFIG_USER_ONLY 2200 #include "hw/core/sysemu-cpu-ops.h" 2201 2202 static const struct SysemuCPUOps arm_sysemu_ops = { 2203 .get_phys_page_attrs_debug = arm_cpu_get_phys_page_attrs_debug, 2204 .asidx_from_attrs = arm_asidx_from_attrs, 2205 .write_elf32_note = arm_cpu_write_elf32_note, 2206 .write_elf64_note = arm_cpu_write_elf64_note, 2207 .virtio_is_big_endian = arm_cpu_virtio_is_big_endian, 2208 .legacy_vmsd = &vmstate_arm_cpu, 2209 }; 2210 #endif 2211 2212 #ifdef CONFIG_TCG 2213 static const struct TCGCPUOps arm_tcg_ops = { 2214 .initialize = arm_translate_init, 2215 .synchronize_from_tb = arm_cpu_synchronize_from_tb, 2216 .debug_excp_handler = arm_debug_excp_handler, 2217 .restore_state_to_opc = arm_restore_state_to_opc, 2218 2219 #ifdef CONFIG_USER_ONLY 2220 .record_sigsegv = arm_cpu_record_sigsegv, 2221 .record_sigbus = arm_cpu_record_sigbus, 2222 #else 2223 .tlb_fill = arm_cpu_tlb_fill, 2224 .cpu_exec_interrupt = arm_cpu_exec_interrupt, 2225 .do_interrupt = arm_cpu_do_interrupt, 2226 .do_transaction_failed = arm_cpu_do_transaction_failed, 2227 .do_unaligned_access = arm_cpu_do_unaligned_access, 2228 .adjust_watchpoint_address = arm_adjust_watchpoint_address, 2229 .debug_check_watchpoint = arm_debug_check_watchpoint, 2230 .debug_check_breakpoint = arm_debug_check_breakpoint, 2231 #endif /* !CONFIG_USER_ONLY */ 2232 }; 2233 #endif /* CONFIG_TCG */ 2234 2235 static void arm_cpu_class_init(ObjectClass *oc, void *data) 2236 { 2237 ARMCPUClass *acc = ARM_CPU_CLASS(oc); 2238 CPUClass *cc = CPU_CLASS(acc); 2239 DeviceClass *dc = DEVICE_CLASS(oc); 2240 ResettableClass *rc = RESETTABLE_CLASS(oc); 2241 2242 device_class_set_parent_realize(dc, arm_cpu_realizefn, 2243 &acc->parent_realize); 2244 2245 device_class_set_props(dc, arm_cpu_properties); 2246 2247 resettable_class_set_parent_phases(rc, NULL, arm_cpu_reset_hold, NULL, 2248 &acc->parent_phases); 2249 2250 cc->class_by_name = arm_cpu_class_by_name; 2251 cc->has_work = arm_cpu_has_work; 2252 cc->dump_state = arm_cpu_dump_state; 2253 cc->set_pc = arm_cpu_set_pc; 2254 cc->get_pc = arm_cpu_get_pc; 2255 cc->gdb_read_register = arm_cpu_gdb_read_register; 2256 cc->gdb_write_register = arm_cpu_gdb_write_register; 2257 #ifndef CONFIG_USER_ONLY 2258 cc->sysemu_ops = &arm_sysemu_ops; 2259 #endif 2260 cc->gdb_num_core_regs = 26; 2261 cc->gdb_core_xml_file = "arm-core.xml"; 2262 cc->gdb_arch_name = arm_gdb_arch_name; 2263 cc->gdb_get_dynamic_xml = arm_gdb_get_dynamic_xml; 2264 cc->gdb_stop_before_watchpoint = true; 2265 cc->disas_set_info = arm_disas_set_info; 2266 2267 #ifdef CONFIG_TCG 2268 cc->tcg_ops = &arm_tcg_ops; 2269 #endif /* CONFIG_TCG */ 2270 } 2271 2272 static void arm_cpu_instance_init(Object *obj) 2273 { 2274 ARMCPUClass *acc = ARM_CPU_GET_CLASS(obj); 2275 2276 acc->info->initfn(obj); 2277 arm_cpu_post_init(obj); 2278 } 2279 2280 static void cpu_register_class_init(ObjectClass *oc, void *data) 2281 { 2282 ARMCPUClass *acc = ARM_CPU_CLASS(oc); 2283 2284 acc->info = data; 2285 } 2286 2287 void arm_cpu_register(const ARMCPUInfo *info) 2288 { 2289 TypeInfo type_info = { 2290 .parent = TYPE_ARM_CPU, 2291 .instance_size = sizeof(ARMCPU), 2292 .instance_align = __alignof__(ARMCPU), 2293 .instance_init = arm_cpu_instance_init, 2294 .class_size = sizeof(ARMCPUClass), 2295 .class_init = info->class_init ?: cpu_register_class_init, 2296 .class_data = (void *)info, 2297 }; 2298 2299 type_info.name = g_strdup_printf("%s-" TYPE_ARM_CPU, info->name); 2300 type_register(&type_info); 2301 g_free((void *)type_info.name); 2302 } 2303 2304 static const TypeInfo arm_cpu_type_info = { 2305 .name = TYPE_ARM_CPU, 2306 .parent = TYPE_CPU, 2307 .instance_size = sizeof(ARMCPU), 2308 .instance_align = __alignof__(ARMCPU), 2309 .instance_init = arm_cpu_initfn, 2310 .instance_finalize = arm_cpu_finalizefn, 2311 .abstract = true, 2312 .class_size = sizeof(ARMCPUClass), 2313 .class_init = arm_cpu_class_init, 2314 }; 2315 2316 static void arm_cpu_register_types(void) 2317 { 2318 type_register_static(&arm_cpu_type_info); 2319 } 2320 2321 type_init(arm_cpu_register_types) 2322