1 /* 2 * QEMU ARM CPU 3 * 4 * Copyright (c) 2012 SUSE LINUX Products GmbH 5 * 6 * This program is free software; you can redistribute it and/or 7 * modify it under the terms of the GNU General Public License 8 * as published by the Free Software Foundation; either version 2 9 * of the License, or (at your option) any later version. 10 * 11 * This program is distributed in the hope that it will be useful, 12 * but WITHOUT ANY WARRANTY; without even the implied warranty of 13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 14 * GNU General Public License for more details. 15 * 16 * You should have received a copy of the GNU General Public License 17 * along with this program; if not, see 18 * <http://www.gnu.org/licenses/gpl-2.0.html> 19 */ 20 21 #include "qemu/osdep.h" 22 #include "qemu/error-report.h" 23 #include "qapi/error.h" 24 #include "cpu.h" 25 #include "internals.h" 26 #include "qemu-common.h" 27 #include "exec/exec-all.h" 28 #include "hw/qdev-properties.h" 29 #if !defined(CONFIG_USER_ONLY) 30 #include "hw/loader.h" 31 #endif 32 #include "hw/arm/arm.h" 33 #include "sysemu/sysemu.h" 34 #include "sysemu/hw_accel.h" 35 #include "kvm_arm.h" 36 37 static void arm_cpu_set_pc(CPUState *cs, vaddr value) 38 { 39 ARMCPU *cpu = ARM_CPU(cs); 40 41 cpu->env.regs[15] = value; 42 } 43 44 static bool arm_cpu_has_work(CPUState *cs) 45 { 46 ARMCPU *cpu = ARM_CPU(cs); 47 48 return (cpu->power_state != PSCI_OFF) 49 && cs->interrupt_request & 50 (CPU_INTERRUPT_FIQ | CPU_INTERRUPT_HARD 51 | CPU_INTERRUPT_VFIQ | CPU_INTERRUPT_VIRQ 52 | CPU_INTERRUPT_EXITTB); 53 } 54 55 void arm_register_el_change_hook(ARMCPU *cpu, ARMELChangeHook *hook, 56 void *opaque) 57 { 58 /* We currently only support registering a single hook function */ 59 assert(!cpu->el_change_hook); 60 cpu->el_change_hook = hook; 61 cpu->el_change_hook_opaque = opaque; 62 } 63 64 static void cp_reg_reset(gpointer key, gpointer value, gpointer opaque) 65 { 66 /* Reset a single ARMCPRegInfo register */ 67 ARMCPRegInfo *ri = value; 68 ARMCPU *cpu = opaque; 69 70 if (ri->type & (ARM_CP_SPECIAL | ARM_CP_ALIAS)) { 71 return; 72 } 73 74 if (ri->resetfn) { 75 ri->resetfn(&cpu->env, ri); 76 return; 77 } 78 79 /* A zero offset is never possible as it would be regs[0] 80 * so we use it to indicate that reset is being handled elsewhere. 81 * This is basically only used for fields in non-core coprocessors 82 * (like the pxa2xx ones). 83 */ 84 if (!ri->fieldoffset) { 85 return; 86 } 87 88 if (cpreg_field_is_64bit(ri)) { 89 CPREG_FIELD64(&cpu->env, ri) = ri->resetvalue; 90 } else { 91 CPREG_FIELD32(&cpu->env, ri) = ri->resetvalue; 92 } 93 } 94 95 static void cp_reg_check_reset(gpointer key, gpointer value, gpointer opaque) 96 { 97 /* Purely an assertion check: we've already done reset once, 98 * so now check that running the reset for the cpreg doesn't 99 * change its value. This traps bugs where two different cpregs 100 * both try to reset the same state field but to different values. 101 */ 102 ARMCPRegInfo *ri = value; 103 ARMCPU *cpu = opaque; 104 uint64_t oldvalue, newvalue; 105 106 if (ri->type & (ARM_CP_SPECIAL | ARM_CP_ALIAS | ARM_CP_NO_RAW)) { 107 return; 108 } 109 110 oldvalue = read_raw_cp_reg(&cpu->env, ri); 111 cp_reg_reset(key, value, opaque); 112 newvalue = read_raw_cp_reg(&cpu->env, ri); 113 assert(oldvalue == newvalue); 114 } 115 116 /* CPUClass::reset() */ 117 static void arm_cpu_reset(CPUState *s) 118 { 119 ARMCPU *cpu = ARM_CPU(s); 120 ARMCPUClass *acc = ARM_CPU_GET_CLASS(cpu); 121 CPUARMState *env = &cpu->env; 122 123 acc->parent_reset(s); 124 125 memset(env, 0, offsetof(CPUARMState, end_reset_fields)); 126 127 g_hash_table_foreach(cpu->cp_regs, cp_reg_reset, cpu); 128 g_hash_table_foreach(cpu->cp_regs, cp_reg_check_reset, cpu); 129 130 env->vfp.xregs[ARM_VFP_FPSID] = cpu->reset_fpsid; 131 env->vfp.xregs[ARM_VFP_MVFR0] = cpu->mvfr0; 132 env->vfp.xregs[ARM_VFP_MVFR1] = cpu->mvfr1; 133 env->vfp.xregs[ARM_VFP_MVFR2] = cpu->mvfr2; 134 135 cpu->power_state = cpu->start_powered_off ? PSCI_OFF : PSCI_ON; 136 s->halted = cpu->start_powered_off; 137 138 if (arm_feature(env, ARM_FEATURE_IWMMXT)) { 139 env->iwmmxt.cregs[ARM_IWMMXT_wCID] = 0x69051000 | 'Q'; 140 } 141 142 if (arm_feature(env, ARM_FEATURE_AARCH64)) { 143 /* 64 bit CPUs always start in 64 bit mode */ 144 env->aarch64 = 1; 145 #if defined(CONFIG_USER_ONLY) 146 env->pstate = PSTATE_MODE_EL0t; 147 /* Userspace expects access to DC ZVA, CTL_EL0 and the cache ops */ 148 env->cp15.sctlr_el[1] |= SCTLR_UCT | SCTLR_UCI | SCTLR_DZE; 149 /* and to the FP/Neon instructions */ 150 env->cp15.cpacr_el1 = deposit64(env->cp15.cpacr_el1, 20, 2, 3); 151 #else 152 /* Reset into the highest available EL */ 153 if (arm_feature(env, ARM_FEATURE_EL3)) { 154 env->pstate = PSTATE_MODE_EL3h; 155 } else if (arm_feature(env, ARM_FEATURE_EL2)) { 156 env->pstate = PSTATE_MODE_EL2h; 157 } else { 158 env->pstate = PSTATE_MODE_EL1h; 159 } 160 env->pc = cpu->rvbar; 161 #endif 162 } else { 163 #if defined(CONFIG_USER_ONLY) 164 /* Userspace expects access to cp10 and cp11 for FP/Neon */ 165 env->cp15.cpacr_el1 = deposit64(env->cp15.cpacr_el1, 20, 4, 0xf); 166 #endif 167 } 168 169 #if defined(CONFIG_USER_ONLY) 170 env->uncached_cpsr = ARM_CPU_MODE_USR; 171 /* For user mode we must enable access to coprocessors */ 172 env->vfp.xregs[ARM_VFP_FPEXC] = 1 << 30; 173 if (arm_feature(env, ARM_FEATURE_IWMMXT)) { 174 env->cp15.c15_cpar = 3; 175 } else if (arm_feature(env, ARM_FEATURE_XSCALE)) { 176 env->cp15.c15_cpar = 1; 177 } 178 #else 179 /* SVC mode with interrupts disabled. */ 180 env->uncached_cpsr = ARM_CPU_MODE_SVC; 181 env->daif = PSTATE_D | PSTATE_A | PSTATE_I | PSTATE_F; 182 183 if (arm_feature(env, ARM_FEATURE_M)) { 184 uint32_t initial_msp; /* Loaded from 0x0 */ 185 uint32_t initial_pc; /* Loaded from 0x4 */ 186 uint8_t *rom; 187 188 /* For M profile we store FAULTMASK and PRIMASK in the 189 * PSTATE F and I bits; these are both clear at reset. 190 */ 191 env->daif &= ~(PSTATE_I | PSTATE_F); 192 193 /* The reset value of this bit is IMPDEF, but ARM recommends 194 * that it resets to 1, so QEMU always does that rather than making 195 * it dependent on CPU model. 196 */ 197 env->v7m.ccr = R_V7M_CCR_STKALIGN_MASK; 198 199 /* Unlike A/R profile, M profile defines the reset LR value */ 200 env->regs[14] = 0xffffffff; 201 202 /* Load the initial SP and PC from the vector table at address 0 */ 203 rom = rom_ptr(0); 204 if (rom) { 205 /* Address zero is covered by ROM which hasn't yet been 206 * copied into physical memory. 207 */ 208 initial_msp = ldl_p(rom); 209 initial_pc = ldl_p(rom + 4); 210 } else { 211 /* Address zero not covered by a ROM blob, or the ROM blob 212 * is in non-modifiable memory and this is a second reset after 213 * it got copied into memory. In the latter case, rom_ptr 214 * will return a NULL pointer and we should use ldl_phys instead. 215 */ 216 initial_msp = ldl_phys(s->as, 0); 217 initial_pc = ldl_phys(s->as, 4); 218 } 219 220 env->regs[13] = initial_msp & 0xFFFFFFFC; 221 env->regs[15] = initial_pc & ~1; 222 env->thumb = initial_pc & 1; 223 } 224 225 /* AArch32 has a hard highvec setting of 0xFFFF0000. If we are currently 226 * executing as AArch32 then check if highvecs are enabled and 227 * adjust the PC accordingly. 228 */ 229 if (A32_BANKED_CURRENT_REG_GET(env, sctlr) & SCTLR_V) { 230 env->regs[15] = 0xFFFF0000; 231 } 232 233 env->vfp.xregs[ARM_VFP_FPEXC] = 0; 234 #endif 235 236 if (arm_feature(env, ARM_FEATURE_PMSA) && 237 arm_feature(env, ARM_FEATURE_V7)) { 238 if (cpu->pmsav7_dregion > 0) { 239 memset(env->pmsav7.drbar, 0, 240 sizeof(*env->pmsav7.drbar) * cpu->pmsav7_dregion); 241 memset(env->pmsav7.drsr, 0, 242 sizeof(*env->pmsav7.drsr) * cpu->pmsav7_dregion); 243 memset(env->pmsav7.dracr, 0, 244 sizeof(*env->pmsav7.dracr) * cpu->pmsav7_dregion); 245 } 246 env->pmsav7.rnr = 0; 247 } 248 249 set_flush_to_zero(1, &env->vfp.standard_fp_status); 250 set_flush_inputs_to_zero(1, &env->vfp.standard_fp_status); 251 set_default_nan_mode(1, &env->vfp.standard_fp_status); 252 set_float_detect_tininess(float_tininess_before_rounding, 253 &env->vfp.fp_status); 254 set_float_detect_tininess(float_tininess_before_rounding, 255 &env->vfp.standard_fp_status); 256 #ifndef CONFIG_USER_ONLY 257 if (kvm_enabled()) { 258 kvm_arm_reset_vcpu(cpu); 259 } 260 #endif 261 262 hw_breakpoint_update_all(cpu); 263 hw_watchpoint_update_all(cpu); 264 } 265 266 bool arm_cpu_exec_interrupt(CPUState *cs, int interrupt_request) 267 { 268 CPUClass *cc = CPU_GET_CLASS(cs); 269 CPUARMState *env = cs->env_ptr; 270 uint32_t cur_el = arm_current_el(env); 271 bool secure = arm_is_secure(env); 272 uint32_t target_el; 273 uint32_t excp_idx; 274 bool ret = false; 275 276 if (interrupt_request & CPU_INTERRUPT_FIQ) { 277 excp_idx = EXCP_FIQ; 278 target_el = arm_phys_excp_target_el(cs, excp_idx, cur_el, secure); 279 if (arm_excp_unmasked(cs, excp_idx, target_el)) { 280 cs->exception_index = excp_idx; 281 env->exception.target_el = target_el; 282 cc->do_interrupt(cs); 283 ret = true; 284 } 285 } 286 if (interrupt_request & CPU_INTERRUPT_HARD) { 287 excp_idx = EXCP_IRQ; 288 target_el = arm_phys_excp_target_el(cs, excp_idx, cur_el, secure); 289 if (arm_excp_unmasked(cs, excp_idx, target_el)) { 290 cs->exception_index = excp_idx; 291 env->exception.target_el = target_el; 292 cc->do_interrupt(cs); 293 ret = true; 294 } 295 } 296 if (interrupt_request & CPU_INTERRUPT_VIRQ) { 297 excp_idx = EXCP_VIRQ; 298 target_el = 1; 299 if (arm_excp_unmasked(cs, excp_idx, target_el)) { 300 cs->exception_index = excp_idx; 301 env->exception.target_el = target_el; 302 cc->do_interrupt(cs); 303 ret = true; 304 } 305 } 306 if (interrupt_request & CPU_INTERRUPT_VFIQ) { 307 excp_idx = EXCP_VFIQ; 308 target_el = 1; 309 if (arm_excp_unmasked(cs, excp_idx, target_el)) { 310 cs->exception_index = excp_idx; 311 env->exception.target_el = target_el; 312 cc->do_interrupt(cs); 313 ret = true; 314 } 315 } 316 317 return ret; 318 } 319 320 #if !defined(CONFIG_USER_ONLY) || !defined(TARGET_AARCH64) 321 static bool arm_v7m_cpu_exec_interrupt(CPUState *cs, int interrupt_request) 322 { 323 CPUClass *cc = CPU_GET_CLASS(cs); 324 ARMCPU *cpu = ARM_CPU(cs); 325 CPUARMState *env = &cpu->env; 326 bool ret = false; 327 328 /* ARMv7-M interrupt masking works differently than -A or -R. 329 * There is no FIQ/IRQ distinction. Instead of I and F bits 330 * masking FIQ and IRQ interrupts, an exception is taken only 331 * if it is higher priority than the current execution priority 332 * (which depends on state like BASEPRI, FAULTMASK and the 333 * currently active exception). 334 */ 335 if (interrupt_request & CPU_INTERRUPT_HARD 336 && (armv7m_nvic_can_take_pending_exception(env->nvic))) { 337 cs->exception_index = EXCP_IRQ; 338 cc->do_interrupt(cs); 339 ret = true; 340 } 341 return ret; 342 } 343 #endif 344 345 #ifndef CONFIG_USER_ONLY 346 static void arm_cpu_set_irq(void *opaque, int irq, int level) 347 { 348 ARMCPU *cpu = opaque; 349 CPUARMState *env = &cpu->env; 350 CPUState *cs = CPU(cpu); 351 static const int mask[] = { 352 [ARM_CPU_IRQ] = CPU_INTERRUPT_HARD, 353 [ARM_CPU_FIQ] = CPU_INTERRUPT_FIQ, 354 [ARM_CPU_VIRQ] = CPU_INTERRUPT_VIRQ, 355 [ARM_CPU_VFIQ] = CPU_INTERRUPT_VFIQ 356 }; 357 358 switch (irq) { 359 case ARM_CPU_VIRQ: 360 case ARM_CPU_VFIQ: 361 assert(arm_feature(env, ARM_FEATURE_EL2)); 362 /* fall through */ 363 case ARM_CPU_IRQ: 364 case ARM_CPU_FIQ: 365 if (level) { 366 cpu_interrupt(cs, mask[irq]); 367 } else { 368 cpu_reset_interrupt(cs, mask[irq]); 369 } 370 break; 371 default: 372 g_assert_not_reached(); 373 } 374 } 375 376 static void arm_cpu_kvm_set_irq(void *opaque, int irq, int level) 377 { 378 #ifdef CONFIG_KVM 379 ARMCPU *cpu = opaque; 380 CPUState *cs = CPU(cpu); 381 int kvm_irq = KVM_ARM_IRQ_TYPE_CPU << KVM_ARM_IRQ_TYPE_SHIFT; 382 383 switch (irq) { 384 case ARM_CPU_IRQ: 385 kvm_irq |= KVM_ARM_IRQ_CPU_IRQ; 386 break; 387 case ARM_CPU_FIQ: 388 kvm_irq |= KVM_ARM_IRQ_CPU_FIQ; 389 break; 390 default: 391 g_assert_not_reached(); 392 } 393 kvm_irq |= cs->cpu_index << KVM_ARM_IRQ_VCPU_SHIFT; 394 kvm_set_irq(kvm_state, kvm_irq, level ? 1 : 0); 395 #endif 396 } 397 398 static bool arm_cpu_virtio_is_big_endian(CPUState *cs) 399 { 400 ARMCPU *cpu = ARM_CPU(cs); 401 CPUARMState *env = &cpu->env; 402 403 cpu_synchronize_state(cs); 404 return arm_cpu_data_is_big_endian(env); 405 } 406 407 #endif 408 409 static inline void set_feature(CPUARMState *env, int feature) 410 { 411 env->features |= 1ULL << feature; 412 } 413 414 static inline void unset_feature(CPUARMState *env, int feature) 415 { 416 env->features &= ~(1ULL << feature); 417 } 418 419 static int 420 print_insn_thumb1(bfd_vma pc, disassemble_info *info) 421 { 422 return print_insn_arm(pc | 1, info); 423 } 424 425 static int arm_read_memory_func(bfd_vma memaddr, bfd_byte *b, 426 int length, struct disassemble_info *info) 427 { 428 assert(info->read_memory_inner_func); 429 assert((info->flags & INSN_ARM_BE32) == 0 || length == 2 || length == 4); 430 431 if ((info->flags & INSN_ARM_BE32) != 0 && length == 2) { 432 assert(info->endian == BFD_ENDIAN_LITTLE); 433 return info->read_memory_inner_func(memaddr ^ 2, (bfd_byte *)b, 2, 434 info); 435 } else { 436 return info->read_memory_inner_func(memaddr, b, length, info); 437 } 438 } 439 440 static void arm_disas_set_info(CPUState *cpu, disassemble_info *info) 441 { 442 ARMCPU *ac = ARM_CPU(cpu); 443 CPUARMState *env = &ac->env; 444 445 if (is_a64(env)) { 446 /* We might not be compiled with the A64 disassembler 447 * because it needs a C++ compiler. Leave print_insn 448 * unset in this case to use the caller default behaviour. 449 */ 450 #if defined(CONFIG_ARM_A64_DIS) 451 info->print_insn = print_insn_arm_a64; 452 #endif 453 } else if (env->thumb) { 454 info->print_insn = print_insn_thumb1; 455 } else { 456 info->print_insn = print_insn_arm; 457 } 458 if (bswap_code(arm_sctlr_b(env))) { 459 #ifdef TARGET_WORDS_BIGENDIAN 460 info->endian = BFD_ENDIAN_LITTLE; 461 #else 462 info->endian = BFD_ENDIAN_BIG; 463 #endif 464 } 465 if (info->read_memory_inner_func == NULL) { 466 info->read_memory_inner_func = info->read_memory_func; 467 info->read_memory_func = arm_read_memory_func; 468 } 469 info->flags &= ~INSN_ARM_BE32; 470 if (arm_sctlr_b(env)) { 471 info->flags |= INSN_ARM_BE32; 472 } 473 } 474 475 uint64_t arm_cpu_mp_affinity(int idx, uint8_t clustersz) 476 { 477 uint32_t Aff1 = idx / clustersz; 478 uint32_t Aff0 = idx % clustersz; 479 return (Aff1 << ARM_AFF1_SHIFT) | Aff0; 480 } 481 482 static void arm_cpu_initfn(Object *obj) 483 { 484 CPUState *cs = CPU(obj); 485 ARMCPU *cpu = ARM_CPU(obj); 486 static bool inited; 487 488 cs->env_ptr = &cpu->env; 489 cpu->cp_regs = g_hash_table_new_full(g_int_hash, g_int_equal, 490 g_free, g_free); 491 492 #ifndef CONFIG_USER_ONLY 493 /* Our inbound IRQ and FIQ lines */ 494 if (kvm_enabled()) { 495 /* VIRQ and VFIQ are unused with KVM but we add them to maintain 496 * the same interface as non-KVM CPUs. 497 */ 498 qdev_init_gpio_in(DEVICE(cpu), arm_cpu_kvm_set_irq, 4); 499 } else { 500 qdev_init_gpio_in(DEVICE(cpu), arm_cpu_set_irq, 4); 501 } 502 503 cpu->gt_timer[GTIMER_PHYS] = timer_new(QEMU_CLOCK_VIRTUAL, GTIMER_SCALE, 504 arm_gt_ptimer_cb, cpu); 505 cpu->gt_timer[GTIMER_VIRT] = timer_new(QEMU_CLOCK_VIRTUAL, GTIMER_SCALE, 506 arm_gt_vtimer_cb, cpu); 507 cpu->gt_timer[GTIMER_HYP] = timer_new(QEMU_CLOCK_VIRTUAL, GTIMER_SCALE, 508 arm_gt_htimer_cb, cpu); 509 cpu->gt_timer[GTIMER_SEC] = timer_new(QEMU_CLOCK_VIRTUAL, GTIMER_SCALE, 510 arm_gt_stimer_cb, cpu); 511 qdev_init_gpio_out(DEVICE(cpu), cpu->gt_timer_outputs, 512 ARRAY_SIZE(cpu->gt_timer_outputs)); 513 514 qdev_init_gpio_out_named(DEVICE(cpu), &cpu->gicv3_maintenance_interrupt, 515 "gicv3-maintenance-interrupt", 1); 516 #endif 517 518 /* DTB consumers generally don't in fact care what the 'compatible' 519 * string is, so always provide some string and trust that a hypothetical 520 * picky DTB consumer will also provide a helpful error message. 521 */ 522 cpu->dtb_compatible = "qemu,unknown"; 523 cpu->psci_version = 1; /* By default assume PSCI v0.1 */ 524 cpu->kvm_target = QEMU_KVM_ARM_TARGET_NONE; 525 526 if (tcg_enabled()) { 527 cpu->psci_version = 2; /* TCG implements PSCI 0.2 */ 528 if (!inited) { 529 inited = true; 530 arm_translate_init(); 531 } 532 } 533 } 534 535 static Property arm_cpu_reset_cbar_property = 536 DEFINE_PROP_UINT64("reset-cbar", ARMCPU, reset_cbar, 0); 537 538 static Property arm_cpu_reset_hivecs_property = 539 DEFINE_PROP_BOOL("reset-hivecs", ARMCPU, reset_hivecs, false); 540 541 static Property arm_cpu_rvbar_property = 542 DEFINE_PROP_UINT64("rvbar", ARMCPU, rvbar, 0); 543 544 static Property arm_cpu_has_el2_property = 545 DEFINE_PROP_BOOL("has_el2", ARMCPU, has_el2, true); 546 547 static Property arm_cpu_has_el3_property = 548 DEFINE_PROP_BOOL("has_el3", ARMCPU, has_el3, true); 549 550 static Property arm_cpu_cfgend_property = 551 DEFINE_PROP_BOOL("cfgend", ARMCPU, cfgend, false); 552 553 /* use property name "pmu" to match other archs and virt tools */ 554 static Property arm_cpu_has_pmu_property = 555 DEFINE_PROP_BOOL("pmu", ARMCPU, has_pmu, true); 556 557 static Property arm_cpu_has_mpu_property = 558 DEFINE_PROP_BOOL("has-mpu", ARMCPU, has_mpu, true); 559 560 /* This is like DEFINE_PROP_UINT32 but it doesn't set the default value, 561 * because the CPU initfn will have already set cpu->pmsav7_dregion to 562 * the right value for that particular CPU type, and we don't want 563 * to override that with an incorrect constant value. 564 */ 565 static Property arm_cpu_pmsav7_dregion_property = 566 DEFINE_PROP_UNSIGNED_NODEFAULT("pmsav7-dregion", ARMCPU, 567 pmsav7_dregion, 568 qdev_prop_uint32, uint32_t); 569 570 static void arm_cpu_post_init(Object *obj) 571 { 572 ARMCPU *cpu = ARM_CPU(obj); 573 574 /* M profile implies PMSA. We have to do this here rather than 575 * in realize with the other feature-implication checks because 576 * we look at the PMSA bit to see if we should add some properties. 577 */ 578 if (arm_feature(&cpu->env, ARM_FEATURE_M)) { 579 set_feature(&cpu->env, ARM_FEATURE_PMSA); 580 } 581 582 if (arm_feature(&cpu->env, ARM_FEATURE_CBAR) || 583 arm_feature(&cpu->env, ARM_FEATURE_CBAR_RO)) { 584 qdev_property_add_static(DEVICE(obj), &arm_cpu_reset_cbar_property, 585 &error_abort); 586 } 587 588 if (!arm_feature(&cpu->env, ARM_FEATURE_M)) { 589 qdev_property_add_static(DEVICE(obj), &arm_cpu_reset_hivecs_property, 590 &error_abort); 591 } 592 593 if (arm_feature(&cpu->env, ARM_FEATURE_AARCH64)) { 594 qdev_property_add_static(DEVICE(obj), &arm_cpu_rvbar_property, 595 &error_abort); 596 } 597 598 if (arm_feature(&cpu->env, ARM_FEATURE_EL3)) { 599 /* Add the has_el3 state CPU property only if EL3 is allowed. This will 600 * prevent "has_el3" from existing on CPUs which cannot support EL3. 601 */ 602 qdev_property_add_static(DEVICE(obj), &arm_cpu_has_el3_property, 603 &error_abort); 604 605 #ifndef CONFIG_USER_ONLY 606 object_property_add_link(obj, "secure-memory", 607 TYPE_MEMORY_REGION, 608 (Object **)&cpu->secure_memory, 609 qdev_prop_allow_set_link_before_realize, 610 OBJ_PROP_LINK_UNREF_ON_RELEASE, 611 &error_abort); 612 #endif 613 } 614 615 if (arm_feature(&cpu->env, ARM_FEATURE_EL2)) { 616 qdev_property_add_static(DEVICE(obj), &arm_cpu_has_el2_property, 617 &error_abort); 618 } 619 620 if (arm_feature(&cpu->env, ARM_FEATURE_PMU)) { 621 qdev_property_add_static(DEVICE(obj), &arm_cpu_has_pmu_property, 622 &error_abort); 623 } 624 625 if (arm_feature(&cpu->env, ARM_FEATURE_PMSA)) { 626 qdev_property_add_static(DEVICE(obj), &arm_cpu_has_mpu_property, 627 &error_abort); 628 if (arm_feature(&cpu->env, ARM_FEATURE_V7)) { 629 qdev_property_add_static(DEVICE(obj), 630 &arm_cpu_pmsav7_dregion_property, 631 &error_abort); 632 } 633 } 634 635 qdev_property_add_static(DEVICE(obj), &arm_cpu_cfgend_property, 636 &error_abort); 637 } 638 639 static void arm_cpu_finalizefn(Object *obj) 640 { 641 ARMCPU *cpu = ARM_CPU(obj); 642 g_hash_table_destroy(cpu->cp_regs); 643 } 644 645 static void arm_cpu_realizefn(DeviceState *dev, Error **errp) 646 { 647 CPUState *cs = CPU(dev); 648 ARMCPU *cpu = ARM_CPU(dev); 649 ARMCPUClass *acc = ARM_CPU_GET_CLASS(dev); 650 CPUARMState *env = &cpu->env; 651 int pagebits; 652 Error *local_err = NULL; 653 654 cpu_exec_realizefn(cs, &local_err); 655 if (local_err != NULL) { 656 error_propagate(errp, local_err); 657 return; 658 } 659 660 /* Some features automatically imply others: */ 661 if (arm_feature(env, ARM_FEATURE_V8)) { 662 set_feature(env, ARM_FEATURE_V7); 663 set_feature(env, ARM_FEATURE_ARM_DIV); 664 set_feature(env, ARM_FEATURE_LPAE); 665 } 666 if (arm_feature(env, ARM_FEATURE_V7)) { 667 set_feature(env, ARM_FEATURE_VAPA); 668 set_feature(env, ARM_FEATURE_THUMB2); 669 set_feature(env, ARM_FEATURE_MPIDR); 670 if (!arm_feature(env, ARM_FEATURE_M)) { 671 set_feature(env, ARM_FEATURE_V6K); 672 } else { 673 set_feature(env, ARM_FEATURE_V6); 674 } 675 676 /* Always define VBAR for V7 CPUs even if it doesn't exist in 677 * non-EL3 configs. This is needed by some legacy boards. 678 */ 679 set_feature(env, ARM_FEATURE_VBAR); 680 } 681 if (arm_feature(env, ARM_FEATURE_V6K)) { 682 set_feature(env, ARM_FEATURE_V6); 683 set_feature(env, ARM_FEATURE_MVFR); 684 } 685 if (arm_feature(env, ARM_FEATURE_V6)) { 686 set_feature(env, ARM_FEATURE_V5); 687 if (!arm_feature(env, ARM_FEATURE_M)) { 688 set_feature(env, ARM_FEATURE_AUXCR); 689 } 690 } 691 if (arm_feature(env, ARM_FEATURE_V5)) { 692 set_feature(env, ARM_FEATURE_V4T); 693 } 694 if (arm_feature(env, ARM_FEATURE_M)) { 695 set_feature(env, ARM_FEATURE_THUMB_DIV); 696 } 697 if (arm_feature(env, ARM_FEATURE_ARM_DIV)) { 698 set_feature(env, ARM_FEATURE_THUMB_DIV); 699 } 700 if (arm_feature(env, ARM_FEATURE_VFP4)) { 701 set_feature(env, ARM_FEATURE_VFP3); 702 set_feature(env, ARM_FEATURE_VFP_FP16); 703 } 704 if (arm_feature(env, ARM_FEATURE_VFP3)) { 705 set_feature(env, ARM_FEATURE_VFP); 706 } 707 if (arm_feature(env, ARM_FEATURE_LPAE)) { 708 set_feature(env, ARM_FEATURE_V7MP); 709 set_feature(env, ARM_FEATURE_PXN); 710 } 711 if (arm_feature(env, ARM_FEATURE_CBAR_RO)) { 712 set_feature(env, ARM_FEATURE_CBAR); 713 } 714 if (arm_feature(env, ARM_FEATURE_THUMB2) && 715 !arm_feature(env, ARM_FEATURE_M)) { 716 set_feature(env, ARM_FEATURE_THUMB_DSP); 717 } 718 719 if (arm_feature(env, ARM_FEATURE_V7) && 720 !arm_feature(env, ARM_FEATURE_M) && 721 !arm_feature(env, ARM_FEATURE_PMSA)) { 722 /* v7VMSA drops support for the old ARMv5 tiny pages, so we 723 * can use 4K pages. 724 */ 725 pagebits = 12; 726 } else { 727 /* For CPUs which might have tiny 1K pages, or which have an 728 * MPU and might have small region sizes, stick with 1K pages. 729 */ 730 pagebits = 10; 731 } 732 if (!set_preferred_target_page_bits(pagebits)) { 733 /* This can only ever happen for hotplugging a CPU, or if 734 * the board code incorrectly creates a CPU which it has 735 * promised via minimum_page_size that it will not. 736 */ 737 error_setg(errp, "This CPU requires a smaller page size than the " 738 "system is using"); 739 return; 740 } 741 742 /* This cpu-id-to-MPIDR affinity is used only for TCG; KVM will override it. 743 * We don't support setting cluster ID ([16..23]) (known as Aff2 744 * in later ARM ARM versions), or any of the higher affinity level fields, 745 * so these bits always RAZ. 746 */ 747 if (cpu->mp_affinity == ARM64_AFFINITY_INVALID) { 748 cpu->mp_affinity = arm_cpu_mp_affinity(cs->cpu_index, 749 ARM_DEFAULT_CPUS_PER_CLUSTER); 750 } 751 752 if (cpu->reset_hivecs) { 753 cpu->reset_sctlr |= (1 << 13); 754 } 755 756 if (cpu->cfgend) { 757 if (arm_feature(&cpu->env, ARM_FEATURE_V7)) { 758 cpu->reset_sctlr |= SCTLR_EE; 759 } else { 760 cpu->reset_sctlr |= SCTLR_B; 761 } 762 } 763 764 if (!cpu->has_el3) { 765 /* If the has_el3 CPU property is disabled then we need to disable the 766 * feature. 767 */ 768 unset_feature(env, ARM_FEATURE_EL3); 769 770 /* Disable the security extension feature bits in the processor feature 771 * registers as well. These are id_pfr1[7:4] and id_aa64pfr0[15:12]. 772 */ 773 cpu->id_pfr1 &= ~0xf0; 774 cpu->id_aa64pfr0 &= ~0xf000; 775 } 776 777 if (!cpu->has_el2) { 778 unset_feature(env, ARM_FEATURE_EL2); 779 } 780 781 if (!cpu->has_pmu) { 782 unset_feature(env, ARM_FEATURE_PMU); 783 cpu->id_aa64dfr0 &= ~0xf00; 784 } 785 786 if (!arm_feature(env, ARM_FEATURE_EL2)) { 787 /* Disable the hypervisor feature bits in the processor feature 788 * registers if we don't have EL2. These are id_pfr1[15:12] and 789 * id_aa64pfr0_el1[11:8]. 790 */ 791 cpu->id_aa64pfr0 &= ~0xf00; 792 cpu->id_pfr1 &= ~0xf000; 793 } 794 795 /* MPU can be configured out of a PMSA CPU either by setting has-mpu 796 * to false or by setting pmsav7-dregion to 0. 797 */ 798 if (!cpu->has_mpu) { 799 cpu->pmsav7_dregion = 0; 800 } 801 if (cpu->pmsav7_dregion == 0) { 802 cpu->has_mpu = false; 803 } 804 805 if (arm_feature(env, ARM_FEATURE_PMSA) && 806 arm_feature(env, ARM_FEATURE_V7)) { 807 uint32_t nr = cpu->pmsav7_dregion; 808 809 if (nr > 0xff) { 810 error_setg(errp, "PMSAv7 MPU #regions invalid %" PRIu32, nr); 811 return; 812 } 813 814 if (nr) { 815 env->pmsav7.drbar = g_new0(uint32_t, nr); 816 env->pmsav7.drsr = g_new0(uint32_t, nr); 817 env->pmsav7.dracr = g_new0(uint32_t, nr); 818 } 819 } 820 821 if (arm_feature(env, ARM_FEATURE_EL3)) { 822 set_feature(env, ARM_FEATURE_VBAR); 823 } 824 825 register_cp_regs_for_features(cpu); 826 arm_cpu_register_gdb_regs_for_features(cpu); 827 828 init_cpreg_list(cpu); 829 830 #ifndef CONFIG_USER_ONLY 831 if (cpu->has_el3) { 832 cs->num_ases = 2; 833 } else { 834 cs->num_ases = 1; 835 } 836 837 if (cpu->has_el3) { 838 AddressSpace *as; 839 840 if (!cpu->secure_memory) { 841 cpu->secure_memory = cs->memory; 842 } 843 as = address_space_init_shareable(cpu->secure_memory, 844 "cpu-secure-memory"); 845 cpu_address_space_init(cs, as, ARMASIdx_S); 846 } 847 cpu_address_space_init(cs, 848 address_space_init_shareable(cs->memory, 849 "cpu-memory"), 850 ARMASIdx_NS); 851 #endif 852 853 qemu_init_vcpu(cs); 854 cpu_reset(cs); 855 856 acc->parent_realize(dev, errp); 857 } 858 859 static ObjectClass *arm_cpu_class_by_name(const char *cpu_model) 860 { 861 ObjectClass *oc; 862 char *typename; 863 char **cpuname; 864 865 if (!cpu_model) { 866 return NULL; 867 } 868 869 cpuname = g_strsplit(cpu_model, ",", 1); 870 typename = g_strdup_printf("%s-" TYPE_ARM_CPU, cpuname[0]); 871 oc = object_class_by_name(typename); 872 g_strfreev(cpuname); 873 g_free(typename); 874 if (!oc || !object_class_dynamic_cast(oc, TYPE_ARM_CPU) || 875 object_class_is_abstract(oc)) { 876 return NULL; 877 } 878 return oc; 879 } 880 881 /* CPU models. These are not needed for the AArch64 linux-user build. */ 882 #if !defined(CONFIG_USER_ONLY) || !defined(TARGET_AARCH64) 883 884 static void arm926_initfn(Object *obj) 885 { 886 ARMCPU *cpu = ARM_CPU(obj); 887 888 cpu->dtb_compatible = "arm,arm926"; 889 set_feature(&cpu->env, ARM_FEATURE_V5); 890 set_feature(&cpu->env, ARM_FEATURE_VFP); 891 set_feature(&cpu->env, ARM_FEATURE_DUMMY_C15_REGS); 892 set_feature(&cpu->env, ARM_FEATURE_CACHE_TEST_CLEAN); 893 cpu->midr = 0x41069265; 894 cpu->reset_fpsid = 0x41011090; 895 cpu->ctr = 0x1dd20d2; 896 cpu->reset_sctlr = 0x00090078; 897 } 898 899 static void arm946_initfn(Object *obj) 900 { 901 ARMCPU *cpu = ARM_CPU(obj); 902 903 cpu->dtb_compatible = "arm,arm946"; 904 set_feature(&cpu->env, ARM_FEATURE_V5); 905 set_feature(&cpu->env, ARM_FEATURE_PMSA); 906 set_feature(&cpu->env, ARM_FEATURE_DUMMY_C15_REGS); 907 cpu->midr = 0x41059461; 908 cpu->ctr = 0x0f004006; 909 cpu->reset_sctlr = 0x00000078; 910 } 911 912 static void arm1026_initfn(Object *obj) 913 { 914 ARMCPU *cpu = ARM_CPU(obj); 915 916 cpu->dtb_compatible = "arm,arm1026"; 917 set_feature(&cpu->env, ARM_FEATURE_V5); 918 set_feature(&cpu->env, ARM_FEATURE_VFP); 919 set_feature(&cpu->env, ARM_FEATURE_AUXCR); 920 set_feature(&cpu->env, ARM_FEATURE_DUMMY_C15_REGS); 921 set_feature(&cpu->env, ARM_FEATURE_CACHE_TEST_CLEAN); 922 cpu->midr = 0x4106a262; 923 cpu->reset_fpsid = 0x410110a0; 924 cpu->ctr = 0x1dd20d2; 925 cpu->reset_sctlr = 0x00090078; 926 cpu->reset_auxcr = 1; 927 { 928 /* The 1026 had an IFAR at c6,c0,0,1 rather than the ARMv6 c6,c0,0,2 */ 929 ARMCPRegInfo ifar = { 930 .name = "IFAR", .cp = 15, .crn = 6, .crm = 0, .opc1 = 0, .opc2 = 1, 931 .access = PL1_RW, 932 .fieldoffset = offsetof(CPUARMState, cp15.ifar_ns), 933 .resetvalue = 0 934 }; 935 define_one_arm_cp_reg(cpu, &ifar); 936 } 937 } 938 939 static void arm1136_r2_initfn(Object *obj) 940 { 941 ARMCPU *cpu = ARM_CPU(obj); 942 /* What qemu calls "arm1136_r2" is actually the 1136 r0p2, ie an 943 * older core than plain "arm1136". In particular this does not 944 * have the v6K features. 945 * These ID register values are correct for 1136 but may be wrong 946 * for 1136_r2 (in particular r0p2 does not actually implement most 947 * of the ID registers). 948 */ 949 950 cpu->dtb_compatible = "arm,arm1136"; 951 set_feature(&cpu->env, ARM_FEATURE_V6); 952 set_feature(&cpu->env, ARM_FEATURE_VFP); 953 set_feature(&cpu->env, ARM_FEATURE_DUMMY_C15_REGS); 954 set_feature(&cpu->env, ARM_FEATURE_CACHE_DIRTY_REG); 955 set_feature(&cpu->env, ARM_FEATURE_CACHE_BLOCK_OPS); 956 cpu->midr = 0x4107b362; 957 cpu->reset_fpsid = 0x410120b4; 958 cpu->mvfr0 = 0x11111111; 959 cpu->mvfr1 = 0x00000000; 960 cpu->ctr = 0x1dd20d2; 961 cpu->reset_sctlr = 0x00050078; 962 cpu->id_pfr0 = 0x111; 963 cpu->id_pfr1 = 0x1; 964 cpu->id_dfr0 = 0x2; 965 cpu->id_afr0 = 0x3; 966 cpu->id_mmfr0 = 0x01130003; 967 cpu->id_mmfr1 = 0x10030302; 968 cpu->id_mmfr2 = 0x01222110; 969 cpu->id_isar0 = 0x00140011; 970 cpu->id_isar1 = 0x12002111; 971 cpu->id_isar2 = 0x11231111; 972 cpu->id_isar3 = 0x01102131; 973 cpu->id_isar4 = 0x141; 974 cpu->reset_auxcr = 7; 975 } 976 977 static void arm1136_initfn(Object *obj) 978 { 979 ARMCPU *cpu = ARM_CPU(obj); 980 981 cpu->dtb_compatible = "arm,arm1136"; 982 set_feature(&cpu->env, ARM_FEATURE_V6K); 983 set_feature(&cpu->env, ARM_FEATURE_V6); 984 set_feature(&cpu->env, ARM_FEATURE_VFP); 985 set_feature(&cpu->env, ARM_FEATURE_DUMMY_C15_REGS); 986 set_feature(&cpu->env, ARM_FEATURE_CACHE_DIRTY_REG); 987 set_feature(&cpu->env, ARM_FEATURE_CACHE_BLOCK_OPS); 988 cpu->midr = 0x4117b363; 989 cpu->reset_fpsid = 0x410120b4; 990 cpu->mvfr0 = 0x11111111; 991 cpu->mvfr1 = 0x00000000; 992 cpu->ctr = 0x1dd20d2; 993 cpu->reset_sctlr = 0x00050078; 994 cpu->id_pfr0 = 0x111; 995 cpu->id_pfr1 = 0x1; 996 cpu->id_dfr0 = 0x2; 997 cpu->id_afr0 = 0x3; 998 cpu->id_mmfr0 = 0x01130003; 999 cpu->id_mmfr1 = 0x10030302; 1000 cpu->id_mmfr2 = 0x01222110; 1001 cpu->id_isar0 = 0x00140011; 1002 cpu->id_isar1 = 0x12002111; 1003 cpu->id_isar2 = 0x11231111; 1004 cpu->id_isar3 = 0x01102131; 1005 cpu->id_isar4 = 0x141; 1006 cpu->reset_auxcr = 7; 1007 } 1008 1009 static void arm1176_initfn(Object *obj) 1010 { 1011 ARMCPU *cpu = ARM_CPU(obj); 1012 1013 cpu->dtb_compatible = "arm,arm1176"; 1014 set_feature(&cpu->env, ARM_FEATURE_V6K); 1015 set_feature(&cpu->env, ARM_FEATURE_VFP); 1016 set_feature(&cpu->env, ARM_FEATURE_VAPA); 1017 set_feature(&cpu->env, ARM_FEATURE_DUMMY_C15_REGS); 1018 set_feature(&cpu->env, ARM_FEATURE_CACHE_DIRTY_REG); 1019 set_feature(&cpu->env, ARM_FEATURE_CACHE_BLOCK_OPS); 1020 set_feature(&cpu->env, ARM_FEATURE_EL3); 1021 cpu->midr = 0x410fb767; 1022 cpu->reset_fpsid = 0x410120b5; 1023 cpu->mvfr0 = 0x11111111; 1024 cpu->mvfr1 = 0x00000000; 1025 cpu->ctr = 0x1dd20d2; 1026 cpu->reset_sctlr = 0x00050078; 1027 cpu->id_pfr0 = 0x111; 1028 cpu->id_pfr1 = 0x11; 1029 cpu->id_dfr0 = 0x33; 1030 cpu->id_afr0 = 0; 1031 cpu->id_mmfr0 = 0x01130003; 1032 cpu->id_mmfr1 = 0x10030302; 1033 cpu->id_mmfr2 = 0x01222100; 1034 cpu->id_isar0 = 0x0140011; 1035 cpu->id_isar1 = 0x12002111; 1036 cpu->id_isar2 = 0x11231121; 1037 cpu->id_isar3 = 0x01102131; 1038 cpu->id_isar4 = 0x01141; 1039 cpu->reset_auxcr = 7; 1040 } 1041 1042 static void arm11mpcore_initfn(Object *obj) 1043 { 1044 ARMCPU *cpu = ARM_CPU(obj); 1045 1046 cpu->dtb_compatible = "arm,arm11mpcore"; 1047 set_feature(&cpu->env, ARM_FEATURE_V6K); 1048 set_feature(&cpu->env, ARM_FEATURE_VFP); 1049 set_feature(&cpu->env, ARM_FEATURE_VAPA); 1050 set_feature(&cpu->env, ARM_FEATURE_MPIDR); 1051 set_feature(&cpu->env, ARM_FEATURE_DUMMY_C15_REGS); 1052 cpu->midr = 0x410fb022; 1053 cpu->reset_fpsid = 0x410120b4; 1054 cpu->mvfr0 = 0x11111111; 1055 cpu->mvfr1 = 0x00000000; 1056 cpu->ctr = 0x1d192992; /* 32K icache 32K dcache */ 1057 cpu->id_pfr0 = 0x111; 1058 cpu->id_pfr1 = 0x1; 1059 cpu->id_dfr0 = 0; 1060 cpu->id_afr0 = 0x2; 1061 cpu->id_mmfr0 = 0x01100103; 1062 cpu->id_mmfr1 = 0x10020302; 1063 cpu->id_mmfr2 = 0x01222000; 1064 cpu->id_isar0 = 0x00100011; 1065 cpu->id_isar1 = 0x12002111; 1066 cpu->id_isar2 = 0x11221011; 1067 cpu->id_isar3 = 0x01102131; 1068 cpu->id_isar4 = 0x141; 1069 cpu->reset_auxcr = 1; 1070 } 1071 1072 static void cortex_m3_initfn(Object *obj) 1073 { 1074 ARMCPU *cpu = ARM_CPU(obj); 1075 set_feature(&cpu->env, ARM_FEATURE_V7); 1076 set_feature(&cpu->env, ARM_FEATURE_M); 1077 cpu->midr = 0x410fc231; 1078 cpu->pmsav7_dregion = 8; 1079 } 1080 1081 static void cortex_m4_initfn(Object *obj) 1082 { 1083 ARMCPU *cpu = ARM_CPU(obj); 1084 1085 set_feature(&cpu->env, ARM_FEATURE_V7); 1086 set_feature(&cpu->env, ARM_FEATURE_M); 1087 set_feature(&cpu->env, ARM_FEATURE_THUMB_DSP); 1088 cpu->midr = 0x410fc240; /* r0p0 */ 1089 cpu->pmsav7_dregion = 8; 1090 } 1091 static void arm_v7m_class_init(ObjectClass *oc, void *data) 1092 { 1093 CPUClass *cc = CPU_CLASS(oc); 1094 1095 #ifndef CONFIG_USER_ONLY 1096 cc->do_interrupt = arm_v7m_cpu_do_interrupt; 1097 #endif 1098 1099 cc->cpu_exec_interrupt = arm_v7m_cpu_exec_interrupt; 1100 } 1101 1102 static const ARMCPRegInfo cortexr5_cp_reginfo[] = { 1103 /* Dummy the TCM region regs for the moment */ 1104 { .name = "ATCM", .cp = 15, .opc1 = 0, .crn = 9, .crm = 1, .opc2 = 0, 1105 .access = PL1_RW, .type = ARM_CP_CONST }, 1106 { .name = "BTCM", .cp = 15, .opc1 = 0, .crn = 9, .crm = 1, .opc2 = 1, 1107 .access = PL1_RW, .type = ARM_CP_CONST }, 1108 { .name = "DCACHE_INVAL", .cp = 15, .opc1 = 0, .crn = 15, .crm = 5, 1109 .opc2 = 0, .access = PL1_W, .type = ARM_CP_NOP }, 1110 REGINFO_SENTINEL 1111 }; 1112 1113 static void cortex_r5_initfn(Object *obj) 1114 { 1115 ARMCPU *cpu = ARM_CPU(obj); 1116 1117 set_feature(&cpu->env, ARM_FEATURE_V7); 1118 set_feature(&cpu->env, ARM_FEATURE_THUMB_DIV); 1119 set_feature(&cpu->env, ARM_FEATURE_ARM_DIV); 1120 set_feature(&cpu->env, ARM_FEATURE_V7MP); 1121 set_feature(&cpu->env, ARM_FEATURE_PMSA); 1122 cpu->midr = 0x411fc153; /* r1p3 */ 1123 cpu->id_pfr0 = 0x0131; 1124 cpu->id_pfr1 = 0x001; 1125 cpu->id_dfr0 = 0x010400; 1126 cpu->id_afr0 = 0x0; 1127 cpu->id_mmfr0 = 0x0210030; 1128 cpu->id_mmfr1 = 0x00000000; 1129 cpu->id_mmfr2 = 0x01200000; 1130 cpu->id_mmfr3 = 0x0211; 1131 cpu->id_isar0 = 0x2101111; 1132 cpu->id_isar1 = 0x13112111; 1133 cpu->id_isar2 = 0x21232141; 1134 cpu->id_isar3 = 0x01112131; 1135 cpu->id_isar4 = 0x0010142; 1136 cpu->id_isar5 = 0x0; 1137 cpu->mp_is_up = true; 1138 cpu->pmsav7_dregion = 16; 1139 define_arm_cp_regs(cpu, cortexr5_cp_reginfo); 1140 } 1141 1142 static const ARMCPRegInfo cortexa8_cp_reginfo[] = { 1143 { .name = "L2LOCKDOWN", .cp = 15, .crn = 9, .crm = 0, .opc1 = 1, .opc2 = 0, 1144 .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0 }, 1145 { .name = "L2AUXCR", .cp = 15, .crn = 9, .crm = 0, .opc1 = 1, .opc2 = 2, 1146 .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0 }, 1147 REGINFO_SENTINEL 1148 }; 1149 1150 static void cortex_a8_initfn(Object *obj) 1151 { 1152 ARMCPU *cpu = ARM_CPU(obj); 1153 1154 cpu->dtb_compatible = "arm,cortex-a8"; 1155 set_feature(&cpu->env, ARM_FEATURE_V7); 1156 set_feature(&cpu->env, ARM_FEATURE_VFP3); 1157 set_feature(&cpu->env, ARM_FEATURE_NEON); 1158 set_feature(&cpu->env, ARM_FEATURE_THUMB2EE); 1159 set_feature(&cpu->env, ARM_FEATURE_DUMMY_C15_REGS); 1160 set_feature(&cpu->env, ARM_FEATURE_EL3); 1161 cpu->midr = 0x410fc080; 1162 cpu->reset_fpsid = 0x410330c0; 1163 cpu->mvfr0 = 0x11110222; 1164 cpu->mvfr1 = 0x00011111; 1165 cpu->ctr = 0x82048004; 1166 cpu->reset_sctlr = 0x00c50078; 1167 cpu->id_pfr0 = 0x1031; 1168 cpu->id_pfr1 = 0x11; 1169 cpu->id_dfr0 = 0x400; 1170 cpu->id_afr0 = 0; 1171 cpu->id_mmfr0 = 0x31100003; 1172 cpu->id_mmfr1 = 0x20000000; 1173 cpu->id_mmfr2 = 0x01202000; 1174 cpu->id_mmfr3 = 0x11; 1175 cpu->id_isar0 = 0x00101111; 1176 cpu->id_isar1 = 0x12112111; 1177 cpu->id_isar2 = 0x21232031; 1178 cpu->id_isar3 = 0x11112131; 1179 cpu->id_isar4 = 0x00111142; 1180 cpu->dbgdidr = 0x15141000; 1181 cpu->clidr = (1 << 27) | (2 << 24) | 3; 1182 cpu->ccsidr[0] = 0xe007e01a; /* 16k L1 dcache. */ 1183 cpu->ccsidr[1] = 0x2007e01a; /* 16k L1 icache. */ 1184 cpu->ccsidr[2] = 0xf0000000; /* No L2 icache. */ 1185 cpu->reset_auxcr = 2; 1186 define_arm_cp_regs(cpu, cortexa8_cp_reginfo); 1187 } 1188 1189 static const ARMCPRegInfo cortexa9_cp_reginfo[] = { 1190 /* power_control should be set to maximum latency. Again, 1191 * default to 0 and set by private hook 1192 */ 1193 { .name = "A9_PWRCTL", .cp = 15, .crn = 15, .crm = 0, .opc1 = 0, .opc2 = 0, 1194 .access = PL1_RW, .resetvalue = 0, 1195 .fieldoffset = offsetof(CPUARMState, cp15.c15_power_control) }, 1196 { .name = "A9_DIAG", .cp = 15, .crn = 15, .crm = 0, .opc1 = 0, .opc2 = 1, 1197 .access = PL1_RW, .resetvalue = 0, 1198 .fieldoffset = offsetof(CPUARMState, cp15.c15_diagnostic) }, 1199 { .name = "A9_PWRDIAG", .cp = 15, .crn = 15, .crm = 0, .opc1 = 0, .opc2 = 2, 1200 .access = PL1_RW, .resetvalue = 0, 1201 .fieldoffset = offsetof(CPUARMState, cp15.c15_power_diagnostic) }, 1202 { .name = "NEONBUSY", .cp = 15, .crn = 15, .crm = 1, .opc1 = 0, .opc2 = 0, 1203 .access = PL1_RW, .resetvalue = 0, .type = ARM_CP_CONST }, 1204 /* TLB lockdown control */ 1205 { .name = "TLB_LOCKR", .cp = 15, .crn = 15, .crm = 4, .opc1 = 5, .opc2 = 2, 1206 .access = PL1_W, .resetvalue = 0, .type = ARM_CP_NOP }, 1207 { .name = "TLB_LOCKW", .cp = 15, .crn = 15, .crm = 4, .opc1 = 5, .opc2 = 4, 1208 .access = PL1_W, .resetvalue = 0, .type = ARM_CP_NOP }, 1209 { .name = "TLB_VA", .cp = 15, .crn = 15, .crm = 5, .opc1 = 5, .opc2 = 2, 1210 .access = PL1_RW, .resetvalue = 0, .type = ARM_CP_CONST }, 1211 { .name = "TLB_PA", .cp = 15, .crn = 15, .crm = 6, .opc1 = 5, .opc2 = 2, 1212 .access = PL1_RW, .resetvalue = 0, .type = ARM_CP_CONST }, 1213 { .name = "TLB_ATTR", .cp = 15, .crn = 15, .crm = 7, .opc1 = 5, .opc2 = 2, 1214 .access = PL1_RW, .resetvalue = 0, .type = ARM_CP_CONST }, 1215 REGINFO_SENTINEL 1216 }; 1217 1218 static void cortex_a9_initfn(Object *obj) 1219 { 1220 ARMCPU *cpu = ARM_CPU(obj); 1221 1222 cpu->dtb_compatible = "arm,cortex-a9"; 1223 set_feature(&cpu->env, ARM_FEATURE_V7); 1224 set_feature(&cpu->env, ARM_FEATURE_VFP3); 1225 set_feature(&cpu->env, ARM_FEATURE_VFP_FP16); 1226 set_feature(&cpu->env, ARM_FEATURE_NEON); 1227 set_feature(&cpu->env, ARM_FEATURE_THUMB2EE); 1228 set_feature(&cpu->env, ARM_FEATURE_EL3); 1229 /* Note that A9 supports the MP extensions even for 1230 * A9UP and single-core A9MP (which are both different 1231 * and valid configurations; we don't model A9UP). 1232 */ 1233 set_feature(&cpu->env, ARM_FEATURE_V7MP); 1234 set_feature(&cpu->env, ARM_FEATURE_CBAR); 1235 cpu->midr = 0x410fc090; 1236 cpu->reset_fpsid = 0x41033090; 1237 cpu->mvfr0 = 0x11110222; 1238 cpu->mvfr1 = 0x01111111; 1239 cpu->ctr = 0x80038003; 1240 cpu->reset_sctlr = 0x00c50078; 1241 cpu->id_pfr0 = 0x1031; 1242 cpu->id_pfr1 = 0x11; 1243 cpu->id_dfr0 = 0x000; 1244 cpu->id_afr0 = 0; 1245 cpu->id_mmfr0 = 0x00100103; 1246 cpu->id_mmfr1 = 0x20000000; 1247 cpu->id_mmfr2 = 0x01230000; 1248 cpu->id_mmfr3 = 0x00002111; 1249 cpu->id_isar0 = 0x00101111; 1250 cpu->id_isar1 = 0x13112111; 1251 cpu->id_isar2 = 0x21232041; 1252 cpu->id_isar3 = 0x11112131; 1253 cpu->id_isar4 = 0x00111142; 1254 cpu->dbgdidr = 0x35141000; 1255 cpu->clidr = (1 << 27) | (1 << 24) | 3; 1256 cpu->ccsidr[0] = 0xe00fe019; /* 16k L1 dcache. */ 1257 cpu->ccsidr[1] = 0x200fe019; /* 16k L1 icache. */ 1258 define_arm_cp_regs(cpu, cortexa9_cp_reginfo); 1259 } 1260 1261 #ifndef CONFIG_USER_ONLY 1262 static uint64_t a15_l2ctlr_read(CPUARMState *env, const ARMCPRegInfo *ri) 1263 { 1264 /* Linux wants the number of processors from here. 1265 * Might as well set the interrupt-controller bit too. 1266 */ 1267 return ((smp_cpus - 1) << 24) | (1 << 23); 1268 } 1269 #endif 1270 1271 static const ARMCPRegInfo cortexa15_cp_reginfo[] = { 1272 #ifndef CONFIG_USER_ONLY 1273 { .name = "L2CTLR", .cp = 15, .crn = 9, .crm = 0, .opc1 = 1, .opc2 = 2, 1274 .access = PL1_RW, .resetvalue = 0, .readfn = a15_l2ctlr_read, 1275 .writefn = arm_cp_write_ignore, }, 1276 #endif 1277 { .name = "L2ECTLR", .cp = 15, .crn = 9, .crm = 0, .opc1 = 1, .opc2 = 3, 1278 .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0 }, 1279 REGINFO_SENTINEL 1280 }; 1281 1282 static void cortex_a7_initfn(Object *obj) 1283 { 1284 ARMCPU *cpu = ARM_CPU(obj); 1285 1286 cpu->dtb_compatible = "arm,cortex-a7"; 1287 set_feature(&cpu->env, ARM_FEATURE_V7); 1288 set_feature(&cpu->env, ARM_FEATURE_VFP4); 1289 set_feature(&cpu->env, ARM_FEATURE_NEON); 1290 set_feature(&cpu->env, ARM_FEATURE_THUMB2EE); 1291 set_feature(&cpu->env, ARM_FEATURE_ARM_DIV); 1292 set_feature(&cpu->env, ARM_FEATURE_GENERIC_TIMER); 1293 set_feature(&cpu->env, ARM_FEATURE_DUMMY_C15_REGS); 1294 set_feature(&cpu->env, ARM_FEATURE_CBAR_RO); 1295 set_feature(&cpu->env, ARM_FEATURE_LPAE); 1296 set_feature(&cpu->env, ARM_FEATURE_EL3); 1297 cpu->kvm_target = QEMU_KVM_ARM_TARGET_CORTEX_A7; 1298 cpu->midr = 0x410fc075; 1299 cpu->reset_fpsid = 0x41023075; 1300 cpu->mvfr0 = 0x10110222; 1301 cpu->mvfr1 = 0x11111111; 1302 cpu->ctr = 0x84448003; 1303 cpu->reset_sctlr = 0x00c50078; 1304 cpu->id_pfr0 = 0x00001131; 1305 cpu->id_pfr1 = 0x00011011; 1306 cpu->id_dfr0 = 0x02010555; 1307 cpu->pmceid0 = 0x00000000; 1308 cpu->pmceid1 = 0x00000000; 1309 cpu->id_afr0 = 0x00000000; 1310 cpu->id_mmfr0 = 0x10101105; 1311 cpu->id_mmfr1 = 0x40000000; 1312 cpu->id_mmfr2 = 0x01240000; 1313 cpu->id_mmfr3 = 0x02102211; 1314 cpu->id_isar0 = 0x01101110; 1315 cpu->id_isar1 = 0x13112111; 1316 cpu->id_isar2 = 0x21232041; 1317 cpu->id_isar3 = 0x11112131; 1318 cpu->id_isar4 = 0x10011142; 1319 cpu->dbgdidr = 0x3515f005; 1320 cpu->clidr = 0x0a200023; 1321 cpu->ccsidr[0] = 0x701fe00a; /* 32K L1 dcache */ 1322 cpu->ccsidr[1] = 0x201fe00a; /* 32K L1 icache */ 1323 cpu->ccsidr[2] = 0x711fe07a; /* 4096K L2 unified cache */ 1324 define_arm_cp_regs(cpu, cortexa15_cp_reginfo); /* Same as A15 */ 1325 } 1326 1327 static void cortex_a15_initfn(Object *obj) 1328 { 1329 ARMCPU *cpu = ARM_CPU(obj); 1330 1331 cpu->dtb_compatible = "arm,cortex-a15"; 1332 set_feature(&cpu->env, ARM_FEATURE_V7); 1333 set_feature(&cpu->env, ARM_FEATURE_VFP4); 1334 set_feature(&cpu->env, ARM_FEATURE_NEON); 1335 set_feature(&cpu->env, ARM_FEATURE_THUMB2EE); 1336 set_feature(&cpu->env, ARM_FEATURE_ARM_DIV); 1337 set_feature(&cpu->env, ARM_FEATURE_GENERIC_TIMER); 1338 set_feature(&cpu->env, ARM_FEATURE_DUMMY_C15_REGS); 1339 set_feature(&cpu->env, ARM_FEATURE_CBAR_RO); 1340 set_feature(&cpu->env, ARM_FEATURE_LPAE); 1341 set_feature(&cpu->env, ARM_FEATURE_EL3); 1342 cpu->kvm_target = QEMU_KVM_ARM_TARGET_CORTEX_A15; 1343 cpu->midr = 0x412fc0f1; 1344 cpu->reset_fpsid = 0x410430f0; 1345 cpu->mvfr0 = 0x10110222; 1346 cpu->mvfr1 = 0x11111111; 1347 cpu->ctr = 0x8444c004; 1348 cpu->reset_sctlr = 0x00c50078; 1349 cpu->id_pfr0 = 0x00001131; 1350 cpu->id_pfr1 = 0x00011011; 1351 cpu->id_dfr0 = 0x02010555; 1352 cpu->pmceid0 = 0x0000000; 1353 cpu->pmceid1 = 0x00000000; 1354 cpu->id_afr0 = 0x00000000; 1355 cpu->id_mmfr0 = 0x10201105; 1356 cpu->id_mmfr1 = 0x20000000; 1357 cpu->id_mmfr2 = 0x01240000; 1358 cpu->id_mmfr3 = 0x02102211; 1359 cpu->id_isar0 = 0x02101110; 1360 cpu->id_isar1 = 0x13112111; 1361 cpu->id_isar2 = 0x21232041; 1362 cpu->id_isar3 = 0x11112131; 1363 cpu->id_isar4 = 0x10011142; 1364 cpu->dbgdidr = 0x3515f021; 1365 cpu->clidr = 0x0a200023; 1366 cpu->ccsidr[0] = 0x701fe00a; /* 32K L1 dcache */ 1367 cpu->ccsidr[1] = 0x201fe00a; /* 32K L1 icache */ 1368 cpu->ccsidr[2] = 0x711fe07a; /* 4096K L2 unified cache */ 1369 define_arm_cp_regs(cpu, cortexa15_cp_reginfo); 1370 } 1371 1372 static void ti925t_initfn(Object *obj) 1373 { 1374 ARMCPU *cpu = ARM_CPU(obj); 1375 set_feature(&cpu->env, ARM_FEATURE_V4T); 1376 set_feature(&cpu->env, ARM_FEATURE_OMAPCP); 1377 cpu->midr = ARM_CPUID_TI925T; 1378 cpu->ctr = 0x5109149; 1379 cpu->reset_sctlr = 0x00000070; 1380 } 1381 1382 static void sa1100_initfn(Object *obj) 1383 { 1384 ARMCPU *cpu = ARM_CPU(obj); 1385 1386 cpu->dtb_compatible = "intel,sa1100"; 1387 set_feature(&cpu->env, ARM_FEATURE_STRONGARM); 1388 set_feature(&cpu->env, ARM_FEATURE_DUMMY_C15_REGS); 1389 cpu->midr = 0x4401A11B; 1390 cpu->reset_sctlr = 0x00000070; 1391 } 1392 1393 static void sa1110_initfn(Object *obj) 1394 { 1395 ARMCPU *cpu = ARM_CPU(obj); 1396 set_feature(&cpu->env, ARM_FEATURE_STRONGARM); 1397 set_feature(&cpu->env, ARM_FEATURE_DUMMY_C15_REGS); 1398 cpu->midr = 0x6901B119; 1399 cpu->reset_sctlr = 0x00000070; 1400 } 1401 1402 static void pxa250_initfn(Object *obj) 1403 { 1404 ARMCPU *cpu = ARM_CPU(obj); 1405 1406 cpu->dtb_compatible = "marvell,xscale"; 1407 set_feature(&cpu->env, ARM_FEATURE_V5); 1408 set_feature(&cpu->env, ARM_FEATURE_XSCALE); 1409 cpu->midr = 0x69052100; 1410 cpu->ctr = 0xd172172; 1411 cpu->reset_sctlr = 0x00000078; 1412 } 1413 1414 static void pxa255_initfn(Object *obj) 1415 { 1416 ARMCPU *cpu = ARM_CPU(obj); 1417 1418 cpu->dtb_compatible = "marvell,xscale"; 1419 set_feature(&cpu->env, ARM_FEATURE_V5); 1420 set_feature(&cpu->env, ARM_FEATURE_XSCALE); 1421 cpu->midr = 0x69052d00; 1422 cpu->ctr = 0xd172172; 1423 cpu->reset_sctlr = 0x00000078; 1424 } 1425 1426 static void pxa260_initfn(Object *obj) 1427 { 1428 ARMCPU *cpu = ARM_CPU(obj); 1429 1430 cpu->dtb_compatible = "marvell,xscale"; 1431 set_feature(&cpu->env, ARM_FEATURE_V5); 1432 set_feature(&cpu->env, ARM_FEATURE_XSCALE); 1433 cpu->midr = 0x69052903; 1434 cpu->ctr = 0xd172172; 1435 cpu->reset_sctlr = 0x00000078; 1436 } 1437 1438 static void pxa261_initfn(Object *obj) 1439 { 1440 ARMCPU *cpu = ARM_CPU(obj); 1441 1442 cpu->dtb_compatible = "marvell,xscale"; 1443 set_feature(&cpu->env, ARM_FEATURE_V5); 1444 set_feature(&cpu->env, ARM_FEATURE_XSCALE); 1445 cpu->midr = 0x69052d05; 1446 cpu->ctr = 0xd172172; 1447 cpu->reset_sctlr = 0x00000078; 1448 } 1449 1450 static void pxa262_initfn(Object *obj) 1451 { 1452 ARMCPU *cpu = ARM_CPU(obj); 1453 1454 cpu->dtb_compatible = "marvell,xscale"; 1455 set_feature(&cpu->env, ARM_FEATURE_V5); 1456 set_feature(&cpu->env, ARM_FEATURE_XSCALE); 1457 cpu->midr = 0x69052d06; 1458 cpu->ctr = 0xd172172; 1459 cpu->reset_sctlr = 0x00000078; 1460 } 1461 1462 static void pxa270a0_initfn(Object *obj) 1463 { 1464 ARMCPU *cpu = ARM_CPU(obj); 1465 1466 cpu->dtb_compatible = "marvell,xscale"; 1467 set_feature(&cpu->env, ARM_FEATURE_V5); 1468 set_feature(&cpu->env, ARM_FEATURE_XSCALE); 1469 set_feature(&cpu->env, ARM_FEATURE_IWMMXT); 1470 cpu->midr = 0x69054110; 1471 cpu->ctr = 0xd172172; 1472 cpu->reset_sctlr = 0x00000078; 1473 } 1474 1475 static void pxa270a1_initfn(Object *obj) 1476 { 1477 ARMCPU *cpu = ARM_CPU(obj); 1478 1479 cpu->dtb_compatible = "marvell,xscale"; 1480 set_feature(&cpu->env, ARM_FEATURE_V5); 1481 set_feature(&cpu->env, ARM_FEATURE_XSCALE); 1482 set_feature(&cpu->env, ARM_FEATURE_IWMMXT); 1483 cpu->midr = 0x69054111; 1484 cpu->ctr = 0xd172172; 1485 cpu->reset_sctlr = 0x00000078; 1486 } 1487 1488 static void pxa270b0_initfn(Object *obj) 1489 { 1490 ARMCPU *cpu = ARM_CPU(obj); 1491 1492 cpu->dtb_compatible = "marvell,xscale"; 1493 set_feature(&cpu->env, ARM_FEATURE_V5); 1494 set_feature(&cpu->env, ARM_FEATURE_XSCALE); 1495 set_feature(&cpu->env, ARM_FEATURE_IWMMXT); 1496 cpu->midr = 0x69054112; 1497 cpu->ctr = 0xd172172; 1498 cpu->reset_sctlr = 0x00000078; 1499 } 1500 1501 static void pxa270b1_initfn(Object *obj) 1502 { 1503 ARMCPU *cpu = ARM_CPU(obj); 1504 1505 cpu->dtb_compatible = "marvell,xscale"; 1506 set_feature(&cpu->env, ARM_FEATURE_V5); 1507 set_feature(&cpu->env, ARM_FEATURE_XSCALE); 1508 set_feature(&cpu->env, ARM_FEATURE_IWMMXT); 1509 cpu->midr = 0x69054113; 1510 cpu->ctr = 0xd172172; 1511 cpu->reset_sctlr = 0x00000078; 1512 } 1513 1514 static void pxa270c0_initfn(Object *obj) 1515 { 1516 ARMCPU *cpu = ARM_CPU(obj); 1517 1518 cpu->dtb_compatible = "marvell,xscale"; 1519 set_feature(&cpu->env, ARM_FEATURE_V5); 1520 set_feature(&cpu->env, ARM_FEATURE_XSCALE); 1521 set_feature(&cpu->env, ARM_FEATURE_IWMMXT); 1522 cpu->midr = 0x69054114; 1523 cpu->ctr = 0xd172172; 1524 cpu->reset_sctlr = 0x00000078; 1525 } 1526 1527 static void pxa270c5_initfn(Object *obj) 1528 { 1529 ARMCPU *cpu = ARM_CPU(obj); 1530 1531 cpu->dtb_compatible = "marvell,xscale"; 1532 set_feature(&cpu->env, ARM_FEATURE_V5); 1533 set_feature(&cpu->env, ARM_FEATURE_XSCALE); 1534 set_feature(&cpu->env, ARM_FEATURE_IWMMXT); 1535 cpu->midr = 0x69054117; 1536 cpu->ctr = 0xd172172; 1537 cpu->reset_sctlr = 0x00000078; 1538 } 1539 1540 #ifdef CONFIG_USER_ONLY 1541 static void arm_any_initfn(Object *obj) 1542 { 1543 ARMCPU *cpu = ARM_CPU(obj); 1544 set_feature(&cpu->env, ARM_FEATURE_V8); 1545 set_feature(&cpu->env, ARM_FEATURE_VFP4); 1546 set_feature(&cpu->env, ARM_FEATURE_NEON); 1547 set_feature(&cpu->env, ARM_FEATURE_THUMB2EE); 1548 set_feature(&cpu->env, ARM_FEATURE_V8_AES); 1549 set_feature(&cpu->env, ARM_FEATURE_V8_SHA1); 1550 set_feature(&cpu->env, ARM_FEATURE_V8_SHA256); 1551 set_feature(&cpu->env, ARM_FEATURE_V8_PMULL); 1552 set_feature(&cpu->env, ARM_FEATURE_CRC); 1553 cpu->midr = 0xffffffff; 1554 } 1555 #endif 1556 1557 #endif /* !defined(CONFIG_USER_ONLY) || !defined(TARGET_AARCH64) */ 1558 1559 typedef struct ARMCPUInfo { 1560 const char *name; 1561 void (*initfn)(Object *obj); 1562 void (*class_init)(ObjectClass *oc, void *data); 1563 } ARMCPUInfo; 1564 1565 static const ARMCPUInfo arm_cpus[] = { 1566 #if !defined(CONFIG_USER_ONLY) || !defined(TARGET_AARCH64) 1567 { .name = "arm926", .initfn = arm926_initfn }, 1568 { .name = "arm946", .initfn = arm946_initfn }, 1569 { .name = "arm1026", .initfn = arm1026_initfn }, 1570 /* What QEMU calls "arm1136-r2" is actually the 1136 r0p2, i.e. an 1571 * older core than plain "arm1136". In particular this does not 1572 * have the v6K features. 1573 */ 1574 { .name = "arm1136-r2", .initfn = arm1136_r2_initfn }, 1575 { .name = "arm1136", .initfn = arm1136_initfn }, 1576 { .name = "arm1176", .initfn = arm1176_initfn }, 1577 { .name = "arm11mpcore", .initfn = arm11mpcore_initfn }, 1578 { .name = "cortex-m3", .initfn = cortex_m3_initfn, 1579 .class_init = arm_v7m_class_init }, 1580 { .name = "cortex-m4", .initfn = cortex_m4_initfn, 1581 .class_init = arm_v7m_class_init }, 1582 { .name = "cortex-r5", .initfn = cortex_r5_initfn }, 1583 { .name = "cortex-a7", .initfn = cortex_a7_initfn }, 1584 { .name = "cortex-a8", .initfn = cortex_a8_initfn }, 1585 { .name = "cortex-a9", .initfn = cortex_a9_initfn }, 1586 { .name = "cortex-a15", .initfn = cortex_a15_initfn }, 1587 { .name = "ti925t", .initfn = ti925t_initfn }, 1588 { .name = "sa1100", .initfn = sa1100_initfn }, 1589 { .name = "sa1110", .initfn = sa1110_initfn }, 1590 { .name = "pxa250", .initfn = pxa250_initfn }, 1591 { .name = "pxa255", .initfn = pxa255_initfn }, 1592 { .name = "pxa260", .initfn = pxa260_initfn }, 1593 { .name = "pxa261", .initfn = pxa261_initfn }, 1594 { .name = "pxa262", .initfn = pxa262_initfn }, 1595 /* "pxa270" is an alias for "pxa270-a0" */ 1596 { .name = "pxa270", .initfn = pxa270a0_initfn }, 1597 { .name = "pxa270-a0", .initfn = pxa270a0_initfn }, 1598 { .name = "pxa270-a1", .initfn = pxa270a1_initfn }, 1599 { .name = "pxa270-b0", .initfn = pxa270b0_initfn }, 1600 { .name = "pxa270-b1", .initfn = pxa270b1_initfn }, 1601 { .name = "pxa270-c0", .initfn = pxa270c0_initfn }, 1602 { .name = "pxa270-c5", .initfn = pxa270c5_initfn }, 1603 #ifdef CONFIG_USER_ONLY 1604 { .name = "any", .initfn = arm_any_initfn }, 1605 #endif 1606 #endif 1607 { .name = NULL } 1608 }; 1609 1610 static Property arm_cpu_properties[] = { 1611 DEFINE_PROP_BOOL("start-powered-off", ARMCPU, start_powered_off, false), 1612 DEFINE_PROP_UINT32("psci-conduit", ARMCPU, psci_conduit, 0), 1613 DEFINE_PROP_UINT32("midr", ARMCPU, midr, 0), 1614 DEFINE_PROP_UINT64("mp-affinity", ARMCPU, 1615 mp_affinity, ARM64_AFFINITY_INVALID), 1616 DEFINE_PROP_INT32("node-id", ARMCPU, node_id, CPU_UNSET_NUMA_NODE_ID), 1617 DEFINE_PROP_END_OF_LIST() 1618 }; 1619 1620 #ifdef CONFIG_USER_ONLY 1621 static int arm_cpu_handle_mmu_fault(CPUState *cs, vaddr address, int rw, 1622 int mmu_idx) 1623 { 1624 ARMCPU *cpu = ARM_CPU(cs); 1625 CPUARMState *env = &cpu->env; 1626 1627 env->exception.vaddress = address; 1628 if (rw == 2) { 1629 cs->exception_index = EXCP_PREFETCH_ABORT; 1630 } else { 1631 cs->exception_index = EXCP_DATA_ABORT; 1632 } 1633 return 1; 1634 } 1635 #endif 1636 1637 static gchar *arm_gdb_arch_name(CPUState *cs) 1638 { 1639 ARMCPU *cpu = ARM_CPU(cs); 1640 CPUARMState *env = &cpu->env; 1641 1642 if (arm_feature(env, ARM_FEATURE_IWMMXT)) { 1643 return g_strdup("iwmmxt"); 1644 } 1645 return g_strdup("arm"); 1646 } 1647 1648 static void arm_cpu_class_init(ObjectClass *oc, void *data) 1649 { 1650 ARMCPUClass *acc = ARM_CPU_CLASS(oc); 1651 CPUClass *cc = CPU_CLASS(acc); 1652 DeviceClass *dc = DEVICE_CLASS(oc); 1653 1654 acc->parent_realize = dc->realize; 1655 dc->realize = arm_cpu_realizefn; 1656 dc->props = arm_cpu_properties; 1657 1658 acc->parent_reset = cc->reset; 1659 cc->reset = arm_cpu_reset; 1660 1661 cc->class_by_name = arm_cpu_class_by_name; 1662 cc->has_work = arm_cpu_has_work; 1663 cc->cpu_exec_interrupt = arm_cpu_exec_interrupt; 1664 cc->dump_state = arm_cpu_dump_state; 1665 cc->set_pc = arm_cpu_set_pc; 1666 cc->gdb_read_register = arm_cpu_gdb_read_register; 1667 cc->gdb_write_register = arm_cpu_gdb_write_register; 1668 #ifdef CONFIG_USER_ONLY 1669 cc->handle_mmu_fault = arm_cpu_handle_mmu_fault; 1670 #else 1671 cc->do_interrupt = arm_cpu_do_interrupt; 1672 cc->do_unaligned_access = arm_cpu_do_unaligned_access; 1673 cc->get_phys_page_attrs_debug = arm_cpu_get_phys_page_attrs_debug; 1674 cc->asidx_from_attrs = arm_asidx_from_attrs; 1675 cc->vmsd = &vmstate_arm_cpu; 1676 cc->virtio_is_big_endian = arm_cpu_virtio_is_big_endian; 1677 cc->write_elf64_note = arm_cpu_write_elf64_note; 1678 cc->write_elf32_note = arm_cpu_write_elf32_note; 1679 #endif 1680 cc->gdb_num_core_regs = 26; 1681 cc->gdb_core_xml_file = "arm-core.xml"; 1682 cc->gdb_arch_name = arm_gdb_arch_name; 1683 cc->gdb_stop_before_watchpoint = true; 1684 cc->debug_excp_handler = arm_debug_excp_handler; 1685 cc->debug_check_watchpoint = arm_debug_check_watchpoint; 1686 #if !defined(CONFIG_USER_ONLY) 1687 cc->adjust_watchpoint_address = arm_adjust_watchpoint_address; 1688 #endif 1689 1690 cc->disas_set_info = arm_disas_set_info; 1691 } 1692 1693 static void cpu_register(const ARMCPUInfo *info) 1694 { 1695 TypeInfo type_info = { 1696 .parent = TYPE_ARM_CPU, 1697 .instance_size = sizeof(ARMCPU), 1698 .instance_init = info->initfn, 1699 .class_size = sizeof(ARMCPUClass), 1700 .class_init = info->class_init, 1701 }; 1702 1703 type_info.name = g_strdup_printf("%s-" TYPE_ARM_CPU, info->name); 1704 type_register(&type_info); 1705 g_free((void *)type_info.name); 1706 } 1707 1708 static const TypeInfo arm_cpu_type_info = { 1709 .name = TYPE_ARM_CPU, 1710 .parent = TYPE_CPU, 1711 .instance_size = sizeof(ARMCPU), 1712 .instance_init = arm_cpu_initfn, 1713 .instance_post_init = arm_cpu_post_init, 1714 .instance_finalize = arm_cpu_finalizefn, 1715 .abstract = true, 1716 .class_size = sizeof(ARMCPUClass), 1717 .class_init = arm_cpu_class_init, 1718 }; 1719 1720 static void arm_cpu_register_types(void) 1721 { 1722 const ARMCPUInfo *info = arm_cpus; 1723 1724 type_register_static(&arm_cpu_type_info); 1725 1726 while (info->name) { 1727 cpu_register(info); 1728 info++; 1729 } 1730 } 1731 1732 type_init(arm_cpu_register_types) 1733