xref: /openbmc/qemu/target/arm/cpu.c (revision 80e5db30)
1 /*
2  * QEMU ARM CPU
3  *
4  * Copyright (c) 2012 SUSE LINUX Products GmbH
5  *
6  * This program is free software; you can redistribute it and/or
7  * modify it under the terms of the GNU General Public License
8  * as published by the Free Software Foundation; either version 2
9  * of the License, or (at your option) any later version.
10  *
11  * This program is distributed in the hope that it will be useful,
12  * but WITHOUT ANY WARRANTY; without even the implied warranty of
13  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
14  * GNU General Public License for more details.
15  *
16  * You should have received a copy of the GNU General Public License
17  * along with this program; if not, see
18  * <http://www.gnu.org/licenses/gpl-2.0.html>
19  */
20 
21 #include "qemu/osdep.h"
22 #include "qemu/error-report.h"
23 #include "qapi/error.h"
24 #include "cpu.h"
25 #include "internals.h"
26 #include "qemu-common.h"
27 #include "exec/exec-all.h"
28 #include "hw/qdev-properties.h"
29 #if !defined(CONFIG_USER_ONLY)
30 #include "hw/loader.h"
31 #endif
32 #include "hw/arm/arm.h"
33 #include "sysemu/sysemu.h"
34 #include "sysemu/hw_accel.h"
35 #include "kvm_arm.h"
36 
37 static void arm_cpu_set_pc(CPUState *cs, vaddr value)
38 {
39     ARMCPU *cpu = ARM_CPU(cs);
40 
41     cpu->env.regs[15] = value;
42 }
43 
44 static bool arm_cpu_has_work(CPUState *cs)
45 {
46     ARMCPU *cpu = ARM_CPU(cs);
47 
48     return !cpu->powered_off
49         && cs->interrupt_request &
50         (CPU_INTERRUPT_FIQ | CPU_INTERRUPT_HARD
51          | CPU_INTERRUPT_VFIQ | CPU_INTERRUPT_VIRQ
52          | CPU_INTERRUPT_EXITTB);
53 }
54 
55 void arm_register_el_change_hook(ARMCPU *cpu, ARMELChangeHook *hook,
56                                  void *opaque)
57 {
58     /* We currently only support registering a single hook function */
59     assert(!cpu->el_change_hook);
60     cpu->el_change_hook = hook;
61     cpu->el_change_hook_opaque = opaque;
62 }
63 
64 static void cp_reg_reset(gpointer key, gpointer value, gpointer opaque)
65 {
66     /* Reset a single ARMCPRegInfo register */
67     ARMCPRegInfo *ri = value;
68     ARMCPU *cpu = opaque;
69 
70     if (ri->type & (ARM_CP_SPECIAL | ARM_CP_ALIAS)) {
71         return;
72     }
73 
74     if (ri->resetfn) {
75         ri->resetfn(&cpu->env, ri);
76         return;
77     }
78 
79     /* A zero offset is never possible as it would be regs[0]
80      * so we use it to indicate that reset is being handled elsewhere.
81      * This is basically only used for fields in non-core coprocessors
82      * (like the pxa2xx ones).
83      */
84     if (!ri->fieldoffset) {
85         return;
86     }
87 
88     if (cpreg_field_is_64bit(ri)) {
89         CPREG_FIELD64(&cpu->env, ri) = ri->resetvalue;
90     } else {
91         CPREG_FIELD32(&cpu->env, ri) = ri->resetvalue;
92     }
93 }
94 
95 static void cp_reg_check_reset(gpointer key, gpointer value,  gpointer opaque)
96 {
97     /* Purely an assertion check: we've already done reset once,
98      * so now check that running the reset for the cpreg doesn't
99      * change its value. This traps bugs where two different cpregs
100      * both try to reset the same state field but to different values.
101      */
102     ARMCPRegInfo *ri = value;
103     ARMCPU *cpu = opaque;
104     uint64_t oldvalue, newvalue;
105 
106     if (ri->type & (ARM_CP_SPECIAL | ARM_CP_ALIAS | ARM_CP_NO_RAW)) {
107         return;
108     }
109 
110     oldvalue = read_raw_cp_reg(&cpu->env, ri);
111     cp_reg_reset(key, value, opaque);
112     newvalue = read_raw_cp_reg(&cpu->env, ri);
113     assert(oldvalue == newvalue);
114 }
115 
116 /* CPUClass::reset() */
117 static void arm_cpu_reset(CPUState *s)
118 {
119     ARMCPU *cpu = ARM_CPU(s);
120     ARMCPUClass *acc = ARM_CPU_GET_CLASS(cpu);
121     CPUARMState *env = &cpu->env;
122 
123     acc->parent_reset(s);
124 
125     memset(env, 0, offsetof(CPUARMState, end_reset_fields));
126 
127     g_hash_table_foreach(cpu->cp_regs, cp_reg_reset, cpu);
128     g_hash_table_foreach(cpu->cp_regs, cp_reg_check_reset, cpu);
129 
130     env->vfp.xregs[ARM_VFP_FPSID] = cpu->reset_fpsid;
131     env->vfp.xregs[ARM_VFP_MVFR0] = cpu->mvfr0;
132     env->vfp.xregs[ARM_VFP_MVFR1] = cpu->mvfr1;
133     env->vfp.xregs[ARM_VFP_MVFR2] = cpu->mvfr2;
134 
135     cpu->powered_off = cpu->start_powered_off;
136     s->halted = cpu->start_powered_off;
137 
138     if (arm_feature(env, ARM_FEATURE_IWMMXT)) {
139         env->iwmmxt.cregs[ARM_IWMMXT_wCID] = 0x69051000 | 'Q';
140     }
141 
142     if (arm_feature(env, ARM_FEATURE_AARCH64)) {
143         /* 64 bit CPUs always start in 64 bit mode */
144         env->aarch64 = 1;
145 #if defined(CONFIG_USER_ONLY)
146         env->pstate = PSTATE_MODE_EL0t;
147         /* Userspace expects access to DC ZVA, CTL_EL0 and the cache ops */
148         env->cp15.sctlr_el[1] |= SCTLR_UCT | SCTLR_UCI | SCTLR_DZE;
149         /* and to the FP/Neon instructions */
150         env->cp15.cpacr_el1 = deposit64(env->cp15.cpacr_el1, 20, 2, 3);
151 #else
152         /* Reset into the highest available EL */
153         if (arm_feature(env, ARM_FEATURE_EL3)) {
154             env->pstate = PSTATE_MODE_EL3h;
155         } else if (arm_feature(env, ARM_FEATURE_EL2)) {
156             env->pstate = PSTATE_MODE_EL2h;
157         } else {
158             env->pstate = PSTATE_MODE_EL1h;
159         }
160         env->pc = cpu->rvbar;
161 #endif
162     } else {
163 #if defined(CONFIG_USER_ONLY)
164         /* Userspace expects access to cp10 and cp11 for FP/Neon */
165         env->cp15.cpacr_el1 = deposit64(env->cp15.cpacr_el1, 20, 4, 0xf);
166 #endif
167     }
168 
169 #if defined(CONFIG_USER_ONLY)
170     env->uncached_cpsr = ARM_CPU_MODE_USR;
171     /* For user mode we must enable access to coprocessors */
172     env->vfp.xregs[ARM_VFP_FPEXC] = 1 << 30;
173     if (arm_feature(env, ARM_FEATURE_IWMMXT)) {
174         env->cp15.c15_cpar = 3;
175     } else if (arm_feature(env, ARM_FEATURE_XSCALE)) {
176         env->cp15.c15_cpar = 1;
177     }
178 #else
179     /* SVC mode with interrupts disabled.  */
180     env->uncached_cpsr = ARM_CPU_MODE_SVC;
181     env->daif = PSTATE_D | PSTATE_A | PSTATE_I | PSTATE_F;
182     /* On ARMv7-M the CPSR_I is the value of the PRIMASK register, and is
183      * clear at reset. Initial SP and PC are loaded from ROM.
184      */
185     if (IS_M(env)) {
186         uint32_t initial_msp; /* Loaded from 0x0 */
187         uint32_t initial_pc; /* Loaded from 0x4 */
188         uint8_t *rom;
189 
190         env->daif &= ~PSTATE_I;
191         rom = rom_ptr(0);
192         if (rom) {
193             /* Address zero is covered by ROM which hasn't yet been
194              * copied into physical memory.
195              */
196             initial_msp = ldl_p(rom);
197             initial_pc = ldl_p(rom + 4);
198         } else {
199             /* Address zero not covered by a ROM blob, or the ROM blob
200              * is in non-modifiable memory and this is a second reset after
201              * it got copied into memory. In the latter case, rom_ptr
202              * will return a NULL pointer and we should use ldl_phys instead.
203              */
204             initial_msp = ldl_phys(s->as, 0);
205             initial_pc = ldl_phys(s->as, 4);
206         }
207 
208         env->regs[13] = initial_msp & 0xFFFFFFFC;
209         env->regs[15] = initial_pc & ~1;
210         env->thumb = initial_pc & 1;
211     }
212 
213     /* AArch32 has a hard highvec setting of 0xFFFF0000.  If we are currently
214      * executing as AArch32 then check if highvecs are enabled and
215      * adjust the PC accordingly.
216      */
217     if (A32_BANKED_CURRENT_REG_GET(env, sctlr) & SCTLR_V) {
218         env->regs[15] = 0xFFFF0000;
219     }
220 
221     env->vfp.xregs[ARM_VFP_FPEXC] = 0;
222 #endif
223     set_flush_to_zero(1, &env->vfp.standard_fp_status);
224     set_flush_inputs_to_zero(1, &env->vfp.standard_fp_status);
225     set_default_nan_mode(1, &env->vfp.standard_fp_status);
226     set_float_detect_tininess(float_tininess_before_rounding,
227                               &env->vfp.fp_status);
228     set_float_detect_tininess(float_tininess_before_rounding,
229                               &env->vfp.standard_fp_status);
230 #ifndef CONFIG_USER_ONLY
231     if (kvm_enabled()) {
232         kvm_arm_reset_vcpu(cpu);
233     }
234 #endif
235 
236     hw_breakpoint_update_all(cpu);
237     hw_watchpoint_update_all(cpu);
238 }
239 
240 bool arm_cpu_exec_interrupt(CPUState *cs, int interrupt_request)
241 {
242     CPUClass *cc = CPU_GET_CLASS(cs);
243     CPUARMState *env = cs->env_ptr;
244     uint32_t cur_el = arm_current_el(env);
245     bool secure = arm_is_secure(env);
246     uint32_t target_el;
247     uint32_t excp_idx;
248     bool ret = false;
249 
250     if (interrupt_request & CPU_INTERRUPT_FIQ) {
251         excp_idx = EXCP_FIQ;
252         target_el = arm_phys_excp_target_el(cs, excp_idx, cur_el, secure);
253         if (arm_excp_unmasked(cs, excp_idx, target_el)) {
254             cs->exception_index = excp_idx;
255             env->exception.target_el = target_el;
256             cc->do_interrupt(cs);
257             ret = true;
258         }
259     }
260     if (interrupt_request & CPU_INTERRUPT_HARD) {
261         excp_idx = EXCP_IRQ;
262         target_el = arm_phys_excp_target_el(cs, excp_idx, cur_el, secure);
263         if (arm_excp_unmasked(cs, excp_idx, target_el)) {
264             cs->exception_index = excp_idx;
265             env->exception.target_el = target_el;
266             cc->do_interrupt(cs);
267             ret = true;
268         }
269     }
270     if (interrupt_request & CPU_INTERRUPT_VIRQ) {
271         excp_idx = EXCP_VIRQ;
272         target_el = 1;
273         if (arm_excp_unmasked(cs, excp_idx, target_el)) {
274             cs->exception_index = excp_idx;
275             env->exception.target_el = target_el;
276             cc->do_interrupt(cs);
277             ret = true;
278         }
279     }
280     if (interrupt_request & CPU_INTERRUPT_VFIQ) {
281         excp_idx = EXCP_VFIQ;
282         target_el = 1;
283         if (arm_excp_unmasked(cs, excp_idx, target_el)) {
284             cs->exception_index = excp_idx;
285             env->exception.target_el = target_el;
286             cc->do_interrupt(cs);
287             ret = true;
288         }
289     }
290 
291     return ret;
292 }
293 
294 #if !defined(CONFIG_USER_ONLY) || !defined(TARGET_AARCH64)
295 static bool arm_v7m_cpu_exec_interrupt(CPUState *cs, int interrupt_request)
296 {
297     CPUClass *cc = CPU_GET_CLASS(cs);
298     ARMCPU *cpu = ARM_CPU(cs);
299     CPUARMState *env = &cpu->env;
300     bool ret = false;
301 
302 
303     if (interrupt_request & CPU_INTERRUPT_FIQ
304         && !(env->daif & PSTATE_F)) {
305         cs->exception_index = EXCP_FIQ;
306         cc->do_interrupt(cs);
307         ret = true;
308     }
309     /* ARMv7-M interrupt return works by loading a magic value
310      * into the PC.  On real hardware the load causes the
311      * return to occur.  The qemu implementation performs the
312      * jump normally, then does the exception return when the
313      * CPU tries to execute code at the magic address.
314      * This will cause the magic PC value to be pushed to
315      * the stack if an interrupt occurred at the wrong time.
316      * We avoid this by disabling interrupts when
317      * pc contains a magic address.
318      */
319     if (interrupt_request & CPU_INTERRUPT_HARD
320         && !(env->daif & PSTATE_I)
321         && (env->regs[15] < 0xfffffff0)) {
322         cs->exception_index = EXCP_IRQ;
323         cc->do_interrupt(cs);
324         ret = true;
325     }
326     return ret;
327 }
328 #endif
329 
330 #ifndef CONFIG_USER_ONLY
331 static void arm_cpu_set_irq(void *opaque, int irq, int level)
332 {
333     ARMCPU *cpu = opaque;
334     CPUARMState *env = &cpu->env;
335     CPUState *cs = CPU(cpu);
336     static const int mask[] = {
337         [ARM_CPU_IRQ] = CPU_INTERRUPT_HARD,
338         [ARM_CPU_FIQ] = CPU_INTERRUPT_FIQ,
339         [ARM_CPU_VIRQ] = CPU_INTERRUPT_VIRQ,
340         [ARM_CPU_VFIQ] = CPU_INTERRUPT_VFIQ
341     };
342 
343     switch (irq) {
344     case ARM_CPU_VIRQ:
345     case ARM_CPU_VFIQ:
346         assert(arm_feature(env, ARM_FEATURE_EL2));
347         /* fall through */
348     case ARM_CPU_IRQ:
349     case ARM_CPU_FIQ:
350         if (level) {
351             cpu_interrupt(cs, mask[irq]);
352         } else {
353             cpu_reset_interrupt(cs, mask[irq]);
354         }
355         break;
356     default:
357         g_assert_not_reached();
358     }
359 }
360 
361 static void arm_cpu_kvm_set_irq(void *opaque, int irq, int level)
362 {
363 #ifdef CONFIG_KVM
364     ARMCPU *cpu = opaque;
365     CPUState *cs = CPU(cpu);
366     int kvm_irq = KVM_ARM_IRQ_TYPE_CPU << KVM_ARM_IRQ_TYPE_SHIFT;
367 
368     switch (irq) {
369     case ARM_CPU_IRQ:
370         kvm_irq |= KVM_ARM_IRQ_CPU_IRQ;
371         break;
372     case ARM_CPU_FIQ:
373         kvm_irq |= KVM_ARM_IRQ_CPU_FIQ;
374         break;
375     default:
376         g_assert_not_reached();
377     }
378     kvm_irq |= cs->cpu_index << KVM_ARM_IRQ_VCPU_SHIFT;
379     kvm_set_irq(kvm_state, kvm_irq, level ? 1 : 0);
380 #endif
381 }
382 
383 static bool arm_cpu_virtio_is_big_endian(CPUState *cs)
384 {
385     ARMCPU *cpu = ARM_CPU(cs);
386     CPUARMState *env = &cpu->env;
387 
388     cpu_synchronize_state(cs);
389     return arm_cpu_data_is_big_endian(env);
390 }
391 
392 #endif
393 
394 static inline void set_feature(CPUARMState *env, int feature)
395 {
396     env->features |= 1ULL << feature;
397 }
398 
399 static inline void unset_feature(CPUARMState *env, int feature)
400 {
401     env->features &= ~(1ULL << feature);
402 }
403 
404 static int
405 print_insn_thumb1(bfd_vma pc, disassemble_info *info)
406 {
407   return print_insn_arm(pc | 1, info);
408 }
409 
410 static void arm_disas_set_info(CPUState *cpu, disassemble_info *info)
411 {
412     ARMCPU *ac = ARM_CPU(cpu);
413     CPUARMState *env = &ac->env;
414 
415     if (is_a64(env)) {
416         /* We might not be compiled with the A64 disassembler
417          * because it needs a C++ compiler. Leave print_insn
418          * unset in this case to use the caller default behaviour.
419          */
420 #if defined(CONFIG_ARM_A64_DIS)
421         info->print_insn = print_insn_arm_a64;
422 #endif
423     } else if (env->thumb) {
424         info->print_insn = print_insn_thumb1;
425     } else {
426         info->print_insn = print_insn_arm;
427     }
428     if (bswap_code(arm_sctlr_b(env))) {
429 #ifdef TARGET_WORDS_BIGENDIAN
430         info->endian = BFD_ENDIAN_LITTLE;
431 #else
432         info->endian = BFD_ENDIAN_BIG;
433 #endif
434     }
435 }
436 
437 static void arm_cpu_initfn(Object *obj)
438 {
439     CPUState *cs = CPU(obj);
440     ARMCPU *cpu = ARM_CPU(obj);
441     static bool inited;
442 
443     cs->env_ptr = &cpu->env;
444     cpu->cp_regs = g_hash_table_new_full(g_int_hash, g_int_equal,
445                                          g_free, g_free);
446 
447 #ifndef CONFIG_USER_ONLY
448     /* Our inbound IRQ and FIQ lines */
449     if (kvm_enabled()) {
450         /* VIRQ and VFIQ are unused with KVM but we add them to maintain
451          * the same interface as non-KVM CPUs.
452          */
453         qdev_init_gpio_in(DEVICE(cpu), arm_cpu_kvm_set_irq, 4);
454     } else {
455         qdev_init_gpio_in(DEVICE(cpu), arm_cpu_set_irq, 4);
456     }
457 
458     cpu->gt_timer[GTIMER_PHYS] = timer_new(QEMU_CLOCK_VIRTUAL, GTIMER_SCALE,
459                                                 arm_gt_ptimer_cb, cpu);
460     cpu->gt_timer[GTIMER_VIRT] = timer_new(QEMU_CLOCK_VIRTUAL, GTIMER_SCALE,
461                                                 arm_gt_vtimer_cb, cpu);
462     cpu->gt_timer[GTIMER_HYP] = timer_new(QEMU_CLOCK_VIRTUAL, GTIMER_SCALE,
463                                                 arm_gt_htimer_cb, cpu);
464     cpu->gt_timer[GTIMER_SEC] = timer_new(QEMU_CLOCK_VIRTUAL, GTIMER_SCALE,
465                                                 arm_gt_stimer_cb, cpu);
466     qdev_init_gpio_out(DEVICE(cpu), cpu->gt_timer_outputs,
467                        ARRAY_SIZE(cpu->gt_timer_outputs));
468 
469     qdev_init_gpio_out_named(DEVICE(cpu), &cpu->gicv3_maintenance_interrupt,
470                              "gicv3-maintenance-interrupt", 1);
471 #endif
472 
473     /* DTB consumers generally don't in fact care what the 'compatible'
474      * string is, so always provide some string and trust that a hypothetical
475      * picky DTB consumer will also provide a helpful error message.
476      */
477     cpu->dtb_compatible = "qemu,unknown";
478     cpu->psci_version = 1; /* By default assume PSCI v0.1 */
479     cpu->kvm_target = QEMU_KVM_ARM_TARGET_NONE;
480 
481     if (tcg_enabled()) {
482         cpu->psci_version = 2; /* TCG implements PSCI 0.2 */
483         if (!inited) {
484             inited = true;
485             arm_translate_init();
486         }
487     }
488 }
489 
490 static Property arm_cpu_reset_cbar_property =
491             DEFINE_PROP_UINT64("reset-cbar", ARMCPU, reset_cbar, 0);
492 
493 static Property arm_cpu_reset_hivecs_property =
494             DEFINE_PROP_BOOL("reset-hivecs", ARMCPU, reset_hivecs, false);
495 
496 static Property arm_cpu_rvbar_property =
497             DEFINE_PROP_UINT64("rvbar", ARMCPU, rvbar, 0);
498 
499 static Property arm_cpu_has_el2_property =
500             DEFINE_PROP_BOOL("has_el2", ARMCPU, has_el2, true);
501 
502 static Property arm_cpu_has_el3_property =
503             DEFINE_PROP_BOOL("has_el3", ARMCPU, has_el3, true);
504 
505 /* use property name "pmu" to match other archs and virt tools */
506 static Property arm_cpu_has_pmu_property =
507             DEFINE_PROP_BOOL("pmu", ARMCPU, has_pmu, true);
508 
509 static Property arm_cpu_has_mpu_property =
510             DEFINE_PROP_BOOL("has-mpu", ARMCPU, has_mpu, true);
511 
512 static Property arm_cpu_pmsav7_dregion_property =
513             DEFINE_PROP_UINT32("pmsav7-dregion", ARMCPU, pmsav7_dregion, 16);
514 
515 static void arm_cpu_post_init(Object *obj)
516 {
517     ARMCPU *cpu = ARM_CPU(obj);
518 
519     if (arm_feature(&cpu->env, ARM_FEATURE_CBAR) ||
520         arm_feature(&cpu->env, ARM_FEATURE_CBAR_RO)) {
521         qdev_property_add_static(DEVICE(obj), &arm_cpu_reset_cbar_property,
522                                  &error_abort);
523     }
524 
525     if (!arm_feature(&cpu->env, ARM_FEATURE_M)) {
526         qdev_property_add_static(DEVICE(obj), &arm_cpu_reset_hivecs_property,
527                                  &error_abort);
528     }
529 
530     if (arm_feature(&cpu->env, ARM_FEATURE_AARCH64)) {
531         qdev_property_add_static(DEVICE(obj), &arm_cpu_rvbar_property,
532                                  &error_abort);
533     }
534 
535     if (arm_feature(&cpu->env, ARM_FEATURE_EL3)) {
536         /* Add the has_el3 state CPU property only if EL3 is allowed.  This will
537          * prevent "has_el3" from existing on CPUs which cannot support EL3.
538          */
539         qdev_property_add_static(DEVICE(obj), &arm_cpu_has_el3_property,
540                                  &error_abort);
541 
542 #ifndef CONFIG_USER_ONLY
543         object_property_add_link(obj, "secure-memory",
544                                  TYPE_MEMORY_REGION,
545                                  (Object **)&cpu->secure_memory,
546                                  qdev_prop_allow_set_link_before_realize,
547                                  OBJ_PROP_LINK_UNREF_ON_RELEASE,
548                                  &error_abort);
549 #endif
550     }
551 
552     if (arm_feature(&cpu->env, ARM_FEATURE_EL2)) {
553         qdev_property_add_static(DEVICE(obj), &arm_cpu_has_el2_property,
554                                  &error_abort);
555     }
556 
557     if (arm_feature(&cpu->env, ARM_FEATURE_PMU)) {
558         qdev_property_add_static(DEVICE(obj), &arm_cpu_has_pmu_property,
559                                  &error_abort);
560     }
561 
562     if (arm_feature(&cpu->env, ARM_FEATURE_MPU)) {
563         qdev_property_add_static(DEVICE(obj), &arm_cpu_has_mpu_property,
564                                  &error_abort);
565         if (arm_feature(&cpu->env, ARM_FEATURE_V7)) {
566             qdev_property_add_static(DEVICE(obj),
567                                      &arm_cpu_pmsav7_dregion_property,
568                                      &error_abort);
569         }
570     }
571 
572 }
573 
574 static void arm_cpu_finalizefn(Object *obj)
575 {
576     ARMCPU *cpu = ARM_CPU(obj);
577     g_hash_table_destroy(cpu->cp_regs);
578 }
579 
580 static void arm_cpu_realizefn(DeviceState *dev, Error **errp)
581 {
582     CPUState *cs = CPU(dev);
583     ARMCPU *cpu = ARM_CPU(dev);
584     ARMCPUClass *acc = ARM_CPU_GET_CLASS(dev);
585     CPUARMState *env = &cpu->env;
586     int pagebits;
587     Error *local_err = NULL;
588 
589     cpu_exec_realizefn(cs, &local_err);
590     if (local_err != NULL) {
591         error_propagate(errp, local_err);
592         return;
593     }
594 
595     /* Some features automatically imply others: */
596     if (arm_feature(env, ARM_FEATURE_V8)) {
597         set_feature(env, ARM_FEATURE_V7);
598         set_feature(env, ARM_FEATURE_ARM_DIV);
599         set_feature(env, ARM_FEATURE_LPAE);
600     }
601     if (arm_feature(env, ARM_FEATURE_V7)) {
602         set_feature(env, ARM_FEATURE_VAPA);
603         set_feature(env, ARM_FEATURE_THUMB2);
604         set_feature(env, ARM_FEATURE_MPIDR);
605         if (!arm_feature(env, ARM_FEATURE_M)) {
606             set_feature(env, ARM_FEATURE_V6K);
607         } else {
608             set_feature(env, ARM_FEATURE_V6);
609         }
610 
611         /* Always define VBAR for V7 CPUs even if it doesn't exist in
612          * non-EL3 configs. This is needed by some legacy boards.
613          */
614         set_feature(env, ARM_FEATURE_VBAR);
615     }
616     if (arm_feature(env, ARM_FEATURE_V6K)) {
617         set_feature(env, ARM_FEATURE_V6);
618         set_feature(env, ARM_FEATURE_MVFR);
619     }
620     if (arm_feature(env, ARM_FEATURE_V6)) {
621         set_feature(env, ARM_FEATURE_V5);
622         if (!arm_feature(env, ARM_FEATURE_M)) {
623             set_feature(env, ARM_FEATURE_AUXCR);
624         }
625     }
626     if (arm_feature(env, ARM_FEATURE_V5)) {
627         set_feature(env, ARM_FEATURE_V4T);
628     }
629     if (arm_feature(env, ARM_FEATURE_M)) {
630         set_feature(env, ARM_FEATURE_THUMB_DIV);
631     }
632     if (arm_feature(env, ARM_FEATURE_ARM_DIV)) {
633         set_feature(env, ARM_FEATURE_THUMB_DIV);
634     }
635     if (arm_feature(env, ARM_FEATURE_VFP4)) {
636         set_feature(env, ARM_FEATURE_VFP3);
637         set_feature(env, ARM_FEATURE_VFP_FP16);
638     }
639     if (arm_feature(env, ARM_FEATURE_VFP3)) {
640         set_feature(env, ARM_FEATURE_VFP);
641     }
642     if (arm_feature(env, ARM_FEATURE_LPAE)) {
643         set_feature(env, ARM_FEATURE_V7MP);
644         set_feature(env, ARM_FEATURE_PXN);
645     }
646     if (arm_feature(env, ARM_FEATURE_CBAR_RO)) {
647         set_feature(env, ARM_FEATURE_CBAR);
648     }
649     if (arm_feature(env, ARM_FEATURE_THUMB2) &&
650         !arm_feature(env, ARM_FEATURE_M)) {
651         set_feature(env, ARM_FEATURE_THUMB_DSP);
652     }
653 
654     if (arm_feature(env, ARM_FEATURE_V7) &&
655         !arm_feature(env, ARM_FEATURE_M) &&
656         !arm_feature(env, ARM_FEATURE_MPU)) {
657         /* v7VMSA drops support for the old ARMv5 tiny pages, so we
658          * can use 4K pages.
659          */
660         pagebits = 12;
661     } else {
662         /* For CPUs which might have tiny 1K pages, or which have an
663          * MPU and might have small region sizes, stick with 1K pages.
664          */
665         pagebits = 10;
666     }
667     if (!set_preferred_target_page_bits(pagebits)) {
668         /* This can only ever happen for hotplugging a CPU, or if
669          * the board code incorrectly creates a CPU which it has
670          * promised via minimum_page_size that it will not.
671          */
672         error_setg(errp, "This CPU requires a smaller page size than the "
673                    "system is using");
674         return;
675     }
676 
677     /* This cpu-id-to-MPIDR affinity is used only for TCG; KVM will override it.
678      * We don't support setting cluster ID ([16..23]) (known as Aff2
679      * in later ARM ARM versions), or any of the higher affinity level fields,
680      * so these bits always RAZ.
681      */
682     if (cpu->mp_affinity == ARM64_AFFINITY_INVALID) {
683         uint32_t Aff1 = cs->cpu_index / ARM_DEFAULT_CPUS_PER_CLUSTER;
684         uint32_t Aff0 = cs->cpu_index % ARM_DEFAULT_CPUS_PER_CLUSTER;
685         cpu->mp_affinity = (Aff1 << ARM_AFF1_SHIFT) | Aff0;
686     }
687 
688     if (cpu->reset_hivecs) {
689             cpu->reset_sctlr |= (1 << 13);
690     }
691 
692     if (!cpu->has_el3) {
693         /* If the has_el3 CPU property is disabled then we need to disable the
694          * feature.
695          */
696         unset_feature(env, ARM_FEATURE_EL3);
697 
698         /* Disable the security extension feature bits in the processor feature
699          * registers as well. These are id_pfr1[7:4] and id_aa64pfr0[15:12].
700          */
701         cpu->id_pfr1 &= ~0xf0;
702         cpu->id_aa64pfr0 &= ~0xf000;
703     }
704 
705     if (!cpu->has_el2) {
706         unset_feature(env, ARM_FEATURE_EL2);
707     }
708 
709     if (!cpu->has_pmu || !kvm_enabled()) {
710         cpu->has_pmu = false;
711         unset_feature(env, ARM_FEATURE_PMU);
712     }
713 
714     if (!arm_feature(env, ARM_FEATURE_EL2)) {
715         /* Disable the hypervisor feature bits in the processor feature
716          * registers if we don't have EL2. These are id_pfr1[15:12] and
717          * id_aa64pfr0_el1[11:8].
718          */
719         cpu->id_aa64pfr0 &= ~0xf00;
720         cpu->id_pfr1 &= ~0xf000;
721     }
722 
723     if (!cpu->has_mpu) {
724         unset_feature(env, ARM_FEATURE_MPU);
725     }
726 
727     if (arm_feature(env, ARM_FEATURE_MPU) &&
728         arm_feature(env, ARM_FEATURE_V7)) {
729         uint32_t nr = cpu->pmsav7_dregion;
730 
731         if (nr > 0xff) {
732             error_setg(errp, "PMSAv7 MPU #regions invalid %" PRIu32, nr);
733             return;
734         }
735 
736         if (nr) {
737             env->pmsav7.drbar = g_new0(uint32_t, nr);
738             env->pmsav7.drsr = g_new0(uint32_t, nr);
739             env->pmsav7.dracr = g_new0(uint32_t, nr);
740         }
741     }
742 
743     if (arm_feature(env, ARM_FEATURE_EL3)) {
744         set_feature(env, ARM_FEATURE_VBAR);
745     }
746 
747     register_cp_regs_for_features(cpu);
748     arm_cpu_register_gdb_regs_for_features(cpu);
749 
750     init_cpreg_list(cpu);
751 
752 #ifndef CONFIG_USER_ONLY
753     if (cpu->has_el3) {
754         cs->num_ases = 2;
755     } else {
756         cs->num_ases = 1;
757     }
758 
759     if (cpu->has_el3) {
760         AddressSpace *as;
761 
762         if (!cpu->secure_memory) {
763             cpu->secure_memory = cs->memory;
764         }
765         as = address_space_init_shareable(cpu->secure_memory,
766                                           "cpu-secure-memory");
767         cpu_address_space_init(cs, as, ARMASIdx_S);
768     }
769     cpu_address_space_init(cs,
770                            address_space_init_shareable(cs->memory,
771                                                         "cpu-memory"),
772                            ARMASIdx_NS);
773 #endif
774 
775     qemu_init_vcpu(cs);
776     cpu_reset(cs);
777 
778     acc->parent_realize(dev, errp);
779 }
780 
781 static ObjectClass *arm_cpu_class_by_name(const char *cpu_model)
782 {
783     ObjectClass *oc;
784     char *typename;
785     char **cpuname;
786 
787     if (!cpu_model) {
788         return NULL;
789     }
790 
791     cpuname = g_strsplit(cpu_model, ",", 1);
792     typename = g_strdup_printf("%s-" TYPE_ARM_CPU, cpuname[0]);
793     oc = object_class_by_name(typename);
794     g_strfreev(cpuname);
795     g_free(typename);
796     if (!oc || !object_class_dynamic_cast(oc, TYPE_ARM_CPU) ||
797         object_class_is_abstract(oc)) {
798         return NULL;
799     }
800     return oc;
801 }
802 
803 /* CPU models. These are not needed for the AArch64 linux-user build. */
804 #if !defined(CONFIG_USER_ONLY) || !defined(TARGET_AARCH64)
805 
806 static void arm926_initfn(Object *obj)
807 {
808     ARMCPU *cpu = ARM_CPU(obj);
809 
810     cpu->dtb_compatible = "arm,arm926";
811     set_feature(&cpu->env, ARM_FEATURE_V5);
812     set_feature(&cpu->env, ARM_FEATURE_VFP);
813     set_feature(&cpu->env, ARM_FEATURE_DUMMY_C15_REGS);
814     set_feature(&cpu->env, ARM_FEATURE_CACHE_TEST_CLEAN);
815     cpu->midr = 0x41069265;
816     cpu->reset_fpsid = 0x41011090;
817     cpu->ctr = 0x1dd20d2;
818     cpu->reset_sctlr = 0x00090078;
819 }
820 
821 static void arm946_initfn(Object *obj)
822 {
823     ARMCPU *cpu = ARM_CPU(obj);
824 
825     cpu->dtb_compatible = "arm,arm946";
826     set_feature(&cpu->env, ARM_FEATURE_V5);
827     set_feature(&cpu->env, ARM_FEATURE_MPU);
828     set_feature(&cpu->env, ARM_FEATURE_DUMMY_C15_REGS);
829     cpu->midr = 0x41059461;
830     cpu->ctr = 0x0f004006;
831     cpu->reset_sctlr = 0x00000078;
832 }
833 
834 static void arm1026_initfn(Object *obj)
835 {
836     ARMCPU *cpu = ARM_CPU(obj);
837 
838     cpu->dtb_compatible = "arm,arm1026";
839     set_feature(&cpu->env, ARM_FEATURE_V5);
840     set_feature(&cpu->env, ARM_FEATURE_VFP);
841     set_feature(&cpu->env, ARM_FEATURE_AUXCR);
842     set_feature(&cpu->env, ARM_FEATURE_DUMMY_C15_REGS);
843     set_feature(&cpu->env, ARM_FEATURE_CACHE_TEST_CLEAN);
844     cpu->midr = 0x4106a262;
845     cpu->reset_fpsid = 0x410110a0;
846     cpu->ctr = 0x1dd20d2;
847     cpu->reset_sctlr = 0x00090078;
848     cpu->reset_auxcr = 1;
849     {
850         /* The 1026 had an IFAR at c6,c0,0,1 rather than the ARMv6 c6,c0,0,2 */
851         ARMCPRegInfo ifar = {
852             .name = "IFAR", .cp = 15, .crn = 6, .crm = 0, .opc1 = 0, .opc2 = 1,
853             .access = PL1_RW,
854             .fieldoffset = offsetof(CPUARMState, cp15.ifar_ns),
855             .resetvalue = 0
856         };
857         define_one_arm_cp_reg(cpu, &ifar);
858     }
859 }
860 
861 static void arm1136_r2_initfn(Object *obj)
862 {
863     ARMCPU *cpu = ARM_CPU(obj);
864     /* What qemu calls "arm1136_r2" is actually the 1136 r0p2, ie an
865      * older core than plain "arm1136". In particular this does not
866      * have the v6K features.
867      * These ID register values are correct for 1136 but may be wrong
868      * for 1136_r2 (in particular r0p2 does not actually implement most
869      * of the ID registers).
870      */
871 
872     cpu->dtb_compatible = "arm,arm1136";
873     set_feature(&cpu->env, ARM_FEATURE_V6);
874     set_feature(&cpu->env, ARM_FEATURE_VFP);
875     set_feature(&cpu->env, ARM_FEATURE_DUMMY_C15_REGS);
876     set_feature(&cpu->env, ARM_FEATURE_CACHE_DIRTY_REG);
877     set_feature(&cpu->env, ARM_FEATURE_CACHE_BLOCK_OPS);
878     cpu->midr = 0x4107b362;
879     cpu->reset_fpsid = 0x410120b4;
880     cpu->mvfr0 = 0x11111111;
881     cpu->mvfr1 = 0x00000000;
882     cpu->ctr = 0x1dd20d2;
883     cpu->reset_sctlr = 0x00050078;
884     cpu->id_pfr0 = 0x111;
885     cpu->id_pfr1 = 0x1;
886     cpu->id_dfr0 = 0x2;
887     cpu->id_afr0 = 0x3;
888     cpu->id_mmfr0 = 0x01130003;
889     cpu->id_mmfr1 = 0x10030302;
890     cpu->id_mmfr2 = 0x01222110;
891     cpu->id_isar0 = 0x00140011;
892     cpu->id_isar1 = 0x12002111;
893     cpu->id_isar2 = 0x11231111;
894     cpu->id_isar3 = 0x01102131;
895     cpu->id_isar4 = 0x141;
896     cpu->reset_auxcr = 7;
897 }
898 
899 static void arm1136_initfn(Object *obj)
900 {
901     ARMCPU *cpu = ARM_CPU(obj);
902 
903     cpu->dtb_compatible = "arm,arm1136";
904     set_feature(&cpu->env, ARM_FEATURE_V6K);
905     set_feature(&cpu->env, ARM_FEATURE_V6);
906     set_feature(&cpu->env, ARM_FEATURE_VFP);
907     set_feature(&cpu->env, ARM_FEATURE_DUMMY_C15_REGS);
908     set_feature(&cpu->env, ARM_FEATURE_CACHE_DIRTY_REG);
909     set_feature(&cpu->env, ARM_FEATURE_CACHE_BLOCK_OPS);
910     cpu->midr = 0x4117b363;
911     cpu->reset_fpsid = 0x410120b4;
912     cpu->mvfr0 = 0x11111111;
913     cpu->mvfr1 = 0x00000000;
914     cpu->ctr = 0x1dd20d2;
915     cpu->reset_sctlr = 0x00050078;
916     cpu->id_pfr0 = 0x111;
917     cpu->id_pfr1 = 0x1;
918     cpu->id_dfr0 = 0x2;
919     cpu->id_afr0 = 0x3;
920     cpu->id_mmfr0 = 0x01130003;
921     cpu->id_mmfr1 = 0x10030302;
922     cpu->id_mmfr2 = 0x01222110;
923     cpu->id_isar0 = 0x00140011;
924     cpu->id_isar1 = 0x12002111;
925     cpu->id_isar2 = 0x11231111;
926     cpu->id_isar3 = 0x01102131;
927     cpu->id_isar4 = 0x141;
928     cpu->reset_auxcr = 7;
929 }
930 
931 static void arm1176_initfn(Object *obj)
932 {
933     ARMCPU *cpu = ARM_CPU(obj);
934 
935     cpu->dtb_compatible = "arm,arm1176";
936     set_feature(&cpu->env, ARM_FEATURE_V6K);
937     set_feature(&cpu->env, ARM_FEATURE_VFP);
938     set_feature(&cpu->env, ARM_FEATURE_VAPA);
939     set_feature(&cpu->env, ARM_FEATURE_DUMMY_C15_REGS);
940     set_feature(&cpu->env, ARM_FEATURE_CACHE_DIRTY_REG);
941     set_feature(&cpu->env, ARM_FEATURE_CACHE_BLOCK_OPS);
942     set_feature(&cpu->env, ARM_FEATURE_EL3);
943     cpu->midr = 0x410fb767;
944     cpu->reset_fpsid = 0x410120b5;
945     cpu->mvfr0 = 0x11111111;
946     cpu->mvfr1 = 0x00000000;
947     cpu->ctr = 0x1dd20d2;
948     cpu->reset_sctlr = 0x00050078;
949     cpu->id_pfr0 = 0x111;
950     cpu->id_pfr1 = 0x11;
951     cpu->id_dfr0 = 0x33;
952     cpu->id_afr0 = 0;
953     cpu->id_mmfr0 = 0x01130003;
954     cpu->id_mmfr1 = 0x10030302;
955     cpu->id_mmfr2 = 0x01222100;
956     cpu->id_isar0 = 0x0140011;
957     cpu->id_isar1 = 0x12002111;
958     cpu->id_isar2 = 0x11231121;
959     cpu->id_isar3 = 0x01102131;
960     cpu->id_isar4 = 0x01141;
961     cpu->reset_auxcr = 7;
962 }
963 
964 static void arm11mpcore_initfn(Object *obj)
965 {
966     ARMCPU *cpu = ARM_CPU(obj);
967 
968     cpu->dtb_compatible = "arm,arm11mpcore";
969     set_feature(&cpu->env, ARM_FEATURE_V6K);
970     set_feature(&cpu->env, ARM_FEATURE_VFP);
971     set_feature(&cpu->env, ARM_FEATURE_VAPA);
972     set_feature(&cpu->env, ARM_FEATURE_MPIDR);
973     set_feature(&cpu->env, ARM_FEATURE_DUMMY_C15_REGS);
974     cpu->midr = 0x410fb022;
975     cpu->reset_fpsid = 0x410120b4;
976     cpu->mvfr0 = 0x11111111;
977     cpu->mvfr1 = 0x00000000;
978     cpu->ctr = 0x1d192992; /* 32K icache 32K dcache */
979     cpu->id_pfr0 = 0x111;
980     cpu->id_pfr1 = 0x1;
981     cpu->id_dfr0 = 0;
982     cpu->id_afr0 = 0x2;
983     cpu->id_mmfr0 = 0x01100103;
984     cpu->id_mmfr1 = 0x10020302;
985     cpu->id_mmfr2 = 0x01222000;
986     cpu->id_isar0 = 0x00100011;
987     cpu->id_isar1 = 0x12002111;
988     cpu->id_isar2 = 0x11221011;
989     cpu->id_isar3 = 0x01102131;
990     cpu->id_isar4 = 0x141;
991     cpu->reset_auxcr = 1;
992 }
993 
994 static void cortex_m3_initfn(Object *obj)
995 {
996     ARMCPU *cpu = ARM_CPU(obj);
997     set_feature(&cpu->env, ARM_FEATURE_V7);
998     set_feature(&cpu->env, ARM_FEATURE_M);
999     cpu->midr = 0x410fc231;
1000 }
1001 
1002 static void cortex_m4_initfn(Object *obj)
1003 {
1004     ARMCPU *cpu = ARM_CPU(obj);
1005 
1006     set_feature(&cpu->env, ARM_FEATURE_V7);
1007     set_feature(&cpu->env, ARM_FEATURE_M);
1008     set_feature(&cpu->env, ARM_FEATURE_THUMB_DSP);
1009     cpu->midr = 0x410fc240; /* r0p0 */
1010 }
1011 static void arm_v7m_class_init(ObjectClass *oc, void *data)
1012 {
1013     CPUClass *cc = CPU_CLASS(oc);
1014 
1015 #ifndef CONFIG_USER_ONLY
1016     cc->do_interrupt = arm_v7m_cpu_do_interrupt;
1017 #endif
1018 
1019     cc->cpu_exec_interrupt = arm_v7m_cpu_exec_interrupt;
1020 }
1021 
1022 static const ARMCPRegInfo cortexr5_cp_reginfo[] = {
1023     /* Dummy the TCM region regs for the moment */
1024     { .name = "ATCM", .cp = 15, .opc1 = 0, .crn = 9, .crm = 1, .opc2 = 0,
1025       .access = PL1_RW, .type = ARM_CP_CONST },
1026     { .name = "BTCM", .cp = 15, .opc1 = 0, .crn = 9, .crm = 1, .opc2 = 1,
1027       .access = PL1_RW, .type = ARM_CP_CONST },
1028     REGINFO_SENTINEL
1029 };
1030 
1031 static void cortex_r5_initfn(Object *obj)
1032 {
1033     ARMCPU *cpu = ARM_CPU(obj);
1034 
1035     set_feature(&cpu->env, ARM_FEATURE_V7);
1036     set_feature(&cpu->env, ARM_FEATURE_THUMB_DIV);
1037     set_feature(&cpu->env, ARM_FEATURE_ARM_DIV);
1038     set_feature(&cpu->env, ARM_FEATURE_V7MP);
1039     set_feature(&cpu->env, ARM_FEATURE_MPU);
1040     cpu->midr = 0x411fc153; /* r1p3 */
1041     cpu->id_pfr0 = 0x0131;
1042     cpu->id_pfr1 = 0x001;
1043     cpu->id_dfr0 = 0x010400;
1044     cpu->id_afr0 = 0x0;
1045     cpu->id_mmfr0 = 0x0210030;
1046     cpu->id_mmfr1 = 0x00000000;
1047     cpu->id_mmfr2 = 0x01200000;
1048     cpu->id_mmfr3 = 0x0211;
1049     cpu->id_isar0 = 0x2101111;
1050     cpu->id_isar1 = 0x13112111;
1051     cpu->id_isar2 = 0x21232141;
1052     cpu->id_isar3 = 0x01112131;
1053     cpu->id_isar4 = 0x0010142;
1054     cpu->id_isar5 = 0x0;
1055     cpu->mp_is_up = true;
1056     define_arm_cp_regs(cpu, cortexr5_cp_reginfo);
1057 }
1058 
1059 static const ARMCPRegInfo cortexa8_cp_reginfo[] = {
1060     { .name = "L2LOCKDOWN", .cp = 15, .crn = 9, .crm = 0, .opc1 = 1, .opc2 = 0,
1061       .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0 },
1062     { .name = "L2AUXCR", .cp = 15, .crn = 9, .crm = 0, .opc1 = 1, .opc2 = 2,
1063       .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0 },
1064     REGINFO_SENTINEL
1065 };
1066 
1067 static void cortex_a8_initfn(Object *obj)
1068 {
1069     ARMCPU *cpu = ARM_CPU(obj);
1070 
1071     cpu->dtb_compatible = "arm,cortex-a8";
1072     set_feature(&cpu->env, ARM_FEATURE_V7);
1073     set_feature(&cpu->env, ARM_FEATURE_VFP3);
1074     set_feature(&cpu->env, ARM_FEATURE_NEON);
1075     set_feature(&cpu->env, ARM_FEATURE_THUMB2EE);
1076     set_feature(&cpu->env, ARM_FEATURE_DUMMY_C15_REGS);
1077     set_feature(&cpu->env, ARM_FEATURE_EL3);
1078     cpu->midr = 0x410fc080;
1079     cpu->reset_fpsid = 0x410330c0;
1080     cpu->mvfr0 = 0x11110222;
1081     cpu->mvfr1 = 0x00011111;
1082     cpu->ctr = 0x82048004;
1083     cpu->reset_sctlr = 0x00c50078;
1084     cpu->id_pfr0 = 0x1031;
1085     cpu->id_pfr1 = 0x11;
1086     cpu->id_dfr0 = 0x400;
1087     cpu->id_afr0 = 0;
1088     cpu->id_mmfr0 = 0x31100003;
1089     cpu->id_mmfr1 = 0x20000000;
1090     cpu->id_mmfr2 = 0x01202000;
1091     cpu->id_mmfr3 = 0x11;
1092     cpu->id_isar0 = 0x00101111;
1093     cpu->id_isar1 = 0x12112111;
1094     cpu->id_isar2 = 0x21232031;
1095     cpu->id_isar3 = 0x11112131;
1096     cpu->id_isar4 = 0x00111142;
1097     cpu->dbgdidr = 0x15141000;
1098     cpu->clidr = (1 << 27) | (2 << 24) | 3;
1099     cpu->ccsidr[0] = 0xe007e01a; /* 16k L1 dcache. */
1100     cpu->ccsidr[1] = 0x2007e01a; /* 16k L1 icache. */
1101     cpu->ccsidr[2] = 0xf0000000; /* No L2 icache. */
1102     cpu->reset_auxcr = 2;
1103     define_arm_cp_regs(cpu, cortexa8_cp_reginfo);
1104 }
1105 
1106 static const ARMCPRegInfo cortexa9_cp_reginfo[] = {
1107     /* power_control should be set to maximum latency. Again,
1108      * default to 0 and set by private hook
1109      */
1110     { .name = "A9_PWRCTL", .cp = 15, .crn = 15, .crm = 0, .opc1 = 0, .opc2 = 0,
1111       .access = PL1_RW, .resetvalue = 0,
1112       .fieldoffset = offsetof(CPUARMState, cp15.c15_power_control) },
1113     { .name = "A9_DIAG", .cp = 15, .crn = 15, .crm = 0, .opc1 = 0, .opc2 = 1,
1114       .access = PL1_RW, .resetvalue = 0,
1115       .fieldoffset = offsetof(CPUARMState, cp15.c15_diagnostic) },
1116     { .name = "A9_PWRDIAG", .cp = 15, .crn = 15, .crm = 0, .opc1 = 0, .opc2 = 2,
1117       .access = PL1_RW, .resetvalue = 0,
1118       .fieldoffset = offsetof(CPUARMState, cp15.c15_power_diagnostic) },
1119     { .name = "NEONBUSY", .cp = 15, .crn = 15, .crm = 1, .opc1 = 0, .opc2 = 0,
1120       .access = PL1_RW, .resetvalue = 0, .type = ARM_CP_CONST },
1121     /* TLB lockdown control */
1122     { .name = "TLB_LOCKR", .cp = 15, .crn = 15, .crm = 4, .opc1 = 5, .opc2 = 2,
1123       .access = PL1_W, .resetvalue = 0, .type = ARM_CP_NOP },
1124     { .name = "TLB_LOCKW", .cp = 15, .crn = 15, .crm = 4, .opc1 = 5, .opc2 = 4,
1125       .access = PL1_W, .resetvalue = 0, .type = ARM_CP_NOP },
1126     { .name = "TLB_VA", .cp = 15, .crn = 15, .crm = 5, .opc1 = 5, .opc2 = 2,
1127       .access = PL1_RW, .resetvalue = 0, .type = ARM_CP_CONST },
1128     { .name = "TLB_PA", .cp = 15, .crn = 15, .crm = 6, .opc1 = 5, .opc2 = 2,
1129       .access = PL1_RW, .resetvalue = 0, .type = ARM_CP_CONST },
1130     { .name = "TLB_ATTR", .cp = 15, .crn = 15, .crm = 7, .opc1 = 5, .opc2 = 2,
1131       .access = PL1_RW, .resetvalue = 0, .type = ARM_CP_CONST },
1132     REGINFO_SENTINEL
1133 };
1134 
1135 static void cortex_a9_initfn(Object *obj)
1136 {
1137     ARMCPU *cpu = ARM_CPU(obj);
1138 
1139     cpu->dtb_compatible = "arm,cortex-a9";
1140     set_feature(&cpu->env, ARM_FEATURE_V7);
1141     set_feature(&cpu->env, ARM_FEATURE_VFP3);
1142     set_feature(&cpu->env, ARM_FEATURE_VFP_FP16);
1143     set_feature(&cpu->env, ARM_FEATURE_NEON);
1144     set_feature(&cpu->env, ARM_FEATURE_THUMB2EE);
1145     set_feature(&cpu->env, ARM_FEATURE_EL3);
1146     /* Note that A9 supports the MP extensions even for
1147      * A9UP and single-core A9MP (which are both different
1148      * and valid configurations; we don't model A9UP).
1149      */
1150     set_feature(&cpu->env, ARM_FEATURE_V7MP);
1151     set_feature(&cpu->env, ARM_FEATURE_CBAR);
1152     cpu->midr = 0x410fc090;
1153     cpu->reset_fpsid = 0x41033090;
1154     cpu->mvfr0 = 0x11110222;
1155     cpu->mvfr1 = 0x01111111;
1156     cpu->ctr = 0x80038003;
1157     cpu->reset_sctlr = 0x00c50078;
1158     cpu->id_pfr0 = 0x1031;
1159     cpu->id_pfr1 = 0x11;
1160     cpu->id_dfr0 = 0x000;
1161     cpu->id_afr0 = 0;
1162     cpu->id_mmfr0 = 0x00100103;
1163     cpu->id_mmfr1 = 0x20000000;
1164     cpu->id_mmfr2 = 0x01230000;
1165     cpu->id_mmfr3 = 0x00002111;
1166     cpu->id_isar0 = 0x00101111;
1167     cpu->id_isar1 = 0x13112111;
1168     cpu->id_isar2 = 0x21232041;
1169     cpu->id_isar3 = 0x11112131;
1170     cpu->id_isar4 = 0x00111142;
1171     cpu->dbgdidr = 0x35141000;
1172     cpu->clidr = (1 << 27) | (1 << 24) | 3;
1173     cpu->ccsidr[0] = 0xe00fe019; /* 16k L1 dcache. */
1174     cpu->ccsidr[1] = 0x200fe019; /* 16k L1 icache. */
1175     define_arm_cp_regs(cpu, cortexa9_cp_reginfo);
1176 }
1177 
1178 #ifndef CONFIG_USER_ONLY
1179 static uint64_t a15_l2ctlr_read(CPUARMState *env, const ARMCPRegInfo *ri)
1180 {
1181     /* Linux wants the number of processors from here.
1182      * Might as well set the interrupt-controller bit too.
1183      */
1184     return ((smp_cpus - 1) << 24) | (1 << 23);
1185 }
1186 #endif
1187 
1188 static const ARMCPRegInfo cortexa15_cp_reginfo[] = {
1189 #ifndef CONFIG_USER_ONLY
1190     { .name = "L2CTLR", .cp = 15, .crn = 9, .crm = 0, .opc1 = 1, .opc2 = 2,
1191       .access = PL1_RW, .resetvalue = 0, .readfn = a15_l2ctlr_read,
1192       .writefn = arm_cp_write_ignore, },
1193 #endif
1194     { .name = "L2ECTLR", .cp = 15, .crn = 9, .crm = 0, .opc1 = 1, .opc2 = 3,
1195       .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0 },
1196     REGINFO_SENTINEL
1197 };
1198 
1199 static void cortex_a7_initfn(Object *obj)
1200 {
1201     ARMCPU *cpu = ARM_CPU(obj);
1202 
1203     cpu->dtb_compatible = "arm,cortex-a7";
1204     set_feature(&cpu->env, ARM_FEATURE_V7);
1205     set_feature(&cpu->env, ARM_FEATURE_VFP4);
1206     set_feature(&cpu->env, ARM_FEATURE_NEON);
1207     set_feature(&cpu->env, ARM_FEATURE_THUMB2EE);
1208     set_feature(&cpu->env, ARM_FEATURE_ARM_DIV);
1209     set_feature(&cpu->env, ARM_FEATURE_GENERIC_TIMER);
1210     set_feature(&cpu->env, ARM_FEATURE_DUMMY_C15_REGS);
1211     set_feature(&cpu->env, ARM_FEATURE_CBAR_RO);
1212     set_feature(&cpu->env, ARM_FEATURE_LPAE);
1213     set_feature(&cpu->env, ARM_FEATURE_EL3);
1214     cpu->kvm_target = QEMU_KVM_ARM_TARGET_CORTEX_A7;
1215     cpu->midr = 0x410fc075;
1216     cpu->reset_fpsid = 0x41023075;
1217     cpu->mvfr0 = 0x10110222;
1218     cpu->mvfr1 = 0x11111111;
1219     cpu->ctr = 0x84448003;
1220     cpu->reset_sctlr = 0x00c50078;
1221     cpu->id_pfr0 = 0x00001131;
1222     cpu->id_pfr1 = 0x00011011;
1223     cpu->id_dfr0 = 0x02010555;
1224     cpu->pmceid0 = 0x00000000;
1225     cpu->pmceid1 = 0x00000000;
1226     cpu->id_afr0 = 0x00000000;
1227     cpu->id_mmfr0 = 0x10101105;
1228     cpu->id_mmfr1 = 0x40000000;
1229     cpu->id_mmfr2 = 0x01240000;
1230     cpu->id_mmfr3 = 0x02102211;
1231     cpu->id_isar0 = 0x01101110;
1232     cpu->id_isar1 = 0x13112111;
1233     cpu->id_isar2 = 0x21232041;
1234     cpu->id_isar3 = 0x11112131;
1235     cpu->id_isar4 = 0x10011142;
1236     cpu->dbgdidr = 0x3515f005;
1237     cpu->clidr = 0x0a200023;
1238     cpu->ccsidr[0] = 0x701fe00a; /* 32K L1 dcache */
1239     cpu->ccsidr[1] = 0x201fe00a; /* 32K L1 icache */
1240     cpu->ccsidr[2] = 0x711fe07a; /* 4096K L2 unified cache */
1241     define_arm_cp_regs(cpu, cortexa15_cp_reginfo); /* Same as A15 */
1242 }
1243 
1244 static void cortex_a15_initfn(Object *obj)
1245 {
1246     ARMCPU *cpu = ARM_CPU(obj);
1247 
1248     cpu->dtb_compatible = "arm,cortex-a15";
1249     set_feature(&cpu->env, ARM_FEATURE_V7);
1250     set_feature(&cpu->env, ARM_FEATURE_VFP4);
1251     set_feature(&cpu->env, ARM_FEATURE_NEON);
1252     set_feature(&cpu->env, ARM_FEATURE_THUMB2EE);
1253     set_feature(&cpu->env, ARM_FEATURE_ARM_DIV);
1254     set_feature(&cpu->env, ARM_FEATURE_GENERIC_TIMER);
1255     set_feature(&cpu->env, ARM_FEATURE_DUMMY_C15_REGS);
1256     set_feature(&cpu->env, ARM_FEATURE_CBAR_RO);
1257     set_feature(&cpu->env, ARM_FEATURE_LPAE);
1258     set_feature(&cpu->env, ARM_FEATURE_EL3);
1259     cpu->kvm_target = QEMU_KVM_ARM_TARGET_CORTEX_A15;
1260     cpu->midr = 0x412fc0f1;
1261     cpu->reset_fpsid = 0x410430f0;
1262     cpu->mvfr0 = 0x10110222;
1263     cpu->mvfr1 = 0x11111111;
1264     cpu->ctr = 0x8444c004;
1265     cpu->reset_sctlr = 0x00c50078;
1266     cpu->id_pfr0 = 0x00001131;
1267     cpu->id_pfr1 = 0x00011011;
1268     cpu->id_dfr0 = 0x02010555;
1269     cpu->pmceid0 = 0x0000000;
1270     cpu->pmceid1 = 0x00000000;
1271     cpu->id_afr0 = 0x00000000;
1272     cpu->id_mmfr0 = 0x10201105;
1273     cpu->id_mmfr1 = 0x20000000;
1274     cpu->id_mmfr2 = 0x01240000;
1275     cpu->id_mmfr3 = 0x02102211;
1276     cpu->id_isar0 = 0x02101110;
1277     cpu->id_isar1 = 0x13112111;
1278     cpu->id_isar2 = 0x21232041;
1279     cpu->id_isar3 = 0x11112131;
1280     cpu->id_isar4 = 0x10011142;
1281     cpu->dbgdidr = 0x3515f021;
1282     cpu->clidr = 0x0a200023;
1283     cpu->ccsidr[0] = 0x701fe00a; /* 32K L1 dcache */
1284     cpu->ccsidr[1] = 0x201fe00a; /* 32K L1 icache */
1285     cpu->ccsidr[2] = 0x711fe07a; /* 4096K L2 unified cache */
1286     define_arm_cp_regs(cpu, cortexa15_cp_reginfo);
1287 }
1288 
1289 static void ti925t_initfn(Object *obj)
1290 {
1291     ARMCPU *cpu = ARM_CPU(obj);
1292     set_feature(&cpu->env, ARM_FEATURE_V4T);
1293     set_feature(&cpu->env, ARM_FEATURE_OMAPCP);
1294     cpu->midr = ARM_CPUID_TI925T;
1295     cpu->ctr = 0x5109149;
1296     cpu->reset_sctlr = 0x00000070;
1297 }
1298 
1299 static void sa1100_initfn(Object *obj)
1300 {
1301     ARMCPU *cpu = ARM_CPU(obj);
1302 
1303     cpu->dtb_compatible = "intel,sa1100";
1304     set_feature(&cpu->env, ARM_FEATURE_STRONGARM);
1305     set_feature(&cpu->env, ARM_FEATURE_DUMMY_C15_REGS);
1306     cpu->midr = 0x4401A11B;
1307     cpu->reset_sctlr = 0x00000070;
1308 }
1309 
1310 static void sa1110_initfn(Object *obj)
1311 {
1312     ARMCPU *cpu = ARM_CPU(obj);
1313     set_feature(&cpu->env, ARM_FEATURE_STRONGARM);
1314     set_feature(&cpu->env, ARM_FEATURE_DUMMY_C15_REGS);
1315     cpu->midr = 0x6901B119;
1316     cpu->reset_sctlr = 0x00000070;
1317 }
1318 
1319 static void pxa250_initfn(Object *obj)
1320 {
1321     ARMCPU *cpu = ARM_CPU(obj);
1322 
1323     cpu->dtb_compatible = "marvell,xscale";
1324     set_feature(&cpu->env, ARM_FEATURE_V5);
1325     set_feature(&cpu->env, ARM_FEATURE_XSCALE);
1326     cpu->midr = 0x69052100;
1327     cpu->ctr = 0xd172172;
1328     cpu->reset_sctlr = 0x00000078;
1329 }
1330 
1331 static void pxa255_initfn(Object *obj)
1332 {
1333     ARMCPU *cpu = ARM_CPU(obj);
1334 
1335     cpu->dtb_compatible = "marvell,xscale";
1336     set_feature(&cpu->env, ARM_FEATURE_V5);
1337     set_feature(&cpu->env, ARM_FEATURE_XSCALE);
1338     cpu->midr = 0x69052d00;
1339     cpu->ctr = 0xd172172;
1340     cpu->reset_sctlr = 0x00000078;
1341 }
1342 
1343 static void pxa260_initfn(Object *obj)
1344 {
1345     ARMCPU *cpu = ARM_CPU(obj);
1346 
1347     cpu->dtb_compatible = "marvell,xscale";
1348     set_feature(&cpu->env, ARM_FEATURE_V5);
1349     set_feature(&cpu->env, ARM_FEATURE_XSCALE);
1350     cpu->midr = 0x69052903;
1351     cpu->ctr = 0xd172172;
1352     cpu->reset_sctlr = 0x00000078;
1353 }
1354 
1355 static void pxa261_initfn(Object *obj)
1356 {
1357     ARMCPU *cpu = ARM_CPU(obj);
1358 
1359     cpu->dtb_compatible = "marvell,xscale";
1360     set_feature(&cpu->env, ARM_FEATURE_V5);
1361     set_feature(&cpu->env, ARM_FEATURE_XSCALE);
1362     cpu->midr = 0x69052d05;
1363     cpu->ctr = 0xd172172;
1364     cpu->reset_sctlr = 0x00000078;
1365 }
1366 
1367 static void pxa262_initfn(Object *obj)
1368 {
1369     ARMCPU *cpu = ARM_CPU(obj);
1370 
1371     cpu->dtb_compatible = "marvell,xscale";
1372     set_feature(&cpu->env, ARM_FEATURE_V5);
1373     set_feature(&cpu->env, ARM_FEATURE_XSCALE);
1374     cpu->midr = 0x69052d06;
1375     cpu->ctr = 0xd172172;
1376     cpu->reset_sctlr = 0x00000078;
1377 }
1378 
1379 static void pxa270a0_initfn(Object *obj)
1380 {
1381     ARMCPU *cpu = ARM_CPU(obj);
1382 
1383     cpu->dtb_compatible = "marvell,xscale";
1384     set_feature(&cpu->env, ARM_FEATURE_V5);
1385     set_feature(&cpu->env, ARM_FEATURE_XSCALE);
1386     set_feature(&cpu->env, ARM_FEATURE_IWMMXT);
1387     cpu->midr = 0x69054110;
1388     cpu->ctr = 0xd172172;
1389     cpu->reset_sctlr = 0x00000078;
1390 }
1391 
1392 static void pxa270a1_initfn(Object *obj)
1393 {
1394     ARMCPU *cpu = ARM_CPU(obj);
1395 
1396     cpu->dtb_compatible = "marvell,xscale";
1397     set_feature(&cpu->env, ARM_FEATURE_V5);
1398     set_feature(&cpu->env, ARM_FEATURE_XSCALE);
1399     set_feature(&cpu->env, ARM_FEATURE_IWMMXT);
1400     cpu->midr = 0x69054111;
1401     cpu->ctr = 0xd172172;
1402     cpu->reset_sctlr = 0x00000078;
1403 }
1404 
1405 static void pxa270b0_initfn(Object *obj)
1406 {
1407     ARMCPU *cpu = ARM_CPU(obj);
1408 
1409     cpu->dtb_compatible = "marvell,xscale";
1410     set_feature(&cpu->env, ARM_FEATURE_V5);
1411     set_feature(&cpu->env, ARM_FEATURE_XSCALE);
1412     set_feature(&cpu->env, ARM_FEATURE_IWMMXT);
1413     cpu->midr = 0x69054112;
1414     cpu->ctr = 0xd172172;
1415     cpu->reset_sctlr = 0x00000078;
1416 }
1417 
1418 static void pxa270b1_initfn(Object *obj)
1419 {
1420     ARMCPU *cpu = ARM_CPU(obj);
1421 
1422     cpu->dtb_compatible = "marvell,xscale";
1423     set_feature(&cpu->env, ARM_FEATURE_V5);
1424     set_feature(&cpu->env, ARM_FEATURE_XSCALE);
1425     set_feature(&cpu->env, ARM_FEATURE_IWMMXT);
1426     cpu->midr = 0x69054113;
1427     cpu->ctr = 0xd172172;
1428     cpu->reset_sctlr = 0x00000078;
1429 }
1430 
1431 static void pxa270c0_initfn(Object *obj)
1432 {
1433     ARMCPU *cpu = ARM_CPU(obj);
1434 
1435     cpu->dtb_compatible = "marvell,xscale";
1436     set_feature(&cpu->env, ARM_FEATURE_V5);
1437     set_feature(&cpu->env, ARM_FEATURE_XSCALE);
1438     set_feature(&cpu->env, ARM_FEATURE_IWMMXT);
1439     cpu->midr = 0x69054114;
1440     cpu->ctr = 0xd172172;
1441     cpu->reset_sctlr = 0x00000078;
1442 }
1443 
1444 static void pxa270c5_initfn(Object *obj)
1445 {
1446     ARMCPU *cpu = ARM_CPU(obj);
1447 
1448     cpu->dtb_compatible = "marvell,xscale";
1449     set_feature(&cpu->env, ARM_FEATURE_V5);
1450     set_feature(&cpu->env, ARM_FEATURE_XSCALE);
1451     set_feature(&cpu->env, ARM_FEATURE_IWMMXT);
1452     cpu->midr = 0x69054117;
1453     cpu->ctr = 0xd172172;
1454     cpu->reset_sctlr = 0x00000078;
1455 }
1456 
1457 #ifdef CONFIG_USER_ONLY
1458 static void arm_any_initfn(Object *obj)
1459 {
1460     ARMCPU *cpu = ARM_CPU(obj);
1461     set_feature(&cpu->env, ARM_FEATURE_V8);
1462     set_feature(&cpu->env, ARM_FEATURE_VFP4);
1463     set_feature(&cpu->env, ARM_FEATURE_NEON);
1464     set_feature(&cpu->env, ARM_FEATURE_THUMB2EE);
1465     set_feature(&cpu->env, ARM_FEATURE_V8_AES);
1466     set_feature(&cpu->env, ARM_FEATURE_V8_SHA1);
1467     set_feature(&cpu->env, ARM_FEATURE_V8_SHA256);
1468     set_feature(&cpu->env, ARM_FEATURE_V8_PMULL);
1469     set_feature(&cpu->env, ARM_FEATURE_CRC);
1470     cpu->midr = 0xffffffff;
1471 }
1472 #endif
1473 
1474 #endif /* !defined(CONFIG_USER_ONLY) || !defined(TARGET_AARCH64) */
1475 
1476 typedef struct ARMCPUInfo {
1477     const char *name;
1478     void (*initfn)(Object *obj);
1479     void (*class_init)(ObjectClass *oc, void *data);
1480 } ARMCPUInfo;
1481 
1482 static const ARMCPUInfo arm_cpus[] = {
1483 #if !defined(CONFIG_USER_ONLY) || !defined(TARGET_AARCH64)
1484     { .name = "arm926",      .initfn = arm926_initfn },
1485     { .name = "arm946",      .initfn = arm946_initfn },
1486     { .name = "arm1026",     .initfn = arm1026_initfn },
1487     /* What QEMU calls "arm1136-r2" is actually the 1136 r0p2, i.e. an
1488      * older core than plain "arm1136". In particular this does not
1489      * have the v6K features.
1490      */
1491     { .name = "arm1136-r2",  .initfn = arm1136_r2_initfn },
1492     { .name = "arm1136",     .initfn = arm1136_initfn },
1493     { .name = "arm1176",     .initfn = arm1176_initfn },
1494     { .name = "arm11mpcore", .initfn = arm11mpcore_initfn },
1495     { .name = "cortex-m3",   .initfn = cortex_m3_initfn,
1496                              .class_init = arm_v7m_class_init },
1497     { .name = "cortex-m4",   .initfn = cortex_m4_initfn,
1498                              .class_init = arm_v7m_class_init },
1499     { .name = "cortex-r5",   .initfn = cortex_r5_initfn },
1500     { .name = "cortex-a7",   .initfn = cortex_a7_initfn },
1501     { .name = "cortex-a8",   .initfn = cortex_a8_initfn },
1502     { .name = "cortex-a9",   .initfn = cortex_a9_initfn },
1503     { .name = "cortex-a15",  .initfn = cortex_a15_initfn },
1504     { .name = "ti925t",      .initfn = ti925t_initfn },
1505     { .name = "sa1100",      .initfn = sa1100_initfn },
1506     { .name = "sa1110",      .initfn = sa1110_initfn },
1507     { .name = "pxa250",      .initfn = pxa250_initfn },
1508     { .name = "pxa255",      .initfn = pxa255_initfn },
1509     { .name = "pxa260",      .initfn = pxa260_initfn },
1510     { .name = "pxa261",      .initfn = pxa261_initfn },
1511     { .name = "pxa262",      .initfn = pxa262_initfn },
1512     /* "pxa270" is an alias for "pxa270-a0" */
1513     { .name = "pxa270",      .initfn = pxa270a0_initfn },
1514     { .name = "pxa270-a0",   .initfn = pxa270a0_initfn },
1515     { .name = "pxa270-a1",   .initfn = pxa270a1_initfn },
1516     { .name = "pxa270-b0",   .initfn = pxa270b0_initfn },
1517     { .name = "pxa270-b1",   .initfn = pxa270b1_initfn },
1518     { .name = "pxa270-c0",   .initfn = pxa270c0_initfn },
1519     { .name = "pxa270-c5",   .initfn = pxa270c5_initfn },
1520 #ifdef CONFIG_USER_ONLY
1521     { .name = "any",         .initfn = arm_any_initfn },
1522 #endif
1523 #endif
1524     { .name = NULL }
1525 };
1526 
1527 static Property arm_cpu_properties[] = {
1528     DEFINE_PROP_BOOL("start-powered-off", ARMCPU, start_powered_off, false),
1529     DEFINE_PROP_UINT32("psci-conduit", ARMCPU, psci_conduit, 0),
1530     DEFINE_PROP_UINT32("midr", ARMCPU, midr, 0),
1531     DEFINE_PROP_UINT64("mp-affinity", ARMCPU,
1532                         mp_affinity, ARM64_AFFINITY_INVALID),
1533     DEFINE_PROP_END_OF_LIST()
1534 };
1535 
1536 #ifdef CONFIG_USER_ONLY
1537 static int arm_cpu_handle_mmu_fault(CPUState *cs, vaddr address, int rw,
1538                                     int mmu_idx)
1539 {
1540     ARMCPU *cpu = ARM_CPU(cs);
1541     CPUARMState *env = &cpu->env;
1542 
1543     env->exception.vaddress = address;
1544     if (rw == 2) {
1545         cs->exception_index = EXCP_PREFETCH_ABORT;
1546     } else {
1547         cs->exception_index = EXCP_DATA_ABORT;
1548     }
1549     return 1;
1550 }
1551 #endif
1552 
1553 static gchar *arm_gdb_arch_name(CPUState *cs)
1554 {
1555     ARMCPU *cpu = ARM_CPU(cs);
1556     CPUARMState *env = &cpu->env;
1557 
1558     if (arm_feature(env, ARM_FEATURE_IWMMXT)) {
1559         return g_strdup("iwmmxt");
1560     }
1561     return g_strdup("arm");
1562 }
1563 
1564 static void arm_cpu_class_init(ObjectClass *oc, void *data)
1565 {
1566     ARMCPUClass *acc = ARM_CPU_CLASS(oc);
1567     CPUClass *cc = CPU_CLASS(acc);
1568     DeviceClass *dc = DEVICE_CLASS(oc);
1569 
1570     acc->parent_realize = dc->realize;
1571     dc->realize = arm_cpu_realizefn;
1572     dc->props = arm_cpu_properties;
1573 
1574     acc->parent_reset = cc->reset;
1575     cc->reset = arm_cpu_reset;
1576 
1577     cc->class_by_name = arm_cpu_class_by_name;
1578     cc->has_work = arm_cpu_has_work;
1579     cc->cpu_exec_interrupt = arm_cpu_exec_interrupt;
1580     cc->dump_state = arm_cpu_dump_state;
1581     cc->set_pc = arm_cpu_set_pc;
1582     cc->gdb_read_register = arm_cpu_gdb_read_register;
1583     cc->gdb_write_register = arm_cpu_gdb_write_register;
1584 #ifdef CONFIG_USER_ONLY
1585     cc->handle_mmu_fault = arm_cpu_handle_mmu_fault;
1586 #else
1587     cc->do_interrupt = arm_cpu_do_interrupt;
1588     cc->do_unaligned_access = arm_cpu_do_unaligned_access;
1589     cc->get_phys_page_attrs_debug = arm_cpu_get_phys_page_attrs_debug;
1590     cc->asidx_from_attrs = arm_asidx_from_attrs;
1591     cc->vmsd = &vmstate_arm_cpu;
1592     cc->virtio_is_big_endian = arm_cpu_virtio_is_big_endian;
1593     cc->write_elf64_note = arm_cpu_write_elf64_note;
1594     cc->write_elf32_note = arm_cpu_write_elf32_note;
1595 #endif
1596     cc->gdb_num_core_regs = 26;
1597     cc->gdb_core_xml_file = "arm-core.xml";
1598     cc->gdb_arch_name = arm_gdb_arch_name;
1599     cc->gdb_stop_before_watchpoint = true;
1600     cc->debug_excp_handler = arm_debug_excp_handler;
1601     cc->debug_check_watchpoint = arm_debug_check_watchpoint;
1602 
1603     cc->disas_set_info = arm_disas_set_info;
1604 }
1605 
1606 static void cpu_register(const ARMCPUInfo *info)
1607 {
1608     TypeInfo type_info = {
1609         .parent = TYPE_ARM_CPU,
1610         .instance_size = sizeof(ARMCPU),
1611         .instance_init = info->initfn,
1612         .class_size = sizeof(ARMCPUClass),
1613         .class_init = info->class_init,
1614     };
1615 
1616     type_info.name = g_strdup_printf("%s-" TYPE_ARM_CPU, info->name);
1617     type_register(&type_info);
1618     g_free((void *)type_info.name);
1619 }
1620 
1621 static const TypeInfo arm_cpu_type_info = {
1622     .name = TYPE_ARM_CPU,
1623     .parent = TYPE_CPU,
1624     .instance_size = sizeof(ARMCPU),
1625     .instance_init = arm_cpu_initfn,
1626     .instance_post_init = arm_cpu_post_init,
1627     .instance_finalize = arm_cpu_finalizefn,
1628     .abstract = true,
1629     .class_size = sizeof(ARMCPUClass),
1630     .class_init = arm_cpu_class_init,
1631 };
1632 
1633 static void arm_cpu_register_types(void)
1634 {
1635     const ARMCPUInfo *info = arm_cpus;
1636 
1637     type_register_static(&arm_cpu_type_info);
1638 
1639     while (info->name) {
1640         cpu_register(info);
1641         info++;
1642     }
1643 }
1644 
1645 type_init(arm_cpu_register_types)
1646