1 /* 2 * QEMU ARM CPU 3 * 4 * Copyright (c) 2012 SUSE LINUX Products GmbH 5 * 6 * This program is free software; you can redistribute it and/or 7 * modify it under the terms of the GNU General Public License 8 * as published by the Free Software Foundation; either version 2 9 * of the License, or (at your option) any later version. 10 * 11 * This program is distributed in the hope that it will be useful, 12 * but WITHOUT ANY WARRANTY; without even the implied warranty of 13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 14 * GNU General Public License for more details. 15 * 16 * You should have received a copy of the GNU General Public License 17 * along with this program; if not, see 18 * <http://www.gnu.org/licenses/gpl-2.0.html> 19 */ 20 21 #include "qemu/osdep.h" 22 #include "qemu/error-report.h" 23 #include "qapi/error.h" 24 #include "cpu.h" 25 #include "internals.h" 26 #include "qemu-common.h" 27 #include "exec/exec-all.h" 28 #include "hw/qdev-properties.h" 29 #if !defined(CONFIG_USER_ONLY) 30 #include "hw/loader.h" 31 #endif 32 #include "hw/arm/arm.h" 33 #include "sysemu/sysemu.h" 34 #include "sysemu/hw_accel.h" 35 #include "kvm_arm.h" 36 37 static void arm_cpu_set_pc(CPUState *cs, vaddr value) 38 { 39 ARMCPU *cpu = ARM_CPU(cs); 40 41 cpu->env.regs[15] = value; 42 } 43 44 static bool arm_cpu_has_work(CPUState *cs) 45 { 46 ARMCPU *cpu = ARM_CPU(cs); 47 48 return (cpu->power_state != PSCI_OFF) 49 && cs->interrupt_request & 50 (CPU_INTERRUPT_FIQ | CPU_INTERRUPT_HARD 51 | CPU_INTERRUPT_VFIQ | CPU_INTERRUPT_VIRQ 52 | CPU_INTERRUPT_EXITTB); 53 } 54 55 void arm_register_el_change_hook(ARMCPU *cpu, ARMELChangeHook *hook, 56 void *opaque) 57 { 58 /* We currently only support registering a single hook function */ 59 assert(!cpu->el_change_hook); 60 cpu->el_change_hook = hook; 61 cpu->el_change_hook_opaque = opaque; 62 } 63 64 static void cp_reg_reset(gpointer key, gpointer value, gpointer opaque) 65 { 66 /* Reset a single ARMCPRegInfo register */ 67 ARMCPRegInfo *ri = value; 68 ARMCPU *cpu = opaque; 69 70 if (ri->type & (ARM_CP_SPECIAL | ARM_CP_ALIAS)) { 71 return; 72 } 73 74 if (ri->resetfn) { 75 ri->resetfn(&cpu->env, ri); 76 return; 77 } 78 79 /* A zero offset is never possible as it would be regs[0] 80 * so we use it to indicate that reset is being handled elsewhere. 81 * This is basically only used for fields in non-core coprocessors 82 * (like the pxa2xx ones). 83 */ 84 if (!ri->fieldoffset) { 85 return; 86 } 87 88 if (cpreg_field_is_64bit(ri)) { 89 CPREG_FIELD64(&cpu->env, ri) = ri->resetvalue; 90 } else { 91 CPREG_FIELD32(&cpu->env, ri) = ri->resetvalue; 92 } 93 } 94 95 static void cp_reg_check_reset(gpointer key, gpointer value, gpointer opaque) 96 { 97 /* Purely an assertion check: we've already done reset once, 98 * so now check that running the reset for the cpreg doesn't 99 * change its value. This traps bugs where two different cpregs 100 * both try to reset the same state field but to different values. 101 */ 102 ARMCPRegInfo *ri = value; 103 ARMCPU *cpu = opaque; 104 uint64_t oldvalue, newvalue; 105 106 if (ri->type & (ARM_CP_SPECIAL | ARM_CP_ALIAS | ARM_CP_NO_RAW)) { 107 return; 108 } 109 110 oldvalue = read_raw_cp_reg(&cpu->env, ri); 111 cp_reg_reset(key, value, opaque); 112 newvalue = read_raw_cp_reg(&cpu->env, ri); 113 assert(oldvalue == newvalue); 114 } 115 116 /* CPUClass::reset() */ 117 static void arm_cpu_reset(CPUState *s) 118 { 119 ARMCPU *cpu = ARM_CPU(s); 120 ARMCPUClass *acc = ARM_CPU_GET_CLASS(cpu); 121 CPUARMState *env = &cpu->env; 122 123 acc->parent_reset(s); 124 125 memset(env, 0, offsetof(CPUARMState, end_reset_fields)); 126 127 g_hash_table_foreach(cpu->cp_regs, cp_reg_reset, cpu); 128 g_hash_table_foreach(cpu->cp_regs, cp_reg_check_reset, cpu); 129 130 env->vfp.xregs[ARM_VFP_FPSID] = cpu->reset_fpsid; 131 env->vfp.xregs[ARM_VFP_MVFR0] = cpu->mvfr0; 132 env->vfp.xregs[ARM_VFP_MVFR1] = cpu->mvfr1; 133 env->vfp.xregs[ARM_VFP_MVFR2] = cpu->mvfr2; 134 135 cpu->power_state = cpu->start_powered_off ? PSCI_OFF : PSCI_ON; 136 s->halted = cpu->start_powered_off; 137 138 if (arm_feature(env, ARM_FEATURE_IWMMXT)) { 139 env->iwmmxt.cregs[ARM_IWMMXT_wCID] = 0x69051000 | 'Q'; 140 } 141 142 if (arm_feature(env, ARM_FEATURE_AARCH64)) { 143 /* 64 bit CPUs always start in 64 bit mode */ 144 env->aarch64 = 1; 145 #if defined(CONFIG_USER_ONLY) 146 env->pstate = PSTATE_MODE_EL0t; 147 /* Userspace expects access to DC ZVA, CTL_EL0 and the cache ops */ 148 env->cp15.sctlr_el[1] |= SCTLR_UCT | SCTLR_UCI | SCTLR_DZE; 149 /* and to the FP/Neon instructions */ 150 env->cp15.cpacr_el1 = deposit64(env->cp15.cpacr_el1, 20, 2, 3); 151 #else 152 /* Reset into the highest available EL */ 153 if (arm_feature(env, ARM_FEATURE_EL3)) { 154 env->pstate = PSTATE_MODE_EL3h; 155 } else if (arm_feature(env, ARM_FEATURE_EL2)) { 156 env->pstate = PSTATE_MODE_EL2h; 157 } else { 158 env->pstate = PSTATE_MODE_EL1h; 159 } 160 env->pc = cpu->rvbar; 161 #endif 162 } else { 163 #if defined(CONFIG_USER_ONLY) 164 /* Userspace expects access to cp10 and cp11 for FP/Neon */ 165 env->cp15.cpacr_el1 = deposit64(env->cp15.cpacr_el1, 20, 4, 0xf); 166 #endif 167 } 168 169 #if defined(CONFIG_USER_ONLY) 170 env->uncached_cpsr = ARM_CPU_MODE_USR; 171 /* For user mode we must enable access to coprocessors */ 172 env->vfp.xregs[ARM_VFP_FPEXC] = 1 << 30; 173 if (arm_feature(env, ARM_FEATURE_IWMMXT)) { 174 env->cp15.c15_cpar = 3; 175 } else if (arm_feature(env, ARM_FEATURE_XSCALE)) { 176 env->cp15.c15_cpar = 1; 177 } 178 #else 179 /* SVC mode with interrupts disabled. */ 180 env->uncached_cpsr = ARM_CPU_MODE_SVC; 181 env->daif = PSTATE_D | PSTATE_A | PSTATE_I | PSTATE_F; 182 183 if (arm_feature(env, ARM_FEATURE_M)) { 184 uint32_t initial_msp; /* Loaded from 0x0 */ 185 uint32_t initial_pc; /* Loaded from 0x4 */ 186 uint8_t *rom; 187 188 /* For M profile we store FAULTMASK and PRIMASK in the 189 * PSTATE F and I bits; these are both clear at reset. 190 */ 191 env->daif &= ~(PSTATE_I | PSTATE_F); 192 193 /* The reset value of this bit is IMPDEF, but ARM recommends 194 * that it resets to 1, so QEMU always does that rather than making 195 * it dependent on CPU model. 196 */ 197 env->v7m.ccr = R_V7M_CCR_STKALIGN_MASK; 198 199 /* Unlike A/R profile, M profile defines the reset LR value */ 200 env->regs[14] = 0xffffffff; 201 202 /* Load the initial SP and PC from the vector table at address 0 */ 203 rom = rom_ptr(0); 204 if (rom) { 205 /* Address zero is covered by ROM which hasn't yet been 206 * copied into physical memory. 207 */ 208 initial_msp = ldl_p(rom); 209 initial_pc = ldl_p(rom + 4); 210 } else { 211 /* Address zero not covered by a ROM blob, or the ROM blob 212 * is in non-modifiable memory and this is a second reset after 213 * it got copied into memory. In the latter case, rom_ptr 214 * will return a NULL pointer and we should use ldl_phys instead. 215 */ 216 initial_msp = ldl_phys(s->as, 0); 217 initial_pc = ldl_phys(s->as, 4); 218 } 219 220 env->regs[13] = initial_msp & 0xFFFFFFFC; 221 env->regs[15] = initial_pc & ~1; 222 env->thumb = initial_pc & 1; 223 } 224 225 /* AArch32 has a hard highvec setting of 0xFFFF0000. If we are currently 226 * executing as AArch32 then check if highvecs are enabled and 227 * adjust the PC accordingly. 228 */ 229 if (A32_BANKED_CURRENT_REG_GET(env, sctlr) & SCTLR_V) { 230 env->regs[15] = 0xFFFF0000; 231 } 232 233 env->vfp.xregs[ARM_VFP_FPEXC] = 0; 234 #endif 235 set_flush_to_zero(1, &env->vfp.standard_fp_status); 236 set_flush_inputs_to_zero(1, &env->vfp.standard_fp_status); 237 set_default_nan_mode(1, &env->vfp.standard_fp_status); 238 set_float_detect_tininess(float_tininess_before_rounding, 239 &env->vfp.fp_status); 240 set_float_detect_tininess(float_tininess_before_rounding, 241 &env->vfp.standard_fp_status); 242 #ifndef CONFIG_USER_ONLY 243 if (kvm_enabled()) { 244 kvm_arm_reset_vcpu(cpu); 245 } 246 #endif 247 248 hw_breakpoint_update_all(cpu); 249 hw_watchpoint_update_all(cpu); 250 } 251 252 bool arm_cpu_exec_interrupt(CPUState *cs, int interrupt_request) 253 { 254 CPUClass *cc = CPU_GET_CLASS(cs); 255 CPUARMState *env = cs->env_ptr; 256 uint32_t cur_el = arm_current_el(env); 257 bool secure = arm_is_secure(env); 258 uint32_t target_el; 259 uint32_t excp_idx; 260 bool ret = false; 261 262 if (interrupt_request & CPU_INTERRUPT_FIQ) { 263 excp_idx = EXCP_FIQ; 264 target_el = arm_phys_excp_target_el(cs, excp_idx, cur_el, secure); 265 if (arm_excp_unmasked(cs, excp_idx, target_el)) { 266 cs->exception_index = excp_idx; 267 env->exception.target_el = target_el; 268 cc->do_interrupt(cs); 269 ret = true; 270 } 271 } 272 if (interrupt_request & CPU_INTERRUPT_HARD) { 273 excp_idx = EXCP_IRQ; 274 target_el = arm_phys_excp_target_el(cs, excp_idx, cur_el, secure); 275 if (arm_excp_unmasked(cs, excp_idx, target_el)) { 276 cs->exception_index = excp_idx; 277 env->exception.target_el = target_el; 278 cc->do_interrupt(cs); 279 ret = true; 280 } 281 } 282 if (interrupt_request & CPU_INTERRUPT_VIRQ) { 283 excp_idx = EXCP_VIRQ; 284 target_el = 1; 285 if (arm_excp_unmasked(cs, excp_idx, target_el)) { 286 cs->exception_index = excp_idx; 287 env->exception.target_el = target_el; 288 cc->do_interrupt(cs); 289 ret = true; 290 } 291 } 292 if (interrupt_request & CPU_INTERRUPT_VFIQ) { 293 excp_idx = EXCP_VFIQ; 294 target_el = 1; 295 if (arm_excp_unmasked(cs, excp_idx, target_el)) { 296 cs->exception_index = excp_idx; 297 env->exception.target_el = target_el; 298 cc->do_interrupt(cs); 299 ret = true; 300 } 301 } 302 303 return ret; 304 } 305 306 #if !defined(CONFIG_USER_ONLY) || !defined(TARGET_AARCH64) 307 static bool arm_v7m_cpu_exec_interrupt(CPUState *cs, int interrupt_request) 308 { 309 CPUClass *cc = CPU_GET_CLASS(cs); 310 ARMCPU *cpu = ARM_CPU(cs); 311 CPUARMState *env = &cpu->env; 312 bool ret = false; 313 314 /* ARMv7-M interrupt masking works differently than -A or -R. 315 * There is no FIQ/IRQ distinction. Instead of I and F bits 316 * masking FIQ and IRQ interrupts, an exception is taken only 317 * if it is higher priority than the current execution priority 318 * (which depends on state like BASEPRI, FAULTMASK and the 319 * currently active exception). 320 */ 321 if (interrupt_request & CPU_INTERRUPT_HARD 322 && (armv7m_nvic_can_take_pending_exception(env->nvic))) { 323 cs->exception_index = EXCP_IRQ; 324 cc->do_interrupt(cs); 325 ret = true; 326 } 327 return ret; 328 } 329 #endif 330 331 #ifndef CONFIG_USER_ONLY 332 static void arm_cpu_set_irq(void *opaque, int irq, int level) 333 { 334 ARMCPU *cpu = opaque; 335 CPUARMState *env = &cpu->env; 336 CPUState *cs = CPU(cpu); 337 static const int mask[] = { 338 [ARM_CPU_IRQ] = CPU_INTERRUPT_HARD, 339 [ARM_CPU_FIQ] = CPU_INTERRUPT_FIQ, 340 [ARM_CPU_VIRQ] = CPU_INTERRUPT_VIRQ, 341 [ARM_CPU_VFIQ] = CPU_INTERRUPT_VFIQ 342 }; 343 344 switch (irq) { 345 case ARM_CPU_VIRQ: 346 case ARM_CPU_VFIQ: 347 assert(arm_feature(env, ARM_FEATURE_EL2)); 348 /* fall through */ 349 case ARM_CPU_IRQ: 350 case ARM_CPU_FIQ: 351 if (level) { 352 cpu_interrupt(cs, mask[irq]); 353 } else { 354 cpu_reset_interrupt(cs, mask[irq]); 355 } 356 break; 357 default: 358 g_assert_not_reached(); 359 } 360 } 361 362 static void arm_cpu_kvm_set_irq(void *opaque, int irq, int level) 363 { 364 #ifdef CONFIG_KVM 365 ARMCPU *cpu = opaque; 366 CPUState *cs = CPU(cpu); 367 int kvm_irq = KVM_ARM_IRQ_TYPE_CPU << KVM_ARM_IRQ_TYPE_SHIFT; 368 369 switch (irq) { 370 case ARM_CPU_IRQ: 371 kvm_irq |= KVM_ARM_IRQ_CPU_IRQ; 372 break; 373 case ARM_CPU_FIQ: 374 kvm_irq |= KVM_ARM_IRQ_CPU_FIQ; 375 break; 376 default: 377 g_assert_not_reached(); 378 } 379 kvm_irq |= cs->cpu_index << KVM_ARM_IRQ_VCPU_SHIFT; 380 kvm_set_irq(kvm_state, kvm_irq, level ? 1 : 0); 381 #endif 382 } 383 384 static bool arm_cpu_virtio_is_big_endian(CPUState *cs) 385 { 386 ARMCPU *cpu = ARM_CPU(cs); 387 CPUARMState *env = &cpu->env; 388 389 cpu_synchronize_state(cs); 390 return arm_cpu_data_is_big_endian(env); 391 } 392 393 #endif 394 395 static inline void set_feature(CPUARMState *env, int feature) 396 { 397 env->features |= 1ULL << feature; 398 } 399 400 static inline void unset_feature(CPUARMState *env, int feature) 401 { 402 env->features &= ~(1ULL << feature); 403 } 404 405 static int 406 print_insn_thumb1(bfd_vma pc, disassemble_info *info) 407 { 408 return print_insn_arm(pc | 1, info); 409 } 410 411 static int arm_read_memory_func(bfd_vma memaddr, bfd_byte *b, 412 int length, struct disassemble_info *info) 413 { 414 assert(info->read_memory_inner_func); 415 assert((info->flags & INSN_ARM_BE32) == 0 || length == 2 || length == 4); 416 417 if ((info->flags & INSN_ARM_BE32) != 0 && length == 2) { 418 assert(info->endian == BFD_ENDIAN_LITTLE); 419 return info->read_memory_inner_func(memaddr ^ 2, (bfd_byte *)b, 2, 420 info); 421 } else { 422 return info->read_memory_inner_func(memaddr, b, length, info); 423 } 424 } 425 426 static void arm_disas_set_info(CPUState *cpu, disassemble_info *info) 427 { 428 ARMCPU *ac = ARM_CPU(cpu); 429 CPUARMState *env = &ac->env; 430 431 if (is_a64(env)) { 432 /* We might not be compiled with the A64 disassembler 433 * because it needs a C++ compiler. Leave print_insn 434 * unset in this case to use the caller default behaviour. 435 */ 436 #if defined(CONFIG_ARM_A64_DIS) 437 info->print_insn = print_insn_arm_a64; 438 #endif 439 } else if (env->thumb) { 440 info->print_insn = print_insn_thumb1; 441 } else { 442 info->print_insn = print_insn_arm; 443 } 444 if (bswap_code(arm_sctlr_b(env))) { 445 #ifdef TARGET_WORDS_BIGENDIAN 446 info->endian = BFD_ENDIAN_LITTLE; 447 #else 448 info->endian = BFD_ENDIAN_BIG; 449 #endif 450 } 451 if (info->read_memory_inner_func == NULL) { 452 info->read_memory_inner_func = info->read_memory_func; 453 info->read_memory_func = arm_read_memory_func; 454 } 455 info->flags &= ~INSN_ARM_BE32; 456 if (arm_sctlr_b(env)) { 457 info->flags |= INSN_ARM_BE32; 458 } 459 } 460 461 uint64_t arm_cpu_mp_affinity(int idx, uint8_t clustersz) 462 { 463 uint32_t Aff1 = idx / clustersz; 464 uint32_t Aff0 = idx % clustersz; 465 return (Aff1 << ARM_AFF1_SHIFT) | Aff0; 466 } 467 468 static void arm_cpu_initfn(Object *obj) 469 { 470 CPUState *cs = CPU(obj); 471 ARMCPU *cpu = ARM_CPU(obj); 472 static bool inited; 473 474 cs->env_ptr = &cpu->env; 475 cpu->cp_regs = g_hash_table_new_full(g_int_hash, g_int_equal, 476 g_free, g_free); 477 478 #ifndef CONFIG_USER_ONLY 479 /* Our inbound IRQ and FIQ lines */ 480 if (kvm_enabled()) { 481 /* VIRQ and VFIQ are unused with KVM but we add them to maintain 482 * the same interface as non-KVM CPUs. 483 */ 484 qdev_init_gpio_in(DEVICE(cpu), arm_cpu_kvm_set_irq, 4); 485 } else { 486 qdev_init_gpio_in(DEVICE(cpu), arm_cpu_set_irq, 4); 487 } 488 489 cpu->gt_timer[GTIMER_PHYS] = timer_new(QEMU_CLOCK_VIRTUAL, GTIMER_SCALE, 490 arm_gt_ptimer_cb, cpu); 491 cpu->gt_timer[GTIMER_VIRT] = timer_new(QEMU_CLOCK_VIRTUAL, GTIMER_SCALE, 492 arm_gt_vtimer_cb, cpu); 493 cpu->gt_timer[GTIMER_HYP] = timer_new(QEMU_CLOCK_VIRTUAL, GTIMER_SCALE, 494 arm_gt_htimer_cb, cpu); 495 cpu->gt_timer[GTIMER_SEC] = timer_new(QEMU_CLOCK_VIRTUAL, GTIMER_SCALE, 496 arm_gt_stimer_cb, cpu); 497 qdev_init_gpio_out(DEVICE(cpu), cpu->gt_timer_outputs, 498 ARRAY_SIZE(cpu->gt_timer_outputs)); 499 500 qdev_init_gpio_out_named(DEVICE(cpu), &cpu->gicv3_maintenance_interrupt, 501 "gicv3-maintenance-interrupt", 1); 502 #endif 503 504 /* DTB consumers generally don't in fact care what the 'compatible' 505 * string is, so always provide some string and trust that a hypothetical 506 * picky DTB consumer will also provide a helpful error message. 507 */ 508 cpu->dtb_compatible = "qemu,unknown"; 509 cpu->psci_version = 1; /* By default assume PSCI v0.1 */ 510 cpu->kvm_target = QEMU_KVM_ARM_TARGET_NONE; 511 512 if (tcg_enabled()) { 513 cpu->psci_version = 2; /* TCG implements PSCI 0.2 */ 514 if (!inited) { 515 inited = true; 516 arm_translate_init(); 517 } 518 } 519 } 520 521 static Property arm_cpu_reset_cbar_property = 522 DEFINE_PROP_UINT64("reset-cbar", ARMCPU, reset_cbar, 0); 523 524 static Property arm_cpu_reset_hivecs_property = 525 DEFINE_PROP_BOOL("reset-hivecs", ARMCPU, reset_hivecs, false); 526 527 static Property arm_cpu_rvbar_property = 528 DEFINE_PROP_UINT64("rvbar", ARMCPU, rvbar, 0); 529 530 static Property arm_cpu_has_el2_property = 531 DEFINE_PROP_BOOL("has_el2", ARMCPU, has_el2, true); 532 533 static Property arm_cpu_has_el3_property = 534 DEFINE_PROP_BOOL("has_el3", ARMCPU, has_el3, true); 535 536 static Property arm_cpu_cfgend_property = 537 DEFINE_PROP_BOOL("cfgend", ARMCPU, cfgend, false); 538 539 /* use property name "pmu" to match other archs and virt tools */ 540 static Property arm_cpu_has_pmu_property = 541 DEFINE_PROP_BOOL("pmu", ARMCPU, has_pmu, true); 542 543 static Property arm_cpu_has_mpu_property = 544 DEFINE_PROP_BOOL("has-mpu", ARMCPU, has_mpu, true); 545 546 static Property arm_cpu_pmsav7_dregion_property = 547 DEFINE_PROP_UINT32("pmsav7-dregion", ARMCPU, pmsav7_dregion, 16); 548 549 static void arm_cpu_post_init(Object *obj) 550 { 551 ARMCPU *cpu = ARM_CPU(obj); 552 553 if (arm_feature(&cpu->env, ARM_FEATURE_CBAR) || 554 arm_feature(&cpu->env, ARM_FEATURE_CBAR_RO)) { 555 qdev_property_add_static(DEVICE(obj), &arm_cpu_reset_cbar_property, 556 &error_abort); 557 } 558 559 if (!arm_feature(&cpu->env, ARM_FEATURE_M)) { 560 qdev_property_add_static(DEVICE(obj), &arm_cpu_reset_hivecs_property, 561 &error_abort); 562 } 563 564 if (arm_feature(&cpu->env, ARM_FEATURE_AARCH64)) { 565 qdev_property_add_static(DEVICE(obj), &arm_cpu_rvbar_property, 566 &error_abort); 567 } 568 569 if (arm_feature(&cpu->env, ARM_FEATURE_EL3)) { 570 /* Add the has_el3 state CPU property only if EL3 is allowed. This will 571 * prevent "has_el3" from existing on CPUs which cannot support EL3. 572 */ 573 qdev_property_add_static(DEVICE(obj), &arm_cpu_has_el3_property, 574 &error_abort); 575 576 #ifndef CONFIG_USER_ONLY 577 object_property_add_link(obj, "secure-memory", 578 TYPE_MEMORY_REGION, 579 (Object **)&cpu->secure_memory, 580 qdev_prop_allow_set_link_before_realize, 581 OBJ_PROP_LINK_UNREF_ON_RELEASE, 582 &error_abort); 583 #endif 584 } 585 586 if (arm_feature(&cpu->env, ARM_FEATURE_EL2)) { 587 qdev_property_add_static(DEVICE(obj), &arm_cpu_has_el2_property, 588 &error_abort); 589 } 590 591 if (arm_feature(&cpu->env, ARM_FEATURE_PMU)) { 592 qdev_property_add_static(DEVICE(obj), &arm_cpu_has_pmu_property, 593 &error_abort); 594 } 595 596 if (arm_feature(&cpu->env, ARM_FEATURE_MPU)) { 597 qdev_property_add_static(DEVICE(obj), &arm_cpu_has_mpu_property, 598 &error_abort); 599 if (arm_feature(&cpu->env, ARM_FEATURE_V7)) { 600 qdev_property_add_static(DEVICE(obj), 601 &arm_cpu_pmsav7_dregion_property, 602 &error_abort); 603 } 604 } 605 606 qdev_property_add_static(DEVICE(obj), &arm_cpu_cfgend_property, 607 &error_abort); 608 } 609 610 static void arm_cpu_finalizefn(Object *obj) 611 { 612 ARMCPU *cpu = ARM_CPU(obj); 613 g_hash_table_destroy(cpu->cp_regs); 614 } 615 616 static void arm_cpu_realizefn(DeviceState *dev, Error **errp) 617 { 618 CPUState *cs = CPU(dev); 619 ARMCPU *cpu = ARM_CPU(dev); 620 ARMCPUClass *acc = ARM_CPU_GET_CLASS(dev); 621 CPUARMState *env = &cpu->env; 622 int pagebits; 623 Error *local_err = NULL; 624 625 cpu_exec_realizefn(cs, &local_err); 626 if (local_err != NULL) { 627 error_propagate(errp, local_err); 628 return; 629 } 630 631 /* Some features automatically imply others: */ 632 if (arm_feature(env, ARM_FEATURE_V8)) { 633 set_feature(env, ARM_FEATURE_V7); 634 set_feature(env, ARM_FEATURE_ARM_DIV); 635 set_feature(env, ARM_FEATURE_LPAE); 636 } 637 if (arm_feature(env, ARM_FEATURE_V7)) { 638 set_feature(env, ARM_FEATURE_VAPA); 639 set_feature(env, ARM_FEATURE_THUMB2); 640 set_feature(env, ARM_FEATURE_MPIDR); 641 if (!arm_feature(env, ARM_FEATURE_M)) { 642 set_feature(env, ARM_FEATURE_V6K); 643 } else { 644 set_feature(env, ARM_FEATURE_V6); 645 } 646 647 /* Always define VBAR for V7 CPUs even if it doesn't exist in 648 * non-EL3 configs. This is needed by some legacy boards. 649 */ 650 set_feature(env, ARM_FEATURE_VBAR); 651 } 652 if (arm_feature(env, ARM_FEATURE_V6K)) { 653 set_feature(env, ARM_FEATURE_V6); 654 set_feature(env, ARM_FEATURE_MVFR); 655 } 656 if (arm_feature(env, ARM_FEATURE_V6)) { 657 set_feature(env, ARM_FEATURE_V5); 658 if (!arm_feature(env, ARM_FEATURE_M)) { 659 set_feature(env, ARM_FEATURE_AUXCR); 660 } 661 } 662 if (arm_feature(env, ARM_FEATURE_V5)) { 663 set_feature(env, ARM_FEATURE_V4T); 664 } 665 if (arm_feature(env, ARM_FEATURE_M)) { 666 set_feature(env, ARM_FEATURE_THUMB_DIV); 667 } 668 if (arm_feature(env, ARM_FEATURE_ARM_DIV)) { 669 set_feature(env, ARM_FEATURE_THUMB_DIV); 670 } 671 if (arm_feature(env, ARM_FEATURE_VFP4)) { 672 set_feature(env, ARM_FEATURE_VFP3); 673 set_feature(env, ARM_FEATURE_VFP_FP16); 674 } 675 if (arm_feature(env, ARM_FEATURE_VFP3)) { 676 set_feature(env, ARM_FEATURE_VFP); 677 } 678 if (arm_feature(env, ARM_FEATURE_LPAE)) { 679 set_feature(env, ARM_FEATURE_V7MP); 680 set_feature(env, ARM_FEATURE_PXN); 681 } 682 if (arm_feature(env, ARM_FEATURE_CBAR_RO)) { 683 set_feature(env, ARM_FEATURE_CBAR); 684 } 685 if (arm_feature(env, ARM_FEATURE_THUMB2) && 686 !arm_feature(env, ARM_FEATURE_M)) { 687 set_feature(env, ARM_FEATURE_THUMB_DSP); 688 } 689 690 if (arm_feature(env, ARM_FEATURE_V7) && 691 !arm_feature(env, ARM_FEATURE_M) && 692 !arm_feature(env, ARM_FEATURE_MPU)) { 693 /* v7VMSA drops support for the old ARMv5 tiny pages, so we 694 * can use 4K pages. 695 */ 696 pagebits = 12; 697 } else { 698 /* For CPUs which might have tiny 1K pages, or which have an 699 * MPU and might have small region sizes, stick with 1K pages. 700 */ 701 pagebits = 10; 702 } 703 if (!set_preferred_target_page_bits(pagebits)) { 704 /* This can only ever happen for hotplugging a CPU, or if 705 * the board code incorrectly creates a CPU which it has 706 * promised via minimum_page_size that it will not. 707 */ 708 error_setg(errp, "This CPU requires a smaller page size than the " 709 "system is using"); 710 return; 711 } 712 713 /* This cpu-id-to-MPIDR affinity is used only for TCG; KVM will override it. 714 * We don't support setting cluster ID ([16..23]) (known as Aff2 715 * in later ARM ARM versions), or any of the higher affinity level fields, 716 * so these bits always RAZ. 717 */ 718 if (cpu->mp_affinity == ARM64_AFFINITY_INVALID) { 719 cpu->mp_affinity = arm_cpu_mp_affinity(cs->cpu_index, 720 ARM_DEFAULT_CPUS_PER_CLUSTER); 721 } 722 723 if (cpu->reset_hivecs) { 724 cpu->reset_sctlr |= (1 << 13); 725 } 726 727 if (cpu->cfgend) { 728 if (arm_feature(&cpu->env, ARM_FEATURE_V7)) { 729 cpu->reset_sctlr |= SCTLR_EE; 730 } else { 731 cpu->reset_sctlr |= SCTLR_B; 732 } 733 } 734 735 if (!cpu->has_el3) { 736 /* If the has_el3 CPU property is disabled then we need to disable the 737 * feature. 738 */ 739 unset_feature(env, ARM_FEATURE_EL3); 740 741 /* Disable the security extension feature bits in the processor feature 742 * registers as well. These are id_pfr1[7:4] and id_aa64pfr0[15:12]. 743 */ 744 cpu->id_pfr1 &= ~0xf0; 745 cpu->id_aa64pfr0 &= ~0xf000; 746 } 747 748 if (!cpu->has_el2) { 749 unset_feature(env, ARM_FEATURE_EL2); 750 } 751 752 if (!cpu->has_pmu) { 753 cpu->has_pmu = false; 754 unset_feature(env, ARM_FEATURE_PMU); 755 } 756 757 if (!arm_feature(env, ARM_FEATURE_EL2)) { 758 /* Disable the hypervisor feature bits in the processor feature 759 * registers if we don't have EL2. These are id_pfr1[15:12] and 760 * id_aa64pfr0_el1[11:8]. 761 */ 762 cpu->id_aa64pfr0 &= ~0xf00; 763 cpu->id_pfr1 &= ~0xf000; 764 } 765 766 if (!cpu->has_mpu) { 767 unset_feature(env, ARM_FEATURE_MPU); 768 } 769 770 if (arm_feature(env, ARM_FEATURE_MPU) && 771 arm_feature(env, ARM_FEATURE_V7)) { 772 uint32_t nr = cpu->pmsav7_dregion; 773 774 if (nr > 0xff) { 775 error_setg(errp, "PMSAv7 MPU #regions invalid %" PRIu32, nr); 776 return; 777 } 778 779 if (nr) { 780 env->pmsav7.drbar = g_new0(uint32_t, nr); 781 env->pmsav7.drsr = g_new0(uint32_t, nr); 782 env->pmsav7.dracr = g_new0(uint32_t, nr); 783 } 784 } 785 786 if (arm_feature(env, ARM_FEATURE_EL3)) { 787 set_feature(env, ARM_FEATURE_VBAR); 788 } 789 790 register_cp_regs_for_features(cpu); 791 arm_cpu_register_gdb_regs_for_features(cpu); 792 793 init_cpreg_list(cpu); 794 795 #ifndef CONFIG_USER_ONLY 796 if (cpu->has_el3) { 797 cs->num_ases = 2; 798 } else { 799 cs->num_ases = 1; 800 } 801 802 if (cpu->has_el3) { 803 AddressSpace *as; 804 805 if (!cpu->secure_memory) { 806 cpu->secure_memory = cs->memory; 807 } 808 as = address_space_init_shareable(cpu->secure_memory, 809 "cpu-secure-memory"); 810 cpu_address_space_init(cs, as, ARMASIdx_S); 811 } 812 cpu_address_space_init(cs, 813 address_space_init_shareable(cs->memory, 814 "cpu-memory"), 815 ARMASIdx_NS); 816 #endif 817 818 qemu_init_vcpu(cs); 819 cpu_reset(cs); 820 821 acc->parent_realize(dev, errp); 822 } 823 824 static ObjectClass *arm_cpu_class_by_name(const char *cpu_model) 825 { 826 ObjectClass *oc; 827 char *typename; 828 char **cpuname; 829 830 if (!cpu_model) { 831 return NULL; 832 } 833 834 cpuname = g_strsplit(cpu_model, ",", 1); 835 typename = g_strdup_printf("%s-" TYPE_ARM_CPU, cpuname[0]); 836 oc = object_class_by_name(typename); 837 g_strfreev(cpuname); 838 g_free(typename); 839 if (!oc || !object_class_dynamic_cast(oc, TYPE_ARM_CPU) || 840 object_class_is_abstract(oc)) { 841 return NULL; 842 } 843 return oc; 844 } 845 846 /* CPU models. These are not needed for the AArch64 linux-user build. */ 847 #if !defined(CONFIG_USER_ONLY) || !defined(TARGET_AARCH64) 848 849 static void arm926_initfn(Object *obj) 850 { 851 ARMCPU *cpu = ARM_CPU(obj); 852 853 cpu->dtb_compatible = "arm,arm926"; 854 set_feature(&cpu->env, ARM_FEATURE_V5); 855 set_feature(&cpu->env, ARM_FEATURE_VFP); 856 set_feature(&cpu->env, ARM_FEATURE_DUMMY_C15_REGS); 857 set_feature(&cpu->env, ARM_FEATURE_CACHE_TEST_CLEAN); 858 cpu->midr = 0x41069265; 859 cpu->reset_fpsid = 0x41011090; 860 cpu->ctr = 0x1dd20d2; 861 cpu->reset_sctlr = 0x00090078; 862 } 863 864 static void arm946_initfn(Object *obj) 865 { 866 ARMCPU *cpu = ARM_CPU(obj); 867 868 cpu->dtb_compatible = "arm,arm946"; 869 set_feature(&cpu->env, ARM_FEATURE_V5); 870 set_feature(&cpu->env, ARM_FEATURE_MPU); 871 set_feature(&cpu->env, ARM_FEATURE_DUMMY_C15_REGS); 872 cpu->midr = 0x41059461; 873 cpu->ctr = 0x0f004006; 874 cpu->reset_sctlr = 0x00000078; 875 } 876 877 static void arm1026_initfn(Object *obj) 878 { 879 ARMCPU *cpu = ARM_CPU(obj); 880 881 cpu->dtb_compatible = "arm,arm1026"; 882 set_feature(&cpu->env, ARM_FEATURE_V5); 883 set_feature(&cpu->env, ARM_FEATURE_VFP); 884 set_feature(&cpu->env, ARM_FEATURE_AUXCR); 885 set_feature(&cpu->env, ARM_FEATURE_DUMMY_C15_REGS); 886 set_feature(&cpu->env, ARM_FEATURE_CACHE_TEST_CLEAN); 887 cpu->midr = 0x4106a262; 888 cpu->reset_fpsid = 0x410110a0; 889 cpu->ctr = 0x1dd20d2; 890 cpu->reset_sctlr = 0x00090078; 891 cpu->reset_auxcr = 1; 892 { 893 /* The 1026 had an IFAR at c6,c0,0,1 rather than the ARMv6 c6,c0,0,2 */ 894 ARMCPRegInfo ifar = { 895 .name = "IFAR", .cp = 15, .crn = 6, .crm = 0, .opc1 = 0, .opc2 = 1, 896 .access = PL1_RW, 897 .fieldoffset = offsetof(CPUARMState, cp15.ifar_ns), 898 .resetvalue = 0 899 }; 900 define_one_arm_cp_reg(cpu, &ifar); 901 } 902 } 903 904 static void arm1136_r2_initfn(Object *obj) 905 { 906 ARMCPU *cpu = ARM_CPU(obj); 907 /* What qemu calls "arm1136_r2" is actually the 1136 r0p2, ie an 908 * older core than plain "arm1136". In particular this does not 909 * have the v6K features. 910 * These ID register values are correct for 1136 but may be wrong 911 * for 1136_r2 (in particular r0p2 does not actually implement most 912 * of the ID registers). 913 */ 914 915 cpu->dtb_compatible = "arm,arm1136"; 916 set_feature(&cpu->env, ARM_FEATURE_V6); 917 set_feature(&cpu->env, ARM_FEATURE_VFP); 918 set_feature(&cpu->env, ARM_FEATURE_DUMMY_C15_REGS); 919 set_feature(&cpu->env, ARM_FEATURE_CACHE_DIRTY_REG); 920 set_feature(&cpu->env, ARM_FEATURE_CACHE_BLOCK_OPS); 921 cpu->midr = 0x4107b362; 922 cpu->reset_fpsid = 0x410120b4; 923 cpu->mvfr0 = 0x11111111; 924 cpu->mvfr1 = 0x00000000; 925 cpu->ctr = 0x1dd20d2; 926 cpu->reset_sctlr = 0x00050078; 927 cpu->id_pfr0 = 0x111; 928 cpu->id_pfr1 = 0x1; 929 cpu->id_dfr0 = 0x2; 930 cpu->id_afr0 = 0x3; 931 cpu->id_mmfr0 = 0x01130003; 932 cpu->id_mmfr1 = 0x10030302; 933 cpu->id_mmfr2 = 0x01222110; 934 cpu->id_isar0 = 0x00140011; 935 cpu->id_isar1 = 0x12002111; 936 cpu->id_isar2 = 0x11231111; 937 cpu->id_isar3 = 0x01102131; 938 cpu->id_isar4 = 0x141; 939 cpu->reset_auxcr = 7; 940 } 941 942 static void arm1136_initfn(Object *obj) 943 { 944 ARMCPU *cpu = ARM_CPU(obj); 945 946 cpu->dtb_compatible = "arm,arm1136"; 947 set_feature(&cpu->env, ARM_FEATURE_V6K); 948 set_feature(&cpu->env, ARM_FEATURE_V6); 949 set_feature(&cpu->env, ARM_FEATURE_VFP); 950 set_feature(&cpu->env, ARM_FEATURE_DUMMY_C15_REGS); 951 set_feature(&cpu->env, ARM_FEATURE_CACHE_DIRTY_REG); 952 set_feature(&cpu->env, ARM_FEATURE_CACHE_BLOCK_OPS); 953 cpu->midr = 0x4117b363; 954 cpu->reset_fpsid = 0x410120b4; 955 cpu->mvfr0 = 0x11111111; 956 cpu->mvfr1 = 0x00000000; 957 cpu->ctr = 0x1dd20d2; 958 cpu->reset_sctlr = 0x00050078; 959 cpu->id_pfr0 = 0x111; 960 cpu->id_pfr1 = 0x1; 961 cpu->id_dfr0 = 0x2; 962 cpu->id_afr0 = 0x3; 963 cpu->id_mmfr0 = 0x01130003; 964 cpu->id_mmfr1 = 0x10030302; 965 cpu->id_mmfr2 = 0x01222110; 966 cpu->id_isar0 = 0x00140011; 967 cpu->id_isar1 = 0x12002111; 968 cpu->id_isar2 = 0x11231111; 969 cpu->id_isar3 = 0x01102131; 970 cpu->id_isar4 = 0x141; 971 cpu->reset_auxcr = 7; 972 } 973 974 static void arm1176_initfn(Object *obj) 975 { 976 ARMCPU *cpu = ARM_CPU(obj); 977 978 cpu->dtb_compatible = "arm,arm1176"; 979 set_feature(&cpu->env, ARM_FEATURE_V6K); 980 set_feature(&cpu->env, ARM_FEATURE_VFP); 981 set_feature(&cpu->env, ARM_FEATURE_VAPA); 982 set_feature(&cpu->env, ARM_FEATURE_DUMMY_C15_REGS); 983 set_feature(&cpu->env, ARM_FEATURE_CACHE_DIRTY_REG); 984 set_feature(&cpu->env, ARM_FEATURE_CACHE_BLOCK_OPS); 985 set_feature(&cpu->env, ARM_FEATURE_EL3); 986 cpu->midr = 0x410fb767; 987 cpu->reset_fpsid = 0x410120b5; 988 cpu->mvfr0 = 0x11111111; 989 cpu->mvfr1 = 0x00000000; 990 cpu->ctr = 0x1dd20d2; 991 cpu->reset_sctlr = 0x00050078; 992 cpu->id_pfr0 = 0x111; 993 cpu->id_pfr1 = 0x11; 994 cpu->id_dfr0 = 0x33; 995 cpu->id_afr0 = 0; 996 cpu->id_mmfr0 = 0x01130003; 997 cpu->id_mmfr1 = 0x10030302; 998 cpu->id_mmfr2 = 0x01222100; 999 cpu->id_isar0 = 0x0140011; 1000 cpu->id_isar1 = 0x12002111; 1001 cpu->id_isar2 = 0x11231121; 1002 cpu->id_isar3 = 0x01102131; 1003 cpu->id_isar4 = 0x01141; 1004 cpu->reset_auxcr = 7; 1005 } 1006 1007 static void arm11mpcore_initfn(Object *obj) 1008 { 1009 ARMCPU *cpu = ARM_CPU(obj); 1010 1011 cpu->dtb_compatible = "arm,arm11mpcore"; 1012 set_feature(&cpu->env, ARM_FEATURE_V6K); 1013 set_feature(&cpu->env, ARM_FEATURE_VFP); 1014 set_feature(&cpu->env, ARM_FEATURE_VAPA); 1015 set_feature(&cpu->env, ARM_FEATURE_MPIDR); 1016 set_feature(&cpu->env, ARM_FEATURE_DUMMY_C15_REGS); 1017 cpu->midr = 0x410fb022; 1018 cpu->reset_fpsid = 0x410120b4; 1019 cpu->mvfr0 = 0x11111111; 1020 cpu->mvfr1 = 0x00000000; 1021 cpu->ctr = 0x1d192992; /* 32K icache 32K dcache */ 1022 cpu->id_pfr0 = 0x111; 1023 cpu->id_pfr1 = 0x1; 1024 cpu->id_dfr0 = 0; 1025 cpu->id_afr0 = 0x2; 1026 cpu->id_mmfr0 = 0x01100103; 1027 cpu->id_mmfr1 = 0x10020302; 1028 cpu->id_mmfr2 = 0x01222000; 1029 cpu->id_isar0 = 0x00100011; 1030 cpu->id_isar1 = 0x12002111; 1031 cpu->id_isar2 = 0x11221011; 1032 cpu->id_isar3 = 0x01102131; 1033 cpu->id_isar4 = 0x141; 1034 cpu->reset_auxcr = 1; 1035 } 1036 1037 static void cortex_m3_initfn(Object *obj) 1038 { 1039 ARMCPU *cpu = ARM_CPU(obj); 1040 set_feature(&cpu->env, ARM_FEATURE_V7); 1041 set_feature(&cpu->env, ARM_FEATURE_M); 1042 cpu->midr = 0x410fc231; 1043 } 1044 1045 static void cortex_m4_initfn(Object *obj) 1046 { 1047 ARMCPU *cpu = ARM_CPU(obj); 1048 1049 set_feature(&cpu->env, ARM_FEATURE_V7); 1050 set_feature(&cpu->env, ARM_FEATURE_M); 1051 set_feature(&cpu->env, ARM_FEATURE_THUMB_DSP); 1052 cpu->midr = 0x410fc240; /* r0p0 */ 1053 } 1054 static void arm_v7m_class_init(ObjectClass *oc, void *data) 1055 { 1056 CPUClass *cc = CPU_CLASS(oc); 1057 1058 #ifndef CONFIG_USER_ONLY 1059 cc->do_interrupt = arm_v7m_cpu_do_interrupt; 1060 #endif 1061 1062 cc->cpu_exec_interrupt = arm_v7m_cpu_exec_interrupt; 1063 } 1064 1065 static const ARMCPRegInfo cortexr5_cp_reginfo[] = { 1066 /* Dummy the TCM region regs for the moment */ 1067 { .name = "ATCM", .cp = 15, .opc1 = 0, .crn = 9, .crm = 1, .opc2 = 0, 1068 .access = PL1_RW, .type = ARM_CP_CONST }, 1069 { .name = "BTCM", .cp = 15, .opc1 = 0, .crn = 9, .crm = 1, .opc2 = 1, 1070 .access = PL1_RW, .type = ARM_CP_CONST }, 1071 REGINFO_SENTINEL 1072 }; 1073 1074 static void cortex_r5_initfn(Object *obj) 1075 { 1076 ARMCPU *cpu = ARM_CPU(obj); 1077 1078 set_feature(&cpu->env, ARM_FEATURE_V7); 1079 set_feature(&cpu->env, ARM_FEATURE_THUMB_DIV); 1080 set_feature(&cpu->env, ARM_FEATURE_ARM_DIV); 1081 set_feature(&cpu->env, ARM_FEATURE_V7MP); 1082 set_feature(&cpu->env, ARM_FEATURE_MPU); 1083 cpu->midr = 0x411fc153; /* r1p3 */ 1084 cpu->id_pfr0 = 0x0131; 1085 cpu->id_pfr1 = 0x001; 1086 cpu->id_dfr0 = 0x010400; 1087 cpu->id_afr0 = 0x0; 1088 cpu->id_mmfr0 = 0x0210030; 1089 cpu->id_mmfr1 = 0x00000000; 1090 cpu->id_mmfr2 = 0x01200000; 1091 cpu->id_mmfr3 = 0x0211; 1092 cpu->id_isar0 = 0x2101111; 1093 cpu->id_isar1 = 0x13112111; 1094 cpu->id_isar2 = 0x21232141; 1095 cpu->id_isar3 = 0x01112131; 1096 cpu->id_isar4 = 0x0010142; 1097 cpu->id_isar5 = 0x0; 1098 cpu->mp_is_up = true; 1099 define_arm_cp_regs(cpu, cortexr5_cp_reginfo); 1100 } 1101 1102 static const ARMCPRegInfo cortexa8_cp_reginfo[] = { 1103 { .name = "L2LOCKDOWN", .cp = 15, .crn = 9, .crm = 0, .opc1 = 1, .opc2 = 0, 1104 .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0 }, 1105 { .name = "L2AUXCR", .cp = 15, .crn = 9, .crm = 0, .opc1 = 1, .opc2 = 2, 1106 .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0 }, 1107 REGINFO_SENTINEL 1108 }; 1109 1110 static void cortex_a8_initfn(Object *obj) 1111 { 1112 ARMCPU *cpu = ARM_CPU(obj); 1113 1114 cpu->dtb_compatible = "arm,cortex-a8"; 1115 set_feature(&cpu->env, ARM_FEATURE_V7); 1116 set_feature(&cpu->env, ARM_FEATURE_VFP3); 1117 set_feature(&cpu->env, ARM_FEATURE_NEON); 1118 set_feature(&cpu->env, ARM_FEATURE_THUMB2EE); 1119 set_feature(&cpu->env, ARM_FEATURE_DUMMY_C15_REGS); 1120 set_feature(&cpu->env, ARM_FEATURE_EL3); 1121 cpu->midr = 0x410fc080; 1122 cpu->reset_fpsid = 0x410330c0; 1123 cpu->mvfr0 = 0x11110222; 1124 cpu->mvfr1 = 0x00011111; 1125 cpu->ctr = 0x82048004; 1126 cpu->reset_sctlr = 0x00c50078; 1127 cpu->id_pfr0 = 0x1031; 1128 cpu->id_pfr1 = 0x11; 1129 cpu->id_dfr0 = 0x400; 1130 cpu->id_afr0 = 0; 1131 cpu->id_mmfr0 = 0x31100003; 1132 cpu->id_mmfr1 = 0x20000000; 1133 cpu->id_mmfr2 = 0x01202000; 1134 cpu->id_mmfr3 = 0x11; 1135 cpu->id_isar0 = 0x00101111; 1136 cpu->id_isar1 = 0x12112111; 1137 cpu->id_isar2 = 0x21232031; 1138 cpu->id_isar3 = 0x11112131; 1139 cpu->id_isar4 = 0x00111142; 1140 cpu->dbgdidr = 0x15141000; 1141 cpu->clidr = (1 << 27) | (2 << 24) | 3; 1142 cpu->ccsidr[0] = 0xe007e01a; /* 16k L1 dcache. */ 1143 cpu->ccsidr[1] = 0x2007e01a; /* 16k L1 icache. */ 1144 cpu->ccsidr[2] = 0xf0000000; /* No L2 icache. */ 1145 cpu->reset_auxcr = 2; 1146 define_arm_cp_regs(cpu, cortexa8_cp_reginfo); 1147 } 1148 1149 static const ARMCPRegInfo cortexa9_cp_reginfo[] = { 1150 /* power_control should be set to maximum latency. Again, 1151 * default to 0 and set by private hook 1152 */ 1153 { .name = "A9_PWRCTL", .cp = 15, .crn = 15, .crm = 0, .opc1 = 0, .opc2 = 0, 1154 .access = PL1_RW, .resetvalue = 0, 1155 .fieldoffset = offsetof(CPUARMState, cp15.c15_power_control) }, 1156 { .name = "A9_DIAG", .cp = 15, .crn = 15, .crm = 0, .opc1 = 0, .opc2 = 1, 1157 .access = PL1_RW, .resetvalue = 0, 1158 .fieldoffset = offsetof(CPUARMState, cp15.c15_diagnostic) }, 1159 { .name = "A9_PWRDIAG", .cp = 15, .crn = 15, .crm = 0, .opc1 = 0, .opc2 = 2, 1160 .access = PL1_RW, .resetvalue = 0, 1161 .fieldoffset = offsetof(CPUARMState, cp15.c15_power_diagnostic) }, 1162 { .name = "NEONBUSY", .cp = 15, .crn = 15, .crm = 1, .opc1 = 0, .opc2 = 0, 1163 .access = PL1_RW, .resetvalue = 0, .type = ARM_CP_CONST }, 1164 /* TLB lockdown control */ 1165 { .name = "TLB_LOCKR", .cp = 15, .crn = 15, .crm = 4, .opc1 = 5, .opc2 = 2, 1166 .access = PL1_W, .resetvalue = 0, .type = ARM_CP_NOP }, 1167 { .name = "TLB_LOCKW", .cp = 15, .crn = 15, .crm = 4, .opc1 = 5, .opc2 = 4, 1168 .access = PL1_W, .resetvalue = 0, .type = ARM_CP_NOP }, 1169 { .name = "TLB_VA", .cp = 15, .crn = 15, .crm = 5, .opc1 = 5, .opc2 = 2, 1170 .access = PL1_RW, .resetvalue = 0, .type = ARM_CP_CONST }, 1171 { .name = "TLB_PA", .cp = 15, .crn = 15, .crm = 6, .opc1 = 5, .opc2 = 2, 1172 .access = PL1_RW, .resetvalue = 0, .type = ARM_CP_CONST }, 1173 { .name = "TLB_ATTR", .cp = 15, .crn = 15, .crm = 7, .opc1 = 5, .opc2 = 2, 1174 .access = PL1_RW, .resetvalue = 0, .type = ARM_CP_CONST }, 1175 REGINFO_SENTINEL 1176 }; 1177 1178 static void cortex_a9_initfn(Object *obj) 1179 { 1180 ARMCPU *cpu = ARM_CPU(obj); 1181 1182 cpu->dtb_compatible = "arm,cortex-a9"; 1183 set_feature(&cpu->env, ARM_FEATURE_V7); 1184 set_feature(&cpu->env, ARM_FEATURE_VFP3); 1185 set_feature(&cpu->env, ARM_FEATURE_VFP_FP16); 1186 set_feature(&cpu->env, ARM_FEATURE_NEON); 1187 set_feature(&cpu->env, ARM_FEATURE_THUMB2EE); 1188 set_feature(&cpu->env, ARM_FEATURE_EL3); 1189 /* Note that A9 supports the MP extensions even for 1190 * A9UP and single-core A9MP (which are both different 1191 * and valid configurations; we don't model A9UP). 1192 */ 1193 set_feature(&cpu->env, ARM_FEATURE_V7MP); 1194 set_feature(&cpu->env, ARM_FEATURE_CBAR); 1195 cpu->midr = 0x410fc090; 1196 cpu->reset_fpsid = 0x41033090; 1197 cpu->mvfr0 = 0x11110222; 1198 cpu->mvfr1 = 0x01111111; 1199 cpu->ctr = 0x80038003; 1200 cpu->reset_sctlr = 0x00c50078; 1201 cpu->id_pfr0 = 0x1031; 1202 cpu->id_pfr1 = 0x11; 1203 cpu->id_dfr0 = 0x000; 1204 cpu->id_afr0 = 0; 1205 cpu->id_mmfr0 = 0x00100103; 1206 cpu->id_mmfr1 = 0x20000000; 1207 cpu->id_mmfr2 = 0x01230000; 1208 cpu->id_mmfr3 = 0x00002111; 1209 cpu->id_isar0 = 0x00101111; 1210 cpu->id_isar1 = 0x13112111; 1211 cpu->id_isar2 = 0x21232041; 1212 cpu->id_isar3 = 0x11112131; 1213 cpu->id_isar4 = 0x00111142; 1214 cpu->dbgdidr = 0x35141000; 1215 cpu->clidr = (1 << 27) | (1 << 24) | 3; 1216 cpu->ccsidr[0] = 0xe00fe019; /* 16k L1 dcache. */ 1217 cpu->ccsidr[1] = 0x200fe019; /* 16k L1 icache. */ 1218 define_arm_cp_regs(cpu, cortexa9_cp_reginfo); 1219 } 1220 1221 #ifndef CONFIG_USER_ONLY 1222 static uint64_t a15_l2ctlr_read(CPUARMState *env, const ARMCPRegInfo *ri) 1223 { 1224 /* Linux wants the number of processors from here. 1225 * Might as well set the interrupt-controller bit too. 1226 */ 1227 return ((smp_cpus - 1) << 24) | (1 << 23); 1228 } 1229 #endif 1230 1231 static const ARMCPRegInfo cortexa15_cp_reginfo[] = { 1232 #ifndef CONFIG_USER_ONLY 1233 { .name = "L2CTLR", .cp = 15, .crn = 9, .crm = 0, .opc1 = 1, .opc2 = 2, 1234 .access = PL1_RW, .resetvalue = 0, .readfn = a15_l2ctlr_read, 1235 .writefn = arm_cp_write_ignore, }, 1236 #endif 1237 { .name = "L2ECTLR", .cp = 15, .crn = 9, .crm = 0, .opc1 = 1, .opc2 = 3, 1238 .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0 }, 1239 REGINFO_SENTINEL 1240 }; 1241 1242 static void cortex_a7_initfn(Object *obj) 1243 { 1244 ARMCPU *cpu = ARM_CPU(obj); 1245 1246 cpu->dtb_compatible = "arm,cortex-a7"; 1247 set_feature(&cpu->env, ARM_FEATURE_V7); 1248 set_feature(&cpu->env, ARM_FEATURE_VFP4); 1249 set_feature(&cpu->env, ARM_FEATURE_NEON); 1250 set_feature(&cpu->env, ARM_FEATURE_THUMB2EE); 1251 set_feature(&cpu->env, ARM_FEATURE_ARM_DIV); 1252 set_feature(&cpu->env, ARM_FEATURE_GENERIC_TIMER); 1253 set_feature(&cpu->env, ARM_FEATURE_DUMMY_C15_REGS); 1254 set_feature(&cpu->env, ARM_FEATURE_CBAR_RO); 1255 set_feature(&cpu->env, ARM_FEATURE_LPAE); 1256 set_feature(&cpu->env, ARM_FEATURE_EL3); 1257 cpu->kvm_target = QEMU_KVM_ARM_TARGET_CORTEX_A7; 1258 cpu->midr = 0x410fc075; 1259 cpu->reset_fpsid = 0x41023075; 1260 cpu->mvfr0 = 0x10110222; 1261 cpu->mvfr1 = 0x11111111; 1262 cpu->ctr = 0x84448003; 1263 cpu->reset_sctlr = 0x00c50078; 1264 cpu->id_pfr0 = 0x00001131; 1265 cpu->id_pfr1 = 0x00011011; 1266 cpu->id_dfr0 = 0x02010555; 1267 cpu->pmceid0 = 0x00000000; 1268 cpu->pmceid1 = 0x00000000; 1269 cpu->id_afr0 = 0x00000000; 1270 cpu->id_mmfr0 = 0x10101105; 1271 cpu->id_mmfr1 = 0x40000000; 1272 cpu->id_mmfr2 = 0x01240000; 1273 cpu->id_mmfr3 = 0x02102211; 1274 cpu->id_isar0 = 0x01101110; 1275 cpu->id_isar1 = 0x13112111; 1276 cpu->id_isar2 = 0x21232041; 1277 cpu->id_isar3 = 0x11112131; 1278 cpu->id_isar4 = 0x10011142; 1279 cpu->dbgdidr = 0x3515f005; 1280 cpu->clidr = 0x0a200023; 1281 cpu->ccsidr[0] = 0x701fe00a; /* 32K L1 dcache */ 1282 cpu->ccsidr[1] = 0x201fe00a; /* 32K L1 icache */ 1283 cpu->ccsidr[2] = 0x711fe07a; /* 4096K L2 unified cache */ 1284 define_arm_cp_regs(cpu, cortexa15_cp_reginfo); /* Same as A15 */ 1285 } 1286 1287 static void cortex_a15_initfn(Object *obj) 1288 { 1289 ARMCPU *cpu = ARM_CPU(obj); 1290 1291 cpu->dtb_compatible = "arm,cortex-a15"; 1292 set_feature(&cpu->env, ARM_FEATURE_V7); 1293 set_feature(&cpu->env, ARM_FEATURE_VFP4); 1294 set_feature(&cpu->env, ARM_FEATURE_NEON); 1295 set_feature(&cpu->env, ARM_FEATURE_THUMB2EE); 1296 set_feature(&cpu->env, ARM_FEATURE_ARM_DIV); 1297 set_feature(&cpu->env, ARM_FEATURE_GENERIC_TIMER); 1298 set_feature(&cpu->env, ARM_FEATURE_DUMMY_C15_REGS); 1299 set_feature(&cpu->env, ARM_FEATURE_CBAR_RO); 1300 set_feature(&cpu->env, ARM_FEATURE_LPAE); 1301 set_feature(&cpu->env, ARM_FEATURE_EL3); 1302 cpu->kvm_target = QEMU_KVM_ARM_TARGET_CORTEX_A15; 1303 cpu->midr = 0x412fc0f1; 1304 cpu->reset_fpsid = 0x410430f0; 1305 cpu->mvfr0 = 0x10110222; 1306 cpu->mvfr1 = 0x11111111; 1307 cpu->ctr = 0x8444c004; 1308 cpu->reset_sctlr = 0x00c50078; 1309 cpu->id_pfr0 = 0x00001131; 1310 cpu->id_pfr1 = 0x00011011; 1311 cpu->id_dfr0 = 0x02010555; 1312 cpu->pmceid0 = 0x0000000; 1313 cpu->pmceid1 = 0x00000000; 1314 cpu->id_afr0 = 0x00000000; 1315 cpu->id_mmfr0 = 0x10201105; 1316 cpu->id_mmfr1 = 0x20000000; 1317 cpu->id_mmfr2 = 0x01240000; 1318 cpu->id_mmfr3 = 0x02102211; 1319 cpu->id_isar0 = 0x02101110; 1320 cpu->id_isar1 = 0x13112111; 1321 cpu->id_isar2 = 0x21232041; 1322 cpu->id_isar3 = 0x11112131; 1323 cpu->id_isar4 = 0x10011142; 1324 cpu->dbgdidr = 0x3515f021; 1325 cpu->clidr = 0x0a200023; 1326 cpu->ccsidr[0] = 0x701fe00a; /* 32K L1 dcache */ 1327 cpu->ccsidr[1] = 0x201fe00a; /* 32K L1 icache */ 1328 cpu->ccsidr[2] = 0x711fe07a; /* 4096K L2 unified cache */ 1329 define_arm_cp_regs(cpu, cortexa15_cp_reginfo); 1330 } 1331 1332 static void ti925t_initfn(Object *obj) 1333 { 1334 ARMCPU *cpu = ARM_CPU(obj); 1335 set_feature(&cpu->env, ARM_FEATURE_V4T); 1336 set_feature(&cpu->env, ARM_FEATURE_OMAPCP); 1337 cpu->midr = ARM_CPUID_TI925T; 1338 cpu->ctr = 0x5109149; 1339 cpu->reset_sctlr = 0x00000070; 1340 } 1341 1342 static void sa1100_initfn(Object *obj) 1343 { 1344 ARMCPU *cpu = ARM_CPU(obj); 1345 1346 cpu->dtb_compatible = "intel,sa1100"; 1347 set_feature(&cpu->env, ARM_FEATURE_STRONGARM); 1348 set_feature(&cpu->env, ARM_FEATURE_DUMMY_C15_REGS); 1349 cpu->midr = 0x4401A11B; 1350 cpu->reset_sctlr = 0x00000070; 1351 } 1352 1353 static void sa1110_initfn(Object *obj) 1354 { 1355 ARMCPU *cpu = ARM_CPU(obj); 1356 set_feature(&cpu->env, ARM_FEATURE_STRONGARM); 1357 set_feature(&cpu->env, ARM_FEATURE_DUMMY_C15_REGS); 1358 cpu->midr = 0x6901B119; 1359 cpu->reset_sctlr = 0x00000070; 1360 } 1361 1362 static void pxa250_initfn(Object *obj) 1363 { 1364 ARMCPU *cpu = ARM_CPU(obj); 1365 1366 cpu->dtb_compatible = "marvell,xscale"; 1367 set_feature(&cpu->env, ARM_FEATURE_V5); 1368 set_feature(&cpu->env, ARM_FEATURE_XSCALE); 1369 cpu->midr = 0x69052100; 1370 cpu->ctr = 0xd172172; 1371 cpu->reset_sctlr = 0x00000078; 1372 } 1373 1374 static void pxa255_initfn(Object *obj) 1375 { 1376 ARMCPU *cpu = ARM_CPU(obj); 1377 1378 cpu->dtb_compatible = "marvell,xscale"; 1379 set_feature(&cpu->env, ARM_FEATURE_V5); 1380 set_feature(&cpu->env, ARM_FEATURE_XSCALE); 1381 cpu->midr = 0x69052d00; 1382 cpu->ctr = 0xd172172; 1383 cpu->reset_sctlr = 0x00000078; 1384 } 1385 1386 static void pxa260_initfn(Object *obj) 1387 { 1388 ARMCPU *cpu = ARM_CPU(obj); 1389 1390 cpu->dtb_compatible = "marvell,xscale"; 1391 set_feature(&cpu->env, ARM_FEATURE_V5); 1392 set_feature(&cpu->env, ARM_FEATURE_XSCALE); 1393 cpu->midr = 0x69052903; 1394 cpu->ctr = 0xd172172; 1395 cpu->reset_sctlr = 0x00000078; 1396 } 1397 1398 static void pxa261_initfn(Object *obj) 1399 { 1400 ARMCPU *cpu = ARM_CPU(obj); 1401 1402 cpu->dtb_compatible = "marvell,xscale"; 1403 set_feature(&cpu->env, ARM_FEATURE_V5); 1404 set_feature(&cpu->env, ARM_FEATURE_XSCALE); 1405 cpu->midr = 0x69052d05; 1406 cpu->ctr = 0xd172172; 1407 cpu->reset_sctlr = 0x00000078; 1408 } 1409 1410 static void pxa262_initfn(Object *obj) 1411 { 1412 ARMCPU *cpu = ARM_CPU(obj); 1413 1414 cpu->dtb_compatible = "marvell,xscale"; 1415 set_feature(&cpu->env, ARM_FEATURE_V5); 1416 set_feature(&cpu->env, ARM_FEATURE_XSCALE); 1417 cpu->midr = 0x69052d06; 1418 cpu->ctr = 0xd172172; 1419 cpu->reset_sctlr = 0x00000078; 1420 } 1421 1422 static void pxa270a0_initfn(Object *obj) 1423 { 1424 ARMCPU *cpu = ARM_CPU(obj); 1425 1426 cpu->dtb_compatible = "marvell,xscale"; 1427 set_feature(&cpu->env, ARM_FEATURE_V5); 1428 set_feature(&cpu->env, ARM_FEATURE_XSCALE); 1429 set_feature(&cpu->env, ARM_FEATURE_IWMMXT); 1430 cpu->midr = 0x69054110; 1431 cpu->ctr = 0xd172172; 1432 cpu->reset_sctlr = 0x00000078; 1433 } 1434 1435 static void pxa270a1_initfn(Object *obj) 1436 { 1437 ARMCPU *cpu = ARM_CPU(obj); 1438 1439 cpu->dtb_compatible = "marvell,xscale"; 1440 set_feature(&cpu->env, ARM_FEATURE_V5); 1441 set_feature(&cpu->env, ARM_FEATURE_XSCALE); 1442 set_feature(&cpu->env, ARM_FEATURE_IWMMXT); 1443 cpu->midr = 0x69054111; 1444 cpu->ctr = 0xd172172; 1445 cpu->reset_sctlr = 0x00000078; 1446 } 1447 1448 static void pxa270b0_initfn(Object *obj) 1449 { 1450 ARMCPU *cpu = ARM_CPU(obj); 1451 1452 cpu->dtb_compatible = "marvell,xscale"; 1453 set_feature(&cpu->env, ARM_FEATURE_V5); 1454 set_feature(&cpu->env, ARM_FEATURE_XSCALE); 1455 set_feature(&cpu->env, ARM_FEATURE_IWMMXT); 1456 cpu->midr = 0x69054112; 1457 cpu->ctr = 0xd172172; 1458 cpu->reset_sctlr = 0x00000078; 1459 } 1460 1461 static void pxa270b1_initfn(Object *obj) 1462 { 1463 ARMCPU *cpu = ARM_CPU(obj); 1464 1465 cpu->dtb_compatible = "marvell,xscale"; 1466 set_feature(&cpu->env, ARM_FEATURE_V5); 1467 set_feature(&cpu->env, ARM_FEATURE_XSCALE); 1468 set_feature(&cpu->env, ARM_FEATURE_IWMMXT); 1469 cpu->midr = 0x69054113; 1470 cpu->ctr = 0xd172172; 1471 cpu->reset_sctlr = 0x00000078; 1472 } 1473 1474 static void pxa270c0_initfn(Object *obj) 1475 { 1476 ARMCPU *cpu = ARM_CPU(obj); 1477 1478 cpu->dtb_compatible = "marvell,xscale"; 1479 set_feature(&cpu->env, ARM_FEATURE_V5); 1480 set_feature(&cpu->env, ARM_FEATURE_XSCALE); 1481 set_feature(&cpu->env, ARM_FEATURE_IWMMXT); 1482 cpu->midr = 0x69054114; 1483 cpu->ctr = 0xd172172; 1484 cpu->reset_sctlr = 0x00000078; 1485 } 1486 1487 static void pxa270c5_initfn(Object *obj) 1488 { 1489 ARMCPU *cpu = ARM_CPU(obj); 1490 1491 cpu->dtb_compatible = "marvell,xscale"; 1492 set_feature(&cpu->env, ARM_FEATURE_V5); 1493 set_feature(&cpu->env, ARM_FEATURE_XSCALE); 1494 set_feature(&cpu->env, ARM_FEATURE_IWMMXT); 1495 cpu->midr = 0x69054117; 1496 cpu->ctr = 0xd172172; 1497 cpu->reset_sctlr = 0x00000078; 1498 } 1499 1500 #ifdef CONFIG_USER_ONLY 1501 static void arm_any_initfn(Object *obj) 1502 { 1503 ARMCPU *cpu = ARM_CPU(obj); 1504 set_feature(&cpu->env, ARM_FEATURE_V8); 1505 set_feature(&cpu->env, ARM_FEATURE_VFP4); 1506 set_feature(&cpu->env, ARM_FEATURE_NEON); 1507 set_feature(&cpu->env, ARM_FEATURE_THUMB2EE); 1508 set_feature(&cpu->env, ARM_FEATURE_V8_AES); 1509 set_feature(&cpu->env, ARM_FEATURE_V8_SHA1); 1510 set_feature(&cpu->env, ARM_FEATURE_V8_SHA256); 1511 set_feature(&cpu->env, ARM_FEATURE_V8_PMULL); 1512 set_feature(&cpu->env, ARM_FEATURE_CRC); 1513 cpu->midr = 0xffffffff; 1514 } 1515 #endif 1516 1517 #endif /* !defined(CONFIG_USER_ONLY) || !defined(TARGET_AARCH64) */ 1518 1519 typedef struct ARMCPUInfo { 1520 const char *name; 1521 void (*initfn)(Object *obj); 1522 void (*class_init)(ObjectClass *oc, void *data); 1523 } ARMCPUInfo; 1524 1525 static const ARMCPUInfo arm_cpus[] = { 1526 #if !defined(CONFIG_USER_ONLY) || !defined(TARGET_AARCH64) 1527 { .name = "arm926", .initfn = arm926_initfn }, 1528 { .name = "arm946", .initfn = arm946_initfn }, 1529 { .name = "arm1026", .initfn = arm1026_initfn }, 1530 /* What QEMU calls "arm1136-r2" is actually the 1136 r0p2, i.e. an 1531 * older core than plain "arm1136". In particular this does not 1532 * have the v6K features. 1533 */ 1534 { .name = "arm1136-r2", .initfn = arm1136_r2_initfn }, 1535 { .name = "arm1136", .initfn = arm1136_initfn }, 1536 { .name = "arm1176", .initfn = arm1176_initfn }, 1537 { .name = "arm11mpcore", .initfn = arm11mpcore_initfn }, 1538 { .name = "cortex-m3", .initfn = cortex_m3_initfn, 1539 .class_init = arm_v7m_class_init }, 1540 { .name = "cortex-m4", .initfn = cortex_m4_initfn, 1541 .class_init = arm_v7m_class_init }, 1542 { .name = "cortex-r5", .initfn = cortex_r5_initfn }, 1543 { .name = "cortex-a7", .initfn = cortex_a7_initfn }, 1544 { .name = "cortex-a8", .initfn = cortex_a8_initfn }, 1545 { .name = "cortex-a9", .initfn = cortex_a9_initfn }, 1546 { .name = "cortex-a15", .initfn = cortex_a15_initfn }, 1547 { .name = "ti925t", .initfn = ti925t_initfn }, 1548 { .name = "sa1100", .initfn = sa1100_initfn }, 1549 { .name = "sa1110", .initfn = sa1110_initfn }, 1550 { .name = "pxa250", .initfn = pxa250_initfn }, 1551 { .name = "pxa255", .initfn = pxa255_initfn }, 1552 { .name = "pxa260", .initfn = pxa260_initfn }, 1553 { .name = "pxa261", .initfn = pxa261_initfn }, 1554 { .name = "pxa262", .initfn = pxa262_initfn }, 1555 /* "pxa270" is an alias for "pxa270-a0" */ 1556 { .name = "pxa270", .initfn = pxa270a0_initfn }, 1557 { .name = "pxa270-a0", .initfn = pxa270a0_initfn }, 1558 { .name = "pxa270-a1", .initfn = pxa270a1_initfn }, 1559 { .name = "pxa270-b0", .initfn = pxa270b0_initfn }, 1560 { .name = "pxa270-b1", .initfn = pxa270b1_initfn }, 1561 { .name = "pxa270-c0", .initfn = pxa270c0_initfn }, 1562 { .name = "pxa270-c5", .initfn = pxa270c5_initfn }, 1563 #ifdef CONFIG_USER_ONLY 1564 { .name = "any", .initfn = arm_any_initfn }, 1565 #endif 1566 #endif 1567 { .name = NULL } 1568 }; 1569 1570 static Property arm_cpu_properties[] = { 1571 DEFINE_PROP_BOOL("start-powered-off", ARMCPU, start_powered_off, false), 1572 DEFINE_PROP_UINT32("psci-conduit", ARMCPU, psci_conduit, 0), 1573 DEFINE_PROP_UINT32("midr", ARMCPU, midr, 0), 1574 DEFINE_PROP_UINT64("mp-affinity", ARMCPU, 1575 mp_affinity, ARM64_AFFINITY_INVALID), 1576 DEFINE_PROP_INT32("node-id", CPUState, numa_node, CPU_UNSET_NUMA_NODE_ID), 1577 DEFINE_PROP_END_OF_LIST() 1578 }; 1579 1580 #ifdef CONFIG_USER_ONLY 1581 static int arm_cpu_handle_mmu_fault(CPUState *cs, vaddr address, int rw, 1582 int mmu_idx) 1583 { 1584 ARMCPU *cpu = ARM_CPU(cs); 1585 CPUARMState *env = &cpu->env; 1586 1587 env->exception.vaddress = address; 1588 if (rw == 2) { 1589 cs->exception_index = EXCP_PREFETCH_ABORT; 1590 } else { 1591 cs->exception_index = EXCP_DATA_ABORT; 1592 } 1593 return 1; 1594 } 1595 #endif 1596 1597 static gchar *arm_gdb_arch_name(CPUState *cs) 1598 { 1599 ARMCPU *cpu = ARM_CPU(cs); 1600 CPUARMState *env = &cpu->env; 1601 1602 if (arm_feature(env, ARM_FEATURE_IWMMXT)) { 1603 return g_strdup("iwmmxt"); 1604 } 1605 return g_strdup("arm"); 1606 } 1607 1608 static void arm_cpu_class_init(ObjectClass *oc, void *data) 1609 { 1610 ARMCPUClass *acc = ARM_CPU_CLASS(oc); 1611 CPUClass *cc = CPU_CLASS(acc); 1612 DeviceClass *dc = DEVICE_CLASS(oc); 1613 1614 acc->parent_realize = dc->realize; 1615 dc->realize = arm_cpu_realizefn; 1616 dc->props = arm_cpu_properties; 1617 1618 acc->parent_reset = cc->reset; 1619 cc->reset = arm_cpu_reset; 1620 1621 cc->class_by_name = arm_cpu_class_by_name; 1622 cc->has_work = arm_cpu_has_work; 1623 cc->cpu_exec_interrupt = arm_cpu_exec_interrupt; 1624 cc->dump_state = arm_cpu_dump_state; 1625 cc->set_pc = arm_cpu_set_pc; 1626 cc->gdb_read_register = arm_cpu_gdb_read_register; 1627 cc->gdb_write_register = arm_cpu_gdb_write_register; 1628 #ifdef CONFIG_USER_ONLY 1629 cc->handle_mmu_fault = arm_cpu_handle_mmu_fault; 1630 #else 1631 cc->do_interrupt = arm_cpu_do_interrupt; 1632 cc->do_unaligned_access = arm_cpu_do_unaligned_access; 1633 cc->get_phys_page_attrs_debug = arm_cpu_get_phys_page_attrs_debug; 1634 cc->asidx_from_attrs = arm_asidx_from_attrs; 1635 cc->vmsd = &vmstate_arm_cpu; 1636 cc->virtio_is_big_endian = arm_cpu_virtio_is_big_endian; 1637 cc->write_elf64_note = arm_cpu_write_elf64_note; 1638 cc->write_elf32_note = arm_cpu_write_elf32_note; 1639 #endif 1640 cc->gdb_num_core_regs = 26; 1641 cc->gdb_core_xml_file = "arm-core.xml"; 1642 cc->gdb_arch_name = arm_gdb_arch_name; 1643 cc->gdb_stop_before_watchpoint = true; 1644 cc->debug_excp_handler = arm_debug_excp_handler; 1645 cc->debug_check_watchpoint = arm_debug_check_watchpoint; 1646 #if !defined(CONFIG_USER_ONLY) 1647 cc->adjust_watchpoint_address = arm_adjust_watchpoint_address; 1648 #endif 1649 1650 cc->disas_set_info = arm_disas_set_info; 1651 } 1652 1653 static void cpu_register(const ARMCPUInfo *info) 1654 { 1655 TypeInfo type_info = { 1656 .parent = TYPE_ARM_CPU, 1657 .instance_size = sizeof(ARMCPU), 1658 .instance_init = info->initfn, 1659 .class_size = sizeof(ARMCPUClass), 1660 .class_init = info->class_init, 1661 }; 1662 1663 type_info.name = g_strdup_printf("%s-" TYPE_ARM_CPU, info->name); 1664 type_register(&type_info); 1665 g_free((void *)type_info.name); 1666 } 1667 1668 static const TypeInfo arm_cpu_type_info = { 1669 .name = TYPE_ARM_CPU, 1670 .parent = TYPE_CPU, 1671 .instance_size = sizeof(ARMCPU), 1672 .instance_init = arm_cpu_initfn, 1673 .instance_post_init = arm_cpu_post_init, 1674 .instance_finalize = arm_cpu_finalizefn, 1675 .abstract = true, 1676 .class_size = sizeof(ARMCPUClass), 1677 .class_init = arm_cpu_class_init, 1678 }; 1679 1680 static void arm_cpu_register_types(void) 1681 { 1682 const ARMCPUInfo *info = arm_cpus; 1683 1684 type_register_static(&arm_cpu_type_info); 1685 1686 while (info->name) { 1687 cpu_register(info); 1688 info++; 1689 } 1690 } 1691 1692 type_init(arm_cpu_register_types) 1693